AS4C4M32D1A-5BCN [ALSC]
DLL aligns DQ and DQS transitions;
| 型号： | AS4C4M32D1A-5BCN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | DLL aligns DQ and DQS transitions |
| 文件： | 总64页 (文件大小：2373K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Revision History
128Mb AS4C4M32D1A - 144 ball FBGA PACKAGE
Revision Details
Date
Rev 1.0
Preliminary datasheet
May. 2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
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Overview
Features
Fast clock rate: 200 MHz
Differential Clock CK &
•
•
The 128Mb DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 128
Mbits. It is internally configured as a quad 1M x 32
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
input
CK
4 Bi-directional DQS. Data transactions on both
edges of DQS (1DQS / Byte)
•
Data outputs occur at both rising edges of CK and
.
CK
DLL aligns DQ and DQS transitions
Edge aligned data & DQS output
Center aligned data & DQS inpu
•
•
•
•
•
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command, which is then
followed by a Read or Write command. The device
provides programmable Read or Write burst lengths of
2, 4, 8. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the
end of the burst sequence. The refresh functions, either
Auto or Self Refresh are easy to use. In addition, 128Mb
DDR SDRAM features programmable DLL option. By
having a programmable mode register and extended
mode register, the system can choose the most suitable
modes to maximize its performance. These devices are
well suited for applications requiring high memory
bandwidth; result in a device particularly well suited to
high performance main memory and graphics
4 internal banks, 1M x 32-bit for each bank
Programmable mode and extended mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleave
All inputs except DQ’s & DM are at the positive
edge of the system clock
•
4 individual DM control for write masking only
Auto Refresh and Self Refresh
4096 refresh cycles / 64ms
•
•
•
•
Operating Temperature:
- Industrial -40 C~85 C
°
°
applications.
Commercial 0°C to 70°C
-
Power supplies: V
V
= 2.5V ± 0.2V
DD & DDQ
•
Interface: SSTL_2 I/O compatible
144-ball 12 x 12 x 1.4mm LFBGA package
-Pb and Halogen Free
•
•
Tableꢀ1.ꢀOrderingꢀInformationꢀ
PartꢀNumberꢀ
ꢀꢀAS4C4M32D1A-5BCNꢀ
AS4C4M32D1A-5BINꢀ
Orgꢀ
Temperatureꢀ
MaxClockꢀ(MHz)ꢀ
Packageꢀ
4Mx32ꢀ
4Mx32ꢀ
Commercialꢀꢀ0°Cꢀtoꢀ70°Cꢀ
Industrialꢀ-40°Cꢀtoꢀ85°Cꢀ
200ꢀ
200ꢀ
144-ballꢀFBGAꢀ
144-ballꢀFBGAꢀ
Tableꢀ2.ꢀSpeedꢀGradeꢀInformationꢀ
SpeedꢀGradeꢀ
ClockꢀFrequencyꢀ
CASꢀLatencyꢀ
tRCDꢀ(ns)ꢀ
tRPꢀ(ns)ꢀ
ꢀ
ꢀ
DDR1-400ꢀ
200MHzꢀ
3ꢀ
15ꢀ
15ꢀ
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Figure 1. Pin Assignment (LFBGA 144Ball Top View)
1
2
3
4
5
6
7
8
9
10
11
12
DQS0
DM0
VSSQ
DQ3
DQ2
DQ0
DQ31
DQ29
DQ28
VSSQ
DM3
DQS3
A
B
C
D
E
F
DQ4
DQ6
VDDQ
DQ5
NC
VDDQ
VSSQ
VSS
DQ1
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
A10
VDDQ VDDQ
DQ30
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
NC
VDDQ
VSSQ
VSS
NC
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
VSSQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
A11
A3
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
A9
VSSQ
VDD
DQ7
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
RAS
CS
VDDQ VSSQ
VDDQ VSSQ
VSSQ VDDQ
VSSQ VDDQ
NC
VSSQ
VSSQ
NC
G
H
J
VDDQ VSSQ
VDDQ VSSQ
VSSQ VDDQ
VSSQ VDDQ
VDD
NC
VSS
BA1
A0
VSS
NC
A7
VDD
CK
NC
NC
K
L
NC
A2
A5
CK
NC
NC
BA0
A1
A4
A6
A8
CKE
VREF
M
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Table 3. Pin Assignment by Name (LFBGA 144Ball)
Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location Symbol Location
A0
A1
A2
A3
M4
M5
L5
DQ6
DQ7
DQ8
DQ9
C1
D1
DQ24 D12
DQ25 C12
CK
L10 VDDQ B6
L11 VDDQ B7
VSS
VSS
VSS
VSS
E5
E6
E7
E8
VSS
VSS
VSS
VSS
J7
J8
VSSQ G4
VSSQ G9
CK
J12 DQ26 C11
J11 DQ27 B12
CKE M11 VDDQ B9
K4 VSSQ H4
K9 VSSQ H9
M6
M1 VDDQ B11
CS
A4
A5
M7 DQ10 H12 DQ28
L8 DQ11 H11 DQ29
A9
A8
L1 VDDQ D2
VSS
VSS
VSS
F5
F6
VSSQ A3 VSSQ
VSSQ A10 VSSQ
J4
J9
B3
RAS
K1 VDDQ D11
CAS
A6
A7
M8 DQ12 F12 DQ30
M9 DQ13 F11 DQ31
B8
A7
K2 VDDQ E3
F7
F8
VSSQ C3
VSSQ C4
NC
WE
VREF M12 VDDQ E10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B10
G3
G10
K8
K11
K12
L2
L3
L9
L12
M2
A8/AP M10 DQ14 E12 DQS0 A1
A9
VDD
DQ15 E11 DQS1 G12 VDD
C6 VDDQ F3
C7 VDDQ F10
D3 VDDQ H3
D10 VDDQ H10
G5 VSSQ C5
G6 VSSQ C8
G7 VSSQ C9
G8 VSSQ C10
H5 VSSQ D5
H6 VSSQ D8
H7 VSSQ E4
H8 VSSQ E9
L7
K5
L6
A6
B5
A5
A4
B1
C2
A10
A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
E2
E1
F2
F1
H2
H1
J1
DQS2 G1
DQS3 A12
DM0
VDD
VDD
VDD
A2
K3 VDDQ
J3
DM1 G11 VDD
K6 VDDQ J10
DM2
DM3
BA0
BA1
G2
A11
VDD
VDD
K7
K10
VSS
VSS
VSS
VSS
D4
D6
D7
D9
M3 VDDQ B2
L4 VDDQ B4
J5
J6
VSSQ F4
VSSQ F9
J2
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Figure 2. Block Diagram
CK
DLL
CLOCK
BUFFER
CK
CKE
4096 x 256 x 32
CELL ARRAY
(BANK #0)
Column Decoder
CS
CONTROL
SIGNAL
GENERATOR
COMMAND
DECODER
RAS
CAS
WE
4096 x 256 x 32
CELL ARRAY
(BANK #1)
COLUMN
COUNTER
A8/AP
MODE
REGISTER
Column Decoder
ADDRESS
BUFFER
A0
A9
A10
A11
BA0
BA1
4096 x 256 x 32
CELL ARRAY
(BANK #2)
REFRESH
COUNTER
Column Decoder
DATA
STROBE
BUFFER
DQS0~3
DQ0
DQ
Buffer
4096 x 256 x 32
CELL ARRAY
(BANK #3)
DQ31
Column Decoder
DM0~3
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Pin Descriptions
Table 4. Pin Details
Symbol
CK,
Type
Description
are driven by the system clock. All SDRAM input
Input
CK
Differential Clock: CK,
CK
commands are sampled on the positive edge of CK. Both CK and
internal burst counter and controls the output registers.
increment the
CK
CKE
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next
clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the
entry to the Power Down and Self Refresh modes.
BA0, BA1
A0-A11
Input Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied. They also define which Mode Register or
Extended Mode Register is loaded during a Mode Register Set command.
Input Address Inputs: A0-A11 are sampled during the Bank Activate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A8 defining
Auto Precharge) to select one location out of the 1M available in the respective bank.
During a Precharge command, A8 is sampled to determine if all banks are to be
precharged (A8 = HIGH). The address inputs also provide the op-code during a Mode
Register Set or Extended Mode Register Set command.
Input
Chip Select:
enables (sampled LOW) and disables (sampled HIGH) the
CS
CS
command decoder. All commands are masked when
is sampled HIGH.
CS
CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Input
Row Address Strobe: The
signal defines the operation commands in
RAS
RAS
and /WE signals and is latched at the positive edges of CK.
conjunction with the
CAS
are asserted "LOW" and
When
and
is asserted "HIGH" either the
CAS
CS
RAS
BankActivate command or the Precharge command is selected by the
signal.
WE
When the
is asserted "HIGH," the BankActivate command is selected and the
WE
bank designated by BA is turned on to the active state. When the
is asserted
WE
"LOW," the Precharge command is selected and the bank designated by BA is
switched to the idle state after the precharge operation.
Input
Input
Column Address Strobe: The
signal defines the operation commands in
CAS
CAS
and /WE signals and is latched at the positive edges of CK.
conjunction with the
RAS
When /RAS is held "HIGH" and
is asserted "LOW" the column access is started
CS
by asserting
"LOW" Then, the Read or Write command is selected by asserting
CAS
"HIGH " or “LOW".
WE
Write Enable: The
signal defines the operation commands in conjunction with
WE
WE
signals and is latched at the positive edges of CK. The
CAS
the
and
input
WE
RAS
is used to select the BankActivate or Precharge command and Read or Write
command.
DQS0-DQS3 Input / Bidirectional Data Strobe: The DQSx signals are mapped to the following data
bytes: DQS0 to DQ0-DQ7, DQS1 to DQ8-DQ15, DQS2 to DQ16-DQ23, and DQS3 to
DQ24-DQ31.
Output
DM0 - DM3
Input Data Input Mask: DM0-DM3 are byte specific. Input data is masked when DM is
sampled HIGH during a write cycle. DM3 masks DQ31-DQ24, DM2 masks DQ23-
DQ16, DM1 masks DQ15-DQ8, and DM0 masks DQ7-DQ0.
DQ0 - DQ31 Input / Data I/O: The DQ0-DQ31 input and output data are synchronized with positive and
Output negative edges of DQS0~DQS3. The I/Os are byte-maskable during Writes.
Power Supply: Power for the input buffers and core logic.
VDD
VSS
Supply
Supply
.
Ground: Ground for the input buffers and core logic
VDDQ
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
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VSSQ
VREF
NC
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply Reference Voltage for Inputs: +0.5 x VDDQ
No Connect: No internal connection, these pins suggest to be left unconnected.
-
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Operation Mode
Table 5 shows the truth table for the operation commands.
Table 5. Truth Table (Note (1), (2))
Command
BankActivate
State
CKEn-1 CKEn DM BA1 BA0 A8 A11-A9, A7-0
CS RAS CAS
WE
H
L
Idle(3)
Any
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
V
V
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
L
V
V
X
V
V
V
V
L
Row Address
L
L
L
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
H
L
X
X
L
L
H
H
H
L
BankPrecharge
Precharge All
L
H
L
X
X
Any
L
L
Write
Active(3)
Active(3)
Active(3)
Active(3)
Idle
H
H
H
H
L
L
Column
Address
Write and AutoPrecharge
Read
H
L
L
L
L
H
H
L
A0~A7
Read and Autoprecharge
Mode Register Set
Extended Mode Register Set
No-Operation
H
L
L
OP code
Idle
L
H
X
X
X
X
X
L
L
L
Any
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
H
L
H
X
H
L
H
X
L
Device Deselect
Burst Stop
Any
Active(4)
AutoRefresh
Idle
H
H
X
H
X
H
X
H
X
X
SelfRefresh Entry
Idle
L
L
X
H
X
H
X
H
X
X
X
H
X
H
X
H
X
X
Idle
SelfRefresh Exit
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(Self Refresh)
Power Down Mode Entry
Power Down Mode Exit
Idle/Active(5)
Any
(Power Down)
Active
H
Data Mask Enable(6)
Data Mask Disable
H
H
X
X
H
L
X
X
X
X
X
X
X
X
Active
Note: 1. V = Valid data, X = Don't Care, L = Low level, H = High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA0, BA1signals.
4. Read burst stop with BST command for all burst types.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DM0 – DM3 can be enabled respectively.
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Mode Register Set (MRS)
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs
CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The
default value of the Mode Register is not defined; therefore the Mode Register must be written by the user.
Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by
asserting Low on
,
,
,
, BA1 and BA0 (the device should have all banks idle with no bursts in
WE
CS RAS CAS
progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A11 and
BA0, BA1 in the same cycle in which and are asserted Low is written into the Mode
,
,
WE
CS RAS CAS
Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode
Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses
A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0 should
be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not be
used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific
codes for various burst lengths, burst types and CAS latencies.
Table 6. Mode Register Bitmap
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0 Address Field
0
0
0
T.M.
CAS Latency
Burst Length
Mode Register
Burst Length
Reserved
2
A8 A7
Test Mode
Normal mode
DLL Reset
A6 A5 A4 CAS Latency A3 Burst Type A2 A1 A0
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Sequential
Interleave
X
4
Test mode
3
8
Reserved
Reserved
2.5
Reserved
Reserved
Reserved
Reserved
BA0 Mode
0
1
MRS
EMRS
Reserved
Burst Length Field (A2~A0)
•
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be
2, 4, and 8.
Table 7. Burst Length
A2
0
A1
0
A0
0
Burst Length
Reserved
2
0
0
1
0
1
0
4
0
1
1
8
1
0
0
Reserved
Reserved
Reserved
Reserved
1
0
1
1
1
0
1
1
1
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Addressing Mode Select Field (A3)
•
The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential
Mode and Interleave Mode support burst length of 2, 4, and 8.
Table 8. Addressing Mode
A3
0
Addressing Mode
Sequential
1
Interleave
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
•
Table 9. Burst Address ordering
Start Address
Burst
Length
Sequential
Interleave
A2
A1
X
X
0
A0
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
2
4
0
1
1
0
0
1
1
0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
0
1
1
CAS Latency Field (A6~A4)
•
This field specifies the number of clock cycles from the assertion of the Read command to the first read data.
The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value
satisfying the following formula must be programmed into this field. tCAC (min) ≤ CAS Latency X tCK
Table 10. CAS Latency
A6
0
A5
0
A4
0
CAS Latency
Reserved
Reserved
2 clocks
0
0
1
0
1
0
0
1
1
3 clocks
1
0
0
Reserved
Reserved
2.5 clocks
Reserved
1
0
1
1
1
0
1
1
1
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Test Mode Field (A8~A7)
•
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 11. Test Mode
A8
0
A7
0
Test Mode
Normal mode
DLL Reset
1
0
X
1
Test mode
(BA0, BA1)
•
Table 12. MRS/EMRS
BA1
RFU
RFU
BA0
0
A11 ~ A0
MRS Cycle
1
Extended Functions (EMRS)
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power up
for proper operation. The extended mode register is written by asserting low on
,
,
, and WE . (the
CS RAS CAS
device should have all banks idle with no bursts in progress prior to writing into the mode register, and CKE
should be High)The state of A0 ~ A11 and BA1 are written in the mode register in the same cycle
as
,
,
, and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high
CK RAS CAS
prior to writing into the extended mode register. A1 is used for setting driver strength. Two clock cycles are
required to complete the write operation in the extended mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific
codes.
Table 13. Extended Mode Register Bitmap
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 Address Field
0
1
RFU must be set to “0”
DS DLL Extended Mode Register
A0
DLL
BA0
0
Mode
MRS
A1
0
Drive Strength
Full
0
1
Enable
Disable
1
EMRS
1
Reserved
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Table 14. Absolute Maximum Rating
Rating
Symbol
Item
Unit
Note
-5
- 0.5 ~ VDDQ+0.5
-1 ~ 3.6
0~70
VIN, VOUT
VDD, VDDQ
V
V
1,2
1,2
1
Input, Output Voltage
Power Supply Voltage
Ambient Temperature
Commercial
Industrial
C
°
C
°
C
°
C
°
TA
-40~85
- 55~150
260
1
TSTG
TSOLDER
PD
1
Storage Temperature
1
Soldering Temperature (10s)
Power Dissipation
2.0
W
1
IOS
50
mA
1
Short Circuit Output Current
Note1: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage of the
devices
Note2: These voltages are relative to Vss
Table 15. Recommended D.C. Operating Conditions
°
(SSTL_2 In/Out, TA = -40 ~ 85 C)
Symbol
Parameter
Power Supply Voltage
Min.
Max.
Unit
Note
VDD
2.3
2.7
V
1
VDDQ
2.3
2.7
V
1
Power Supply Voltage(for I/O )
VREF
VTT
0.49 x VDDQ
VREF – 0.04
VREF + 0.15
VSSQ - 0.3
- 2
0.51 x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF- 0.15
2
V
V
Input Reference Voltage
Termination Voltage
Input High Voltage
VIH(DC)
VIL(DC)
IIL
V
V
Input Low Voltage
µA
µA
mA
mA
Input Leakage Current
Output Leakage Current
Output High Current
Output Low Current
IOZ
- 5
5
IOH
IOL
-16.2
16.2
-
-
V
= 1.95V
= 0.35V
OH
V
OL
Table 16. Capacitance
°
(VDD = 2.5V, f = 1MHz, TA = 25 C)
Symbol
Parameter
Min.
Max.
Unit
Input Capacitance (CK,
)
CIN1
1.5
2.5
pF
CK
CIN2
CI/O
Input Capacitance (All other input-only pins)
1.5
3.5
2.5
4.5
pF
pF
DM, DQ, DQS Input/Output Capacitance
Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested.
Table 17. Decoupling Capacitance Guide Line
Symbol
Parameter
Value
Unit
µF
CDC1 Decouping Capacitance between VDD and VSS
CDC2 Decouping Capacitance between VDDQ and VSSQ
0.1+0.01
0.1+0.01
µF
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Table 18. D.C. Characteristics
±
°
(VDD=2.5V 0.2V, TA =-40~85 C)
Parameter & Test Condition
OPERATING CURRENT: One bank; Active-Precharge; t =t (min);
-5
Symbol
Unit
Max.
RC RC
210
mA
t
=t (min); DQ, DM and DQS inputs changing once per clock cycle;
CK CK
IDD0
Address and control inputs changing once every two clock cycles.
OPERATING CURRENT : One bank; Active-Read-Precharge; BL=4;
240
75
t
=t (min); t =t (min); lout=0mA; Address and control inputs
CK CK
RC RC
IDD1
mA
mA
changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; t =t (min); CKE=LOW
IDD2P
CK CK
IDLE STANDBY CURRENT : CKE = HIGH;
=HIGH(DESELECT); All
CS
100
75
IDD2N
IDD3P
IDD3N
mA
mA
mA
banks idle; t =t (min); Address and control inputs changing once per
CK CK
clock cycle; V =V
for DQ, DQS and DM
REF
IN
ACTIVE POWER-DOWN STANDBY CURRENT : one bank active; power-
down mode; CKE=LOW; t =t (min)
CK CK
ACTIVE STANDBY CURRENT :
=HIGH;CKE=HIGH; one bank active ;
CS
=t (max);t =t (min);Address and control inputs changing once per
220
t
RC RC
CK CK
clock cycle; DQ,DQS,and DM inputs changing twice per clock cycle
OPERATING CURRENT BURST READ : BL=2; READs; Continuous burst;
420
420
one bank active; Address and control inputs changing once per clock cycle;
IDD4R
IDD4W
mA
mA
t
=t (min); lout=0mA;50% of data changing on every transfer
CK CK
OPERATING CURRENT BURST Write : BL=2; WRITES; Continuous
Burst ;one bank active; address and control inputs changing once per clock
cycle; t =t (min); DQ,DQS,and DM changing twice per clock cycle; 50%
CK CK
of data changing on every transfer
AUTO REFRESH CURRENT :
300
6
IDD5
IDD6
mA
mA
t
=t
(min); t =t (min)
RC RFC CK CK
SELF REFRESH CURRENT:
≦
Self Refresh Mode ; CKE 0.2V;t =t (min)
CK CK
BURST OPERATING CURRENT 4 bank operation:
Four bank interleaving READs; BL=4;with Auto Precharge; t =t (min);
RC RC
570
IDD7
mA
t
=t (min); Address and control inputs change only during Active,
CK CK
READ , or WRITE command
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage of the
device.
2. All voltages are referenced to VSS.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK.
4. Power-up sequence is described in later page.
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Table 19. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 2.5V ± 0.2V, TA = -40~85 °C)
-5
Symbol
Parameter
Unit
Min.
7.5
6
Max.
12
CL = 2
CL = 2.5
CL = 3
ns
ns
ns
tCK
tCK
tCK
Clock cycle time
12
5
7.5
tCH
tCL
tDQSCK
tAC
Clock high level width
Clock low level width
0.45
0.45
0.55
0.55
DQS-out access time from CK,
Output access time from CK,
-0.6
-0.7
0.6
0.7
ns
ns
CK
CK
tDQSQ
tRPRE
tRPST
tDQSS
DQS-DQ Skew
Read preamble
Read postamble
CK to valid DQS-in
-
0.4
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
ns
µs
ns
ns
0.9
1.1
0.4
0.6
0.72
1.25
tWPRES DQS-in setup time
0
-
tWPRE
tWPST
tDQSH
tDQSL
tIS
DQS Write preamble
0.25
-
DQS write postamble
0.4
0.6
DQS in high level pulse width
DQS in low level pulse width
0.4
-
0.4
-
Address and Control input setup time
Address and Control input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Clock half period
0.7
-
tIH
0.7
-
tDS
0.4
-
tDH
0.4
-
tHP
tCLMIN or tCHMIN
-
tQH
DQ/DQS output hold time from DQS
Row cycle time
tHP - tQHS
-
tRC
55
-
tRFC
tRAS
tRCD
tRP
Refresh row cycle time
70
-
Row active time
40
100K
Active to Read or Write delay
Row precharge time
15
-
15
-
tRRD
tWR
Row active to Row active delay
Write recovery time
2
3
-
-
tMRD
tDAL
tXSRD
tPDEX
tREFI
tIPW
tDIPW
Mode register set cycle time
Auto precharge write recovery + Precharge time
Self refresh exit to read command delay
Power down exit time
2
-
tWR + tRP
200
tCK + tIS
-
-
-
-
Average Refresh interval time
Control and Address input pulse width
DQ & DM input pulse width (for each input)
15.6
2.2
-
-
1.75
Data-out high-impedance window from CK/
tHZ
tLZ
-
0.7
0.7
ns
ns
CK
Data-out low-impedance window from CK/
-0.7
CK
tQHS
Data Hold Skew Factor
-
0.5
ns
ns
DVW
Output data valid window
tQH - tDQSQ
-
-
-
-
-
tXSNR
tCCD
tDSS
tDSH
Exit Self-Refresh to non-Read command
CAS# to CAS# Delay time
75
1
ns
tCK
tCK
tCK
DQS falling edge to CK setup time
DQS falling edge hold time from CK
0.2
0.2
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Table 20. Recommended A.C. Operating Conditions
°
±
(TA = -40~85 C, VDD=2.5V 0.2V)
-5
Parameter
Input High Voltage (AC)
Symbol
Unit
Min.
+ 0.31
Max.
VIH (AC)
VIL (AC)
V
-
V
V
REF
Input Low Voltage (AC)
-
V
– 0.31
REF
Input Different Voltage, CK and
inputs
VID (AC)
inputs
VIX (AC)
0.7
V
0.6
V
V
DDQ +
CK
Input Crossing Point Voltage, CK and
0.5*V
-0.2
0.5*V
+0.2
DDQ
DDQ
CK
Note:
1. All voltages are referenced to VSS
.
2. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during tCK
3. Power-up sequence is described in Note 5.
4. A.C. Test Conditions
.
Table 21. SSTL_2 Interface
Reference Level of Output Signals (VREF
Output Load
)
0.5 * V
DDQ
Reference to the Test Load
VREF+0.31 V / VREF-0.31 V
1 V/ns
Input Signal Levels
Input Signals Slew Rate
Reference Level of Input Signals
0.5 * V
DDQ
Figure 3. SSTL_2 A.C. Test Load
0.5 * VDDQ
50Ω
DQ, DQS
Z0=50Ω
30pF
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5. Power up Sequence
Power up must be performed in the following sequence.
1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held
"NOP" state and maintain CKE “LOW”.
2) Start clock and maintain stable condition for minimum 200us.
3) Issue a “NOP” command and keep CKE “HIGH”
4) Issue a “Precharge All” command.
5) Issue EMRS – enable DLL.
6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL).
7) Precharge all banks of the device.
8) Issue two or more Auto Refresh commands.
9) Issue MRS – with A8 to low to initialize the mode register.
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Timing Waveforms
Figure 4. Activating a Specific Row in a Specific Bank
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
RA
BA
Address
BA0,1
RA=Row Address
BA=Bank Address
Don’t Care
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Figure 5. tRCD and tRRD Definition
CK
CK
RD/WR
COMMAND
ACT
Row
NOP
NOP
NOP
NOP
NOP
ACT
Row
Col
Address
Bank A
Bank B
Bank B
BA0,BA1
tRRD
tRCD
Don’t Care
Figure 6. READ Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
CA
A0 ~ A7
A8
EN AP
DIS AP
BA
BA0,1
CA=Column Address
BA=Bank Address
EN AP=Enable Autoprecharge
DIS AP=Disable Autoprecharge
Don’t Care
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Figure 7. Read Burst Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
Bank A,
Col n
CL=2
DQS
DQ
DO
n
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order
following DO n
Don’t Care
Read Burst Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
Bank A,
Col n
CL=2.5
DQS
DQ
DO
n
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
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Read Burst Required CAS Latencies (CL=3)
CK
CK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
Bank A,
Col n
CL=3
DQS
DQ
DO
n
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order
following DO n
Don’t Care
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Figure 8. Consecutive Read Bursts Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
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Consecutive Read Bursts Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2.5
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
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Consecutive Read Bursts Required CAS Latencies (CL=3)
CK
CK
READ
NOP
READ
COMMAND
ADDRESS
NOP
NOP
NOP
Bank,
Col n
Bank,
Col o
CL=3
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
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Figure 9. Non-Consecutive Read Bursts Required CAS Latencies (CL=2)
CK
CK
READ
NOP
NOP
COMMAND
ADDRESS
READ
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
Non-Consecutive Read Bursts Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2.5
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
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Non-Consecutive Read Bursts Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
READ
NOP
NOP
Bank,
Col n
Bank,
Col o
CL=3
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
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Figure 10. Random Read Accesses Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
NOP
NOP
Bank,
Col o
Bank,
Col p
Bank,
Col q
Bank,
Col n
CL=2
DQS
DQ
DO
q
DO
n'
DO
o
DO
o'
DO
n
DO
p
DO
p'
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
Random Read Accesses Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
NOP
NOP
Bank,
Col o
Bank,
Col p
Bank,
Col q
Bank,
Col n
CL=2.5
DQS
DQ
DO
n'
DO
o
DO
o'
DO
n
DO
p
DO
p'
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
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Random Read Accesses Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
NOP
NOP
Bank,
Col o
Bank,
Col q
Bank,
Col n
Bank,
Col p
CL=3
DQS
DQ
DO
n'
DO
o
DO
o'
DO
n
DO
p
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
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Figure 11. Terminating a Read Burst Required CAS Latencies (CL=2)
CK
CK
READ
NOP
BST
COMMAND
ADDRESS
NOP
NOP
NOP
Bank A,
Col n
CL=2
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Terminating a Read Burst Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
BST
NOP
NOP
NOP
Bank A,
Col n
CL=2.5
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
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Terminating a Read Burst Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
BST
NOP
NOP
NOP
Bank A,
Col n
CL=3
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
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Figure 12. Read to Write Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
WRITE
READ
BST
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
tDQSS
min
CL=2
DQS
DQ
DO
n
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
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Read to Write Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
WRITE
READ
BST
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
ADDRESS
CL=2.5
tDQSS
min
DQS
DQ
DO
n
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
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Read to Write Required CAS Latencies (CL=3)
CK
CK
COMMAND
WRITE
READ
BST
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
ADDRESS
tDQSS
min
CL=3
DQS
DQ
DO
n
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 13. Read to Precharge Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
tRP
Bank A,
Col n
Bank
(a or all)
Bank A,
Row
CL=2
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Read to Precharge Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
tRP
Bank
(a or all)
Bank A,
Col n
Bank A,
Row
CL=2.5
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Read to Precharge Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
tRP
Bank A,
Col n
Bank
(a or all)
Bank A,
Row
CL=3
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 14. Write Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
CA
A0 ~ A7
A8
EN AP
DIS AP
BA
BA0,1
CA=Column Address
BA=Bank Address
EN AP=Enable Autoprecharge
DIS AP=Disable Autoprecharge
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 15. Write Max DQSS
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
Bank A,
Col n
tDQSS
max
DQS
DQ
DI
n
DM
DI n = Data In for column n
3 subsequent elements of Data In are applied in the programmed
order following DI n
A non-interrupted burst of 4 is shown
A8 is LOW with the WRITE command (AUTO PRECHARGE
disabled)
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 16. Write Min DQSS
T4
T0
T1
T2
T3
T5
T6
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
Bank A,
Col n
tDQSS
min
DQS
DQ
DI
n
DM
DI n = Data In for column n
3 subsequent elements of Data In are applied in the programmed
order following DI n
A non-interrupted burst of 4 is shown
A8 is LOW with the WRITE command (AUTO PRECHARGE
disabled)
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 17. Write Burst Nom, Min, and Max tDQSS
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
NOP
NOP
Bank ,
Col n
tDQSS (nom)
DQS
DQ
DI
n
DM
tDQSS (min)
DQS
DQ
DI
n
DM
tDQSS (max)
DQS
DI
n
DQ
DM
DI n = Data In for column n
3 subsequent elements of Data are applied in the programmed order following DI n
A non-interrupted burst of 4 is shown
A8 is LOW with the WRITE command (AUTO PRECHARGE disabled)
DM=DM0 ~ DM3
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 18. Write to Write Max tDQSS
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
WRITE
NOP
NOP
NOP
NOP
Bank ,
Col o
Bank ,
Col n
tDQSS (max)
DQS
DQ
DI
n
DI
o
DM
DI n , etc. = Data In for column n,etc.
3 subsequent elements of Data In are applied in the programmed order following DI n
3 subsequent elements of Data In are applied in the programmed order following DI o
Non-interrupted bursts of 4 are shown
DM= DM0 ~ DM3
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 19. Write to Write Max tDQSS, Non Consecutive
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
WRITE
NOP
NOP
NOP
NOP
Bank
Col n
Bank
Col o
tDQSS (max)
DQS
DQ
DI
n
DI
o
DM
DI n, etc. = Data In for column n, etc.
3 subsequent elements of Data In are applied in the programmed order following DI n
3 subsequent elements of Data In are applied in the programmed order following DI o
Non-interrupted bursts of 4 are shown
DM= DM0 ~ DM3
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 20. Random Write Cycles Max tDQSS
T8
T9
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
Bank
Col r
Bank
Col n
Bank
Col o
Bank
Col p
Bank
Col q
tDQSS (max)
DQS
DQ
DI
n
DI
n'
DI
o
DI
o'
DI
p'
DI
p
DI
q'
DI
q
DM
DI n, etc. = Data In for column n, etc.
n', etc. = the next Data In following DI n, etc. according to the programmed burst order
Programmed Burst Length 2, 4, or 8 in cases shown
If burst of 4 or 8, the burst would be truncated
Each WRITE command may be to any bank and may be to the same or different devices
DM= DM0 ~ DM3
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 21. Write to Read Max tDQSS Non Interrupting
T12
T8
T9
T10 T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
WRITE
READ
NOP
NOP
NOP
NOP
NOP
tWTR
Bank
Col o
Bank
Col n
ADDRESS
CL=3
tDQSS (max)
DQS
DQ
DI
n
DM
DI n, etc. = Data In for column n, etc.
1 subsequent elements of Data In are applied in the programmed order following DI n
A non-interrupted burst of 2 is shown
tWTR is referenced from the first positive CK edge after the last Data In Pair
A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
DM= DM0 ~ DM3
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 22. Write to Read Max tDQSS Interrupting
T8
T9
T10
T11
T12
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
READ
NOP
NOP
NOP
NOP
tWTR
Bank
Col o
Bank
Col n
CL=3
tDQSS (max)
DQS
DQ
DI
n
DM
DI n, etc. = Data In for column n, etc.
1 subsequent elements of Data In are applied in the programmed order following DI n
An interrupted burst of 8 is shown, 2 data elements are written
tWTR is referenced from the first positive CK edge after the last Data In Pair
A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
DM= DM0 ~ DM3
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 23. Write to Read Max tDQSS, ODD Number of Data, Interrupting
T4
T8
T9
T10
T11
T12
T0
T1
T2
T3
T5
T6
T7
CK
CK
WRITE
READ
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
tWTR
Bank
Col o
Bank
Col n
CL=3
tDQSS (max)
DQS
DQ
DI
n
DM
DI n = Data In for column n
An interrupted burst of 8 is shown, 1 data elements are written
tWTR is referenced from the first positive CK edge after the last Data In Pair (not the last desired
Data In element)
A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
DM= DM0 ~ DM3
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 24. Write to Precharge Max tDQSS, NON- Interrupting
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
PRE
NOP
tWR
Bank a,
Col n
Bank
(a or al)
tRP
tDQSS (max)
DQS
DQ
DI
n
DM
DI n = Data In for column n
1 subsequent elements of Data In are applied in the programmed order following DI n
A non-interrupted burst of 2 is shown
tWR is referenced from the first positive CK edge after the last Data In Pair
A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
DM= DM0 ~ DM3
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 25. Write to Precharge Max tDQSS, Interrupting
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
PRE
NOP
NOP
NOP
tWR
Bank a,
Col n
Bank
(a or all)
tRP
tDQSS (max)
*2
DQS
DQ
DI
n
DM
*1
*1
*1
*1
DI n = Data In for column n
An interrupted burst of 4 or 8 is shown, 2 data elements are written
tWR is referenced from the first positive CK edge after the last Data In Pair
A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
DM= DM0 ~ DM3
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 26. Write to Precharge Max tDQSS ODD Number of Data Interrupting
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
NOP
PRE
tWR
Bank a,
Col n
Bank
(a or all)
tRP
tDQSS (max)
*2
DQS
DQ
DI
n
DM
*1
*1
*1
*1
DI n = Data In for column n
An interrupted burst of 4 or 8 is shown, 1 data element is written
tWR is referenced from the first positive CK edge after the last Data In Pair
A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
DM= DM0 ~ DM3
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 27. Precharge Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
A0-A7,
A9-A11
ALL BANKS
A8
ONE BANK
BA
BA0,1
BA= Bank Address (if A8 is LOW,
otherwise don't care)
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 28. Power-Down
Tn+3 Tn+4 Tn+5 Tn+6
T4
T0
T1
T2
T3
Tn Tn+1 Tn+2
CK
CK
tIS
tIS
CKE
VALID
VALID
COMMAND
NOP
NOP
Exit power-down
mode
Enter power-down
mode
No column access
in progress
Don’t Care
Figure 29. Clock Frequency Change in Precharge
Ty+1
Ty+3
Ty+4
T0
T1
T2
T4
Tx
Tx+1
Ty
Ty+2
Tz
CK
CK
DLL
RESET
NOP NOP
NOP
NOP
NOP
Valid
CMD
CKE
tIS
Frequency Change
Occurs here
tRP
Minmum 2 clocks
Required before
200 Clocks
Stable new clock
Before power down exit
Changing frequency
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 30. Data input (Write) Timing
tDQSH
tDQSL
DQS
DQ
tDS
DI
n
tDH
tDS
DM
tDH
DI n = Data In for column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed order
following DI n
Don’t Care
Figure 31. Data Output (Read) Timing
tCL
tCH
CK
CK
DQS
DQ
tDQSQ
max
tDQSQ
max
tQH
tQH
Burst Length = 4 in the case shown
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 32. Initialize and Mode Register Sets
VDD
VDDQ
tVDT>=0
VTT
(system*)
tCK
VREF
tCH tCL
CK
CK
tIS tIH
LVCMOS LOW LEVEL
CKE
tIS tIH
EMRS
AR
MRS
COMMAND
DM
NOP
PRE
MRS
PRE
AR
ACT
tIS tIH
A0-A7,
A9-A11
CODE
CODE
CODE
CODE
CODE
RA
RA
BA
tIS tIH
ALL BANKS
ALL BANKS
CODE
A8
tIS tIH
tIS tIH
tIS tIH
BA0=H
BA1=L
BA0=L
BA1=L
BA0=L
BA1=L
BA0,BA1
High-Z
DQS
DQ
High-Z
**tMRD
**tMRD
tRFC
tRFC
**tMRD
tRP
200 cycles of CK**
T=200µs
Extended mode
Register set
Load Mode
Register,
(with A8=L)
Power-up:
Load Mode
VDD and
Register,
CLK stable
Reset DLL (with A8=H)
Don’t Care
*=VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CK are required before any executable
command can be applied the two auto Refresh commands may be moved to follow the first MRS but precede the second
PRECHARGE ALL command.
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 33. Power Down Mode
tCK
tCH
tCL
CK
CK
tIS tIH
tIS
tIS
CKE
tIS tIH
VALID*
VALID
COMMAND
NOP
NOP
tIS tIH
VALID
VALID
ADDR
DQS
DQ
DM
Enter
power-down mode
Exit
power-down mode
No column accesses are allowed to be in progress at the time Power-Down is entered
*=If this command is a PRECHARGE ALL (or if the device is already in the idle state) then the Power-Down
mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active)
then the Power-Down mode shown is active Power Down.
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 34. Auto Refresh Mode
tCK
tCH tCL
CK
CK
tIS
tIH
CKE
VALID
VALID
tIS tIH
NOP
ACT
RA
AR
NOP
AR
NOP
NOP
PRE
NOP
NOP
COMMAND
A0-A7
A9-A11
RA
RA
BA
ALL BANKS
A8
ONE BANKS
tIS tIH
*Bank(s)
BA0,BA1
DQS
DQ
DM
tRFC
tRP
tRFC
* = “ Don't Care” , if A8 is HIGH at this point; A8 must be HIGH if more than one bank is active (i.e., must precharge all active banks)
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other valid commands may be possible after tRFC
DM, DQ and DQS signals are all “ Don't Care” /High-Z for operations shown
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 35. Self Refresh Mode
tCK
Clock must be stable before
Exiting Self Refresh mode
tCH
tCL
CK
CK
tIS tIH
tIS
tIS
CKE
tIS tIH
NOP
VALID
COMMAND
NOP
AR
tIS tIH
VALID
ADDR
DQS
DQ
DM
tXSNR/
tXSRD**
tRP*
Enter Self Refresh
mode
Exit Self Refresh
mode
* = Device must be in the “ All banks idle” state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is
required before a READ command can be applied.
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 36. Read without Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS
tIH
CKE
VALID
NOP
VALID
NOP
VALID
NOP
tIS tIH
NOP
NOP
NOP
ACT
RA
READ
PRE
NOP
COMMAND
ADDRESS
tIS tIH
Col n
tIS tIH
ALL BANKS
ONE BANKS
A8
RA
DIS AP
tIS tIH
Bank X
*Bank X
Bank X
BA0,BA1
CL=3
tRP
DM
Case 1:
tAC/tDQSCK=min
tDQSCK
tRPST
min
tRPRE
DQS
DQ
tLZ
min
DO
n
tLZ
tAC
min
min
Case 2:
AC/tDQSCK=max
tDQSCK
t
tRPST
max
tRPRE
DQS
DQ
tLZ
tHZ
max
max
DO
n
tLZ
tAC
max
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP = Disable Autoprecharge
* =“ Don't Care” , if A8 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other commands may be valid at these times
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 37. Read with Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS
tIH
CKE
VALID
NOP
VALID
NOP
VALID
NOP
tIS tIH
NOP
NOP
ACT
RA
NOP
READ
NOP
NOP
COMMAND
A0-A7
tIS tIH
Col n
A9-A11
A8
RA
RA
EN AP
tIS tIH
tIS
tIH
Bank X
Bank X
BA0,BA1
CL=3
tRP
DM
Case 1:
t
AC/tDQSCK=min
tDQSCK
tRPST
min
tRPRE
DQS
DQ
tLZ
min
DO
n
tLZ
tAC
min
min
Case 2:
AC/tDQSCK=max
tDQSCK
max
t
tRPST
tRPRE
DQS
DQ
tLZ
tHZ
max
max
DO
n
tLZ
tAC
max
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
EN AP = Enable Autoprecharge
ACT = ACTIVE, RA = Row Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
The READ command may not be issued until tRAP has been satisfied. If Fast Autoprecharge is supported, tRAP = tRCD, else the READ
may not be issued prior to tRASmin – (BL*tCK/2)
Don’t Care
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 38. Bank Read Access
tCK
tCH tCL
CK
CK
tIS tIH
CKE
tIS tIH
NOP
ACT
NOP
NOP
NOP
NOP
READ
Col n
PRE
NOP
NOP
ACT
COMMAND
A0-A7
tIS tIH
RA
RA
RA
A9-A11
RA
RA
tIS tIH
ALL BANKS
ONE BANKS
A8
RA
DIS AP
tIS
tIH
Bank X
Bank X
Bank X
*Bank X
BA0,BA1
tRC
tRAS
CL=3
tRCD
tRP
DM
Case 1:
tDQSCK
min
t
AC/tDQSCK=min
tRPST
tRPRE
DQS
tLZ
DO
n
min
DQ
tLZ
tAC
min
min
Case 2:
tDQSCK
max
t
AC/tDQSCK=max
tRPST
tRPRE
DQS
tHZ
max
tLZ
max
DO
n
DQ
tLZ
tAC
max
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP = Disable Autoprecharge
* = ” Don't Care” , if A8 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS
would be limiting)
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 39. Write without Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS
tIH
CKE
VALID
tIS tIH
WRITE
NOP
NOP
PRE
NOP
NOP
ACT
RA
NOP
NOP
NOP
COMMAND
A0-A7
tIS tIH
Col n
A9-A11
A8
RA
RA
BA
tIS tIH
ALL BANKS
ONE BANKS
DIS AP
tIS tIH
Bank X
*Bank X
BA0,BA1
Case 1:
tRP
tDSH
tDSH
tDQSS
tWR
tDQSS=min
tDQSH
tWPST
DQS
tDQSL
tWPRES
tWPRE
DI
n
DQ
DM
tDSS
tDQSH
tDSS
tWPST
Case 2:
tDQSS=max
tDQSS
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=” Don't Care” , if A8 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the +
25% window of the corresponding positive clock edge
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Don’t Care
Confidential
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Rev.1.0 May 2016
AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 40. Write with Auto Precharge
tCK
tCH tCL
CK
CK
tIS
tIH
CKE
VALID
NOP
VALID
NOP
VALID
NOP
tIS tIH
WRITE
NOP
NOP
ACT
RA
NOP
NOP
NOP
COMMAND
A0-A7
tIS tIH
Col n
A9-A11
RA
DIS AP
RA
BA
A8
tIS
tIH
Bank X
BA0,BA1
tDAL
Case 1:
tDSH
tDSH
tDQSS
tDQSS=min
tDQSH
tWPST
DQS
tWPRES
tWPRE
tDQSL
DI
n
DQ
DM
tDSS
tDQSH
tDSS
Case 2:
tDQSS=max
tDQSS
tWPST
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DI n
EN AP = Enable Autoprecharge
ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Don’t Care
Confidential
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AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 41. Bank Write Access
tCK
tCH tCL
CK
CK
tIS
tIH
CKE
tIS tIH
WRITE
Col n
NOP
NOP
PRE
NOP
NOP
NOP
ACT
NOP
NOP
COMMAND
A0-A7
tIS tIH
RA
RA
RA
A9-A11
tIS tIH
ALL BANKS
A8
DIS AP
ONE BANK
*Bank X
tIS tIH
Bank X
Bank X
BA0,BA1
tRAS
tRCD
tWR
Case 1:
tDSH
tDQSH
tDSH
tWPST
t
DQSS=min
tDQSS
DQS
tWPRES
tWPRE
tDQSL
DI
n
DQ
DM
tDSS
Case 2:
tDSS
tWPST
tDQSH
t
DQSS=max
tDQSS
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=” Don't Care” , if A8 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Don’t Care
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Confidential
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Rev.1.0 May 2016
AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 42. Write DM Operation
tCK
tCH tCL
CK
CK
tIS
tIH
CKE
VALID
tIS tIH
WRITE
NOP
NOP
PRE
NOP
NOP
ACT
RA
NOP
NOP
NOP
COMMAND
A0-A7
tIS tIH
Col n
A9-A11
A8
RA
RA
BA
tIS tIH
ALL BANKS
ONE BANKS
DIS AP
tIS tIH
Bank X
BA0,BA1
Case 1:
*Bank X
tRP
tDSH
tDSH
tDQSS
tDQSS=min
tWR
tDQSH
tWPST
DQS
tDQSL
tWPRES
tWPRE
DI
n
DQ
DM
tDSS
tDQSH
tDSS
tWPST
Case 2:
tDQSS=max
tDQSS
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=” Don't Care” , if A8 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Don’t Care
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Confidential
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Rev.1.0 May 2016
AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
Figure 43. 144 ball LFBGA Package Outline Drawing Information
Units: mm
PIN #1
Top View
Side View
Bottom View
"A"
DETAIL : "A"
Dimension in inch
Dimension in mm
Symbol
Min
--
Nom Max
-- 0.055
Min
--
Nom Max
-- 1.40
A
A1
A2
D
0.012 0.014 0.016 0.30 0.35 0.40
0.036 0.038 0.040 0.91 0.96 1.01
0.469 0.472 0.476 11.90 12.00 12.10
0.469 0.472 0.476 11.90 12.00 12.10
E
D1
E1
e
--
--
--
0.346
0.346
0.031
--
--
--
--
--
--
8.80
8.80
0.80
--
--
--
b
0.016 0.018 0.020 0.40 0.45 0.50
Confidential
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Rev.1.0 May 2016
AS4C4M32D1A-5BIN
AS4C4M32D1A-5BCN
PART NUMBERING SYSTEM
AS4Cꢀ
4M32D1Aꢀ
5ꢀ
Bꢀ
C/Iꢀ
Nꢀ
C=ꢀCommercialꢀ
(0°ꢀC~70°ꢀC)ꢀ
I=ꢀIndustrialꢀ
(-40°ꢀC~85°ꢀC)ꢀ
4M32=4Mx32ꢀ
D1=DDR1ꢀ
A=ꢀAꢀdieꢀversionꢀ
IndicatesꢀPbꢀandꢀ
HalogenꢀFreeꢀ
DRAMꢀ
5=200MHzꢀ
Bꢀ=ꢀFBGAꢀ
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time
without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right
to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties related to the
sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms
and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively
according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a
license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting
systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such
use and agrees to indemnify Alliance against all claims arising from such use.
Confidential
- 64/64 -
Rev.1.0 May 2016
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