AS4C4M32SA-7TCN [ALSC]
4M x 32bit -AS4C4M32SA - 86-pin TSOP II PACKAGE;
| 型号： | AS4C4M32SA-7TCN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 4M x 32bit -AS4C4M32SA - 86-pin TSOP II PACKAGE 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总47页 (文件大小：1959K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Revision History
4M x 32bit -AS4C4M32SA - 86-pin TSOP II PACKAGE
Revision Details
Date
Rev 1.0
Preliminary datasheet
Sep. 2015
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
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Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Overview
Features
The 128Mb SDRAM is a high-speed CMOS
synchronous DRAM containing 134,217,728 Mbits. It
is internally configured as a quad 1M x 32 DRAM
Fast access time from clock: 5.4/5.4 ns
•
with
a synchronous interface (all signals are
Fast clock rate: 166/143 MHz
Fully synchronous operation
Internal pipelined architecture
Four internal banks (1M x 32-bit x 4bank)
Programmable Mode
•
•
•
•
•
registered on the positive edge of the clock signal,
CLK). Each of the 1M x 32 bit banks is organized as
4096 rows by 256 columns by 32 bits. Read and
write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
- CAS Latency: 2 or 3
The SDRAM provides for programmable Read or
Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use. By having a programmable
mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring
high memory bandwidth.
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: Sequential & Interleaved
- Burst-Read-Single-Write
Burst stop function
•
•
•
•
•
•
Individual byte controlled by DQM0-3
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
Single 3.3V ±0.3V power supply
Operating Temperature
- Commercial (0°C~+70°C)
- Industrial (-40°C~+85°C)
Interface: LVTTL
•
•
Package:
- 86-pin 400 mil plastic TSOP II package (Pb free and Halogen free)
Table 1. Ordering Information
Org
Temperature
Max Clock (MHz)
166 MHz
Product part No
Package
AS4C4M32SA-6TIN
Industrial -40°C to +85°C
86-pin TSOP II
4M x 32
4M x 32
4M x 32
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Commercial 0°C to +70°C
Commercial 0°C to +70°C
166 MHz
86-pin TSOP II
86-pin TSOP II
143 MHz
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AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 1. Pin Assignment
(Top View)
VDD
DQ0
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
2
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ1
3
4
DQ2
5
VSSQ
DQ3
6
7
DQ4
8
VDDQ
DQ5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ6
VSSQ
DQ7
VDDQ
DQ8
NC
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
VSS
DQM1
NC
NC
CLK
CKE
A9
A11
BA0
A8
BA1
A7
A10/AP
A0
A6
A5
A1
A4
A2
A3
DQM2
VDD
DQM3
VSS
NC
NC
DQ16
VSSQ
DQ17
DQ18
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
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AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 2. Block Diagram
4096 x 256 x 32
CELL ARRAY
(BANK #0)
CLOCK
BUFFER
CLK
CKE
Column Decoder
CS#
DQ0
DQ Buffer
RAS#
CAS#
WE#
COMMAND
DECODER
DQ31
CONTROL
SIGNAL
GENERATOR
DQM0~3
4096 x 256 x 32
CELL ARRAY
(BANK #1)
COLUMN
COUNTER
A10/AP
Column Decoder
MODE
REGISTER
A0
ADDRESS
BUFFER
4096 x256 x 32
CELL ARRAY
(BANK #2)
A9
A11
BA0
BA1
Column Decoder
REFRESH
COUNTER
4096 x 256 x 32
CELL ARRAY
(BANK #3)
Column Decoder
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AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Pin Descriptions
Table 2. Pin Details
Symbol
Type
Description
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE
goes low synchronously with clock(set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When all banks are in the
idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until exiting the same
mode. The input buffers, including CLK, are disabled during Power Down and Self
Refresh modes, providing low standby power.
BA0, BA1
A0-A11
Input
Input
Bank Activate: BA0 and BA1 defines to which bank the BankActivate, Read, Write,
or BankPrecharge command is being applied. The bank address BA0 and BA1 is
used latched in mode register set.
Address Inputs: A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 1M available in the
respective bank. During a Precharge command, A10 is sampled to determine if all
banks are to be precharged (A10 = HIGH). The address inputs also provide the op-
code during a Mode Register Set or Special Mode Register Set command.
CS#
Input
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
RAS#
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH,"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
CAS#
WE#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is
started by asserting CAS# "LOW." Then, the Read or Write command is selected by
asserting WE# "LOW" or "HIGH."
Input
Input
Write Enable: The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
DQM0-
DQM3
Data Input/Output Mask: Data Input Mask: DQM0-DQM3 are byte specific. Input
data is masked when DQM is sampled HIGH during a write cycle. DQM3 masks
DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0
masks DQ7-DQ0.
DQ0-
DQ31
Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive
Output edges of CLK. The I/Os are byte-maskable during Reads and Writes.
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AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
NC
VDDQ
VSSQ
VDD
-
No Connect: These pins should be left unconnected.
Supply DQ Power: Provide isolated power to DQs for improved noise immunity.
Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Supply
±
Power Supply: 3.3V 0.3V.
VSS
Supply Ground
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AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 3 shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
State CKEn-1 CKEn DQM(6) BA0,1 A10 A11, A9-0 CS# RAS# CAS# WE#
Idle(3)
H
H
H
H
H
X
X
X
X
X
X
X
X
V
V
V
V
X
V
V
Row address
L
L
L
L
L
L
L
H
H
H
L
H
L
L
L
L
BankActivate
BankPrecharge
PrechargeAll
Any
L
H
L
X
X
Any
L
Active(3)
Active(3)
H
H
Write
Column
address
(A0 ~ A7)
Write and AutoPrecharge
H
L
Active(3)
Active(3)
H
H
X
X
V
V
V
V
L
L
L
H
H
L
L
H
H
Read
Column
address
(A0 ~ A7)
Read and Autoprecharge
H
Mode Register Set
No-Operation
Idle
Any
H
H
H
H
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
OP code
L
L
L
H
H
X
L
L
H
H
X
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Active(4)
L
Burst Stop
Device Deselect
AutoRefresh
Any
H
L
X
H
H
X
H
X
V
X
H
X
X
H
X
X
Idle
SelfRefresh Entry
SelfRefresh Exit
Idle
L
L
L
Idle
H
H
L
X
H
X
V
X
H
X
X
H
X
X
X
H
X
V
X
H
X
X
H
X
X
(SelfRefresh)
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any(5)
Active
H
H
L
L
X
X
X
X
X
X
X
X
H
L
H
L
Clock Suspend Mode Exit
Power Down Mode Exit
L
L
H
H
X
X
X
X
X
X
X
X
X
H
L
Any
(PowerDown)
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
H
H
X
X
L
X
X
X
X
X
X
X
X
H
Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
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AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Commands
1
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BA 0,1= Bank, A0-A11 = Row Address)
The BankActivate command activates the idle bank designated by the BA0,1 (Bank Activate)
signal. By latching the row address on A0 to A11 at the time of this command, the selected row
access is initiated. The read or write operation in the same bank can occur after a time delay of
tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row
in the same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares
part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of
the two banks. tRRD(min.) specifies the minimum time required between activating different banks.
After this command is used, the Write command performs the no mask write operation.
Figure 3. BankActivate Command Cycle
(Burst Length = n)
T0
T1
T2
T3
Tn+3 Tn+4
Tn+5
Tn+6
CLK
Bank A
Bank A
Bank B
Bank A
ADDRESS
Row Addr.
Col Addr.
Row Addr.
Row Addr.
RAS# - CAS# delay(tRCD
)
RAS# - RAS# delay time(tRRD)
Bank A
Activate
Bank B
Activate
Bank A
Activate
R/W A with
AutoPrecharge
NOP
NOP
NOP
NOP
COMMAND
RAS# - Cycle time(tRC
)
AutoPrecharge
Begin
Don’t Care
2
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BA0, 1 = Bank, A10 = "L", A0-A9, A11 = Don't care)
The BankPrecharge command precharges the bank designated by BA0, 1 signal. The
precharged bank is switched from the active state to the idle state. This command can be asserted
anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The
maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function
must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged
bank is still in the idle state and is ready to be activated again.
3
4
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BA0,1 = Don’t care, A10 = "H", A0-A9, A11 = Don't care)
The PrechargeAll command precharges all the four banks simultaneously and can be issued
even if all banks are not in the active state. All banks are then switched to the idle state.
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BA0, 1 = Bank, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS latency after the issue of the Read command. Each subsequent data-out
element will be valid by the next positive clock edge (refer to the following figure). The DQs go into
high-impedance at the end of the burst unless other command is initiated. The burst length, burst
sequence, and CAS latency are determined by the mode register which is already programmed. A
full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and
continue).
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AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 4. Burst Read Operation
(Burst Length = 4, CAS# Latency = 2, 3)
T3 T4 T5 T6 T7 T8
T0
T1
T2
CLK
NOP
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS# latency=2
tCK2, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e.
DQM latency is two clocks for output buffers). A read burst without the auto precharge function may
be interrupted by a subsequent Read or Write command to the same bank or the other active bank
before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank too. The interrupt coming from the Read command can occur on any
clock cycle following a previous Read command (refer to the following figure).
Figure 5. Read Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ B
CAS# latency=2
tCK2, DQ
DOUT A0
DOUT B0
DOUT A0
DOUT B1
DOUT B0
DOUT B2 DOUT B3
CAS# latency=3
DOUT B1
DOUT B2 DOUT B3
tCK3, DQ
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from
a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write
command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a
single cycle with high-impedance on the DQ pins must occur between the last read data and the
Write command (refer to the following figure). If the data output of the burst read occurs at the
second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the
Write command to avoid internal bus contention.
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Figure 6. Read to Write Interval
(Burst Length ≥ 4, CAS# Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
DQM
WRITE
A
BANKA
ACTIVATE
NOP
NOP
NOP
READ A
NOP
NOP
NOP
NOP
COMMAND
CAS# latency=2
DIN A0
DIN A1
DIN A2
DIN A3
tCK2, DQ
Must be Hi-Z before
the Write Command
Figure 7. Read to Write Interval
(Burst Length ≥ 4, CAS# Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
WRITE B
DIN B0
NOP
NOP
READ A
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS# latency=2
tCK2, DQ
DIN B1
DIN B2
DIN B3
Must be Hi-Z before
the Write Command
Don’t Care
≧
Figure 8. Read to Write Interval
(Burst Length
4, CAS# Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
DIN B0
NOP
NOP
COMMAND
CAS# Latency=3
tCK3, DQ
DOUT A0
DIN B1
DIN B2
Must be Hi-Z before
the Write Command
Don’t Care
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/ PrechargeAll command is issued in different CAS latency.
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Figure 9. Read to Precharge
(CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Bank,
Col A
Bank
Row
Bank(s)
ADDRESS
tRP
NOP
Precharge
READ A
NOP
NOP
NOP
NOP
NOP
Activate
COMMAND
CAS# latency=2
tCK2, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
CAS# latency=3
tCK3, DQ
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Don’t Care
5
6
Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read operation. Once this command is given, any subsequent command cannot occur within a time
delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
Write command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is
issued. During write bursts, the first valid data-in element will be registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge
(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless
another command is initiated. The burst length and burst sequence are determined by the mode
register, which is already programmed. A full-page burst will continue until terminated (at the end of
the page it will wrap to column 0 and continue).
Figure 10. Burst Write Operation
(Burst Length = 4)
T3 T4 T5
T0
T1
T2
T6
T7
T8
CLK
NOP
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQ
DIN A1
DIN A2
DIN A3
The first data element and the write
are registered on the same clock edge
Don’t Care
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command
(refer to the following figure).
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Figure 11. Write Interrupted by a Write
(Burst Length = 4)
T4 T5 T6
T0
T1
T2
T3
T7
T8
CLK
WRITE A WRITE B
COMMAND
DQ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
The Read command that interrupts a write burst without auto precharge function should be
issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid
data contention, input data must be removed from the DQs at least one clock cycle before the first
read data appears on the outputs (refer to the following figure). Once the Read command is
registered, the data inputs will be ignored and writes will not be executed.
Figure 12. Write Interrupted by a Read
(Burst Length = 4, CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
WRITE A
DIN A0
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
READ B
NOP
CAS# latency=2
DOUT B0 DOUT B1 DOUT B2 DOUT B3
tCK2, DQ
CAS# latency=3
tCK3, DQ
DIN A0
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ at least one clock cycle before
the Read data appears on the outputs to avoid data contention
Don’t Care
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto
precharge function should be issued m cycles after the clock edge in which the last data-in element
is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM
signals must be used to mask input data, starting with the clock edge following the last data-in
element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is
entered (refer to the following figure).
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Figure 13. Write to Precharge
T0
T1
T2
T3
T4
T5
T6
T7
CLK
DQM
tRP
Precharge
BANK(S)
NOP
NOP
WRITE
Activate
ROW
NOP
NOP
NOP
COMMAND
ADDRESS
BANK
COL n
tWR
DIN
N+1
DIN
N
DQ
Don’t Care
Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.
7
Write and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "L", BA = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the
write operation. Once this command is given, any subsequent command can not occur within a time
delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed
in this command and the auto precharge function is ignored.
Figure 14. Burst Write with Auto-Precharge
(Burst Length = 2)
T5 T6 T7
T0
T1
T2
T3
T4
T8
T9
CLK
Bank A
Activate
Bank A
Activate
WRITE A
Auto Precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
tDAL
DIN A0
DIN A1
DQ
tDAL=tWR+tRP
Begin AutoPrecharge
Bank can be reactivated at
completion of tDAL
8
Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The
Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst
Length in the Mode register to make SDRAM useful for a variety of different applications. The default
values of the Mode Register after power-up are undefined; therefore this command must be issued
at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to
the mode register. Two clock cycles are required to complete the write in the mode register (refer to
the following figure). The contents of the mode register can be changed using the same command
and the clock cycle requirements during operation as long as all banks are in the idle state.
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Table 4. Mode Register Bitmap
BA1 BA0 A11 A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
0
0
0
0
W.B.L
TM
CAS Latency
Burst Length
A9 Write Burst Length
A8
0
1
A7 Test Mode
A3 Burst Type
0
1
Burst
Single Bit
0
0
1
Normal
Reserved
Reserved
0
1
Sequential
Interleave
0
A6
0
0
0
0
A5
0
0
1
1
A4
0
1
0
1
CAS Latency
Reserved
Reserved
2 clocks
3 clocks
Reserved
A2
0
0
0
0
A1
0
0
1
1
A0
Burst Length
0
1
0
1
1
1
2
4
8
1
0
0
1
1
Full Page (Sequential)
All other Reserved
All other Reserved
Note: Column address is repeated until terminated in Full Page Mode
Figure 15. Mode Register Set Cycle
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLK
CKE
tMRD
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
Hi-Z
PrechargeAll
Mode Register
Set Command
Any
Command
Don’t Care
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Burst Definition, Addressing Sequence of Sequential and Interleave Mode
•
Table 5. Burst Definition
Start Address
Burst Length
Sequential
Interleave
A2
X
X
X
X
X
X
0
0
0
0
1
A1
X
X
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
2
4
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
n, n+1, n+2, n+3, …255, 0,
1, 2, … n-1, n, …
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
1
0
0
1
8
1
1
1
1
Full page location = 0-255
Not Support
9
No-Operation command (RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is
Low). This prevents unwanted commands from being registered during idle or wait states.
10 Burst Stop command (RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This
command is only effective in a read/write burst without the auto precharge function. The terminated
read burst ends after a delay equal to the CAS latency (refer to the following figure). The termination
of a write burst is shown in the following figure.
Figure 16. Termination of a Burst Read Operation
＞
(Burst Length 4, CAS# Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
The burst ends after a delay equal to the CAS# latency
CAS# latency=2
tCK2, DQ
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
CAS# latency=3
tCK3, DQ
DOUT A3
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Figure 17. Termination of a Burst Write Operation
(Burst Length = X)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Burst
Stop
WRITE A
DIN A0
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DIN A1 DIN A2
DQ
Don’t Care
11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#
and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar
to the No Operation command.
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BA0,1 = “Don‘t care, A0-A11 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to
CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it
must be issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal
refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh
operation must be performed 4096 times within 64ms. The time required to complete the auto
refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to
be in the idle state and the device must not be in power down mode (CKE is high in the previous
cycle). This command must be followed by NOPs until the auto refresh operation is completed. The
precharge time requirement, tRP(min), must be met before successive auto refresh operations are
performed.
13 SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A11 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh
mode for data retention and low power operation. Once the SelfRefresh command is registered, all
the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.
The refresh addressing and timing is internally generated to reduce power consumption. The
SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by
restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP
or Device Deselect commands must be issued for tRC(min.) because time is required for the
completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are
performed during normal operation, a burst of 4096 auto refresh cycles should be completed just
prior to entering and just after exiting the SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held
intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command
performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are
turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown
state longer than the refresh period (64ms) since the command does not perform any refresh
operations.
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16 Clock Suspend Mode Exit / PowerDown Mode Exit command
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from
the subsequent cycle by providing this command (asserting CKE "HIGH", the command should be
NOP or deselect). When the device is in the PowerDown mode, the device exits this mode and all
disabled buffers are turned on to the active state. tXSR(min.) is required when the device exits from
the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end
of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of the
input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also
used for device selection, byte selection and bus control in a memory system.
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Table 6. Absolute Maximum Rating
Symbol
Item
Input, Output Voltage
Values
Unit Note
VIN, VOUT
-1.0 ~ 4.6
V
VDD, VDDQ
-1.0 ~ 4.6
0 ~ 70
-40 ~ 85
-55 ~ 150
1.1
V
°C
°C
°C
W
Power Supply Voltage
Commercial
Industrial
Ambient Temperature
TA
TSTG
PD
Storage Temperature
Power Dissipation
IOS
50
mA
Short Circuit Output Current
Note: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
±
Table 7. Recommended D.C. Operating Conditions
(VDD = 3.3V 0.3V, TA = -40~85°C)
Symbol
VDD
Parameter/ Condition
DRAM Core Supply Voltage
Min.
3.0
3.0
2
Typ.
3.3
3.3
-
Max.
3.6
Unit Note
V
V
V
V
2
2
2
2
VDDQ
VIH
I/O Supply Voltage
3.6
Input High Level Voltage
Input Low Level Voltage
Input Leakage Current
V
+0.3
DDQ
-
VIL
-0.3
0.8
IIL
-
-
-10
-10
10
10
µA
µA
≦
≦
( 0V VIN VDD, All other pins not under test = 0V )
Output Leakage Current
IOZ
≦
≦
(Output Disable, 0V VIN VDDQ )
-
-
VOH
VOL
Output High Level Voltage ( IOUT = -2mA )
Output Low Level Voltage ( IOUT = 2mA )
2.4
-
-
V
V
0.4
Table 8. Capacitance
(VDD = 3.3V, f = 1MHz, TA = 25°C)
Parameter
Symbol
Min.
Max.
5.5
Unit
pF
CI
Input Capacitance
Input/Output Capacitance
3.5
5.5
7.5
CI/O
pF
Note: These parameters are periodically sampled and are not 100% tested.
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±
Table 9. D.C. Characteristics
(VDD = 3.3V 0.3V, TA = -40~85°C)
-6
Max.
-7
-5
Unit Note
Description/Test condition
Symbol
IDD1
Operating Current
RC ≥ tRC(min), Outputs Open, One bank active
Precharge Standby Current in power down mode
tCK = 15ns, CKE ≤ VIL(max)
3
200
3
160
3
140
3
t
IDD2P
Precharge Standby Current in power down mode
tCK = ∞, CKE ≤ VIL(max)
IDD2PS
3
3
3
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# ≥ VIH(min), CKE ≥ VIH
Input signals are changed every 2clks
Precharge Standby Current in non-power down mode
tCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH
Active Standby Current in non-power down mode
tCK = 15ns, CKE ≥ VIH(min), CS# ≥ VIH(min)
Input signals are changed every 2clks
Active Standby Current in non-power down mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞
Operating Current (Burst mode)
IDD2N
50
30
50
30
50
30
IDD2NS
IDD3N
IDD3NS
IDD4
mA
60
60
60
50
240
300
3
50
200
260
3
50
170
230
3
3, 4
3
tCK =tCK(min), Outputs Open, Multi-bank interleave
Refresh Current
IDD5
t
RC ≥ tRC(min)
Self Refresh Current
CKE ≤ 0.2V ; for other inputs VIH VDD - 0.2V, VIL ≤ 0.2V
IDD6
≧
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Table 10. Electrical Characteristics and Recommended A.C. Operating Conditions
±
(VDD = 3.3V 0.3V, TA = -40~85°C) (Note: 5~8)
-5
-6
-7
Unit Note
Symbol
A.C. Parameter
Min. Max. Min. Max. Min. Max.
tRC
Row cycle time (same bank)
55
15
-
-
60
18
-
-
63
21
-
-
tRCD
tRP
RAS# to CAS# delay (same bank)
Precharge to refresh / row activate
command (same bank)
15
10
40
-
-
18
12
42
-
-
21
14
42
-
-
ns
tRRD
tRAS
Row activate to row active delay
(different banks)
Row activate to precharge time
(same bank)
100K
100K
100K
Write recovery time
2
1
-
-
2
1
-
2
1
-
tWR
tCK
CAS# to CAS# Delay time
-
-
9
tCCD
CL* = 2
-
-
10
6
-
10
7
-
Clock cycle time
tCK
CL* = 3
5
-
-
-
tCH
tCL
Clock high time
Clock low time
2
-
2.5
2.5
-
-
2.5
2.5
-
-
ns
10
10
2
-
-
6
-
6.5
5.4
-
CL* = 2
CL* = 3
-
-
Access time from CLK
(positive edge)
tAC
-
5
-
-
5.4
-
-
tOH
tLZ
tHZ
tIS
Data output hold time
2
2.5
1
2.5
1
9
Data output low impedance
1
-
-
-
ns
Data output high impedance CL* = 3
Data/Address/Control Input set-up time
Data/Address/Control Input hold time
PowerDown Exit Setup Time
-
5
-
-
5.4
-
-
5.4
-
8
1.5
0.8
1.5
0.8
1.5
0.8
10
10
tIH
-
-
-
ns
ns
tCK
µs
ns
tIS+ CK
t
-
-
tIS+ CK
t
-
-
tIS+ CK
t
-
-
tPDE
tMRD
tREFI
tXSR
2
-
2
-
2
-
Mode Register Set Command Cycle Time
Refresh Interval Time
15.6
15.6
15.6
tRC+ IS
t
-
tRC+ IS
t
-
tRC+ IS
t
-
Exit Self-Refresh to any Command
*CL is CAS Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
≦
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width
3ns. VIL(Min) = -1.0V for pulse
≦
width
3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions
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Table 11. LVTTL Interface
Reference Level of Output Signals
1.4V / 1.4V
Output Load
Reference to the Under Output Load (B)
Input Signal Levels (VIH /VIL)
2.4V / 0.4V
1ns
Transition Time (Rise and Fall) of Input Signals
Reference Level of Input Signals
1.4V
1.4V
3.3V
50Ω
1.2KΩ
Output
Output
Z0=50Ω
870Ω
30pF
30pF
Figure 18.1 LVTTL D.C. Test Load (A)
Figure 18.2 LVTTL A.C. Test Load (B)
7. Transition times are measured between VIH and VIL. Transition (rise and fall) of input signals are in a fixed
slope (1 ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns, (tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT (tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns
should be added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when CKE= “L”, DQM= “H” and all input
signals are held "NOP" state.
2) Start clock and maintain stable condition for minimum 200 µs, then bring CKE= “H” and, it is
recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the
device.
* The Auto Refresh command can be issue before or after Mode Register Set command
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Timing Waveforms
Figure 19. AC Parameters for Write Timing
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tCH
tCL
tIS
tIS
Begin Auto
Precharge Bank A
Begin Auto
Precharge Bank B
tIH
CS#
RAS#
CAS#
WE#
BA0,1
A10
tIH
RAx
RBx
RBx
RAy
RAy
tIS
A0-A9,
A11
RAx
CAx
CBx
CAy
DQM
DQ
tRCD
tDAL
tIS
tRC
tWR
tIH
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
Write with
Activate
Command
Bank A
Write with
Activate
Auto Precharge Command
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank A
Auto Precharge
Command
Bank B
Command
Bank A
Bank B
Don’t Care
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Figure 20. AC Parameters for Read Timing
(Burst Length=2, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
CLK
CKE
tCH tCL
Begin Auto
Precharge Bank B
tIH
tIS
tIS
tIH
CS#
RAS#
CAS#
WE#
BA0,1
A10
tIH
RAx
RBx
RBx
RAy
RAy
tIS
A0-A9,
A11
RAx
CAx
tRRD
CBx
tRAS
tAC
tRC
DQM
DQ
tRCD
tRP
tHZ
tLZ
Hi-Z
Bx0
Bx1
Ax0
tOH
Ax1
tHZ
Read with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Don’t Care
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Figure 21. Auto Refresh
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
tRC
tRP
tRC
tRCD
DQM
DQ
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Precharge All
Command
Auto Refresh
Command
Auto Refresh
Command
Don’t Care
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AS4C4M32SA-7TCN
Figure 22. Power on Sequence and Auto Refresh
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High Level
Minimum for 2 Refresh Cycles are required
Is reguired
CS#
RAS#
CAS#
WE#
BA0,1
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
tMRD
Hi-Z
Precharge All
Command
Any
Command
1st Auto Refresh(*)
Command
2nd Auto Refresh(*)
Command
Inputs must be
Mode Register
Set Command
Stable for
200µs
Don’t Care
Note(*): The Auto Refresh command can be issue before or after Mode Register Set command
Confidential
-25/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 23. Self Refresh Entry & Exit Cycle
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
CLK
CKE
*Note 2
*Note 8
tXSR
*Note 5
*Note 1
*Note 3,4
tPDE
tIS
tIH
*Note 6
tIS
*Note 7
CS#
RAS#
CAS#
WE#
*Note 9
BA0,1
A10
A0-A9,
A11
DQM
DQ
Hi-Z
Hi-Z
Self Refresh Exit
Auto Refresh
Self Refresh Entry
Don’t Care
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for valid setup time and hold time.
7. CS# starts from high.
8. Minimum tXSR is required after CKE going high to complete SelfRefresh exit.
9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the
system uses burst refresh.
Confidential
-26/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 24. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
tHZ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Activate
Command
Bank A
Read
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Don’t Care
Confidential
-27/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 25. Clock Suspension During Burst Write (Using CKE)
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
Hi-Z
DAx0
Write
DAx1
DAx2
DAx3
Activate
Command
Bank A
Clock Suspend
3 Cycles
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Command
Bank A
Don’t Care
Confidential
-28/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 26. Power Down Mode and Clock Suspension
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
tIH tIS
tPDE
Valid
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
tHZ
Ax3
Hi-Z
Ax0
Ax1
Ax2
ACTIVE
STANDBY
PRECHARGE
STANDBY
Precharge
Command
Bank A
Activate
Command
Bank A
Power Down
Mode Exit
Read
Command
Bank A
Clock Suspension
Start
Clock Suspension
End
Any
Command
Power Down
Mode Exit
Power Down
Mode Entry
Power Down
Mode Entry
Don’t Care
Confidential
-29/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 27. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAw
RAw
RAz
RAz
A0-A9,
A11
CAw
CAx
CAy
CAz
DQM
DQ
Hi-Z
Aw0
Aw1
Aw2 Aw3
Read
Ax0
Ax1
Ay0
Ay1
Ay2
Ay3
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Command
Bank A
Don’t Care
Confidential
-30/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 28. Random Column Write (Page within same Bank)
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBw
RBw
RBz
RBz
A0-A9,
A11
CBw
CBx
CBy
CBz
DQM
DQ
Hi-Z
DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
DBz0 DBz1
Precharge
Command
Bank B
Activate
Command
Bank B
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Don’t Care
Confidential
-31/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 29. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBx
RAx
RAx
RBy
RBy
A0-A9,
A11
RBx
CBx
CAx
CBy
tAC
tRCD
tRP
DQM
DQ
Hi-Z
Bx0
Bx1
Bx2
Bx3
Bx4
Bx5
Bx6
Bx7
Ax0
Ax1
Ax2
Ax3
Ax4
Ax5
Ax6
Ax7
By0
Activate
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank A
Read
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Don’t Care
Confidential
-32/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 30. Random Row Write (Interleaving Banks)
(Burst Length=8)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RBx
RBx
RAy
RAy
A0-A9,
A11
RAx
CAx
CBx
CAy
tRCD
tWR*
tRP
tWR*
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3
Activate
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank B
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Don’t Care
*tWR>tWR (min.)
Confidential
-33/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 31. Read and Write Cycle
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
A0-A9,
A11
RAx
CAx
CAy
CAz
DQM
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
DAy0 DAy1
DAy3
Az0
Az1
Az3
The Write Data
The Read Data
is Masked with a
Two Clock
Activate
Command
Bank A
Read
Command
Bank A
Write
Command
Bank A
is Masked with a
Zero Clock
Read
Command
Bank A
Latency
Latency
Don’t Care
Confidential
-34/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 32. Interleaved Column Read Cycle
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
RBx
RBx
A0-A9,
A11
CAx
CBx
CBy
CBz
CAy
tRCD
DQM
DQ
tAC
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
By0
By1
Bz0
Bz1
Ay0
Ay1
Ay2
Ay3
Precharge
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Activate
Command
Bank B
Don’t Care
Confidential
-35/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 33. Interleaved Column Write Cycle
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAx
RBw
A0-A9,
A11
CAx RBw
CBw
CBx
CBy
CAy
CBz
tWR
tWR
tRCD
DQM
DQ
tRRD>tRRD (min)
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Hi-Z
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Activate
Precharge
Command
Bank B
Command
Bank A
Don’t Care
Confidential
-36/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 34. Auto Precharge after Read Burst
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBy
RBy
RAx
RBx
RBx
A0-A9,
A11
RAx
CAx
CBx
CAy
tRP
CBy
DQM
DQ
Hi-Z
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Bx2
Bx3
Ay0
Ay1
Ay2
Ay3
By0
By1
By2
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Read with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Don’t Care
Confidential
-37/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 35. Auto Precharge after Write Burst
(Burst Length=4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBy
RBy
RAx
RBx
RBx
A0-A9,
A11
RAx
CAx
CBx
CAy
CBy
tDAL
DQM
DQ
Hi-Z
DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3
DBy0 DBy1 DBy2 DBy3
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
Write with
Auto Precharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Activate
Command
Bank B
Don’t Care
Confidential
-38/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 36. Full Page Read Cycle
(Burst Length=Full Page, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBy
RBy
RAx
RBx
RBx
A0-A9,
A11
RAx
CAx
CBx
tRP
DQM
DQ
Hi-Z
Ax
Ax+1 Ax+2 Ax-2 Ax-1
Ax
Ax+1
Bx
Bx+1 Bx+2 Bx+3 Bx+4 Bx+5
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
The burst counter wraps
from the highest order
Burst Stop
Command
Don’t Care
page address back to zero
during this time interval
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Confidential
-39/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 37. Full Page Write Cycle
(Burst Length=Full Page)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBy
RBy
RAx
RBx
RBx
A0-A9,
A11
RAx
CAx
CBx
DQM
DQ
Data is ignored
Hi-Z
DAx
DAx+1 DAx+2 DAx+3 DAx-1
Activate
DAx
DAx+1
DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
Activate
Command
Bank B
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Burst Stop
Command
Full Page burst operation does not
Don’t Care
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address
Confidential
-40/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 38. Byte Read and Write Operation
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0, 1
A10
RAx
A0-A9,
A11
RAx
CAx
CAy
CAz
DQM m
DQM n
DQ M
Ax0
Ax1
Ax1
Ax2
Ax2
DAy1 Day2
Az1
Az1
Az2
Az2
Ax3
DAy0 DAy1
DAy3
Az0
Az3
DQ N
Upper Byte
is masked
Read
Command
Bank A
Activate
Command
Bank A
Read
Command
Bank A
Upper Byte
is masked
Lower Byte
is masked
Write
Command
Bank A
Lower Byte
is masked
Lower Byte
is masked
Don’t Care
Note : M represent DQ in the byte m; N represent DQ in the byte n.
Confidential
-41/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 39. Random Row Read (Interleaving Banks)
(Burst Length=4, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0, 1
A10
RBw
RBw
RAx
RAx
RBx
RBx
A0-A9,
A11
CAx
CBx
CAy
CBy
CBz
tRP
DQM
DQ
tRRD
tRCD
Hi-Z
Ax0
Ax1
Bx0
Ay0
Ay1
By0
By1
By2
By3
Bz0
Bz1
Bz2
Read
Command
Bank B
Activate
Command
Bank A
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Activate
Command
Bank B
Read
Read
Command
Bank A
Command
Bank A
Don’t Care
Confidential
-42/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 40. Full Page Random Column Read
(Burst Length=Full Page, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBw
RBw
RAx
RAx
RBx
RBx
A0-A9,
A11
CAx
CBx
CAy
CBy
CAz
CBz
tRP
DQM
DQ
tRRD
tRCD
Hi-Z
Ax0
Ax1
Bx0
Ay0
Ay1
By0
By1
Az0
Az1
Az2
Bz0
Bz1
Bz2
Read
Command
Bank B
Activate
Command
Bank A
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Activate
Command
Bank B
Read
Read
Command
Bank A
Command
Bank A
Don’t Care
Confidential
-43/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 41. Full Page Random Column Write
(Burst Length=Full Page)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
RBw
RBw
RAx
RAx
RBx
RBx
A0-A9,
A11
CAx
CBx
CAy
CBy
CAz
CBz
tWR
tRP
DQM
DQ
tRRD
tRCD
DAx0 DAx1 DBx0 DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2
Hi-Z
Write
Command
Bank B
Activate
Command
Bank A
Precharge
Command Bank B
(Precharge Temination)
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank B
Write
Write
Command
Bank A
Write Data
are masked
Command
Bank A
Don’t Care
Confidential
-44/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 42. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
CS#
RAS#
CAS#
WE#
BA0,1
A10
RAx
RAy
RAy
RAz
RAz
A0-A9,
A11
RAx
CAx
CAy
tWR
tRP
tRP
DQM
DQ
DAx0 DAx1
Ay0
Ay1
Ay2
Precharge Termination
of a Read Burst
Activate
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank A
Precharge Termination
of a Write Burst
Write Data are masked
Don’t Care
Confidential
-45/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
Figure 43. 86 Pin TSOP II Package Outline Drawing Information
86
44
θ°
L
L1
1
43
D
L
L1
e
y
B
S
Symbol
Dimension in inch
Dimension in mm
Min
－
Normal
－
Max
0.047
0.008
0.043
0.011
－
Min
－
Normal
－
Max
1.20
0.2
1.1
0.27
－
A
A1
A2
B
0.002
0.035
0.007
－
0.004
0.039
0.009
0.005
0.05
0.9
0.17
－
0.10
1
0.22
0.127
C
D
E
e
0.87
0.395
－
0.875
0.400
0.0197
0.88
0.405
－
22.09
10.03
－
22.22
10.16
0.50
22.35
10.29
－
HE
L
L1
0.455
0.016
－
0.463
0.020
0.0315
0.024
0.471
0.024
－
11.56
0.40
－
11.76
0.50
0.80
0.61
11.96
0.60
－
S
－
－
－
－
y
0.004
0.10
－
－
－
－
－
－
°
°
°
°
8
θ
0
8
0
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension: mm
Confidential
-46/47-
Rev.1.0 Sep.2015
AS4C4M32SA-6TIN
AS4C4M32SA-6TCN
AS4C4M32SA-7TCN
PART NUMBERING SYSTEM
4M32SA
C/I
6/7
T
N
AS4C
C=Commercial
(0°C - +70°C)
I=Industrial
6=166MHz
7=143MHz
Indicates Pb and
Halogen Free
128Mb=4Mx32
DRAM
T = TSOP II
A die version
(-40°C - +85°C)
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time
without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right
to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warranty to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties related to the
sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms
and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively
according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a
license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting
systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such
use and agrees to indemnify Alliance against all claims arising from such use.
Confidential
-47/47-
Rev.1.0 Sep.2015
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