AS4C64M8D1-5TIN [ALSC]
Fully synchronous operation;
| 型号： | AS4C64M8D1-5TIN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Fully synchronous operation |
| 文件： | 总64页 (文件大小：1754K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4C64M8D1
Revision History AS4C64M8D1 -
Revision Details
Date
Rev 1.0
Rev 2.0
Preliminary datasheet
Typing error data rate 800bps/pin to 400bps/pin page 1
February 2014
October 2014
Confidential
0
Rev.2.0
Oct. /2014
AS4C64M8D1
512M – (64M x 8 bit) DDR Synchronous DRAM (SDRAM)
Confidential
Features
(Rev. 2.0, Oct. /2014)
Overview
The 512Mb DDR SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 512
Mbits. It is internally configured as a quad 16M x 8-bit
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal, CK).
Fast clock rate: 200MHz
Differential Clock CK &
CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
CK
Data outputs occur at both rising edges of CK and
.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the
registration of a BankActivate command which is then
followed by a Read or Write command. The DDR
SDRAM provides programmable Read or Write burst
lengths of 2, 4, or 8. An auto precharge function may
be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use. In addition, The DDR SDRAM features
programmable DLL option. By having a programmable
mode register and extended mode register, the system
can choose the most suitable modes to maximize its
performance. These devices are well suited for
applications requiring high memory bandwidth, result in
a device particularly well suited to high performance
main memory and graphics applications.
Internal pipeline architecture
Four internal banks, 16M x 8-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Precharge & active power down
Operating temperature range: T = 0 ~ 70°C
A
±
= 2.5V 0.2V
DD & DDQ
Power supplies: V
V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
Package: 60-Ball, 8x13x1.2 mm (max) TFBGA
- All parts ROHS Compliant
Table 1. Ordering Information
Part Number
AS4C64M8D1-5TCN
AS4C64M8D1-5TIN
AS4C64M8D1-5BCN
AS4C64M8D1-5BIN
Clock Frequency
200MHz
Data Rate
Power Supply
Package
400Mbps/pin
400Mbps/pin
400Mbps/pin
400Mbps/pin
66pin TSOP II
66 pin TSOP II
60 ball TFBGA
60 ball TFBGA
VDD 2.5V, VDDQ 1.8V
VDD 2.5V, VDDQ 1.8V
VDD 2.5V, VDDQ 1.8V
VDD 2.5V, VDDQ 1.8V
200MHz
200MHz
200MHz
T: indicated 66 pin TSOP II B: indicates 60-ball 8 x 10 x 1.2mm (max) TFBGA package
C: indicates commercial temperature
I: indicates industrial temperature
N: indicates Pb and Halogen Free - ROHS Compliant
Table 2. Speed Grade Information
Speed Grade
Clock Frequency
CAS Latency
t
(ns)
t
(ns)
RCD
RP
DDR1-400
200 MHz
2.5
15
15
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Rev.2.0
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AS4C64M8D1
Figure 1. Pin Assignment (Top View)
Figure 1.1 Ball Assignment (Top View)
1
2
3
7
8
9
…
VSS
DQ7
VSSQ
NC
VDD
DQ0
VDDQ
NC
1
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSSQ
DQ7
VSS
VDD
DQ0
VDDQ
2
A
B
C
D
3
NC
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
DQ6
DQ5
DQ4
DQS
DM
DQ1
DQ2
DQ3
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
NC
NC
NC
NC
NC
4
DQ6
VDDQ
NC
DQ1
VSSQ
NC
5
6
NC
7
DQ5
VSSQ
NC
DQ2
VDDQ
NC
8
NC
E
F
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VREF
NC
DQ3
VSSQ
NC
DQ4
VDDQ
NC
G
CK
CK
WE
CAS
CS
A12
CKE
RAS
H
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
VDDQ
NC
A11
A8
A9
A7
A5
BA1
A0
BA0
A10
A1
J
K
L
NC
VDD
NC
A6
A2
NC
A4
VSS
VDD
A3
M
CK
WE
CAS
RAS
CS
CK
CKE
NC
NC
A12
A11
A9
BA0
BA1
A10/AP
A0
A8
A7
A1
A6
A2
A5
A3
A4
VDD
VSS
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AS4C64M8D1
Figure 2. Block Diagram
CK
DLL
CLOCK
BUFFER
CK
CKE
16M x 8
CELL ARRAY
(BANK #0)
CS
RAS
CAS
WE
CONTROL
SIGNAL
GENERATOR
Column Decoder
COMMAND
DECODER
16M x 8
CELL ARRAY
(BANK #1)
COLUMN
COUNTER
A10/AP
A0
MODE
REGISTER
Column Decoder
ADDRESS
BUFFER
A9
A11
A12
BA0
BA1
16M x 8
CELL ARRAY
(BANK #2)
REFRESH
COUNTER
Column Decoder
DATA
STROBE
BUFFER
DQS
DQ
Buffer
DQ0 ~ 7
16M x 8
CELL ARRAY
(BANK #3)
DM
Column Decoder
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AS4C64M8D1
Pin Descriptions
Table 2. Pin Details
Symbol
CK,
Type
Description
are differential clock inputs. All address and control
Input
Differential Clock: CK and
CK
CK
input signals are sampled on the crossing of the positive edge of CK and negative
edge of . Input and output data is referenced to the crossing of CK and (both
CK
directions of the crossing)
CK
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE
goes low synchronously with clock, the internal clock is suspended from the next clock
cycle and the state of output and burst address is frozen as long as the CKE remains
low. When all banks are in the idle state, deactivating the clock controls the entry to
the Power Down and Self Refresh modes.
BA0, BA1
A0-A12
Input
Input
Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
Address Inputs: A0-A12 are sampled during the BankActivate command (row
address A0-A12) and Read/Write command (column address A0-A9, A11 with A10
defining Auto Precharge).
Input
Input
Chip Select:
enables (sampled LOW) and disables (sampled HIGH) the
CS
command decoder. All commands are masked when
CS
is sampled HIGH.
CS
CS
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe: The
signal defines the operation commands in
RAS
signals and is latched at the positive edges of CK.
RAS
conjunction with the
and
WE
CAS
are asserted "LOW" and
When
and
is asserted "HIGH," either the
CAS
RAS
CS
BankActivate command or the Precharge command is selected by the
signal.
WE
is asserted "HIGH," the BankActivate command is selected and the
When the
WE
bank designated by BA is turned on to the active state. When the
is asserted
WE
"LOW," the Precharge command is selected and the bank designated by BA is
switched to the idle state after the precharge operation.
Input
Input
Column Address Strobe: The
signal defines the operation commands in
CAS
signals and is latched at the positive edges of CK.
is asserted "LOW," the column access is started
CAS
WE
conjunction with the
and
RAS
WE
CS
When
RAS
by asserting
is held "HIGH" and
"LOW." Then, the Read or Write command is selected by asserting
CAS
"HIGH" or “LOW”.
WE
Write Enable: The
signal defines the operation commands in conjunction with
WE
signals and is latched at the positive edges of CK. The
the
and
input
WE
RAS
CAS
is used to select the BankActivate or Precharge command and Read or Write
command.
DQS
DM
Input /
Output
Input
Data Strobe: Output with read data, input with write data. Edge--aligned with read
data, centered in write data. Used to capture write data.
Data Input Mask: Input data is masked when DM is sampled HIGH during a write
cycle.
DQ0 – DQ7 Input /
Data Bus: Data Input/output.
Output
VDD
VSS
Supply
Supply
±
Power Supply: 2.5V 0.2V
Ground
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AS4C64M8D1
VDDQ
VSSQ
VREF
NC
Supply
Supply
Supply
-
±
DQ Power: 2.5V 0.2V. Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
SSTL_2 reference Voltage
No Connect: These pins should be left unconnected.
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AS4C64M8D1
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CK. Table 3
shows the truth table for the operation commands.
Table 3. Truth Table (Note (1), (2))
Command
BankActivate
State
Idle(3)
Any
CKEn-1 CKEn DM BA0,1 A10 A0-9, 11-12
CS RAS CAS
WE
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
Row address
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
H
L
H
L
H
L
X
X
L
L
H
H
H
L
BankPrecharge
PrechargeAll
L
H
L
X
X
Any
L
L
Active(3)
Active(3)
Active(3)
Active(3)
Idle
H
H
H
H
L
L
Column
address
(A0 ~ A9)
Write
Write and AutoPrecharge
Read
H
L
L
L
Column
address
(A0 ~ A9)
L
H
H
L
Read and Autoprecharge
Mode Register Set
Extended MRS
No-Operation
H
L
OP code
L
Idle
OP code
L
L
L
Any
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
L
H
H
X
L
H
L
Active(4)
Burst Stop
Device Deselect
AutoRefresh
Any
X
H
H
X
H
X
H
X
H
X
V
X
H
X
X
Idle
SelfRefresh Entry
SelfRefresh Exit
Idle
L
L
Idle
H
X
H
X
H
X
H
X
V
X
H
X
X
X
H
X
H
X
H
X
V
X
H
X
X
(SelfRefresh)
Precharge Power Down Mode
Entry
Idle
H
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Precharge Power Down Mode
Exit
Any
(PowerDown)
Active Power Down Mode Entry
Active Power Down Mode Exit
Active
H
L
Any
H
(PowerDown)
Data Input Mask Disable
Data Input Mask Enable
Active
Active
H
H
X
X
L
X
X
X
X
X
X
H
Note: 1. V=Valid data, X=Don't Care, L=Low level, H=High level
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BA signal.
4. Device state is 2, 4, and 8 burst operation.
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AS4C64M8D1
Mode Register Set (MRS)
The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs CAS
Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The default
value of the Mode Register is not defined; therefore the Mode Register must be written by the user. Values
stored in the register will be retained until the register is reprogrammed. The Mode Register is written by
asserting Low on
,
,
,
, BA1 and BA0 (the device should have all banks idle with no bursts in
CS RAS CAS WE
progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A12
and BA0, BA1 in the same cycle in which and are asserted Low is written into the Mode
,
,
CS RAS CAS
WE
Register. A minimum of two clock cycles, tMRD, are required to complete the write operation in the Mode
Register. The Mode Register is divided into various fields depending on functionality. The Burst Length uses
A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0
should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should not
be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for specific
codes for various burst lengths, burst types and CAS latencies.
Table 4. Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Field
Mode Register
0
0
RFU must be set to “0”
T.M.
CAS Latency
Burst Length
A8 A7 Test Mode
A6 A5 A4 CAS Latency A3 Burst Type A2 A1 A0 Burst Length
0
1
0 Normal mode
DLL Reset
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
0
4
3
8
BA0 Mode
Reserved
Reserved
2.5
Reserved
Reserved
Reserved
Reserved
0
1
MRS
EMRS
Reserved
Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4,
8.
Table 5. Burst Length
A2
0
A1
0
A0
0
Burst Length
Reserved
2
0
0
1
0
1
0
4
0
1
1
8
1
0
0
Reserved
Reserved
Reserved
Reserved
1
0
1
1
1
0
1
1
1
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AS4C64M8D1
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential
Mode and Interleave Mode support burst length of 2, 4 and 8.
Table 6. Addressing Mode
A3
0
Addressing Mode
Sequential
1
Interleave
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 7. Burst Address ordering
Start Address
Burst Length
Sequential
Interleave
A2
X
X
X
X
X
X
0
A1
X
X
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
2
4
8
1
0
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
CAS Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first read data.
The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value
satisfying the following formula must be programmed into this field.
tCAC(min) CAS Latency X tCK
Table 8. CAS Latency
A6
0
A5
0
A4
0
CAS Latency
Reserved
Reserved
2 clocks
0
0
1
0
1
0
0
1
1
3 clocks
1
0
0
Reserved
Reserved
2.5 clocks
Reserved
1
0
1
1
1
0
1
1
1
Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
Table 9. Test Mode
A8
0
A7
0
Test Mode
Normal mode
DLL Reset
1
0
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AS4C64M8D1
( BA0, BA1)
Table 10. MRS/EMRS
BA1
RFU
RFU
BA0
0
A12 ~ A0
MRS Cycle
1
Extended Functions (EMRS)
Extended Mode Register Set (EMRS)
The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver
strength. The default value of the extended mode register is not defined, therefore must be written after power
up for proper operation. The Extended Mode Register is written by asserting Low on CS
BA1 and BA0 (the device should have all banks idle with no bursts in progress prior to writing into the mode
register, and CKE should be High). The state of A0 ~ A12, BA0 and BA1 is written in the mode register in the
same cycle asCS
RAS CAS, and WE going low. The DDR SDRAM should be in all bank precharge with
RAS CAS
WE
, , , ,
,
,
CKE already high prior to writing into the extended mode register. A1 is used for setting driver strength to normal,
or weak. Two clock cycles are required to complete the write operation in the extended mode register. The
mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used
for EMRS. Refer to the table for specific codes.
Table 11. Extended Mode Register Bitmap
BA1 BA0 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0
1
RFU must be set to “0”
DS0 DLL Extend Mode Register
BA0
0
Mode
MRS
A1
0
Drive Strength
Full
A0
0
DLL
Enable
Disable
1
EMRS
1
Weak
1
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AS4C64M8D1
Table 12. Absolute Maximum Rating
Symbol
VIN, VOUT
VDD, VDDQ
TA
Item
Rating
Unit
V
Input, Output Voltage
Power Supply Voltage
Ambient Temperature
Storage Temperature
Soldering Temperature
Power Dissipation
- 0.5~ VDDQ + 0.5
- 1~3.6
0~70
- 55~150
260
V
C
°
TSTG
C
°
C
°
TSOLDER
PD
1
W
IOS
Short Circuit Output Current
50
mA
Note1: Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
Note2: These voltages are relative to Vss
Table 13. Recommended D.C. Operating Conditions
(TA = 0 ~ 70 C)
Min.
Symbol
VDD
Parameter
Power Supply Voltage
Max.
2.7
Unit
V
2.3
VDDQ
VREF
Power Supply Voltage (for I/O Buffer)
Input Reference Voltage
2.3
2.7
V
0.49 x VDDQ
VREF + 0.15
-0.3
0.51 x VDDQ
VDDQ + 0.3
VREF – 0.15
V
VIH (DC) Input High Voltage (DC)
V
Input Low Voltage (DC)
Termination Voltage
VIL (DC)
V
VTT
VREF - 0.04
-0.3
VREF + 0.04
VDDQ + 0.3
V
V
VIN (DC)
Input Voltage Level, CK and
inputs
CK
VID (DC)
0.36
VDDQ + 0.6
V
Input Different Voltage, CK and
Input leakage current
inputs
CK
II
-2
-5
2
5
-
A
A
IOZ
IOH
IOL
Output leakage current
Output High current (VOUT = 1.95V)
Output Low current (VOUT = 0.35V)
-16.2
16.2
mA
mA
-
Note : All voltages are referenced to VSS.
Table 14. Capacitance
(VDD = 2.5V, f = 1MHz, TA = 25 C)
Symbol
Parameter
Min.
Max.
Unit
pF
CIN1
Input Capacitance (CK,
)
2
3
CK
CIN2
CI/O
Input Capacitance (All other input-only pins)
DQ, DQS, DM Input/Output Capacitance
2
4
3
5
pF
pF
Note: These parameters are guaranteed by design, periodically sampled and are not 100% tested
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AS4C64M8D1
Table 15. D.C. Characteristics
(VDD = 2.5V 0.2V, TA = 0 ~ 70 C)
-5
Parameter & Test Condition
Symbol
Unit
Max.
OPERATING CURRENT:
One bank; Active-Precharge; t =t (min); t =t (min); DQ,DM
and DQS inputs changing once per clock cycle; Address and control
inputs changing once every two clock cycles.
RC RC
CK CK
IDD0
80
mA
OPERATING CURRENT:
IDD1
90
5
mA
mA
One bank; BL=4; reads - Refer to the following page for detailed test
conditions
PRECHARGE POWER-DOWN STANDBY CURRENT:
IDD2P
All banks idle; power-down mode; t =t (min); CKE = LOW
CK CK
PRECHARGE FLOATING STANDBY CURRENT:
CS = HIGH; all banks idle; CKE = HIGH; t =t (min); address and
CK CK
IDD2F
35
mA
other control inputs changing once per clock cycle; V = V
for
IN
REF
DQ, DQS and DM
PRECHARGE QUIET STANDBY CURRENT:
CS =HIGH; all banks idle; CKE =HIGH; t =t (min) address and
CK CK
IDD2Q
IDD3P
IDD3N
35
20
65
mA
mA
mA
other control inputs stable at ≥ V (min) or ≤ V (max); V = V
REF
IH
IL
IN
for DQ, DQS and DM
ACTIVE POWER-DOWN STANDBY CURRENT : one bank active;
power-down mode; CKE=LOW; t =t (min)
CK CK
ACTIVE STANDBY CURRENT :
=HIGH;CKE=HIGH; one bank
CS
active ; t =t (max);t =t (min);Address and control inputs
RC RC
CK CK
changing once per clock cycle; DQ,DQS,and DM inputs changing
twice per clock cycle
OPERATING CURRENT BURST READ : BL=2; READS;
Continuous burst; one bank active; Address and control inputs
IDD4R
IDD4W
130
130
mA
mA
changing once per clock cycle; t =t (min); lout=0mA;50% of data
CK CK
changing on every transfer
OPERATING CURRENT BURST Write : BL=2; WRITES;
Continuous Burst ;one bank active; address and control inputs
changing once per clock cycle; t =t (min); DQ,DQS,and DM
CK CK
changing twice per clock cycle; 50% of data changing on every
transfer
AUTO REFRESH CURRENT : t =t
(min); t =t (min)
IDD5
IDD6
140
6
mA
mA
RC RFC
CK CK
≦
SELF REFRESH CURRENT: Self Refresh Mode ; CKE
0.2V;t =t (min)
CK CK
BURST OPERATING CURRENT 4 bank operation:
Four bank interleaving READs; BL=4;with Auto Precharge;
=t (min); t =t (min); Address and control inputs change only
IDD7
210
mA
t
RC RC
CK CK
during Active, READ , or WRITE command
Confidential
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Rev.2.0
Oct. /2014
AS4C64M8D1
Table 16. Electrical Characteristics and Recommended A.C.Operating Condition
(VDD = 2.5V ± 0.2V, TA = 0 ~ 70 C)
-5
Symbol
Parameter
Unit Note
Min.
7.5
6
Max.
12
CL = 2
CL = 2.5
CL = 3
ns
ns
ns
tCK
tCK
tCK
Clock cycle time
12
5
12
tCH
tCL
Clock high level width
Clock low level width
0.45
0.45
0.55
0.55
tCLMIN or
tCHMIN
tHP
Clock half period
-
ns
2
tHZ
tLZ
Data-out-high impedance time from CK,
Data-out-low impedance time from CK,
-
0.7
0.7
0.6
0.7
ns
ns
ns
ns
3
3
CK
CK
-0.7
-0.6
-0.7
tDQSCK DQS-out access time from CK,
CK
tAC
Output access time from CK,
CK
tDQSQ
tRPRE
tRPST
tDQSS
DQS-DQ Skew
Read preamble
Read postamble
CK to valid DQS-in
-
0.9
0.4
0.72
0
0.4
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
s
tCK
ns
ns
ns
ns
ns
tCK
tCK
1.1
0.6
1.25
tWPRES DQS-in setup time
-
4
5
tWPRE
tWPST
tDQSH
tDQSL
tIS
DQS Write preamble
0.25
0.4
0.35
0.35
0.7
0.7
0.4
0.4
tHP - tQHS
55
-
DQS write postamble
0.6
DQS in high level pulse width
DQS in low level pulse width
-
-
Address and Control input setup time
Address and Control input hold time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
DQ/DQS output hold time from DQS
Row cycle time
-
6
6
tIH
-
tDS
-
tDH
-
tQH
-
tRC
-
tRFC
tRAS
tRCD
tRP
Refresh row cycle time
70
-
Row active time
40
70K
Active to Read or Write delay
Row precharge time
15
-
15
-
tRRD
tWR
Row active to Row active delay
Write recovery time
10
-
15
-
tWTR
tMRD
tREFI
tXSRD
tXSNR
tDAL
tDIPW
tIPW
tQHS
tDSS
tDSH
Internal Write to Read Command Delay
Mode register set cycle time
Average Periodic Refresh interval
Self refresh exit to read command delay
2
-
10
-
-
7.8
7
200
75
-
Self refresh exit to non-read command delay
-
Auto Precharge write recovery + precharge time tWR+tRP
-
DQ and DM input pulse width
Control and Address input pulse width
Data Hold Skew Factor
1.75
2.2
-
-
-
0.5
-
DQS falling edge to CK setup time
DQS falling edge hold time from CK
0.2
0.2
-
Confidential
12
Rev.2.0
Oct. /2014
AS4C64M8D1
Table 17. Recommended A.C. Operating Conditions
(VDD = 2.5V ± 0.2V, TA = 0 ~ 70 C)
Symbol
Parameter
Min.
Max.
Unit
V
VIH (AC) Input High Voltage (AC)
VIL (AC) Input Low Voltage (AC)
VREF + 0.31
-
-
VREF – 0.31
V
VID (AC)
VIX (AC)
V
Input Different Voltage, CK and
inputs
0.7
VDDQ + 0.6
CK
V
Input Crossing Point Voltage, CK and
inputs
0.5 x VDDQ-0.2
0.5 x VDDQ+0.2
CK
Note:
1) Enables on-chip refresh and address counters.
2) Min(tCL, tCH) refers to the smaller of the actual clock low time and actual clock high time as provided to the
device.
3) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters
are not referenced to a specific voltage level, but specify when the device output is no longer driving(HZ), or
begins driving(LZ).
4) The specific requirement is that DQS be valid (High, Low, or at some point on a valid transition) on or before
this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of
the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to
logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to
LOW at this time, depending on tDQSS
.
5) The maximum limit for this parameter is not a device limit. The device will operate with a greater value for
this parameter, but system performance (bus turnaround) will degrade accordingly.
≧
1.0V/ns.
6) For command/address and CK &
slew rate
CK
7) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
8) Power-up sequence is described in Note 10
9) A.C. Test Conditions
Table 18. SSTL _2 Interface
Reference Level of Output Signals (VREF
)
0.5 x VDDQ
Reference to the Test Load
VREF+0.31 V / VREF-0.31 V
1 V/ns
Output Load
Input Signal Levels
Input Signals Slew Rate
Reference Level of Input Signals
0.5 x VDDQ
Confidential
13
Rev.2.0
Oct . /2014
AS4C64M8D1
Figure 3. SSTL_2 A.C. Test Load
0.5 * VDDQ
50Ω
DQ, DQS
Z0=50Ω
30pF
10) Power up Sequence
Power up must be performed in the following sequence.
1) Apply power to VDD before or at the same time as VDDQ, VTT and VREF when all input signals are held
"NOP" state and maintain CKE “LOW”.
2) Start clock and maintain stable condition for minimum 200s.
3) Issue a “NOP” command and keep CKE “HIGH”
4) Issue a “Precharge All” command.
5) Issue EMRS – enable DLL.
6) Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL).
7) Precharge all banks of the device.
8) Issue two or more Auto Refresh commands.
9) Issue MRS – with A8 to low to initialize the mode register.
Confidential
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Rev.2.0
Oct. /2014
AS4C64M8D1
Timing Waveforms
Figure 4. Activating a Specific Row in a Specific Bank
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
RA
BA
Address
BA0,1
RA=Row Address
BA=Bank Address
Don’t Care
Confidential
15
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 5. tRCD and tRRD Definition
CK
CK
RD/WR
COMMAND
ACT
Row
NOP
NOP
NOP
NOP
NOP
ACT
Row
Col
Address
Bank A
Bank B
Bank B
BA0,BA1
tRRD
tRCD
Don’t Care
Figure 6. READ Command
CK
CK
CKE
HIGH
CS
RAS
CAS
WE
CA
Address
A10
EN AP
DIS AP
BA
BA0,1
CA=Column Address
BA=Bank Address
EN AP=Enable Autoprecharge
DIS AP=Disable Autoprecharge
Don’t Care
Confidential
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Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 7. Read Burst Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
Bank A,
Col n
CL=2
DQS
DQ
DO
n
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order
following DO n
Don’t Care
Read Burst Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
Bank A,
Col n
CL=2.5
DQS
DQ
DO
n
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Oct /2014
Confidential
17
Rev.2.0
AS4C64M8D1
Read Burst Required CAS Latencies (CL=3)
CK
CK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
Bank A,
Col n
CL=3
DQS
DQ
DO
n
DO n=Data Out from column n
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order
following DO n
Don’t Care
Confidential
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Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 8. Consecutive Read Bursts Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
Confidential
19
Rev.2.0
Oct. /2014
AS4C64M8D1
Consecutive Read Bursts Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2.5
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
Confidential
20
Rev.2.0
Oct. /2014
AS4C64M8D1
Consecutive Read Bursts Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
READ
NOP
NOP
NOP
Bank,
Col n
Bank,
Col o
CL=3
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)
3 subsequent elements of Data Out appear in the programmed order following DO n
3 (or 7) subsequent elements of Data Out appear in the programmed order following DO o
Read commands shown must be to the same device
Don’t Care
Confidential
21
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 9. Non-Consecutive Read Bursts Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
Non-Consecutive Read Bursts Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
READ
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
CL=2.5
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
Oct. /2014
Confidential
22
Rev.2.0
AS4C64M8D1
Non-Consecutive Read Bursts Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
NOP
NOP
READ
NOP
NOP
Bank,
Col n
Bank,
Col o
CL=3
DQS
DQ
DO
n
DO
o
DO n (or o)=Data Out from column n (or column o)
Burst Length=4
3 subsequent elements of Data Out appear in the programmed order following DO n
(and following DO o)
Don’t Care
Confidential
23
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 10. Random Read Accesses Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
NOP
NOP
Bank,
Col o
Bank,
Col p
Bank,
Col q
Bank,
Col n
CL=2
DQS
DQ
DO
q
DO
n'
DO
o
DO
o'
DO
n
DO
p
DO
p'
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
Confidential
24
Rev.2.0
Oct. /2014
AS4C64M8D1
Random Read Accesses Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
NOP
NOP
Bank,
Col o
Bank,
Col p
Bank,
Col q
Bank,
Col n
CL=2.5
DQS
DQ
DO
n'
DO
o
DO
o'
DO
n
DO
p
DO
p'
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
Random Read Accesses Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
READ
READ
READ
NOP
NOP
Bank,
Col o
Bank,
Col q
Bank,
Col n
Bank,
Col p
CL=3
DQS
DQ
DO
n'
DO
o
DO
o'
DO
n
DO
p
DO n, etc. =Data Out from column n, etc.
n', etc. =the next Data Out following DO n, etc. according to the programmed burst order
Burst Length=2,4 or 8 in cases shown. If burst of 4 or 8, the burst is interrupted
Reads are to active rows in any banks
Don’t Care
Oct. /2014
Confidential
25
Rev.2.0
AS4C64M8D1
Figure 11. Terminating a Read Burst Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
BST
NOP
NOP
NOP
Bank A,
Col n
CL=2
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Terminating a Read Burst Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
BST
NOP
NOP
NOP
Bank A,
Col n
CL=2.5
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Oct. /2014
Confidential
26
Rev.2.0
AS4C64M8D1
Terminating a Read Burst Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
BST
NOP
NOP
NOP
Bank A,
Col n
CL=3
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are bursts of 8 terminated after 4 data elements
3 subsequent elements of Data Out appear in the programmed order following DO n
Don’t Care
Confidential
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Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 12. Read to Write Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
WRITE
READ
BST
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
tDQSS
min
CL=2
DQS
DQ
DO
n
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
Confidential
28
Rev.2.0
Oct. /2014
AS4C64M8D1
Read to Write Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
WRITE
READ
BST
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
ADDRESS
CL=2.5
tDQSS
min
DQS
DQ
DO
n
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
Confidential
29
Rev.2.0
Oct. /2014
AS4C64M8D1
Read to Write Required CAS Latencies (CL=3)
CK
CK
COMMAND
WRITE
READ
BST
NOP
NOP
NOP
Bank,
Col o
Bank,
Col n
ADDRESS
tDQSS
min
CL=3
DQS
DQ
DO
n
DI
o
DM
DO n (or o)= Data Out from column n (or column o)
Burst Length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the BST
command shown can be NOP)
1 subsequent element of Data Out appears in the programmed order following DO n
Data in elements are applied following DI o in the programmed order
Don’t Care
Confidential
30
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 13. Read to Precharge Required CAS Latencies (CL=2)
CK
CK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
tRP
Bank A,
Col n
Bank
(a or all)
Bank A,
Row
CL=2
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
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Rev.2.0
Oct. /2014
AS4C64M8D1
Read to Precharge Required CAS Latencies (CL=2.5)
CK
CK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
tRP
Bank
(a or all)
Bank A,
Col n
Bank A,
Row
CL=2.5
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
32
Rev.2.0
Oct. /2014
AS4C64M8D1
Read to Precharge Required CAS Latencies (CL=3)
CK
CK
COMMAND
ADDRESS
READ
NOP
PRE
NOP
NOP
ACT
tRP
Bank A,
Col n
Bank
(a or all)
Bank A,
Row
CL=3
DQS
DQ
DO
n
DO n = Data Out from column n
Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8
3 subsequent elements of Data Out appear in the programmed order
following DO n
Precharge may be applied at (BL/2) tCK after the READ command
Note that Precharge may not be issued before tRAS ns after the ACTIVE
command for applicable banks
The Active command may be applied if tRC has been met
Don’t Care
Confidential
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Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 14. Write Command
CK
CK
CKE
CS
HIGH
RAS
CAS
WE
CA
Address
EN AP
DIS AP
A10
BA
BA0,1
CA=Column Address
BA=Bank Address
EN AP=Enable Autoprecharge
DIS AP=Disable Autoprecharge
Don’t Care
Confidential
34
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 15. Write Max DQSS
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
Bank A,
Col n
tDQSS
max
DQS
DQ
DI
n
DM
DI n = Data In for column n
3 subsequent elements of Data In are applied in the programmed
order following DI n
A non-interrupted burst of 4 is shown
A10 is LOW with the WRITE command (AUTO PRECHARGE
disabled)
Don’t Care
Confidential
35
Rev.2.0
Oct /2014
AS4C64M8D1
Figure 16. Write Min DQSS
T4
T0
T1
T2
T3
T5
T6
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
Bank A,
Col n
tDQSS
min
DQS
DQ
DI
n
DM
DI n = Data In for column n
3 subsequent elements of Data In are applied in the programmed
order following DI n
A non-interrupted burst of 4 is shown
A10 is LOW with the WRITE command (AUTO PRECHARGE
disabled)
Don’t Care
Confidential
36
Rev.2.0
Oct /2014
AS4C64M8D1
Figure 17. Write Burst Nom, Min, and Max tDQSS
T4
T8
T9
T10
T11
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
NOP
NOP
Bank ,
Col n
tDQSS (nom)
DQS
DQ
DI
n
DM
tDQSS (min)
DQS
DQ
DI
n
DM
tDQSS (max)
DQS
DI
n
DQ
DM
DI n = Data In for column n
3 subsequent elements of Data are applied in the programmed order following DI n
A non-interrupted burst of 4 is shown
A10 is LOW with the WRITE command (AUTO PRECHARGE disabled)
Don’t Care
Confidential
37
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 18. Write to Write Max tDQSS
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
WRITE
NOP
NOP
NOP
NOP
Bank ,
Col o
Bank ,
Col n
tDQSS (max)
DQS
DQ
DI
n
DI
o
DM
DI n , etc. = Data In for column n,etc.
3 subsequent elements of Data In are applied in the programmed order following DI n
3 subsequent elements of Data In are applied in the programmed order following DI o
Non-interrupted bursts of 4 are shown
Don’t Care
Confidential
38
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 19. Write to Write Max tDQSS, Non Consecutive
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
WRITE
NOP
NOP
NOP
NOP
Bank
Col n
Bank
Col o
tDQSS (max)
DQS
DQ
DI
n
DI
o
DM
DI n, etc. = Data In for column n, etc.
3 subsequent elements of Data In are applied in the programmed order following DI n
3 subsequent elements of Data In are applied in the programmed order following DI o
Non-interrupted bursts of 4 are shown
Don’t Care
Confidential
39
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 20. Random Write Cycles Max tDQSS
T8
T9
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
Bank
Col r
Bank
Col n
Bank
Col o
Bank
Col p
Bank
Col q
tDQSS (max)
DQS
DQ
DI
n
DI
n'
DI
o
DI
o'
DI
p'
DI
p
DI
q'
DI
q
DM
DI n, etc. = Data In for column n, etc.
n', etc. = the next Data In following DI n, etc. according to the programmed burst order
Programmed Burst Length 2, 4, or 8 in cases shown
If burst of 4 or 8, the burst would be truncated
Each WRITE command may be to any bank and may be to the same or different devices
Don’t Care
Confidential
40
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 21. Write to Read Max tDQSS Non Interrupting
T12
T8
T9
T10 T11
NOP
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
WRITE
READ
NOP
NOP
NOP
NOP
tWTR
Bank
Col o
Bank
Col n
ADDRESS
CL=3
tDQSS (max)
DQS
DQ
DI
n
DM
DI n, etc. = Data In for column n, etc.
1 subsequent elements of Data In are applied in the programmed order following DI n
A non-interrupted burst of 2 is shown
tWTR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
Don’t Care
Confidential
41
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 22. Write to Read Max tDQSS Interrupting
T4
T8
T9
T10
T11
T12
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
READ
NOP
NOP
NOP
NOP
tWTR
Bank
Col o
Bank
Col n
CL=3
tDQSS (max)
DQS
DQ
DI
n
DM
DI n, etc. = Data In for column n, etc.
1 subsequent elements of Data In are applied in the programmed order following DI n
An interrupted burst of 8 is shown, 2 data elements are written
tWTR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
Don’t Care
Confidential
42
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 23. Write to Read Max tDQSS, ODD Number of Data, Interrupting
T8
T9
T10
T11
T12
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
WRITE
READ
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
tWTR
Bank
Col o
Bank
Col n
CL=3
tDQSS (max)
DQS
DQ
DI
n
DM
DI n = Data In for column n
An interrupted burst of 8 is shown, 1 data elements are written
tWTR is referenced from the first positive CK edge after the last Data In Pair (not the last desired
Data In element)
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
The READ and WRITE commands are to the same devices but not necessarily to the same bank
Don’t Care
Confidential
43
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 24. Write to Precharge Max tDQSS, NON- Interrupting
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
PRE
NOP
tWR
Bank a,
Col n
Bank
(a or al)
tRP
tDQSS (max)
DQS
DQ
DI
n
DM
DI n = Data In for column n
1 subsequent elements of Data In are applied in the programmed order following DI n
A non-interrupted burst of 2 is shown
tWR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
Don’t Care
Confidential
44
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 25. Write to Precharge Max tDQSS, Interrupting
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
PRE
NOP
NOP
NOP
tWR
Bank a,
Col n
Bank
(a or all)
tRP
tDQSS (max)
*2
DQS
DQ
DI
n
DM
*1
*1
*1
*1
DI n = Data In for column n
An interrupted burst of 4 or 8 is shown, 2 data elements are written
tWR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
Don’t Care
Confidential
45
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 26. Write to Precharge Max tDQSS ODD Number of Data Interrupting
T8
T9
T10
T11
T4
T0
T1
T2
T3
T5
T6
T7
CK
CK
COMMAND
ADDRESS
WRITE
NOP
NOP
NOP
NOP
PRE
tWR
Bank a,
Col n
Bank
(a or all)
tRP
tDQSS (max)
*2
DQS
DQ
DI
n
DM
*1
*1
*1
*1
DI n = Data In for column n
An interrupted burst of 4 or 8 is shown, 1 data element is written
tWR is referenced from the first positive CK edge after the last Data In Pair
A10 is LOW with the WRITE command (AUTO PRECHARGE is disabled)
*1 = can be don't care for programmed burst length of 4
*2 = for programmed burst length of 4, DQS becomes don't care at this point
Don’t Care
Confidential
46
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 27. Precharge Command
CK
CK
CKE
CS
HIGH
RAS
CAS
WE
A0-A9,
A11,A12
ALL BANKS
A10
ONE BANK
BA
BA0,1
BA= Bank Address (if A10 is
LOW, otherwise don't care)
Don’t Care
Confidential
47
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 28. Power-Down
Tn+3 Tn+4 Tn+5 Tn+6
T4
T0
T1
T2
T3
Tn Tn+1 Tn+2
CK
CK
tIS
tIS
CKE
VALID
VALID
COMMAND
NOP
NOP
Exit power-down
mode
Enter power-down
mode
No column access
in progress
Don’t Care
Figure 29. Clock Frequency Change in Precharge
Ty+1
Ty+3
Ty+4
T0
T1
T2
T4
Tx
Tx+1
Ty
Ty+2
Tz
CK
CK
DLL
RESET
NOP
NOP
NOP
NOP
NOP
Valid
CMD
CKE
tIS
Frequency Change
Occurs here
tRP
Stable new clock
Before power down
exit
Minmum 2 clocks
Required before
Changing frequency
200 Clocks
Confidential
48
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 30. Data input (Write) Timing
tDQSH
tDQSL
DQS
DQ
tDS
DI
n
tDH
tDS
DM
tDH
DI n = Data In for column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed order
following DI n
Don’t Care
Figure 31. Data Output (Read) Timing
tCL
tCH
CK
CK
DQS
DQ
tDQSQ
max
tDQSQ
max
tQH
tQH
Burst Length = 4 in the case shown
Confidential
49
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 32. Initialize and Mode Register Sets
VDD
VDDQ
tVDT>=0
VTT
(system*)
VREF
tCK
tCH tCL
CK
CK
tIS tIH
CKE
tIS tIH
MRS
ACT
AR
AR
MRS
PRE
PRE
EMRS
NOP
COMMAND
DM
tIS tIH
A0-A9,
A11,A12
CODE
CODE
CODE
CODE
CODE
RA
RA
BA
ALL BANKS
tIS tIH
ALL BANKS
A10
CODE
tIS tIH
t
IS tIH
tIS tIH
BA0=H
BA1=L
BA0=L
BA1=L
BA0=L
BA1=L
BA0,BA1
High-Z
DQS
DQ
High-Z
**tMRD
**tMRD
tRP
200 cycles of CK**
tRFC
tRFC
**tMRD
T=200µs
Extended mode
Register set
Load Mode
Register,
(with A8=L)
Power-up:
VDD and
CLK stable
Load Mode
Register,
Reset DLL (with A8=H)
*=VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up
**=tMRD is required before any command can be applied, and 200 cycles of CK are required before any executable command can be applied
The two Auto Refresh commands may be moved to follow the first MRS but precede the second PRECHARGE ALL command
Don’t Care
Confidential
50
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 33. Power Down Mode
tCK
tCH
tCL
CK
CK
tIS tIH
tIS
tIS
CKE
tIS tIH
VALID*
VALID
VALID
COMMAND
NOP
NOP
tIS tIH
VALID
ADDR
DQS
DQ
DM
Enter
power-down mode
Exit
power-down mode
No column accesses are allowed to be in progress at the time Power-Down is entered
*=If this command is a PRECHARGE ALL (or if the device is already in the idle state) then the Power-Down
mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already active)
then the Power-Down mode shown is active Power Down.
Don’t Care
Confidential
51
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 34. Auto Refresh Mode
tCK
tCH tCL
CK
CK
tIS
tIH
CKE
VALID
VALID
tIS tIH
NOP
ACT
RA
AR
NOP
AR
NOP
NOP
PRE
NOP
NOP
COMMAND
A0-A9
A11,A12
A10
RA
RA
BA
ALL BANKS
ONE BANKS
tIS tIH
*Bank(s)
BA0,BA1
DQS
DQ
DM
tRFC
tRP
tRFC
* = “Don't Care”, if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks)
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other valid commands may be possible after tRFC
DM, DQ and DQS signals are all “Don't Care”/High-Z for operations shown
Don’t Care
Confidential
52
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 35. Self Refresh Mode
tCK
Clock must be stable before
Exiting Self Refresh mode
tCH
tCL
CK
CK
tIS tIH
tIS
tIS
CKE
tIS tIH
NOP
VALID
COMMAND
NOP
AR
tIS tIH
VALID
ADDR
DQS
DQ
DM
tXSNR/
tXSRD**
Exit Self Refresh
mode
tRP*
Enter Self Refresh
mode
* = Device must be in the “All banks idle” state prior to entering Self Refresh mode
** = tXSNR is required before any non-READ command can be applied, and tXSRD (200 cycles of CK) is
required before a READ command can be applied.
Don’t Care
Confidential
53
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 36. Read without Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS
tIH
CKE
VALID
NOP
VALID
NOP
VALID
NOP
tIS tIH
NOP
NOP
ACT
RA
NOP
READ
PRE
NOP
COMMAND
A0-A9
tIS tIH
Col n
RA
RA
A11,A12
A10
tIS tIH
ALL BANKS
ONE BANKS
DIS AP
tIS tIH
Bank X
Bank X
*Bank X
BA0,BA1
CL=3
tRP
DM
Case 1:
tAC/tDQSCK=min
tDQSCK
tRPST
min
tRPRE
DQS
DQ
tLZ
min
DO
n
tLZ
tAC
min
min
Case 2:
tAC/tDQSCK=max
tDQSCK
tRPST
max
tRPRE
DQS
tLZ
tHZ
max
max
DO
DQ
n
tLZ
tAC
max
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP = Disable Autoprecharge
* =“Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other commands may be valid at these times
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Don’t Care
Oct. /2014
Confidential
54
Rev.2.0
AS4C64M8D1
Figure 37. Read with Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS
tIH
CKE
VALID
NOP
VALID
NOP
VALID
NOP
tIS tIH
NOP
NOP
ACT
RA
NOP
READ
NOP
NOP
COMMAND
A0-A9
tIS tIH
Col n
A11,A12
A10
RA
RA
EN AP
tIS tIH
tIS
tIH
Bank X
Bank X
BA0,BA1
CL=3
tRP
DM
Case 1:
tAC/tDQSCK=min
tDQSCK
tRPST
min
tRPRE
DQS
DQ
tLZ
min
DO
n
tLZ
tAC
min
min
Case 2:
tAC/tDQSCK=max
tDQSCK
tRPST
max
tRPRE
DQS
tLZ
tHZ
max
max
DO
n
DQ
tLZ
tAC
max
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
EN AP = Enable Autoprecharge
ACT = ACTIVE, RA = Row Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
The READ command may not be issued until tRAP has been satisfied. If Fast Autoprecharge is supported, tRAP = tRCD, else the READ
may not be issued prior to tRASmin – (BL*tCK/2)
Don’t Care
Confidential
55
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 38. Bank Read Access
tCK
tCH tCL
CK
CK
tIS tIH
CKE
tIS tIH
NOP
ACT
NOP
NOP
NOP
NOP
READ
Col n
PRE
NOP
NOP
ACT
COMMAND
A0-A9
tIS tIH
RA
RA
RA
A11,A12
RA
RA
tIS tIH
ALL BANKS
ONE BANKS
A10
RA
DIS AP
tIS
tIH
Bank X
Bank X
Bank X
*Bank X
BA0,BA1
tRC
tRAS
CL=3
tRCD
tRP
DM
Case 1:
tAC/tDQSCK=min
tDQSCK
min
tRPST
tRPRE
DQS
DQ
tLZ
DO
n
min
tLZ
tAC
min
min
Case 2:
tAC/tDQSCK=max
tDQSCK
max
tRPST
tRPRE
DQS
tHZ
max
tLZ
max
DO
n
DQ
tLZ
tAC
max
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP = Disable Autoprecharge
* = ”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS
would be limiting)
Don’t Care
Confidential
56
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 39. Write without Auto Precharge
tCK
tCH tCL
CK
CK
tIH
tIS
tIH
CKE
VALID
tIS tIH
WRITE
NOP
NOP
PRE
NOP
NOP
ACT
RA
NOP
NOP
NOP
COMMAND
A0-A9
tIS tIH
Col n
A11,A12
A10
RA
RA
BA
tIS tIH
ALL BANKS
ONE BANKS
DIS AP
tIS tIH
Bank X
*Bank X
BA0,BA1
Case 1:
tRP
tDSH
tDQSH
tDSH
tDQSS
tWR
tDQSS=min
tWPST
DQS
tDQSL
tWPRES
tWPRE
DI
n
DQ
DM
tDSS
tDQSH
tDSS
tWPST
Case 2:
tDQSS=max
tDQSS
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address, AR = AUTOREFRESH
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the +
25% window of the corresponding positive clock edge
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Don’t Care
Oct. /2014
Confidential
57
Rev.2.0
AS4C64M8D1
Figure 40. Write with Auto Precharge
tCK
tCH tCL
CK
CK
tIS
tIH
CKE
VALID
NOP
VALID
NOP
VALID
tIS tIH
ACT
RA
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
A0-A9
tIS tIH
Col n
A11,A12
RA
DIS AP
RA
BA
A10
tIS
tIH
Bank X
BA0,BA1
tDAL
Case 1:
tDQSS=min
tDSH
tDQSH
tDSH
tDQSS
tWPST
DQS
tWPRES
tWPRE
tDQSL
DI
n
DQ
DM
tDSS
tDQSH
tDSS
Case 2:
tDQSS=max
tDQSS
tWPST
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DI n
EN AP = Enable Autoprecharge
ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Don’t Care
Confidential
58
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 41. Bank Write Access
tCK
tCH tCL
CK
CK
tIS
tIH
CKE
tIS tIH
WRITE
Col n
NOP
NOP
PRE
NOP
NOP
NOP
ACT
NOP
NOP
COMMAND
A0-A9
tIS tIH
RA
RA
RA
A11,A12
tIS tIH
ALL BANKS
A10
DIS AP
ONE BANK
*Bank X
tIS tIH
Bank X
Bank X
BA0,BA1
tRAS
tRCD
tWR
Case 1:
tDQSS=min
tDSH
tDQSH
tDSH
tWPST
tDQSS
DQS
tWPRES
tWPRE
tDQSL
DI
n
DQ
DM
tDSS
Case 2:
tDSS
tWPST
tDQSH
tDQSS=max
tDQSS
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Don’t Care
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Confidential
59
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 42. Write DM Operation
tCK
tCH tCL
CK
CK
tIS
tIH
CKE
VALID
tIS tIH
WRITE
NOP
NOP
PRE
NOP
NOP
ACT
RA
NOP
NOP
NOP
COMMAND
A0-A9
tIS tIH
Col n
A11,A12
A10
RA
RA
BA
tIS tIH
ALL BANKS
ONE BANKS
DIS AP
tIS tIH
Bank X
BA0,BA1
Case 1:
*Bank X
tRP
tDSH
tDQSH
tDSH
tDQSS
tDQSS=min
tWR
tWPST
DQS
tDQSL
tWPRES
tWPRE
DI
n
DQ
DM
tDSS
tDQSH
tDSS
tWPST
Case 2:
tDQSS=max
tDQSS
DQS
tWPRES
tDQSL
tWPRE
DI
n
DQ
DM
DI n = Data In from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are provided in the programmed order following DI n
DIS AP = Disable Autoprecharge
*=”Don't Care”, if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Although tDQSS is drawn only for the first DQS rising edge, each rising edge of DQS must fall within the + 25%
window of the corresponding positive clock edge
Don’t Care
Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks
Confidential
60
Rev.2.0
Oct. /2014
AS4C64M8D1
Figure 43. 66 Pin TSOP II Package Outline Drawing Information
Units: mm
D
C
θ
b
S
e
F
(TYP)
Dimension in mm
Dimension in inch
Symbol
Min
Nom
Max
Min
Nom
Max
---
---
1.2
---
---
0.047
0.008
0.043
0.018
---
A
A1
A2
b
e
C
D
E
HE
L
L1
F
0.05
0.9
---
0.2
0.002
0.035
0.009
---
---
1.0
1.1
0.039
---
0.22
---
---
0.45
---
0.65
0.125
22.22
10.16
11.76
0.5
0.026
0.005
0.875
0.4
0.095
22.09
10.03
11.56
0.40
---
0.21
22.35
10.29
11.96
0.6
0.004
0.87
0.395
0.455
0.016
---
0.008
0.88
0.405
0.471
0.024
---
0.463
0.02
0.032
0.01
---
0.8
---
---
0.25
---
---
---
---
°
°
°
°
8
θ
0
8
0
S
---
---
0.71
---
---
---
---
0.028
---
---
y
0.10
0.004
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AS4C64M8D1
Figure 44. BGA 60ball package Outline Drawing Information
Pin A1 index
Top View
Side View
Bottom View
DETAIL : "A"
Dimension (inch)
Nom
Dimension (mm)
Symbol
Min
--
Max
0.047
0.016
0.031
0.009
0.319
0.516
--
Min
--
Nom
--
Max
1.20
0.40
0.8
0.23
8.10
13.10
--
A
A1
A2
A3
D
--
0.012
--
0.014
--
0.30
--
0.35
--
0.005
0.311
0.508
--
0.007
0.315
0.512
0.252
0.433
0.039
0.031
0.018
0.126
0.031
0.02
0.13
7.90
12.90
--
0.18
8.00
13.00
6.40
11.00
1.00
0.80
0.45
3.20
0.80
0.50
--
E
D1
E1
e1
e2
b
--
--
--
--
--
--
--
--
--
--
--
--
0.016
--
0.020
--
0.40
--
0.50
--
F
SD
SE
D2
--
--
--
--
--
--
--
--
--
--
0.081
--
2.05
Confidential
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Oct. /2014
AS4C64M8D1
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
Confidential
63
Rev.2.0
Oct. /2014
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