AS4C8M32S-6TIN_技术文档

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Revision History

AS4C8M32S - 86-pin TSOPII PACKAGE

Revision Details

Date

Rev 1.0

Preliminary datasheet

Mar. 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Features

Overview

Fast access time from clock: 5/5.4 ns

Fast clock rate: 166/143MHz

Fully synchronous operation

Internal pipelined architecture

2M word x 32-bit x 4-bank

•

The 256Mb SDRAM is

a

high-speed CMOS

synchronous DRAM containing 256 Mbits. It is

internally configured as 4 Banks of 2M word x 32

DRAM with a synchronous interface (all signals are

registered on the positive edge of the clock signal,

CLK). Read and write accesses to the SDRAM are

burst oriented; accesses start at a selected location

and continue for a programmed number of locations in

a programmed sequence. Accesses begin with the

registration of a BankActivate command which is then

followed by a Read or Write command.

Programmable Mode registers

- CAS Latency: 2, or 3

The SDRAM provides for programmable Read or

Write burst lengths of 1, 2, 4, 8, or full page, with a

burst termination option. An auto precharge function

may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst sequence. The

refresh functions, either Auto or Self Refresh are easy

to use. By having a programmable mode register, the

system can choose the most suitable modes to

maximize its performance. These devices are well

suited for applications requiring high memory

bandwidth and particularly well suited to high

performance PC applications.

- Burst Length: 1, 2, 4, 8, or full page

- Burst Type: Sequential or Interleaved

- Burst stop function

Auto Refresh and Self Refresh

4096 refresh cycles/64ms

CKE power down mode

•

±

Single +3.3V 0.3V power supply

Operating Temperature:

- Commercial (0~70°C)

- Industrial (-40~85°C)

Interface: LVTTL

•

86-pin 400 mil plastic TSOP II package

- Pb free and Halogen free

Table 1. Key Specifications

AS4C8M32S

Clock Cycle time (min.)

-6/7

tCK3

tAC3

tRAS

tRC

6/7

Access time from CLK (max.)

Row Active time (min.)

Row Cycle time (min.)

5/5.4

42/42

60/63

Table 2. Ordering Information

Part Number

Frequency

Package

Temperature

Temp Range

166MHz

AS4C8M32S-6TIN

Industrial

-40~85°C

86 Pin TSOP II

143MHz

Commercial

AS4C8M32S-7TCN

86 Pin TSOP II

0~70°C

T:indicates TSOP II package

C:Commercial

I:Industrial

N:indicates Pb free and Halogen free

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 1. Pin Assignment

(Top View)

VDD

DQ0

1

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

VSS

DQ15

2

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ1

3

4

DQ2

5

VSSQ

DQ3

6

7

DQ4

8

VDDQ

DQ5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

DQ6

VSSQ

DQ7

VDDQ

DQ8

NC

VDD

DQM0

WE#

CAS#

RAS#

CS#

VSS

DQM1

NC

CLK

CKE

A9

A11

BA0

A8

BA1

A7

A10/AP

A0

A6

A5

A1

A4

A2

A3

DQM2

VDD

DQM3

VSS

NC

DQ16

VSSQ

DQ17

DQ18

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS

VDDQ

DQ19

DQ20

VSSQ

DQ21

DQ22

VDDQ

DQ23

VDD

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Figure 2. Block Diagram

CLOCK

BUFFER

CLK

2M x 32

CELL ARRAY

(BANK #A)

CKE

CS#

Column Decoder

RAS#

CAS#

WE#

DQ0

COMMAND

DECODER

DQ

Buffer

CONTROL

SIGNAL

GENERATOR

DQ31

DQM0 ~ DQM3

COLUMN

COUNTER

2M x 32

CELL ARRAY

(BANK #B)

A10/AP

MODE

REGISTER

Column Decoder

A0

ADDRESS

BUFFER

A9

2M x 32

CELL ARRAY

(BANK #C)

A11

BA0

BA1

Column Decoder

REFRESH

COUNTER

2M x 32

CELL ARRAY

(BANK #D)

Column Decoder

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Pin Descriptions

Table 3. Pin Details

Symbol Type Description

CLK

Input

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the

positive edge of CLK. CLK also increments the internal burst counter and controls the

output registers.

CKE

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE

goes low synchronously with clock (set-up and hold time same as other inputs), the

internal clock is suspended from the next clock cycle and the state of output and burst

address is frozen as long as the CKE remains low. When all banks are in the idle state,

deactivating the clock controls the entry to the Power Down and Self Refresh modes.

CKE is synchronous except after the device enters Power Down and Self Refresh modes,

where CKE becomes asynchronous until exiting the same mode. The input buffers,

including CLK, are disabled during Power Down and Self Refresh modes, providing low

standby power.

Input

BA0,

BA1

Bank Activate: BA0 and BA1 define to which bank the BankActivate, Read, Write, or

BankPrecharge command is being applied. The bank address BA0 and BA1 is used

latched in mode register set.

A0-A11 Input

Address Inputs: A0-A11 are sampled during the BankActivate command (row address

A0-A11) and Read/Write command (column address A0-A8 with A10 defining Auto

Precharge) to select one location out of the 2M available in the respective bank. During a

Precharge command, A10 is sampled to determine if all banks are to be precharged (A10

= HIGH). The address inputs also provide the op-code during a Mode Register Set or

Special Mode Register Set command.

CS#

Input

Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command

decoder. All commands are masked when CS# is sampled HIGH. CS# provides for

external bank selection on systems with multiple banks. It is considered part of the

command code.

RAS#

Row Address Strobe: The RAS# signal defines the operation commands in conjunction

with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS#

and CS# are asserted "LOW" and CAS# is asserted "HIGH" either the BankActivate

command or the Precharge command is selected by the WE# signal. When the WE# is

asserted "HIGH" the BankActivate command is selected and the bank designated by BA

is turned on to the active state. When the WE# is asserted "LOW" the Precharge

command is selected and the bank designated by BA is switched to the idle state after

the precharge operation.

CAS#

WE#

Input

Column Address Strobe: The CAS# signal defines the operation commands in conjunction

with the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS#

is held "HIGH" and CS# is asserted "LOW" the column access is started by asserting CAS#

"LOW". Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH".

Input

Write Enable: The WE# signal defines the operation commands in conjunction with the

RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is

used to select the BankActivate or Precharge command and Read or Write command.

DQM0 -

DQM3

Data Input/Output Mask: Data Input Mask: DQM0-DQM3 are byte specific. Input data

is masked when DQM is sampled HIGH during a write cycle. DQM3 masks DQ31-DQ24,

DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0.

DQ0- Input/Ou Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of

DQ31

tput CLK. The I/Os are byte-maskable during Reads and Writes.

NC

-

No Connect: These pins should be left unconnected.

V_DDQSupply DQ Power: Provide isolated power to DQs for improved noise immunity.

V_SSQSupply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

V_DD

V_SS

Supply

Power Supply: +3.3V±0.3V

Supply Ground

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Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 4

shows the truth table for the operation commands.

Table 4. Truth Table (Note (1), (2))

Command

BankActivate

State CKE_n-1CKE_nDQM BA0,1 A10 A0-9,11 CS# RAS# CAS# WE#

Idle⁽³⁾

Any

H

X

H

L

X

V

X

V

X

V

L

H

L

H

L

H

L

H

L

X

H

L

X

L

H

L

H

L

Row address

BankPrecharge

PrechargeAll

L

H

L

X

Any

L

Active⁽³⁾

Idle

H

L

Column

address

(A0 ~ A8)

Write

Write and AutoPrecharge

Read

H

L

Column

address

(A0 ~ A8)

L

H

L

Read and Autoprecharge

Mode Register Set

No-Operation

H

L

OP code

L

Any

X

H

X

L

H

X

L

H

L

Burst Stop

Active⁽⁴⁾

Any

Device Deselect

AutoRefresh

X

H

X

H

X

V

X

H

X

H

X

Idle

SelfRefresh Entry

SelfRefresh Exit

Idle

L

Idle

X

H

X

V

X

H

X

H

X

H

X

V

X

H

X

H

X

L

H

L

X

(SelfRefresh)

Clock Suspend Mode Entry

Power Down Mode Entry

Active

Any⁽⁵⁾

Active

H

L

X

Clock Suspend Mode Exit

Power Down Mode Exit

L

H

X

Any

(PowerDown)

Data Write/Output Enable

Data Mask/Output Disable

Active

H

X

L

X

H

Note: 1. V=Valid, X=Don't Care, L=Low level, H=High level

2. CKE_nsignal is input level when commands are provided.

CKE_n-1signal is input level one clock cycle before the commands are provided.

3. These are states of bank designated by BA signal.

4. Device state is 1, 2, 4, 8, and full page burst operation.

5. Power Down Mode can not enter in the burst operation.

When this command is asserted in the burst cycle, device state is clock suspend mode.

6. DQM0-3

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Commands

1

BankActivate

(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)

The BankActivate command activates the idle bank designated by the BA0, 1 signal. By

latching the row address on A0 to A11 at the time of this command, the selected row access is

initiated. The read or write operation in the same bank can occur after a time delay of t_RCD(min.)

from the time of bank activation. A subsequent BankActivate command to a different row in the same

bank can only be issued after the previous active row has been precharged (refer to the following

figure). The minimum time interval between successive BankActivate commands to the same bank is

defined by t_RC(min.). The SDRAM has four internal banks on the same chip and shares part of the

internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the two

banks. t_RRD(min.) specifies the minimum time required between activating different banks. After this

command is used, the Write command and the Block Write command perform the no mask write

operation.

T0

T1

T2

T3

Tn+3 Tn+4

Tn+5

Tn+6

CLK

Bank A

Bank B

Bank A

ADDRESS

Row Addr.

Col Addr.

RAS# - CAS# delay(t_RCD

)

RAS# - RAS# delay time(t_RRD

)

Bank A

Activate

Bank A

Activate

R/W A with

AutoPrecharge

Bank B

Activate

NOP

COMMAND

RAS# - Cycle time(t_RC

)

AutoPrecharge

Begin

Don’t Care

Figure 3. BankActivate Command Cycle

(Burst Length = n)

2

BankPrecharge command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)

The BankPrecharge command precharges the bank disignated by BA signal. The precharged

bank is switched from the active state to the idle state. This command can be asserted anytime after

t_RAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any

bank can be active is specified by t_RAS(max.). Therefore, the precharge function must be performed

in any active bank within t_RAS(max.). At the end of precharge, the precharged bank is still in the idle

state and is ready to be activated again.

3

4

PrechargeAll command

(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don’t care, A10 = "H", A0-A9 and A11 = Don't care)

The PrechargeAll command precharges all banks simultaneously and can be issued even if all

banks are not in the active state. All banks are then switched to the idle state.

Read command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address)

The Read command is used to read a burst of data on consecutive clock cycles from an active

row in an active bank. The bank must be active for at least t_RCD(min.) before the Read command is

issued. During read bursts, the valid data-out element from the starting column address will be

available following the CAS latency after the issue of the Read command. Each subsequent data-out

element will be valid by the next positive clock edge (refer to the following figure). The DQs go into

high-impedance at the end of the burst unless other command is initiated. The burst length, burst

sequence, and CAS latency are determined by the mode register, which is already programmed. A

full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and

continue).

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T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

NOP

READ A

NOP

COMMAND

CAS# latency=2

t_CK2,DQ

DOUT A₀DOUT A₁DOUT A₂DOUT A₃

CAS# latency=3

t_CK3,DQ

DOUT A₀DOUT A₁DOUT A₂DOUT A₃

Figure 4. Burst Read Operation

(Burst Length = 4, CAS# Latency = 2, 3)

The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier

(i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function

may be interrupted by a subsequent Read or Write command to the same bank or the other active

bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll

command to the same bank too. The interrupt coming from the Read command can occur on any

clock cycle following a previous Read command (refer to the following figure).

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

READ A READ B

NOP

COMMAND

CAS# latency=2

t_CK2,DQ

DOUT A₀DOUT B₀DOUT B₁DOUT B₂DOUT B₃

CAS# latency=3

DOUT A₀DOUT B₀DOUT B₁DOUT B₂DOUT B₃

t_CK3,DQ

Figure 5. Read Interrupted by a Read

(Burst Length = 4, CAS# Latency = 2, 3)

The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from

a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write

command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a

single cycle with high-impedance on the DQ pins must occur between the last read data and the

Write command (refer to the following three figures). If the data output of the burst read occurs at the

second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the

Write command to avoid internal bus contention.

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CLK

DQM

BANKA

ACTIVATE

WRITE A

DIN A₀

NOP

READ A

NOP

NNOOPP

NOP

COMMAND

CAS# latency=2

t_CK2,DQ

DIN A₁

DIN A₂

DIN A₃

Must be Hi-Z before

the Write Command

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Figure 6. Read to Write Interval

≥

(Burst Length 4, CAS# Latency = 2)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

DQM

WRITE B

DIN B₀

NOP

READ A

NOP

COMMAND

CAS# latency=2

t_CK2,DQ

DIN B₁

DIN B₂

DIN B₃

Must be Hi-Z before

the Write Command

Don’t Care

≧

Figure 7. Read to Write Interval

(Burst Length

T4 T5

4, CAS# Latency = 3)

T0

T1

T2

T3

T6

T7

T8

CLK

DQM

WRITE B

DIN B₀

NOP

READ A

NOP

COMMAND

CAS# latency=3

t_CK3,DQ

DOUT A₀

DIN B₁

DIN B₂

Must be Hi-Z before

the Write Command

Don’t Care

Figure 8. Read to Write Interval

≥

(Burst Length 4, CAS# Latency = 2)

A read burst without the auto precharge function may be interrupted by a BankPrecharge/

PrechargeAll command to the same bank. The following figure shows the optimum time that

BankPrecharge/ PrechargeAll command is issued in different CAS latency.

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T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

Bank,

Col A

Bank

Row

Bank(s)

ADDRESS

tRP

NOP

Precharge

READ A

NOP

Activate

NOP

COMMAND

CAS# latency=2

t_CK2,DQ

DOUT A₀DOUT A₁DOUT A₂DOUT A₃

CAS# latency=3

t_CK3,DQ

DOUT A₀DOUT A₁DOUT A₂DOUT A₃

Don’t Care

Figure 9. Read to Precharge

(CAS# Latency = 2, 3)

5

6

Read and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A8 = Column Address)

The Read and AutoPrecharge command automatically performs the precharge operation after

the read operation. Once this command is given, any subsequent command cannot occur within a

time delay of {t_RP(min.) + burst length}. At full-page burst, only the read operation is performed in this

command and the auto precharge function is ignored.

Write command

(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A8 = Column Address)

The Write command is used to write a burst of data on consecutive clock cycles from an active

row in an active bank. The bank must be active for at least t_RCD(min.) before the Write command is

issued. During write bursts, the first valid data-in element will be registered coincident with the Write

command. Subsequent data elements will be registered on each successive positive clock edge

(refer to the following figure). The DQs remain with high-impedance at the end of the burst unless

another command is initiated. The burst length and burst sequence are determined by the mode

register, which is already programmed. A full-page burst will continue until terminated (at the end of

the page it will wrap to column 0 and continue).

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

WRITE A

DIN A₀

NOP

COMMAND

don’t care

DIN A₁

DIN A₂

DIN A₃

DQ

The first data element and the write

are registered on the same clock edge

Figure 10. Burst Write Operation

(Burst Length = 4)

A write burst without the auto precharge function may be interrupted by a subsequent Write,

BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt

coming from Write command can occur on any clock cycle following the previous Write command

(refer to the following figure).

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T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

WRITE A WRITE B

NOP

COMMAND

DQ

DIN A₀

DIN B₀

DIN B₁

DIN B₂

DIN B₃

Figure 11. Write Interrupted by a Write

(Burst Length = 4)

The Read command that interrupts a write burst without auto precharge function should be

issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid

data contention, input data must be removed from the DQs at least one clock cycle before the first

read data appears on the outputs (refer to the following figure). Once the Read command is

registered, the data inputs will be ignored and writes will not be executed.

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

WRITE A

DIN A₀

NOP

READ B

NOP

COMMAND

CAS# latency=2

don’t care

DOUT B₀DOUT B₁DOUT B₂DOUT B₃

t_CK2,DQ

CAS# latency=3

t_CK3,DQ

don’t care

DIN A₀

DOUT B₀DOUT B₁DOUT B₂DOUT B₃

Input data must be removed from the DQ

at least one clock cycle before the Read

data appears on the outputs to avoid data

contention

Figure 12. Write Interrupted by a Read

(Burst Length = 4, CAS# Latency = 2, 3)

The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto

precharge function should be issued m cycles after the clock edge in which the last data-in element

is registered, where m equals t_WR/t_CKrounded up to the next whole number. In addition, the DQM

signals must be used to mask input data, starting with the clock edge following the last data-in

element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is

entered (refer to the following figure).

T0

T1

T2

T3

T4

T5

T6

T7

CLK

DQM

tRP

NOP

Precharge

BANK(S)

NOP

WRITE

Activate

ROW

COMMAND

ADDRESS

BANK

COL n

tWR

DIN

N

DIN

N+1

DQ

Don’t Care

Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2.

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Figure 13. Write to Precharge

7

Write and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H",

A0-A8 = Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after the

write operation. Once this command is given, any subsequent command can not occur within a time

delay of {(burst length -1) + t_WR+ t_RP(min.)}. At full-page burst, only the write operation is performed

in this command and the auto precharge function is ignored.

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CLK

Bank A

Activate

Bank A

Activate

Write A

Auto Precharge

NOP

COMMAND

t_DAL

DQ

DIN A₀

DIN A₁

Begin AutoPrecharge

Bank can be reactivated at

completion of t_DAL

t_DAL=t_WR+t_RP

Figure 14. Burst Write with Auto-Precharge

(Burst Length = 2)

8

Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The

Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst

Length in the Mode register to make SDRAM useful for a variety of different applications. The default

values of the Mode Register after power-up are undefined; therefore this command must be issued

at the power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to

the mode register. Two clock cycles are required to complete the write in the mode register (refer to

the following figure). The contents of the mode register can be changed using the same command

and the clock cycle requirements during operation as long as all banks are in the idle state.

Table 5. Mode Register Bitmap

BA0,1 A11,A10 A9

RFU* RFU* WBL

A8

Test Mode

A7

A6

A5

A4

A3

BT

A2

A1

A0

CAS Latency

Burst Length

A9 Write Burst Length

A8 A7

Test Mode

Normal

Vendor Use Only

A3

0

1

Burst Type

Sequential

Interleave

0

1

Burst

Single Bit

0

1

0

1

A6

0

A5

0

A4

0

1

CAS Latency

Reserved

2 clocks

A2

0

A1

0

A0

0

1

Burst Length

1

2

4

0

1

0

1

0

1

0

1

0

3 clocks

Reserved

0

1

8

Full Page (Sequential)

All other Reserved

*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.

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T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

CLK

CKE

CS#

t_MRD

RAS#

CAS#

WE#

BA0, 1

A10

Address Key

A0-A9,

A11

DQM

DQ

t_RP

Hi-Z

PrechargeAll

Mode Register

Set Command

Any

Command

Don’t Care

Figure 15. Mode Register Set Cycle

Burst Length Field (A2~A0)

•

This field specifies the data length of column access using the A2~A0 pins and selects the Burst

Length to be 2, 4, 8, or full page.

Table 6. Burst Length Field

A2

0

A1

0

A0

0

Burst Length

1

0

1

2

0

1

0

4

0

1

8

1

0

Reserved

Full Page

1

0

1

0

1

Full Page Length: 512

Burst Type Field (A3)

•

The Burst Type can be one of two modes, Interleave Mode or Sequential Mode.

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Table 7. Burst Type Field

A3

0

Burst Type

Sequential

Interleave

1

Burst Definition, Addressing Sequence of Sequential and Interleave Mode

•

Table 8. Burst Definition

Start Address

Burst Length

Sequential

Interleave

A2

X

0

1

A1

X

0

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0, 1

1, 0

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

0, 1

1, 0

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

2

4

0

1

0

1

0

3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

n, n+1, n+2, n+3, …511, 0,

1, 2, … n-1, n, …

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

8

1

0

1

Full page location = 0-255

Not Support

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CAS Latency Field (A6~A4)

•

This field specifies the number of clock cycles from the assertion of the Read command to the first

read data. The minimum whole value of CAS Latency depends on the frequency of CLK. The

minimum whole value satisfying the following formula must be programmed into this field.

t_CAC(min) ≤ CAS Latency X t_CK

Table 9. CAS Latency Field

A6

0

A5

0

A4

0

CAS Latency

Reserved

2 clocks

0

1

0

1

0

1

3 clocks

1

X

Reserved

Test Mode Field (A8~A7)

•

These two bits are used to enter the test mode and must be programmed to "00" in normal operation.

Table 10. Test Mode Field

A8

0

A7

0

Test Mode

normal mode

0

1

Vendor Use Only

1

X

Write Burst Length (A9)

•

This bit is used to select the burst write length.

Table 11. Write Burst length

A9

0

Write Burst Length

Burst

1

Single Bit

9

No-Operation command

(RAS# = "H", CAS# = "H", WE# = "H")

The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is

Low). This prevents unwanted commands from being registered during idle or wait states.

10 Burst Stop command

(RAS# = "H", CAS# = "H", WE# = "L")

The Burst Stop command is used to terminate either fixed-length or full-page bursts. This

command is only effective in a read/write burst without the auto precharge function. The terminated

read burst ends after a delay equal to the CAS latency (refer to the following figure). The termination

of a write burst is shown in the following figure.

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

Burst Stop

READ A NOP

NOP

COMMAND

The burst ends after a delay equal to the CAS# latency

CAS# latency=2

t_CK2,DQ

DOUT A₀DOUT A₁DOUT A₂DOUT A₃

CAS# latency=3

t_CK3,DQ

Figure 16. Termination of a Burst Read Operation _{(Burst Length}

＞

4, CAS# Latency = 2, 3)

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T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

WRITE A

Burst Stop

don’t care

NOP

COMMAND

DIN A₀DIN A₁DIN A₂

DQ

Figure 17. Termination of a Burst Write Operation

(Burst Length = X)

11 Device Deselect command (CS# = "H")

The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE#

and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar

to the No Operation command.

12 AutoRefresh command

(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", A0-A11 = Don't care)

The AutoRefresh command is used during normal operation of the SDRAM and is analogous to

CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it

must be issued each time a refresh is required. The addressing is generated by the internal refresh

controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal

refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh

operation must be performed 4096 times within 64ms. The time required to complete the auto

refresh operation is specified by t_RC(min.). To provide the AutoRefresh command, all banks need to

be in the idle state and the device must not be in power down mode (CKE is high in the previous

cycle). This command must be followed by NOPs until the auto refresh operation is completed. The

precharge time requirement, t_RP(min), must be met before successive auto refresh operations are

performed.

13 SelfRefresh Entry command

(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A11 = Don't care)

The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh

mode for data retention and low power operation. Once the SelfRefresh command is registered, all

the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW.

The refresh addressing and timing is internally generated to reduce power consumption. The

SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by

restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command).

14 SelfRefresh Exit command

This command is used to exit from the SelfRefresh mode. Once this command is registered,

NOP or Device Deselect commands must be issued for t_RC(min.) because time is required for the

completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are

performed during normal operation, a burst of 4096 auto refresh cycles should be completed just

prior to entering and just after exiting the SelfRefresh mode.

15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")

When the SDRAM is operating the burst cycle, the internal CLK is suspended (masked) from

the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held

intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command

performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are

turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown

state longer than the refresh period (64ms) since the command does not perform any refresh

operations.

16 Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H")

When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from

the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the

PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active

state. t_PDE(min.) is required when the device exits from the PowerDown mode. Any subsequent

commands can be issued after one clock cycle from the end of this command.

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17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")

During a write cycle, the DQM signal functions as a Data Mask and can control every word of

the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is

also used for device selection, byte selection and bus control in a memory system.

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Table 12. Absolute Maximum Rating

Symbol

Item

Values

Unit Note

V_IN, V_OUTInput, Output Voltage

-1.0 ~ 4.6

0 ~ 70

V

1

V_DD, V_DDQPower Supply Voltage

V

Commercial

Industrial

°C

T_A

Ambient Temperature

Storage Temperature

-40 ~ 85

-55 ~ 125

260

T_STG

T_SOLDER

Soldering Temperature (10 seconds)

P_D

I_OS

Power Dissipation

1

W

1

Short Circuit Output Current

50

mA

Table 13. Recommended D.C. Operating Conditions

±

(V_DD= 3.3V 0.3V, T_A= -40~85°C)

Symbol

V_DD

Parameter

Power Supply Voltage

Min.

3.0

Typ.

3.3

3.0

0

Max.

3.6

Unit Note

V

2

V_DDQ

V_IH

Power Supply Voltage(for I/O Buffer)

LVTTL Input High Voltage

3.0

3.6

2.0

V_DDQ+0.3

0.8

V_IL

LVTTL Input Low Voltage

-0.3

Input Leakage Current

( 0V ≤ VIN ≤ VDD, All other pins not under test = 0V )

－

I_IL

-10

2.4

－

10

－

µA

V

Output Leakage Current

Output disable, 0V ≤ V_OUT≤ V_DDQ

I_OZ

)

LVTTL Output "H" Level Voltage

( I_OUT= -2mA )

V_OH

V_OL

LVTTL Output "L" Level Voltage

( I_OUT= 2mA )

0.4

V

Table 14. Capacitance

(V_DD= 3.3V, f = 1MHz, T_A= 25°C)

Parameter

Symbol

Min.

Max.

5.5

6

Unit

pF

C_I

Input Capacitance

Input/Output Capacitance

3.5

4

C_I/O

pF

Note: These parameters are periodically sampled and are not 100% tested.

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Table 15. D.C. Characteristics

±

(V_DD= 3.3V 0.3V, T_A= -40~85°C)

-6

-7

Unit Note

Max.

Description/Test condition

Symbol

I_DD1

Operating Current

t_RC≥ t_RC(min), Outputs Open

One bank active

Precharge Standby Current in non-power down mode

t_CK= 15ns, CS# ≥ V_IH(min), CKE ≥ V_IH

Input signals are changed every 2clks

Precharge Standby Current in non-power down mode

t_CK= ∞, CLK ≤ V_IL(max), CKE ≥ V_IH

Precharge Standby Current in power down mode

t_CK= 15ns, CKE ≤ V_IL(max)

3

100

40

100

40

I_DD2N

36

4

36

4

I_DD2NS

I_DD2P

Precharge Standby Current in power down mode

t_CK= ∞, CKE ≤ V_IL(max)

4

I_DD2PS

mA

Active Standby Current in non-power down mode

t_CK= 15ns, CKE ≥ V_IH(min), CS# ≥ V_IH(min)

Input signals are changed every 2clks

Active Standby Current in non-power down mode

CKE ≥ V_IH(min), CLK ≤ V_IL(max), t_CK= ∞

Operating Current (Burst mode)

t_CK=t_CK(min), Outputs Open, Multi-bank interleave

Refresh Current

t_RC≥ t_RC(min)

70

I_DD3N

70

124

150

4

I_DD3NS

I_DD4

120

150

4

3, 4

3

I_DD5

Self Refresh Current

I_DD6

≧

CKE ≤ 0.2V ; for other inputs VIH VDD - 0.2V, VIL ≤ 0.2V

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Table 16. Electrical Characteristics and Recommended A.C. Operating Conditions

(V_DD= 3.3V

±

0.3V, T_A= -40~85°C) (Note: 5, 6, 7, 8)

-6

-7

Symbol

A.C. Parameter

Unit Note

Min.

Max.

Min.

Max.

60

-

63

-

Row cycle time (same bank)

t

RC

18

-

21

-

RAS# to CAS# delay (same bank)

RCD

Precharge to refresh/row activate command

(same bank)

t

RP

Row activate to row activate delay

(different banks)

12

-

14

-

RRD

Row activate to precharge time

(same bank)

42

12

100k

-

42

14

100k

-

t

RAS

WR

Write recovery time

CL* = 2

10

6

-

10

7

-

9

t

Clock cycle time

CK

CL* = 3

ns

10

2.5

Clock high time

Clock low time

2

-

t

CH

CL

10

9

CL* = 2

-

6

5

-

6

Access time from CLK

t

AC

(positive edge)

CL* = 3

-

5.4

Data output hold time

Data output low impedance

Data output high impedance

2.5

0

-

t

OH

LZ

HZ

IS

0

-

5

-

5.4

-

8

-

Data/Address/Control Input set-up time

Data/Address/Control Input hold time

Power Down Exit set-up time

1.5

0.8

1.5

0.8

10

-

IH

t_IS+ t_CK

-

15.6

-

t_IS+ t_CK

-

15.6

-

PDE

Average Refresh Interval time

REFI

µs

Exit Self Refresh to any command time

t_XSR

tIS+ tRC

ns

*

CL is CAS Latency.

Note:

1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to

the device. Absolute maximum DC requirements contain stress ratings only. Functional operation at the

absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may

affect device reliability.

2. All voltages are referenced to V_SS. VIH (Max) = 4.6V for pulse width ≤ 3ns. VIL (Min) = -1.0V for pulse

width ≤ 3ns.

3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the

minimum value of t_CKand t_RC. Input signals are changed one time during every 2 t_CK

.

4. These parameters depend on the output loading. Specified values are obtained with the output open.

5. Power-up sequence is described in Note 11.

6. A.C. Test Conditions

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Table 17. LVTTL Interface

Reference Level of Output Signals

1.4V / 1.4V

Output Load

Input Signal Levels

Reference to the Under Output Load (B)

2.4V / 0.4V

1ns

Transition Time (Rise and Fall) of Input Signals

Reference Level of Input Signals

1.4V

3.3V

50Ω

1.2KΩ

Output

Z0=50Ω

870Ω

30pF

Figure 18.1 LVTTL D.C. Test Load (A)

Figure 18.2 LVTTL A.C. Test Load (B)

7. Transition times are measured between V_IHand V_IL. Transition (rise and fall) of input signals are in a

fixed slope (1 ns).

8. t_HZdefines the time in which the outputs achieve the open circuit condition and are not at reference

levels.

9. If clock rising time is longer than 1 ns, (t_R/ 2 -0.5) ns should be added to the parameter.

10. Assumed input rise and fall time t_T(t_R& t_F) = 1 ns

If t_Ror t_Fis longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns

should be added to the parameter.

11. Power up Sequence

Power up must be performed in the following sequence.

1) Power must be applied to V_DDand V_DDQ(simultaneously) when CKE= “L”, DQM= “H” and all input

signals are held "NOP" state.

2) Start clock and maintain stable condition for minimum 200 µs, then bring CKE= “H” and, it is

recommended that DQM is held "HIGH" (V_DDlevels) to ensure DQ output is in high impedance.

3) All banks must be precharged.

4) Mode Register Set command must be asserted to initialize the Mode register.

5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the

device.

* The Auto Refresh command can be issue before or after Mode Register Set command.

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Timing Waveforms

Figure 19. AC Parameters for Write Timing

(Burst Length=4)

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17T18T19 T20 T21 T22

T0 T1 T2 T3 T4 T5 T6

CLK

t_CH

t_CL

t_IS

t_IH

Begin Auto

Precharge Bank A

Begin Auto

Precharge Bank B

CKE

CS#

t_IS

RAS#

CAS#

WE#

BA0,1

A10

t_IH

RAx

RBx

RAy

t_I

S

A0-A9,

A11

CAx

CBx

CAy

DQM

DQ

t_DAL

t_IS

t_WR

t_RCD

t_RC

t_IH

Hi-Z

Ay1 Ay2 Ay3

Ax1 Ax2 Ax3

Bx0 Bx1 Bx2 Bx3

Ay0

Ax0

Write with

Activate

Command

Bank B

Write with

Activate

Command

Bank A

Activate

Command

Bank A

Write

Command

Bank A

Precharge

Command

Bank A

Auto Precharge

Command

Bank A

Auto Precharge

Command

Bank B

Don’t Care

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Figure 20. AC Parameters for Read Timing

(Burst Length=2, CAS# Latency=2)

T0

T1

T4

T5

T2

T6

T8

T12 T13 T14 T15 T16

T3

T7

T9 T10 T11

CLK

CKE

CS#

t_CHt_CL

t_IS

Begin Auto

Precharge Bank B

t_IH

t_IS

t_IH

RAS#

CAS#

WE#

BA0,1

t_IH

RAx

RBx

RAy

A10

t_IS

A0-A9,

A11

CBx

CAx

t_RRD

t_RAS

t_RC

DQM

DQ

t_AC

t_LZ

t_RP

t_HZ

t_RCD

Hi-Z

Ax0

Ax1

Bx0

Bx1

t_HZ

t_OH

Activate

Command

Bank B

Activate

Command

Bank A

Read

Command

Bank A

Read with

Auto Precharge

Command

Activate

Command

Bank A

Precharge

Command

Bank A

Bank B

Don’t Care

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Figure 21. Auto Refresh

(Burst Length=4, CAS# Latency=2)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T3 T4 T5 T6

T22

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

A0-A9,

A11

RAx

CAx

t_RP

t_RCD

t_RC

DQM

DQ

Ax0 Ax1

Precharge All

Command

Auto Refresh

Command

Read

Command

Bank A

Activate

Command

Bank A

Auto Refresh

Command

Don’t Care

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Figure 22. Power on Sequence and Auto Refresh

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

High Level

Minimum for 2 Refresh Cycles are required

Is reguired

CS#

RAS#

CAS#

WE#

BA0,1

A10

Address Key

A0-A9,

A11

DQM

DQ

t_RP

t_MRD

Hi-Z

Precharge All

Command

Any

Command

1st Auto Refresh^(*)

Command

2nd Auto Refresh^(*)

Command

Inputs must be

Mode Register

Set Command

Stable for

200μs

Don’t Care

Note^(*): The Auto Refresh command can be issue before or after Mode Register Set command

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Figure 23. Self Refresh Entry & Exit Cycle

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19

t_XSR

CLK

CKE

*Note 2

*Note 8

*Note 1

*Note 5

*Note 3, 4

t_ISt_IH

t_PDE

*Note 6

*Note 7

t_IS

CS#

RAS#

*Note 9

CAS#

BA0,1

A0-A9,

A11

WE#

DQM

DQ

Hi-Z

Self Refresh Entry

Self Refresh Exit

Auto Refresh

Don’t Care

Note: To Enter SelfRefresh Mode

1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.

3. The device remains in SelfRefresh mode as long as CKE stays "low".

4. Once the device enters SelfRefresh mode, minimum t_RASis required before exit from SelfRefresh.

To Exit SelfRefresh Mode

5. System clock restart and be stable before returning CKE high.

6. Enable CKE and CKE should be set high for valid setup time and hold time.

7. CS# starts from high.

8. Minimum t_XSRis required after CKE going high to complete SelfRefresh exit.

9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the

system uses burst refresh.

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Figure 24.1. Clock Suspension During Burst Read (Using CKE)

(Burst Length=4, CAS# Latency=2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

A0-A9,

A11

RAx

CAx

DQM

DQ

t_HZ

Hi-Z

Ax1

Ax2

Ax3

Ax0

Activate

Cammand

Bank A

Clock Suspend

3 Cycles

Clock Suspend

2 Cycles

Read

Command

Bank A

Clock Suspend

1 Cycle

Don’t Care

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Figure 24.2. Clock Suspension During Burst Read (Using CKE)

(Burst Length=4, CAS# Latency=3)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

A0-A9,

A11

CAx

RAx

DQM

DQ

t_HZ

Hi-Z

Ax1

Ax2

Ax3

Ax0

Activate

Cammand

Bank A

Clock Suspend

3 Cycles

Clock Suspend

2 Cycles

Clock Suspend

1 Cycle

Read

Command

Bank A

Don’t Care

Confidential

- 28/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 25. Clock Suspension During Burst Write (Using CKE)

(Burst Length=4)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T22

T3 T4 T5 T6

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

A0-A9,

A11

CAx

DQM

Hi-Z

DAx1

DAx2

DAx0

DAx3

DQ

Clock Suspend

2 Cycles

Clock Suspend

3 Cycles

Activate

Cammand

Bank A

Clock Suspend

1 Cycle

Don’t Care

Write

Command

Bank A

Confidential

- 29/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 26. Power Down Mode and Clock Suspension

(Burst Length=4, CAS# Latency=2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

t

t_PDE

_IHt_IS

CKE

CS#

Valid

RAS#

CAS#

WE#

BA0,1

A10

RAx

A0-A9,

A11

CAx

DQM

DQ

t_HZ

Ax3

Hi-Z

Ax2

Ax0 Ax1

PRECHARGE

STANDBY

ACTIVE

STANDBY

Precharge

Command

Bank A

Clock Suspension

End

Read

Command

Bank A

Clock Suspension

Start

Power Down

Mode Exit

Activate

Cammand

Bank A

Any

Commad

Power Down

Mode Entry

Power Down

Mode Exit

Power Down

Mode Entry

Don’t Care

Confidential

- 30/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 27.1. Random Column Read (Page within same Bank)

(Burst Length=4, CAS# Latency=2)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T22

T3 T4 T5 T6

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

x

RAw

RAz

A0-A9,

A11

RAw

CAx

CAw

CAy

CAz

DQM

Hi-Z

Az0

DQ

Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3

Read

Command

Bank A

Read

Command

Bank A

Activate

Cammand

Bank A

Read

Command

Bank A

Activate

Command

Bank A

Read

Command

Bank A

Precharge

Command

Bank A

Don’t Care

Confidential

- 31/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 27.2. Random Column Read (Page within same Bank)

(Burst Length=4, CAS# Latency=3)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T22

T3 T4 T5 T6

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

x

RAw

RAz

A0-A9,

A11

RAw

CAx

CAw

CAy

CAz

DQM

Hi-Z

Aw0 Aw1 Aw2 Aw3 Ax0 Ax1

Ay3

DQ

Ay0 Ay1 Ay2

Read

Command

Bank A

Read

Command

Bank A

Activate

Cammand

Bank A

Read

Command

Bank A

Activate

Command

Bank A

Read

Command

Bank A

Precharge

Command

Bank A

Don’t Care

Confidential

- 32/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 28. Random Column Write (Page within same Bank)

(Burst Length=4)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T22

T3 T4 T5 T6

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

Ax

A10

RBw

RBz

A0-A9,

A11

RBw

CBx

CBw

CBy

CBz

DQM

Hi-Z

DBw0

Write

Command

Bank B

DBw2

DBx0 DBx1

DBw1

DBw3

DBy0 DBy1 DBy2 DBy3

DBz0 DBz1

DQ

Write

Command

Bank B

Write

Command

Bank B

Activate

Cammand

Bank B

Activate

Command

Bank B

Write

Command

Bank B

Precharge

Command

Bank B

Don’t Care

Confidential

- 33/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 29.1. Random Row Read (Interleaving Banks)

(Burst Length=8, CAS# Latency=2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

High

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RBx

RAx

RBy

A0-A9,

A11

CBy

CBx

CAx

t_AC

t_RCD

t_RP

DQM

Hi-Z

Bx1 Bx2

Bx4 Bx5

Ax1 Ax2 Ax3 Ax4 Ax5

DQ

Bx0

Bx3

Bx6 Bx7

Read

Command

Bank A

Ax0

Ax6 Ax7

Activate

Command

Bank A

Activate

Command

Bank B

Activate

Cammand

Bank B

Read

Command

Bank B

Read

Command

Bank B

Precharge

Command

Bank B

Don’t Care

Confidential

- 34/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 29.2. Random Row Read (Interleaving Banks)

(Burst Length=8, CAS# Latency=3)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

High

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RBx

RAx

RBy

A0-A9,

A11

CBx

CAx

CBy

t_AC

t_RCD

t_RP

DQM

Hi-Z

DQ

Bx0

Bx1 Bx2

Bx3

Bx4 Bx5

Read

Bx6 Bx7 Ax0

Precharge

Ax1 Ax2 Ax3 Ax4 Ax5

Ax7

Ax6 By0

Activate

Command

Bank A

Activate

Cammand

Bank B

Activate

Command

Bank B

Read

Command

Bank B

Read

Command

Bank B

Precharge

Command

Bank A

Command

Bank B

Command

Bank A

Don’t Care

Confidential

- 35/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 30. Random Row Write (Interleaving Banks)

(Burst Length=8)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

High

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

RBx

RAy

A0-A9,

A11

RAx

CAx

CBx

CAy

t_RP

t_WR*

t_RCD

DQM

DQ

Hi-Z

DAx0 DAx1 DAx2 DAx3 DAx4

Write

Command

Bank A

DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3

Activate

Command

Bank B

Precharge

Command

Bank A

Write

Command

Bank B

Activate

Cammand

Bank A

Activate

Command

Bank A

Write

Command

Bank A

Precharge

Command

Bank B

Don’t Care

* t_WR> t_WR(min.)

Confidential

- 36/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 31.1. Read and Write Cycle

(Burst Length=4, CAS# Latency=2)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T22

T3 T4 T5 T6

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

A0-A9,

A11

CAy

CAz

CAx

DQM

DQ

Hi-Z

DAy0

DAy3

Az3

Ax2

DAy1

Az1

Ax0 Ax1

Ax3

Az0

The Read Data

is Masked with a

Two Clock

Activate

Cammand

Bank A

Write

Command

Bank A

Read

Command

Bank A

The Write Data

is Masked with a

Zero Clock

Read

Command

Bank A

Latency

Don’t Care

Confidential

- 37/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 31.2. Read and Write Cycle

(Burst Length=4, CAS# Latency=3)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

A0-A9,

A11

RAx

CAy

CAx

CAz

DQM

DQ

Hi-Z

DAy0

Ax2

DAy1

Az1

Ax1

Ax3

DAy3

Az3

Ax0

Az0

The Read Data

is Masked with a

Two Clock

Activate

Cammand

Bank A

Write

Command

Bank A

Read

Command

Bank A

The Write Data

is Masked with a

Zero Clock

Latency

Read

Command

Bank A

Don’t Care

Confidential

- 38/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 32.1. Interleaving Column Read Cycle

(Burst Length=4, CAS# Latency=2)

T0 T1 T2

T7 T8 T9 T10 T11T12 T13 T14 T15 T16 T17 T18 T19T20 T21

T22

T3 T4 T5 T6

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RBx

RAx

A0-A9,

A11

RAx

RBx

CBw

CBx

CBy

CAy

CBz

t_AC

t_RCD

DQM

Hi-Z

DQ

Ax0 Ax1 Ax2 Ax3

Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3

Read

Command

Bank B

Read

Precharge

Command

Bank B

Read

Activate

Read

Activate

Cammand

Bank A

Read

Command

Bank A

Command

Bank B

Command

Command Command

Bank B Bank B

Bank A

Bank B

Precharge

Command

Bank A

Don’t Care

Confidential

- 39/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 32.2. Interleaved Column Read Cycle

(Burst Length=4, CAS# Latency=3)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T22

T3 T4 T5 T6

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RBx

RAx

t_RCD

A0-A9,

A11

CAx RBx

CBx

CBy

CBz

CAy

t_AC

DQM

DQ

Hi-Z

Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3

Activate

Cammand

Bank A

Read

Precharge

Command

Bank A

Read

Command

Bank A

Read

Command Command Command

Bank B Bank B

Bank A

Precharge

Command Command

Bank B

Activate

Command

Bank B

Don’t Care

Confidential

- 40/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 33. Interleaved Column Write Cycle

(Burst Length=4)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RBw

RAx

A0-A9,

A11

RAx

CAx RBw

CBw

CBx

CBy

CAy

CBz

t_RCD

t_WR

DQM

t_RRD>t_RRD(min)

Hi-Z

DAx0 DAx1 DAx2

DBw0

DBx1

DAy0 DAy1

DAx3

DBw1 DBx0

DBy0 DBy1

DBz0 DBz1

DBz2 DBz3

DQ

Activate

Cammand

Bank A

Write

CommandCommand

Bank B Bank B

Write

Precharge

Command

Bank B

Write

Command

Bank A

Write

Command CommandCommand

Bank B Bank A Bank B

Activate

Precharge

Command

Bank B

Command

Bank A

Don’t Care

Confidential

- 41/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 34.1. Auto Precharge after Read Burst

(Burst Length=4, CAS# Latency=2)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T22

T3 T4 T5 T6

CLK

CKE

High

Begin Auto

Precharge

Bank A

Begin Auto

Precharge

Bank B

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

RBx

RBy

RAz

A0-A9,

A11

RAx

CAx

RBx

CBx

RAy

RBy

CBy

t_RP

DQM

DQ

Hi-Z

Ax0 Ax1 Ax2 Ax3

Activate

Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3

By0 By1 By2

Activate

Cammand

Bank A

Read

Command

Bank A

Activate

Command

Bank B

Activate

Command

Bank A

Read with

Command

Bank B

Auto Precharge

Command

Bank B

Read with

Auto Precharge

Command

Read with

Auto Precharge

Command

Bank B

Bank A

Don’t Care

Confidential

- 42/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 34.2. Auto Precharge after Read Burst

(Burst Length=4, CAS# Latency=3)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

Begin Auto

High

Precharge

Bank B

Bank A

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

RBx

RBy

A0-A9,

A11

CAx RBx

CBx

CAy

RBy

CBy

t_RP

DQM

Hi-Z

DQ

Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3

By0 By1 By2

Read with

Auto Precharge

Command

Bank A

Activate

Cammand

Bank A

Read

Command

Bank A

Read with

Auto Precharge

Command

Bank B

Activate

Command

Bank B

Auto Precharge

Command

Bank B

Activate

Command

Bank B

Don’t Care

Confidential

- 43/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 35. Auto Precharge after Write Burst

(Burst Length=4)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T22

T3 T4 T5 T6

CLK

CKE

High

Begin Auto

Precharge

Bank A

Begin Auto

Precharge

Bank B

CS#

RAS#

CAS#

WE#

BA0,1

RAx

RBx

RBy

A10

A0-A9,

A11

RAx

CAx RBx

CBx

CAy

RBy

CBy

t_DAL

DQM

Hi-Z

DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3

DBy0 DBy1 DBy2 DBy3

DQ

Activate

Command

Bank B

Activate

Cammand

Bank A

Activate

Command

Bank B

Write with

Auto Precharge

Command

Bank B

Write with

Auto Precharge

Command

Bank A

Write with

Auto Precharge

Command

Bank B

Write

Command

Bank A

Don’t Care

Confidential

- 44/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 36.1. Full Page Read Cycle

(Burst Length=Full Page, CAS# Latency=2)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T3 T4 T5 T6

T22

CLK

High

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

RBx

RBy

A0-A9,

A11

RAx

CAx

RBx

CBx

RBy

t_RP

DQM

DQ

Hi-Z

Bx+6

Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5

Precharge

Command

Bank B

Activate

Command

Bank B

Activate

Cammand

Bank A

Read

Command Cammand

Bank A Bank B

Activate

Read

Command

Bank B

Burst Stop

Command

The burst counter wraps

from the highest order

page address back to zero

during this time interval

Full Page burst operation does not

terminate when the burst length is satisfied;

the burst counter increments and continues

bursting beginning with the starting address

Don’t Care

Confidential

- 45/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 36.2. Full Page Read Cycle

(Burst Length=Full Page, CAS# Latency=3)

T0 T1 T2

T7 T8 T9 T10 T11 T12T13 T14 T15 T16 T17 T18 T19T20 T21

T3 T4 T5 T6

T22

CLK

High

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

RBx

RBy

A0-A9,

A11

RAx

CAx

RBx

CBx

RBy

t_RP

DQM

Hi-Z

Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5

DQ

Precharge

Read

Activate

Command

Bank B

Activate

Cammand

Bank A

Read

Activate

Command

Command Cammand

Bank A Bank B

Bank B

The burst counter wraps

from the highest order

page address back to zero

during this time interval

Burst Stop

Command

Full Page burst operation does not

terminate when the burst length is

satisfied; the burst counter increments

and continues bursting beginning with

the starting address

Don’t Care

Confidential

- 46/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 37. Full Page Write Cycle

(Burst Length=Full Page)

T0 T1 T2

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21

T3 T4 T5 T6

T22

CLK

High

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

RBx

RBy

A0-A9,

A11

RAx

CBx

RBy

CAx

RBx

DQM

Data is ignored

Hi-Z

DAx DAx+1

DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3

DAx+2

DBx+5

DBx+4

DQ

Precharge

Command

Bank B

Activate

Command

Bank B

Write

Command

Bank B

Activate

Cammand

Bank A

Write

Command Cammand

Bank A Bank B

Activate

Burst Stop

Command

The burst counter wraps

from the highest order

page address back to zero

during this time interval

Full Page burst operation does not

terminate when the burst length is

satisfied; the burst counter increments

and continues bursting beginning with

the starting address

Don’t Care

Confidential

- 47/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 38. Byte Read and Write Operation

(Burst Length=4, CAS# Latency=2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

High

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

A0-A9,

A11

RAx

CAy

CAz

CAx

DQM m

DQM n

DQ M

Ax0 Ax1

Ax2

DAy1 DAy2

Az1

Az2

DQ N

Ax1 Ax2 Ax3

DAy0 DAy1

DAy3

Az1 Az2 Az3

Az0

Activate

Cammand

Bank A

Read

Command

Bank A

Write

Command

Bank A

Read

Command

Bank A

Upper Byte

is masked

Upper Byte

is masked

Lower Byte

is masked

Lower Byte

is masked

Lower Byte

is masked

Don’t Care

Note : M represent DQ in the byte m; N represent DQ in the byte n.

Confidential

- 48/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 39. Random Row Read (Interleaving Banks)

(Burst Length=4, CAS# Latency=2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

High

Begin Auto

Precharge

Bank B

Begin Auto

Precharge

Bank A

Begin Auto

Precharge

Bank B

Begin Auto

Precharge

Bank A

CS#

RAS#

CAS#

WE#

BA0,1

A10

RBu

RAu

RBv

RBw

RAv

A0-A9,

A11

RBu

CBu

CAu

RBv

CBv

CAv

RBw

t_RP

DQM

DQ

Av

2

Au

3

Av

0

Au0

Av3

Bu3

Au2

Bv3

Av1

Bu1

Bu2

Bv0

Bv2

Bu0

Au1

Bv1

Activate

Command

Bank B

Activate

Command

Bank A

Activate

Command

Bank B

Activate

Command

Bank A

Activate

Command

Bank B

Read

Bank A

with Auto

Precharge

Read

Bank A

with Auto

Precharge

Read

Bank B

with Auto

Precharge

Bank B

with Auto

Precharge

Don’t Care

Confidential

- 49/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 40. Full Page Random Column Read

(Burst Length=Full Page, CAS# Latency=2)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RBx

RBw

RAx

A0-A9,

A11

RBx CAx

CBx

CBy

CAz

CBz

CAy

t_RP

DQM

t_RRD

t_RCD

Hi-Z

DQ

Ax0 Ax1 Bx0 Ay0

By1 Az0

Az2

Bz1

Bz0 Bz2

Ay1 By0

Az1

Precharge

Command Bank B

(Precharge Temination)

Activate

Cammand

Bank A

Read

Command

Bank B

Activate

Command

Bank B

Read Read

Command Command

Read

Command

Bank B

Activate

Command

Bank B

Bank A

Read

Command

Bank A

Read

Command

Bank A

Don’t Care

Confidential

- 50/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 41. Full Page Random Column Write

(Burst Length=Full Page)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RBx

RBw

RAx

A0-A9,

A11

RBx CAx

CBx

CBy

CAz

CBz

CAy

t_WR

t_RP

DQM

DQ

t_RCD

t_RRD

Hi-Z

DAx0 DAx1 DBx0 DAy0

DAz1

DBz2

DAz2 DBz0 DBz1

DAy1 DBy0 DBy1 DAz0

Precharge

Command Bank B

(Precharge Temination)

Activate

Cammand

Bank A

Write

Command

Bank B

Activate

Command

Bank B

Write

CommandCommand

Bank B Bank A

Write

Command

Bank B

Activate

Command

Bank B

Write

Command

Bank A

Write

Command

Bank A

Write Data

are masked

Don’t Care

Confidential

- 51/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 42. Precharge Termination of a Burst

(Burst Length=4, 8 or Full Page, CAS# Latency=3)

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

CLK

High

CKE

CS#

RAS#

CAS#

WE#

BA0,1

A10

RAx

RAy

RAz

A0-A9,

A11

RAx

CAx

CAy

t_WR

t_RP

DQM

DQ

DAx0 DAx1

Ay0 Ay1 Ay2

Activate

Command

Bank A

Activate

Cammand

Bank A

Write

Command

Bank A

Precharge

Command

Bank A

Precharge

Command

Bank A

Read

Command

Bank A

Activate

Command

Bank A

Precharge Termination

of a Read Burst

Precharge Termination

of a Write Burst

Write Data are masked

Don’t Care

Confidential

- 52/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

Figure 43. 86 Pin TSOP II Package Outline Drawing Information

86

44

θ°

L

L¹

1

43

D

L

L1

e

y

B

S

Dimension in inch

Normal

－

Dimension in mm

Symbol

A

Min

－

Max

0.047

Min

－

Normal

－

Max

1.20

A1

A2

B

0.002

0.035

0.007

－

0.004

0.039

0.009

0.005

0.008

0.043

0.011

－

0.05

0.9

0.17

－

0.10

1

0.2

1.1

0.27

－

0.22

0.127

22.22

10.16

0.50

C

D

E

0.87

0.395

－

0.875

0.400

0.0197

0.88

0.405

－

22.09

10.03

－

22.35

10.29

－

e

HE

L

L1

0.455

0.016

－

0.463

0.020

0.0315

0.471

0.024

－

11.56

0.40

－

11.76

0.50

0.80

11.96

0.60

－

S

y

θ

0.024

－

0.61

－

0°

－

0.004

8°

－

0°

－

0.10

8°

－

Notes:

1. Dimension D&E do not include interlead flash.

2. Dimension B does not include dambar protrusion/intrusion.

3. Dimension S includes end flash.

4. Controlling dimension: mm

Confidential

- 53/54 -

Rev.1.0 Mar 2016

AS4C8M32S-6TIN

AS4C8M32S-7TCN

PART NUMBERING SYSTEM

AS4C

8M32S

6/7

T

C/I

N

C=Commercial

(0° Cꢀ70° C)

6= 166 MHz

7= 143 MHz

8M32=8Mx32

Indicates Pb and

Halogen Free

DRAM

T =TSOPII

I=Industrial

S=SDRAM

(-40° Cꢀ85° C)

Alliance Memory, Inc.

511 Taylor Way,

San Carlos, CA 94070

Tel: 650-610-6800

Fax: 650-620-9211

www.alliancememory.com

trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their

respective companies. Alliance reserves the right to make changes to this document and its products at any time

without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data

contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right

to change or correct this data at any time, without notice. If the product described herein is under development,

significant changes to these specifications are possible. The information in this product data sheet is intended to be

general descriptive information for potential customers and users, and is not intended to operate as, or provide, any

guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of

the application or use of any product described herein, and disclaims any express or implied warranties related to the

sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,

merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms

and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively

according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a

license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of

Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting

systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the

inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such

use and agrees to indemnify Alliance against all claims arising from such use.

Confidential

- 54/54 -

Rev.1.0 Mar 2016


型号：	AS4C8M32S-6TIN
厂家：	ALLIANCE SEMICONDUCTOR CORPORATION
描述：	Fully synchronous operation 动态存储器光电二极管内存集成电路
文件：	总54页 (文件大小：1849K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AS4C8M32S-6TIN [ALSC]

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