AS4LC1M16S0-10 [ALSC]
DRAM;
| 型号： | AS4LC1M16S0-10 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | DRAM 动态存储器 |
| 文件： | 总26页 (文件大小：576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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• Automatic and direct precharge
• Organization:
• Burst read, single write
• Can assert random column address in every cycle
• LVTTL compatible I/ O
1,048,576 words × 8 bits × 2 banks (2M×8)
524,288 words × 16 bits × 2 banks (1M×16)
• All signals referenced to positive edge of clock
• Dual internal banks controlled by A11 (bank select)
• High speed
- 125/ 100/ 83 MHz
- 6/ 7/ 8.5 ns clock access time
• Low power consumption
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP II (2M×8)
- 400 mil, 50-pin TSOP II (1M×16)
• Read/ write data masking
• Programmable burst length (1/ 2/ 4/ 8/ full page)
• Programmable burst sequence (sequential/ interleaved)
• Programmable CAS latency (1/ 2/ 3)
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/ O
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
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Pin(s)
Description
TSOP II
TSOP II
VCC
DQ0
DQ1
SSQ
DQ2
V
SS
VCC
DQ0
V
SS
1
2
3
4
5
6
7
8
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DQM (2M×8)
UDQM/ LDQM (1M×16)
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
DQ15
DQ14
DQ7
Output disable/ write mask
V
V
SSQ
SSQ
V
V
SSQ
DQ6
VCCQ
DQ1
VCCQ
DQ13
DQ12
VCCQ
DQ11
DQ10
A0 to A10
A11
Address inputs
Bank select
DQ3
VCCQ
DQ2
DQ5
V
V
SSQ
SSQ
DQ4
DQ5
DQ3
VCCQ
NC
DQ4
VCCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
9
DQ0 to DQ7 (2M×8)
DQ0 to DQ15 (1M×16)
Input/ output
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
SSQ
SSQ
DQ6
DQ7
VCCQ
DQ9
DQ8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
RAS
Row address strobe
Column address strobe
Write enable
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
CAS
WE
CS
Chip select
VCC, VCCQ
VSS, VSSQ
CLK
Power (3.3V ± 0.3V)
Ground
A4
V
SS
23
24
25
28
27
26
A4
Clock input
V
SS
CKE
Clock enable
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Symbol
fmax
tAC
AS4LC2M8S0-8
AS4LC2M8S0-10 AS4LC2M8S0-12 Unit
Bus frequency (CL = 3)
125
6
100
7
83.3
8.5
3.0
1.0
90
MHz
ns
Maximum clock access time (CL = 3)
Minimum input setup time
Minimum input hold time
tS
2
2
ns
tH
1.0
72
100
1
1.0
80
80
1
ns
Row cycle time (CL=3, BL=1)
Maximum operating current
tRC
ns
ICC1
75
mA
mA
Maximum CMOS standby current, self refresh ICC6
1
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The AS4LC2M8S0 and AS4LC1M16S0 are high performance 16 megabit CMOS Synchronous Dynamic Random Access Memories (SDRAM)
organized as 1,048,576 words × 8 bits × 2 banks and 524,288 words × 16 bits × 2 banks,respectively. Very high bandwidth is achi eved
using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable bu rst mode
can be used to read up to a full page of data (512 bytes for 2M×8 and 256 bytes for 1M×16) without selecting a new column address.
The two internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving operations. This
provides a significant advantage over asynchronous EDO and fast page mode devices.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type
(sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maxi mum
frequency of operation. This feature enables flexible performance optimization for a variety of applications.
DRAM commands and functions are decoded from control inputs. Basic commands are as follows:
• Mode register set
• Select column, write
• Auto precharge with read/ write
• De-activate bank
• Select column, read
• Self refresh
• Deactivate all banks
• Deselect, power down
• Select row, activate bank
• CBR refresh
Both devices are available in 400 mil plastic TSOP type 2 package. The AS4LC2M8S0 has 44 pins, and the AS4LC1M16S0 has 50 pins. Both
devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise and EMI. Inputs
and outputs are LVTTL compatible.
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CLK
Clock generator
CKE
A11
Bank select
A[10:0]
Row
address
buffer
†
Bank A
1M×8
(1024×512×8)
Mode register
Refresh
counter
†
Bank B
1M×8
(1024×512×8)
Sense amplifier
CS
Column decoder and
latch circuit
DQM
Column
address
buffer
RAS
CAS
Data control circuit
DQ
Burst
counter
WE
†
For AS4LC1M16S0, Banks A & B will read 1M×16 (1024×256×16).
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Parameter
Symbol
Min
3.0
0.0
2.0
–0.3†
2.4
–
Nominal
Max
Unit
V
VCC,VCCQ
GND
3.3
0.0
–
3.6
Supply voltage
Input voltage
0.0
V
V
VCC + 0.3
V
IH
V
–
0.8
–
V
IL
V
–
V
OH
Output voltage‡
V
–
0.4
70
V
OL
Ambient operating temperature
TA
0
°C
†
V
min = -1.5V for pulse widths less than 5 ns.
IL
‡
I
= -2mA, and I = 2mA
OL
OH
Recommended operating conditions apply throughout this document unless otherwise specified.
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Parameter
Symbol
V ,V
Min
-1.0
-1.0
-55
–
Max
Unit
V
Input voltage
+4.6
+4.6
+150
1
in out
Power supply voltage
Storage temperature (plastic)
Power dissipation
VCC,VCCQ
TSTG
PD
V
°C
W
Short circuit output current
Iout
–
50
mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions outside those indicated in the operational sections of this specification is notimplied. Exposure to absolute max-
imum rating conditions for extended periodsmay affect reliability.
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-10
-12
Parameter
Symbol Test conditions
Min Max Min Max Min Max Unit Notes
0V ≤ V ≤ VCC,
Pins not under test = 0V
in
Input leakage current
IIL
-5
-5
–
+5
+5
-5
-5
–
+5
+5
80
-5
-5
–
+5
+5
µA
µA
Output leakage current
IOL
DOUT disabled, 0V ≤ Vout ≤ VCCQ
Operating current (one
bank active)
t
RC ≥ min, IOL = 0mA, burst length =
1
ICC1
ICC2P
100
75 mA
1
CKE ≤ V (max), tCK = 15 ns
–
–
2.0
2.0
–
–
2.0
2.0
–
–
2.0 mA
2.0 mA
Precharge standby current
(power down mode)
IL
ICC2PS CKE & CLK ≤ V (max), tCK = ∞
IL
CS ≥ V (min), CKE ≥ V (min),
IH
IH
ICC2N
tCC = 15 ns; input signals changed
once during 30 ns
–
–
20
6
–
–
20
6
–
–
20 mA
Precharge standby current
(non-power-down mode)
CLK ≤ V (max), CKE ≥ V (min),
IL
IH
ICC2NS
6
mA
t
CK = ∞; input signals stabl
ICC3P
ICC3PS CLK, CKE ≤ V (max), tCK = ∞
CKE ≤ V (max), tCK = 15 ns
–
–
2
2
–
–
2
2
–
–
2
2
mA
mA
Active standby current
(power down mode)
IL
IL
CKE ≥ V (min), CS ≥ V (min),
IH
IH
ICC3N
t
CK = 15 ns; input signals changed
–
35
–
27
–
27 mA
Active standby current
(non power down mode,
one bank active)
once during 30 ns
CKE ≥ V (min), CLK ≥ V (max),
tCK = ∞; input signals stabl
IH
IL
ICC3NS
–
12
–
10
–
10 mA
110
IOL = 0 mA
Page burst
All banks activated
tCCD = tCCD(min)
CL =3
CL =2
CL =1
–
–
–
–
–
–
130
95
70
70
2
–
–
–
–
–
–
120
85
60
65
2
–
–
–
–
–
–
Operating current
(burst mode)
80
55
ICC4
mA 1,2
Refresh current
ICC5
t
RC ≥ tRC(min)
65 mA
3
4
2
1
mA
mA
Self refresh current
CL = CAS latency
CKE ≤ 0.2 V
ICC6
1
1
1
2
3
4
This parameter depends on output loading and cycle rates. Measured with outputs open, inputs only change one time during t (min).
CK
Assumed t
(min)
CCD
Refresh period = 64ms.
Low power version
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-10
-12
CAS
Symbol Parameter
latency
Min
16
20
20
48
72
1
Max
Min
20
26
26
50
80
1
Max
Min
24
30
30
60
90
1
Max
Unit Notes
tRRD
tRCD
tRP
Row active to row active delay
–
–
–
–
–
–
–
–
–
ns
ns
1
RAS to CAS delay time
1
Row precharge
ns
1
tRAS
tRC
Row active
100,000
100,000
100,000
ns
1
Row cycle time
–
–
–
–
–
ns
1
tCDL
tRDL
tBDL
tCCD
Last data in to new column address delay
Last data in to row precharge
Last data in to burst stop
Column address to column address delay
–
CLK
CLK
CLK
CLK
2
1
–
1
–
1
–
2
1
–
1
–
1
–
2
1
–
1
–
1
–
3
3
2
1
3
2
1
3
2
1
8
1000
10
14
28
–
1000
1000
1000
7
12
15
30
–
1000
1000
1000
8.5
9.0
25
–
4
tCK
tAC
tOH
CLK cycle time
10
20
–
1000
ns
ns
ns
4
1000
6
4
4,5
4,5
4,5
CLK to valid output delay
Output data hold time
–
6
–
8.5
23
–
–
–
16
–
–
–
3
3
3
3
–
3
–
3
–
3
–
3
–
3
–
tCH
tCL
tS
CLK high pulse width
CLK low pulse width
Input setup time
3
–
3.5
3.5
2
–
4
–
ns
ns
ns
ns
ns
6
6
6
6
5
3
–
–
4
–
2
–
–
3
–
tH
Input hold time
1
–
1
–
1
–
tSLZ
CLK to output in low Z
1
3
2
1
1
–
1
–
1
–
3
6
–
8
–
8
tSHZ
CLK to output in high Z
3
7
–
11
18
–
11
18
ns
3
15
–
–
1
2
3
4
5
6
Minimum clock cycles = (Minimum time / clock cycle time) rounded up
Minimum delay required to complete write.
Column address change allowed every cycle.
Parameters dependent on CAS latency.
If clock rising time > 1ns, (tr/ 2-0.5)ns should be added to parameter.
If (tr and tf) > 1ns, [(tr+tf)/ 2-1]ns should be added to parameter.
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Command
CKE
CKE
CS
RAS
L
CAS
L
WE
DQM A11
A10
A9–A0
Note
1,2
3
n-1
n
Mode register set
Auto refresh
Entry
H
X
H
L
L
L
L
L
L
X
X
X
X
X
Op code
H
H
L
L
H
H
H
X
H
X
X
X
X
L
L
3
Self
H
H
3
refresh
Exit
L
H
H
H
X
X
H
L
X
X
3
Bank activate
Read
L
H
X
V
row address
Auto precharge disable
Auto precharge enabl
Auto precharge disable
Auto precharge enabl
L
H
L
4
4,5
4
column
address
L
H
L
H
X
V
V
column
address
Write
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
H
4,5
6
Burst stop
Precharge
X
Selected bank
Both banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
X
X
X
X
X
X
V
X
X
Entry
Exit
H
L
L
H
L
Clock suspend or
active power down
X
X
H
L
Entry
H
Precharge power
down mode
X
H
L
Exit
L
H
H
H
X
X
DQM
X
H
L
X
X
X
7
No operation
command
X
1
OP = operation code
A0~A11 see page 8
2
3
MRS can be issued only when both banks are precharged. A new command can be issued 2 clock cycles after MRS.
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/ self refresh can only be issued after both banks are precharged.
4
5
A11: bank select address. If low during read, write, row active and precharge, bank A is selected.
If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge.
A new read/ write command cannot be issued during a burst read/ write with auto precharge.
It must be issued after the end of the burst. A new row active command can be issued after t from the end of the burst.
RP
6
7
Burst stop command valid at every burst length.
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
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Register programmed with
MRS
Address
A11~A10
RFU†
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Function
WBL
TM
CAS latency
burst length
†
RFU = 0 during MRS cycle.
Write burst length
A9 Length
Burst type
A3
0
Type
Sequential
Interleaved
Programmed
0
burst length
1
1
Single burst
Test mode
A8 A7
Type
0
0
1
1
0
1
0
1
Mode register set
Reserved
Reserved
Reserved
CAS latency
A6 A5
Burst length
A4
0
Latency
A2
0
A1
0
A0
0
BT = 0
BT = 1
0
0
0
0
1
0
0
1
1
X
Reserved
1
2
4
8
1
2
4
8
1
1
0
0
1
0
2
0
1
0
1
3
0
1
1
X
Reserved
1
X
X
Reserved† Reserved
†
Burst length = full page when A2~A0 = 1.
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Initial address
A1
0
A0
0
Sequential
Interleave
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
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Initial address
A2
0
A1
A0
0
Sequential
Interleave
0
0
1
1
0
0
1
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
0
1
0
0
0
1
1
0
1
1
1
0
1
1
3LQ#GHVFULSWLRQV#
Pin
Name
Description
All operations synchronized to rising edge of CLK.
CLK
System clock
Controls CLK input. If CKE is high, the next CLK rising edge is valid. If CKE is
low, the internal clock is suspended from the next clock cycle and the burst
address and output states are frozen. If both banks are idle and CKE goes low, the
SDRAM will enter power down mode from the next clock cycle. When in power
down mode and CKE is low, no input commands will be acknowledged.To exit
power down mode, raise CKE high before the rising edge of CLK.
CKE
Clock enable
Enables or disables device operation by masking or enabling all inputs except
CLK, CKE, DQM.
CS
Chip select
Address
Row and column addresses are multiplexed. Row address: A0~A10. Column
address (2M×8): A0~A8. Column address (1Mx16): A0~A7.
A0~A10
Memory cell array is organized in 2 banks. A11 selects which internal bank will
be active. A11 is latched during bank activate, read, write, mode register set,
and precharge operations. Asserting A11 low selects Bank A; A11 high selects
Bank B.
A11
Bank select
Enables row access and precharge operation. When RAS is low, row address is
latched at the rising edge of CLK.
RAS
CAS
WE
Row address strobe
Enables column access. When CAS is low, column address is latched at the rising
edge of CLK.
Column address strobe
Write enable
Enables write operation and row precharge operation. When WE is low, input
data is latched starting from CAS.
Controls I/ O buffers. When DQM is high, output buffers are disabled during a
DQM
Output disable/ write mask read operation and input data is masked during a write operation. DQM latency
is 2 clocks for Read and 0 clocks for Write.
DQ0~DQ15 Data input/ output
VDD/ VSS Power supply/ ground
VDDQ/ V
Data inputs/ outputs are multiplexed.
Power and ground for core logic and input buffers.
Data output power/ ground Power and ground for data output buffers.
SSQ
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Command
Pin settings
Description
The following sequence is recommended prior to normal operation.
1. Apply power, start clock, and assert CKE and DQM high. All other signals
are NOP.
2. After power-up, pause for a minimum of 200µs. CKE/ DQM = high; all oth-
ers NOP.
Power up
3. Precharge both banks.
4. Perform Mode Register Set command to initialize mode register.
5. Perform a minimum of 8 auto refresh cycles to stabilize internal circuitry.
(Steps 4 and 5 may be interchanged.)
The mode register stores the user selected opcode for the SDRAM operating
modes. The CAS latency, burst length, burst type, test mode and other vendor
specific functions are selected/ programmed during the Mode Register Set
command cycle. The default setting of the mode register is not defined after
power-up. Therefore, it is recommended that the power-up and mode register
set cycle be executed prior to normal SDRAM operation. Refer to the Mode
Register Set table and timing for details.
Moderegister CS = RAS = CAS = WE =
set
low; A0~A11 = opcode
The SDRAM performs a "no operation" (NOP) when RAS, CAS, and WE = high.
Since the NOP performs no operation, itmay be used as a wait state in
performing normal SDRAM functions. The SDRAM is deselected when CS is
high. CS high disables the command decoder such that RAS, CAS, WE and
address inputs are ignored. Device deselection is also considered a NOP.
Device
deselect and CS = high
no operation
CS = RAS = low; CAS = WE The SDRAM is configured with two internal banks. Use the Bank Activate
= high; A0~A10 = row command to select a row in one of the two idle banks. Initiate a read or write
address; A11 = bank select operation after tRCD(min) from the time of bank activation.
Bank
activation
Use the Burst Read command to access a consecutive burst of data from an
CS = CAS = A10 = low;
active row in an active bank. Burst read can be initiated on any column address
RAS = WE = high; A11 =
of an active row. The burst length, sequence and latency are determined by the
bank select, A0~A8 =
mode register setting. The first output data appears after the CAS latency from
column address; (A9 =
Burst read
the read command. The output goes into a high impedance state at the end of
don’t care for 2M×8;
the burst (BL = 1,2,4,8) unless a new burst read is initiated to form a gapless
A8,A9 = don’t care for
output data stream. Terminate the burst with a burst stop command, precharge
1M×16)
command to the same bank or another burst read/ write
CS = CAS = WE = A10 =
Use the Burst Write command to write data into the SDRAM on consecutive
low; RAS = high; A0~A9 = clock cycles to adjacent column addresses. The burst length and addressing
column address; (A9 =
don’t care for 2M×8;
A8,A9 = don’t care for
1M×16)
mode is determined by the mode register opcode. Input the initial write address
in the same clock cycle as the Burst Write command. Terminate the burst with a
burst stop command, precharge command to the same bank or another burst
read/ write. DQM can also be used to mask the input data.
Burst write
Use DQM to mask input and output data. It disables the output buffers in a read
operation and masks input data in a write operation. The output data is invalid 2
clocks after DQM assertion (2 clock latency). Input data is masked on the same
clock as DQM assertion (0 clock latency).
DQM
operation
CS = WE = low; RAS = CAS Use burst stop to terminate burst operation. This command may be used to
Burst stop
= high
terminate all legal burst lengths.
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Command
Pin settings
Description
The Bank Precharge command precharges the bank specified by A11. The
precharged bank is switched from active to idle state and is ready to be activated
again. Assert the precharge command after tRAS(min) of the bank activate
command in the specified bank. The precharge operation requires a time of
tRP(min) to complete.
CS = A10 = RAS = WE =
low; CAS = high; A11 =
bank select; A0~A9 = don’t
care
Bank
precharge
CS = RAS = WE = low; CAS
Precharge all = A10 = high; A11 = bank
select; A0~A9 = don’t care
The Precharge All command precharges both banks simultaneously. Both banks
are switched to the idle state on precharge completion.
CS = CAS = WE (write) =
low; RAS = WE (read) =
A10 = high; A11 = bank
During auto precharge, the SDRAM adjusts internal timing to satisfy tRAS(min)
and tRP for the programmed CAS latency and burst length. Couple the auto
precharge with a burst read/ write operation by asserting A10 to a high state at
the same time the burst read/ write commands are issued. At auto precharge
completion, the specified bank is switched from active to idle state. Note that no
new commands can be issued until the specified bank achieves the idle state
Auto
select; A0~A9 = column
precharge
address; (A9 = don’t care
for 2M×8; A8,A9 = don’t
care for 1M×16)
When CKE is low, the internal clock is frozen or suspended from the next clock
cycle and the state of the output and burst address are frozen. If both banks are
idle and CKE goes low,the SDRAM enters power down mode at the next clock
cycle. When in power down mode, no input commands are acknowledged as
long as CKE remains low. To exit power down mode, raise CKE high before the
rising edge of CLK.
Clock
suspend/
CKE = low
power down
mode entry
Clock
Resume internal clock operation by asserting CKE high before the rising edge of
CLK. Subsequent commands can be issued one clock cycle after the end of the
Exit command.
suspend/
CKE = high
power down
mode exit
SDRAM storage cells must be refreshed every 64ms to maintain data integrity.
Use the Auto Refresh command to accomplish the refreshing of all rows in both
banks of the SDRAM. The row address is provided by an internal counter which
CS = RAS = CAS = low; WE increments automatically. Auto refresh can only be asserted when both banks are
Auto refresh = CKE = high; A0~A11 = idle and the device is not in the power down mode. The time required to
don’t care
complete the auto refresh operation is tRC(min). Use NOPs in the interim until
the auto refresh operation is complete. This is the most common refresh mode.
It is typically performed once every 15.6us or in a burst of 4096 auto refresh
cycles every 64ms. Both banks will be in the idle state after this operation.
Self refresh is another mode for refreshing SDRAM cells. In this mode, refresh
address and timing are provided internally. Self refresh entry is allowed only
when both banks are idle. The internal clock and all input buffers with the
exception of CKE are disabled in this mode. Exit self refresh by restarting the
external clock and then asserting CKE high. NOP’s must follow for a time of
CS = RAS = CAS = CKE =
low; WE = high; A0~A11
= don’t care
Self refresh
t
RC(min) for the SDRAM to reach the idle state where normal operation is
allowed. If burst auto refresh is used in normal operation, burst 4096 auto
refresh cycles immediately after exiting self refresh.
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CLK
CMD
PRE
MRS
ACT
tRP
tRSC(min)
MRS can be issued only when both banks are idle.
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Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after t RP.. The earliest assertion of the precharge
command without losing any burst data is show below.
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CLK
CMD
WE
PRE
DQ
D
D
D
D
3
0
1
2
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CLK
CMD
DQ(CL1)
DQ(CL2)
DQ(CL3)
Read data
PRE
Q0
Q1
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Q
3
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
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0
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A10 controls the selection of auto precharge during the read or write command cycle.
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CLK
CMD
WE
DQ
D
D
D
D
3
0
1
2
Auto precharge starts*
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CLK
CMD
Read data
DQ(CL1)
DQ(CL2)
DQ(CL3)
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
3
0
1
2
Auto precharge starts*
*The row active command of the precharge bank can be issued after t from this point. The new read/ write command of another activated bank can be
RP
issued from this point. At burst read/ write with auto precharge, CAS interrupt of the same/ another bank is illegal.
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CLK external
CLK internal
CKE
DQM
DQ
Q
Q
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Q
Q
Q
7
1
2
3
4
6
OPEN
OPEN
CLK external
CLK internal
CKE
DQM
DQ
Q
Q
2
Q
Q
Q
6
1
3
4
OPEN
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CLK external
CLK internal
CKE
DQM
DQ
Q
1
Q
Q
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4
Q
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5
2
3
6
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CLK external
CLK internal
CKE
DQM
DQ
D1
D2
D6
D6
D6
D3
D5
DQM Mask
CKE Mask
CLK external
CLK internal
CKE
DQM
DQ
D1
D2
D3
D5
DQM Mask
CKE Mask
CLK external
CLK internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
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CLK
CMD
Read data
Read data
B
ADD
A
DQ (CL1)
DQ (CL2)
DQ (CL3)
QA
QB
QB
QB
QB
3
0
0
1
2
QA
QB
QB
QB
QB
3
0
0
1
2
QA
QB
QB
QB
QB
3
0
0
1
2
tCCD
t
= CAS to CAS delay (= 1 CLK)
CCD
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CLK
tCCD
CMD
Write data
Write data
ADD
DQ
A
B
0
0
DA
DB
DB
DB
DB
3
0
0
1
2
tCDL
t
t
= CAS to CAS delay (= 1 CLK)
CCD
= last address in to new column addres delay (= 1 CLK)
CDL
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CLK
tCCD
CMD
Write data
A
Read data
B
ADD
DQ (CL1)
DQ (CL2)
DQ (CL3)
DA
QB
QB
QB
QB
3
0
0
1
2
DA
QB
QB
QB
QB
3
0
0
1
2
DA
QB
QB
QB
QB
3
0
0
1
2
tCDL
t
t
= CAS to CAS delay (= 1 CLK)
CCD
= last address in to new column addres delay (= 1 CLK)
CDL
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CLK
CMD1
DQM1
DQ1
Read data
Read data
Read data
Write data
D
D
D
D
3
0
1
2
CMD2
DQM2
DQ2
Write data
D
D
D
D
3
0
1
2
CMD3
DQM3
DQ3
Write data
Q
D
D
D
D
3
Q
1
0
1
2
0
To prevent bus contention, maintain a gap between data in and data out.
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CLK
CMD1
Read data Write data
DQM1
DQ1
D
D
D
D
3
0
1
2
CMD2
DQM2
DQ2
Read data
Read data
Read data
Write data
D
D
D
D
3
0
1
2
CMD3
DQM3
DQ3
Write data
D
D
D
D
3
0
1
2
CMD4
DQM4
DQ4
Write data
Q
D
D
D
D
3
0
1
2
0
To prevent bus contention, maintain a gap between data in and data out.
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CLK
CMD1
DQM1
Read data Write data
DQ1
CMD2
DQM2
DQ2
D
D
D
D
3
0
1
2
Read data
Read data
Read data
Write data
D
D
D
D
3
0
1
2
CMD3
DQM3
DQ3
Write data
D
D
D
D
3
0
1
2
CMD4
DQM4
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Write data
D
D
D
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3
0
1
2
To prevent bus contention, maintain a gap between data in and data out.
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Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read
cycle, burst read data is terminated and the data bus goes to Hi-Z after CAS latency. When Burst Stop is asserted during the write cycle, burst
write data is terminated and the databus goes to HI-Z simultaneously.
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CLK
CMD
Read data
Burst stop
DQ (CL = 1)
DQ (CL = 2)
DQ (CL = 3)
Q
Q
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2
0
1
Q
Q
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0
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Q
Q
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DQ
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DQ
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A Precharge command terminates a burst read/ write operation during the read cycle. The same bank can be activated after meeting tRP.
UHDG#F\FOH#+&/# #4,#
CLK
CMD
Read data
PRE
ACT
DQ
Q
Q
Q
Q
3
0
1
2
tRP
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CLK
CMD
DQ
Read data
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ACT
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2
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CLK
CMD
DQ
Read data
PRE
ACT
Q
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Write data
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ACT
DQ
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4
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2
3
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CLK
tRP
tRC
tRC
CS
RAS
CAS
WE
A10
A0-A9
DQM
CKE
DQ
Precharge both banks
Auto refresh
Auto refresh
Auto refresh
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CLK
CS
RAS
CAS
WE
A11
A0-A10
DQM
CKE
DQ
tRC
Self refresh cycle
Precharge both banks
Arbitrary cycle
Self refresh entry
Self refresh exit
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+&/# #6,#
CLK
CS
RAS
CAS
WE
A11
A10
RA
RA
a
a
A0-A9
DQM
CKE
RA
RA
a
CA
x
CA
a
a
DQ
Active standby
Precharge standby
Bank activate
NOP
Power down mode exit
NOP Bank activate
Power down mode
Power down mode
Power down mode entry
Enter power down mode by pulling CKE low.
Power down mode entry
Power down mode exit
All input/ output buffers (except CKE buffer) are turned off in power down mode.
When CKE goes high, command input must be equal to no operation at next CLK rising edge.
5HDG2ZULWH#ZDYHIRUP
+%/# #;/#&/# #6,#
CLK
tRAS
CS
RAS
CAS
WE
A11
tRCD
A10
RA
a
RA
b
A0-A9
RA
CA
a
CA
RA
b
a
b
DQM
CKE
DQ
tRP
A
A
A
A
A
A
A
A
A
A
A
A
b5
a0
a1
a2
a3
a4
a5
b0
b1
b2
b3
b4
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Bank activate
Bank activate
Read
Precharge
Write
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A10
RA
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A9
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d
a
a
b
c
DQM
CKE
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d3
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a4
a5
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Single
Write
Q
Q
Q
Q
Activate
Q
Q
Q
Q
Read
Read
D
D
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tRAS
tCCD
tCCD
CS
RAS
CAS
WE
A11
tRCD
tRCD
A10
A0-A9
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RB
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a
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b
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a
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c
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Read
Precharge
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RAS
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tRP
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tRP
tRCD
tRRD
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tRCD
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Bank A:
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Precharge
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A11
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RAS
tRAS
tRP
tRAS
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CAS
tRCD
tRCD
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A11
A10
RA
a
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a1
a4
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Bank B
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Precharge
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Precharge
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tRP
tRAS
tRAS
CAS
WE
tRCD
tRCD
tRCD
A11
A10
RA
a
RB
RA
c
b
A9
RA
RA
CA
RB
CA
b
CA
c
a
a
b
c
DQM
CKE
DQ
DA DA
DA DA DA DA DB DBb1 DB DB
DB DB DB DB DA DA DA
a0
a1
a4
a5
a6
a7
b0
b2
b3
b4
b5
b6
b7
c0
c1
c2
Write
AP Bank A
Write
Active
Write
Bank A Active
Bank B
AP Bank B
Active
AP = internal precharge begins
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50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
44-pin TSOP II
50-pin TSOP II
Min
Max
Min
Max
(mm)
(mm)
(mm)
(mm)
A
–
1.2
–
1.2
TSOP II
E He
A
0.05
0.95
0.30
0.05
0.95
1
A
1.05
0.45
1.05
0.45
2
b
0.30
c
D
E
He
e
0.127 (typical)
0.12
0.21
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
18.28
10.03
11.56
18.54
10.29
11.96
20.85
10.03
11.56
21.05
10.29
11.96
D
l
0.80 (typical)
0.40 0.60
0.80 (typical)
l
0.40
0.60
A
2
A
0–5°
A
1
b
e
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- Input reference levels of VIH = 2.4V and V = 0.4V
IL
- Output reference levels = 1.4V
- Input rise and fall times: 2 ns
+1.4V
50Ω
CLOAD = 50 pF
Z0 = 50Ω
Dout
Figure A: Equivalent output load
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Parameter
Symbol
Signals
Max
Unit
C
A0 to A11
4
pF
IN1
Input capacitance
I/ O capacitance
C
DQM, RAS, CAS, WE, CS, CLK, CKE,
4
pF
IN2
DQ0 to DQ7 (2M×8)
DQ0 to DQ15 (1M×16)
C
5
pF
I/ O
2UGHULQJ#LQIRUPDWLRQ
Package \ 1/ frequency
8 ns
10 ns
12 ns
AS4LC2M8S0-12TC
TSOP II, 400 mil, 44-pin
TSOP II, 400 mil, 50-pin
AS4LC2M8S0-8TC
AS4LC1M16S0-8TC
AS4LC2M8S0-10TC
AS4LC1M16S0-10TC
AS4LC1M16S0-12TC
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AS4
LC
XXXS0
–XX
T
C
Device number for
synchronous
DRAM
Package (device dependent):
TSOP II 400 mil, 44 pin
TSOP II 400 mil, 50 pin
Commercial temperature
range, 0°C to 70 °C
DRAM prefix
LC = 3.3V CMOS
1/ frequency
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