AS4LC1M16S0 [ALSC]
3.3V 2M × 8/1M × 16 CMOS synchronous DRAM; 3.3V 2M × 8 / 1M × 16的CMOS同步DRAM
| 型号： | AS4LC1M16S0 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 2M × 8/1M × 16 CMOS synchronous DRAM |
| 文件： | 总29页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS4LC2M8S1
AS4LC2M8S0
AS4LC1M16S1
AS4LC1M16S0
May 2001
Preliminary
®
3.3V 2M × 8/1M × 16 CMOS synchronous DRAM
Features
• Organization
- 1,048,576 words × 8 bits × 2 banks (2M × 8)
11 row, 9 column address
- 524,288 words × 16 bits × 2 banks (1M × 16)
11 row, 8 column address
• All signals referenced to positive edge of clock, fully
synchronous
• Dual internal banks controlled by A11 (bank select)
• High speed
- 143/125/100 MHz
- 7/8/10 ns clock access time
• Low power consumption
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/O
• 2048 refresh cycles, 32 ms refresh interval
• 4096 refresh cycles, 64 ms refresh interval
• Auto refresh and self refresh
• PC100 functionality
• Automatic and direct precharge including concurrent
autoprecharge
• Burst read, write/Single write
• Random column address assertion in every cycle, pipelined
operation
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP 2 (2M × 8)
- 400 mil, 50-pin TSOP 2 (1M × 16)
• Read/write data masking
• Programmable burst length (1/2/4/8/ full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (1/2/3)
Pin arrangement
Pin designation
TSOP 2
50
TSOP 2
Pin(s)
Description
V
V
SS
V
V
SS
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CC
1
CC
DQ0
DQ1
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
DQ15
DQ14
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DQ0
DQ7
2
DQM (2M × 8)
UDQM/LDQM (1M × 16)
V
V
3
SSQ
SSQ
Output disable/write mask
V
V
SSQ
SSQ
DQ6
4
DQ1
DQ13
V
V
DQ2
DQ3
5
CCQ
CCQ
DQ12
RA0 – 10
Address inputs CA0 – 7 (×16)
CA0 – 8 (×8)
DQ2
DQ5
6
V
V
V
V
CCQ
DQ4
DQ5
CCQ
7
SSQ
SSQ
A0 to A10
A11
DQ11
DQ10
DQ3
DQ4
8
V
V
CCQ
NC
9
CCQ
V
V
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
SSQ
SSQ
DQ6
DQ7
DQ9
DQ8
NC
WE
CAS
NC
DQM
CLK
Bank address (BA)
V
V
CCQ
CCQ
DQ0 to DQ7 (2M × 8)
DQ0 to DQ15 (1M × 16)
LDQM
Input/output
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
RAS
CS
A11
A10
A0
A1
A2
A3
CKE
NC
A9
A8
A7
A6
A5
A4
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
RAS
CAS
Row address strobe
Column address strobe
Write enable
WE
V
V
CC
SS
CS
Chip select
23
24
25
28
27
26
A4
VCC, VCCQ
VSS, VSSQ
CLK
Power (3.3V 0.3V)
Ground
V
V
CC
SS
LEGEND
2M × 8
1M × 16
512K × 16 × 2 banks
2K/4K
Configuration
Refresh Count
Row Address
Bank Address
Column Address
1M × 8 × 2 banks
2K/4K
Clock input
(A0 – A10)
2 (BA)
512 (A0 – A8)
(A0 – A10)
2 (BA)
256 (A0 – A7)
CKE
Clock enable
Selection guide
Symbol
fMax
tAC
–7
143
5.5
2
–8
125
6
–10
100
6
Unit
MHz
ns
Bus frequency (CL = 3)
Maximum clock access time (CL = 3)
Minimum input setup time
Minimum input hold time
tS
2
2
ns
tH
1.0
70
1.0
80
1.0
80
ns
Row cycle time (CL = 3, BL = 1)
tRC
ns
Maximum operating current ([×16], RD or
ICC1
130
1
100
1
100
mA
mA
WR, CL = 3), BL = 2
Maximum CMOS standby current, self refresh
ICC6
1
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Copyright ©Alliance Semiconductor. All rights reserved.
AS4LC2M8S1
AS4LC1M16S1
®
Functional description
The AS4LC2M8S1, AS4LC2M8S0, and AS4LC1M16S1, AS4LC1M16S0 are high-performance 16-megabit CMOS Synchronous Dynamic
Random Access Memory (SDRAM) devices organized as 1,048,576 words × 8 bits × 2 banks (2048 rows × 512 columns) and 524,288
words × 16 bits × 2 banks (2048 rows × 256 columns), respectively. Very high bandwidth is achieved using a pipelined architecture where
all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page
of data (512 bytes for 2M × 8 and 256 bytes for 1M × 16) without selecting a new column address.
The operational advantages of an SDRAM are as follows: (1) the ability to synchronously output data at a high clock frequency with
automatic increments of column-address (burst access); (2) bank-interleaving, which hides precharge time and attains seamless operation;
and (3) the capability to change column-address randomly on every clock cycle during burst access.
This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type
(sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum
frequency of operation. This feature enables flexible performance optimization for a variety of applications.
SDRAM commands and functions are decoded from control inputs. Basic commands are as follows:
• Mode register set
• Deactivate bank
• Select column; read
• Self-refresh
• Deactivate all banks
• Select row; activate bank
• CBR refresh
• Select column; write
• Deselect; power down
• Auto precharge with read/write
Both devices are available in 400-mil plastic TSOP type 2 package. The AS4LC2M8S1/ AS4LC2M8S0 have 44 pins, and the AS4LC1M16S1/
AS4LC1M16S0 have 50 pins. All devices operate with a power supply of 3.3V 0.3V. Multiple power and ground pins are provided for low
switching noise and EMI. Inputs and outputs are LVTTL compatible.
Logic block diagram
CLK
Clock generator
CKE
A11
Bank select
A[10:0]
Row
address
buffer
Bank A†
16 (2048
512K
512K
×
×
×
256
256
×
×
16)
16)
Mode register
Refresh
counter
Bank B†
16 (2048
×
Sense amplifier
DQMU/DQML
CS
Column decoder and
latch circuit
Column
address
buffer
RAS
CAS
Data control circuit
DQ
Burst
counter
WE
† For AS4LC2M8S1/AS4LC2M8S0, Banks A and B will read 1M × 8 (2048 × 512 × 8).
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AS4LC2M8S1
AS4LC1M16S1
®
Pin descriptions
Pin
Name
Description
CLK
System clock
All operations synchronized to rising edge of CLK.
Controls CLK input. If CKE is high, the next CLK rising edge is valid.
If CKE is low, the internal clock is suspended from the next clock
cycle and the burst address and output states are frozen. If both banks
are idle and CKE goes low, the SDRAM will enter power down mode
from the next clock cycle. When in power down mode and CKE is
low, no input commands will be acknowledged. To exit power down
mode, raise CKE high before the rising edge of CLK.
CKE
Clock enable
Enables or disables device operation by masking or enabling all inputs
except CLK, CKE, UDQM/LDQM (×16), DQM (×8).
CS
Chip select
Address
Row and column addresses are multiplexed. Row address: A0~A10.
Column address (2M × 8): A0~A8. Column address (1M × 16):
A0~A7.
A0~A10
Memory cell array is organized in 2 banks. A11 selects which internal
bank will be active. A11 is latched during bank activate, read, write,
mode register set, and precharge operations. Asserting A11 low
selects Bank A; A11 high selects Bank B.
A11
Bank select
RAS
CAS
WE
Row address strobe
Column address strobe
Write enable
Command inputs.
RAS, CAS, and WE, along with CS, define the command being
entered.
Controls I/O buffers. When DQM is high, output buffers are disabled
during a read operation and input data is masked during a write
operation. DQM latency is 2 clocks for Read and 0 clocks for Write.
For ×16, LDQM controls the lower byte (DQ0 – 7) and UDQM
controls the upper byte (DQ8 – 15). UDQM and LDQM are
considered to be in the same state when referred to jointly as DQM.
×8: DQM
×16: UDQM, LDQM
Output disable/ write mask
DQ0~DQ15
VCC/VSS
Data input/output
Data inputs/outputs are multiplexed.
Power supply/ground
Power and ground for core logic and input buffers.
VCCQ/VSSQ
Data output power/ground Power and ground for data output buffers.
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AS4LC2M8S1
AS4LC1M16S1
®
Operating modes
Command
CKEn-1 CKEn
CS
L
RAS
L
CAS
L
WE DQM A11
A10 A9–A0 Note
Mode register set
H
H
H
X
H
L
L
X
X
X
X
X
X
Op code
1,2
3
Auto refresh
L
L
L
H
H
H
X
X
X
X
X
Entry
Exit
L
L
L
3
Self
refresh
L
H
X
H
X
3
L
H
X
X
H
L
3
Bank activate
H
H
L
H
H
V*
V
row address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
column
address
Read
L
H
L
H
X
column
address
Write
H
H
H
X
X
X
L
L
L
H
H
L
L
L
L
L
X
X
X
V
H
4,5
6
Burst stop
Precharge
H
H
X
Selected bank
Both banks
V
X
L
X
H
H
L
X
V
X
X
H
X
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
X
X
X
X
X
X
V
X
X
Entry
Exit
H
L
L
H
L
Clock suspend or
active power down
X
X
H
L
Entry
H
Precharge power
down mode
X
H
L
Exit
L
H
X
X
DQM
H
H
X
H
L
X
X
X
7
No operation command
X
* V = Valid.
1
OP= operation code.
A0~A11 see page 5.
2
3
MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles after MRS.
Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic.
Auto/self refresh can only be issued after both banks are precharged.
4
5
A11: bank select address. If low during read, write, row active and precharge, bank A is selected.
If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge.
A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge.
A new row active command can be issued after t from the end of the burst.
RP
6
7
Burst stop command valid at every burst length except full-page burst.
DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0).
Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2).
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AS4LC2M8S1
AS4LC1M16S1
®
Mode register fields
Register programmed with MRS
Address
Function
A11~A10 A9
RFU†
WBL
A8
A7
A6
A5
CAS latency
A4
A3
BT
A2
A1
A0
TM
Burst length
†
RFU = 0 during MRS cycle.
Write burst length
Burst type
A9
Length
A3
0
1
Type
Sequential
Interleaved
Programmed
burst length
0
1
Single burst
Test mode
A8 A7
Type
Mode register set
Reserved
0
0
1
1
0
1
0
1
Reserved
Reserved
CAS latency
Burst length
A6 A5
A4
0
1
0
1
Latency
Reserved
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
BT = 0
BT = 1
0
0
0
0
1
0
0
1
1
X
1
2
4
8
1
2
4
8
1
2
3
X
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full page Reserved
Burst sequence (burst length = 4)
Initial address
A1
0
0
1
1
A0
0
1
0
1
Sequential
Interleave
0
1
2
3
1
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
2
3
0
Burst sequence (burst length = 8)
Initial address
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Sequential
Interleave
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
2
3
4
5
6
7
0
3
4
5
6
7
0
1
1
2
3
4
5
6
7
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AS4LC2M8S1
AS4LC1M16S1
®
Recommended operating conditions
Parameter
Symbol
VCC,VCCQ
GND
VIH
Min
3.0
0.0
2.0
–0.3†
2.4
–
Nominal
Max
3.6
Unit
V
Notes
3.3
0.0
–
Supply voltage
Input voltage
0.0
V
VCC + 0.3
0.8
V
8
8
VIL
–
V
VOH
–
–
V
Output voltage‡
VOL
–
0.4
V
Ambient operating temperature
TA
0
70
°C
†
V
Min = –1.5V for pulse widths less than 5 ns.
IL
‡
I
= –2mA, and I = 2mA.
OH
OL
Recommended operating conditions apply throughout this document unless otherwise specified.
Absolute maximum ratings
Parameter
Symbol
VIN,VOUT
VCC,VCCQ
TSTG
Min
–1.0
–1.0
–55
–
Max
Unit
V
Notes
Input voltage
+4.6
+4.6
+150
1
Power supply voltage
V
Storage temperature (plastic)
Power dissipation
°C
W
PD
Short circuit output current
IOUT
–
50
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
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AS4LC2M8S1
AS4LC1M16S1
®
DC electrical characteristics
–7
–8
–10
Parameter
Symbol
IIL
Test conditions
0V ≤ VIN ≤ VCC,
Pins not under test = 0V
Min Max Min Max Min Max Unit Notes
Input leakage current
–5 +5 –5 +5 –5 +5 µA
Output leakage
current
IOL
DOUT disabled, 0V ≤ VOUT ≤ VCCQ
–10 +10 –10 +10 –10 +10 µA
1,3,
Operating current
(one bank active)
tRC ≥ min, IO = 0mA,
ICC1
CL =3
–
140
–
100
–
100 mA
burst length = 1
4,5
Precharge standby
current (power
down mode)
ICC2P
CKE ≤ VIL(max), tCK = 15 ns
CKE and CLK ≤ VIL(max), tCK = ∞
CS ≥ VIH(min), CKE ≥ VIH(min),
–
–
2.0
2.0
–
–
2.0
2.0
–
–
2.0 mA
2.0 mA
ICC2PS
ICC2N
t
CK = 15 ns; input signals changed
–
30
–
30
–
30 mA 1,2,3
Precharge standby
current (non-power-
down mode)
once during 30 ns
CLK ≤ VIL(max), CKE ≥ VIH(min),
CK = ∞; input signals stable
ICC2NS
–
6
–
6
–
6
mA 1,2,3
t
Active standby
current (power-
down mode)
ICC3P
CKE ≤ VIL(max), tCK = 15 ns
CLK, CKE ≤ VIL(max), tCK = ∞
–
–
2
2
–
–
2
2
–
–
2
2
mA 1,2,3
mA 1,2,3
ICC3PS
CKE ≥ VIH(min), CS ≥ VIH(min),
CK = 15 ns; input signals changed
once during 30 ns
Active standby
ICC3N
t
–
–
35
–
35
–
35 mA 1,2,3
current (non-power-
down mode, one
bank active)
CKE ≥ VIH(min), CLK ≥ VIL(max),
ICC3NS
10
–
10
–
10 mA 1,2,3
t
CK = ∞; input signals stable
IO = 0 mA
Page burst
All banks activated
CL =3
CL =2
140
125
–
–
130
115
–
–
120
1,2,
Operating current
(burst mode)
100
70
ICC4
mA
3,5
CL =1
80
–
–
70
90
–
–
t
CCD = tCCD(min)
1,2,
3,5
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
100
80 mA
2
1
–
–
2
1
–
–
2
1
mA
mA 15
Self refresh current
CKE ≤ 0.2 V
CL = CAS latency.
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AS4LC2M8S1
AS4LC1M16S1
®
AC parameters common to all waveforms
–7
–8
–10
CAS
Sym
Parameter
latency Min
Max
5.5
8.5
18
1
Min
–
Max
6
Min
–
Max
6
Unit
ns
Notes
6
3
2
1
–
–
–
–
2
0
tAC CLK to valid output delay
–
7
–
6
ns
6,8
6,8
7
–
22
1
–
22
1
ns
tAH Address hold time
tAS Address setup time
tBDL Last data-in to burst stop
–
–
ns
–
2
–
2
–
ns
7
–
0
–
0
–
tCK
9
Read/write command to
tCCD
1
1
–
–
1
1
–
–
1
1
–
–
tCK
tCK
9
9
read/write command
Last data-in to new
tCDL
column address delay
tCH CLK high-level width
2.75
7
–
3
8
–
3
–
ns
ns
ns
ns
7
3
2
1
1000
1000
1000
1000
1000
1000
10
12
25
1000
1000
1000
10
10
10
tCK CLK cycle time
8.7
20
10
25
CKE to CLOCK disable or
tCKED
1
–
1
–
1
–
tCK
power-down entry mode
tCKH CKE hold time
tCKS CKE setup time
tCL CLK low-level width
1
2
–
–
–
1
2
3
–
–
–
1
2
–
–
–
ns
ns
ns
2.75
3.5
7
CS, RAS, CAS, WE, DQM
hold time
tCMH
1
2
–
–
1
2
–
–
1
2
–
–
ns
ns
CS, RAS, CAS, WE, DQM
setup time
tCMS
3
2
1
5
5
4
1
2
1
–
–
–
–
–
–
5
5
4
1
2
1
–
–
–
–
–
–
5
5
4
1
2
1
–
–
–
–
–
–
tCK
tCK
tCK
ns
5,11
5,11
5,11
Data-in to ACTIVE
command
tDAL
tDH Data in hold time
tDPL Data in to PRECHARGE
tDQD DQM to input data delay
tCK
tCK
12
9
DQM to data mask during
writes
tDQM
0
–
0
–
0
–
tCK
9
9
DQM to data high Z
tDQZ
2
2
0
–
–
–
2
2
0
–
–
–
2
2
0
–
–
–
tCK
ns
during reads
tDS Data in setup time
Write command to input
data delay
tDWD
tCK
9
3
2
1
–
–
–
5.5
8.5
18
–
–
–
6
9
–
–
–
9
9
ns
ns
ns
13
13
13
Data-out high-impedance
time
tHZ
22
22
Data-out low-impedance
time
tLZ
1
–
1
–
1
–
ns
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P. 8 of 29
AS4LC2M8S1
AS4LC1M16S1
®
–7
–8
–10
CAS
Sym
Parameter
latency Min
Max
–
Min
2
Max
–
Min
2
Max
–
Unit
tCK
Notes
5
Load mode register to
active/refresh command
tMRD
2
3
2
1
2
2
2
–
–
–
2.5
2.5
2.5
–
–
–
3
3
3
–
–
–
ns
ns
ns
6
6
6
Output data hold time @
30 pF
tOH
CKE to CLOCK enable or
power-down exit mode
tPED
1
–
1
–
1
–
tCK
Active to precharge
command
tRAS
42 120,000
48
120,000
50
120,000 ns
tRC Active command period
tRCAR Auto refresh period
70
70
–
–
80
80
–
–
80
80
–
–
ns
ns
8
8
Active to read or write
delay
tRCD
3
3
–
–
3
–
–
3
–
–
tCK
ms
Refresh period—2048
rows
tREF
64
64
64
3
2
1
3
2
1
–
–
–
3
2
1
–
–
–
3
2
1
–
–
–
tCK
tCK
tCK
9
9
9
Data-out high Z from
tROH precharge/burst stop
command
Precharge command
period
tRP
3
3
–
–
3
–
–
3
–
–
tCK
ns
8
Active Bank A to Active
tRRD
14
16
20
Bank B command
tT Transition time
0.3
2
1.0
–
0.3
2
1.0
–
0.3
2
1.0
–
ns
tWR WRITE recovery time
tCK
Exit SELF REFRESH to
tXSR
70
–
80
–
80
–
ns
20
ACTIVE command
Notes
1
2
3
4
5
6
7
8
I
is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
DD
Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid V or V levels.
IH
IL
Address transitions average one transition every two-clock period.
The I current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-latency is reduced.
DD
t
= 7 ns for –7, 8 ns for –8, and 10 ns for –10.
CK
If clock t > 1 ns, (t – 0.5)ns should be added to the parameter.
r
r/2
If clock (t and t ) > 1 ns, [(t + t )/2 – 1] ns should be added to the parameter.
r
f
r
f
V
V
overshoot: V
= V
+ 2V for a pulse width ≤ 3 ns, and the pulse width cannot be greater than one third of the cycle rate. V undershoot:
IH
IH(max)
DDQ
IL
= –2V for a pulse width ≤ 3 ns and the pulse width cannot be greater than one third of the cycle rate.
IL(min)
9
Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter.
10 The clock frequency must remain constant during access or precharge states (READ, WRITE, including t and PRECHARGE commands). CKE may be
WR
used to reduce the data rate.
11 Timing actually specified t plus t ; clock(s) specified as a reference only at minimum cycle rate.
WR
RP
12 Timing actually specified by t
.
WR
13
t
defines the time at which the output achieves the open circuit condition; it is not a reference to V or V . The last valid data element will meet t
HZ OH OL OH
before going to HIGH-Z.
14 CLK must be toggled a minimum of two times during this period.
15 Enables on-chip refresh and address counters.
16 All voltages referenced to V .
SS
17 The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0° C ≤ T ≤ 70° C) is
A
endured.
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P. 9 of 29
AS4LC2M8S1
AS4LC1M16S1
®
18 A proper power-up initialization sequence (as described on page 10) is needed before proper device operation is ensured. (V and V
must be
DD
DDQ
powered up simultaneously. V and V must be at the same potential.)Two AUTOREFRESH command wake-ups should be repeated any time the t
SS
SSQ
REF
refresh requirement is exceeded.
19 AC characteristics assume t = 1 ns.
T
20 In addition to meeting the transition rate specification, the clock and CKE must transit between V and V (or between V and V ) in a monotonic
IH
IL
IL
IH
manner.
21 AC timing and I tests have V = 0V and V = 3.0 V with timing referenced to 1.4V crossover point.
DD
IL
IH
22
I
specifications are tested after the device is properly initialized.
DD
23 Minimum clock cycles = (minimum time/clock cycle time) rounded up.
Device operation
Command
Power up
Pin settings
Description
The following sequence is recommended prior to normal operation.
1
Apply power, start clock, and assert CKE and DQM high. All other
signals are NOP.
After power-up, pause for a minimum of 200µs. CKE/DQM =
high; all others NOP.
2
3
4
5
Precharge both banks.
Perform Mode Register Set command to initialize mode register.
Perform a minimum of 8 auto refresh cycles to stabilize internal
circuitry.
(Steps 4 and 5 may be interchanged.)
The mode register stores the user selected opcode for the SDRAM
operating modes. The CAS latency, burst length, burst type, test mode
and other vendor specific functions are selected/programmed during
CS = RAS = CAS = WE = low; the Mode Register Set command cycle. The default setting of the mode
Mode register set
A0~A11 = opcode
register is not defined after power-up. Therefore, it is recommended
that the power-up and mode register set cycle be executed prior to
normal SDRAM operation. Refer to the Mode Register Set table and
timing for details.
The SDRAM performs a “no operation” (NOP) when RAS, CAS, and
WE = high. Since the NOP performs no operation, it may be used as a
wait state in performing normal SDRAM functions. The SDRAM is
deselected when CS is high. CS high disables the command decoder
such that RAS, CAS, WE and address inputs are ignored. Device
deselection is also considered a NOP.
Device deselect and
no operation
CS = high, or
RAS, CAS, WE = high
The SDRAM is configured with two internal banks. Use the Bank
Activate command to select a row in one of the two idle banks. Initiate
a read or write operation after tRCD(min) from the time of bank
activation.
CS = RAS = low; CAS = WE =
high; A0~A10 = row address;
A11 = bank select
Bank activation
Use the Burst Read command to access a consecutive burst of data from
an active row in an active bank. Burst read can be initiated on any
column address of an active row. The burst length, sequence and
latency are determined by the mode register setting. The first output
data appears after the CAS latency from the read command. The output
goes into a high impedance state at the end of the burst (BL = 1,2,4,8)
unless a new burst read is initiated to form a gapless output data
stream. A full-page burst does not terminate automatically at the end of
the burst. Terminate the burst with a burst stop command, precharge
command to the same bank or another burst read/write
CS = CAS = A10 = low; RAS =
WE = high; A11 = bank select,
A0~A8 = column address; (A9
= don’t care for 2M × 8; A8,
A9 = don’t care for 1M × 16)
Burst read
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AS4LC2M8S1
AS4LC1M16S1
®
Command
Burst write
Pin settings
Description
Use the Burst Write command to write data into the SDRAM on
consecutive clock cycles to adjacent column addresses. The burst
length and addressing mode is determined by the mode register
opcode. Input the initial write address in the same clock cycle as the
Burst Write command. Burst terminate behavior for write is the same
as that for read. Terminate the burst with a burst stop command,
precharge command to the same bank or another burst read/write.
DQM can also be used to mask the input data.
CS = CAS = WE = A10 = low;
RAS = high; A0~A9 = column
address; (A9 = don’t care for
2M × 8; A8, A9 = don’t care
for 1M × 16)
Use DQM to mask input and output data. It disables the output buffers
in a read operation and masks input data in a write operation. The
output data is invalid 2 clocks after DQM assertion (2 clock latency).
Input data is masked on the same clock as DQM assertion (0 clock
latency).
UDQM/LDQM (×16)
DQM (×8) operation
CS = WE = low; RAS = CAS = Use burst stop to terminate burst operation. This command may be
Burst stop
high
used to terminate all legal burst lengths.
The Bank Precharge command precharges the bank specified by A11.
CS = A10 = RAS = WE = low; The precharged bank is switched from active to idle state and is ready
CAS = high; A11 = bank to be activated again. Assert the precharge command after tRAS(min) of
Bank precharge
select; A0~A9 = don’t care the bank activate command in the specified bank. The precharge
operation requires a time of tRP(min) to complete.
CS = RAS = WE = low; CAS =
The Precharge All command precharges both banks simultaneously.
A10 = high; A11, A0~A9 =
Precharge all
Both banks are switched to the idle state on precharge completion.
don’t care
During auto precharge, the SDRAM adjusts internal timing to satisfy
t
RAS(min) and tRP for the programmed CAS latency and burst length.
Write: CS = CAS = WE = low ;
Read: CS = CAS = low;
Couple the auto precharge with a burst read/write operation by
asserting A10 to a high state at the same time the burst read/write
commands are issued. At auto precharge completion, the specified
bank is switched from active to idle state. Note that no new commands
(RD/WR/DEAC) can be issued to the same bank until the specified
bank achieves the idle state. Auto precharge does not work with full-
page burst.
A10 = high; A11 = bank select
A0~A9 = column address;
;
Auto precharge
(A9 = don’t care for 2M × 8; A8,
A9 = don’t care for 1M × 16)
When CKE is low, the internal clock is frozen or suspended from the
next clock cycle and the state of the output and burst address are
frozen. If both banks are idle and CKE goes low, the SDRAM enters
power down mode at the next clock cycle. When in power down
mode, no input commands are acknowledged as long as CKE remains
low. To exit power down mode, raise CKE high before the rising edge
of CLK.
Clocksuspend/power
down mode entry
CKE = low
CKE = high
Resume internal clock operation by asserting CKE high before the
rising edge of CLK. Subsequent commands can be issued one clock
cycle after the end of the Exit command.
Clocksuspend/power
down mode exit
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P. 11 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Command
Pin settings
Description
SDRAM storage cells must be refreshed every 64 ms to maintain data
integrity. Use the auto refresh command to accomplish the refreshing
of all rows in both banks of the SDRAM. The row address is provided
CS = RAS = CAS = low; WE = by an internal counter which increments automatically. Auto refresh
CKE = high; A0~A11 = don’t can only be asserted when both banks are idle and the device is not in
Auto refresh
care
the power down mode. The time required to complete the auto refresh
operation is tRC(min). Use NOPs in the interim until the auto refresh
operation is complete. Both banks will be in the idle state after this
operation.
Self refresh is another mode for refreshing SDRAM cells. In this mode,
refresh address and timing are provided internally. Self refresh entry is
allowed only when both banks are idle. The internal clock and all input
CS = RAS = CAS = CKE = low; buffers with the exception of CKE are disabled in this mode. Exit self
WE = high; A0~A11 = don’t refresh by restarting the external clock and then asserting CKE high.
Self refresh
care
NOPs must follow for a time of tRC(min) for the SDRAM to reach the
idle state where normal operation is allowed. If burst auto refresh is
used in normal operation, burst 2048 auto refresh cycles immediately
after exiting self refresh.
Initialize and load mode register
T0
T1
Tn
Tm
Tp+1
Tp+2
Tp+3
t
CL
t
CK
CLK
t
CH
t
t
CKH
CKS
CKE
t
t
CMH
CMS
PRECHARGE
ALL
LOAD MODE
REGISTER
COMMAND
NOP
AUTO REFRESH
AUTO REFRESH
NOP
ACTIVE
NOP NOP
NOP NOP
*
DQM
t
t
AS
AH
A10=HIGH
ADDRESS
DQ
CODE
BANK ROW
High Z
T=200µs
(min)
t
t
t
RP
MRD
RCAR
(8 AUTO REFRESH
CYCLES)
†ƒ
Power up:
and
Precharge
all banks.
Program Mode Register
V
AUTO REFRESH
DD
CLK stable.
* DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
† The Mode Register may be loaded prior to the auto refresh cycles if desired.
ƒ Outputs are guaranteed High-Z after command is issued.
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P. 12 of 29
AS4LC2M8S1
AS4LC1M16S1
®
*
Read—DQM operation
T0
*†ƒ T1
T2
T3
T4
T5
T6
T7
T8
t
t
t
CL
CK
CL
CLK
t
CH
t
t
CKH
CKS
CKE
t
t
CMH
CMS
ACTIVE
NOP
COMMAND
DQMƒ
NOP
NOP
NOP
READ
NOP
NOP
NOP
t
t
CMH
CMS
t
DQZ
t
t
AH
AS
Column m
3
ROW
A0–A9
(A0-A7)
ROW
ENABLE AUTOPRECHARGE
t
t
t
AS
AH
A10
BA
ROW
DISABLE AUTOPRECHARGE
BANK
t
AS
AH
BANK
*†ƒ
t
AC
t
t
*†ƒ
*†ƒ
OH
t
t
t
OH
AC
AC
OH
D
D
D
OUT m
OUT m+3
DQ
OUT m+2
t
t
t
LZ
LZ
HZ
t
HZ
t
CAS latency
RCD
* For this example, the burst length = 4, and the CAS latency = 2.
† A8 and A9 = “Don’t care.”
ƒ DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
*
Write—DQM operation
T0
*†ƒ T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
t
CH
t
t
CKS CKH
CKE
t
t
CMH
CMS
ACTIVE
COMMAND
DQMƒ
NOP
NOP
NOP
NOP
WRITE
NOP
NOP
t
t
CMH
CMS
t
t
t
AS
AH
Column m
†
ROW
A0–A9
(A0-A7)
t
t
AS
AH
ENABLE AUTOPRECHARGE
A10
BA
ROW
DISABLE AUTOPRECHARGE
BANK
t
AS
AH
BANK
t
t
t
t
t
DH
t
DS
DS
DS
DH
DH
D
m
DQ
D
IN
m+2
D
m+3
IN
IN
t
RCD
*
†
ƒ
For this example, the burst length = 4.
A8 and A9 = “Don’t care.”
DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
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P. 13 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Write—full-page burst
Tn+3
T0
T1
T2
T3
T4
T5
Tn+1
Tn+2
*†ƒ
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS CKH
t
t
CMH
CMS
ACTIVE
COMMAND
DQM†
NOP
NOP
WRITE
t
NOP
NOP
NOP
NOP
BURST TERM
t
CMH
CMS
t
t
AH
AS
Column m
*
ROW
A0–A9
(A0-A7)
t
t
t
AS
AH
A10
BA
ROW
t
AS
AH
BANK
BANK
t
t
t
t
t
t
DH
t
t
t
DS
DH
t
DS
DS
DH
DS
t
t
DH
DS
DH
DH
DS
D
D
D
DQ
IN m+2
D
D
IN m+255
IN m+1
IN m
IN m+3
t
RCD
256 locations within same row
Full page completed
Full-page burst does not
self terminate. Can use
ƒ
BURST TERMINATE command.
*
†
ƒ
A8 and A9 = Don’t care.
DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
Page left open; no t
.
RP
*
Read—full-page burst
T0
T1
T2
T3
T4
T5
T6
Tn+1
Tn+2
Tn+3
Tn+4
t
CL
t
CK
CLK
CKE
t
CH
t
t
CMS CMH
t
t
CMS CMH
BURST
TERM
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Command
DQM†
t
t
AH
AS
COLUMN m
†
ROW
A0–A9
A10
(A0-A7)
t
AS
t
AH
ROW
t
t
AH
AS
BA
BANK
BANK
*†ƒ
*†ƒ
*†ƒ
*†ƒ
*†ƒ
t
t
t
t
AC
*†ƒ
AC
OH
t
AC
AC
AC
OH
t
AC
OH
t
t
t
OH
D
OUT m+1
t
t
t
OH
OUT m
OH
D
D
D
D
D
DQ
OUT
m
OUT m+2
OUT m+255
OUT m+1
256 locations within same row
*†ƒ
t
HZ
t
LZ
t
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
CAS Latency
Full page completed
**
RCD
*
†
ƒ
For this example, the CAS latency = 2.
A8 and A9 = “Don’t care.”
DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
**
Page left open; no t .
RP
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P. 14 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Mode register set command waveform
CLK
PRE
MRS
ACT
CMD
t
t
(min)
MRD
RP
Or Auto Refresh
RSC
t
MRS can be issued only when both banks are idle.
Precharge waveforms
Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP. The earliest assertion of the precharge
command without losing any burst data is show below.
(normal write; BL = 4)
CLK
CMD
WE
PRE
DQ
D
D
0
D
D
3
2
1
(normal read; BL = 4)
CLK
CMD
DQ(CL1)
DQ(CL2)
DQ(CL3)
Read data
PRE
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
3
0
1
2
Auto precharge waveforms
A10 controls the selection of auto precharge during the read or write command cycle.
(write with auto precharge; BL = 4)
CLK
CMD
WE
DQ
D
D
D
D
3
0
1
2
Auto precharge starts*
(read with auto precharge; BL = 4)
CLK
CMD
Read data
DQ(CL1)
DQ(CL2)
DQ(CL3)
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
3
0
1
2
Q
Q
Q
Q
3
0
1
2
Auto precharge starts*
*The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be
issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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AS4LC2M8S1
AS4LC1M16S1
®
DQM waveforms:
read (CL = 3, BL = 4)
CLK
Read data
CMD
DQM
t
t
DQZ
DQ(CL = 3)
DQ(CL = 2)
Q
Q
2
0
Q
Q
Q
3
0
1
DQZ
DQM waveforms:
write(BL =4)
CLK
Write data
CMD
Ext D
D
0
D
D
D
D
1
2
3
IN
DQM
D
0
Data written
3
D ignored
1
D ignored
2
Concurrent Auto-P Waveforms
According to Intel™’s specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst is in a
different bank than the ongoing burst.
(A) RD-P interrupted by RD in another bank
(CL = 3, BL = 4)
CLK
RD-P(A)
RD (B)
CMD
DQ
A
A
B
B
B
B
3
0
1
0
1
2
t
RP(A)
Bank A precharge starts
(B) RD-P interrupted by WR in another bank
(CL = 3, BL = 8)
CLK
RD-P (A)
WR (B)
CMD
DQM
DQ
QA
QA
DN
D
D
D
(B7)
0
1
(B0)
(B1)
(B2)
t
RP
Bank A precharge starts
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AS4LC2M8S1
AS4LC1M16S1
®
(C) WR-P interrupted by RD in another bank
(CL = 2, BL = 4)
CLK
WRP (A)
RD (B)
CMD
DQ
D
D
Q
Q
Q
Q
B3
(A1)
(A0)
B0
B1
B2
t
RP
Bank A precharge starts
(D) WR-P Interrupted by WR in another bank
(CL = 3, BL = 4)
CLK
Bank A precharge starts
WRP (A)
WR (B)
CMD
D
D
A1
DQ
D
D
D
D
D
B3
A0
A2
B0
B1
B2
Clock suspension read waveforms
CLK external
(BL = 8)
CLK internal
CKE
DQM
Q
Q
2
Q
Q
Q
6
Q
7
DQ
1
3
4
OPEN
OPEN
CLK external
CLK internal
CKE
DQM
DQ
Q
1
Q
Q
Q
Q
2
3
4
6
t
t
PED
CKED
CLK external
CLK internal
CKE
DQM
DQ
Q
Q
Q
3
Q
Q
6
Q
1
2
4
5
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AS4LC2M8S1
AS4LC1M16S1
®
Clock suspension write waveforms
CLK external
CLK internal
CKE
t
CKH
t
CKS
DQM
DQ
D1
D2
D3
D6
D5
DQM Mask
CKE Mask
CLK external
CLK internal
CKE
DQM
D6
DQ
D1
D2
D5
D3
DQM Mask
CKE Mask
CLK external
CLK internal
CKE
t
t
CMS
CMH
DQM
DQ
D4
D5
D6
D1
D2
D3
CKE Mask
Read/write interrupt timing
read interrupted by read (BL = 4)
CLK
t
t
CMH
CMS
CMD
ADD
Read data
Read data
A
B
DQ (CL1)
DQ (CL2)
DQ (CL3)
QA0
QB0
QA0
QB1
QB2
QB3
QB0
QA0
QB1
QB2
QB1
QB3
QB2
QB0
QB3
t
CCD
t
= CAS to CAS delay (= 1 CLK).
CCD
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P. 18 of 29
AS4LC2M8S1
AS4LC1M16S1
®
write interrupted by write (BL = 4)
t
CK
t
CL
t
CH
CLK
CMD
ADD
DQ
t
CCD
Write data
Write data
A
B
0
0
0
DA
DB
DB
DB
DB
3
0
1
2
t
CDL
t
DS
t
DH
t
t
= CAS to CAS delay (= 1 CLK).
= last address in to new column addres delay (= 1 CLK).
CCD
CDL
write interrupted by read (BL = 4)
CLK
t
CCD
CMD
ADD
Write data
A
Read data
B
DQ (CL1)
DQ (CL2)
DQ (CL3)
DA
QB
QB
QB
QB
0
0
1
2
3
QB
QB
QB
QB
3
DA
DA
0
1
2
0
QB
QB
QB
QB
3
0
0
1
2
t
CDL
t
t
= CAS to CAS delay (= 1 CLK).
= last address in to new column addres delay (= 1 CLK).
CCD
CDL
Interrupting RD/WR can be for either the same or different banks.
read interrupted by write (CL = 1, BL = 4)
CLK
CMD1
Read data
Write data
DQM1
DQ1
D
D
D
D
3
0
1
2
t
LZ
t
HZ
CMD2
DQM2
DQ2
Read data
Write data
D
D
D
D
3
0
1
2
CMD3
DQM3
DQ3
Read data
Write data
Q
Q
D
D
D
D
3
0
1
0
1
2
To prevent bus contention, maintain a gap between data in and data out.
5/21/01; v.1.1
Alliance Semiconductor
P. 19 of 29
AS4LC2M8S1
AS4LC1M16S1
®
read interrupted by write (CL = 2, BL = 4)
CLK
CMD1
DQM1
DQ1
Read data
Read data
Write data
D
D
D
D
3
0
1
2
CMD2
DQM2
Write data
DQ2
D
D
D
D
3
0
1
2
CMD3
DQM3
Read data
Read data
Write data
DQ3
CMD4
DQM4
D
D
D
D
3
0
1
2
Write data
DQ4
Q
D
0
D
D
D
3
0
1
2
To prevent bus contention, maintain a gap between data in and data out.
read interrupted by write (CL = 3, BL = 4)
t
CCD
CLK
CMD1
DQM1
Read data
Write data
DQ1
D
D
D
D
3
0
1
2
CMD2
DQM2
Read data
Read data
Write data
DQ2
CMD3
DQM3
D
D
D
D
D
D
0
1
2
3
Write data
DQ3
CMD4
DQM4
DQ4
D
D
3
0
1
2
Read data
Write data
D
D
D
D
3
0
1
2
To prevent bus contention, maintain a gap between data in and data out.
Burst termination
Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read
cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is asserted during the write cycle,
burst write data is terminated and the databus goes to High Z simultaneously.
5/21/01; v.1.1
Alliance Semiconductor
P. 20 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Burst stop command waveform
readcycle
t
T
CLK
CMD
Read data
Burst stop
t
OH
DQ (CL = 1)
DQ (CL = 2)
DQ (CL = 3)
Q
Q
Q
2
0
1
Q
Q
Q
0
1
0
2
Q
Q
Q
2
1
write cycle (BL = 8)
CLK
CMD
Write data
Burst stop
DQ
(CL = 1,2,3)
D
D
D
D
3
Q
1
2
Precharge termination
A Precharge command terminates a burst read/write operation during the read cycle. The same bank can be activated after meeting tRP. If an
RD-burst is terminated, o/p will go to High Z after the number of cycles = CAS latency.
read cycle (CL = 1)
CLK
CMD
Read data
PRE
ACT
DQ
Q
Q
Q
Q
3
0
1
2
t
RP
read cycle (CL = 2)
tRP
CLK
CMD
DQ
Read data
PRE
ACT
Q
Q
Q
Q
3
0
1
2
t
(CL = 2)
ROH
read cycle (CL = 3)
t
RP
CLK
CMD
Read data
PRE
ACT
DQ
Q
Q
Q
Q
3
0
1
2
t
ROH (CL = 3)
5/21/01; v.1.1
Alliance Semiconductor
P. 21 of 29
AS4LC2M8S1
AS4LC1M16S1
®
writecycle
t
WR
CLK
CMD
Write data
PRE
ACT
DQ
D
D
D
Q
D
0
1
2
3
4
t
RP
Write recovery
(BL = 4)
t
DPL
CLK
t
RP
CMD
Write data
PRE
ACT
t
DAL
DQ
D
D
D
D
0
3
1
2
This precharge is implicit in case of Auto-P Write.
Auto refresh waveform
CLK
t
t
t
RP
RC
RC
CS
RAS
CAS
WE
A10
A0–A9
DQM
CKE
DQ
Precharge both banks Auto refresh
Auto refresh
Auto refresh
5/21/01; v.1.1
Alliance Semiconductor
P. 22 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Self refresh waveform
CLK
CS
RAS
CAS
WE
A11
A0–A10
DQM
CKE
DQ
t
RC
Self refresh
cycle
Precharge both banks
Arbitrary cycle
Self refresh exit
Self refresh entry
Clock stable before
self refresh exit
Power down mode waveform
(CL = 3)
CLK
CS
RAS
CAS
WE
A11
A10
RA
RA
RA
RA
a
a
a
A0–A9
DQM
CA
CA
a
a
x
CKE
DQ
Active standby
Precharge standby
Power down mode
Data burst
Bank activate
NOP
NOP Bank activate
Power down mode exit
Power down mode
Power down mode entry
Power down mode exit
Power down mode entry
Enter power down mode by pulling CKE low.
All input/output buffers (except CKE buffer) are turned off in power down mode.
When CKE goes high, command input must be equal to no operation at next CLK rising edge.
5/21/01; v.1.1
Alliance Semiconductor
P. 23 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Read/write waveform
(BL = 8, CL = 3)
CLK
t
RAS
CS
RAS
CAS
WE
A11
t
RCD
A10
RA
RA
RA
RA
b
a
A0–A9
DQM
CA
CA
a
b
a
b
CKE
DQ
t
RP
A
A
A
A
A
A
A
A
A
A
A
A
b5
a0
a1
a2
a3
a4
a5
b0
b1
b2
b3
b4
D
Write
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Bank activate
Bank activate
Read
Precharge
Burst read/single write waveform
(BL = 4, CL = 3)
CLK
CS
RAS
CAS
WE
A11
A10
RA
RA
a
A9
DQM
CKE
CA
CA
CA
CA
d
a
a
b
c
DQ
A
A
A
A
A
A
A
A
A
A
d3
a0
a1
a2
a3
b
c
d0
d1
d2
Single
Write
Q
Q
Q
Q
Activate
Q
Q
Q
Q
Read
Read
D
D
5/21/01; v.1.1
Alliance Semiconductor
P. 24 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Interleaved bank read waveform
(BL = 4, CL = 3)
CLK
t
t
t
CCD
CCD
CCD
CS
RAS
CAS
WE
t
RAS
A11
t
t
RCD
RCD
A10
A0–A9
DQM
CKE
RA
RB
a
a
CA
CB
b
RA
CA RB
CA
c
CB
b
a
a
a
a
t
RAS
DQ
QB
QB
QB QB
QA
QA QA QA QB
QB QA QA QA
QA QA QA
b0
b1 b2 b3
a0
a1
a2
a3
a0
a1
b0
b1
b2
c0
c1
c2
Read
Read
Precharge
Bank A:
Bank B:
Active
Read
Active
Read
Read
Precharge
Interleaved bank read waveform
(BL = 4, CL = 3, Autoprecharge)
CLK
CS
t
RC
t
RC
RAS
t
t
t
RP
t
RAS
RAS
RP
t
t
RP
RAS
CAS
WE
A11
t
t
t
RCD
RCD
RCD
A10
A9
RA
RA
RB
RB
RA
RA
RB
RB
a
b
c
d
CB
CA
c
CA
b
a
a
b
c
d
DQM
CKE
t
t
RRD
t
RRD
RRD
DQ
QA
QA
QA QA
QB
QB
QB
QB
QA
QA
QA
QA
c2 c3
a0
a1
a2
a3
b0
b1
b2
b3
c0
c1
Active
Read
Read
AP
Bank A:
Bank B:
Active Read
AP
Active
AP
Active
AP = internal precharge begins
5/21/01; v.1.1
Alliance Semiconductor
P. 25 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Interleaved bank read waveform
(BL = 8, CL = 3)
CLK
CS
t
RC
RAS
t
t
RP
RAS
t
t
RAS
RP
CAS
WE
A11
t
t
t
RCD
RCD
RCD
A10
A9
RB
RB
RA
RA
RA
RA
a
b
c
CB
CA
QB
CA
b
b
c
c
a
a
DQM
CKE
DQ
QA
QA
QA QA
QA
QA
QA
QB
QB
QB
QB
QB
QA
QA
c1
a0
a1
a2
a3
a4
a5
a6
b0 b1
b4
b5
b6
b7
c0
Active
Read
Bank A: Active
Bank B:
Precharge
Read
Precharge
Active
Read
Precharge
Interleaved bank read waveform
(BL = 8, CL = 3, Autoprecharge)
CLK
CS
t
RC
RAS
t
t
RP
RAS
t
RAS
CAS
WE
A11
t
t
t
RCD
RCD
RCD
RA
RB
RA
c
a
b
A10
A9
RA
RA
CA
RB
CA
CA
a
a
b
b
c
c
DQM
CKE
DQ
QA
QA
QA
QA
QA
QA QA
QA
QB
QB
QB
QB
QB
QA
QA
c0
a0
a1
a2
a3
a4
a5
a6
a7
b0
b1
b4
b5
b6
c0
t
t
RRD
RRD
Bank A Active
Bank B
Read
AP
Read
Active
Read
Active
AP
AP = internal precharge begins
5/21/01; v.1.1
Alliance Semiconductor
P. 26 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Interleaved bank write waveform
(BL = 8)
CLK
CS
tRC
RAS
t
t
RP
RAS
t
RAS
CAS
t
t
t
RCD
RCD
RCD
WE
A11
A10
A9
RA
RA
RB
RB
RA
c
a
b
b
CA
CA
RA
CA
c
a
a
b
c
DQM
CKE
DQ
DA
DA
DA
DA
DA
DA
DB
DB
DB
DB
DB
DB
DB
DB
DA
DA
DA
c2
a0
a1
a4
a5
a6
a7
b0
b1
b2
b3
b4
b5
b6
b7
c0
c1
Bank A Active
Bank B
Precharge
Active
Write
Precharge
Write
Active
Write
Interleaved bank write
(BL = 8, Autoprecharge)
CLK
CS
t
RC
RAS
t
t
RAS
RP
t
RAS
CAS
WE
t
t
t
RCD
RCD
RCD
A11
A10
A9
RA
RA
RB
RB
RA
c
a
b
RA
CA
CA
CA
c
c
a
a
b
b
DQM
CKE
DQ
DB
DA
DA
DA
a4
DA
DA
DA
DB
DB
DB
DB DB
DB DB
DA
DA
DA
c2
b2
a0
a1
a5
a6
a7
b0
b1
b3
b4
b5
b6
b7
c0
c1
Write
AP Bank B
AP Bank A
Bank A Active
Bank B
Write
Active
Active
Write
AP = internal precharge begins
5/21/01; v.1.1
Alliance Semiconductor
P. 27 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Package dimensions
c
50 4948474645 444342 414039383736 35343332 313029282726
44-pin TSOP 2
Min Max
(mm) (mm) (mm) (mm)
50-pin TSOP 2
Min
Max
A
A1
A2
b
–
1.2
–
1.2
TSOP 2
E H
e
0.05
0.95
0.30
0.05
0.95
0.30
0.12
1.05
0.45
1.05
0.45
0.21
1 2 3 4 5 6 7 8 9 10111213 14 1516171819 202122232425
c
0.127 (typical)
18.28 18.54
10.03 10.29
11.56 11.96
0.80 (typical)
D
D
E
20.85 21.05
10.03 10.29
11.56 11.96
0.80 (typical)
l
He
e
A
2
A
l
0.40
0.60
0.40
0.60
0–5°
A
1
b
e
AC test conditions
+1.5V
- Output reference levels = 1.4V
- Input rise and fall times: 2 ns
50
Ω
D
OUT
C
= 50 pF
LOAD
Figure A: Equivalent output load
Symbol
Capacitance 15
ƒ = 1 MHz, T = 25° C, V = 3.3V
a CC
Parameter
Signals
Max
Unit
CIN1
CIN2
A0 to A11
4
pF
Input capacitance
I/O capacitance
DQM, RAS, CAS, WE, CS, CLK, CKE,
4
pF
DQ0 to DQ7 (2M × 8)
DQ0 to DQ15 (1M × 16)
CI/O
5
pF
Ordering information
Package \1/ frequency
TSOP 2, 400 mil, 44-pin
TSOP 2, 400 mil, 44-pin
TSOP 2, 400 mil, 50-pin
TSOP 2, 400 mil, 50-pin
–7 ns
AS4LC2M8S1-7TC
–8 ns
–10 ns
AS4LC2M8S1-8TC
AS4LC2M8S0-8TC
AS4LC1M16S1-8TC
AS4LC1M16S0-8TC
AS4LC2M8S1-10TC
AS4LC2M8S0-10TC
AS4LC1M16S1-10TC
AS4LC1M16S0-10TC
AS4LC2M8S0-7TC
AS4LC1M16S1-7TC
AS4LC1M16S0-7TC
5/21/01; v.1.1
Alliance Semiconductor
P. 28 of 29
AS4LC2M8S1
AS4LC1M16S1
®
Part numbering system
AS4
LC
XXX
SX
–XX
T
C
Package (device
dependent):
TSOP 2 400 mil, 44 pin
TSOP 2 400 mil, 50 pin
Commercial
temperature
range: 0° C to
70° C
Device number
DRAM prefix 3.3V CMOS for synchronous
DRAM
S1 = 2K refresh
S0 = 4K refresh
1/frequency
5/21/01; v.1.1
Alliance Semiconductor
P. 29 of 29
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be
the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may
appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the
product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of
any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made
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intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected
to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use.
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