AS7C1024-12HC [ALSC]
Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32;
| 型号： | AS7C1024-12HC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 128KX8, 12ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2000
AS7C1024
AS7C31024
®
5V/3.3V 128K×8 CMOS SRAM (Evolutionary Pinout)
Features
• AS7C1024 (5V version)
• 2.0V data retention
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP I
- 8 × 13.4 mm sTSOP I
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• AS7C31024 (3.3V version)
• Industrial and commercial temperatures
• Organization: 131,072 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5/6/8/10 ns output enable access time
• Low power consumption: ACTIVE
- 825 mW (AS7C1024) / max @ 12 ns
- 360 mW (AS7C31024) / max @ 12 ns
• Low power consumption: STANDBY
- 55 mW (AS7C1024) / max CMOS
- 36 mW (AS7C31024) / max CMOS
Logic block diagram
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
32-pin TSOP I and sTSOP I
(8 x 20mm and 8 x 13.4mm)
VCC
GND
A11
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
V
A15
CE2
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CC
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
Input buffer
A8
A13
WE
CE2
A15
WE
A13
A0
A1
A2
A3
A4
A5
A6
A7
A8
A8
I/O7
I/O0
V
A9
CC
NC
A16
A14
A12
A7
A11
512×256×8
9
OE
A10
Array
(1,048,576)
10
11
12
13
14
15
16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A6
A1
18
17
A5
A2
A4
A3
WE
Column decoder
Control
circuit
OE
CE1
CE2
Selection guide
AS7C1024-10 AS7C1024-12 AS7C1024-15 AS7C1024-20
AS7C31024-10 AS7C31024-12 AS7C31024-15 AS7C31024-20 Unit
Maximum address access time
Maximum output enable access time
10
5
12
6
15
8
20
10
ns
ns
AS7C1024
AS7C31024
AS7C1024
AS7C31024
150
100
10
140
90
10
10
125
80
10
10
110
75
15
mA
mA
mA
mA
Maximum operating current
Maximum CMOS standby current
10
15
Shaded areas contain advance information.
10/18/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS7C1024
AS7C31024
®
Functional description
The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM)
devices organized as 131,072 words × 8 bits. It is designed for memory applications where fast data access, low power, and
simple interfacing are desired.
Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5/6/8/10 ns
AA RC WC
OE
are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion
with multiple-bank systems.
When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume I
SB
power. If the bus is static, then full standby power is reached (I
or I ). For example, the AS7C31024 is guaranteed not
SB1
SB2
to exceed 0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as
low as 2.0V.
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/
O0-I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2).To
avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE)
or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE)
high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output
enable is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter
Symbol
Min
–0.50
-0.50
–0.50
–
Max
+7.0
+5.0
Unit
V
AS7C1024
V
V
V
t1
t1
t2
D
Voltage on V relative to GND
CC
AS7C31024
V
Voltage on any pin relative to GND
Power dissipation
V
+0.50
V
CC
P
1.0
+150
+125
20
W
Storage temperature (plastic)
T
–65
–55
–
°C
°C
mA
stg
Ambient temperature with V applied
T
bias
CC
DC current into outputs (low)
I
OUT
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this spec ification is not implied. Expo-
sure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE1
CE2
X
WE
X
OE
X
Data
Mode
Standby (I , I
H
High Z
High Z
High Z
)
)
SB SB1
X
L
X
X
Standby (I , I
SB SB1
L
H
H
H
Output disable (I
)
CC
L
H
H
L
D
Read (I
)
OUT
CC
L
H
L
X
D
Write (
)
ICC
IN
Key: X = Don’t Care, L = Low, H = High
2
ALLIANCE SEMICONDUCTOR
10/18/00
AS7C1024
AS7C31024
®
Recommended operating conditions
Parameter
Device
Symbol
Min
4.5
3.0
2.2
2.0
–0.5
0
Nominal
Max
5.5
Unit
V
AS7C1024
AS7C31024
AS7C1024
AS7C31024
V
V
5.0
3.3
–
CC
CC
Supply voltage
Input voltage
3.6
V
V
V
V
V
+ 0.5
CC
V
V
IH
IH
–
+ 0.5
CC
†
V
–
0.8
V
IL
commercial
industrial
T
–
70
85
°C
°C
A
Ambient operating temperature
T
–40
–
A
† VILmin = –3.0V for pulse width less than tRC/2
.
DC operating characteristics (over the operating range)1
-10
-12
-15
-20
Unit
Parameter
Sym
|I |
Test conditions
= Max, V = GND to
Device
Min Max Min Max Min Max Min Max
Input leakage
current
V
CC
IN
–
–
1
1
–
–
1
1
–
–
1
1
–
–
1
1
µA
LI
V
CC
V
= Max, CE1 = V or
IH
CC
Output leakage
current
|I
|
CE2 = V , V
= GND to
µA
mA
mA
mA
LO
CC
IL
OUT
CC
V
Operating
power supply
current
V
= Max, CE1 = V ,
AS7C1024
–
–
–
–
–
–
150
100
80
–
–
–
–
–
–
140
90
75
50
10
10
–
–
–
–
–
–
125
80
65
40
10
10
–
–
–
–
–
–
110
75
60
35
15
15
CC
IL
I
CE2 = V , f = f , I
= 0
IH
Max OUT
AS7C31024
mA
V
= Max, CE1 ≥ V and/or AS7C1024
IH
CC
I
CE2 ≤ V , V = V or V ,
SB
IL IN IH IL
AS7C31024
60
f = f , I
= 0mA
Max OUT
Standby power
supply current
V
= Max, CE1 ≥ V –0.2V AS7C1024
10
CC
CC
I
V
≤ GND + 0.2V or
SB1
IN
AS7C31024
10
V
≥ V –0.2V, f = 0
CC
IN
V
I
= 8 mA, V = Min
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
OL
OL
CC
Output voltage
V
I
= –4 mA, V = Min
2.4
2.4
2.4
2.4
OH
OH
CC
Shaded areas contain advance information.
Capacitance (f = 1 MHz, T = 25 °C, V = NOMINAL)2
a
CC
Parameter
Symbol
Signals
Test conditions
= 0V
Max
Unit
Input capacitance
I/O capacitance
C
A, CE1, CE2, WE, OE
I/O
V
5
7
pF
pF
IN
IN
C
V
= V
= 0V
I/O
IN
OUT
10/18/00
ALLIANCE SEMICONDUCTOR
3
AS7C1024
AS7C31024
®
Read cycle (over the operating range)3,9,12
-10
-12
-15
-20
Parameter
Read cycle time
Symbol Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
10
–
–
–
–
2
3
3
–
–
0
–
0
–
–
10
10
10
3
12
–
–
–
–
3
3
3
–
–
0
–
0
–
–
12
12
12
3
15
–
–
–
–
3
3
3
–
–
0
–
0
–
–
15
15
15
4
20
–
–
–
–
3
3
3
–
–
0
–
0
–
–
20
20
20
5
RC
AA
Address access time
t
3
Chip enable (CE1) access time
Chip enable (CE2) access time
Output enable (OE) access time
Output hold from address change
CE1 Low to output in low Z
CE2 High to output in low Z
CE1 Low to output in high Z
CE2 Low to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
t
t
3, 12
3, 12
ACE1
ACE2
t
OE
t
–
–
–
–
5
OH
t
t
–
–
–
–
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
CLZ1
CLZ2
CHZ1
CHZ2
–
–
–
–
t
t
3
3
4
5
3
3
4
5
t
–
–
–
–
OLZ
t
3
3
4
5
4, 5
OHZ
t
t
–
–
–
–
4, 5, 12
4, 5, 12
PU
PD
Power down time
10
12
15
20
Key to switching waveforms
Rising input
Falling input
Undefined / don’t care
Read waveform 1 (address controlled)3,6,7,9,12
tRC
Address
tAA
tOH
DOUT
Data valid
Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12
tRC1
CE1
CE2
OE
tOE
tOLZ
tOHZ
tCHZ1, tCHZ2
tACE1
,
tACE2
DOUT
Data valid
tCLZ1, tCLZ2
tPU
tPD
ICC
ISB
Current
supply
50%
50%
4
ALLIANCE SEMICONDUCTOR
10/18/00
AS7C1024
AS7C31024
®
Write cycle (over the operating range)11, 12
-10
-12
-15
-20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max Unit
Notes
t
10
9
9
9
0
7
0
6
0
–
3
–
–
–
–
–
–
–
–
–
5
–
12
10
10
10
0
–
–
–
–
–
–
–
–
–
5
–
15
12
12
12
0
–
–
–
–
–
–
–
–
–
5
–
20
12
12
12
0
–
–
–
–
–
–
–
–
–
5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
Chip enable (CE1) to write end
Chip enable (CE2) to write end
Address setup to write end
Address setup time
t
t
12
12
CW1
CW2
t
AW
t
12
AS
Write pulse width
t
8
9
12
0
WP
Address hold from end of write
Data valid to write end
t
0
0
AH
t
6
9
10
0
DW
Data hold time
t
0
0
4, 5
4, 5
4, 5
DH
WZ
Write enable to output in high Z
Output active from write end
Shaded areas contain advance information.
t
–
–
–
t
3
3
3
OW
Write waveform 1 ( WE controlled)10,11,12
tWC
tAW
tAH
Address
tWP
WE
tAS
tDW
Data valid
tDH
DIN
tWZ
tOW
DOUT
Write waveform 2 (CE1 and CE2 controlled)10,11,12
tWC
tAW
tAH
Address
tAS
tCW1, tCW2
CE1
CE2
tWP
WE
tWZ
tDW
tDH
DIN
Data valid
DOUT
10/18/00
ALLIANCE SEMICONDUCTOR
5
AS7C1024
AS7C31024
®
Data retention characteristics (over the operating range)13
Parameter
Symbol
Test conditions
Device
Min
2.0
–
Max
Unit
V
V
for data retention
VDR
–
5
1
–
–
1
CC
V
= 2.0V
AS7C1024
mA
mA
ns
CC
Data retention current
ICCDR
CE1 ≥ V –0.2V or
CC
AS7C31024
–
CE2 ≤ 0.2V
Chip deselect to data retention time
Operation recovery time
tCDR
tR
0
V
≥ V –0.2V or
IN
CC
V
≤ 0.2V
t
ns
IN
RC
Input leakage current
| ILI |
–
µA
Data retention waveform
Data retention mode
VDR 2.0V
VCC
VCC
≥
VCC
tCDR
tR
VDR
VIH
VIH
CE1
AC test conditions
– 5V output load: see Figure B or Figure C.
Thevenin equivalent:
168W
– Input pulse level: GND to 3.0V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V.
DOUT
+1.728V (5V and 3.3V)
+5V
+3.3V
480W
320W
DOUT
DOUT
255W
+3.0V
90%
10%
90%
10%
255W
C(14)
GND
C(14)
GND
2 ns
Figure A: Input pulse
GND
Figure B: 5V Output load
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification.
This parameter is sampled and not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
t
CLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE1 and OE are Low and CE2 is High for read cycle.
Address valid prior to or coincident with CE1 transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 2V data retention applies to commercial temperature operating range only.
14 C=30pF, except all high Z and low Z parameters, C=5pF.
6
ALLIANCE SEMICONDUCTOR
10/18/00
AS7C1024
AS7C31024
®
Typical DC and AC characteristics
Normalized supply current ICC, ISB
Normalized supply current ICC, ISB
vs. ambient temperature Ta
Normalized supply current ISB1
vs. supply voltage VCC
1.4
vs. ambient temperature T
a
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.2
625
25
V
= V (NOMINAL)
CC
ICC
ICC
CC
1.0
0.8
0.6
5
1
ISB
ISB
0.4
0.2
0.04
0.2
0.0
MIN
NOMINAL
–55
–10
35
80
-55
-10
Ambient temperature (°C)
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
35
80
MAX
125
125
VCC
125
Supply voltage (V)
Ambient temperature (°C)
Normalized access time tAA
vs. supply voltage VCC
Normalized access time tAA
vs. ambient temperature T
a
1.5
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
V
= V (NOMINAL)
CC
CC
1.4
1.3
1.2
1.1
1.0
0.9
0.8
T = 25° C
T = 25° C
V
= V (NOMINAL)
CC
a
a
CC
MIN
NOMINAL
–55
–10
35
80
0
25
50
75
MAX
100
Supply voltage (V)
Ambient temperature (°C)
Cycle frequency (MHz)
Output source current IOH
vs. output voltage VOH
Output sink current IOL
vs. output voltage VOL
Typical access time change
∆tAA
vs. output capacitive loading
140
120
100
80
140
120
100
80
35
30
25
20
15
10
5
V
= V (NOMINAL)
V
= V (NOMINAL)
CC
CC
CC
CC
V
= V (NOMINAL)
CC
T = 25° C
CC
T = 25° C
a
a
60
60
40
40
20
20
0
0
0
0
0
0
250
500
750
VCC
1000
Output voltage (V)
Output voltage (V)
Capacitance (pF)
10/18/00
ALLIANCE SEMICONDUCTOR
7
AS7C1024
AS7C31024
®
Package dimensions
32-pin PDIP
A
Min
Max
0.180
-
0.055
0.021
0.012
1.571
0.325
0.295
D
B
S
A
A1
B
b
c
D
E
E1
e
-
0.015
0.045
0.015
0.008
-
E
E1
L
A1
e
b
Seating
Plane
Pin 1
0.300
0.280
α
c
eA
0.100 BSC
eA
L
a
0.330
0.110
0°
0.370
0.142
15°
D
S
-
0.043
B
e
32-pin SOJ 300 mil 32-pin SOJ 400 mil
A
E2
E1
A1
Min
-
A1 0.025
A2 0.086
Max
0.145
-
Min
-
Max
0.145
-
Seating
Plane
b
A
0.025
0.086
0.026
0.015
0.007
0.820
0.360
0.395
0.435
Pin 1
c
0.105
0.032
0.020
0.013
0.830
0.275
0.305
0.340
0.115
0.032
0.020
0.013
0.830
0.380
0.405
0.445
A2
B
b
c
D
E
0.026
0.014
0.006
0.820
0.250
E
b
e
E1 0.292
E2 0.330
e
0.050 BSC
0.050 BSC
α
32-pin sTSOP
8×13.4
Min Max
32-pin TSOP
8×20
c
D
Hd
A2
A A1
Min
–
0.05
0.95
0.17
0.10
Max
1.20
0.15
1.05
0.27
0.21
L
A
–
1.25
–
A
A1
A1 0.05
pin 1
pin 32
A2 0.95 1.05 A2
b
C
D
0.17 0.23
0.142 0.158
13.2 13.6
b
c
D
e
18.20 18.60
0.50 nominal
E
pin 16
pin 17
D1 11.7 11.9
E
e
L
S
α
7.9
8.1
E
7.80
8.20
0.50 BSC
0.30 0.70
0.278 Typ.
Hd 19.80 20.20
L
0.50
0°
0.70
5°
0°
5°
α
8
ALLIANCE SEMICONDUCTOR
10/18/00
AS7C1024
AS7C31024
®
Ordering codes
Package \ Access
Volt/Temp
5V commercial
5V industrial
time
10 ns
AS7C1024-10TJC
NA
12 ns
15 ns
20 ns
AS7C1024-12TJC
AS7C1024-12TJI
AS7C1024-15TJC
AS7C1024-15TJI
AS7C31024-15TJC
AS7C31024-15TJI
AS7C1024-15JC
AS7C1024-15JI
AS7C31024-15JC
AS7C31024-15JI
AS7C1024-15TC
AS7C1024-15TI
AS7C31024-15TC
AS7C31024-15TI
AS7C1024-15HC
AS7C1024-15HI
AS7C31024-15HC
AS7C31024-15HI
AS7C1024-20TJC
AS7C1024-20TJI
AS7C31024-20TJC
AS7C31024-20TJI
AS7C1024-20JC
AS7C1024-20JI
AS7C31024-20JC
AS7C31024-20JI
AS7C1024-20TC
AS7C1024-20TI
AS7C31024-20TC
AS7C31024-20TI
AS7C1024-20HC
AS7C1024-20HI
AS7C31024-20HC
AS7C31024-20HI
Plastic SOJ, 300
mL
3.3V commercial AS7C31024-10TJC AS7C31024-12TJC
AS7C31024-12TJI
AS7C1024-12JC
AS7C1024-12JI
AS7C31024-12JC
AS7C31024-12JI
AS7C1024-12TC
AS7C1024-12TI
AS7C31024-12TC
AS7C31024-12TI
AS7C1024-12HC
AS7C1024-12HI
AS7C31024-12HC
AS7C31024-12HI
3.3V industrial
5V commercial
5V industrial
NA
AS7C1024-10JC
NA
Plastic SOJ, 400
mL
AS7C31024-10JC
3.3V commercial
3.3V industrial
5V commercial
5V industrial
NA
NA
NA
NA
NA
NA
NA
NA
NA
TSOP 8×20
3.3V commercial
3.3V industrial
5V commercial
5V industrial
sTSOP 8×13.4
3.3V commercial
3.3V industrial
NA: not available
Shaded areas contain advance information.
Part numbering system
AS7C
X
1024
–XX
X
X
Package: TP=PDIP 300 mil
T=TSOP 8×20
Temperature range
C = Commercial, 0°C to 70°C
I = Industrial, -40°C to 85°C
SRAM Blank=5V CMOS Device Access
prefix 3=3.3V CMOS number time
J=SOJ 400 mil
TJ=SOJ 300 mil
H=sTSOP 8×13.4
10/18/00
ALLIANCE SEMICONDUCTOR
9
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