AS7C1029 [ALSC]

5V 256K X 4 CMOS SRAM (Center power and ground); 5V 256K ×4 CMOS SRAM （中心电源和地）


型号：	AS7C1029
厂家：	ALLIANCE SEMICONDUCTOR CORPORATION
描述：	5V 256K X 4 CMOS SRAM (Center power and ground) 5V 256K ×4 CMOS SRAM （中心电源和地）静态存储器
文件：	总9页 (文件大小：112K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

September 2006

Advance Information

AS7C1029

5V 256K X 4 CMOS SRAM (Center power and ground)

Features

• Industrial (-40^oto 85^oC) temperature.

• Organization: 262,144 x 4 bits

• High speed

• JEDEC-standard package

- 32-pin, 400 mil SOJ

• ESD protection ≥ 2000 volts

- 12 ns address access time

- 6 ns output enable access time

• Low power consumption via chip deselect

• Easy memory expansion with CE

• Center power and ground

• TTL/LVTTL-compatible, three-state I/O

, OE inputs

Pin arrangement

Logic block diagram

32-pin SOJ (400 mil)

A17

A16

A15

A14

A13

I/O3

GND

V_CC

GND

I/O0

Input buffer

V_CC

GND

I/O1

I/O2

A12

A11

A10

I/O3

I/O0

262,144 x 4

Array

(262,144)

Address decoder

Control

circuit

11 12

15 16

13 14

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AS7C1029

Functional description

The AS7C1029 is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as

262,144 x 4 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are

desired.

Equal address access and cycle times (t_AA, t_RC, t_WC) of 12 ns with output enable access times (t_OE) of 6 ns are ideal for high-

performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory

systems.

When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume I_SBpower. If the bus is

static, then full standby power is reached (I_SB1).

A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7

is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should

drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).

A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chips

drive I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write

enable is active, output drivers stay in high-impedance mode.

All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C1029 is packaged in

common industry standard packages.

Absolute maximum ratings

Parameter

Voltage on V_CCrelative to GND

Voltage on any pin relative to GND

Power dissipation

Symbol

V_t1

Min

–0.50

–

Max

+7.0

Unit

V_t2

V_CC+ 0.5

1.25

P_D

Storage temperature (plastic)

Ambient temperature with V_CCapplied

DC current into outputs (low)

Notes:

T_stg

–55

–

+125

^oC

T_bias

I_OUT

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Truth table

Data

High Z

D_OUT

D_IN

Mode

Standby (I_SB, I_SB1

)

Output disable (I_CC

Read (I_CC

Write (I_CC

)

Key: X = don’t care, L = low, H = high.

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AS7C1029

Recommended operating conditions

Parameter

Symbol

V_CC

V_IH

Min

4.5

Nominal

Max

Unit

Supply voltage

5.0

–

5.5

V_CC+ 0.5

0.8

2.2

Input voltage

V_IL

–0.5

–40

–

^oC

Ambient operating temperature (Industrial)

T_A

–

Notes:

min = -1.5V for pulse width less than 5ns, once per cycle.

max = V +2.0V for pulse width less than 5ns, once per cycle.

DC operating characteristics (over the operating range)¹

AS7C1029-12

Parameter

Input leakage current

Symbol

Test conditions

V_CC= Max, V_IN= GND to V_CC

_CC= Max, CE = V_IH

Min

Max Unit

| I_LI

–

μA

Output leakage current

| I_LO

–

μA

V_out= GND to V_CC

V_CC= Max

Operating power supply current

I_CC

160

^CE≤ V_IL, f = f_Max,I_OUT= 0 mA

V_CC= Max

Standby power supply current¹

I_SB

–

CE ≥ V_IH, f = f_Max

V_CC= Max

CE ≥ V_CC–0.2 V,

V_IN≤ 0.2 V or V_IN≥ V_CC–0.2 V,

f = 0

I_SB1

V_OL

V_OH

I_OL= 8 mA, V_CC= Min

I_OH= –4 mA, V_CC= Min

–

0.4

–

Output voltage

2.4

Capacitance (f = 1 MHz, T_a= 25^oC, V_CC= NOMINAL)²

Parameter

Input capacitance

Symbol

C_IN

Signals

A, CE WE

I/O

Test conditions

V_IN= 3dV

Max

Unit

I/O capacitance

C_I/O

V_IN= V_OUT= 3dV

Note:

This parameter is guaranteed by device characterization, but is not production tested.

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AS7C1029

Read cycle (over the operating range)^3,9

AS7C1029-12

Min Max

Parameter

Read cycle time

Symbol

t_RC

Unit

Notes

–

Address access time

t_AA

–

Chip enable (CE) access time

Output enable (OE) access time

Output hold from address change

CE low to output in low Z

CE low to output in high Z

OE low to output in low Z

OE high to output in high Z

Power up time

t_ACE

t_OE

t_OH

–

t_CLZ

t_CHZ

t_OLZ

t_OHZ

t_PU

–

4, 5

–

Power down time

t_PD

Key to switching waveforms

Rising input

Falling input

Undefined/don’t care

Read waveform 1 (address controlled)^3,6,7,9

Address

Data valid

OUT

Read waveform 2 (CE and OE controlled)^3,6,8,9

RC1

OHZ

OLZ

CHZ

ACE

OUT

Data valid

CLZ

Supply

current

50%

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AS7C1029

Write cycle (over the operating range)¹¹

AS7C1029-12

Min Max

Parameter

Write cycle time

Symbol

t_WC

t_CW

t_AW

t_AS

Unit

Notes

–

Chip enable (CE) to write end

Address setup to write end

Address setup time

–

Write pulse width

t_WP

Write recovery time

t_WR

t_AH

t_DW

t_DH

t_WZ

t_OW

Address hold from end of write

Data valid to write end

Data hold time

4, 5

Write enable to output in high Z

Output active from write end

Write waveform 1 (WE controlled)^10,11

Address

Data valid

OUT

Write waveform 2 (CE controlled)^10,11

Address

Data valid

OUT

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AS7C1029

AC test conditions

– Output load: see Figure B.

– Input pulse level: GND to 3.0 V. See Figure A.

– Input rise and fall times: 3 ns. See Figure A.

– Input and output timing reference levels: 1.5 V.

+5 V

Thevenin equivalent:

168

480

OUT

+3.0V

GND

90%

10%

90%

10%

255

+1.728 V

OUT

3 ns

Figure A: Input pulse

GND

Figure B: 5 V Output load

Notes:

During V power-up, a pull-up resistor to V on CE is required to meet I specification.

CC CC SB

This parameter is sampled, but not 100% tested.

For test conditions, see AC Test Conditions, Figures A and B.

and t

are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage.

CHZ

CLZ

This parameter is guaranteed, but not 100% tested.

WE is high for read cycle.

CE and OE are low for read cycle.

Address is valid prior to or coincident with CE transition low.

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 N/A

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 N/A.

13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.

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AS7C1029

Package dimensions

32-pin SOJ

400 mil

Symbol Min Max

0.132 0.146

0.025

32-pin SOJ

400 mil

0.105 0.115

0.026 0.032

0.015 0.020

0.007 0.013

0.820 0.830

0.354 0.378

0.395 0.405

0.435 0.445

0.050 BSC

Pin 1

Seating

plane

Note: This part is compatible with both pin numbering

conventions used by various manufacturers.

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AS7C1029

Ordering Codes

Package

Volt/Temp

12 ns

Plastic SOJ, 400 mil

5V industrial

AS7C1029-12JIN

Part numbering system

AS7C

1029C

–XX

Temperature range

I = industrial, -40°

C to 85° C

Device

number

Package:

J = SOJ 400 mil

N = LEAD FREE

PART

SRAM prefix

Access time

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AS7C1029

Alliance Memory, Inc.

1116 South Amphlett

San Mateo, CA 94402

Tel: 650-525-3737

Part Number: AS7C1029

Document Version: v. 1.0

Fax: 650-525-0449

www.alliancememory.com

Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this

document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data

contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any

time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in

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claims arising from such use.

AS7C1029 [ALSC]

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