AS7C256A-15TIN [ALSC]
5V 32K X 8 CMOS SRAM (Common I/O); 5V 32K ×8 CMOS SRAM （通用I / O）
| 型号： | AS7C256A-15TIN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 5V 32K X 8 CMOS SRAM (Common I/O) |
| 文件： | 总9页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2004
AS7C256A
®
5V 32K X 8 CMOS SRAM (Common I/O)
Features
• TTL-compatible, three-state I/O
• 28-pin JEDEC standard packages
- 300 mil SOJ
• Pin compatible with AS7C256
• Industrial and commercial temperature options
• Organization: 32,768 words × 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5, 6, 7, 8 ns output enable access time
• Very low power consumption: ACTIVE
- 412.5 mW max @ 10 ns
- 8 × 13.4 mm TSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• 2.0V Data retention
• Very low power consumption: STANDBY
- 11 mW max CMOS I/O
• Easy memory expansion with CE and OE inputs
Logic block diagram
Pin arrangement
28-pin TSOP 1 (8×13.4 mm)
V
28-pin SOJ (300 mil)
CC
GND
Input buffer
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
V
CC
WE
A13
A8
A9
A11
OE
OE
A11
A9
1
A10
CE
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
3
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A0
A1
A8
4
I/O7
I/O0
A13
WE
5
6
A2
A3
A4
A5
A6
A7
256 X 128 X 8
Array
V
7
CC
8
A14
A12
A7
AS7C256A
9
A10
CE
10
11
12
13
14
9
(262,144)
A6
A5
A0
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A4
A1
A2
I/O0
I/O1
I/O2
GND
A3
17
16
15
WE
OE
CE
Column decoder
Control
circuit
A
8
A
9
A A A A A
10 11 12 13 14
Selection guide
-10
10
5
-12
12
6
-15
-20
Unit
ns
Maximum address access time
Maximum output enable access time
Maximum operating current
15
7
20
8
ns
75
2
70
2
65
2
60
2
mA
mA
Maximum CMOS standby current
9/24/04; v.1.2
Alliance Semiconductor
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.
AS7C256A
®
Functional description
The AS7C256A is a 5.0V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized
as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including
TM
TM
Pentium , PowerPC , and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V
operation without sacrificing performance or operating margins.
The device enters standby mode when CE is high. CMOS standby mode consumes ≤11 mW. Normal operation offers 75%
power reduction after initial access, resulting in significant power savings during CPU idle, suspend, and stretch mode.
Equal address access and cycle times (t , t , t ) of 10/12/15/20 ns with output enable access times (t ) of 5, 6, 7, 8 ns
AA RC WC
OE
are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank
memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7
is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should
drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The
chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write
enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0 ±0.5V supply. The AS7C256A is packaged
in high volume industry standard packages.
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–
Max
Unit
V
Voltage on V relative to GND
V
V
+7.0
CC
t1
t2
D
Voltage on any pin relative to GND
Power dissipation
V
+ 0.5
V
CC
P
1.0
W
o
Storage temperature (plastic)
T
–65
–55
–
+150
+125
20
C
stg
bias
o
Ambient temperature with V applied
T
C
CC
DC current into outputs (low)
I
mA
OUT
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE
H
L
WE
X
OE
X
Data
Mode
Standby (I , I
High Z
High Z
)
SB SB1
H
H
Output disable (I
)
CC
L
H
L
D
D
Read (I
)
CC
OUT
IN
L
L
X
Write (I
)
CC
Key: X = Don’t care, L = Low, H = High
9/24/04; v.1.2
Alliance Semiconductor
P. 2 of 9
AS7C256A
®
Recommended operating conditions
Parameter
Symbol
Min
4.5
2.2
-0.5
0
Typical
Max
5.5
+0.5
Unit
V
Supply voltage
Input voltage
V
5.0
–
CC
**
V
V
V
IH
CC
*
V
–
0.8
70
85
V
IL
o
commercial
industrial
T
–
C
A
Ambient operating temperature
o
T
–40
–
C
A
*
**
VIL min = –1.0V for pulse width less than 5ns.
VIH max = VCC + 2.0V for pulse width less than 5ns.
DC operating characteristics (over the operating range)1
-10
-12
-15
-20
Parameter Sym
Test conditions
Min Max Min Max Min Max Min Max Unit Notes
Input leakage
current
V
= Max,
CC
|I |
–
–
1
1
–
–
1
1
–
–
1
1
–
–
1
1
µA
µA
LI
V = GND to V
in CC
Outputleakage
current
V
V
= Max,
CC
|I
|
LO
CC
SB
= GND to V
OUT
CC
Operating
power supply
current
V
= Max, CE < V
IL
CC
I
I
I
–
–
–
75
45
-
70
45
–
–
–
65
40
–
–
–
60
40
mA
mA
f = f , I
= 0mA
Max OUT
V
f = f
= Max, CE > V
CC
IH
–
–
Max
Standby power
supply current
V
V
V
= Max, CE > V –0.2V
< 0.2V or
CC
CC
2.0
2.0
2.0
2.0 mA
SB1
IN
IN
> V –0.2V, f = 0
CC
V
V
I
= 8 mA, V = Min
–
0.4
–
–
0.4
–
–
0.4
–
–
0.4
–
V
V
4
4
OL OL
CC
Output voltage
I
= –4 mA, V = Min
2.4
2.4
2.4
2.4
OH OH
CC
Capacitance (f = 1MHz, T = room temperature, V = NOMINAL)4
a
CC
Signals
A, CE WE
I/O
Parameter
Input capacitance
I/O capacitance
Symbol
Test conditions
V = 0V
Max
Unit
pF
C
,
,
OE
5
7
IN
in
C
V = V = 0V
pF
I/O
in
out
9/24/04; v.1.2
Alliance Semiconductor
P. 3 of 9
AS7C256A
®
Read cycle (over the operating range)2,8
-10
-12
-15
-20
Parameter
Read cycle time
Symbol Min Max Min Max Min Max Min Max Unit Notes
t
t
t
t
t
t
t
t
t
t
t
10
–
–
–
3
3
–
0
–
0
–
–
10
10
5
12
–
–
–
3
3
–
0
–
0
–
–
12
12
6
15
–
–
–
3
3
–
0
–
0
–
–
15
15
7
20
–
–
–
3
3
–
0
–
0
–
–
20
20
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address access time
2
2
AA
Chip enable (CE) access time
Output enable (OE) access time
Output hold from address change
CE LOW to output in low Z
CE HIGH to output in high Z
OE LOW to output in low Z
OE HIGH to output in high Z
Power up time
ACE
OE
–
–
–
–
4
OH
–
–
–
–
3,4
3,4
3,4
3,4
3,4
3,4
CLZ
CHZ
OLZ
OHZ
PU
3
3
4
5
–
–
–
–
3
3
4
5
–
–
–
–
Power down time
10
12
15
20
PD
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)2,5,6,8
t
RC
Address
tAA
t
OH
D
Data valid
out
Read waveform 2 (CE controlled)2,5,7,8
1
t
RC
CE
OE
t
OE
t
t
t
OLZ
OHZ
CHZ
t
ACE
D
out
Data valid
t
CLZ
t
PD
I
CC
t
PU
I
Supply
current
SB
50%
50%
9/24/04; v.1.2
Alliance Semiconductor
P. 4 of 9
AS7C256A
®
Write cycle (over the operating range)9
-10
-12
-15
-20
Parameter
Write cycle time
Symbol Min Max Min Max Min Max Min Max Unit Notes
t
t
t
10
8
8
0
7
0
0
5
0
–
3
–
–
–
–
–
–
–
–
–
5
–
12
8
8
0
8
0
0
6
0
–
3
–
–
–
–
–
–
–
–
–
6
–
15
10
10
0
–
–
–
–
–
–
–
–
–
7
–
20
12
12
0
–
–
–
–
–
–
–
–
–
8
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CW
AW
Chip enable to write end
Address setup to write end
Address setup time
t
AS
WP
WR
Write pulse width
t
9
12
0
Write recovery time
t
0
Address hold from end of write
Data valid to write end
Data hold time
t
0
0
AH
t
t
8
10
0
DW
t
0
3,4
3,4
3,4
DH
WZ
OW
Write enable to output in high Z
Output active from write end
–
–
t
3
3
Write waveform 1 (WE controlled)9
t
WC
t
t
AH
AW
Address
WE
t
t
WR
WP
t
AS
t
t
DH
DW
D
Data valid
in
t
t
WZ
OW
D
out
Write waveform 2 (CE controlled)9
t
WC
t
t
AH
AW
Address
t
t
t
CW
WR
AS
CE
WE
t
t
DW
DH
D
Data valid
in
9/24/04; v.1.2
Alliance Semiconductor
P. 5 of 9
AS7C256A
®
AC test conditions
- Output load: see Figure B
- Input pulse level: GND to V See Figure A.
CC
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
+5.0V
Thevenin equivalent
168
480
Ω
D
V
out
CC
Ω
90%
10%
90%
10%
255
Ω
C10
D
+1.72V
out
2 ns
Figure A: Input pulse
GND
GND
Figure B: Output load
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
For test conditions, see AC Test Conditions, Figures A, B.
These parameters are specified with CL = 5pF, as in Figures B. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
10 C=30pF, except on High Z and Low Z parameters, where C=5pF.
9/24/04; v.1.2
Alliance Semiconductor
P. 6 of 9
AS7C256A
®
Package diagrams
28-pin SOJ
28-pin SOJ
Min
in inches
Max
D
e
B
0.128
0.026
0.095
0.026
0.016
0.007
0.720
0.255
0.295
0.330
0.148
-
A
A1
A2
B
b
c
D
E
E1
E2
e
A
A1
E1 E2
0.105
0.032
0.020
0.010
0.730
0.275
0.305
0.340
Seating
Plane
b
Pin 1
c
A2
E
28-pin TSOP1
0.050 BSC
e
b
28-pin TSOP1
8×13.4 mm
c
A2
A
A1
L
Min
1.00
0.05
0.91
0.17
0.10
11.70
Max
1.20
0.15
1.05
0.27
0.20
11.90
A
A1
A2
b
c
D
D
Hd
α
0.55 nominal
e
E
Hd
L
7.90
13.20
0.50
0°
8.10
13.60
0.70
5°
E
α
9/24/04; v.1.2
Alliance Semiconductor
P. 7 of 9
AS7C256A
®
Ordering information
Package / Access time
Temperature
10 ns
12 ns
15 ns
20 ns
Commercial
Industrial
AS7C256A-10JC
AS7C256A-10JI
AS7C256A-10TC
AS7C256A-10TI
AS7C256A-12JC
AS7C256A-12JI
AS7C256A-12TC
AS7C256A-12TI
AS7C256A-15JC
AS7C256A-15JI
AS7C256A-15TC
AS7C256A-15TI
AS7C256A-20JC
AS7C256A-20JI
AS7C256A-20TC
AS7C256A-20TI
Plastic SOJ, 300 mil
Commercial
Industrial
TSOP 8x13.4mm
Note: Add suffix ‘N’to the above part number for lead free parts. (Ex. AS7C256A-10JIN)
Part numbering system
AS7C
256A
–XX
X
C or I
X
Temperature range:
C = 0 oC to 70 0C
I = -40C to 85C
Packages:
SRAM prefix Device number Access time
N= Lead Free Part
J = SOJ 300 mil
T = TSOP 8x13.4mm
9/24/04; v.1.2
Alliance Semiconductor
P. 8 of 9
AS7C256A
®
®
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: AS7C256A
Document Version: v.1.2
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered
trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make
changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at
any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related
to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and
Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of
Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems
where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-
supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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