AS7C33256PFD32A-133TQIN [ALSC]
3.3V 256K x 32/36 pipelined burst synchronous SRAM; 3.3V 256K X 32/36流水线突发同步SRAM
| 型号： | AS7C33256PFD32A-133TQIN |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 3.3V 256K x 32/36 pipelined burst synchronous SRAM |
| 文件： | 总20页 (文件大小：527K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2004
AS7C33256PFD32A
AS7C33256PFD36A
®
3.3V 256K × 32/36 pipelined burst synchronous SRAM
Features
• Organization: 262,144 words x 32 or 36 bits
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous register-to-register operation
• Dual-cycle deselect
• Individual byte write and global write
• Multiple chip enables for easy expansion
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
• 3.3V core power supply
• Asynchronous output enable control
• Available in100-pin TQFP
• 2.5V or 3.3V I/O operation with separate V
DDQ
Logic block diagram
LBO
CLK
CLK
CE
ADV
Burst logic
ADSC
CLR
256K × 32/36
Memory
array
18
ADSP
2
2
18
16
18
D
CE
CLK
Q
A
[17:0]
Address
register
36/32
36/32
BWE
GWE
d
D
Q
DQ
d
Byte write
BW
registers
CLK
D
Q
DQ
c
BW
c
Byte write
registers
CLK
D
Q
DQ
b
BW
b
Byte write
registers
CLK
D
Q
DQ
a
4
BW
a
Byte write
registers
CLK
D
CE0
CE1
CE2
OE
Q
Q
Output
Input
Enable
register
registers
registers
CE
CLK
CLK
CLK
D
Enable
Power
down
delay
ZZ
register
CLK
36/32
DQ[a:d]
OE
Selection guide
–166
6
–133
7.5
133
4
Units
Minimum cycle time
ns
MHz
ns
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
166
3.5
475
130
30
425
100
30
mA
mA
mA
Maximum CMOS standby current (DC)
12/1/04, v.1.2
Alliance Semiconductor
P. 1 of 20
Copyright ©Alliance Semiconductor. All rights reserved.
AS7C33256PFD32A
AS7C33256PFD36A
®
1,2
8 Mb Synchronous SRAM products list
Org
Part Number
Mode
PL-SCD
PL-SCD
PL-SCD
PL-DCD
PL-DCD
PL-DCD
FT
Speed
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
512KX18
256KX32
256KX36
AS7C33512PFS18A
AS7C33256PFS32A
AS7C33256PFS36A
AS7C33512PFD18A
AS7C33256PFD32A
AS7C33256PFD36A
AS7C33512FT18A
AS7C33256FT32A
AS7C33256FT36A
AS7C33512NTD18A
AS7C33256NTD32A
AS7C33256NTD36A
AS7C33512NTF18A
AS7C33256NTF32A
AS7C33256NTF36A
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
166/133 MHz
166/133 MHz
166/133 MHz
7.5/8.5/10 ns
7.5/8.5/10 ns
7.5/8.5/10 ns
FT
FT
NTD-PL
NTD-PL
NTD-PL
NTD-FT
NTD-FT
NTD-FT
1 Core Power Supply: VDD = 3.3V + 0.165V
2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O
VDDQ = 2.5V + 0.125V for 2.5V I/O
PL-SCD
PL-DCD
FT
:
:
:
Pipelined Burst Synchronous SRAM - Single Cycle Deselect
Pipelined Burst Synchronous SRAM - Double Cycle Deselect
Flow-through Burst Synchronous SRAM
1
TM
NTD -PL
:
:
Pipelined Burst Synchronous SRAM with NTD
TM
NTD-FT
Flow-through Burst Synchronous SRAM with NTD
1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of
their respective owners.
12/1/04, v.1.2
Alliance Semiconductor
P. 2 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Pin arrangement TQFP
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
DQPc/NC
DQc0
DQc1
VDDQ
VSSQ
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
4
5
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6 12
DQc7 13
6
7
8
9
10
11
14
15
NC
NC
VDD
TQFP 14 × 20 mm
VDD
ZZ
NC 16
VSS 17
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
DQd0 18
DQd1 19
VDDQ
VSSQ
20
21
DQd2 22
DQd3 23
DQd4 24
DQd5 25
VSSQ
VDDQ
26
27
DQd6 28
DQd7 29
DQPd/NC 30
Note: Pins 1, 30, 51, 80 are NC for ×32
12/1/04, v.1.2
Alliance Semiconductor
P. 3 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Functional description
The AS7C33256PFD32A and AS7C33256PFD36A are high-performance CMOS 8-Mbit Synchronous Static Random Access
Memory (SRAM) devices organized as 262,144 words x 32 or 36 bits, and incorporate a two-stage register-register pipeline
for highest frequency on any given technology.
Fast cycle times of 6/7.5 ns with clock access times (t ) of 3.5/4.0 ns enable 166 and 133 MHz bus frequencies. Two-chip
CD
enable and three-chip enable (CE) inputs permit versatility and easy memory expansion. Burst operation is initiated in one of
two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV)
allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip
address register when ADSP is sampled LOW, the chip enables are sampled active, and the output buffer is enabled with OE.
In a read operation the data accessed by the current address, registered in the address registers by the positive edge of CLK, are
carried to the data-out registers and driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock
edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for the next
access of the burst when ADV is sampled LOW, and both address strobes are HIGH. Burst mode is selectable with the LBO
input. With LBO unconnected or driven HIGH, burst operations use an interleaved count sequence. With LBO driven LOW, the
device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable
GWE writes all 32/36 bits regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is HIGH, one or more
bytes may be written by asserting BWE and the appropriate individual byte BWn signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output buffers are
disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register when BWn is sampled
LOW. Address is incremented internally to the next burst address if BWn and ADV are sampled LOW. This device operates in
double cycle deselect features during real cycle.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC
and ADSP are as follows:
• ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
• Master chip enable CE0 blocks ADSP, but not ADSC.
AS7C33256PFD32A and AS7C33256PFD36A family operates from a core 3.3V power supply. I/Os use a separate power
supply that can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14 × 20 mm TQFP package.
TQFP thermal Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
Test conditions
= 0V
Min
Max
Unit
pF
*
C
V
-
-
5
7
IN
IN
*
C
V
= V = 0V
OUT
pF
I/O
IN
*
Guaranteed not tested
TQFP thermal resistance
Description
Conditions
Symbol
Typical
40
Units
°C/W
°C/W
1–layer
4–layer
θJA
θJA
Thermal resistance
(junction to ambient)1
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51
22
Thermal resistance
(junction to top of case)1
θJC
8
°C/W
1 This parameter is sampled
12/1/04, v.1.2
Alliance Semiconductor
P. 4 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Signal descriptions
Signal
I/O Properties Description
CLK
I
I
CLOCK
SYNC
SYNC
Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and OE is active.
A, A0, A1
DQ[a,b,c,d] I/O
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0
is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more
information.
CE0
I
SYNC
Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on
clock edges when ADSC is active or when CE0 and ADSP are active.
CE1, CE2
ADSP
I
I
SYNC
SYNC
Address strobe processor. Asserted LOW to load a new bus address or to enter standby
mode.
Address strobe controller. Asserted LOW to load a new address or to enter standby
mode.
ADSC
ADV
GWE
I
I
I
SYNC
SYNC
SYNC
Advance. Asserted LOW to continue burst read/write.
Global write enable. Asserted LOW to write all 32/36 bits. When HIGH, BWE and
BW[a:d] control write enable.
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d]
inputs.
BWE
I
SYNC
SYNC
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =
LOW. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a
write cycle. If all BW[a:d] are inactive the cycle is a read cycle.
BW[a,b,c,d] I
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in
read mode.
OE
I
I
ASYNC
STATIC
Selects Burst mode. When tied to V or left floating, device follows Interleaved Burst
DD
LBO
order. When driven Low, device follows linear Burst order. This signal is internally
pulled High.
ZZ
I
-
ASYNC
-
Snooze. Places device in LOW power mode; data is retained. Connect to GND if unused.
No connect
NC
Snooze Mode
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ
is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE
MODE.
12/1/04, v.1.2
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P. 5 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Write enable truth table (per byte)
Function
GWE BWE
BWa
X
BWb
X
BWc
BWd
X
L
H
H
H
H
H
X
L
L
L
H
L
X
L
Write All Bytes
L
L
L
Write Byte a
L
H
H
L
H
Write Byte c and d
H
H
L
X
X
X
H
X
Read
H
H
H
Key: X = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal.
Asynchronous Truth Table
Operation
Snooze mode
ZZ
H
L
OE
X
I/O Status
High-Z
L
Dout
Read
L
H
High-Z
Write
L
X
Din, High-Z
High-Z
Deselected
L
X
Burst order table
Interleaved Burst Order (LBO=1)
A1 A0 A1 A0 A1 A0 A1 A0
Linear Burst Order (LBO=0)
A1 A0 A1 A0 A1 A0 A1 A0
Starting Address
First increment
0 0
0 1
1 0
1 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
0 0
Starting Address
First increment
0 0
0 1
1 0
1 1
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
Second increment
Third increment
Second increment
Third increment
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P. 6 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
[4]
Synchronous truth table
[2]
CE01
H
L
CE1
X
L
CE2
X
X
X
H
H
L
ADSP ADSC ADV WRITE
OE
X
X
X
X
X
L
Address accessed
NA
CLK
Operation
Deselect
DQ
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Q
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
NA
Deselect
L
L
H
L
NA
Deselect
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA
Deselect
L
H
L
NA
Deselect
L
X
X
L
External
External
External
External
Next
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read
L
L
L
H
L
Begin read
Hi−Z
Q
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
L
H
L
Next
Hi−Z
Q
H
H
L
Current
Current
Next
H
L
Hi−Z
Q
L
H
L
Next
Hi−Z
Q
H
H
X
L
Current
Current
External
Next
H
X
X
X
X
X
Hi−Z
3
D
X
H
X
H
X
X
X
X
H
H
H
H
L
D
D
D
D
L
L
Next
H
H
L
Current
Current
L
1 X = don’t care, L = low, H = high
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all
BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time
4 ZZ pin is always Low.
12/1/04, v.1.2
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P. 7 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
1
Absolute maximum ratings
Parameter
Symbol
Min
–0.5
–0.5
–0.5
–
Max
Unit
V
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
V
, V
+4.6
DD
DDQ
V
V
+ 0.5
DD
V
IN
IN
V
V
+ 0.5
V
DDQ
P
1.8
W
D
Short circuit output current
I
–
50
mA
OUT
o
Storage temperature (plastic)
Temperature under bias
T
–65
–65
+150
+135
C
stg
o
T
C
bias
Recommended operating conditions at 3.3V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
Nominal
Max
3.465
3.465
0
Unit
3.135
3.135
0
3.3
3.3
0
V
V
V
VDDQ
Vss
Recommended operating conditions at 2.5V I/O
Parameter
Supply voltage for inputs
Supply voltage for I/O
Ground supply
Symbol
VDD
Min
3.135
2.375
0
Nominal
Max
3.465
2.625
0
Unit
V
3.3
2.5
0
VDDQ
Vss
V
V
1Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions may affect reliability.
12/1/04, v.1.2
Alliance Semiconductor
P. 8 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
DC electrical characteristics for 3.3V I/O operation
Parameter
Input leakage current1
Output leakage current
Sym
|ILI|
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
µA
2
|ILO
|
-2
2*
2*
-0.3**
-0.5**
2.4
–
2
VDD+0.3
VDDQ+0.3
0.8
µA
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
V
V
Address and control pins
I/O pins
VIL
0.8
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 3.135V
IOL = 8 mA, VDDQ = 3.465V
–
V
V
0.4
1 LBO, and ZZ pins have an internal pull-up or pull-down, and input leakage = ±10 µA.
DC electrical characteristics for 2.5V I/O operation
Parameter
Input leakage current
Output leakage current
Sym
|ILI|
Conditions
VDD = Max, 0V < VIN < VDD
OE ≥ VIH, VDD = Max, 0V < VOUT < VDDQ
Address and control pins
I/O pins
Min
-2
Max
Unit
2
µA
µA
V
|ILO
|
-2
2
VDD+0.3
VDDQ+0.3
0.7
1.7*
1.7*
-0.3**
-0.3**
1.7
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
V
Address and control pins
I/O pins
V
VIL
0.7
V
Output high voltage
Output low voltage
VOH
VOL
IOH = –4 mA, VDDQ = 2.375V
IOL = 8 mA, VDDQ = 2.625V
–
V
–
0.7
V
*VIH max < VDD +1.5V for pulse width less than 0.2 X tCYC
**
V
min = -1.5 for pulse width less than 0.2 X tCYC
IL
I
operating conditions and maximum limits
DD
Parameter
Sym
Conditions
-166
-133
Unit
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
,
IOUT = 0 mA, ZZ < VIL
Operating power supply current1
Standby power supply current
ICC
475
425
mA
All VIN ≤ 0.2V or >
V
– 0.2V, Deselected,
DD
f = fMax, ZZ < VIL
Deselected, f = 0, ZZ < 0.2V,
all VIN ≤ 0.2V or ≥ VDD – 0.2V
ISB
130
30
100
30
Deselected, f = f , ZZ
≥
V
– 0.2V,
Max
DD
ISB1
mA
all VIN ≤ VIL or ≥ VIH
CE0 < VIL, CE1 > VIH, CE2 < VIL, f = fMax
,
ISB2
30
30
IOUT = 0 mA, ZZ < VIL
1 I given with no output loading. I increases with faster cycle times and greater output loading.
CC
CC
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P. 9 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Timing characteristics for 3.3 V I/O operation
–166
–133
1
Parameter
Clock frequency
Symbol
Min Max Min Max Unit
Notes
f
–
166
–
–
133
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Cycle time
t
6
7.5
-
CYC
Clock access time
t
-
3.5
3.5
–
4.0
4.0
–
CD
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
OE
t
0
0
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
OH
t
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
–
4.0
4.0
–
t
–
–
HZC
t
0
0
OHOE
t
2.4
2.3
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
2.5
2.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
0.5
0.5
0.5
–
5
5
CH
Clock low pulse width
t
t
t
–
–
CL
AS
DS
Address setup to clock high
Data setup to clock high
–
–
6
–
–
6
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 17
t
–
–
6,7
6,8
6
WS
t
–
–
CSS
t
–
–
AH
DH
WH
t
–
–
6
t
–
–
6,7
6,8
6
t
–
–
CSH
t
–
–
ADVS
t
–
–
6
ADSPS
ADSCS
t
–
–
6
t
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
6
t
–
–
6
12/1/04, v.1.2
Alliance Semiconductor
P. 10 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Timing characteristics for 2.5 V I/O operation
–166
–133
1
Parameter
Clock frequency
Symbol
Min Max Min Max Unit
Notes
f
–
166
–
–
133
–
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Max
Cycle time
t
6
7.5
-
CYC
Clock access time
t
-
3.8
3.5
–
4.2
4.0
–
CD
OE
Output enable low to data valid
Clock high to output low Z
Data output invalid from clock high
Output enable low to output low Z
Output enable high to output high Z
Clock high to output high Z
Output enable high to invalid output
Clock high pulse width
t
–
–
t
0
0
2,3,4
2
LZC
t
1.5
0
–
1.5
0
–
OH
t
–
–
2,3,4
2,3,4
2,3,4
LZOE
HZOE
t
–
3.5
3.5
–
–
4.0
4.0
–
t
–
–
HZC
t
0
0
OHOE
t
2.4
2.3
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
0.7
0.7
0.7
–
2.5
2.5
1.7
1.7
1.7
1.7
0.7
0.7
0.7
0.7
1.7
1.7
1.7
0.7
0.7
0.7
–
5
5
CH
Clock low pulse width
t
t
t
–
–
CL
AS
DS
Address setup to clock high
Data setup to clock high
–
–
6
–
–
6
Write setup to clock high
Chip select setup to clock high
Address hold from clock high
Data hold from clock high
Write hold from clock high
Chip select hold from clock high
ADV setup to clock high
ADSP setup to clock high
ADSC setup to clock high
ADV hold from clock high
ADSP hold from clock high
ADSC hold from clock high
1 See “Notes” on page 17
t
–
–
6,7
6,8
6
WS
t
–
–
CSS
t
–
–
AH
DH
WH
t
–
–
6
t
–
–
6,7
6,8
6
t
–
–
CSH
t
–
–
ADVS
t
–
–
6
ADSPS
ADSCS
t
–
–
6
t
–
–
6
ADVH
ADSPH
ADSCH
t
–
–
6
t
–
–
6
Snooze Mode Electrical Characteristics
Description
Conditions
ZZ > V
Symbol
Min
Max
Units
mA
Current during Snooze Mode
ZZ active to input ignored
I
30
IH
SB2
PDS
PUS
t
t
2
2
cycle
cycle
cycle
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
t
2
ZZI
t
0
RZZI
12/1/04, v.1.2
Alliance Semiconductor
P. 11 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Key to switching waveforms
Rising input
Falling input
don’t care
Undefined
Timing waveform of read cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
Address
LOAD NEW ADDRESS
A3
tAH
tAS
A1
A2
tWS
tWH
GWE, BWE
tCSS
tCSH
CE0, CE2
CE1
tADVS
tADVH
ADV
OE
ADV inserts wait states
t
OE
tCD
tHZC
tHZOE
tOH
tLZOE
Q(A2)
Q(A2Ý01)
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A3Ý01) Q(A3Ý10)
Q(A1)
Dout
Read Suspend Read
Burst
Read
Burst
Read
Suspend
Read
2Ý10
Burst
Read
Read
Q(A3)
Burst
Read
3Ý01
Burst
Read
3Ý10
Burst
Read
3Ý11
) Q(A )
Q(A1)
Read
Q(A2)
DSEL*
Q(A1)
2Ý01
2Ý10
2Ý11
Q(A
) Q(A
) Q(A
) Q(A
)
Q(A
) Q(A
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low. BW[a:d] is don’t care.
*Outputs are disabled within two clk cycles after DSEL command
12/1/04, v.1.2
Alliance Semiconductor
P. 12 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Timing waveform of write cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPH
ADSP
tADSCS
tADSCH
ADSC
ADSC LOADS NEW ADDRESS
A3
tAS
tAH
A1
A2
Address
tWS
tWH
BWE
BW[a:d]
tCSS
tCSH
CE0, CE2
CE1
ADV SUSPENDS BURST
tADVH
tADVS
ADV
OE
tDS
tDH
D(A1)
D(A2)
D(A2Ý01)
D(A2Ý01) D(A2Ý10) D(A2Ý11)
D(A3)
D(A3Ý01) D(A3Ý10)
Din
Read
Q(A1)
ADV
Burst
Write
Sus-
pend
Write
D(A1)
Suspend
Write
ADV
Burst
Write
Read
Q(A2)
ADV
Burst
Write
ADV
Burst
Write
Burst
Write
Suspend
Write
Write
3
D(A )
2
D(A )
3Ý01
2Ý01
D(A
)
D(A
)
2Ý01
D(A
)
3Ý10
2Ý10
2Ý11
D(A
)
D(A
)
D(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
12/1/04, v.1.2
Alliance Semiconductor
P. 13 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Timing waveform of read/write cycle (ADSP Controlled; ADSC High)
tCYC
tCH
tCL
CLK
tADSPS
tADSPH
ADSP
tAH
tAS
A2
A3
A1
Address
tWH
tWS
GWE
CE0, CE2
CE1
tADVH
tADVS
ADV
OE
tDH
tDS
Din
D(A2)
tOE
tCD
tLZC
tOH
tHZOE
tLZOE
Dout
Q(A1)
Q(A3)
Q(A3Ý01)
Q(A3Ý10)
Q(A3Ý11)
DSEL
Read
Q(A1)
Suspend
Read
Q(A1)
Read
Q(A2)
Suspend
Write
Read
Q(A3)
ADV
Burst
Read
ADV
Burst
Read
ADV
Burst
Read
2
D(A )
3Ý01
3Ý10
3Ý11
Q(A )
Q(A
)
Q(A
)
Note: Ý = XOR when LBO = high/no connect; Ý = ADD when LBO = low.
12/1/04, v.1.2
Alliance Semiconductor
P. 14 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH)
tCYC
tCH
tCL
CLK
tADSCS
tADSCH
ADSC
tAS
tAH
A9
A8
A5
A7
A1
A4
A6
A3
A2
ADDRESS
tWS
tWH
GWE
CE0,CE2
CE1
tCSS
tCSH
ADV
OE
tOE
tLZOE
tOH
tHZOE
tLZOE
Q(A2)
Q(A1)
Q(A3)
Q(A8)
Q(A4)
Q(A9)
Dout
Din
tDH
tDS
D(A5)
D(A6)
D(A7)
READ
Q(A9)
WRITE
D(A7)
READ READ READ
Q(A1) Q(A2) Q(A3)
WRITE
D(A6)
READ
Q(A8)
READ
Q(A4)
WRITE
D(A5)
12/1/04, v.1.2
Alliance Semiconductor
P. 15 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Timing waveform of power down cycle
tCYC
tCL
tCH
CLK
tADSPS
tADSPS
ADSP
ADSC
A2
A1
ADDRESS
GWE
tWS
tWH
tCSS
tCSH
CE0,CE2
CE1
ADV
OE
tOE
tLZOE
Din
D(A2)
tHZOE
D(A2(Ý01))
tHZC
Dout
Q(A1)
tPUS
tPDS
ZZ Recovery Cycle
Normal Operation Mode
ZZ
ZZ Setup Cycle
tZZI
tRZZI
ISB2
Isupply
Sleep
State
READ
Q(A2)
CON-
TINUE
SUSPEND
WRITE
D(A2)
SUSPEND
READ
Q(A1)
READ
Q(A1)
WRITE
Ý01)
D(A2
12/1/04, v.1.2
Alliance Semiconductor
P. 16 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
AC test conditions
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C.
• Input pulse level: GND to 3V. See Figure A.
Thevenin equivalent:
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
• Input and output timing reference levels: 1.5V.
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
319Ω / 1667Ω
Z0 = 50Ω
50
Ω
DOUT
VL = 1.5V
for 3.3V I/O;
= VDDQ/2
+3.0V
DOUT
90%
10%
90%
10%
5 pF*
353Ω / 1538Ω
30 pF*
GND *including scope
and jig capacitance
GND
for 2.5V I/O
Figure A: Input waveform
Figure B: Output load (A)
Figure C: Output load (B)
Notes
1
2
3
4
5
6
For test conditions, see AC Test Conditions, Figures A, B, and C.
This parameter measured with output load condition in Figure C.
This parameter is sampled, but not 100% tested.
t
HZOE is less than tLZOE, and tHZC is less than tLZC at any given temperature and voltage.
tCH measured as high above VIH, and tCL measured as low below VIL
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times for all rising edges of CLK when chip is enabled.
.
7
8
Write refers to GWE, BWE, and BW[a:d].
Chip select refers to CE0, CE1, and CE2.
12/1/04, v.1.2
Alliance Semiconductor
P. 17 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Package dimensions: 100-pin quad flat pack (TQFP)
A2
TQFP
Min
0.05
c
Max
0.15
A1
L1
L
Hd
A1
A2
b
D
1.35
1.45
0.22
0.38
b
e
0.09
0.20
c
13.80
19.80
14.20
20.20
D
E
0.65 nominal
e
15.80
21.80
0.45
16.20
22.20
0.75
Hd
He
L
α
He
E
1.00 nominal
L1
α
0°
7°
Dimensions in millimeters
12/1/04, v.1.2
Alliance Semiconductor
P. 18 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Ordering information
Package
–166 MHz
–133 MHz
AS7C33256PFD32A-166TQC
AS7C33256PFD32A-166TQI
AS7C33256PFD36A-166TQC
AS7C33256PFD36A-166TQI
AS7C33256PFD32A-133TQC
AS7C33256PFD32A-133TQI
AS7C33256PFD36A-133TQC
AS7C33256PFD36A-133TQI
TQFP x 32
TQFP x 36
Note: Add suffix ‘N’ with the above part number for Lead Free Parts (Ex. AS7C33256PFD32A-166TQCN)
Part numbering guide
AS7C
33
256
PF
D
32/36
A
–XXX
TQ
C/I
X
1
2
3
4
5
6
7
8
9
10
11
1. Alliance Semiconductor SRAM prefix
2. Operating voltage: 33 = 3.3V
3. Organization: 256
4. Pipelined mode
= 256K
5. Deselect: D = double cycle deselect
6. Organization: 32 = x32; 36 = x36
7. Production version: A = first production version
8. Clock speed (MHz)
9. Package type: TQ = TQFP
10. Operating temperature: C = commercial (
11. N = Lead free part
0° C to 70° C); I = industrial (-40° C to 85° C)
12/1/04, v.1.2
Alliance Semiconductor
P. 19 of 20
AS7C33256PFD32A
AS7C33256PFD36A
®
Copyright © Alliance Semiconductor
All Rights Reserved
Alliance Semiconductor Corporation
2575, Augustin®e Drive,
Santa Clara, CA 95054
Tel: 408 - 855 - 4900
Part Number:AS7C33256PFD32A
AS7C33256PFD36A
Document Version: v.1.2
Fax: 408 - 855 - 4999
www.alsc.com
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and
Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products
at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to
change or correct this data at any time, without notice. If the product described herein is under development, significant
changes to these specifications are possible. The information in this product data sheet is intended to be general
descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or
warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application
or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of
Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or
infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale
(which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms
and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights,
copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance
does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure
may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-
supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against
all claims arising from such use.
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