AS8C401825 [ALSC]
Power down controlled by ZZ input;
| 型号： | AS8C401825 |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Power down controlled by ZZ input |
| 文件： | 总19页 (文件大小：806K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AS8C403625
AS8C401825
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
Description
Features
◆
TheAS8C403625/1825 are high-speed SRAMs organized as
128Kx36/256Kx18.TheAS8C403625/1825SRAMs containwrite,data,
address andcontrolregisters.Therearenoregisters inthedataoutput
path(flow-througharchitecture).InternallogicallowstheSRAMtogen-
erateaself-timedwritebaseduponadecisionwhichcanbeleftuntilthe
endofthe write cycle.
128K x 36, 256K x 18 memory configurations
◆
Supports fast access times:
Commercial:
– 7.5ns up to 117MHz clock frequency
Theburstmodefeatureoffersthehighestlevelofperformancetothe
systemdesigner,astheAS8C403625/1825canprovidefourcyclesofdata
forasingleaddress presentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe
next three rising clock edges. The order of these three addresses are
definedbytheinternalburstcounterandtheLBO inputpin.
◆
LBO input selects interleaved or linear burst mode
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite
enable (BWE), and byte writes (BWx)
3.3V core power supply
Power down controlled by ZZ input
3.3V I/O
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆
◆
◆
◆
◆
◆
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack(TQFP),
The AS8C403625/1825 SRAMs utilize IDT’s latest high-performance
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP)
PinDescriptionSummary
A0-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Chip Enable
CE
CS
0
, CS
1
Chip Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
BWE
BW , BW
1
2
, BW
3
, BW (1)
4
CLK
Clock
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
N/A
Synchronous
Synchronous
Synchronous
DC
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
ADV
ADSC
ADSP
LBO
TMS
TDI
Synchronous
Synchronous
N/A
TCK
TDO
Test Clock
Test Data Output
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
JTAG Reset (Optional)
Sleep Mode
TRST
ZZ
I/O
0
-I/O31, I/OP1-I/OP4
DD, VDDQ
SS
Data Input / Output
Core Power, I/O Power
Ground
V
Supply
Supply
V
N/A
NOTE:
SEPTEMBER 522800tbl101 0
1. BW3 and BW4 are not applicable for the AS8C401825.
1
.
DSC-5280/08
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
PinDefinitions(1)
Symbol
Pin Function
I/O
Active
Description
A0-A17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK
and ADSC Low or ADSP Low and CE Low.
Address Status
(Cache Controller)
I
I
I
LOW
LOW
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the
ADSC
ADSP
ADV
address registers with new addresses.
Address Status
(Processor)
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address
registers with new addresses. ADSP is gated by CE.
Burst Address
Advance
Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter,
controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not
incremented; that is, there is no address advance.
Byte Write Enable
I
I
LOW
LOW
Synchronous byte write enable gates the byte write inputs BW
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are
blocked and only GW can initiate a write cycle.
1
-BW . If BWE is LOW at the rising edge of CLK
4
BWE
Individual Byte
Write Enables
Synchronous byte write enables. BW
1
controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte
BW
1
-BW
4
write causes all outputs to be disabled.
Chip Enable
Clock
I
I
I
I
I
LOW
N/A
Synchronous chip enable. CE is used with CS
0
and CS to enable AS8C403625/1825. CE also gates ADSP.
1
CE
CLK
This is the clock input. All timing references for the device are made with respect to this input.
CS
CS
GW
0
Chip Select 0
Chip Select 1
HIGH Synchronous active HIGH chip select. CS
0
is used with CE and CS
1
to enable the chip.
LOW
LOW
Synchronous active LOW chip select. CS
1
is used with CE and CS
0 to enable the chip.
1
Global Write
Enable
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O
I/OP1-I/OP4
0
-I/O31
Data Input/Output
I/O
I
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of
CLK. The data output path is flow-through (no output register).
Linear Burst Order
LOW
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and must not change state
while the device is operating.
LBO
Output Enable
I
LOW
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
OE
TMS
TDI
Test ModeSelect
Test Data Input
I
I
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
TAP controller.
Test DataOutput
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
LOW
TRST
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down theAS8C403625/1825
HIGH to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
ZZ
Sleep Mode
down.
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
V
3.3V I/O Supply.
V
Ground.
NC
No Connect
NC pins are not electrically connected to the device.
5280 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.422
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
FunctionalBlockDiagram
LBO
ADV
CEN
INTERNAL
ADDRESS
128K x 36/
CLK
2
Burst
Logic
17/18
256K x 18-
BIT
Binary
Counter
ADSC
A0*
A1*
Q0
Q1
MEMORY
ARRAY
CLR
ADSP
2
CLK EN
A0,A1
A2 - A17
ADDRESS
REGISTER
A0 -
A
16/17
36/18
36/18
17/18
GW
BWE
Byte 1
Write Register
Byte 1
Write Driver
BW
1
9
9
Byte 2
Write Register
Byte 2
Write Driver
BW2
Byte 3
Write Register
Byte 3
Write Driver
BW
3
9
9
Byte 4
Write Register
Byte 4
Write Driver
BW4
CE
CS
Q
D
0
Enable
DATA INPUT
REGISTER
CS
1
Register
CLK EN
ZZ
Powerdown
OE
OUTPUT
BUFFER
OE
,
36/18
I/O
0
- I/O31
I/OP1 - I/OP4
5280 drw 01
TMS
TDI
TCK
JTAG
(SA Version)
TDO
TRST
(Optional)
6.42AA
3
AS8C403625, AS8C401825 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureSupplyVoltage
Commercial &
Symbol
Rating
Unit
Industrial Values
Grade
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
VDD
VDDQ
(2)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
Commercial
Industrial
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
(3,6)
(4,6)
(5,6)
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
5280 tbl 04
NOTES:
1. TA is the "instant on" case temperature.
VTERM
Terminal Voltage with
Respect to GND
VTERM
Terminal Voltage with
Respect to GND
V
RecommendedDCOperating
Conditions
Commercial
oC
oC
oC
oC
W
Symbol
Parameter
Min. Typ.
3.135 3.3
3.135 3.3
Max.
Unit
V
Operating Temperature
T (7)
A
VDD
Core Supply Voltage
3.465
3.465
0
Industrial
-40 to +85
Operating Temperature
VDDQ I/O Supply Voltage
V
Temperature
Under Bias
-55 to +125
TBIAS
V
SS
IH
IH
IL
Supply Voltage
0
0
V
____
V
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
VDD +0.3
V
Storage
-55 to +125
TSTG
V
2.0
V
DDQ +0.3(1)
0.8
V
____
____
Temperature
V
-0.3(2)
V
P
T
Power Dissipation
DC Output Current
2.0
50
5280 tbl 06
NOTES:
IOUT
mA
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
5280 tbl 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
100PinTQFPCapacitance
119BGACapacitance
(TA = +25° C, f = 1.0mhz)
(TA = +25° C, f = 1.0mhz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
Max. Unit
Symbol
CIN
V
5
7
pF
CIN
V
7
7
pF
CI/O
V
pF
CI/O
VOUT = 3dV
pF
5280 tbl 07
5280 tbl 07a
165fBGACapacitance
(TA = +25° C, f = 1.0mhz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
VOUT = 3dV
pF
5280 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.442
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ran ges
Pin Configuration – 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP2
I/O15
I/O14
I/OP3
I/O16
I/O17
2
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
72
71
70
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
VDDQ
VDDQ
69
68
67
66
65
64
I/O22
I/O9
I/O8
VSS
NC
I/O23
(1)
VSS
VDD
NC
V
DD
ZZ (2)
VSS
63
62
61
60
59
58
57
56
55
54
53
I/O24
I/O25
I/O7
I/O6
VDDQ
V
V
DDQ
SS
VSS
,
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O1
I/O0
I/OP1
52
51
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5280 drw 02a
100TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.42
5
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ra nges
Pin Configuration – 256K x 18
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
A
NC
NC
10
NC
NC
NC
2
79
3
78
77
4
V
DDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
NC
NC
NC
I/OP1
I/O
I/O
7
8
I/O8
7
9
72
71
70
I/O9
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
V
DDQ
VDDQ
69
68
67
66
I/O10
I/O
I/O
VSS
NC
5
4
I/O11
(1)
V
SS
VDD
65
64
NC
V
DD
ZZ(2)
VSS
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O12
I/O13
I/O
I/O
3
2
V
DDQ
V
V
DDQ
SS
VSS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
0
VSS
VSS
V
DDQ
NC
NC
NC
VDDQ
NC
NC
NC
,
31
33 34 35 36
38 39 40 41 42 43 44 45 46 47 48 49 50
37
32
5280 drw 02b
100TQFP
TopView
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
6.462
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
5
µA
ZZ , LBO and JTAG Input Leakage Current(1)
Output Leakage Current
___
___
___
|ILI
|
V
DD = Max., VIN = 0V to VDD
OUT = 0V to VDDQ, Device Deselected
OL = +8mA, VDD = Min.
OH = -8mA, VDD = Min.
30
5
µA
µA
V
|ILO
|
V
VOL
Output Low Voltage
I
0.4
___
VOH
Output High Voltage
I
2.4
V
5280 tbl 08
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ in will be internally pulled to VSS if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(1)
7.5ns
8ns
8.5ns
Com'l
Symbol
Parameter
Test Conditions
Com'l Only Com'l
Ind
Ind
Unit
Operating Power Supply Current
Device Selected, Outputs Open, VDD = Max.,
255
30
200
30
210
180
190
mA
I
DD
(2)
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
DDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
35
95
35
30
35
90
35
mA
mA
V
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
90
85
80
(2,.3)
VDDQ = Max., VIN > VHD or < VLD, f = fMAX
IZZ
Full Sleep Mode Supply Current
ZZ > VHD, DD = Max.
V
30
30
30
mA
5280 tbl 09
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
AC Test Conditions
AC Test Load
V
DDQ/2
(VDDQ = 3.3V)
50Ω
Input Pulse Levels
0 to 3V
2ns
I/O
Z0 = 50Ω
Input Rise/Fall Times
,
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
5280 drw 03
1.5V
Figure 1. AC Test Load
6
5
4
3
See Figure 1
5280 tbl 10
∆tCD
(Typical, ns)
2
1
20 30 50
80 100
Capacitance (pF)
200
,
5280 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
7
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
SynchronousTruthTable(1,3)
CE
CS1
ADSP ADSC ADV
GW
BWE BWx OE(2)
Operation
Address
Used
CS
0
CLK
I/O
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
None
None
H
L
X
X
L
X
H
X
H
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
H
H
L
X
X
X
X
X
L
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cycle, Begin Burst
L
L
L
H
L
HI-Z
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cycle, Begin Burst
L
L
L
L
DOUT
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
HI-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
OUT
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
L
HI-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
HI-Z
Next
L
D
IN
IN
IN
IN
OUT
Next
L
X
L
X
L
D
Next
L
H
L
D
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
L
HI-Z
DOUT
H
X
X
X
X
HI-Z
D
IN
IN
IN
IN
5280 tbl 11
X
L
X
L
D
H
L
D
X
X
D
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ - low for the table.
88
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Synchronous Write Function Truth Table (1, 2)
GW
H
H
L
BWE
H
L
BW
X
H
X
L
1
BW
X
H
X
L
2
BW
X
H
X
L
3
BW4
Operation
Read
X
H
X
L
Read
Write all Bytes
Write all Bytes
X
L
H
H
H
H
H
(3)
Write Byte 1
L
L
H
L
H
H
L
H
H
H
L
(3)
Write Byte 2
L
H
H
H
(3)
Write Byte 3
L
H
H
(3)
Write Byte 4
L
H
5280 tbl 12
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the AS8C401825.
3. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation(2)
OE
ZZ
I/O Status
Power
Read
Read
L
H
X
X
X
L
L
L
L
H
Data Out
High-Z
Active
Active
Write
High-Z – Data In
High-Z
Active
Deselected
Sleep Mode
Standby
Sleep
High-Z
5280 tbl 13
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Interleaved Burst Sequence Table ( LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
A1
A0
First Address
0
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
0
0
5280 tbl 14
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Linear Burst Sequence Table ( LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
First Address
1
Second Address
Third Address
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
Fourth Address(1)
1
1
0
0
0
1
1
0
5280 tbl 15
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
9
9
AS8C403625,AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
7.5ns(5)
8ns
8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
Clock Parameter
____
____
____
____
____
____
t
CY C
Clock Cycle Time
8.5
3
10
4
11.5
4.5
ns
ns
ns
(1)
CH
Clock High Pulse Width
Clock Low Pulse Width
t
(1)
CL
____
____
____
3
4
4.5
t
Output Parameters
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
7.5
8
8.5
ns
ns
ns
____
____
____
tCDC
2
0
2
0
2
0
(2)
CLZ
____
____
____
t
(2)
Clock High to Data High-Z
2
3.5
2
3.5
2
3.5
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Output Active
3.5
3.5
3.5
____
____
____
(2)
(2)
0
0
0
t
OLZ
____
____
____
Output Enable High to Output High-Z
3.5
3.5
3.5
t
OHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SA
SS
SD
SW
SAV
SC
Address Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
2
2
2
2
2
2
2
2
2
2
2
2
ns
ns
ns
ns
ns
ns
t
Address Status Setup Time
Data In Setup Time
t
t
Write Setup Time
t
Address Advance Setup Time
Chip Enable/Select Setup Time
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HA
HS
HD
HW
HAV
HC
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Status Hold Time
Data In Hold Time
t
t
Write Hold Time
t
Address Advance Hold Time
Chip Enable/Select Hold Time
t
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
____
____
____
t
ZZPW
ZZ Pulse Width
100
100
34
100
100
40
100
100
50
ns
ns
(3)
tZZR
ZZ Recovery Time
Configuration Set-up Time
t
CFG (4)
ns
5280 tbl 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
6.1402
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ran ges
Timing Waveform of Flow-Through Read Cycle (1,2)
,
6.42
13
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ra nges
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
,
6.1442
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ran ges
Timing Waveform of Write Cycle No. 1 - GW Controlled (1,2,3)
,
6.42
15
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ra nges
Timing Waveform of Write Cycle No. 2 - Byte Controlled (1,2,3)
,
6.1462
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ran ges
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
,
6.42
17
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
,
5280 drw 10
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS
1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
,
5280 drw 11
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
16
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
JTAG Interface Specification (SA Version only)
t
JCYC
t
JR
tJF
tJCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
3)
(
x
TRST
M5280 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
ScanRegisterSizes
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
Register Name
Bit Size
____
____
t
ns
Instruction (IR)
Bypass (BYR)
4
1
t
40
ns
(1)
____
t
5
ns
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
(1)
____
t
5
ns
Note (1)
____
____
t
50
ns
I5280 tbl 03
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
____
t
20
ns
____
t
0
ns
____
____
t
25
25
ns
t
JTAG Hold
ns
I5280 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
17717172
17
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Value
Description
Revision Number (31:28)
0x2
Reserved for version number.
Device ID (27:12)
0x22C, 0x22E
Defines AS8C403625/1825
JEDEC ID (11:1)
0x33
1
Allows unique identification of device vendor .
Indicates the presence of an ID register.
ID Register Indicator Bit (Bit 0)
I5280 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5280 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
2 18
AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
Commercial Temperature Range
ORDERING INFORMATION
VCC
Range
Speed
ns
Alliance
Organization
Package
Operating Temp
AS8C403625-QC75N
AS8C401825-QC75N
128K x 36
256K x 18
3.1 - 3.4V
3.1 - 3.4V
100 pin TQFP
100 pin TQFP
Comercial 0 - 70C
Comercial 0 - 70C
7.5
7.5
PART NUMBERING SYSTEM
Device
Conf.
Mode
Package
Q = 100 Pin TQFP
Operating Temp
N
AS8C
Speed
0 ~ 70C
7.5 ns
N= Leadfree
01= ZBT
Sync.
SRAM prefix
18= x18
36 = x36
40 = 4M
00 = Pipelined
25 = Flow- Thru
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®
Alliance Memory, Inc.
551 Taylor way, suite#1,
San Carlos, CA 94070
Tel: 650-610-6800
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS8C403625/401825
Document Version: v. 1.0
Fax: 650-620-9211
www.alliancememory.com
© Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of
Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this
document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any
time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in
this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any
product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or
warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's
Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights,
trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in
life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all
claims arising from such use.
19
192
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