ASM2I9942PG-32-LR [ALSC]
Low Voltage 1:18 Clock Distribution Chip; 低电压1:18时钟分配芯片
| 型号： | ASM2I9942PG-32-LR |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Low Voltage 1:18 Clock Distribution Chip |
| 文件： | 总10页 (文件大小：432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2005
rev 0.3
ASM2I9942P
Low Voltage 1:18 Clock Distribution Chip
Features
With low output impedance (≈12Ω), in both the HIGH and
LOW logic states, the output buffers of the ASM2I9942P
are ideal for driving series terminated transmission lines.
With an output impedance of 12Ω, the ASM2I9942P can
drive two series terminated transmission lines from each
output. This capability gives the ASM2I9942P an effective
fanout of 1:36. The ASM2I9942P provides enough copies
of low skew clocks for most high performance synchronous
systems.
LVPECL Clock Input
2.5V LVCMOS Outputs for Pentium IITM*
Microprocessor Support
200pS Maximum Targeted Output–to–Output
Skew
Maximum Output Frequency of 250MHz @3.3 VCC
32–Lead LQFP and TQFP Packaging
Single 3.3V or 2.5V Supply
The differential LVPECL inputs of the ASM2I9942P allow
the device to interface directly with a LVPECL fanout buffer
to build very wide clock fanout trees or to couple to a high
frequency clock source. The OE pins will place the outputs
into a high impedance state. The OE pin has an internal
pullup resistor.
Pin and Function compatible with MPC942P
Functional Description
The ASM2I9942P is a 1:18 low voltage clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device is offered in two versions; the ASM2I9942C has an
LVCMOS input clock while the ASM2I9942P has a
LVPECL input clock. The 18 outputs are 2.5V or 3.3V
LVCMOS compatible and feature the drive strength to drive
50Ω series or parallel terminated transmission lines. With
output-to-output skews of 200pS, the ASM2I9942P is ideal
as a clock distribution chip for the most demanding of
synchronous systems. The 2.5V outputs also make the
device ideal for supplying clocks for a high performance
The ASM2I9942P is a single supply device. The VCC power
pins require either 2.5V or 3.3V. The 32 lead LQFP and
TQFP package is chosen to optimize performance, board
space and cost of the device. The 32–lead LQFP and
TQFP have a 7x7mm2 body size with conservative 0.8mm
pin spacing.
Pentium IITM microprocessor based design.
* Pentium II is a trademark of Intel Corporation
Block Diagram
Table 1. Function Table
Q0
OE
Output
PECL_CLK
PECL_CLK
Q1-Q16
0
1
HIGH IMPEDANCE
OUTPUTS ENABLED
Q17
OE
(Int. Pullup)
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
May 2005
ASM2I9942P
rev 0.3
Pin Diagram
24 23
22
21
20
19
18
17
GND
Q5
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCC
Q12
Q13
Q14
GND
Q15
Q16
Q17
Q4
Q3
ASM2I9942P
VCC
Q2
Q1
Q0
1
2
3
4
5
6
7
8
Table 2. Pin Description
Pin #
Pin Name
I/O
Type
Function
5
6
PECL_CLK,
PECL_CLK
Input
LVPECL
LVPECL Clock Inputs
Output enable/disable
3
OE
Input
-
LVCMOS
-
(high–impedance tristate)
4
NC
No connect
32,31,30,28,27,26,24,23,22,20,19,18,15,
14,13,11,10,9
Q0 – Q17
Output
LVCMOS Clock outputs
Negative power supply (GND)
1,2,12,17,25
GND
Supply
Ground
for I/O and core.
Positive power supply for I/O and
core. All VCC pins must be
connected to the positive power
supply for correct operation
7,8,16,21,29
VCC
Supply
VCC
Table 3. Absolute Maximum Rating1
Symbol
VCC
VI
IIN
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
mA
°C
Supply Voltage
Input Voltage
Input Current
3.6
VCC + 0.3
±20
Storage Temperature Range
–40
125
TStor
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Low Voltage 1:18 Clock Distribution Chip
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Notice: The information in this document is subject to change without notice.
May 2005
ASM2I9942P
rev 0.3
Table 4. DC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%)
Symbol
VIH
Characteristic
Input HIGH Voltage
Min
2.0
Typ
Max
VCC
Unit
V
Condition
VIL
Input LOW Voltage
0.8
V
VPP
VX
VOH
VOL
IIN
CIN
CPD
ZOUT
ICC
Input Swing PECL_CLK
Input Crosspoint PECL_CLK
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
0.6
VCC–1.0
2.0
1.0
VCC–0.6
V
V
V
V
µA
pF
pF
Ω
IOH = –16 mA
IOL = 16 mA
0.5
±200
4.0
14
12
Per Output
0.5
5.0
mA
Table 5. AC Characteristics (TA = 0°to 70°C, VCC = 2.5V ± 5%)
Symbol
Characteristic
Min
Typ
Max
200
4.0
Unit
MHz
nS
nS
pS
nS
pS
nS
Condition
Fmax
Maximum Frequency
Propagation Delay
Propagation Delay
1.8
2.0
tPLH
tPHL
tsk(o)
tsk(pr)
tsk(pr)
tr, tf
4.3
Output-to-Output Skew within one bank
150
2.2
1.3
1.0
Part–to–Part Skew 1
Part–to–Part Skew2
Output Rise/Fall Time
0.1
Note: 1. Across temperature and voltage ranges, includes output skew.
2. For a specific temperature and voltage, includes output skew.
Table 6. DC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%)
Symbol
VIH
Characteristic
Input HIGH Voltage
Min
2.4
Typ
Max
VCC
Unit
V
Condition
VIL
Input LOW Voltage
0.8
V
VPP
VX
VOH
VOL
IIN
CIN
CPD
ZOUT
ICC
Input Swing PECL.CLK
Input Crosspoint PECL_CLK
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
0.6
VCC–1.0
2.4
1.0
VCC–0.6
V
V
V
V
µA
pF
pF
Ω
IOH = –20 mA
IOL = 20 mA
0.6
±200
4.0
14
12
Per Output
0.5
5.0
mA
Low Voltage 1:18 Clock Distribution Chip
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Notice: The information in this document is subject to change without notice.
May 2005
ASM2I9942P
rev 0.3
Table 7. AC Characteristics (TA = 0°to 70°C, VCC = 3.3V ± 5%)
Symbol
Characteristic
Min
Typ
Max
250
3.2
3.6
150
1.7
Unit
Condition
Fmax
Maximum Frequency
MHz
nS
nS
pS
nS
pS
nS
Propagation Delay
Propagation Delay
1.5
1.5
tPLH
tPHL
tsk(o)
tsk(pr)
tsk(pr)
tr, tf
Output-to-output Skew within one bank
Part–to–Part Skew1
Part–to–Part Skew2
1.0
1.0
Output Rise/Fall Time
0.1
Note: 1. Across temperature and voltage ranges, includes output skew.
2. For a specific temperature and voltage, includes output skew.
Low Voltage 1:18 Clock Distribution Chip
4 of 10
Notice: The information in this document is subject to change without notice.
May 2005
ASM2I9942P
rev 0.3
Power Consumption of the ASM2I9942P and
Thermal Management
per output, (Μ)ΣCL represents the external capacitive
output load, N is the number of active outputs (N is
always 12 in case of the ASM2I9942P). The
ASM2I9942P supports driving transmission lines to
maintain high signal integrity and tight timing parameters.
Any transmission line will hide the lumped capacitive load
at the end of the board trace, therefore, ΣCL is zero for
controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination
output termination results in equation 2 for power
dissipation.
The ASM2I9942P AC specification is guaranteed for the
entire operating frequency range up to 250MHz. The
ASM2I9942P power consumption and the associated
long-term reliability may decrease the maximum
frequency limit, depending on operating conditions such
as clock frequency, supply voltage, output loading,
ambient temperature, vertical convection and thermal
conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the
ASM2I9942P die junction temperature and the associated
device reliability.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are
a function of the output termination technique and DCQ is
the clock signal duty cycle. If transmission lines are used
ΣCL is zero in equation 2 and can be eliminated. In
general, the use of controlled transmission line
techniques eliminates the impact of the lumped capacitive
loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die
junction temperature TJ as a function of the power
consumption.
Table 8. Die junction temperature and MTBF
Junction temperature
MTBF (Years)
(°C)
100
110
120
130
20.4
9.1
4.2
2.0
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 8, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM2I9942P in a
series terminated transmission line system, equation 4.
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM2I9942P
needs to be controlled and the thermal impedance of the
board/package should be optimized.The power dissipated
in the ASM2I9942P is represented in equation 1.
Where ICCQ is the static current consumption of the
ASM2I9942P, CPD is the power dissipation capacitance
P
= ICCQ + VCC ⋅ fCLOCK ⋅ N ⋅ C
+
C
⋅VCC
Equation1
L
∑
TOT
PD
M
P
=VCC ⋅ ICCQ + VCC ⋅ fCLOCK ⋅ N ⋅ C
+
C
+
[
∑
P
DC ⋅ I
(
VCC −VOH
)
+
(
1− DCQ
)
⋅ IOL ⋅VOL
]
Equation 2
Equation 3
L
∑
TOT
PD
Q
OH
M
TJ = TA + P ⋅ Rthja
TOT
TJMAX − TA
1
(
)
fCLOCKMAX
=
⋅
− ICCQ ⋅VCC
Equation 4
CPD ⋅ N ⋅VC2C
Rthja
Low Voltage 1:18 Clock Distribution Chip
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Notice: The information in this document is subject to change without notice.
May 2005
rev 0.3
ASM2I9942P
TJ,MAX should be selected according to the MTBF
system requirements and Table 8. Rthja can be derived
from Table 9. The Rthja represent data based on 1S2P
boards, using 2S2P boards will result in lower thermal
impedance than indicated below.
If the calculated maximum frequency is below 350 MHz, it
becomes the upper clock speed limit for the given
application conditions. The following eight derating charts
describe the safe frequency operation range for the
ASM2I9942P. The charts were calculated for a maximum
tolerable die junction temperature of 110°C (120°C),
corresponding to an estimated MTBF of 9.1 years
(4 years), a supply voltage of 3.3V and series terminated
transmission line or capacitive loading. Depending on a
given set of these operating conditions and the available
device convection a decision on the maximum operating
frequency can be made.
Table 9. Thermal package impedance of the
32LQFP
Convection,
LFPM
Rthja (1P2S
Rthja (2P2S
board), °C/W
board), °C/W
Still air
86
76
71
68
66
60
61
56
54
53
52
49
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
6 of 10
May 2005
ASM2I9942P
rev 0.3
Package Information
32-lead TQFP Package
SECTION A-A
Dimensions
Millimeters
Symbol
Inches
Min
Max
Min
…
Max
1.2
A
A1
A2
D
D1
E
….
0.0472
0.0059
0.0413
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0374
0.3465
0.2717
0.3465
0.2717
0.0177
0.05
0.95
8.8
0.15
1.05
9.2
6.9
7.1
8.8
9.2
E1
L
6.9
7.1
0.45
0.75
L1
T
T1
b
b1
R0
a
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0°
0.0079
0.0062
0.0177
0.0157
0.0079
7°
0.09
0.097
0.30
0.30
0.08
0°
0.2
0.157
0.45
0.40
0.2
7°
e
0.031 BASE
0.8 BASE
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
7 of 10
May 2005
rev 0.3
ASM2I9942P
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Millimeters
Min
….
Max
Min
…
0.05
1.35
8.8
6.9
8.8
6.9
0.45
Max
1.6
0.15
1.45
9.2
7.1
9.2
7.1
0.75
A
A1
A2
D
D1
E
0.0630
0.0059
0.0571
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0531
0.3465
0.2717
0.3465
0.2717
0.0177
E1
L
L1
T
T1
b
b1
R0
e
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0.0079
0.0062
0.0177
0.0157
0.0079
0.09
0.097
0.30
0.30
0.08
0.2
0.157
0.45
0.40
0.20
0.031 BASE
0.8 BASE
a
0°
7°
0°
7°
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
8 of 10
May 2005
ASM2I9942P
rev 0.3
Ordering Information
Marking
ASM2I9942PL
Ordering Code
ASM2I9942P-32-LT
ASM2I9942P-32-LR
ASM2I9942PG-32-LT
ASM2I9942PG-32-LR
ASM2I9942P-32-ET
ASM2I9942P-32-ER
ASM2I9942PG-32-ET
ASM2I9942PG-32-ER
Package Type
32-pin LQFP, Tray
Operating Range
Industrial
ASM2I9942PL
ASM2I9942PGL
ASM2I9942PGL
ASM2I9942PE
ASM2I9942PE
ASM2I9942PGE
ASM2I9942PGE
32-pin LQFP,Tape and Reel
32-pin LQFP, Tray, Green
32-pin LQFP,Tape and Reel, Green
32-pin TQFP, Tray
32-pin TQFP,Tape and Reel
32-pin TQFP, Green
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
32-pin TQFP,Tape and Reel, Green
Device Ordering Information
A S M 2 I 9 9 4 2 P G - 3 2 - L R
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
9 of 10
May 2005
rev 0.3
ASM2I9942P
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM2I9942P
Document Version: 0.3
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
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other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
10 of 10
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