ASM2I99446G-32-LR [ALSC]
2.5V and 3.3V LVCMOS Clock Distribution Buffer; 2.5V和3.3V LVCMOS时钟分配缓冲区
| 型号： | ASM2I99446G-32-LR |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | 2.5V and 3.3V LVCMOS Clock Distribution Buffer |
| 文件： | 总14页 (文件大小：573K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2005
rev 0.4
ASM2I99446
2.5V and 3.3V LVCMOS Clock Distribution Buffer
Features
is specified for the extended temperature range of -40°C to
85°C.
Configurable 10 outputs LVCMOS clock
distribution buffer
Compatible to single, dual and mixed 3.3V/2.5V
Voltage supply
Wide range output clock frequency up to 250MHz
Designed for mid-range to high-performance
telecom, networking and computer applications
Supports applications requiring clock redundancy
Max. output skew of 200pS (150pS within one
bank)
Selectable output configurations per output bank
Tristatable outputs
32 lead LQFP & TQFP Packages
Ambient operating temperature range of
-40 to 85°C
The ASM2I99446 is a full static fanout buffer design
supporting clock frequencies up to 250MHz. The signals
are generated and retimed on-chip to ensure minimal skew
between the three output banks. Two independent
LVCMOS compatible clock inputs are available. This
feature supports redundant clock sources or the addition of
a test clock into the system design. Each of the three
output banks can be individually supplied by 2.5V or 3.3V
supporting mixed voltage applications. The FSELx pins
choose between division of the input reference frequency
by one or two. The frequency divider can be set individually
for each of the three output banks. The ASM2I99446 can
be reset and the outputs are disabled by deasserting the
MR/OE pin (logic high state). Asserting MR/OE will enable
the outputs.
-
Functional Description
All inputs accept LVCMOS signals while the outputs
provide LVCMOS compatible levels with the capability to
drive terminated 50Ω transmission lines. Please consult the
ASM2I99456 specification for a 1:10 mixed voltage buffer
with LVPECL compatible inputs. For series terminated
transmission lines, each of the ASM2I99446 outputs can
drive one or two traces giving the devices an effective
fanout of 1:20. The device is packaged in a 7x7mm2
32-lead LQFP and TQFP Packages.
The ASM2I99446 is a 2.5V and 3.3V compatible 1:10 clock
distribution buffer designed for low-voltage mid-range to
high-performance telecom, networking and computing
applications. Both 3.3V, 2.5V and dual supply voltages are
supported for mixed-voltage applications. The ASM2I99446
offers 10 low-skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1:1
and 1:2 output to input frequency ratios. The ASM2I99446
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
ASM2I99446
rev 0.4
Block Diagram
VCC
QA0
QA1
QA2
25K
0
1
0
1
CCLK0
CCLK1
CLK
VCC
25K
CLK-2
CCLK_SEL
QB0
QB1
QB2
25K
0
1
QC0
QC1
QC2
0
1
FSELA
25K
25K
25K
25K
FSELB
FSELC
QC3
MR/OE
Pin Configuration
32 – LEAD PACKAGE PINOUT -- Top View
20
17
19 18
24 23 22 21
QC3
VCCA
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
QA2
GND
QC2
GND
VCCC
QC1
GND
QA1
VCCA
ASM2I99446
QA0
QC0
VCCC
GND
MR/OE
5
8
1
2
3
4
6
7
2.5V and 3.3V LVCMOS Clock Distribution Buffer
2 of 14
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.4
ASM2I99446
Table 1: Pin Configuration
Pin Number
Pin
I/O
Input
Type
Function
3,4
CCLK0, CCLK1
LVCMOS LVCMOS clock inputs
5,6,7
FSELA, FSELB, FSELC
Input
LVCMOS Output bank divide select input
Internal reset and output (high impedance)
Input
-
LVCMOS
Supply
32
MR/OE
control
8,11,15,20,24,27,31 GND
Negative voltage supply (GND)
25,29
VCCA
,
18,22
VCCB
,
-
Supply
Supply
Positive voltage supply for output banks
9,13,17
VCCC
VCC
2
-
Positive voltage supply for core (VCC)
30,28, 26
23,21,19
10,12,14,16
QA0 - QA2
QB0 - QB2
QC0 - QC3
Output
Output
Output
LVCMOS Bank A outputs
LVCMOS Bank B outputs
LVCMOS Bank C outputs
Note: VCCB is internally connected to VCC
.
Table 2: Supported Single and Dual Supply Configurations
1
2
3
4
Supply voltage configuration
VCC
VCCA
VCCB
VCCC
GND
3.3V
3.3V
3.3V
2.5V
3.3V
3.3V or 2.5V
2.5V
3.3V
3.3V
2.5V
3.3V
3.3V or 2.5V
2.5V
0V
0 V
0 V
Mixed voltage supply
2.5V
Note: 1 VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels
2 VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels
3 VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels. VCCB is internally connected to VCC
.
4 VCCC is the positive power supply of the bank B outputs. VCCC voltage defines bank C output levels.
Table 3: Function Table (Controls)
Control
CCLK_SEL
FSELA
FSELB
FSELC
Default
0
1
0
0
0
0
CCLK0
CCLK1
fQA0:2 = fREF
FQBO:2 = fREF
FQCO:3 = fREF
f QA0:2 = fREF ÷2
f QBO:2 = fREF ÷2
f QCO:3 = fREF ÷2
MR/OE
0
Outputs enabled
Internal reset Outputs disabled (tristate)
Table 4: Absolute Maximum Ratings1
Symbol
VCC
VIN
Characteristics
Min
-0.3
-0.3
-0.3
Max
3.6
VCC+0.3
VCC+0.3
±20
Unit Condition
Supply Voltage
V
DC Input Voltage
V
VOUT
IIN
DC Output Voltage
DC Input Current
V
mA
mA
°C
IOUT
TS
DC Output Current
Storage temperature
±50
125
-65
Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
2.5V and 3.3V LVCMOS Clock Distribution Buffer
3 of 14
Notice: The information in this document is subject to change without notice.
July 2005
ASM2I99446
rev 0.4
Table 5: General Specifications
Symbol
VTT
MM
Characteristics
Min
Typ
VCC ÷2
Max
Unit Condition
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch–Up Immunity
V
200
2000
200
V
HBM
LU
V
mA
CPD
CIN
Power Dissipation Capacitance
Input Capacitance
10
4.0
pF
pF
Per output
Table 6: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = –40°C to +85°C)
Symbol Characteristics
Min
2.0
-0.3
Typ
Max
VCC + 0.3
0.8
Unit
Condition
LVCMOS
LVCMOS
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
Input Current 1
V
V
µA
V
V
V
200
VIN=GND or VIN=VCC
VOH
Output High Voltage
2.4
IOH=-24 mA2
0.55
0.30
IOL= 24mA3
IOL= 12mA
VOL
Output Low Voltage
ZOUT
ICCQ
Output Impedance
Maximum Quiescent Supply Current
14 - 17
Ω
3
2.0
mA
All VCC Pins
Note: 1 Input pull-up / pull-down resistors influence input current.
2 The ASM2I99446 is capable of driving 50ꢀ transmission lines on the incident edge. Each output drives one 50ꢀ parallel terminated transmission line
to a termination voltage of VTT. Alternatively, the device drives up to two 50ꢀ series terminated transmission lines.
3 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
2.5V and 3.3V LVCMOS Clock Distribution Buffer
4 of 14
Notice: The information in this document is subject to change without notice.
July 2005
ASM2I99446
rev 0.4
Table 7: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 3.3V ±5%, TA = –40°C to +85°C)1
Symbol
Characteristics
Min Typ Max
Unit
Condition
fref
Input Frequency
0
0
2502
MHz
÷1 output
÷2 output
2502
125
MHz
FSELx=0
FSELx=1
fMAX
Maximum Output Frequency
0
MHz
tP, REF
tr, tf
Reference Input Pulse Width
CCLK Input Rise/Fall Time
1.4
nS
nS
1.03
0.8 to 2.0V
tPLH
tPHL
CCLK0,1 to any Q
CCLK0,1 to any Q
2.2
2.2
2.8
2.8
4.45
nS
Propagation delay
4.2
nS
tPLZ, HZ
tPZL, LZ
Output Disable Time
Output Enable Time
Output-to-output Skew
10
10
nS
nS
150
200
350
pS
pS
pS
Within one bank
tsk(O)
Any output Bank, Same output divider
Any output, Any output divider
tsk(PP)
tSK(P)
Device-to-device Skew
2.25
200
nS
pS
Output pulse skew4
Output Duty Cycle
÷1 output
÷2 output
47
45
50
50
53
%
DCREF = 50%
DCQ
55
%
DC
= 25%-75%
REF
tr, tf
Output Rise/Fall Time
0.1
1.0
nS
0.55 to 2.4V
Note: 1 AC characteristics apply for parallel output termination of 50ꢀ to VTT
2 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
3 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
4 Output pulse skew is the absolute difference of the propagation delay times | tpLH - tpHL |.
Table 8: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)
Symbol
VIH
VIL
VOH
VOL
ZOUT
Characteristics
Min
1.7
-0.3
1.8
Typ
Max
VCC + 0.3
0.7
Unit
V
V
V
V
Condition
Input High Voltage
LVCMOS
Input Low Voltage
LVCMOS
Output High Voltage
Output Low Voltage
Output Impedance
IOH=-15 mA1
IOL= 15 mA
0.6
17 - 202
ꢀ
IIN
ICCQ
Input Current2
±200
2.0
µA
mA
VIN=GND or VIN=VCC
All VCC Pins
3
Maximum Quiescent Supply Current
Note: 1 The ASM2I99446 is capable of driving 50ꢀ transmission lines on the incident edge. Each output drives one 50ꢀ parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up to two 50ꢀ series terminated transmission lines per output.
2 Input pull-up / pull-down resistors influence input current.
3 ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
2.5V and 3.3V LVCMOS Clock Distribution Buffer
5 of 14
Notice: The information in this document is subject to change without notice.
July 2005
ASM2I99446
rev 0.4
Table 9: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)1,2
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
2503
MHz
÷1 output
÷2 output
0
2502
125
MHz
FSELx=0
FSELx=1
fMAX
Maximum Output Frequency
0
MHz
tP, REF
tr, tf
Reference Input Pulse Width
CCLK Input Rise/Fall Time
1.4
nS
nS
1.04
0.7 to 1.7V
tPLH
tPHL
tPLZ, HZ
CCLK0,1 to any Q
CCLK0,1 to any Q
2.6
2.6
5.6
nS
Propagation delay
5.5
nS
Output Disable Time
Output Enable Time
10
10
nS
nS
tPZL, LZ
Output-to-output Skew
Within one bank
150
200
350
pS
pS
pS
tsk(O)
Any output Bank, Same output divider
Any output, Any output divider
tsk(PP)
tSK(P)
Device-to-device Skew
Output pulse skew5
3.0
nS
200
pS
DCQ
tr, tf
Output Duty Cycle
÷1 or ÷2 output
45
0.1
50
55
1.0
%
nS
DCREF = 50%
0.6 to 1.8V
Output Rise/Fall Time
Note: 1 AC characteristics apply for parallel output termination of 50ꢀ to VTT
.
2 AC specifications are design targets, final specification is pending device characterization.
3 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
5 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 10: AC CHARACTERISTICS (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%, TA = –40°C to +85°C)1,2
Symbol
Characteristics
Min
Typ
Max Unit
Condition
Output-to-output Skew
Within one bank
150
250
350
pS
pS
pS
tsk(O)
Any output Bank, Same output divider
Any output, Any output divider
tsk(PP)
Device-to-device Skew
2.5
nS
tPLH,HL
Propagation delay
Output pulse skew3
Output Duty Cycle
CCLK0,1 to any Q
÷1 or ÷2 output
See 3.3V table
tSK(P)
DCQ
250
pS
%
45
50
55
DCREF = 50%
Note: 1 AC characteristics apply for parallel output termination of 50ꢀ to VTT
.
2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
3 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
2.5V and 3.3V LVCMOS Clock Distribution Buffer
6 of 14
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.4
ASM2I99446
APPLICATIONS INFORMATION
impedance mismatch seen looking into the driver. The
parallel combination of the 36ꢀ series resistor plus the
output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
Driving Transmission Lines
The ASM2I99446 clock driver was designed to drive high
speed signals in
a
terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 20ꢀ the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50ꢀ
resistance to VCC÷2.
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50ꢀ || 50ꢀ
RS = 36ꢀ || 36ꢀ
R0 = 14ꢀ
VL = 3.0 ( 25 ÷ (18+14+25)) = 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the ASM2I99446 clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 3. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme the fanout of the ASM2I99446 clock driver
is effectively doubled due to its capability to drive multiple
lines.
round trip delay (in this case 4.0nS).
OutA
OutB
1.5
tD = 3.8956
tD = 3.9386
In
0.5
ASM2I99446
OUTPUT BUFFER
Z0=50ꢀ
RS=36ꢀ
IN
IN
14ꢀ
OUTA
2
4
12
14
ASM2I99446
Z0=50ꢀ
Z0=15ꢀ
RS=36ꢀ
RS=36ꢀ
OUTPUT BUFFER
OUTB0
OUTB1
Figure 4. Single versus Dual Waveforms
14ꢀ
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 5. “Optimized Dual
Line Termination” should be used. In this case the series
terminating resistors are reduced such that when the
parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
Figure 3. Single versus Dual Transmission
Lines
The waveform plots in Figure 4. “Single versus Dual Line
Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both
cases the drive capability of the ASM2I99446 output
buffer is more than sufficient to drive 50ꢀ transmission
lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43pS
exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of
the ASM2I99446. The output waveform in Figure 4
“Single versus Dual Line Termination Waveforms” shows
a step in the waveform. This step is caused by the
ASM2I99446
Z0=50ꢀ
RS=22ꢀ
OUTPUT BUFFER
14ꢀ
IN
Z0=50ꢀ
RS=22ꢀ
14Ω + 22Ω║22Ω = 50Ω║50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
2.5V and 3.3V LVCMOS Clock Distribution Buffer
7 of 14
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.4
ASM2I99446
ASM2I99446
Z0=50Ω
Z0=50Ω
Pulse
Generator
Z=50Ω
RT=50Ω
R=50Ω
Figure 6. CCLK0, 1 ASM2I99446 AC test reference for VCC = 3.3V and VCC = 2.5V
VCC
CCLK
VCC ÷2
GND
VCC = 3.3V VCC = 2.5V
2.4
1.8V
0.6V
VCC
QX
V
CC ÷2
0.55
GND
t(LH)
t(HL)
tR
tF
Figure 7. Output Transition Time Test Reference
Figure 8. Propagation Delay (t) Test Reference
VCC
VCC ÷2
GND
CCLK
VCC
VCC ÷2
GND
VCC
QX
V
CC ÷2
VOH
VCC ÷2
GND
t(LH)
t(HL)
SK(P) │tPLH- tPHL
GND
tSK(LH)
tSK(HL)
t
│
The pin-to-pin skew is defined as the worst case
difference in propagation delay between any similar
delay path within a single device
Figure 10. Propagation Delay (t) Test Reference
Figure 9. Output–to–Output Skew t
VCC
VCC ÷2
GND
TJIT(CC) = |TN -TN + 1|
TN
TN + 1
tP
The variation in cycle time of a signal between adjacent
cycles, over a random sample of adjacent cycle pairs
T0
DC (tP ÷T0 Χ 100%)
The time from the PLL controlled edge to the
non-controlled edge, divided by the time
between PLL controlled edges, expressed as a
percentage.
Figure 11. Output Duty Cycle (DC) Reference
2.5V and 3.3V LVCMOS Clock Distribution Buffer
8 of 14
Notice: The information in this document is subject to change without notice.
July 2005
ASM2I99446
rev 0.4
Where ICCQ is the static current consumption of the
ASM2I99446, CPD is the power dissipation capacitance
Power Consumption of the ASM2I99446 and
Thermal Management
per output, (Μ)ΣCL represents the external capacitive
output load, N is the number of active outputs (N is
always 12 in case of the ASM2I99446). The ASM2I99446
supports driving transmission lines to maintain high signal
integrity and tight timing parameters. Any transmission
line will hide the lumped capacitive load at the end of the
board trace, therefore, ΣCL is zero for controlled
transmission line systems and can be eliminated from
equation 1. Using parallel termination output termination
results in equation 2 for power dissipation.
The ASM2I99446 AC specification is guaranteed for the
entire operating frequency range up to 250MHz. The
ASM2I99446 power consumption and the associated
long-term reliability may decrease the maximum
frequency limit, depending on operating conditions such
as clock frequency, supply voltage, output loading,
ambient temperature, vertical convection and thermal
conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the
ASM2I99446 die junction temperature and the associated
device reliability.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, VOL, IOL, VOH and IOH are
a function of the output termination technique and DCQ is
the clock signal duty cycle. If transmission lines are used
ΣCL is zero in equation 2 and can be eliminated. In
general, the use of controlled transmission line
techniques eliminates the impact of the lumped capacitive
loads at the end lines and greatly reduces the power
dissipation of the device. Equation 3 describes the die
junction temperature TJ as a function of the power
consumption.
Table 11. Die junction temperature and MTBF
Junction temperature (°C)
MTBF (Years)
100
110
120
130
20.4
9.1
4.2
2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable
MTBF, the die junction temperature of the ASM2I99446
needs to be controlled and the thermal impedance of the
board/package should be optimized. The power
Where Rthja is the thermal impedance of the package
(junction to ambient) and TA is the ambient temperature.
According to Table 11, the junction temperature can be
used to estimate the long-term device reliability. Further,
combining equation 1 and equation 2 results in a
maximum operating frequency for the ASM2I99446 in a
series terminated transmission line system, equation 4.
dissipated in the ASM2I99446
equation 1.
is represented in
2.5V and 3.3V LVCMOS Clock Distribution Buffer
9 of 14
Notice: The information in this document is subject to change without notice.
July 2005
ASM2I99446
rev 0.4
TJ,MAX should be selected according to the MTBF
system requirements and Table 11. Rthja can be derived
from Table 12. The Rthja represent data based on 1S2P
boards, using 2S2P boards will result in a lower thermal
impedance than indicated below.
If the calculated maximum frequency is below 350 MHz, it
becomes the upper clock speed limit for the given
application conditions. The following eight derating charts
describe the safe frequency operation range for the
ASM2I99446. The charts were calculated for a maximum
tolerable die junction temperature of 110°C (120°C),
corresponding to an estimated MTBF of 9.1 years
(4 years), a supply voltage of 3.3V and series terminated
transmission line or capacitive loading. Depending on a
given set of these operating conditions and the available
device convection a decision on the maximum operating
frequency can be made.
Table 12. Thermal package impedance of the
32LQFP
Convection,
Rthja (1P2S
Rthja (2P2S
LFPM
board), °C/W
board), °C/W
Still air
86
76
71
68
66
60
61
56
54
53
52
49
100 lfpm
200 lfpm
300 lfpm
400 lfpm
500 lfpm
2.5V and 3.3V LVCMOS Clock Distribution Buffer
10 of
Notice: The information in this document is subject to change without notice.
July 2005
ASM2I99446
rev 0.4
Package Information
32-lead TQFP Package
SECTION A-A
Dimensions
Millimeters
Symbol
Inches
Min
Max
Min
…
Max
1.2
A
A1
A2
D
D1
E
….
0.0472
0.0059
0.0413
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0374
0.3465
0.2717
0.3465
0.2717
0.0177
0.05
0.95
8.8
0.15
1.05
9.2
6.9
7.1
8.8
9.2
E1
L
6.9
7.1
0.45
0.75
L1
T
T1
b
b1
R0
a
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0°
0.0079
0.0062
0.0177
0.0157
0.0079
7°
0.09
0.097
0.30
0.30
0.08
0°
0.2
0.157
0.45
0.40
0.2
7°
e
0.031 BASE
0.8 BASE
2.5V and 3.3V LVCMOS Clock Distribution Buffer
11 of
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.4
ASM2I99446
32-lead LQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Millimeters
Min
….
Max
Min
…
0.05
1.35
8.8
6.9
8.8
6.9
0.45
Max
1.6
0.15
1.45
9.2
7.1
9.2
7.1
0.75
A
A1
A2
D
D1
E
0.0630
0.0059
0.0571
0.3622
0.2795
0.3622
0.2795
0.0295
0.0020
0.0531
0.3465
0.2717
0.3465
0.2717
0.0177
E1
L
L1
T
T1
b
b1
R0
e
0.03937 REF
1.00 REF
0.0035
0.0038
0.0118
0.0118
0.0031
0.0079
0.0062
0.0177
0.0157
0.0079
0.09
0.097
0.30
0.30
0.08
0.2
0.157
0.45
0.40
0.20
0.031 BASE
0.8 BASE
a
0°
7°
0°
7°
2.5V and 3.3V LVCMOS Clock Distribution Buffer
12 of
Notice: The information in this document is subject to change without notice.
July 2005
ASM2I99446
rev 0.4
Ordering Information
Part Number
ASM2I99446-32-LT
ASM2I99446-32-LR
ASM2I99446G-32-LT
ASM2I99446G-32-LR
ASM2I99446-32-ET
ASM2I99446-32-ER
ASM2I99446G-32-ET
ASM2I99446G-32-ER
Marking
Package Type
32-pin LQFP, Tray
Operating Range
Industrial
ASM2I99446L
ASM2I99446L
ASM2I99446GL
ASM2I99446GL
ASM2I99446E
ASM2I99446E
ASM2I99446GE
ASM2I99446GE
32-pin LQFP,Tape and Reel
32-pin LQFP, Tray, Green
32-pin LQFP, Tape and Reel, Green
32-pin TQFP, Tray
32-pin TQFP,Tape and Reel
32-pin TQFP, Tray, Green
32-pin TQFP,Tape and Reel, Green
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Device Ordering Information
A S M 2 I 9 9 4 4 6 G - 3 2 - L R
R = Tape & reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V and 3.3V LVCMOS Clock Distribution Buffer
13 of
Notice: The information in this document is subject to change without notice.
July 2005
rev 0.4
ASM2I99446
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM2I99446
Document Version: 0.4
Fax: 408-855-4999
www.alsc.com
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
2.5V and 3.3V LVCMOS Clock Distribution Buffer
14 of
Notice: The information in this document is subject to change without notice.
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