P1707A [ALSC]
Notebook LCD Panel EMI Reduction IC; 笔记本电脑液晶面板降低EMI IC型号: | P1707A |
厂家: | ALLIANCE SEMICONDUCTOR CORPORATION |
描述: | Notebook LCD Panel EMI Reduction IC |
文件: | 总10页 (文件大小:209K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
October 2003
rev 1.0
P1707A
Notebook LCD Panel EMI Reduction IC
Features
down stream clock and data dependent signals. The
P1707A allows significant system cost savings by reducing
the number of circuit board layers ferrite beads, shielding
and other passive components that are traditionally
required to pass EMI regulations.
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FCC approved method of EMI attenuation.
Generates a low EMI spread spectrum clock of the
input frequency.
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Optimized for frequency range from 60 to 175MHz.
Internal loop filter minimizes external components
and board space.
The P1707A modulates the output of a single PLL in order
to “spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
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Four selectable spread ranges.
Low inherent cycle-to-cycle jitter.
3.3V operating voltage range.
TTL or CMOS compatible inputs and outputs.
Ultra-low power CMOS design.
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14.85 mA @3.3V, 140MHz
16.69mA @3.3V, 162MHz
17.78 mA @3.3V, 175MHz
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Supports notebook VGA and other LCD timing
controller applications.
The P1707A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
Pinout compatible to ICS MK1707 and Cypress
CY25561/CY25560.
SSON/SBM pin for Spread Spectrum On/Off
and Standby Mode controls.
Applications
Available in 8-pin SOIC and TSSOP.
The P1707A is targeted towards notebook LCD displays,
and other displays using an LVDS interface, PC peripheral
devices, and embedded systems.
Product Description
The P1707A is a versatile spread spectrum frequency
modulator designed specifically for input clock frequencies.
The P1707A reduces electromagnetic interference (EMI) at
the clock source, allowing system wide reduction of EMI of
SSON
SR1
SR0
VDD
Block Diagram
PLL
Modulation
CLKIN
Frequency
Divider
Output
Divider
Phase
Detector
Loop
Filter
VCO
Feedback
Divider
ModOUT
VSS
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
October 2003
rev 1.0
P1707A
Pin Configuration
1
2
3
4
8
7
6
5
CLKIN
VDD
VSS
NC
SR0
SR1
P1707A
ModOUT
SSON/SBM
Pin Description
Pin#
Pin Name
Type
Description
Connect to externally generated clock signal. To put the part into standby
mode, disable the input clock signal to this pin and pull SSON/SBM (pin 5)
low. Refer Standby Mode Selection Table.
1
CLKIN
I
2
3
4
VDD
VSS
P
P
O
Connect to +3.3V.
Ground Connection. Connect to system ground.
Spread spectrum clock output.
ModOUT
Spread Spectrum On/Off and standby mode control. Refer Standby Mode
Selection Table. This pin has an internal pull-up resistor.
Digital logic input used to select Spreading Range. Refer Spread Spectrum
Selection Table. This pin has an internal pull-up resistor.
5
6
SSON/SBM
SR1
I
I
Digital logic input used to select Spreading Range. Refer Spread Spectrum
Selection Table. This pin has an internal pull-up resistor.
7
8
SR0
NC
I
-
No connect.
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Notice: The information in this document is subject to change without notice.
October 2003
P1707A
rev 1.0
Standby Mode Selection
Spread
Spectrum
CLKIN
SSON/SBM
ModOUT
PLL
Mode
Disabled
Disabled
Enabled
Enabled
0
1
0
1
N/A
N/A
Off
Disabled
Disabled
Reference
Normal
Disabled
Free Running
Disabled
Standby
Free Running
Buffer out
Normal
On
Normal
Spread Range Selection
SR1
SR0
Spreading Range
± 1.50%
Modulation Rate
0
0
1
1
0
1
0
1
(FIN/80) * 34.72 KHz
(FIN/80) * 34.72 KHz
(FIN/80) * 34.72 KHz
(FIN/80) * 34.72 KHz
± 2.50%
± 0.50%
± 1.00%
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Notice: The information in this document is subject to change without notice.
October 2003
rev 1.0
P1707A
Schematic for Notebook VGA Application
P1707A
60MHz to 175MHz pixel clock input
from VGA chip
Pin 8 can be tied either high or low,
or it can be left unconnected.
NC
8
7
6
5
1
2
3
4
CLKIN
0.1µF
FB
VDD
SR0
SR1
Tie SR0 and SR1 high/low
according to spread range desired.
External resistors are not needed to
pull these pins high.
VDD
VSS
Pin 5 SSON should be left unconnected to turn on
spread spectrum. Pull this pin low to turn spread
spectrum OFF and enable stand-by mode.
ModOUT SSON
Note: To set the P1707A to standby mode, disable the input clock (pin 1 CLKIN) and pull SSON (pin 5) low. Refer Standby Mode Selection
Table.
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Notice: The information in this document is subject to change without notice.
October 2003
P1707A
rev 1.0
Absolute Maximum Ratings
Symbol
VDD, VIN
TSTG
Parameter
Voltage on any pin with respect to GND
Storage temperature
Rating
-0.5 to + 7.0
-65 to +125
0 to 70
Unit
V
°C
°C
TA
Operating temperature
Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VIL
VIH
Input low voltage
Input high voltage
GND – 0.3
2.0
-
-
0.8
V
V
VDD + 0.3
Input low current (pull-up resistors on inputs SR0, SR1
and SSON/SBM)
IIL
-
-
-35
µA
IIH
Input high current
-
-
3
3
-
35
µA
mA
mA
V
IXOL
IXOH
VOL
VOH
XOUT output low current @ 0.4V, VDD = 3.3V
XOUT output high current @ 2.5V, VDD = 3.3V
Output low voltage VDD = 3.3V, IOL = 20mA
Output high voltage VDD = 3.3V, IOH = 20mA
-
-
-
-
-
0.4
-
2.5
-
V
Dynamic supply current normal mode
3.3V and 10pF loading
ICC
8.46
12
17.78
mA
IDD
Static supply current standby mode
Operating voltage
-
2.7
-
0.6
3.3
-
3.7
-
mA
V
VDD
tON
Power up time (first locked clock cycle after power up)
Clock output impedance
0.18
50
mS
Ω
ZOUT
-
-
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Notice: The information in this document is subject to change without notice.
October 2003
rev 1.0
P1707A
AC Electrical Characteristics
Symbol
Parameter
Min
60
Typ
Max
175
175
Unit
fIN
Input frequency
Output frequency
-
-
MHz
MHz
fOUT
60
Output rise time
Measured at 0.8V to 2.0V
tLH*
tHL*
0.7
0.6
0.9
0.8
1.1
1.0
ns
ns
Output fall time
Measured at 0.8V to 2.0V
tJC
tD
Jitter (cycle to cycle)
Output duty cycle
-
-
360
55
ps
%
45
50
*tLH and tHL are measured into a capacitive load of 15pF
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Notice: The information in this document is subject to change without notice.
October 2003
rev 1.0
P1707A
Package Information
Mechanical Package Outline 8-Pin SOIC
H
E
D
A2
A
C
θ
e
A1
D
L
B
Symbol Dimensions in inches Dimensions in millimeters
Min
Max
0.071
0.010
0.069
0.020
0.01
Min
1.45
0.10
1.35
0.31
0.10
4.72
3.75
Max
1.80
0.25
1.75
0.51
0.25
5.12
4.15
A
A1
A2
B
0.057
0.004
0.053
0.012
0.004
0.186
0.148
C
D
E
0.202
0.164
e
0.050 BSC
1.27 BSC
H
L
0.224
0.012
0°
0.248
0.028
8°
5.70
0.30
0°
6.30
0.70
8°
θ
Note: Controlling dimensions are millimeters
SOIC – 0.074 grams unit weight
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Notice: The information in this document is subject to change without notice.
October 2003
rev 1.0
P1707A
Mechanical Package Outline 8-Pin TSSOP
H
E
D
A2
A
C
θ
e
A1
L
B
Dimensions in inches
Dimensions in millimeters
Symbol
Min
Max
Min
Max
1.10
0.15
1.05
0.30
0.20
3.10
4.50
A
A1
A2
B
0.047
0.006
0.041
0.012
0.008
0.122
0.177
0.002
0.031
0.007
0.004
0.114
0.169
0.05
0.80
0.19
0.09
2.90
4.30
C
D
E
e
0.026 BSC
0.65 BSC
H
L
0.244
0.018
0°
0.260
0.030
8°
6.20
0.45
0°
6.60
0.75
8°
θ
Note: Controlling dimensions are millimeters
TSSOP – 0.034 grams unit weight
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Notice: The information in this document is subject to change without notice.
October 2003
P1707A
rev 1.0
Ordering Codes
Temperature
(°C)
Part Number
Marking
Package Type
Qty per reel
P1707A-08ST
P1707A-08SR
P1707A-08TT
P1707A-08TR
P1707A
P1707A
P1707A
P1707A
8-pin SOIC, tube
8-pin SOIC, tape & reel
8-pin TSSOP, tube
0 to 70
0 to 70
0 to 70
0 to 70
2500
2500
8-pin TSSOP, tape and reel
Device Ordering Information
P 1 7 0 7 A - 0 8 X X
OR - SOT23/T/R
SR - SOIC, T/R
TT – TSSOP, TUBE
TR - TSSOP, T/R
VT – TVSOP, TUBE
VR – TVSOP, T/R
ST – SOIC, TUBE
QR – QFN, T/R
QT - QFN, TUBE
BT - BGA, TUBE
BR – BGA, T/R
Pin Count
DEVICE NUMBER
Flow:
P = Commercial Temperature Range (0°C to 70°C)
I = Industrial Temperature Range (-25°C to 85°C)
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Notice: The information in this document is subject to change without notice.
October 2003
rev 1.0
P1707A
Alliance Semiconductor Corporation
2595, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Copyright © Alliance Semiconductor
All Rights Reserved
Preliminary Information
Part Number: P1707A
Document Version: v1.0
Fax: 408-855-4999
www.alsc.com
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Notice: The information in this document is subject to change without notice.
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