EP1C20F144I6ES [ALTERA]
Cyclone FPGA Family Data Sheet; 气旋FPGA系列数据手册
| 型号： | EP1C20F144I6ES |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | Cyclone FPGA Family Data Sheet |
| 文件： | 总104页 (文件大小：1353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Section I. Cyclone FPGA
Family Data Sheet
This section provides designers with the data sheet specifications for
Cyclone® devices. The chapters contain feature definitions of the internal
architecture, configuration and JTAG boundary-scan testing information,
DC operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Cyclone devices.
This section contains the following chapters:
■
■
■
■
■
Chapter 1. Introduction
Chapter 2. Cyclone Architecture
Chapter 3. Configuration & Testing
Chapter 4. DC & Switching Characteristics
Chapter 5. Reference & Ordering Information
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the complete handbook.
Revision History
Altera Corporation
Section I–1
Preliminary
Revision History
Cyclone Device Handbook, Volume 1
Section I–2
Preliminary
Altera Corporation
1. Introduction
C51001-1.4
The Cyclone® field programmable gate array family is based on a 1.5-V,
0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic
elements (LEs) and up to 288 Kbits of RAM. With features like phase-
locked loops (PLLs) for clocking and a dedicated double data rate (DDR)
interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory
requirements, Cyclone devices are a cost-effective solution for data-path
applications. Cyclone devices support various I/O standards, including
LVDS at data rates up to 640 megabits per second (Mbps), and 66- and
33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for
interfacing with and supporting ASSP and ASIC devices. Altera also
offers new low-cost serial configuration devices to configure Cyclone
devices.
Introduction
The following shows the main sections in the Cyclone FPGA Family Data
Sheet:
Section
Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–12
Embedded Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18
Global Clock Network & Phase-Locked Loops. . . . . . . . . . . 2–29
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39
Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . . 2–55
IEEE Std. 1149.1 (JTAG) Boundary Scan Support. . . . . . . . . . 3–1
SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3–5
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8
Timing Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9
Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1
Altera Corporation
January 2007
1–1
Preliminary
Cyclone Device Handbook, Volume 1
The Cyclone device family offers the following features:
Features
■
■
■
■
■
■
■
■
■
2,910 to 20,060 LEs, see Table 1–1
Up to 294,912 RAM bits (36,864 bytes)
Supports configuration through low-cost serial configuration device
Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards
Support for 66- and 33-MHz, 64- and 32-bit PCI standard
High-speed (640 Mbps) LVDS I/O support
Low-speed (311 Mbps) LVDS I/O support
311-Mbps RSDS I/O support
Up to two PLLs per device provide clock multiplication and phase
shifting
■
■
■
Up to eight global clock lines with six clock resources available per
logic array block (LAB) row
Support for external memory, including DDR SDRAM (133 MHz),
FCRAM, and single data rate (SDR) SDRAM
Support for multiple intellectual property (IP) cores, including
®
®
Altera MegaCore functions and Altera Megafunctions Partners
SM
Program (AMPP ) megafunctions.
Table 1–1. Cyclone Device Features
Feature
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
LEs
2,910
13
4,000
17
5,980
20
12,060
52
20,060
64
M4K RAM blocks (128 × 36 bits)
Total RAM bits
59,904
1
78,336
2
92,160
2
239,616
2
294,912
2
PLLs
Maximum user I/O pins (1)
104
301
185
249
301
Note to Table 1–1:
(1) This parameter includes global clock pins.
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Preliminary
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January 2007
Features
Cyclone devices are available in quad flat pack (QFP) and space-saving
FineLine® BGA packages (see Table 1–2 through 1–3).
Table 1–2. Cyclone Package Options & I/O Pin Counts
100-Pin TQFP 144-Pin TQFP 240-PinPQFP
256-Pin
324-Pin
400-Pin
Device
(1)
(1), (2)
(1)
FineLine BGA FineLine BGA FineLine BGA
EP1C3
65
104
EP1C4
EP1C6
EP1C12
EP1C20
249
301
301
98
185
173
185
185
249
233
Notes to Table 1–2:
(1) TQFP: thin quad flat pack.
PQFP: plastic quad flat pack.
(2) Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the
EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package)
Vertical migration means you can migrate a design from one device to
another that has the same dedicated pins, JTAG pins, and power pins, and
are subsets or supersets for a given package across device densities. The
largest density in any package has the highest number of power pins; you
must use the layout for the largest planned density in a package to
provide the necessary power pins for migration.
For I/O pin migration across densities, cross-reference the available I/O
pins using the device pin-outs for all planned densities of a given package
type to identify which I/O pins can be migrated. The Quartus® II
software can automatically cross-reference and place all pins for you
when given a device migration list. If one device has power or ground
pins, but these same pins are user I/O on a different device that is in the
migration path,the Quartus II software ensures the pins are not used as
user I/O in the Quartus II software. Ensure that these pins are connected
to the appropriate plane on the board. The Quartus II software reserves
I/O pins as power pins as necessary for layout with the larger densities
in the same package having more power pins.
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January 2007
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Preliminary
Cyclone Device Handbook, Volume 1
Table 1–3. Cyclone QFP & FineLine BGA Package Sizes
256-Pin
FineLine
BGA
324-Pin
FineLine
BGA
400-Pin
FineLine
BGA
100-Pin
TQFP
144-Pin
TQFP
240-Pin
PQFP
Dimension
Pitch (mm)
0.5
256
0.5
484
0.5
1.0
289
1.0
361
1.0
441
Area (mm2)
1,024
Length × width
(mm × mm)
16 × 16
22 × 22
34.6 × 34.6
17 × 17
19 × 19
21 × 21
Table 1–4 shows the revision history for this document.
Document
Revision History
Table 1–4. Document Revision History
Date &
Document
Version
Changes Made
Summary of Changes
January 2007
v1.4
Added document revision history.
Minor updates.
Added 64-bit PCI support information.
August 2005
v1.3
October 2003
v1.2
September
2003 v1.1
●
●
Updated LVDS data rates to 640 Mbps from 311 Mbps.
Updated RSDS feature information.
May 2003 v1.0 Added document to Cyclone Device Handbook.
1–4
Preliminary
Altera Corporation
January 2007
2. Cyclone Architecture
C51002-1.5
Cyclone® devices contain a two-dimensional row- and column-based
architecture to implement custom logic. Column and row interconnects
of varying speeds provide signal interconnects between LABs and
embedded memory blocks.
Functional
Description
The logic array consists of LABs, with 10 LEs in each LAB. An LE is a
small unit of logic providing efficient implementation of user logic
functions. LABs are grouped into rows and columns across the device.
Cyclone devices range between 2,910 to 20,060 LEs.
M4K RAM blocks are true dual-port memory blocks with 4K bits of
memory plus parity (4,608 bits). These blocks provide dedicated true
dual-port, simple dual-port, or single-port memory up to 36-bits wide at
up to 250 MHz. These blocks are grouped into columns across the device
in between certain LABs. Cyclone devices offer between 60 to 288 Kbits of
embedded RAM.
Each Cyclone device I/O pin is fed by an I/O element (IOE) located at the
ends of LAB rows and columns around the periphery of the device. I/O
pins support various single-ended and differential I/O standards, such as
the 66- and 33-MHz, 64- and 32-bit PCI standard and the LVDS I/O
standard at up to 640 Mbps. Each IOE contains a bidirectional I/O buffer
and three registers for registering input, output, and output-enable
signals. Dual-purpose DQS, DQ, and DM pins along with delay chains
(used to phase-align DDR signals) provide interface support with
external memory devices such as DDR SDRAM, and FCRAM devices at
up to 133 MHz (266 Mbps).
Cyclone devices provide a global clock network and up to two PLLs. The
global clock network consists of eight global clock lines that drive
throughout the entire device. The global clock network can provide
clocks for all resources within the device, such as IOEs, LEs, and memory
blocks. The global clock lines can also be used for control signals. Cyclone
PLLs provide general-purpose clocking with clock multiplication and
phase shifting as well as external outputs for high-speed differential I/O
support.
Figure 2–1 shows a diagram of the Cyclone EP1C12 device.
Altera Corporation
January 2007
2–1
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–1. Cyclone EP1C12 Device Block Diagram
IOEs
Logic Array
PLL
EP1C12 Device
M4K Blocks
The number of M4K RAM blocks, PLLs, rows, and columns vary per
device. Table 2–1 lists the resources available in each Cyclone device.
Table 2–1. Cyclone Device Resources
M4K RAM
Device
PLLs
LAB Columns LAB Rows
Columns
Blocks
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
1
1
1
2
2
13
17
20
52
64
1
2
2
2
2
24
26
32
48
64
13
17
20
26
32
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Preliminary
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January 2007
Logic Array Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE's LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE's register to the
adjacent LE's register within an LAB. The Quartus® II Compiler places
associated logic within an LAB or adjacent LABs, allowing the use of
local, LUT chain, and register chain connections for performance and area
efficiency. Figure 2–2 details the Cyclone LAB.
Logic Array
Blocks
Figure 2–2. Cyclone LAB Structure
Row Interconnect
Column Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect from
adjacent block
Direct link
Direct link
interconnect to
adjacent block
interconnect to
adjacent block
LAB
Local Interconnect
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM
blocks from the left and right can also drive an LAB's local interconnect
through the direct link connection. The direct link connection feature
minimizes the use of row and column interconnects, providing higher
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January 2007
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Preliminary
Cyclone Device Handbook, Volume 1
performance and flexibility. Each LE can drive 30 other LEs through fast
local and direct link interconnects. Figure 2–3 shows the direct link
connection.
Figure 2–3. Direct Link Connection
Direct link interconnect from
left LAB, M4K memory
block, PLL, or IOE output
Direct link interconnect from
right LAB, M4K memory
block, PLL, or IOE output
Direct link
interconnect
to right
Direct link
interconnect
to left
Local
Interconnect
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs.
The control signals include two clocks, two clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load,
synchronous load, and add/subtract control signals. This gives a
maximum of 10 control signals at a time. Although synchronous load and
clear signals are generally used when implementing counters, they can
also be used with other functions.
Each LAB can use two clocks and two clock enable signals. Each LAB's
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1signal will also use labclkena1. If
the LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal will turn off
the LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. The asynchronous load acts as a preset when the
asynchronous load data input is tied high.
2–4
Preliminary
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January 2007
Logic Elements
With the LAB-wide addnsubcontrol signal, a single LE can implement a
one-bit adder and subtractor. This saves LE resources and improves
performance for logic functions such as DSP correlators and signed
multipliers that alternate between addition and subtraction depending
on data.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrackTM interconnect's inherent low skew
allows clock and control signal distribution in addition to data. Figure 2–4
shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
Dedicated
LAB Row
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena2
labclkena1
syncload
labclr2
addnsub
Local
Interconnect
labclk1
labclk2
asyncload
or labpre
labclr1
synclr
The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See Figure 2–5.
Logic Elements
Altera Corporation
January 2007
2–5
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–5. Cyclone LE
Register chain
routing from
previous LE
LAB-wide
Synchronous
Load
Register Bypass
Packed
LAB Carry-In
Programmable
Register
LAB-wide
Carry-In1
addnsub
Synchronous
Clear
Register Select
Carry-In0
LUT chain
routing to next LE
data1
Row, column,
and direct link
routing
PRN/ALD
data2
data3
Synchronous
Load and
Clear Logic
Look-Up
Table
(LUT)
Carry
Chain
D
Q
ADATA
data4
ENA
CLRN
Row, column,
and direct link
routing
labclr1
labclr2
Asynchronous
Clear/Preset/
Load Logic
Local Routing
labpre/aload
Chip-Wide
Reset
Register chain
output
Clock &
Clock Enable
Select
Register
Feedback
labclk1
labclk2
labclkena1
labclkena2
Carry-Out0
Carry-Out1
LAB Carry-Out
Each LE's programmable register can be configured for D, T, JK, or SR
operation. Each register has data, true asynchronous load data, clock,
clock enable, clear, and asynchronous load/preset inputs. Global signals,
general-purpose I/O pins, or any internal logic can drive the register's
clock and clear control signals. Either general-purpose I/O pins or
internal logic can drive the clock enable, preset, asynchronous load, and
asynchronous data. The asynchronous load data input comes from the
data3input of the LE. For combinatorial functions, the LUT output
bypasses the register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources. This
allows the LUT to drive one output while the register drives another
output. This feature, called register packing, improves device utilization
because the device can use the register and the LUT for unrelated
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January 2007
Logic Elements
functions. Another special packing mode allows the register output to
feed back into the LUT of the same LE so that the register is packed with
its own fan-out LUT. This provides another mechanism for improved
fitting. The LE can also drive out registered and unregistered versions of
the LUT output.
LUT Chain & Register Chain
In addition to the three general routing outputs, the LEs within an LAB
have LUT chain and register chain outputs. LUT chain connections allow
LUTs within the same LAB to cascade together for wide input functions.
Register chain outputs allow registers within the same LAB to cascade
together. The register chain output allows an LAB to use LUTs for a single
combinatorial function and the registers to be used for an unrelated shift
register implementation. These resources speed up connections between
LABs while saving local interconnect resources. “MultiTrack
Interconnect” on page 2–12 for more information on LUT chain and
register chain connections.
addnsub Signal
The LE's dynamic adder/subtractor feature saves logic resources by
using one set of LEs to implement both an adder and a subtractor. This
feature is controlled by the LAB-wide control signal addnsub. The
addnsubsignal sets the LAB to perform either A + B or A −B. The LUT
computes addition; subtraction is computed by adding the two's
complement of the intended subtractor. The LAB-wide signal converts to
two's complement by inverting the B bits within the LAB and setting
carry-in = 1 to add one to the least significant bit (LSB). The LSB of an
adder/subtractor must be placed in the first LE of the LAB, where the
LAB-wide addnsubsignal automatically sets the carry-in to 1. The
Quartus II Compiler automatically places and uses the adder/subtractor
feature when using adder/subtractor parameterized functions.
LE Operating Modes
The Cyclone LE can operate in one of the following modes:
■
■
Normal mode
Dynamic arithmetic mode
Each mode uses LE resources differently. In each mode, eight available
inputs to the LE⎯the four data inputs from the LAB local interconnect,
carry-in0and carry-in1from the previous LE, the LAB carry-in
from the previous carry-chain LAB, and the register chain connection⎯are
directed to different destinations to implement the desired logic function.
LAB-wide signals provide clock, asynchronous clear, asynchronous
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Cyclone Device Handbook, Volume 1
preset/load, synchronous clear, synchronous load, and clock enable
control for the register. These LAB-wide signals are available in all LE
modes. The addnsubcontrol signal is allowed in arithmetic mode.
The Quartus II software, in conjunction with parameterized functions
such as library of parameterized modules (LPM) functions, automatically
chooses the appropriate mode for common functions such as counters,
adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which LE operating mode to
use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinatorial functions. In normal mode, four data inputs from the LAB
local interconnect are inputs to a four-input LUT (see Figure 2–6). The
Quartus II Compiler automatically selects the carry-in or the data3
signal as one of the inputs to the LUT. Each LE can use LUT chain
connections to drive its combinatorial output directly to the next LE in the
LAB. Asynchronous load data for the register comes from the data3
input of the LE. LEs in normal mode support packed registers.
Figure 2–6. LE in Normal Mode
sload
sclear
aload
(LAB Wide) (LAB Wide)
(LAB Wide)
Register chain
connection
addnsub (LAB Wide)
ALD/PRE
(1)
Row, column, and
direct link routing
ADATA
D
Q
data1
data2
Row, column, and
direct link routing
ENA
CLRN
data3
cin (from cout
of previous LE)
4-Input
LUT
clock (LAB Wide)
Local routing
data4
ena (LAB Wide)
aclr (LAB Wide)
LUT chain
connection
Register
chain output
Register Feedback
Note to Figure 2–6:
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
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January 2007
Logic Elements
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An LE in dynamic
arithmetic mode uses four 2-input LUTs configurable as a dynamic
adder/subtractor. The first two 2-input LUTs compute two summations
based on a possible carry-in of 1 or 0; the other two LUTs generate carry
outputs for the two chains of the carry select circuitry. As shown in
Figure 2–7, the LAB carry-in signal selects either the carry-in0or
carry-in1chain. The selected chain's logic level in turn determines
which parallel sum is generated as a combinatorial or registered output.
For example, when implementing an adder, the sum output is the
selection of two possible calculated sums:
data1 + data2 + carry-in0
or
data1 + data2 + carry-in1
The other two LUTs use the data1and data2signals to generate two
possible carry-out signals⎯one for a carry of 1 and the other for a carry of
0. The carry-in0signal acts as the carry select for the carry-out0
output and carry-in1acts as the carry select for the carry-out1
output. LEs in arithmetic mode can drive out registered and unregistered
versions of the LUT output.
The dynamic arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, synchronous clear, synchronous load,
and dynamic adder/subtractor options. The LAB local interconnect data
inputs generate the counter enable and synchronous up/down control
signals. The synchronous clear and synchronous load options are LAB-
wide signals that affect all registers in the LAB. The Quartus II software
automatically places any registers that are not used by the counter into
other LABs. The addnsubLAB-wide signal controls whether the LE acts
as an adder or subtractor.
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January 2007
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Cyclone Device Handbook, Volume 1
Figure 2–7. LE in Dynamic Arithmetic Mode
LAB Carry-In
Carry-In0
Carry-In1
sload
sclear
aload
(LAB Wide)
(LAB Wide) (LAB Wide)
Register chain
connection
addnsub
(LAB Wide)
(1)
ALD/PRE
data1
data2
data3
LUT
ADATA
D
Row, column, and
direct link routing
Q
LUT
LUT
LUT
Row, column, and
direct link routing
ENA
CLRN
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
Local routing
LUT chain
connection
Register
chain output
Register Feedback
Carry-Out0 Carry-Out1
Note to Figure 2–7:
(1) The addnsubsignal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in dynamic arithmetic mode. The carry-select chain uses the
redundant carry calculation to increase the speed of carry functions. The
LE is configured to calculate outputs for a possible carry-in of 0 and carry-
in of 1 in parallel. The carry-in0and carry-in1signals from a lower-
order bit feed forward into the higher-order bit via the parallel carry chain
and feed into both the LUT and the next portion of the carry chain. Carry-
select chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel pre-
computation of carry chains. Since the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delays between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the Cyclone architecture
to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
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January 2007
Logic Elements
Figure 2–8 shows the carry-select circuitry in an LAB for a 10-bit full
adder. One portion of the LUT generates the sum of two bits using the
input signals and the appropriate carry-in bit; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for accumulator functions. Another portion of the LUT generates carry-
out bits. An LAB-wide carry-in bit selects which chain is used for the
addition of given inputs. The carry-in signal for each chain, carry-in0
or carry-in1, selects the carry-out to carry forward to the carry-in
signal of the next-higher-order bit. The final carry-out signal is routed to
an LE, where it is fed to local, row, or column interconnects.
Figure 2–8. Carry Select Chain
LAB Carry-In
0
1
LAB Carry-In
Sum1
A1
B1
LE1
LE2
LE3
LE4
LE5
Carry-In0
Carry-In1
Sum2
Sum3
Sum4
Sum5
A2
B2
LUT
LUT
data1
data2
Sum
A3
B3
A4
B4
LUT
LUT
A5
B5
0
1
Carry-Out0
Carry-Out1
Sum6
Sum7
Sum8
Sum9
Sum10
A6
B6
LE6
LE7
LE8
LE9
A7
B7
A8
B8
A9
B9
A10
B10
LE10
LAB Carry-Out
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January 2007
2–11
Preliminary
Cyclone Device Handbook, Volume 1
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 10 LEs by
linking LABs together automatically. For enhanced fitting, a long carry
chain runs vertically allowing fast horizontal connections to M4K
memory blocks. A carry chain can continue as far as a full column.
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOT-
gate push-back technique. Cyclone devices support simultaneous preset/
asynchronous load and clear signals. An asynchronous clear signal takes
precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one preset signal.
In addition to the clear and preset ports, Cyclone devices provide a chip-
wide reset pin (DEV_CLRn) that resets all registers in the device. An
option set before compilation in the Quartus II software controls this pin.
This chip-wide reset overrides all other control signals.
In the Cyclone architecture, connections between LEs, M4K memory
blocks, and device I/O pins are provided by the MultiTrack interconnect
structure with DirectDriveTM technology. The MultiTrack interconnect
consists of continuous, performance-optimized routing lines of different
speeds used for inter- and intra-design block connectivity. The Quartus II
Compiler automatically places critical design paths on faster
interconnects to improve design performance.
MultiTrack
Interconnect
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
within the device. The MultiTrack interconnect and DirectDrive
technology simplify the integration stage of block-based designing by
eliminating the re-optimization cycles that typically follow design
changes and additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and repeatable performance when
2–12
Preliminary
Altera Corporation
January 2007
MultiTrack Interconnect
migrating through different device densities. Dedicated row
interconnects route signals to and from LABs, PLLs, and M4K memory
blocks within the same row. These row resources include:
■
■
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
The direct link interconnect allows an LAB or M4K memory block to
drive into the local interconnect of its left and right neighbors. Only one
side of a PLL block interfaces with direct link and row interconnects. The
direct link interconnect provides fast communication between adjacent
LABs and/or blocks without using row interconnect resources.
The R4 interconnects span four LABs, or two LABs and one M4K RAM
block. These resources are used for fast row connections in a four-LAB
region. Every LAB has its own set of R4 interconnects to drive either left
or right. Figure 2–9 shows R4 interconnect connections from an LAB. R4
interconnects can drive and be driven by M4K memory blocks, PLLs, and
row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive
a given R4 interconnect. For R4 interconnects that drive to the right, the
primary LAB and right neighbor can drive on to the interconnect. For R4
interconnects that drive to the left, the primary LAB and its left neighbor
can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. R4
interconnects can also drive C4 interconnects for connections from one
row to another.
Altera Corporation
January 2007
2–13
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–9. R4 Interconnect Connections
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
R4 Interconnect
Driving Right
C4 Column Interconnects (1)
R4 Interconnect
Driving Left
LAB
Neighbor
Primary
LAB (2)
LAB
Neighbor
Notes to Figure 2–9:
(1) C4 interconnects can drive R4 interconnects.
(2) This pattern is repeated for every LAB in the LAB row.
The column interconnect operates similarly to the row interconnect. Each
column of LABs is served by a dedicated column interconnect, which
vertically routes signals to and from LABs, M4K memory blocks, and row
and column IOEs. These column resources include:
■
■
■
LUT chain interconnects within an LAB
Register chain interconnects within an LAB
C4 interconnects traversing a distance of four blocks in an up and
down direction
Cyclone devices include an enhanced interconnect structure within LABs
for routing LE output to LE input connections faster using LUT chain
connections and register chain connections. The LUT chain connection
allows the combinatorial output of an LE to directly drive the fast input
of the LE right below it, bypassing the local interconnect. These resources
can be used as a high-speed connection for wide fan-in functions from LE
1 to LE 10 in the same LAB. The register chain connection allows the
register output of one LE to connect directly to the register input of the
next LE in the LAB for fast shift registers. The Quartus II Compiler
automatically takes advantage of these resources to improve utilization
and performance. Figure 2–10 shows the LUT chain and register chain
interconnects.
2–14
Preliminary
Altera Corporation
January 2007
MultiTrack Interconnect
Figure 2–10. LUT Chain & Register Chain Interconnects
Local Interconnect
Routing Among LEs
in the LAB
LE 1
LUT Chain
Routing to
Adjacent LE
Register Chain
Routing to Adjacent
LE's Register Input
LE 2
LE 3
LE 4
LE 5
LE 6
LE 7
LE 8
LE 9
Local
Interconnect
LE 10
The C4 interconnects span four LABs or M4K blocks up or down from a
source LAB. Every LAB has its own set of C4 interconnects to drive either
up or down. Figure 2–11 shows the C4 interconnect connections from an
LAB in a column. The C4 interconnects can drive and be driven by all
types of architecture blocks, including PLLs, M4K memory blocks, and
column and row IOEs. For LAB interconnection, a primary LAB or its
LAB neighbor can drive a given C4 interconnect. C4 interconnects can
drive each other to extend their range as well as drive row interconnects
for column-to-column connections.
Altera Corporation
January 2007
2–15
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–11. C4 Interconnect Connections
Note (1)
C4 Interconnect
Drives Local and R4
Interconnects
Up to Four Rows
C4 Interconnect
Driving Up
LAB
Row
Interconnect
Adjacent LAB can
drive onto neighboring
LAB's C4 interconnect
Local
Interconnect
C4 Interconnect
Driving Down
Note to Figure 2–11:
(1) Each C4 interconnect can drive either up or down four rows.
2–16
Preliminary
Altera Corporation
January 2007
MultiTrack Interconnect
All embedded blocks communicate with the logic array similar to LAB-
to-LAB interfaces. Each block (i.e., M4K memory or PLL) connects to row
and column interconnects and has local interconnect regions driven by
row and column interconnects. These blocks also have direct link
interconnects for fast connections to and from a neighboring LAB.
Table 2–2 shows the Cyclone device's routing scheme.
Table 2–2. Cyclone Device Routing Scheme
Destination
Source
LUT Chain
v
v
v
Register Chain
Local Interconnect
v
v
v
v
Direct Link
Interconnect
v
R4 Interconnect
C4 Interconnect
LE
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
M4K RAM Block
PLL
Column IOE
Row IOE
v
v
Altera Corporation
January 2007
2–17
Preliminary
Cyclone Device Handbook, Volume 1
The Cyclone embedded memory consists of columns of M4K memory
Embedded
Memory
blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while
EP1C12 and EP1C20 devices have two columns (see Table 1–1 on
page 1–2 for total RAM bits per density). Each M4K block can implement
various types of memory with or without parity, including true dual-port,
simple dual-port, and single-port RAM, ROM, and FIFO buffers. The
M4K blocks support the following features:
■
■
■
■
■
■
■
■
■
■
■
4,608 RAM bits
250 MHz performance
True dual-port memory
Simple dual-port memory
Single-port memory
Byte enable
Parity bits
Shift register
FIFO buffer
ROM
Mixed clock mode
1
Violating the setup or hold time on the address registers could corrupt the
memory contents. This applies to both read and write operations.
Memory Modes
The M4K memory blocks include input registers that synchronize writes
and output registers to pipeline designs and improve system
performance. M4K blocks offer a true dual-port mode to support any
combination of two-port operations: two reads, two writes, or one read
and one write at two different clock frequencies. Figure 2–12 shows true
dual-port memory.
Figure 2–12. True Dual-Port Memory Configuration
A
B
dataA[]
dataB[]
addressA[]
wrenA
addressB[]
wrenB
clockA
clockenA
qA[]
clockB
clockenB
qB[]
aclrA
aclrB
2–18
Preliminary
Altera Corporation
January 2007
Embedded Memory
In addition to true dual-port memory, the M4K memory blocks support
simple dual-port and single-port RAM. Simple dual-port memory
supports a simultaneous read and write. Single-port memory supports
non-simultaneous reads and writes. Figure 2–13 shows these different
M4K RAM memory port configurations.
Figure 2–13. Simple Dual-Port & Single-Port Memory Configurations
Simple Dual-Port Memory
data[]
rdaddress[]
rden
wraddress[]
wren
q[]
inclock
inclocken
inaclr
outclock
outclocken
outaclr
Single-Port Memory (1)
data[]
address[]
wren
q[]
outclock
inclock
inclocken
inaclr
outclocken
outaclr
Note to Figure 2–13:
(1) Two single-port memory blocks can be implemented in a single M4K block as long
as each of the two independent block sizes is equal to or less than half of the M4K
block size.
The memory blocks also enable mixed-width data ports for reading and
writing to the RAM ports in dual-port RAM configuration. For example,
the memory block can be written in ×1 mode at port A and read out in ×16
mode from port B.
The Cyclone memory architecture can implement fully synchronous
RAM by registering both the input and output signals to the M4K RAM
block. All M4K memory block inputs are registered, providing
synchronous write cycles. In synchronous operation, the memory block
generates its own self-timed strobe write enable (wren) signal derived
from a global clock. In contrast, a circuit using asynchronous RAM must
generate the RAM wrensignal while ensuring its data and address
signals meet setup and hold time specifications relative to the wren
Altera Corporation
January 2007
2–19
Preliminary
Cyclone Device Handbook, Volume 1
signal. The output registers can be bypassed. Pseudo-asynchronous
reading is possible in the simple dual-port mode of M4K blocks by
clocking the read enable and read address registers on the negative clock
edge and bypassing the output registers.
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
Two single-port memory blocks can be implemented in a single M4K
block as long as each of the two independent block sizes is equal to or less
than half of the M4K block size.
The Quartus II software automatically implements larger memory by
combining multiple M4K memory blocks. For example, two 256×16-bit
RAM blocks can be combined to form a 256×32-bit RAM block. Memory
performance does not degrade for memory blocks using the maximum
number of words allowed. Logical memory blocks using less than the
maximum number of words use physical blocks in parallel, eliminating
any external control logic that would increase delays. To create a larger
high-speed memory block, the Quartus II software automatically
combines memory blocks with LE control logic.
Parity Bit Support
The M4K blocks support a parity bit for each byte. The parity bit, along
with internal LE logic, can implement parity checking for error detection
to ensure data integrity. You can also use parity-size data words to store
user-specified control bits. Byte enables are also available for data input
masking during write operations.
Shift Register Support
You can configure M4K memory blocks to implement shift registers for
DSP applications such as pseudo-random number generators, multi-
channel filtering, auto-correlation, and cross-correlation functions. These
and other DSP applications require local data storage, traditionally
implemented with standard flip-flops, which can quickly consume many
logic cells and routing resources for large shift registers. A more efficient
alternative is to use embedded memory as a shift register block, which
saves logic cell and routing resources and provides a more efficient
implementation with the dedicated circuitry.
The size of a w × m × n shift register is determined by the input data width
(w), the length of the taps (m), and the number of taps (n). The size of a
w × m × n shift register must be less than or equal to the maximum number
of memory bits in the M4K block (4,608 bits). The total number of shift
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Preliminary
Altera Corporation
January 2007
Embedded Memory
register outputs (number of taps n × width w) must be less than the
maximum data width of the M4K RAM block (×36). To create larger shift
registers, multiple memory blocks are cascaded together.
Data is written into each address location at the falling edge of the clock
and read from the address at the rising edge of the clock. The shift register
mode logic automatically controls the positive and negative edge
clocking to shift the data in one clock cycle. Figure 2–14 shows the M4K
memory block in the shift register mode.
Figure 2–14. Shift Register Memory Configuration
w × m × n Shift Register
m-Bit Shift Register
w
w
w
m-Bit Shift Register
w
n Number
of Taps
m-Bit Shift Register
w
w
w
m-Bit Shift Register
w
Memory Configuration Sizes
The memory address depths and output widths can be configured as
4,096 × 1, 2,048 × 2, 1,024 × 4, 512 × 8 (or 512 × 9 bits), 256 × 16 (or 256 × 18
bits), and 128 × 32 (or 128 × 36 bits). The 128 × 32- or 36-bit configuration
Altera Corporation
January 2007
2–21
Preliminary
Cyclone Device Handbook, Volume 1
is not available in the true dual-port mode. Mixed-width configurations
are also possible, allowing different read and write widths. Tables 2–3
and 2–4 summarize the possible M4K RAM block configurations.
Table 2–3. M4K RAM Block Configurations (Simple Dual-Port)
Write Port
Read Port
4K × 1
4K × 1 2K × 2 1K × 4 512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
2K × 2
1K × 4
512 × 8
256 × 16
128 × 32
512 × 9
256 × 18
128 × 36
v
v
v
v
v
v
v
v
v
Table 2–4. M4K RAM Block Configurations (True Dual-Port)
Port B
Port A
4K × 1
v
2K × 2
v
1K × 4
v
512 × 8
v
256 × 16
v
512 × 9
256 × 18
4K × 1
2K × 2
v
v
v
v
v
1K × 4
v
v
v
v
v
512 × 8
256 × 16
512 × 9
256 × 18
v
v
v
v
v
v
v
v
v
v
v
v
v
v
When the M4K RAM block is configured as a shift register block, you can
create a shift register up to 4,608 bits (w × m × n).
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Altera Corporation
January 2007
Embedded Memory
Byte Enables
M4K blocks support byte writes when the write port has a data width of
16, 18, 32, or 36 bits. The byte enables allow the input data to be masked
so the device can write to specific bytes. The unwritten bytes retain the
previous written value. Table 2–5 summarizes the byte selection.
Table 2–5. Byte Enable for M4K Blocks
Notes (1), (2)
byteena[3..0]
datain × 18
datain × 36
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[8..0]
[8..0]
[17..9]
[17..9]
–
–
[26..18]
[35..27]
Notes to Table 2–5:
(1) Any combination of byte enables is possible.
(2) Byte enables can be used in the same manner with 8-bit words, i.e., in × 16 and
× 32 modes.
Control Signals & M4K Interface
The M4K blocks allow for different clocks on their inputs and outputs.
Either of the two clocks feeding the block can clock M4K block registers
(renwe, address, byte enable, datain, and output registers). Only the
output register can be bypassed. The six labclksignals or local
interconnects can drive the control signals for the A and B ports of the
M4K block. LEs can also control the clock_a, clock_b, renwe_a,
renwe_b, clr_a, clr_b, clocken_a, and clocken_bsignals, as
shown in Figure 2–15.
The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K block local interconnect. The M4K blocks can communicate with
LABs on either the left or right side through these row resources or with
LAB columns on either the right or left with the column resources. Up to
10 direct link input connections to the M4K block are possible from the
left adjacent LABs and another 10 possible from the right adjacent LAB.
M4K block outputs can also connect to left and right LABs through 10
direct link interconnects each. Figure 2–16 shows the M4K block to logic
array interface.
Altera Corporation
January 2007
2–23
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–15. M4K RAM Block Control Signals
Dedicated
6
LAB Row
Clocks
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
Local
Local
Interconnect
Interconnect
alcr_a
clocken_a
renwe_b
clock_b
Local
Local
Interconnect
Interconnect
clock_a
renwe_a
alcr_b
clocken_b
Figure 2–16. M4K RAM Block LAB Row Interface
C4 Interconnects
R4 Interconnects
10
Direct link
Direct link
interconnect
to adjacent LAB
interconnect
to adjacent LAB
dataout
M4K RAM
Block
Direct link
Direct link
interconnect
interconnect
from adjacent LAB
from adjacent LAB
Byte enable
Clocks
Control
Signals
address
datain
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
2–24
Preliminary
Altera Corporation
January 2007
Embedded Memory
Independent Clock Mode
The M4K memory blocks implement independent clock mode for true
dual-port memory. In this mode, a separate clock is available for each port
(ports A and B). Clock A controls all registers on the port A side, while
clock B controls all registers on the port B side. Each port, A and B, also
supports independent clock enables and asynchronous clear signals for
port A and B registers. Figure 2–17 shows an M4K memory block in
independent clock mode.
Figure 2–17. Independent Clock Mode
Notes (1), (2)
6 LAB Row Clocks
Memory Block
256 ´ 16 (2)
512 ´ 8
1,024 ´ 4
2,048 ´ 2
A
B
6
6
dataA[ ]
dataB[ ]
Data In
Q
Q
D
D
Q
Q
Data In
ENA
ENA
4,096 ´ 1
byteenaA[ ]
byteenaB[ ]
Byte Enable A
D
D
Byte Enable B
ENA
ENA
addressA[ ]
addressB[ ]
Address A
Address B
Q
Q
D
D
Q
Q
ENA
ENA
wrenA
wrenB
Write/Read
Enable
Write/Read
Enable
D
D
Write
Pulse
Generator
Write
Pulse
Generator
clkenA
clockA
clkenB
clockB
ENA
ENA
Data Out
Data Out
D
Q
Q
D
ENA
ENA
qA[ ] qB[ ]
Notes to Figure 2–17:
(1) All registers shown have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and
simple dual-port memory modes. On each of the two ports, A or B, one
clock controls all registers for inputs into the memory block: data input,
wren, and address. The other clock controls the block's data output
registers. Each memory block port, A or B, also supports independent
clock enables and asynchronous clear signals for input and output
registers. Figures 2–18 and 2–19 show the memory block in input/output
clock mode.
Altera Corporation
January 2007
2–25
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–18. Input/Output Clock Mode in True Dual-Port Mode
Note (1), (2)
6 LAB Row Clocks
6
6
Memory Block
256 × 16 (2)
512 × 8
A
B
dataA[ ]
dataB[ ]
Data In
Q
Q
Q
D
D
Q
Q
Q
Data In
ENA
ENA
1,024 × 4
2,048 × 2
4,096 × 1
byteenaA[ ]
byteenaB[ ]
Byte Enable A
D
D
Byte Enable B
ENA
ENA
addressA[ ]
addressB[ ]
Address A
Address B
D
D
ENA
ENA
wrenA
wrenB
Write/Read
Enable
Write/Read
Enable
Write
Pulse
Generator
Write
Pulse
Generator
Q
D
D
Q
clkenA
clockA
ENA
ENA
Data Out
Data Out
clkenB
clockB
D
Q
Q
D
ENA
ENA
qA[ ] qB[ ]
Notes to Figure 2–18:
(1) All registers shown have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
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Preliminary
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January 2007
Embedded Memory
Figure 2–19. Input/Output Clock Mode in Simple Dual-Port Mode
Notes (1), (2)
6 LAB Row
Clocks
Memory Block
6
256 ´ 16
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
data[ ]
address[ ]
byteena[ ]
D
ENA
Q
Q
Q
Data In
Read Address
D
ENA
To MultiTrack
Interconnect
Data Out
D
Q
ENA
Byte Enable
D
ENA
wraddress[ ]
Write Address
D
ENA
Q
Q
rden
Read Enable
D
ENA
wren
outclken
Write
Pulse
Generator
D
ENA
Q
Write Enable
inclken
inclock
outclock
Notes to Figure 2–19:
(1) All registers shown except the rden register have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
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January 2007
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Preliminary
Cyclone Device Handbook, Volume 1
Read/Write Clock Mode
The M4K memory blocks implement read/write clock mode for simple
dual-port memory. You can use up to two clocks in this mode. The write
clock controls the block's data inputs, wraddress, and wren. The read
clock controls the data output, rdaddress, and rden. The memory
blocks support independent clock enables for each clock and
asynchronous clear signals for the read- and write-side registers.
Figure 2–20 shows a memory block in read/write clock mode.
Figure 2–20. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2)
6 LAB Row
Clocks
Memory Block
256 × 16
512 × 8
6
1,024 × 4
data[ ]
D
ENA
Q
Data In
2,048 × 2
4,096 × 1
To MultiTrack
Interconnect
Data Out
D
Q
ENA
address[ ]
Read Address
D
Q
Q
Q
ENA
wraddress[ ]
Write Address
Byte Enable
Read Enable
D
ENA
byteena[ ]
D
ENA
rden
D
Q
ENA
wren
rdclken
Write
Pulse
Generator
D
ENA
Q
wrclken
wrclock
Write Enable
rdclock
Notes to Figure 2–20:
(1) All registers shown except the rden register have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
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January 2007
Global Clock Network & Phase-Locked Loops
Single-Port Mode
The M4K memory blocks also support single-port mode, used when
simultaneous reads and writes are not required. See Figure 2–21. A single
M4K memory block can support up to two single-port mode RAM blocks
if each RAM block is less than or equal to 2K bits in size.
Figure 2–21. Single-Port Mode
Note (1)
6 LAB Row
Clocks
RAM/ROM
6
256 × 16
512 × 8
1,024 × 4
data[ ]
D
ENA
Q
Data In
2,048 × 2
4,096 × 1
To MultiTrack
Interconnect
Data Out
D
Q
ENA
address[ ]
Address
D
Q
ENA
wren
Write Enable
outclken
D
ENA
Q
inclken
inclock
Write
Pulse
Generator
outclock
Note to Figure 2–21:
(1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
Cyclone devices provide a global clock network and up to two PLLs for a
complete clock management solution.
Global Clock
Network &
Phase-Locked
Loops
Global Clock Network
There are four dedicated clock pins (CLK[3..0], two pins on the left side
and two pins on the right side) that drive the global clock network, as
shown in Figure 2–22. PLL outputs, logic array, and dual-purpose clock
(DPCLK[7..0]) pins can also drive the global clock network.
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January 2007
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Preliminary
Cyclone Device Handbook, Volume 1
The eight global clock lines in the global clock network drive throughout
the entire device. The global clock network can provide clocks for all
resources within the device ⎯IOEs, LEs, and memory blocks. The global
clock lines can also be used for control signals, such as clock enables and
synchronous or asynchronous clears fed from the external pin, or DQS
signals for DDR SDRAM or FCRAM interfaces. Internal logic can also
drive the global clock network for internally generated global clocks and
asynchronous clears, clock enables, or other control signals with large
fanout. Figure 2–22 shows the various sources that drive the global clock
network.
Figure 2–22. Global Clock Generation
Note (1)
DPCLK2
DPCLK3
Cyclone Device
Global Clock
Network
8
DPCLK1
DPCLK4
From logic
array
From logic
array
4
4
CLK0
CLK2
PLL2
(2)
PLL1
2
CLK1 (3)
CLK3 (3)
4
4
2
DPCLK0
DPCLK5
DPCLK7
DPCLK6
Notes to Figure 2–22:
(1) The EP1C3 device in the 100-pin TQFP package has five DPCLKpins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and
DPCLK7).
(2) EP1C3 devices only contain one PLL (PLL 1).
(3) The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins CLK1and CLK3.
2–30
Preliminary
Altera Corporation
January 2007
Global Clock Network & Phase-Locked Loops
Dual-Purpose Clock Pins
Each Cyclone device except the EP1C3 device has eight dual-purpose
clock pins, DPCLK[7..0](two on each I/O bank). EP1C3 devices have
five DPCLKpins in the 100-pin TQFP package. These dual-purpose pins
can connect to the global clock network (see Figure 2–22) for high-fanout
control signals such as clocks, asynchronous clears, presets, and clock
enables, or protocol control signals such as TRDYand IRDYfor PCI, or
DQS signals for external memory interfaces.
Combined Resources
Each Cyclone device contains eight distinct dedicated clocking resources.
The device uses multiplexers with these clocks to form six-bit buses to
drive LAB row clocks, column IOE clocks, or row IOE clocks. See
Figure 2–23. Another multiplexer at the LAB level selects two of the six
LAB row clocks to feed the LE registers within the LAB.
Figure 2–23. Global Clock Network Multiplexers
Column I/O Region
IO_CLK]5..0]
Global Clock
Network
Global Clocks [3..0]
Dual-Purpose Clocks [7..0]
Clock [7..0]
LAB Row Clock [5..0]
PLL Outputs [3..0]
Core Logic [7..0]
Row I/O Region
IO_CLK[5..0]
IOE clocks have row and column block regions. Six of the eight global
clock resources feed to these row and column regions. Figure 2–24 shows
the I/O clock regions.
Altera Corporation
January 2007
2–31
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–24. I/O Clock Regions
Column I/O Clock Region
IO_CLK[5..0]
6
I/O Clock Regions
Cyclone Logic Array
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
6
6
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
Global Clock
Network
8
Row
I/O Regions
LAB Row Clocks
labclk[5..0]
LAB Row Clocks
labclk[5..0]
6
6
I/O Clock Regions
6
Column I/O Clock Region
IO_CLK[5..0]
PLLs
Cyclone PLLs provide general-purpose clocking with clock
multiplication and phase shifting as well as outputs for differential I/O
support. Cyclone devices contain two PLLs, except for the EP1C3 device,
which contains one PLL.
2–32
Preliminary
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January 2007
Global Clock Network & Phase-Locked Loops
Table 2–6 shows the PLL features in Cyclone devices. Figure 2–25 shows
a Cyclone PLL.
Table 2–6. Cyclone PLL Features
Feature
PLL Support
Clock multiplication and division
Phase shift
m/(n × post-scale counter) (1)
Down to 125-ps increments (2), (3)
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Yes
2
One differential or one single-ended (4)
Notes to Table 2–6:
(1) The m counter ranges from 2 to 32. The n counter and the post-scale counters
range from 1 to 32.
(2) The smallest phase shift is determined by the voltage-controlled oscillator (VCO)
period divided by 8.
(3) For degree increments, Cyclone devices can shift all output frequencies in
increments of 45°. Smaller degree increments are possible depending on the
frequency and divide parameters.
(4) The EP1C3 device in the 100-pin TQFP package does not support external clock
output. The EP1C6 device in the 144-pin TQFP package does not support external
clock output from PLL2.
Figure 2–25. Cyclone PLL
Note (1)
VCO Phase Selection
Selectable at Each PLL
Output Port
Post-Scale
Counters
Global clock
÷g0
CLK0 or
LVDSCLK1p (2)
Charge
Pump
Loop
Filter
÷n
Δt
÷g1
÷e
PFD (3)
VCO
Global clock
I/O buffer
CLK1 or
LVDSCLK1n (2)
Δt
÷m
Notes to Figure 2–25:
(1) The EP1C3 device in the 100-pin TQFP package does not support external outputs or LVDS inputs. The EP1C6
device in the 144-pin TQFP package does not support external output from PLL2.
(2) LVDS input is supported via the secondary function of the dedicated clock pins. For PLL 1, the CLK0pin’s secondary
function is LVDSCLK1pand the CLK1pin’s secondary function is LVDSCLK1n. For PLL 2, the CLK2pin’s secondary
function is LVDSCLK2pand the CLK3pin’s secondary function is LVDSCLK2n.
(3) PFD: phase frequency detector.
Altera Corporation
January 2007
2–33
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–26 shows the PLL global clock connections.
Figure 2–26. Cyclone PLL Global Clock Connections
G1
G3
G5
G7
G0
G2
G4
G6
g0
g1
e
g0
g1
e
CLK0
CLK2
PLL1
PLL2
CLK1 (1)
CLK3 (2)
PLL1_OUT (3), (4)
PLL2_OUT (3), (4)
Notes to Figure 2–26:
(1) PLL 1 supports one single-ended or LVDS input via pins CLK0and CLK1.
(2) PLL2 supports one single-ended or LVDS input via pins CLK2and CLK3.
(3) PLL1_OUTand PLL2_OUTsupport single-ended or LVDS output. If external output is not required, these pins are
available as regular user I/O pins.
(4) The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the
144-pin TQFP package does not support external clock output from PLL2.
Table 2–7 shows the global clock network sources available in Cyclone
devices.
Table 2–7. Global Clock Network Sources (Part 1 of 2)
Source
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7
PLL Counter
Output
PLL1 G0
PLL1 G1
PLL2 G0 (1)
PLL2 G1 (1)
CLK0
v
v
v
v
v
v
v
v
v
v
v
v
v
Dedicated
Clock Input
Pins
v
CLK1 (2)
CLK2
v
v
CLK3 (2)
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Preliminary
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January 2007
Global Clock Network & Phase-Locked Loops
Table 2–7. Global Clock Network Sources (Part 2 of 2)
Source
GCLK0 GCLK1 GCLK2 GCLK3 GCLK4 GCLK5 GCLK6 GCLK7
Dual-Purpose DPCLK0 (3)
v
Clock Pins
DPCLK1 (3)
v
DPCLK2
DPCLK3
DPCLK4
DPCLK5 (3)
DPCLK6
DPCLK7
v
v
v
v
v
v
Notes to Table 2–7:
(1) EP1C3 devices only have one PLL (PLL 1).
(2) EP1C3 devices in the 100-pin TQFP package do not have dedicated clock pins CLK1and CLK3.
(3) EP1C3 devices in the 100-pin TQFP package do not have the DPCLK0, DPCLK1, or DPCLK5pins.
Clock Multiplication & Division
Cyclone PLLs provide clock synthesis for PLL output ports using
m/(n × post scale counter) scaling factors. The input clock is divided by
a pre-scale divider, n, and is then multiplied by the m feedback factor. The
control loop drives the VCO to match fIN × (m/n). Each output port has
a unique post-scale counter to divide down the high-frequency VCO. For
multiple PLL outputs with different frequencies, the VCO is set to the
least-common multiple of the output frequencies that meets its frequency
specifications. Then, the post-scale dividers scale down the output
frequency for each output port. For example, if the output frequencies
required from one PLL are 33 and 66 MHz, the VCO is set to 330 MHz (the
least-common multiple in the VCO's range).
Each PLL has one pre-scale divider, n, that can range in value from 1 to
32. Each PLL also has one multiply divider, m, that can range in value
from 2 to 32. Global clock outputs have two post scale G dividers for
global clock outputs, and external clock outputs have an E divider for
external clock output, both ranging from 1 to 32. The Quartus II software
automatically chooses the appropriate scaling factors according to the
input frequency, multiplication, and division values entered.
Altera Corporation
January 2007
2–35
Preliminary
Cyclone Device Handbook, Volume 1
External Clock Inputs
Each PLL supports single-ended or differential inputs for source-
synchronous receivers or for general-purpose use. The dedicated clock
pins (CLK[3..0]) feed the PLL inputs. These dual-purpose pins can also
act as LVDS input pins. See Figure 2–25.
Table 2–8 shows the I/O standards supported by PLL input and output
pins.
Table 2–8. PLL I/O Standards
I/O Standard
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
CLK Input
v
EXTCLK Output
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
LVDS
v
SSTL-2 class I
v
SSTL-2 class II
SSTL-3 class I
v
v
SSTL-3 class II
Differential SSTL-2
v
For more information on LVDS I/O support, see “LVDS I/O Pins” on
page 2–54.
External Clock Outputs
Each PLL supports one differential or one single-ended output for source-
synchronous transmitters or for general-purpose external clocks. If the
PLL does not use these PLL_OUTpins, the pins are available for use as
general-purpose I/O pins. The PLL_OUTpins support all I/O standards
shown in Table 2–8.
The external clock outputs do not have their own VCC and ground voltage
supplies. Therefore, to minimize jitter, do not place switching I/O pins
next to these output pins. The EP1C3 device in the 100-pin TQFP package
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January 2007
Global Clock Network & Phase-Locked Loops
does not have dedicated clock output pins. The EP1C6 device in the
144-pin TQFP package only supports dedicated clock outputs from
PLL 1.
Clock Feedback
Cyclone PLLs have three modes for multiplication and/or phase shifting:
■
■
Zero delay buffer mode⎯The external clock output pin is phase-
aligned with the clock input pin for zero delay.
Normal mode⎯If the design uses an internal PLL clock output, the
normal mode compensates for the internal clock delay from the input
clock pin to the IOE registers. The external clock output pin is phase
shifted with respect to the clock input pin if connected in this mode.
You defines which internal clock output from the PLL should be
phase-aligned to compensate for internal clock delay.
■
No compensation mode⎯In this mode, the PLL will not compensate
for any clock networks.
Phase Shifting
Cyclone PLLs have an advanced clock shift capability that enables
programmable phase shifts. You can enter a phase shift (in degrees or
time units) for each PLL clock output port or for all outputs together in
one shift. You can perform phase shifting in time units with a resolution
range of 125 to 250 ps. The finest resolution equals one eighth of the VCO
period. The VCO period is a function of the frequency input and the
multiplication and division factors. Each clock output counter can choose
a different phase of the VCO period from up to eight taps. You can use this
clock output counter along with an initial setting on the post-scale
counter to achieve a phase-shift range for the entire period of the output
clock. The phase tap feedback to the m counter can shift all outputs to a
single phase. The Quartus II software automatically sets the phase taps
and counter settings according to the phase shift entered.
Lock Detect Signal
The lock output indicates that there is a stable clock output signal in
phase with the reference clock. Without any additional circuitry, the lock
signal may toggle as the PLL begins tracking the reference clock.
Therefore, you may need to gate the lock signal for use as a system-
control signal. For correct operation of the lock circuit below
–20 C, fIN/N > 200 MHz.
Altera Corporation
January 2007
2–37
Preliminary
Cyclone Device Handbook, Volume 1
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with
a variable duty cycle. This feature is supported on each PLL post-scale
counter (g0, g1, e). The duty cycle setting is achieved by a low- and high-
time count setting for the post-scale dividers. The Quartus II software
uses the frequency input and the required multiply or divide rate to
determine the duty cycle choices.
Control Signals
There are three control signals for clearing and enabling PLLs and their
outputs. You can use these signals to control PLL resynchronization and
the ability to gate PLL output clocks for low-power applications.
The pllenablesignal enables and disables PLLs. When the pllenable
signal is low, the clock output ports are driven by ground and all the PLLs
go out of lock. When the pllenablesignal goes high again, the PLLs
relock and resynchronize to the input clocks. An input pin or LE output
can drive the pllenablesignal.
The aresetsignals are reset/resynchronization inputs for each PLL.
Cyclone devices can drive these input signals from input pins or from
LEs. When aresetis driven high, the PLL counters will reset, clearing
the PLL output and placing the PLL out of lock. When driven low again,
the PLL will resynchronize to its input as it relocks.
The pfdenasignals control the phase frequency detector (PFD) output
with a programmable gate. If you disable the PFD, the VCO will operate
at its last set value of control voltage and frequency with some drift, and
the system will continue running when the PLL goes out of lock or the
input clock disables. By maintaining the last locked frequency, the system
has time to store its current settings before shutting down. You can either
use their own control signal or gated locked status signals to trigger the
pfdenasignal.
f
For more information on Cyclone PLLs, see Chapter 6, Using PLLs in
Cyclone Devices.
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Preliminary
Altera Corporation
January 2007
I/O Structure
IOEs support many features, including:
I/O Structure
■
■
■
■
■
■
■
■
■
■
■
■
Differential and single-ended I/O standards
3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Output drive strength control
Weak pull-up resistors during configuration
Slew-rate control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors in user mode
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Cyclone device IOEs contain a bidirectional I/O buffer and three registers
for complete embedded bidirectional single data rate transfer.
Figure 2–27 shows the Cyclone IOE structure. The IOE contains one input
register, one output register, and one output enable register. You can use
the input registers for fast setup times and output registers for fast clock-
to-output times. Additionally, you can use the output enable (OE) register
for fast clock-to-output enable timing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins. IOEs can be used as input, output, or
bidirectional pins.
Altera Corporation
January 2007
2–39
Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–27. Cyclone IOE Structure
Logic Array
OE Register
OE
D
Q
Output Register
Output
D
Q
Combinatorial
input (1)
Input
Input Register
D
Q
Note to Figure 2–27:
(1) There are two paths available for combinatorial inputs to the logic array. Each path
contains a unique programmable delay chain.
The IOEs are located in I/O blocks around the periphery of the Cyclone
device. There are up to three IOEs per row I/O block and up to three IOEs
per column I/O block (column I/O blocks span two columns). The row
I/O blocks drive row, column, or direct link interconnects. The column
I/O blocks drive column interconnects. Figure 2–28 shows how a row
I/O block connects to the logic array. Figure 2–29 shows how a column
I/O block connects to the logic array.
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Preliminary
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January 2007
I/O Structure
Figure 2–28. Row I/O Block Connection to the Interconnect
R4 Interconnects
C4 Interconnects
I/O Block Local
Interconnect
21 Data and
Control Signals
from Logic Array (1)
21
LAB
Row
I/O Block
io_datain[2..0] and
comb_io_datain[2..0] (2)
Direct Link
Interconnect
from Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
Row I/O Block
Contains up to
Three IOEs
io_clk[5:0]
LAB Local
Interconnect
Notes to Figure 2–28:
(1) The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
(2) Each of the three IOEs in the row I/O block can have one io_dataininput (combinatorial or registered) and one
comb_io_datain(combinatorial) input.
Altera Corporation
January 2007
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Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–29. Column I/O Block Connection to the Interconnect
Column I/O
Block Contains
up to Three IOEs
Column I/O Block
21 Data &
Control Signals
from Logic Array (1)
IO_datain[2:0] &
comb_io_datain[2..0]
(2)
21
io_clk[5..0]
I/O Block
Local Interconnect
R4 Interconnects
LAB
LAB
LAB
LAB Local
C4 Interconnects
Interconnect
Notes to Figure 2–29:
(1) The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
(2) Each of the three IOEs in the column I/O block can have one io_dataininput (combinatorial or registered) and
one comb_io_datain(combinatorial) input.
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Preliminary
Altera Corporation
January 2007
I/O Structure
The pin's datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks, io_clk[5..0], provide a dedicated routing
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see
“Global Clock Network & Phase-Locked Loops” on page 2–29).
Figure 2–30 illustrates the signal paths through the I/O block.
Figure 2–30. Signal Path through the I/O Block
Row or Column
io_clk[5..0]
To Other
IOEs
io_datain
To Logic
Array
comb_io_datain
oe
ce_in
io_csclr
io_coe
ce_out
aclr/preset
sclr
Data and
Control
Signal
IOE
io_cce_in
io_cce_out
Selection
From Logic
Array
clk_in
io_caclr
io_cclk
clk_out
dataout
io_dataout
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out. Figure 2–31 illustrates the control signal
selection.
Altera Corporation
January 2007
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Preliminary
Cyclone Device Handbook, Volume 1
Figure 2–31. Control Signal Selection per IOE
Dedicated I/O
Clock [5..0]
io_coe
Local
Interconnect
io_csclr
Local
Interconnect
io_caclr
Local
Interconnect
io_cce_out
Local
Interconnect
io_cce_in
io_cclk
Local
Interconnect
ce_out
clk_out
sclr/preset
clk_in
ce_in
aclr/preset
oe
Local
Interconnect
In normal bidirectional operation, you can use the input register for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register is available for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, or the column and row interconnects.
Figure 2–32 shows the IOE in bidirectional configuration.
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Preliminary
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January 2007
I/O Structure
Figure 2–32. Cyclone IOE in Bidirectional I/O Configuration
ioe_clk[5..0]
Column or Row
Interconect
OE
OE Register
PRN
D
Q
V
CCIO
clkout
ENA
Optional
PCI Clamp
CLRN
ce_out
V
CCIO
Programmable
Pull-Up
aclr/prn
Resistor
Chip-Wide Reset
Output Register
Output
Pin Delay
PRN
D
Q
ENA
Drive Strength Control
Open-Drain Output
Slew Control
sclr/preset
CLRN
comb_datain
Input Pin to
Logic Array Delay
data_in
Bus Hold
Input Pin to
Input Register Delay
or Input Pin to
Input Register
PRN
Logic Array Delay
D
Q
ENA
clkin
CLRN
ce_in
The Cyclone device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinatorial logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
Altera Corporation
January 2007
2–45
Preliminary
Cyclone Device Handbook, Volume 1
to automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
registers. Table 2–9 shows the programmable delays for Cyclone devices.
Table 2–9. Cyclone Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Decrease input delay to internal cells
Decrease input delay to input registers
Increase delay to output pin
There are two paths in the IOE for a combinatorial input to reach the logic
array. Each of the two paths can have a different delay. This allows you
adjust delays from the pin to internal LE registers that reside in two
different areas of the device. The designer sets the two combinatorial
input delays by selecting different delays for two different paths under
the Decrease input delay to internal cells logic option in the Quartus II
software. When the input signal requires two different delays for the
combinatorial input, the input register in the IOE is no longer available.
The IOE registers in Cyclone devices share the same source for clear or
preset. The designer can program preset or clear for each individual IOE.
The designer can also program the registers to power up high or low after
configuration is complete. If programmed to power up low, an
asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature
prevents the inadvertent activation of another device's active-low input
upon power up. If one register in an IOE uses a preset or clear signal then
all registers in the IOE must use that same signal if they require preset or
clear. Additionally a synchronous reset signal is available to the designer
for the IOE registers.
External RAM Interfacing
Cyclone devices support DDR SDRAM and FCRAM interfaces at up to
133 MHz through dedicated circuitry.
DDR SDRAM & FCRAM
Cyclone devices have dedicated circuitry for interfacing with DDR
SDRAM. All I/O banks support DDR SDRAM and FCRAM I/O pins.
However, the configuration input pins in bank 1 must operate at 2.5 V
because the SSTL-2 VCCIO level is 2.5 V. Additionally, the configuration
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Preliminary
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January 2007
I/O Structure
output pins (nSTATUSand CONF_DONE) and all the JTAG pins in I/O
bank 3 must operate at 2.5 V because the VCCIO level of SSTL-2 is 2.5 V.
I/O banks 1, 2, 3, and 4 support DQS signals with DQ bus modes of × 8.
For × 8 mode, there are up to eight groups of programmable DQS and DQ
pins, I/O banks 1, 2, 3, and 4 each have two groups in the 324-pin and
400-pin FineLine BGA packages. Each group consists of one DQS pin, a
set of eight DQ pins, and one DM pin (see Figure 2–33). Each DQS pin
drives the set of eight DQ pins within that group.
Figure 2–33. Cyclone Device DQ & DQS Groups in × 8 Mode
Note (1)
Top, Bottom, Left, or Right I/O Bank
DQ Pins
DQS Pin
DM Pin
Note to Figure 2–33:
(1) Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin.
Table 2–10 shows the number of DQ pin groups per device.
Table 2–10. DQ Pin Groups (Part 1 of 2)
Number of × 8 DQ
Total DQ Pin
Device
Package
Pin Groups
Count
EP1C3
100-pin TQFP (1)
144-pin TQFP
3
4
8
8
24
32
64
64
EP1C4
324-pin FineLine BGA
400-pin FineLine BGA
Altera Corporation
January 2007
2–47
Preliminary
Cyclone Device Handbook, Volume 1
Table 2–10. DQ Pin Groups (Part 2 of 2)
Number of × 8 DQ
Total DQ Pin
Count
Device
Package
Pin Groups
EP1C6
144-pin TQFP
4
4
4
4
4
8
8
8
32
32
32
32
32
64
64
64
240-pin PQFP
256-pin FineLine BGA
240-pin PQFP
EP1C12
EP1C20
256-pin FineLine BGA
324-pin FineLine BGA
324-pin FineLine BGA
400-pin FineLine BGA
Note to Table 2–10:
(1) EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in
I/O bank 1.
A programmable delay chain on each DQS pin allows for either a 90°
phase shift (for DDR SDRAM), or a 72° phase shift (for FCRAM) which
automatically center-aligns input DQS synchronization signals within the
data window of their corresponding DQ data signals. The phase-shifted
DQS signals drive the global clock network. This global DQS signal clocks
DQ signals on internal LE registers.
These DQS delay elements combine with the PLL’s clocking and phase
shift ability to provide a complete hardware solution for interfacing to
high-speed memory.
The clock phase shift allows the PLL to clock the DQ output enable and
output paths. The designer should use the following guidelines to meet
133 MHz performance for DDR SDRAM and FCRAM interfaces:
■
■
The DQS signal must be in the middle of the DQ group it clocks
Resynchronize the incoming data to the logic array clock using
successive LE registers or FIFO buffers
■
LE registers must be placed in the LAB adjacent to the DQ I/O pin
column it is fed by
Figure 2–34 illustrates DDR SDRAM and FCRAM interfacing from the
I/O through the dedicated circuitry to the logic array.
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Preliminary
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January 2007
I/O Structure
Figure 2–34. DDR SDRAM & FCRAM Interfacing
DQS
OE LE
Register
OE
DQ
OE
OE LE
Output LE
Register
Register
OE LE
Register
V
CC
Output LE
Registers
t
Δ
clk
Adjacent
LAB LEs
OE LE
Register
Input LE
Registers
DataA
DataB
Output LE
Register
-90˚ clk
GND
Output LE
Registers
Input LE
Registers
Programmable
Delay Chain
PLL
Global Clock
Phase Shifted -90˚
LE
Register
LE
Register
Resynchronizing
Global Clock
Adjacent LAB LEs
Programmable Drive Strength
The output buffer for each Cyclone device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standards have several levels of drive strength that the designer
can control. SSTL-3 class I and II, and SSTL-2 class I and II support a
minimum setting, the lowest drive strength that guarantees the IOH/IOL
Altera Corporation
January 2007
2–49
Preliminary
Cyclone Device Handbook, Volume 1
of the standard. Using minimum settings provides signal slew rate
control to reduce system noise and signal overshoot. Table 2–11 shows the
possible settings for the I/O standards with drive strength control.
Table 2–11. Programmable Drive Strength Note (1)
IOH/IOL Current Strength Setting (mA)
I/O Standard
LVTTL (3.3 V)
4
8
12
16
24(2)
2
LVCMOS (3.3 V)
LVTTL (2.5 V)
4
8
12(2)
2
8
12
16(2)
2
LVTTL (1.8 V)
8
12(2)
2
LVCMOS (1.5 V)
4
8(2)
Notes to Table 2–11:
(1) SSTL-3 class I and II, SSTL-2 class I and II, and 3.3-V PCI I/O Standards do not
support programmable drive strength.
(2) This is the default current strength setting in the Quartus II software.
Open-Drain Output
Cyclone devices provide an optional open-drain (equivalent to an open-
collector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and write-
enable signals) that can be asserted by any of several devices.
2–50
Preliminary
Altera Corporation
January 2007
I/O Structure
Slew-Rate Control
The output buffer for each Cyclone device I/O pin has a programmable
output slew-rate control that can be configured for low noise or high-
speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. However, these fast transitions may
introduce noise transients into the system. A slow slew rate reduces
system noise, but adds a nominal delay to rising and falling edges. Each
I/O pin has an individual slew-rate control, allowing the designer to
specify the slew rate on a pin-by-pin basis. The slew-rate control affects
both the rising and falling edges.
Bus Hold
Each Cyclone device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can hold the signal on an I/O pin at its last-driven
state. Since the bus-hold feature holds the last-driven state of the pin until
the next input signal is present, an external pull-up or pull-down resistor
is not necessary to hold a signal level when the bus is tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. The designer can select this feature individually for each I/O
pin. The bus-hold output will drive no higher than VCCIO to prevent
overdriving signals. If the bus-hold feature is enabled, the device cannot
use the programmable pull-up option. Disable the bus-hold feature when
the I/O pin is configured for differential signals.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of
approximately 7 kΩto pull the signal level to the last-driven state.
Table 4–15 on page 4–6 gives the specific sustaining current for each
VCCIO voltage level driven through this resistor and overdrive current
used to identify the next-driven input level.
The bus-hold circuitry is only active after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Cyclone device I/O pin provides an optional programmable pull-
up resistor during user mode. If the designer enables this feature for an
I/O pin, the pull-up resistor (typically 25 kΩ) holds the output to the
VCCIO level of the output pin's bank. Dedicated clock pins do not have the
optional programmable pull-up resistor.
Altera Corporation
January 2007
2–51
Preliminary
Cyclone Device Handbook, Volume 1
Advanced I/O Standard Support
Cyclone device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
LVDS
RSDS
SSTL-2 class I and II
SSTL-3 class I and II
Differential SSTL-2 class II (on output clocks only)
Table 2–12 describes the I/O standards supported by Cyclone devices.
Table 2–12. Cyclone I/O Standards
Board
Termination
Voltage (VTT) (V)
Input Reference
Voltage (VREF) (V) Voltage (VCCIO) (V)
Output Supply
I/O Standard
Type
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Differential
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.25
1.5
3.3
2.5
1.8
1.5
3.3
2.5
2.5
2.5
3.3
2.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.25
1.5
3.3-V PCI (1)
LVDS (2)
RSDS (2)
Differential
SSTL-2 class I and II
SSTL-3 class I and II
Differential SSTL-2 (3)
Voltage-referenced
Voltage-referenced
Differential
1.25
1.25
Notes to Table 2–12:
(1) There is no megafunction support for EP1C3 devices for the PCI compiler. However, EP1C3 devices support PCI
by using the LVTTL 16-mA I/O standard and drive strength assignments in the Quartus II software. The device
requires an external diode for PCI compliance.
(2) EP1C3 devices in the 100-pin TQFP package do not support the LVDS and RSDS I/O standards.
(3) This I/O standard is only available on output clock pins (PLL_OUTpins). EP1C3 devices in the 100-pin package
do not support this I/O standard as it does not have PLL_OUTpins.
Cyclone devices contain four I/O banks, as shown in Figure 2–35. I/O
banks 1 and 3 support all the I/O standards listed in Table 2–12. I/O
banks 2 and 4 support all the I/O standards listed in Table 2–12 except the
3.3-V PCI standard. I/O banks 2 and 4 contain dual-purpose DQS, DQ,
2–52
Preliminary
Altera Corporation
January 2007
I/O Structure
and DM pins to support a DDR SDRAM or FCRAM interface. I/O bank
1 can also support a DDR SDRAM or FCRAM interface, however, the
configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3
can also support a DDR SDRAM or FCRAM interface, however, all the
JTAG pins in I/O bank 3 must operate at 2.5 V.
Figure 2–35. Cyclone I/O Banks
Notes (1), (2)
I/O Bank 2
I/O Bank 1
Also Supports
the 3.3-V PCI
I/O Standard
I/O Bank 3
Also Supports
the 3.3-V PCI
I/O Standard
All I/O Banks Support
■ 3.3-V LVTTL/LVCMOS
■ 2.5-V LVTTL/LVCMOS
■ 1.8-V LVTTL/LVCMOS
■ 1.5-V LVCMOS
I/O Bank 1
I/O Bank 3
■ LVDS
■ RSDS
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
Individual
Power Bus
I/O Bank 4
Notes to Figure 2–35:
(1) Figure 2–35 is a top view of the silicon die.
(2) Figure 2–35 is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
Each I/O bank has its own VCCIOpins. A single device can support 1.5-V,
1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a
different standard with different I/O voltages. Each bank also has dual-
purpose VREFpins to support any one of the voltage-referenced
standards (e.g., SSTL-3) independently. If an I/O bank does not use
voltage-referenced standards, the VREF pins are available as user I/O pins.
Altera Corporation
January 2007
2–53
Preliminary
Cyclone Device Handbook, Volume 1
Each I/O bank can support multiple standards with the same VCCIO for
input and output pins. For example, when VCCIO is 3.3-V, a bank can
support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
LVDS I/O Pins
A subset of pins in all four I/O banks supports LVDS interfacing. These
dual-purpose LVDS pins require an external-resistor network at the
transmitter channels in addition to 100-Ωtermination resistors on receiver
channels. These pins do not contain dedicated serialization or
deserialization circuitry; therefore, internal logic performs serialization
and deserialization functions.
Table 2–13 shows the total number of supported LVDS channels per
device density.
Table 2–13. Cyclone Device LVDS Channels
Device
Pin Count
Number of LVDS Channels
EP1C3
EP1C4
EP1C6
100
144
324
400
144
240
256
240
256
324
324
400
(1)
34
103
129
29
72
72
EP1C12
66
72
103
95
EP1C20
129
Note to Table 2–13:
(1) EP1C3 devices in the 100-pin TQFP package do not support the LVDS I/O
standard.
MultiVolt I/O Interface
The Cyclone architecture supports the MultiVolt I/O interface feature,
which allows Cyclone devices in all packages to interface with systems of
different supply voltages. The devices have one set of VCC pins for
internal operation and input buffers (VCCINT), and four sets for I/O
output drivers (VCCIO).
2–54
Preliminary
Altera Corporation
January 2007
Power Sequencing & Hot Socketing
The Cyclone VCCINT pins must always be connected to a 1.5-V power
supply. If the VCCINT level is 1.5 V, then input pins are 1.5-V, 1.8-V, 2.5-V,
and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V,
2.5-V, or 3.3-V power supply, depending on the output requirements. The
output levels are compatible with systems of the same voltage as the
power supply (i.e., when VCCIO pins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems). When VCCIO
pins are connected to a 3.3-V power supply, the output high is 3.3-V and
is compatible with 3.3-V or 5.0-V systems. Table 2–14 summarizes
Cyclone MultiVolt I/O support.
Table 2–14. Cyclone MultiVolt I/O Support
Note (1)
Input Signal
1.5 V 1.8 V 2.5 V 3.3 V 5.0 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V
Output Signal
VCCIO (V)
1.5
1.8
2.5
3.3
v (2)
v (2) v (2)
v (2)
v
v
v
v
v
v (3)
v (5)
v
v (5)
v
v
v
v (4)
v (6) v (7) v (7) v (7)
v (8)
v
v
Notes to Table 2–14:
(1) The PCI clamping diode must be disabled to drive an input with voltages higher than VCCIO
.
(2) When VCCIO = 1.5-V or 1.8-V and a 2.5-V or 3.3-V input signal feeds an input pin, higher pin leakage current is
expected. Turn on Allow voltage overdrive for LVTTL / LVCMOS input pins in the Assignments > Device >
Device and Pin Options > Pin Placement tab when a device has this I/O combinations.
(3) When VCCIO = 1.8-V, a Cyclone device can drive a 1.5-V device with 1.8-V tolerant inputs.
(4) When VCCIO = 3.3-V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger
than expected.
(5) When VCCIO = 2.5-V, a Cyclone device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs.
(6) Cyclone devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode.
(7) When VCCIO = 3.3-V, a Cyclone device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.
(8) When VCCIO = 3.3-V, a Cyclone device can drive a device with 5.0-V LVTTL inputs but not 5.0-V LVCMOS inputs.
Because Cyclone devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. Therefore, the VCCIO and VCCINT power supplies may be
powered in any order.
Power
Sequencing &
Hot Socketing
Signals can be driven into Cyclone devices before and during power up
without damaging the device. In addition, Cyclone devices do not drive
out during power up. Once operating conditions are reached and the
device is configured, Cyclone devices operate as specified by the user.
Altera Corporation
January 2007
2–55
Preliminary
Cyclone Device Handbook, Volume 1
Table 2–15 shows the revision history for this document.
Document
Revision History
Table 2–15. Document Revision History
Date &
Document
Version
Changes Made
Summary of Changes
January 2007
v1.5
●
●
Added document revision history.
Updated Figures 2–17, 2–18, 2–19, 2–20, 2–21, and 2–32.
August 2005
v1.4
Minor updates.
February 2005
v1.3
●
●
●
Updated JTAG chain limits. Added test vector information.
Corrected Figure 2-12.
Added a note to Tables 2-17 through 2-21 regarding violating
the setup or hold time.
October 2003
v1.2
●
●
Updated phase shift information.
Added 64-bit PCI support information.
September
2003 v1.1
Updated LVDS data rates to 640 Mbps from 311 Mbps.
May 2003 v1.0 Added document to Cyclone Device Handbook.
2–56
Preliminary
Altera Corporation
January 2007
3. Configuration & Testing
C51003-1.3
All Cyclone® devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be
performed either before or after, but not during configuration. Cyclone
devices can also use the JTAG port for configuration together with either
the Quartus® II software or hardware using either Jam Files (.jam) or Jam
Byte-Code Files (.jbc).
IEEE Std. 1149.1
(JTAG)Boundary
Scan Support
Cyclone devices support reconfiguring the I/O standard settings on the
IOE through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode. Designers can use this ability for JTAG testing before configuration
when some of the Cyclone pins drive or receive from other devices on the
board using voltage-referenced standards. Since the Cyclone device
might not be configured before JTAG testing, the I/O pins might not be
configured for appropriate electrical standards for chip-to-chip
communication. Programming those I/O standards via JTAG allows
designers to fully test I/O connection to other devices.
The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The
TDO pin voltage is determined by the VCCIO of the bank where it resides.
The bank VCCIO selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or
3.3-V compatible.
Cyclone devices also use the JTAG port to monitor the operation of the
®
device with the SignalTap II embedded logic analyzer. Cyclone devices
support the JTAG instructions shown in Table 3–1.
Table 3–1. Cyclone JTAG Instructions (Part 1 of 2)
JTAG Instruction
Instruction Code
Description
00 0000 0101
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
SAMPLE/PRELOAD
00 0000 0000
11 1111 1111
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
EXTEST(1)
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
BYPASS
Altera Corporation
January 2007
3–1
Preliminary
Cyclone Device Handbook, Volume 1
Table 3–1. Cyclone JTAG Instructions (Part 2 of 2)
JTAG Instruction
Instruction Code
Description
00 0000 0111
Selects the 32-bit USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of TDO.
USERCODE
00 0000 0110
00 0000 1011
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
IDCODE
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
HIGHZ(1)
00 0000 1010
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
CLAMP(1)
ICR instructions
Used when configuring a Cyclone device via the JTAG port with a
MasterBlasterTM or ByteBlasterMVTM download cable, or when
using a Jam File or Jam Byte-Code File via an embedded
processor.
00 0000 0001
00 0000 1101
PULSE_NCONFIG
CONFIG_IO
Emulates pulsing the nCONFIGpin low to trigger reconfiguration
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, after, or during
configuration. Stops configuration if executed during configuration.
Once issued, the CONFIG_IOinstruction will hold nSTATUSlow
to reset the configuration device. nSTATUSis held low until the
device is reconfigured.
SignalTap II
instructions
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
Note to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
In the Quartus II software, there is an Auto Usercode feature where you
can choose to use the checksum value of a programming file as the JTAG
user code. If selected, the checksum is automatically loaded to the
USERCODE register. Choose Assignments > Device > Device and Pin
Options > General. Turn on Auto Usercode.
3–2
Preliminary
Altera Corporation
January 2007
IEEE Std. 1149.1 (JTAG) Boundary Scan Support
The Cyclone device instruction register length is 10 bits and the
USERCODE register length is 32 bits. Tables 3–2 and 3–3 show the
boundary-scan register length and device IDCODE information for
Cyclone devices.
Table 3–2. Cyclone Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
339
930
582
774
930
Table 3–3. 32-Bit Cyclone Device IDCODE
IDCODE (32 bits) (1)
Device
Manufacturer Identity
Version (4 Bits)
Part Number (16 Bits)
LSB (1 Bit) (2)
(11 Bits)
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
0000
0000
0000
0000
0000
0010 0000 1000 0001
0010 0000 1000 0101
0010 0000 1000 0010
0010 0000 1000 0011
0010 0000 1000 0100
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
1
1
1
1
1
Notes to Table 3–3:
(1) The most significant bit (MSB) is on the left.
(2) The IDCODE’s least significant bit (LSB) is always 1.
Altera Corporation
January 2007
3–3
Preliminary
Cyclone Device Handbook, Volume 1
Figure 3–1 shows the timing requirements for the JTAG signals.
Figure 3–1. Cyclone JTAG Waveforms
TMS
TDI
tJCP
tJCH
t JCL
tJPH
tJPSU
TCK
TDO
tJPXZ
tJPZX
tJPCO
tJSSU
tJSH
Signal
to Be
Captured
tJSCO
tJSZX
tJSXZ
Signal
to Be
Driven
Table 3–4 shows the JTAG timing parameters and values for Cyclone
devices.
Table 3–4. Cyclone JTAG Timing Parameters & Values
Symbol
tJCP
Parameter
Min Max Unit
100
50
50
20
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCKclock period
tJCH
TCKclock high time
tJCL
TCKclock low time
tJPSU
tJPH
JTAG port setup time
JTAG port hold time
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output
25
25
25
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
20
45
Capture register hold time
tJSCO
tJSZX
tJSXZ
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
35
35
35
3–4
Preliminary
Altera Corporation
January 2007
SignalTap II Embedded Logic Analyzer
1
Cyclone devices must be within the first 8 devices in a JTAG
chain. All of these devices have the same JTAG controller. If any
of the Cyclone devices are in the 9th or after they will fail
configuration. This does not affect the SignalTap® II logic
analyzer.
f
For more information on JTAG, see the following documents:
■
■
AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices
Jam Programming & Test Language Specification
Cyclone devices feature the SignalTap II embedded logic analyzer, which
monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. A designer can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
SignalTap II
Embedded Logic
Analyzer
The logic, circuitry, and interconnects in the Cyclone architecture are
configured with CMOS SRAM elements. Altera FPGAs are
Configuration
reconfigurable and every device is tested with a high coverage
production test program so the designer does not have to perform fault
testing and can instead focus on simulation and design verification.
Cyclone devices are configured at system power-up with data stored in
an Altera configuration device or provided by a system controller. The
Cyclone device's optimized interface allows the device to act as controller
in an active serial configuration scheme with the new low-cost serial
configuration device. Cyclone devices can be configured in under 120 ms
using serial data at 20 MHz. The serial configuration device can be
programmed via the ByteBlaster II download cable, the Altera
Programming Unit (APU), or third-party programmers.
In addition to the new low-cost serial configuration device, Altera offers
in-system programmability (ISP)-capable configuration devices that can
configure Cyclone devices via a serial data stream. The interface also
enables microprocessors to treat Cyclone devices as memory and
configure them by writing to a virtual memory location, making
reconfiguration easy. After a Cyclone device has been configured, it can
be reconfigured in-circuit by resetting the device and loading new data.
Real-time changes can be made during system operation, enabling
innovative reconfigurable computing applications.
Altera Corporation
January 2007
3–5
Preliminary
Cyclone Device Handbook, Volume 1
Operating Modes
The Cyclone architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. Together, the configuration and initialization
processes are called command mode. Normal device operation is called
user mode.
SRAM configuration elements allow Cyclone devices to be reconfigured
in-circuit by loading new configuration data into the device. With real-
time reconfiguration, the device is forced into command mode with a
device pin. The configuration process loads different configuration data,
reinitializes the device, and resumes user-mode operation. Designers can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
A built-in weak pull-up resistor pulls all user I/O pins to VCCIO before
and during device configuration.
The configuration pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O
standards. The voltage level of the configuration output pins is
determined by the VCCIO of the bank where the pins reside. The bank
VCCIO selects whether the configuration inputs are 1.5-V, 1.8-V, 2.5-V, or
3.3-V compatible.
Configuration Schemes
Designers can load the configuration data for a Cyclone device with one
of three configuration schemes (see Table 3–5), chosen on the basis of the
target application. Designers can use a configuration device, intelligent
controller, or the JTAG port to configure a Cyclone device. A low-cost
configuration device can automatically configure a Cyclone device at
system power-up.
3–6
Preliminary
Altera Corporation
January 2007
Document Revision History
Multiple Cyclone devices can be configured in any of the three
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device.
Table 3–5. Data Sources for Configuration
Configuration Scheme
Data Source
Active serial
Low-cost serial configuration device
Passive serial (PS)
Enhanced or EPC2 configuration device,
MasterBlaster or ByteBlasterMV download cable,
or serial data source
JTAG
MasterBlaster or ByteBlasterMV download cable
or a microprocessor with a Jam or JBC file
Table 3–6 shows the revision history for this document.
Document
Revision History
Table 3–6. Document Revision History
Date &
Document
Version
Changes Made
Summary of Changes
January 2007
v1.3
●
●
Added document revision history.
Updated handpara note below Table 3–4.
August 2005
V1.2
Minor updates.
February 2005
V1.1
Updated JTAG chain limits. Added information concerning test
vectors.
May 2003 v1.0 Added document to Cyclone Device Handbook.
Altera Corporation
January 2007
3–7
Preliminary
Cyclone Device Handbook, Volume 1
3–8
Preliminary
Altera Corporation
January 2007
4. DC & Switching
Characteristics
C51004-1.6
Cyclone® devices are offered in both commercial, industrial, and
extended temperature grades. However, industrial-grade and extended-
temperature-grade devices may have limited speed-grade availability.
Operating
Conditions
Tables 4–1 through 4–16 provide information on absolute maximum
ratings, recommended operating conditions, DC operating conditions,
and capacitance for Cyclone devices.
Table 4–1. Cyclone Device Absolute Maximum Ratings
Notes (1), (2)
Symbol
VCCINT
VCCIO
VCCA
VI
Parameter
Conditions
Minimum
–0.5
Maximum
2.4
Unit
V
Supply voltage
With respect to ground (3)
With respect to ground (3)
–0.5
4.6
V
Supply voltage
–0.5
2.4
V
DC input voltage
–0.5
4.6
V
IOUT
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
–25
25
mA
° C
° C
° C
TSTG
TAMB
TJ
No bias
–65
150
135
135
Under bias
–65
BGA packages under bias
Table 4–2. Cyclone Device Recommended Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCINT
Supply voltage for internal logic
and input buffers
(4)
1.425
1.575
V
V
V
V
V
V
VCCIO
Supply voltage for output buffers,
3.3-V operation
(4)
(4)
3.00
2.375
1.71
1.4
3.60
2.625
1.89
1.6
Supply voltage for output buffers,
2.5-V operation
Supply voltage for output buffers,
1.8-V operation
(4)
Supply voltage for output buffers,
1.5-V operation
(4)
VI
Input voltage
(3), (5)
–0.5
4.1
Altera Corporation
January 2007
4–1
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–2. Cyclone Device Recommended Operating Conditions (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Maximum
VCCIO
Unit
V
VO
TJ
Output voltage
Operating junction temperature
0
0
For commercial
use
85
° C
For industrial use
–40
–40
100
125
° C
° C
For extended-
temperature use
Table 4–3. Cyclone Device DC Operating Conditions
Note (6)
Typica
l
Symbol
Parameter
Conditions
Minimum
Maximum Unit
II
Input pin leakage current
VI = VCCIOmax to 0 V (8)
VO = VCCIOmax to 0 V (8)
–10
–10
10
10
μA
μA
IOZ
Tri-stated I/O pin leakage
current
ICC0
VCC supply current (standby)
(All M4K blocks in power-down
mode) (7)
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
4
6
mA
mA
mA
mA
mA
6
8
12
RCONF (9) Value of I/O pin pull-up resistor VI = 0 V; VCCI0 = 3.3 V
15
20
30
50
25
45
65
100
1
50
70
kΩ
kΩ
kΩ
kΩ
kΩ
before and during configuration
VI = 0 V; VCCI0 = 2.5 V
VI = 0 V; VCCI0 = 1.8 V
VI = 0 V; VCCI0 = 1.5 V
100
150
2
Recommended value of I/O pin
external pull-down resistor
before and during configuration
Table 4–4. LVTTL Specifications (Part 1 of 2)
Symbol
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
Conditions
Minimum
3.0
Maximum
Unit
VCCIO
3.6
4.1
0.7
V
V
V
VIH
VIL
1.7
–0.5
4–2
Preliminary
Altera Corporation
January 2007
Operating Conditions
Table 4–4. LVTTL Specifications (Part 2 of 2)
Symbol
Parameter
High-level output voltage
Low-level output voltage
Conditions
Minimum
Maximum
Unit
V
VOH
VOL
IOH = –4 to –24 mA (11)
IOL = 4 to 24 mA (11)
2.4
0.45
V
Table 4–5. LVCMOS Specifications
Symbol
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Conditions
Minimum
3.0
Maximum
3.6
Unit
V
VCCIO
VIH
VIL
1.7
4.1
V
–0.5
0.7
V
VOH
VCCIO = 3.0,
V
CCIO – 0.2
V
IOH = –0.1 mA
VOL
Low-level output voltage
VCCIO = 3.0,
IOL = 0.1 mA
0.2
V
Table 4–6. 2.5-V I/O Specifications
Symbol
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Conditions
Minimum
2.375
1.7
Maximum
2.625
4.1
Unit
V
VCCIO
VIH
VIL
V
–0.5
2.1
0.7
V
VOH
IOH = –0.1 mA
V
I
I
OH = –1 mA
2.0
V
OH = –2 to –16 mA (11)
1.7
V
VOL
Low-level output voltage
IOL = 0.1 mA
0.2
0.4
0.7
V
I
I
OH = 1 mA
V
OH = 2 to 16 mA (11)
V
Altera Corporation
January 2007
4–3
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–7. 1.8-V I/O Specifications
Symbol
Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions
Minimum
1.65
Maximum
1.95
Unit
V
VCCIO
VIH
VIL
0.65 × VCCIO
–0.3
2.25 (12)
0.35 × VCCIO
V
V
VOH
VOL
IOH = –2 to –8 mA (11) VCCIO – 0.45
IOL = 2 to 8 mA (11)
V
0.45
V
Table 4–8. 1.5-V I/O Specifications
Symbol
Parameter
Output supply voltage
High-level input voltage
Conditions
Minimum
Maximum
Unit
V
VCCIO
1.4
1.6
VIH
0.65 × VCCIO VCCIO + 0.3
V
(12)
VIL
Low-level input voltage
High-level output voltage
Low-level output voltage
–0.3
0.35 × VCCIO
V
V
V
VOH
VOL
IOH = –2 mA (11)
IOL = 2 mA (11)
0.75 × VCCIO
0.25 × VCCIO
Table 4–9. 2.5-V LVDS I/O Specifications
Note (13)
Symbol
Parameter
Conditions
Minimum Typical Maximum
Unit
V
VCCIO
I/O supply voltage
2.375
250
2.5
2.625
550
50
VOD
Differential output voltage RL = 100 Ω
mV
mV
Δ VOD
Change in VOD between
high and low
RL = 100 Ω
VOS
Output offset voltage
RL = 100 Ω
RL = 100 Ω
1.125
1.25
1.375
50
V
Δ VOS
Change in VOS between
high and low
mV
VTH
VIN
Differential input threshold VCM = 1.2 V
–100
0.0
100
2.4
mV
V
Receiver input voltage
range
RL
Receiver differential input
resistor
90
100
110
Ω
4–4
Preliminary
Altera Corporation
January 2007
Operating Conditions
Table 4–10. 3.3-V PCI Specifications
Symbol
Parameter
Conditions
Minimum Typical Maximum
Unit
V
VCCIO
Output supply voltage
High-level input voltage
3.0
3.3
3.6
VIH
0.5 ×
VCCIO
VCCIO
0.5
+
V
VIL
Low-level input voltage
High-level output voltage
Low-level output voltage
–0.5
0.3 ×
VCCIO
V
V
V
VOH
VOL
IOUT = –500 μA
IOUT = 1,500 μA
0.9 ×
VCCIO
0.1 ×
VCCIO
Table 4–11. SSTL-2 Class I Specifications
Symbol
Parameter
Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
Unit
V
VCCIO
Output supply voltage
Termination voltage
Reference voltage
VTT
VREF
VIH
VREF – 0.04
1.15
VREF
1.25
VREF + 0.04
1.35
V
V
High-level input voltage
Low-level input voltage
High-level output voltage
VREF + 0.18
–0.3
3.0
V
VIL
VREF – 0.18
V
VOH
IOH = –8.1 mA
VTT + 0.57
V
(11)
VOL
Low-level output voltage
IOL = 8.1 mA (11)
VTT – 0.57
V
Table 4–12. SSTL-2 Class II Specifications
Symbol
Parameter
Conditions
Minimum
2.3
Typical
2.5
Maximum
2.7
Unit
V
VCCIO
Output supply voltage
Termination voltage
Reference voltage
VTT
VREF
VIH
VREF – 0.04
1.15
VREF
1.25
VREF + 0.04
1.35
V
V
High-level input voltage
Low-level input voltage
High-level output voltage
VREF + 0.18
–0.3
VCCIO + 0.3
VREF – 0.18
V
VIL
V
VOH
IOH = –16.4 mA
VTT + 0.76
V
(11)
VOL
Low-level output voltage
IOL = 16.4 mA
VTT – 0.76
V
(11)
Altera Corporation
January 2007
4–5
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–13. SSTL-3 Class I Specifications
Symbol
Parameter
Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
Unit
V
VCCIO
Output supply voltage
Termination voltage
VTT
VREF
VIH
VREF – 0.05
1.3
VREF
1.5
VREF + 0.05
1.7
V
Reference voltage
V
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
VREF + 0.2
–0.3
VCCIO + 0.3
VREF – 0.2
V
VIL
V
VOH
VOL
IOH = –8 mA (11)
IOL = 8 mA (11)
VTT + 0.6
V
VTT – 0.6
V
Table 4–14. SSTL-3 Class II Specifications
Symbol
Parameter
Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
Unit
V
VCCIO
Output supply voltage
Termination voltage
Reference voltage
VTT
VREF
VIH
VREF – 0.05
1.3
VREF
1.5
VREF + 0.05
1.7
V
V
High-level input voltage
Low-level input voltage
High-level output voltage
VREF + 0.2
–0.3
VCCIO + 0.3
VREF – 0.2
V
VIL
V
VOH
IOH = –16 mA
VTT + 0.8
V
(11)
VOL
Low-level output voltage
IOL = 16 mA (11)
VTT – 0.8
V
Table 4–15. Bus Hold Parameters
VCCIO Level
Parameter
Conditions
Unit
1.5 V
Min Max
1.8 V
Max
2.5 V
3.3 V
Min
Min
Max
Min
Max
Low sustaining VIN > VIL
current
30
50
70
μA
μA
μA
μA
(maximum)
High sustaining VIN < VIH
–30
–50
–70
current
(minimum)
Low overdrive
current
0 V < VIN
VCCIO
<
200
300
500
High overdrive 0 V < VIN
<
–200
–300
–500
current
VCCIO
4–6
Preliminary
Altera Corporation
January 2007
Operating Conditions
Table 4–16. Cyclone Device Capacitance
Note (14)
Symbol
Parameter
Typical
Unit
pF
CIO
Input capacitance for user I/O pin
4.0
4.7
CLVDS
CVREF
CDPCLK
CCLK
Input capacitance for dual-purpose LVDS/user I/O pin
Input capacitance for dual-purpose VREF/user I/O pin.
Input capacitance for dual-purpose DPCLK/user I/O pin.
Input capacitance for CLK pin.
pF
12.0
4.4
pF
pF
4.7
pF
Notes to Tables 4–1 through 4–16:
(1) Refer to the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V for
input currents less than 100 mA and periods shorter than 20 ns.
(4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6) Typical values are for TA = 25° C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(7) VI = ground, no load, no toggling inputs.
(8) This value is specified for normal device operation. The value may vary during power-up. This applies for all
VCCIO settings (3.3, 2.5, 1.8, and 1.5 V).
(9) RCONF is the measured value of internal pull-up resistance when the I/O pin is tied directly to GND. RCONF value
will be lower if an external source drives the pin higher than VC CIO
.
(10) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO
.
(11) Drive strength is programmable according to values in Chapter 2, Cyclone Architecture, Table 2–11.
(12) Overdrive is possible when a 1.5 V or 1.8 V and a 2.5 V or 3.3 V input signal feeds an input pin. Turn on “Allow
voltage overdrive” for LVTTL/LVCMOS input pins in the Assignments > Device > Device and Pin Options > Pin
Placement tab when a device has this I/O combination. However, higher leakage current is expected.
(13) The Cyclone LVDS interface requires a resistor network outside of the transmitter channels.
(14) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within 0.5 pF.
Altera Corporation
January 2007
4–7
Preliminary
Cyclone Device Handbook, Volume 1
Designers can use the Altera web Early Power Estimator to estimate the
device power.
Power
Consumption
Cyclone devices require a certain amount of power-up current to
successfully power up because of the nature of the leading-edge process
on which they are fabricated. Table 4–17 shows the maximum power-up
current required to power up a Cyclone device.
Table 4–17. Cyclone Maximum Power-Up Current (ICCINT) Requirements (In-Rush Current)
Device
Commercial Specification
Industrial Specification
Unit
EP1C3
150
150
175
300
500
180
180
210
360
600
mA
mA
mA
mA
mA
EP1C4
EP1C6
EP1C12
EP1C20
Notes to Table 4–17:
(1) The Cyclone devices (except for the EP1C20 device) meet the power up specification for Mini PCI.
(2) The lot codes 9G0082 to 9G2999, or 9G3109 and later comply to the specifications in Table 4–17 and meet the Mini
PCI specification. Lot codes appear at the top of the device.
(3) The lot codes 9H0004 to 9H29999, or 9H3014 and later comply to the specifications in this table and meet the Mini
PCI specification. Lot codes appear at the top of the device.
Designers should select power supplies and regulators that can supply
this amount of current when designing with Cyclone devices. This
specification is for commercial operating conditions. Measurements were
performed with an isolated Cyclone device on the board. Decoupling
capacitors were not used in this measurement. To factor in the current for
decoupling capacitors, sum up the current for each capacitor using the
following equation:
I = C (dV/dt)
The exact amount of current that is consumed varies according to the
process, temperature, and power ramp rate. If the power supply or
regulator can supply more current than required, the Cyclone device may
consume more current than the maximum current specified in Table 4–17.
However, the device does not require any more current to successfully
power up than what is listed in Table 4–17.
The duration of the ICCINT power-up requirement depends on the VCCINT
voltage supply rise time. The power-up current consumption drops when
the VCCINT supply reaches approximately 0.75 V. For example, if the
VCCINT rise time has a linear rise of 15 ms, the current consumption spike
drops by 7.5 ms.
4–8
Preliminary
Altera Corporation
January 2007
Timing Model
Typically, the user-mode current during device operation is lower than
the power-up current in Table 4–17. Altera recommends using the
Cyclone Power Calculator, available on the Altera web site, to estimate
the user-mode ICCINT consumption and then select power supplies or
regulators based on the higher value.
The DirectDrive technology and MultiTrack interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Cyclone device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
Timing Model
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The
Quartus® II software issues an informational message during the design
compilation if the timing models are preliminary. Table 4–18 shows the
status of the Cyclone device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 4–18. Cyclone Device Timing Model Status
Device
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Preliminary
Final
v
v
v
v
v
Altera Corporation
January 2007
4–9
Preliminary
Cyclone Device Handbook, Volume 1
Performance
The maximum internal logic array clock tree frequency is limited to the
specifications shown in Table 4–19.
Table 4–19. Clock Tree Maximum Performance Specification
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Parameter
Definition
Units
Min Typ Max Min Typ Max Min Typ Max
Clock tree
fMAX
Maximumfrequency
that the clock tree
can support for
clocking registered
logic
405
320
275 MHz
Table 4–20 shows the Cyclone device performance for some common
designs. All performance values were obtained with the Quartus II
software compilation of library of parameterized modules (LPM)
functions or megafunctions. These performance values are based on
EP1C6 devices in 144-pin TQFP packages.
Table 4–20. Cyclone Device Performance
Resources Used
M4K
Performance
Resource
Used
Design Size &
Function
M4K
-6 Speed -7 Speed -8 Speed
Mode
LEs
Memory Memory
Grade
(MHz)
Grade
(MHz)
Grade
(MHz)
Bits
Blocks
LE
16-to-1
multiplexer
-
-
21
44
-
-
405.00
320.00
275.00
32-to-1
-
-
317.36
284.98
260.15
multiplexer
16-bit counter
-
-
16
66
-
-
-
-
405.00
208.99
320.00
181.98
275.00
160.75
64-bit counter (1)
4–10
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–20. Cyclone Device Performance
Resources Used
M4K
Performance
-6 Speed -7 Speed -8 Speed
Resource
Used
Design Size &
Function
M4K
Mode
LEs
Memory Memory
Grade
(MHz)
Grade
(MHz)
Grade
(MHz)
Bits
Blocks
M4K
memory
block
RAM 128 × 36 bit Single port
-
-
4,608
4,608
1
1
256.00
255.95
222.67
222.67
197.01
196.97
RAM 128 × 36 bit Simple
dual-port
mode
RAM 256 × 18 bit True dual-
port mode
-
4,608
1
255.95
222.67
196.97
FIFO 128 × 36 bit
-
40
11
4,608
4,536
1
1
256.02
255.95
222.67
222.67
197.01
196.97
Shift register
9 × 4 × 128
Shift
register
Note to Table 4–20:
(1) The performance numbers for this function are from an EP1C6 device in a 240-pin PQFP package.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 4–21 through 4–24 describe the
Cyclone device internal timing microparameters for LEs, IOEs, M4K
memory structures, and MultiTrack interconnects.
Table 4–21. LE Internal Timing Microparameter Descriptions
Symbol
Parameter
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinatorial LUT delay for data-in to data-out
Minimum clear pulse width
tSU
tH
tCO
tLUT
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
Altera Corporation
January 2007
4–11
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–22. IOE Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU
IOE input and output register setup time before clock
IOE input and output register hold time after clock
IOE input and output register clock-to-output delay
Row input pin to IOE combinatorial output
Column input pin to IOE combinatorial output
Row IOE data input to combinatorial output pin
Column IOE data input to combinatorial output pin
Minimum clear pulse width
tH
tCO
tPIN2COMBOUT_R
tPIN2COMBOUT_C
tCOMBIN2PIN_R
tCOMBIN2PIN_C
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
Table 4–23. M4K Block Internal Timing Microparameter Descriptions
Symbol Parameter
tM4KRC
Synchronous read cycle time
tM4KWC
Synchronous write cycle time
tM4KWERESU
tM4KWEREH
tM4KBESU
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
tM4KBEH
tM4KDATAASU
tM4KDATAAH
tM4KADDRASU
tM4KADDRAH
tM4KDATABSU
tM4KDATABH
tM4KADDRBSU
tM4KADDRBH
tM4KDATACO1
tM4KDATACO2
tM4KCLKHL
tM4KCLR
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
4–12
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–24. Routing Delay Internal Timing Microparameter Descriptions
Symbol Parameter
tR4
tC4
tLOCAL
Delay for an R4 line with average loading; covers a distance
of four LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
Local interconnect delay
Figure 4–1 shows the memory waveforms for the M4K timing parameters
shown in Table 4–23.
Figure 4–1. Dual-Port RAM Timing Microparameter Waveform
wrclock
tWEREH
tWERESU
wren
tWADDRH
tWADDRSU
an-1
an
a0
a1
a2
a3
a4
a5
wraddress
data-in
a6
tDATAH
din-1
din4
din5
din6
din
tDATASU
rdclock
tWEREH
tWERESU
rden
tRC
rdaddress
bn
b1
b2
b3
b0
tDATACO1
doutn-1
doutn
dout0
reg_data-out
doutn-2
tDATACO2
doutn
doutn-1
dout0
unreg_data-out
Altera Corporation
January 2007
4–13
Preliminary
Cyclone Device Handbook, Volume 1
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 4–25 through 4–28 show the
internal timing microparameters for LEs, IOEs, TriMatrix memory
structures, DSP blocks, and MultiTrack interconnects.
Table 4–25. LE Internal Timing Microparameters
-6
-7
-8
Symbol
Unit
Min
29
Max
Min
33
Max
Min
37
Max
tSU
ps
ps
ps
ps
ps
ps
ps
tH
12
13
15
tCO
tLUT
tCLR
tPRE
173
454
198
522
224
590
129
129
148
148
167
167
tCLKHL
1,234
1,562
1,818
Table 4–26. IOE Internal Timing Microparameters
-6 -7
-8
Symbol
Unit
Min
348
0
Max
Min
400
0
Max
Min
452
0
Max
tSU
tH
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tCO
511
587
664
tPIN2COMBOUT_R
tPIN2COMBOUT_C
tCOMBIN2PIN_R
tCOMBIN2PIN_C
tCLR
1,130
1,135
2,627
2,615
1,299
1,305
3,021
3,007
1,469
1,475
3,415
3,399
280
280
322
322
364
364
tPRE
tCLKHL
1,234
1,562
1,818
4–14
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–27. M4K Block Internal Timing Microparameters
-6 -7
-8
Symbol
Unit
Max
Min
Max
4,379
2,910
Min
Max
5,035
3,346
Min
tM4KRC
5,691
3,783
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tM4KWC
tM4KWERESU
tM4KWEREH
tM4KBESU
72
43
72
43
72
43
72
43
72
43
72
43
82
49
82
49
82
49
82
49
82
49
82
49
93
55
93
55
93
55
93
55
93
55
93
55
tM4KBEH
tM4KDATAASU
tM4KDATAAH
tM4KADDRASU
tM4KADDRAH
tM4KDATABSU
tM4KDATABH
tM4KADDRBSU
tM4KADDRBH
tM4KDATACO1
tM4KDATACO2
tM4KCLKHL
tM4KCLR
621
714
807
4,351
5,003
5,656
1,234
286
1,562
328
1,818
371
Table 4–28. Routing Delay Internal Timing Microparameters
-6 -7
-8
Symbol
Unit
Min
Max
261
338
244
Min
Max
300
388
281
Min
Max
339
439
318
tR4
tC4
tLOCAL
ps
ps
ps
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 4–2 shows the timing model for bidirectional IOE pin
timing. All registers are within the IOE.
Altera Corporation
January 2007
4–15
Preliminary
Cyclone Device Handbook, Volume 1
Figure 4–2. External Timing in Cyclone Devices
OE Register
PRN
D
Q
t
t
t
t
t
XZ
ZX
INSU
INH
OUTCO
Dedicated
Clock
CLRN
Output Register
PRN
Bidirectional
Pin
D
Q
CLRN
Input Register
PRN
D
Q
CLRN
All external I/O timing parameters shown are for 3.3-V LVTTL I/O
standard with the maximum current strength and fast slew rate. For
external I/O timing using standards other than LVTTL or for different
current strengths, use the I/O standard input and output delay adders in
Tables 4–40 through 4–44.
Table 4–29 shows the external I/O timing parameters when using global
clock networks.
Table 4–29. Cyclone Global Clock External I/O Timing Parameters
Notes (1), (2) (Part 1 of 2)
Symbol
Parameter
Conditions
tINSU
Setup time for input or bidirectional pin using IOE input
register with global clock fed by CLKpin
tINH
Hold time for input or bidirectional pin using IOE input
register with global clock fed by CLKpin
tOUTCO
tINSUPLL
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock fed by CLKpin
CLOAD = 10 pF
Setup time for input or bidirectional pin using IOE input
register with global clock fed by Enhanced PLL with default
phase setting
tINHPLL
Hold time for input or bidirectional pin using IOE input
register with global clock fed by enhanced PLL with default
phase setting
4–16
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–29. Cyclone Global Clock External I/O Timing Parameters
Notes (1), (2) (Part 2 of 2)
Conditions
Symbol
Parameter
tOUTCOPLL
Clock-to-output delay output or bidirectional pin using IOE
output register with global clock enhanced PLL with default
phase setting
CLOAD = 10 pF
Notes to Table 4–29:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for IOE pins using a 3.3-V LVTTL, 24-mA setting. Designers should use the Quartus II
software to verify the external timing for any pin.
Tables 4–30 through 4–31 show the external timing parameters on column
and row pins for EP1C3 devices.
Table 4–30. EP1C3 Column Pin Global Clock External I/O Timing
Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
4.073
2.306
Min
Max
4.682
2.651
Min
Max
5.295
2.998
tINSU
3.085
0.000
2.000
1.795
0.000
0.500
3.547
0.000
2.000
2.063
0.000
0.500
4.009
0.000
2.000
2.332
0.000
0.500
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL
Table 4–31. EP1C3 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
3.984
2.217
Min
Max
4.580
2.549
Min
Max
5.180
2.883
tINSU
3.157
0.000
2.000
1.867
0.000
0.500
3.630
0.000
2.000
2.146
0.000
0.500
4.103
0.000
2.000
2.426
0.000
0.500
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL
Altera Corporation
January 2007
4–17
Preliminary
Cyclone Device Handbook, Volume 1
Tables 4–32 through 4–33 show the external timing parameters on column
and row pins for EP1C4 devices.
Table 4–32. EP1C4 Column Pin Global Clock External I/O Timing
Parameters Note (1)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
3.937
2.080
Min
Max
4.526
2.392
Min
Max
5.119
2.705
tINSU
2.471
0.000
2.000
1.471
0.000
0.500
2.841
0.000
2.000
1.690
0.000
0.500
3.210
0.000
2.000
1.910
0.000
0.500
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL
Table 4–33. EP1C4 Row Pin Global Clock External I/O Timing
Parameters Note (1)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
2.600
0.000
2.000
1.300
0.000
Max
3.991
2.234
Min
2.990
0.000
2.000
1.494
0.000
0.500
Max
4.388
2.569
Min
3.379
0.000
2.000
1.689
0.000
0.500
Max
5.189
2.905
tINSU
ns
tINH
ns
ns
ns
ns
ns
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL 0.500
Note to Tables 4–32 and 4–33:
(1) Contact Altera Applications for EP1C4 device timing parameters.
4–18
Preliminary
Altera Corporation
January 2007
Timing Model
Tables 4–34 through 4–35 show the external timing parameters on column
and row pins for EP1C6 devices.
Table 4–34. EP1C6 Column Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
3.917
2.038
Min
Max
4.503
2.343
Min
Max
5.093
2.651
tINSU
2.691
0.000
2.000
1.513
0.000
0.500
3.094
0.000
2.000
1.739
0.000
0.500
3.496
0.000
2.000
1.964
0.000
0.500
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL
Table 4–35. EP1C6 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade -7 Speed Grade -8 Speed Grade
Symbol
Unit
Min
2.774
0.000
2.000
1.596
0.000
Max
3.817
1.938
Min
3.190
0.000
2.000
1.835
0.000
0.500
Max
4.388
2.228
Min
3.605
0.000
2.000
2.073
0.000
0.500
Max
4.963
2.521
tINSU
ns
tINH
ns
ns
ns
ns
ns
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL 0.500
Tables 4–36 through 4–37 show the external timing parameters on column
and row pins for EP1C12 devices.
Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing
Parameters (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade -8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.510
0.000
2.000
1.588
2.885
0.000
2.000
1.824
3.259
0.000
2.000
2.061
ns
ns
ns
ns
tINH
tOUTCO
tINSUPLL
3.798
4.367
4.940
Altera Corporation
January 2007
4–19
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing
Parameters (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade -8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tINHPLL
tOUTCOPLL
0.000
0.500
0.000
0.500
0.000
0.500
ns
ns
1.663
1.913
2.164
Table 4–37. EP1C12 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
3.671
1.536
Min
Max
4.221
1.767
Min
Max
4.774
1.998
tINSU
2.620
0.000
2.000
1.698
0.000
0.500
3.012
0.000
2.000
1.951
0.000
0.500
3.404
0.000
2.000
2.206
0.000
0.500
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL
Tables 4–38 through 4–39 show the external timing parameters on column
and row pins for EP1C20 devices.
Table 4–38. EP1C20 Column Pin Global Clock External I/O Timing
Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
3.724
1.667
Min
Max
4.282
1.917
Min
Max
4.843
2.169
tINSU
2.417
0.000
2.000
1.417
0.000
0.500
2.779
0.000
2.000
1.629
0.000
0.500
3.140
0.000
2.000
1.840
0.000
0.500
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tINSUPLL
tINHPLL
tOUTCOPLL
4–20
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–39. EP1C20 Row Pin Global Clock External I/O Timing Parameters
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Symbol
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.417
0.000
2.000
2.779
0.000
2.000
3.140
0.000
2.000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
3.724
3.645
3.645
4.282
4.191
4.191
4.843
4.740
4.740
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
1.417
0.000
0.500
1.629
0.000
0.500
1.840
0.000
0.500
1.667
1.588
1.588
1.917
1.826
1.826
2.169
2.066
2.066
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density.
Tables 4–40 through 4–45 show the adder delays associated with column
and row I/O pins for all packages. If an I/O standard is selected other
than LVTTL 4 mA with a fast slew rate, add the selected delay to the
external tCO and tSU I/O parameters shown in Tables 4–25 through
4–28.
Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 1 of 2)
-6 Speed Grade -7 Speed Grade -8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
0
0
0
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
0
0
0
27
31
35
182
278
−250
−250
−278
209
319
−288
−288
−320
236
361
−325
−325
−362
Altera Corporation
January 2007
4–21
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
SSTL-2 class II
LVDS
−278
−261
−320
−301
−362
−340
ps
ps
Table 4–41. Cyclone I/O Standard Row Pin Input Delay Adders
-6 Speed Grade -7 Speed Grade
-8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
0
0
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI (1)
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
0
0
0
27
31
35
182
278
0
209
319
0
236
361
0
−250
−250
−278
−278
−261
−288
−288
−320
−320
−301
−325
−325
−362
−362
−340
Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
0
0
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
4 mA
−489
−855
−993
0
−563
−984
−1,142
0
−636
8 mA
−1,112
−1,291
0
12 mA
4 mA
3.3-V LVTTL
8 mA
−347
−858
−819
−993
−400
−987
−942
−1,142
−452
12 mA
16 mA
24 mA
−1,116
−1,065
−1,291
4–22
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Min Max
Standard
Unit
Min
Max
Min
Max
2.5-V LVTTL
2 mA
329
−661
−655
−795
4
378
−761
−754
−915
4
427
−860
−852
−1034
5
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
1.8-V LVTTL
1.5-V LVTTL
−208
−208
2,288
608
292
−410
−811
−485
−758
−998
−240
−240
2,631
699
−271
−271
2,974
790
335
379
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
−472
−933
−558
−872
−1, 148
−533
−1,055
−631
−986
−1,298
Table 4–43. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 1 of 2)
-6 Speed Grade -7 Speed Grade -8 Speed Grade
Min Max Min Max Min Max
Standard
Unit
LVCMOS
2 mA
0
0
0
ps
4 mA
−489
−855
−993
0
−563
−984
−1,142
0
−636
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
−1,112
−1,291
0
12 mA
4 mA
3.3-V LVTTL
8 mA
−347
-858
−819
−993
329
−661
−655
−795
−400
−987
−942
−1,142
378
−452
12 mA
16 mA
24 mA
2 mA
−1,116
−1,065
−1,291
427
2.5-V LVTTL
8 mA
−761
−754
−915
−860
12 mA
16 mA
−852
−1,034
Altera Corporation
January 2007
4–23
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–43. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Standard
Unit
Min
Max
Min
Max
Min
Max
1.8-V LVTTL
2 mA
1,290
4
1,483
4
1,677
5
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
12 mA
2 mA
4 mA
8 mA
−208
2,288
608
−240
2,631
699
−271
2,974
790
1.5-V LVTTL
292
335
379
3.3-V PCI (1)
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
−877
−410
−811
−485
−758
−998
−1,009
−472
−933
−558
−872
−1,148
−1,141
−533
−1,055
−631
−986
−1,298
Table 4–44. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
1,800
1,311
945
2,070
1,507
1,086
928
2,340
1,704
1,228
1,049
2,380
1,928
1,264
1,315
1,089
3,570
2,283
2,291
2,109
7,157
5,485
5,209
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
4 mA
8 mA
12 mA
4 mA
807
3.3-V LVTTL
1,831
1,484
973
2,105
1,705
1,118
1,163
963
8 mA
12 mA
16 mA
24 mA
2 mA
1,012
838
2.5-V LVTTL
1.8-V LVTTL
2,747
1,757
1,763
1,623
5,506
4,220
4,008
3,158
2,019
2,026
1,865
6,331
4,852
4,608
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
4–24
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–44. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
1.5-V LVTTL
2 mA
6,789
5,109
4,793
1,390
989
7,807
5,875
5,511
1,598
1,137
2,259
1,945
922
8,825
6,641
6,230
1,807
1,285
2,554
2,199
1,042
ps
ps
ps
ps
ps
ps
ps
ps
4 mA
8 mA
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
1,965
1,692
802
Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 1 of 2)
-6 Speed Grade -7 Speed Grade -8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
1,800
1,311
945
2,070
1,507
1,086
928
2,340
1,704
1,228
1,049
2,380
1,928
1,264
1,315
1,089
3,570
2,283
2,291
2,109
7,157
5,485
5,209
8,825
6,641
6,230
1,199
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
4 mA
8 mA
12 mA
4 mA
8 mA
12 mA
16 mA
24 mA
2 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
807
3.3-V LVTTL
1,831
1,484
973
2,105
1,705
1,118
1,163
963
1,012
838
2.5-V LVTTL
2,747
1,757
1,763
1,623
5,506
4,220
4,008
6,789
5,109
4,793
923
3,158
2,019
2,026
1,865
6,331
4,852
4,608
7,807
5,875
5,511
1,061
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
Altera Corporation
January 2007
4–25
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part 2 of 2)
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
SSTL-3 class I
1,390
989
1,598
1,137
2,259
1,945
922
1,807
1,285
2,554
2,199
1,042
ps
ps
ps
ps
ps
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
1,965
1,692
802
Note to Tables 4–40 through 4–45:
(1) EP1C3 devices do not support the PCI I/O standard.
Tables 4–46 through 4–47 show the adder delays for the IOE
programmable delays. These delays are controlled with the Quartus II
software options listed in the Parameter column.
Table 4–46. Cyclone IOE Programmable Delays on Column Pins
-6 Speed Grade -7 Speed Grade
-8 Speed Grade
Parameter
Setting
Unit
Min
Max
Min
Max
Min
Max
Decrease input delay to Off
internal cells
155
2,122
2,639
3,057
155
178
2,543
3,034
3,515
178
201
2,875
3,430
3,974
201
ps
ps
ps
ps
ps
ps
ps
ps
ps
Small
Medium
Large
On
Decrease input delay to Off
input register
0
0
0
On
3,057
0
3,515
0
3,974
0
Increase delay to output Off
pin
On
552
634
717
4–26
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–47. Cyclone IOE Programmable Delays on Row Pins
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Parameter
Setting
Unit
Min
Max
Min
Max
Min
Max
Decrease input delay to
internal cells
Off
154
2,212
2,639
3,057
154
177
2,543
3,034
3,515
177
200
2,875
3,430
3,974
200
ps
ps
ps
ps
ps
ps
ps
ps
ps
Small
Medium
Large
On
Decrease input delay to input Off
register
0
0
0
On
3,057
0
3,515
0
3,974
0
Increase delay to output pin Off
On
556
639
722
Note to Table 4–47:
(1) EPC1C3 devices do not support the PCI I/O standard
Maximum Input & Output Clock Rates
Tables 4–48 and 4–49 show the maximum input clock rate for column and
row pins in Cyclone devices.
Table 4–48. Cyclone Maximum Input Clock Rate for Column Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
I/O Standard
Unit
LVTTL
2.5 V
1.8 V
1.5 V
464
392
387
387
405
405
414
464
473
567
428
302
311
320
374
356
365
428
432
549
387
207
252
243
333
293
302
396
396
531
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Altera Corporation
January 2007
4–27
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–49. Cyclone Maximum Input Clock Rate for Row Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
I/O Standard
Unit
LVTTL
464
392
387
387
405
405
414
464
473
464
567
428
302
311
320
374
356
365
428
432
428
549
387
207
252
243
333
293
302
396
396
387
531
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
3.3-V PCI (1)
LVDS
Note to Tables 4–48 through 4–49:
(1) EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
Tables 4–50 and 4–51 show the maximum output clock rate for column
and row pins in Cyclone devices.
Table 4–50. Cyclone Maximum Output Clock Rate for Column Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
I/O Standard
Unit
LVTTL
2.5 V
1.8 V
1.5 V
304
220
213
166
304
100
100
134
134
320
304
220
213
166
304
100
100
134
134
320
304
220
213
166
304
100
100
134
134
275
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Note to Table 4–50:
(1) EP1C3 devices do not support the PCI I/O standard.
4–28
Preliminary
Altera Corporation
January 2007
Timing Model
Table 4–51. Cyclone Maximum Output Clock Rate for Row Pins
-6 Speed
Grade
-7 Speed
Grade
-8 Speed
Grade
I/O Standard
Unit
LVTTL
2.5 V
1.8 V
1.5 V
296
381
286
219
367
169
160
160
131
66
285
366
277
208
356
166
151
151
123
66
273
349
267
195
343
162
146
142
115
66
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
3.3-V PCI (1)
LVDS
320
303
275
Note to Tables 4–50 through 4–51:
(1) EP1C3 devices do not support the PCI I/O standard. These parameters are only
available on row I/O pins.
PLL Timing
Table 4–52 describes the Cyclone FPGA PLL specifications.
Table 4–52. Cyclone PLL Specifications (Part 1 of 2)
Symbol
Parameter
Min
Max
Unit
fIN
Input frequency (-6 speed
15.625
464
MHz
grade)
Input frequency (-7 speed
grade)
15.625
15.625
40.00
428
387
60
MHz
MHz
Input frequency (-8 speed
grade)
f
t
IN DUTY
IN JITTER
Input clock duty cycle
Input clock period jitter
%
ps
200
f
OUT_EXT (external PLL
PLL output frequency
(-6 speed grade)
15.625
15.625
15.625
320
320
275
MHz
MHz
MHz
clock output)
PLL output frequency
(-7 speed grade)
PLL output frequency
(-8 speed grade)
Altera Corporation
January 2007
4–29
Preliminary
Cyclone Device Handbook, Volume 1
Table 4–52. Cyclone PLL Specifications (Part 2 of 2)
Symbol
Parameter
Min
Max
Unit
fOUT (to global clock)
PLL output frequency
15.625
405
MHz
(-6 speed grade)
PLL output frequency
(-7 speed grade)
15.625
15.625
45.00
320
275
MHz
MHz
%
PLL output frequency
(-8 speed grade)
t
OUT DUTY
Duty cycle for external clock
55
output (when set to 50%)
tJITTER (1)
tLOCK (3)
fVCO
Period jitter for external clock
output
300 (2)
100
ps
Time required to lock from end
of device configuration
10.00
μs
PLL internal VCO operating
range
500.00
1,000
MHz
-
Minimum areset time
Counter values
10
1
ns
N, G0, G1, E
32
integer
Notes to Table 4–52:
(1) The tJITTER specification for the PLL[2..1]_OUTpins are dependent on the I/O pins in its VCCIO bank, how many
of them are switching outputs, how much they toggle, and whether or not they use programmable current strength
or slow slew rate.
(2) fOUT ≥ 100 MHz. When the PLL external clock output frequency (fOUT) is smaller than 100 MHz, the jitter
specification is 60 mUI.
(3) fIN/N must be greater than 200 MHz to ensure correct lock detect circuit operation below –20 C. Otherwise, the PLL
operates with the specified parameters under the specified conditions.
4–30
Preliminary
Altera Corporation
January 2007
Document Revision History
Table 4–53 shows the revision history for this document.
Document
Revision History
Table 4–53. Document Revision History
Date &
Document
Version
Changes Made
Summary of Changes
January 2007
v1.6
●
●
Added document revision history.
Added new row for VCCA details in Table 4–1.
●
●
Updated RCONF information in Table 4–3.
Added new Note (12) on voltage overdrive information to
Table 4–7 and Table 4–8.
●
●
Updated Note (9) on RCONF information to Table 4–3.
Updated information in “External I/O Delay Parameters”
section.
●
Updated speed grade information in Table 4–46 and
Table 4–47.
●
Updated LVDS information in Table 4–51.
August 2005
v1.5
Minor updates.
February 2005
v1.4
●
Updated information on Undershoot voltage. Updated Table
4-2.
●
●
Updated Table 4-3.
Updated the undershoot voltage from 0.5 V to 2.0 V in Note 3
of Table 4-16.
●
●
Updated Table 4-17.
January 2004
v.1.3
Added extended-temperature grade device information.
Updated Table 4-2.
●
Updated ICC0 information in Table 4-3.
October 2003
v.1.2
●
●
Added clock tree information in Table 4-19.
Finalized timing information for EP1C3 and EP1C12 devices.
Updated timing information in Tables 4-25 through 4-26 and
Tables 4-30 through 4-51.
●
Updated PLL specifications in Table 4-52.
July 2003 v1.1
Updated timing information. Timing finalized for EP1C6 and
EP1C20 devices. Updated performance information. Added PLL
Timing section.
May 2003 v1.0 Added document to Cyclone Device Handbook.
Altera Corporation
January 2007
4–31
Preliminary
Cyclone Device Handbook, Volume 1
4–32
Preliminary
Altera Corporation
January 2007
5. Reference & Ordering
Information
C51005-1.3
Cyclone® devices are supported by the Altera® Quartus® II design
software, which provides a comprehensive environment for system-on-a-
programmable-chip (SOPC) design. The Quartus II software includes
HDL and schematic design entry, compilation and logic synthesis, full
simulation and advanced timing analysis, SignalTap® II logic analysis,
and device configuration. Refer to the Design Software Selector Guide for
more details on the Quartus II software features.
Software
The Quartus II software supports the Windows 2000/NT/98, Sun Solaris,
Linux Red Hat v7.1 and HP-UX operating systems. It also supports
seamless integration with industry-leading EDA tools through the
NativeLink® interface.
Device pin-outs for Cyclone devices are available on the Altera web site
(www.altera.com) and in the Cyclone FPGA Device Handbook.
Device Pin-Outs
Figure 5–1 describes the ordering codes for Cyclone devices. For more
information on a specific package, refer to Chapter 15, Package
Information for Cyclone Devices.
Ordering
Information
Figure 5–1. Cyclone Device Packaging Ordering Information
EP1C
20
F
400
C
7
ES
Family Signature
Optional Suffix
EP1C: Cyclone
Indicates specific device options or
shipment method.
ES: Engineering sample
Device Type
3
4
Speed Grade
6, 7, or 8 , with 6 being the fastest
6
12
20
Operating Temperature
Package Type
C: Commercial temperature (t = 0
J
˚
C to 85
C to 100˚
˚
C)
C)
I: Industrial temperature (t = -40
˚
J
T: Thin quad flat pack (TQFP)
Pin Count
Number of pins for a particular package
Q: Plastic quad flat pack (PQFP)
F: FineLine BGA
Altera Corporation
January 2007
5–1
Preliminary
Cyclone Device Handbook, Volume 1
Table 5–1 shows the revision history for this document.
Document
Revision History
Table 5–1. Document Revision History
Date &
Document
Version
Changes Made
Summary of Changes
January 2007
v1.3
Added document revision history.
August 2005
v1.2
Minor updates.
February 2005
v1.1
Updated Figure 5-1.
May 2003 v1.0 Added document to Cyclone Device Handbook.
5–2
Preliminary
Altera Corporation
January 2007
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