EP3SL200H780C3 [ALTERA]
Field Programmable Gate Array, 717MHz, 200000-Cell, CMOS, PBGA780, HBGA-780;型号: | EP3SL200H780C3 |
厂家: | ALTERA CORPORATION |
描述: | Field Programmable Gate Array, 717MHz, 200000-Cell, CMOS, PBGA780, HBGA-780 时钟 LTE 栅 可编程逻辑 |
文件: | 总331页 (文件大小:1711K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1. Stratix III Device Data Sheet: DC and
Switching Characteristics
SIII52001-2.1
Electrical Characteristics
Operating Conditions
®
When Stratix III devices are implemented in a system, they are rated according to a
set of defined parameters. To maintain the highest possible performance and
reliability of Stratix III devices, system designers must consider the operating
requirements discussed in this chapter. Stratix III devices are offered in both
commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3,
–4 and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speed
grades.
1
In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades; commercial with “C” prefix and industrial with “I” prefix.
Commercial devices are therefore indicated as C2, C3, C4, and C4L per respective
speed grades. Industrial devices are indicated as I3, I4, and I4L.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Stratix III
devices. The values are based on experiments conducted with the device and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Conditions beyond those
listed in Table 1–1 may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods may have adverse
effects on the device.
Table 1–1. Stratix III Device Absolute Maximum Ratings (Note 1) (Part 1 of 2)
Symbol
Parameter
Selectable core voltage power supply
I/O registers power supply
Minimum
-0.5
Maximum
1.65
1.65
1.65
3.75
3.75
3.9
Unit
V
VCCL
VCC
-0.5
V
VCCD_PLL
VCCA_PLL
VCCPT
VCCPGM
VCCPD
VCCIO
PLL digital power supply
-0.5
V
PLL analog power supply
-0.5
V
Programmable power technology power supply
Configuration pins power supply
I/O pre-driver power supply
I/O power supply
-0.5
V
-0.5
V
-0.5
3.9
V
-0.5
3.9
V
Differential clock input power supply (top and bottom I/O
banks only)
VCC_CLKIN
-0.5
3.75
V
Battery back-up power supply for design security volatile
key register
VCCBAT
VI
-0.5
-0.5
3.75
4.0
V
V
DC Input voltage
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–2
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–1. Stratix III Device Absolute Maximum Ratings (Note 1) (Part 2 of 2)
Symbol Parameter
Operating junction temperature
Minimum
-55
Maximum
125
Unit
°C
TJ
IOUT
TSTG
DC output current, per pin
-25
40
mA
°C
Storage temperature (No bias)
-65
150
Note to Table 1–1:
(1) Supply voltage specifications apply to voltage readings taken at the device pins, not the power supply.
Maximum Allowed Overshoot/Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 1–2 and
undershoot to -2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
Table 1–2 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage over the lifetime of the device. The maximum
allowed overshoot duration is specified as percentage of high-time over the lifetime of
the device.
A DC signal is equivalent to 100 % duty cycle. For example, a signal that overshoot to
4.2 V can only be at 4.2 V for 15.8 % over the lifetime of the device; for device lifetime
of 10 years, this amounts to 15.8/10ths of a year. Figure 1–1 shows the way to
determine the overshoot duration.
Figure 1–1. Overshoot Duration
4.1 V
3.15 V
3.0 V
ΔT
T
1
Figure 1–1 shows the methodology to determine the overshoot duration. In the
example shown in Figure 1–1, the overshoot voltage is shown in red and is present at
the Stratix III pin, up to 4.1 V. From Table 1–2, for an overshoot of up to 4.1 V, the
percentage of high time for overshoot > 3.15 V can be as high as 46% over an 11.4-year
period. The percentage of high time is calculated as (delta T/T) * 100. This 11.4-year
period assumes the device is always turned on with 100% I/O toggle rate and 50%
duty cycle signal. For lower I/O toggle rates and situations where the device is in an
idle state, lifetimes are increased.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–3
Electrical Characteristics
Table 1–2. Maximum Allowed Overshoot During Transitions
Overshoot duration as % of
high time
Symbol
Parameter
Condition
Unit
4
100.000
79.330
46.270
27.030
15.800
9.240
5.410
3.160
1.850
1.080
0.630
0.370
0.220
0.130
0.074
0.043
0.025
0.015
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
4.05
4.1
4.15
4.2
4.25
4.3
4.35
4.4
Vi (AC)
AC Input Voltage (1)
4.45
4.5
4.55
4.6
4.65
4.7
4.75
4.8
4.85
Note to Table 1–2:
(1) This input voltage is regardless of the VCCIO supply which is used to power up the input buffer.
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for
Stratix III devices. The steady-state voltage and current values expected from
Stratix III devices are provided in Table 1–3. All supplies are required to
monotonically reach their full-rail values within tRAMP
.
Table 1–3. Stratix III Device Recommended Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum Unit
Selectable core voltage power supply for
internal logic and input buffers
—
1.05
1.1
1.15
0.94
V
V
VCCL
Selectable core voltage power supply for
internal logic and input buffers
—
0.86
0.9
VCC
I/O registers power supply
PLL digital power supply
PLL analog power supply
—
—
—
1.05
1.05
1.1
1.1
2.5
1.15
1.15
V
V
V
VCCD_PLL
VCCA_PLL
2.375
2.625
Power supply for the programmable power
technology
VCCPT
—
2.375
2.5
2.625
V
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–4
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–3. Stratix III Device Recommended Operating Conditions (Part 2 of 2)
Symbol
Parameter
Configuration pins power supply, 3.3 V
Configuration pins power supply, 3.0 V
Configuration pins power supply, 2.5 V
Configuration pins power supply, 1.8 V
I/O pre-driver power supply, 3.3 V
I/O pre-driver power supply, 3.0 V
I/O pre-driver power supply, 2.5 V
I/O power supply, 3.3 V
Conditions
Minimum
3.135
2.85
Typical
3.3
3
Maximum Unit
—
—
—
—
—
—
—
—
—
—
—
—
—
3.465
3.15
V
V
V
V
V
V
V
V
V
V
V
V
V
VCCPGM
2.375
1.71
2.5
1.8
3.3
3
2.625
1.89
3.135
2.85
3.465
3.15
VCCPD (1)
2.375
3.135
2.85
2.5
3.3
3
2.625
3.465
3.15
I/O power supply, 3.0 V
I/O power supply, 2.5 V
2.375
1.71
2.5
1.8
1.5
1.2
2.625
1.89
VCCIO
I/O power supply, 1.8 V
I/O power supply, 1.5 V
1.425
1.14
1.575
1.26
I/O power supply, 1.2 V
2.625
Differential clock input power supply (top and
bottom I/O banks only)
VCC_CLKIN
—
—
2.375
1.0
2.5
—
V
V
Battery back-up power supply for design
security volatile key register
VCCBAT (3)
3.3
VI
DC Input voltage
Output voltage
—
—
-0.3
0
—
—
3.6
V
V
VO
VCCIO
For commercial
use
0
—
—
—
—
—
—
85
100
°C
°C
—
—
—
—
TJ
Operating junction temperature
For industrial
-40
use(2)
Normal POR
(PORSEL=0)
50 µs
50 µs
50 µs
50 µs
5 ms
5 ms
100 ms
12 ms
Power Supply Ramptime (For VCCPT
)
Fast POR
(PORSEL=1)
tRAMP
Normal POR
(PORSEL=0)
Power Supply Ramptime (For all power
supplies except VCCPT
)
Fast POR
(PORSEL=1)
Notes to Table 1–3:
(1) VCCPD is 2.5 V, 3.0 V, or 3.3 V. For a 3.3-V I/O standard, VCCPD=3.3 V. For a 3.0-V I/O standard, VCCPD = 3.0 V. For a 2.5 V or lower I/O standard,
CCPD = 2.5 V.
V
(2) For the EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, the industrial junction temperature range is from 0° C to
100° C, regardless of supply voltage.
(3) Altera recommends a 3.0-V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile
security key, you may connect the VCCBAT to either GND or a 3.0-V power supply.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–5
Electrical Characteristics
DC Characteristics
This section lists the input pin capacitances, on-chip termination tolerance, and
hot- socketing specifications.
Supply Current
Standby current is the current the device draws after the device is configured with no
inputs/outputs toggling and no activity in the device. Since these currents vary
largely with the resources used, use the Excel-based Early Power Estimator (EPE) to
get supply current estimates for your design.
Table 1–4 lists supply current specifications for VCC_CLKIN and VCCPGM. Use the EPE to get
supply current estimates for remaining power supplies.
Table 1–4. Supply Current Specifications for VCC_CLKIN and VCCPGM
Symbol
Parameter
VCC_CLKIN current specifications
VCCPGM current specifications
Min
0
Max
250
250
Unit
mA
mA
ICLKIN
IPGM
0
I/O Pin Leakage Current
Table 1–5 defines Stratix III I/O Pin leakage current specifications.
Table 1–5. Stratix III I/O Pin Leakage Current (Note 1), (2)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
II
Input Pin Leakage Current
VI = VCCIOMAX to 0 V
-10
—
10
A
Tri-stated I/O Pin Leakage
Current
IOZ
VO = VCCIOMAX to 0 V
-10
—
10
A
Notes to Table 1–5:
(1) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO
settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V).
(2) 10-A I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be
observed when the diode is on.
Bus Hold Specifications
Table 1–7 shows the Stratix III device family bus hold specifications.
Table 1–6. Bus Hold Parameters (Part 1 of 2)
VCCIO
Parameter
Symbol
Conditions
Unit
1.2V
1.5V
1.8V
2.5V
3.0V/3.3V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Low sustaining
current
VIN>VIL
(maximum)
ISUSL
ISUSH
IODL
22.5
-22.5
—
—
25.0
-25.0
—
—
30.0
-30.0
—
—
50.0
-50.0
—
—
70.0
—
—
µA
µA
µA
High sustaining
current
VIN<VIH
(minimum)
—
—
—
—
-70.0
—
Low overdrive
current
0V<VIN<VCCIO
120
160
200
300
500
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–6
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–6. Bus Hold Parameters (Part 2 of 2)
VCCIO
Parameter
Symbol
Conditions
Unit
1.2V
1.5V
1.8V
2.5V
3.0V/3.3V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
-500
High overdrive
current
IODH
0V<VIN<VCCIO
—
—
-120
—
-160
—
-200
—
-300
—
µA
V
Bus-hold trip
point
VTRIP
0.45 0.95 0.50
1.00 0.68 1.07 0.70 1.70 0.80 2.00
On-Chip Termination (OCT) Specifications
If OCT calibration is enabled, calibration is automatically performed at power-up for
I/Os connected to the calibration block. Table 1–7 lists the Stratix III OCT calibration
block accuracy specifications.
Table 1–7. Stratix III On-Chip Termination Calibration Accuracy Specifications (Note 1)
Calibration
Accuracy
Symbol
Description
Conditions
Unit
C3, C4,
C2
I3
I4
25- RS (2)
3.3/3.0/2.5/1.8/1.5/1.2
Internal series termination with
calibration (25- setting)
VCCIO
=
8
8
8
8
%
%
%
3.3/3.0/2.5/1.8/1.5/1.2 V
50- RS
3.3/3.0/2.5/1.8/1.5/1.2
Internal series termination with
calibration (50- setting)
VCCIO =
8
8
3.3/3.0/2.5/1.8/1.5/1.2 V
Internal parallel termination with
calibration (50- setting)
50- RT 2.5/1.8/1.5/1.2
VCCIO = 2.5/1.8/1.5/1.2 V
10
10
10
Expanded range for internal series VCCIO
=
20-RS to 60-RS
3.3/3.0/2.5/1.8/1.5/1.2
termination with calibration
(Between 20- to 60-setting)
3.3/3.0/2.5/1.8/1.5/1.2 V
(3)
10
10
10
10
10
10
%
%
Internal left shift series termination
with calibration (25- RS _left_shift
setting)
VCCIO
=
25- RS _left_shift
3.3/3.0/2.5/1.8/1.5/1.2 V
Internal series termination with
calibration
ROCT_CAL
(4)
Internal differential termination for
LVDS technology (100-setting)
RD
VCCIO = 2.5 V
-15 to 35
%
Notes to Table 1–7:
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25- RS not supported for 1.5-V and 1.2-V in Row I/O.
(3) 1.5-V and 1.2-V only supports 40- to 60- expanded range.
(4) For resistance tolerance after power-up calibration, refer to Equation 1–1 and Table 1–9.
The accuracy listed in Table 1–7 is valid at the time of calibration. If the voltage or
temperature changes, the termination resistance value varies. Table 1–8 lists the
resistance tolerance for Stratix III on chip termination.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–7
Electrical Characteristics
Table 1–8. Stratix III On-Chip Termination Resistance Tolerance Specification
Resistance
Tolerance
Symbol
Description
Conditions
Unit
C3, C4,
C2
I3
I4
Internal series termination without
calibration
ROCT_UNCAL
—
Internal series termination without
calibration (25- setting)
25- RS 3.3/3.0/2.5
25- RS 1.8/1.5
25- RS 1.2
VCCIO = 3.3/3.0/2.5 V
VCCIO = 1.8/1.5 V
VCCIO = 1.2 V
30
30
35
30
30
35
40
50
60
40
50
60
40
50
60
40
50
60
%
%
%
%
%
%
Internal series termination without
calibration (25- setting)
Internal series termination without
calibration (25- setting)
Internal series termination without
calibration (50- setting)
50- RS 3.3/3.0/2.5
50- RS 1.8/1.5
50- RS 1.2
VCCIO = 3.3/3.0/2.5 V
VCCIO = 1.8/1.5 V
VCCIO = 1.2 V
Internal series termination without
calibration (50- setting)
Internal series termination without
calibration (50- setting)
Table 1–9 lists OCT variation with temperature and voltage after power-up
calibration. Use Table 1–9 and Equation 1–1 to determine OCT variation without re-
calibration.
Equation 1–1. OCT Variation Without Re-Calibration (Note 1)
dR
dT
dR
dV
------
------
ROCT = R
1 +
T
V
SCAL
Notes to Equation 1–1:
(1) ROCT value calculated from Equation 1–1 shows the range of OCT resistance with the variation of temperature and
VCCIO
.
(2) RSCAL is the OCT resistance value at power-up.
(3) T is the variation of temperature with respect to the temperature at power-up.
(4) V is the variation of voltage with respect to the VCCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 1–9. On-Chip Termination Variation after Power-up Calibration (Part 1 of 2) (Note 1)
Commercial
Typical
Symbol
Description
V
CCIO (V)
Unit
3
0.029
0.036
0.065
0.104
0.177
%/mV
%/mV
%/mV
%/mV
%/mV
2.5
1.8
1.5
1.2
dR/dV
OCT variation with voltage without re-calibration
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–8
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–9. On-Chip Termination Variation after Power-up Calibration (Part 2 of 2) (Note 1)
Commercial
Typical
Symbol
Description
V
CCIO (V)
Unit
3
0.294
0.301
0.355
0.344
0.348
%/°C
%/°C
%/°C
%/°C
%/°C
2.5
1.8
1.5
1.2
dR/dT
OCT variation with temperature without re-calibration
Note to Table 1–9:
(1) Valid for VCCIO range of 5% and temperature range of 0° to 85° C.
Pin Capacitance
Table 1–10 shows the Stratix III device family pin capacitance.
Table 1–10. Stratix III Device Capacitance
Symbol
CIOTB
Parameter
Typical
Unit
pF
Input capacitance on top/bottom I/O pins
Input capacitance on left/right I/O pins
4
4
CIOLR
pF
Input capacitance on top/bottom non-
dedicated clock input pins
CCLKTB
CCLKLR
COUTFB
4
4
5
2
pF
pF
pF
pF
Input capacitance on left/right non-dedicated
clock input pins
Input capacitance on dual-purpose clock
output/feedback pins
C
CLK1, CCLK3, CCLK8, and Input capacitance for dedicated clock input
CCLK10 pins
Hot-Socketing
Table 1–11 lists the hot-socketing specifications for Stratix III devices.
Table 1–11. Stratix III Hot-Socketing Specifications
Symbol
IIOPIN(DC)
IIOPIN(AC)
Parameter
Maximum
DC current per I/O pin
AC current per I/O pin
300 A
8 mA for 10 ns
Internal Weak Pull-Up Resistor
Table 1–12 lists the weak pull-up resistor values for Stratix III devices.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–9
Electrical Characteristics
Table 1–12. Stratix III Internal Weak Pull-Up Resistor (Note 1), (3)
Symbol
Parameter
Conditions
Min
—
—
—
—
—
—
Typ
25
25
25
25
25
25
Max
—
Unit
VCCIO = 3.3 V 5% (2)
VCCIO = 3.0 V 5% (2)
k
k
k
k
k
k
Value of I/O pin pull-up
resistor before and
during configuration, as
well as user mode if the
programmable pull-up
resistor option is
—
V
V
CCIO = 2.5 V 5% (2)
CCIO = 1.8 V 5% (2)
—
RPU
—
VCCIO = 1.5 V 5% (2)
CCIO = 1.2 V 5% (2)
—
enabled
V
—
Notes to Table 1–12:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pin.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO
.
(3) The internal weak pull-down feature is only available for JTAG TCKpin. The typical value for this internal weak
pull-down resistor is around 25k .
I/O Standard Specifications
The following tables list input voltage sensitivities (VIH and VIL), output voltages (VOH
and VOL), and current drive characteristics (IOH and IOL) for all I/O standards
supported by Stratix III devices. Table 1–13 through Table 1–18 show the Stratix III
device family I/O standard specifications. Refer to “Glossary” for explanation of
terms used in the Table 1–14 through Table 1–18. VOL and VOH values are valid at the
corresponding IOL and IOH, respectively.
Table 1–13. Single-Ended I/O Standards Specifications
VCCIO (V)
Typ Max Min
VIL (V)
VIH (V)
VOL (V)
Max
VOH (V)
IOL
IOH
I/O Standard
(mA) (mA)
Min
3.135
2.85
Max
Min
Max
Min
2.4
3.3-V LVTTL
3.0-V LVTTL
3.3
3
3.465 -0.3
3.15 -0.3
3.465 -0.3
3.15 -0.3
0.8
0.8
0.8
0.8
1.7
1.7
1.7
1.7
3.6
3.6
3.6
3.6
0.4
0.4
0.2
0.2
2
-2
-2
2.4
2
3.3-V LVCMOS 3.135
3.0-V LVCMOS 2.85
3.3
3
VCCIO - 0.2
0.1
0.1
-0.1
-0.1
VCCIO - 0.2
2.5-V LVTTL/
2.375
2.5
1.8
1.5
1.2
2.625 -0.3
1.89 -0.3
0.7
1.7
3.6
0.4
2
1
2
2
2
-1
-2
-2
-2
LVCMOS
1.8-V LVTTL /
1.71
0.45
VCCIO - 0.45
0.35 * VCCIO 0.65 * VCCIO
VCCIO + 0.3
LVCMOS
1.5-V LVTTL/
1.425
1.575 -0.3 0.35 * VCCIO 0.65 * VCCIO
1.26 -0.3
VCCIO + 0.3 0.25 * VCCIO 0.75 * VCCIO
LVCMOS
1.2-V LVTTL /
1.14
0.25 * VCCIO 0.75 * VCCIO
0.35 * VCCIO 0.65 * VCCIO
VCCIO + 0.3
LVCMOS
3.0-V PCI
2.85
2.85
3
3
3.15
3.15
—
—
3.6
—
0.1 * VCCIO
0.1 * VCCIO
0.9 * VCCIO
0.9 * VCCIO
1.5
1.5
-0.5
-0.5
0.3 * VCCIO
0.5 * VCCIO
0.5 * VCCIO
3.0-V PCI-X
0.35 * VCCIO
Refer to the figure in “Single-Ended Voltage Referenced I/O Standard” in the
“Glossary” for voltage referenced receiver input waveform and explanation of terms
used in Table 1–14.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–10
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–14. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications
VCCIO (V)
Typ
VREF (V)
Typ
VTT (V)
Typ
I/O
Standard
Min
Max
Min
Max
Min
Max
SSTL-2
CLASS I, II
2.375 2.5
1.71 1.8
1.425 1.5
1.71 1.8
1.425 1.5
1.14 1.2
2.625
0.49 * VCCIO
0.5 * VCCIO
0.9
0.51 * VCCIO
VREF - 0.04
VREF
VREF
VREF + 0.04
SSTL-18
CLASS I, II
1.89
0.833
0.47 * VCCIO
0.85
0.969
0.53 * VCCIO
0.95
VREF - 0.04
0.47 * VCCIO
—
VREF + 0.04
0.53 * VCCIO
—
SSTL-15
CLASS I, II
1.575
1.89
0.5 * VCCIO
0.9
VREF
HSTL-18
CLASS I, II
VCCIO/2
VCCIO/2
VCCIO/2
HSTL-15
CLASS I, II
1.575
1.26
0.68
0.75
0.9
—
—
HSTL-12
CLASS I, II
0.47 * VCCIO
0.5 * VCCIO
0.53 * VCCIO
—
—
Table 1–15. Single-Ended SSTL and HSTL I/O Standards Signal Specifications (Note 1)
V
IL(DC) (V)
Max
VIH(DC) (V)
VIL(AC) (V)
Max
VIH(AC) (V)
Min
VOL (V)
Max
VOH (V)
Min
I/O
Standard
IOL
IOH
(mA) (mA)
Min
Min
Max
SSTL-2
CLASS I
-0.3
VREF - 0.15
VREF - 0.15
VREF +0.15
VREF +0.15
VCCIO + 0.3
VREF - 0.31 VREF + 0.31 VTT - 0.57 VTT + 0.57 8.1
-8.1
SSTL-2
CLASS II
-0.3
-0.3
-0.3
—
VCCIO + 0.3
VCCIO + 0.3
VCCIO + 0.3
—
VREF - 0.31 VREF + 0.31 VTT - 0.76 VTT + 0.76 16.2 -16.2
VTT -
0.475
VTT +
0.475
SSTL-18
CLASS I
VREF -0.125 VREF +0.125
VREF -0.125 VREF +0.125
VREF -0.25
VREF -0.25
VREF + 0.25
VREF + 0.25
6.7
-6.7
SSTL-18
CLASS II
0.28
0.2 * VCCIO
0.2 * VCCIO
0.4
VCCIO - 0.28 13.4 -13.4
SSTL-15
CLASS I
VREF -0.1
VREF -0.1
VREF -0.1
VREF -0.1
VREF -0.1
VREF -0.1
VREF -0.08
VREF -0.08
VREF +0.1
VREF +0.1
VREF +0.1
VREF +0.1
VREF +0.1
VREF +0.1
VREF +0.08
VREF +0.08
VREF -0.175 VREF + 0.175
VREF -0.175 VREF + 0.175
0.8 * VCCIO
0.8 * VCCIO
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
VCCIO - 0.4
0.75 * VCCIO
0.75 * VCCIO
8
16
8
-8
-16
-8
SSTL-15
CLASS II
—
—
HSTL-18
CLASS I
—
—
VREF -0.2
VREF -0.2
VREF -0.2
VREF -0.2
VREF -0.15
VREF -0.15
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.15
VREF + 0.15
HSTL-18
CLASS II
—
—
0.4
16
8
-16
-8
HSTL-15
CLASS I
—
—
0.4
HSTL-15
CLASS II
—
—
0.4
16
8
-16
-8
HSTL-12
CLASS I
-0.15
-0.15
VCCIO + 0.15
VCCIO + 0.15
0.25* VCCIO
0.25* VCCIO
HSTL-12
CLASS II
16
-16
Note to Table 1–15:
(1) Use current strength settings that are equal or larger than the IOL/IOH values listed to meet the VOL/VOH specifications for each line. OCT or lower
current strengths may provide better signal integrity and lower power.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–11
Electrical Characteristics
Refer to the figures for “Differential I/O Standards” in “Glossary” for receiver input
and transmitter output waveforms, and for all differential I/O standards (LVDS,
mini-LVDS, RSDS). VCC_CLKIN is the power supply for differential column clock input
pins. VCCPD is the power supply for row I/Os and all other column I/Os.
Table 1–16. Differential SSTL I/O Standard Specifications
V
CCIO (V)
VSWING (DC) (V)
VX (AC) (V)
VSWING(AC) (V)
VOX (AC) (V)
Typ
I/O
Standard
Min Typ Max
Min Max
Min
Typ
Max
VCCIO/2
Min
Max
Min
Max
VCCIO
VCCIO/2
- 0.2
VCCIO/2
VCCIO
VCCIO/2
VCCIO/2+
0.15
SSTL-2
CLASS I, II
2.375 2.5 2.625 0.3
—
0.62
—
+ 0.6
VCCIO
+ 0.2
+ 0.6 - 0.15
VCCIO/2
VCCIO
VCCIO/2
VCCIO/2
+0.125
SSTL-18
CLASS I, II
1.71 1.8 1.89 0.25
1.425 1.5 1.575 0.2
—
0.5
—
+ 0.6 -0.175
+ 0.175
+ 0.6 -0.125
SSTL-15
CLASS I, II
—
—
VCCIO/2
—
0.35
—
—
VCCIO/2
—
Table 1–17. Differential HSTL I/O Standards Specifications
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
Typ
VCM(DC) (V)
Typ
VDIF(AC) (V)
Min Max
I/O Standard
Min Typ Max Min Max Min
Max
Min
Max
HSTL-18
CLASS I, II
1.71 1.8 1.89 0.2
1.425 1.5 1.575 0.2
—
—
0.78
0.68
—
—
1.12
0.78
0.68
—
—
1.12
0.9
0.4
0.4
—
—
HSTL-15
CLASS I, II
0.9
—
VCCIO
VCCIO
HSTL-12
CLASS I, II
1.14 1.2 1.26 0.16
—
0.5* VCCIO
0.4* VCCIO 0.5* VCCIO 0.6* VCCIO 0.3
+ 0.3
+ 0.48
Table 1–18. Differential I/O Standard Specifications (Part 1 of 2)
VCCIO (V)
VID (V)(1)
VICM(DC) (V)
VOD (V) (2)
VOCM (V) (2)
Min Typ Max
I/O
Standard
Min Typ Max Min Condition Max Min Condition Max
Min Typ Max
0.05
(6)
D
max 700
Mbps
1.8
(6)
2.375 2.5 2.625 0.1
2.375 2.5 2.625 0.1
2.375 2.5 2.625 0.1
VCM = 1.25
VCM = 1.25
VCM = 1.25
—
—
—
0.247
0.247
0.247
—
—
—
0.6
0.6
0.6
1.125 1.25 1.375
1.125 1.25 1.375
1.0 1.25 1.5
1.0 1.25 1.5
2.5 V LVDS
(Row I/O)
1.05
(6)
D
max > 700
Mbps
1.55
(6)
0.05
(6)
Dmax 700
1.8
(6)
Mbps
2.5 V LVDS
(Column I/O)
1.05
(6)
D
max > 700
Mbps
1.55
(6)
2.375 2.5 2.625 0.1
2.375 2.5 2.625 0.1
2.375 2.5 2.625 0.1
2.375 2.5 2.625 0.2
2.375 2.5 2.625 0.2
VCM = 1.25
VCM = 1.25
VCM = 1.25
—
—
—
0.247
0.1
—
0.2
0.2
—
0.6
0.6
0.6
0.6
0.6
RSDS
(Row I/O)
0.3
0.3
0.4
0.4
—
—
—
—
1.4
1.4
0.5
0.5
0.5
0.5
1.2
1.2
1.2
1.2
1.4
1.5
1.4
1.5
RSDS
(Column I/O)
—
0.1
Mini-LVDS
(Row I/O)
0.6
0.6
1.325 0.25
1.325 0.25
Mini-LVDS
(Column I/0)
—
—
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–12
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table 1–18. Differential I/O Standard Specifications (Part 2 of 2)
VCCIO (V)
VID (V)(1)
VICM(DC) (V)
VOD (V) (2)
VOCM (V) (2)
Typ Max
I/O
Standard
Min Typ Max Min Condition Max Min Condition Max
Min Typ Max
Min
2.375 2.5 2.625
(5) (5) (5)
D
max 700
Mbps
1.8
(4)
0.3
0.3
—
—
—
—
0.6
1.0
—
—
—
—
—
—
—
—
—
—
—
LVPECL
1.6
(3)
2.375 2.5 2.625
(5) (5) (5)
D
max > 700
Mbps
—
(4)
Notes to Table 1–18:
(1) The minimum VID value is applicable over the entire common mode range, VCM
.
(2) RL range: 90 RL 110 .
(3) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in column I/O use
VCC_CLKIN which should be powered by 2.5 V. Differential clock inputs in row I/O are powered by VCCPD
.
(4) The receiver voltage input range for data rate when Dmax > 700 Mbps,0.85 V VIN 1.75 V.
The receiver voltage input range for data rate when Dmax 700 Mbps, 0.45 V VIN 1.95 V
(5) Power supply for column I/O LVPECL differential clock input buffer is VCC_CLKIN
.
(6) The receiver voltage input range for data rate when Dmax > 700 Mbps, 1.0 V VIN 1.6 V.
The receiver voltage input range for data rate when Dmax 700 Mbps, zero V VIN 1.85 V.
Power Consumption
Altera offers two ways to estimate power for a design: the Excel-based Early Power
Estimator and the Quartus II PowerPlay Power Analyzer feature.
The interactive Excel-based Early Power Estimator is typically used prior to designing
the FPGA in order to get a magnitude estimate of the device power. The Quartus II
PowerPlay Power Analyzer provides better quality estimates based on the specifics
of the design after the place-and-route is complete. The PowerPlay Power Analyzer
can apply a combination of user-entered, simulation-derived and estimated signal
activities which, combined with detailed circuit models, can yield very accurate
power estimates.
See Table 1–4 for supply current estimates for VCCPGM and VCC_CLKIN. Use the EPE and
PowerPlay Power Analyzer for current estimates of remaining power supplies.
f
For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide For Stratix III FPGAs and the PowerPlay Power Analysis chapter in
the Quartus II Handbook.
Switching Characteristics
This section provides performance characteristics of Stratix III core and periphery
blocks for commercial grade devices.
These characteristics can be designated as Preliminary and Final and each
designation is defined below.
Preliminary
Preliminary characteristics are created using simulation results, process data, and
other known parameters.
Final
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–13
Switching Characteristics
Final numbers are based on actual silicon characterization and testing. These numbers
reflect the actual performance of the device under worst-case silicon process, voltage,
and junction temperature conditions. The upper-right hand corner of a table shows
the designation as Preliminary or Final.
Core Performance Specifications
These sections describe the Clock Tree, PLL, DSP, TriMatrix, and Configuration and
JTAG Specifications.
Clock Tree Specifications
Table 1–19 lists the clock tree performance specifications for the logic array, DSP
blocks, and TriMatrix Memory blocks for Stratix III devices.
Table 1–19. Stratix III Clock Tree Performance
C2
C3, I3
C4, I4
C4L, I4L
Unit
Device
VCCL = 1.1V
600
VCCL = 1.1V
500
VCCL = 1.1V
450
VCCL = 1.1V
VCCL = 0.9V
375
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SE260
EP3SL340
EP3SE50
EP3SE80
EP3SE110
450
450
450
450
450
450
450
450
450
450
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
600
500
450
375
600
500
450
375
600
500
450
375
600
500
450
375
600
500
450
375
600
500
450
375
600
500
450
375
600
500
450
375
600
500
450
375
PLL Specifications
Table 1–20 describes the Stratix III PLL specifications when operating in both the
commercial junction temperature range (0 to 85° C) and the industrial junction
temperature range (-40 to 100° C), except for EP3SL340, EP3SE260, and EP3SL200
devices in the I4L ordering code, where the industrial junction temperature range is
from 0° C to 100° C, regardless of supply voltage. Refer to the figure in “PLL
Specifications” in “Glossary” for PLL block diagram.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–20. Stratix III PLL Specifications (Part 1 of 3)
C2
C3, I3
C4, I4
C4L, I4L
Symbol
Parameter
V
CCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 0.9V
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
800
(1)
717
(1)
717
(1)
717
(1)
717
(1)
fIN
Input clock frequency
5
—
5
5
—
5
5
—
5
5
—
5
5
—
MHz
fINPFD
fVCO
Input frequency to the PFD
PLL VCO operating range
5
—
—
325
—
—
325
—
—
325
—
—
325
—
—
325
MHz
MHz
600
1600 600
1300 600
1300 600
1300 600
1300
Input clock or external feedback
clock input duty cycle
tEINDUTY
fOUT
40
—
—
45
—
—
—
—
—
50
—
3.5
60
40
—
—
45
—
—
—
—
—
50
—
3.5
60
40
—
—
45
—
—
—
—
—
50
—
3.5
60
40
—
—
45
—
—
—
—
—
50
—
3.5
60
40
—
—
45
—
—
—
—
—
50
—
3.5
60
%
MHz
MHz
%
Output frequency for internal global
or regional clock
600
(2)
500
(2)
450
(2)
450
(2)
375
(2)
Output frequency for dedicated
external clock output
800
(2)
717
(2)
717
(2)
717
(2)
717
(2)
fOUT_EXT
tOUTDUTY
tFCOMP
Duty cycle for external clock output
(when set to 50%)
55
10
—
55
10
—
55
10
—
55
10
—
55
10
—
External feedback clock
compensation time
ns
Time required to reconfigure scan
chain
scanclk
cycles
tCONFIGPLL
Time required to reconfigure phase
shift
scanclk
cycles
tCONFIGPHASE
fSCANCLK
tLOCK
—
—
—
1
—
100
1
—
—
—
1
—
100
1
—
—
—
1
—
100
1
—
—
—
1
—
100
1
—
—
—
1
—
100
1
scanclk frequency
—
—
—
—
—
—
—
—
—
—
MHz
Time required to lock from end of
device configuration
ms
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale
tDLOCK
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
ms
counters/delays)
Table 1–20. Stratix III PLL Specifications (Part 2 of 3)
C2
C3, I3
C4, I4
C4L, I4L
Symbol
Parameter
V
CCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 0.9V
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
PLL closed-loop low bandwidth
—
0.3
—
—
0.3
—
—
0.3
—
—
0.3
—
—
0.3
—
MHz
MHz
PLL closed-loop medium
bandwidth
—
1.5
—
—
1.5
—
—
1.5
—
—
1.5
—
—
1.5
—
fCLBW
PLL closed-loop high bandwidth
(5)
—
—
10
4
—
50
—
—
—
10
4
—
50
—
—
—
10
4
—
50
—
—
—
10
4
—
50
—
—
—
10
4
—
50
—
MHz
ps
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
—
—
—
—
—
—
—
Minimum pulse width on areset
signal
ns
Input clock cycle to cycle jitter (FREF
100 MHz)
—
—
—
—
—
—
—
—
0.15
750
175
17.5
—
—
—
—
—
—
—
—
0.15
750
175
17.5
—
—
—
—
—
—
—
—
0.15
750
175
17.5
—
—
—
—
—
—
—
—
0.15
750
175
17.5
—
—
—
—
—
—
—
—
0.1 UI (p-p)
500 ps (p-p)
225 ps (p-p)
tINCCJ (3)
Input clock cycle to cycle jitter (FREF
<100 MHz)
Period Jitter for dedicated clock
output (FOUT 100 MHz)
tOUTPJ_DC (4)
Period Jitter for dedicated clock
output (FOUT <100 MHz)
mUI
22.5
(p-p)
Cycle to Cycle Jitter for dedicated
clock output
(FOUT 100 MHz)
—
—
—
—
175
—
—
—
—
175
—
—
—
—
175
—
—
—
—
175
—
—
—
—
225 ps (p-p)
t
OUTCCJ_DC (4)
Cycle to Cycle Jitter for dedicated
clock output
(FOUT <100 MHz)
mUI
22.5
17.5
17.5
17.5
17.5
(p-p)
Period Jitter for clock output on
regular IO (FOUT 100 MHz)
—
—
—
—
600
60
—
—
—
—
600
60
—
—
—
—
600
60
—
—
—
—
600
60
—
—
—
—
750 ps (p-p)
tOUTPJ_IO (4), (7)
Period Jitter for clock output on
regular IO (FOUT <100 MHz)
mUI
75
(p-p)
Table 1–20. Stratix III PLL Specifications (Part 3 of 3)
C2
C3, I3
C4, I4
C4L, I4L
Symbol
Parameter
V
CCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 0.9V
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Cycle to Cycle Jitter for clock
output on regular IO
(FOUT 100 MHz)
—
—
—
—
—
—
600
60
—
—
—
—
—
—
600
60
—
—
—
—
—
—
600
60
—
—
—
—
—
—
600
60
—
—
—
—
—
—
750 ps (p-p)
tOUTCCJ_IO (4), (7)
Cycle to Cycle Jitter for clock
output on regular IO
(FOUT <100 MHz)
mUI
75
(p-p)
Period Jitter for dedicated clock
output in cascaded PLLs (FOUT
100 MHz)
tCASC_OUTPJ_DC (4),
(6)
250
250
250
250
325 ps (p-p)
Period Jitter for dedicated clock
output in cascaded PLLs (FOUT
100 MHz)
mUI
32.5
—
—
—
—
25
10
—
—
—
—
25
10
—
—
—
—
25
10
—
—
—
—
25
10
—
—
—
—
(p-p)
Frequency drift after PFDENAis
disabled for duration of 100 s
fDRIFT
10
%
Notes to Table 1–20:
(1) This specification is limited in Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(2) This specification is limited by the lower of the two: I/O fmax or fout of the PLL.
(3) A high input jitter will directly affect the PLL output jitter. To have low PLL output clock jitter, you need to provide a clean clock source, which is less than 120 ps.
(4) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404 % confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps
is applied.
(5) High bandwidth PLL settings are not supported in external feedback mode.
(6) Cascaded PLL spec only applicable with the following conditions:
a) Upstream PLL: 0.59 MHz Upstream PLL BW < 1 MHz
b) Downstream PLL: Downstream PLL BW > 2 MHz
(7) External memory interface clock output jitter specifications use a different measurement method and are available in Table 1–35.
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–17
Switching Characteristics
DSP Block Specifications
Table 1–21 describes the Stratix III DSP block performance specifications.
Table 1–21. Stratix III DSP Block Performance Specifications (Note 1)
C2 (5)
C3
C4
C4L
I3
I4
I4L
Number of
Multipliers
Mode
Unit
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
VCCL=
1.1V
VCCL=
1.1V
VCCL=
0.9V
1.1V
1.1V
0.9V
99-bit multiplier (a, c, e, g) (2)
99-bit multiplier (b, d, f, h) (2)
1212-bit multiplier (a, e) (3)
1212-bit multiplier (b, d, f, h) (3)
1818-bit multiplier
1
1
1
1
1
1
1
2
4
440
500
440
500
600
440
440
490
490
365
410
365
410
495
365
365
405
405
315
375
315
375
440
315
315
345
345
315
375
315
375
440
315
315
345
345
240
270
240
270
320
220
220
250
250
345
385
345
385
470
345
345
380
380
315
375
315
375
440
315
315
345
345
225
250
225
250
300
205
205
235
235
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
3636-bit multiplier
Double mode
1818-bit multiply adder
1818-bit multiply adder
1818-bit multiply adder with loop
back
2
490
405
345
345
250
380
345
235
MHz
1818-bit multiply adder with loop
back (4)
2
4
4
390
475
475
320
390
390
300
330
330
240
330
330
180
240
240
300
370
370
300
330
330
135
225
225
MHz
MHz
MHz
1818-bit multiply accumulator
1818-bit multiply adder with
chainout
Input Cascade Independent output
of four 1818 bit multiplier
4
1
550
475
455
390
415
330
415
330
270
250
430
370
415
330
250
235
MHz
MHz
36-bit shift (32 bit data)
Notes to Table 1–21:
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) The DSP block implements 8 independent 9b 9b multiplies using a, b, c, d for top DSP half block and e, f, g, h for bottom DSP half block multipliers.
(3) The DSP block implements 6 independent 12b 12b multiplies using a, b, d for top DSP half block and e, f, h for bottom DSP half block multipliers.
(4) Maximum for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled.
(5) The Fmax for EP3SL200, EP3SE260, and EP3SL340 at C2 Speed Grade is 7% slower than the C2 values shown in the table.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–18
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
TriMatrix Memory Block Specifications
Table 1–22 describes the Stratix III TriMatrix Memory Block specifications.
Table 1–22. Stratix III TriMatrix Memory Block Performance Specifications (Note 1) (Part 1 of 3)
C2 (6)
C3
VCCL
C4
VCCL
C4L
VCCL
I3
I4
I4L
Memory
Block
Type
TriMatrix
Memory
Mode
ALUTs
Unit
VCCL
=
=
=
VCCL
=
=
VCCL= VCCL= VCCL=
1.1V 1.1V 1.1V 0.9V 1.1V 1.1V 0.9V
1.1V
Single port 16 × 10
0
0
0
0
0
0
1
1
1
1
1
1
600
600
600
600
550
575
500
500
500
500
465
485
450
450
450
450
390
405
450
450
450
450
390
405
340
340
370
340
245
255
475
475
475
475
440
460
450
450
450
450
390
405
320
320
350
320
230
230
MHz
MHz
MHz
MHz
MHz
MHz
Simple dual-port 16 20
ROM 64 × 10
MLAB
ROM 32 × 20
Single-port 8K × 1
Single-port 4K × 2 or 2K × 4
Single-port 1K × 9 , 512 × 18, or
256 × 36
0
1
565
475
395
395
245
450
395
220
MHz
Simple dual-port, 8K × 1
0
0
1
1
545
570
460
480
385
400
385
400
240
250
435
455
385
400
225
225
MHz
MHz
Simple dual-port, 4K × 2 or 2K × 4
Simple dual-port, 1K × 9 , 512 × 18.
or 256 × 36
0
1
565
475
395
395
245
450
395
220
MHz
Simple dual-port, 8K × 1, 4K × 2 or
2K × 4 with
read-during-write option set to "Old
Data"
0
1
375
312
265
265
205
295
265
185
MHz
Simple dual-port, 1K × 9, 512 × 18,
256 × 36 with read-during-write
option set to "Old Data"
0
1
375
312
265
265
200
295
265
180
MHz
True dual-port, 8K × 1
0
0
0
1
1
1
530
550
545
440
460
460
370
385
380
370
385
380
230
240
235
420
435
435
370
385
380
215
215
210
MHz
MHz
MHz
M9K (2)
True dual-port, 4K × 2 or 2K × 4
True dual-port, 1K × 9 or 512 × 18
True dual-port, 8K × 1, 4K × 2, or
2K × 4 with
read-during-write option set to "Old
Data"
0
0
1
1
350
340
295
285
245
240
245
240
175
165
280
270
245
240
160
150
MHz
MHz
True dual-port, 1K × 9 or 512 × 18
with
read-during-write option set to "Old
Data"
ROM 1P, 8K × 1, 4K × 2, or 2K × 4
0
0
1
1
580
575
485
485
405
405
405
405
260
255
460
460
405
405
235
230
MHz
MHz
ROM 1P, 1K × 9 ,512 × 18, or
256 × 36
ROM 2P, 8K × 1 ,4K × 2, or 2K × 4
ROM 2P, 1K × 9, or 512 × 18
0
0
1
1
580
575
800
500
485
485
405
405
405
405
265
260
460
460
405
405
240
235
MHz
MHz
ps
Min Pulse Width (Clock High Time)
Min Pulse Width (Clock Low Time)
—
—
—
—
1000 1100 1100 1800 1000 1100 1800
625 690 690 1100 625 690 1100
ps
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–19
Switching Characteristics
Table 1–22. Stratix III TriMatrix Memory Block Performance Specifications (Note 1) (Part 2 of 3)
C2 (6)
C3
VCCL
C4
VCCL
C4L
VCCL
I3
I4
I4L
Memory
Block
Type
TriMatrix
Memory
Mode
ALUTs
Unit
VCCL
=
=
=
VCCL
=
=
VCCL= VCCL= VCCL=
1.1V 1.1V 1.1V 0.9V 1.1V 1.1V 0.9V
1.1V
True dual-port 16K × 9 or
8K × 18
0
0
0
1
1
1
350
520
350
300
430
300
245
365
245
245
365
245
180
250
180
280
405
280
245
365
245
170
235
170
MHz
MHz
MHz
True dual-port 4K × 36
Simple dual-port 16K × 9 or
8K × 18
Simple dual-port 4K × 36 or
2K × 72
0
1
565
470
395
395
225
440
395
210
MHz
ROM 1Port
0
0
0
0
1
1
1
1
580
545
385
580
470
450
330
470
425
380
270
425
425
380
270
425
260
260
240
210
470
425
310
470
425
380
270
425
260
245
195
195
MHz
MHz
MHz
MHz
ROM 2 Port
Single-port 16K × 9 or 8K × 18
Single-port 4K × 36
M144K
(3), (4)
True dual-port 16K × 9, 8K × 18, or
4K × 36 with read-during-write
option set to "Old Data"
0
1
325
270
225
225
165
255
225
155
MHz
Simple dual-port 16K × 9,
8K × 18, 4K × 36, or 2K × 72 with
read-during-write option set to "Old
Data"
0
1
350
292
210
250
180
250
180
200
130
275
195
250
180
190
120
MHz
Simple dual-port 2K × 64 (with ECC)
Min Pulse Width (Clock High Time)
Min Pulse Width (Clock Low Time )
0
1
255
800
500
MHz
ps
—
—
—
—
1000 1100 1100 1800 1000 1100 1800
625
360
430
360
690
300
365
300
690
300
365
300
1100
210
250
210
625
340
405
340
690
300
365
300
1100
195
235
195
ps
True dual-port 16K × 9 or
8K × 18
0
0
0
1
1
1
425
520
425
MHz
MHz
MHz
True dual-port 4K × 36
Simple dual-port 16K × 9 or
8K × 18
Simple dual-port 4K × 36 or
2K × 72
0
1
565
470
395
395
225
440
395
210
MHz
ROM 1Port
0
0
0
0
1
1
1
1
580
545
475
580
470
450
405
470
425
380
335
425
425
380
335
425
260
260
210
210
470
425
380
470
425
380
335
425
260
245
195
195
MHz
MHz
MHz
MHz
M144K
(3), (5)
ROM 2 Port
Single-port 16K × 9 or 8K × 18
Single-port 4K × 36
True dual-port 16K × 9, 8K × 18, or
4K × 36 with read-during-write
option set to "Old Data"
0
1
325
270
225
225
165
255
225
155
MHz
Simple dual-port 16K × 9,
8K × 18, 4K × 36, or 2K × 72 with
read-during-write option set to "Old
Data"
0
1
350
292
250
250
200
275
250
190
MHz
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–20
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table 1–22. Stratix III TriMatrix Memory Block Performance Specifications (Note 1) (Part 3 of 3)
C2 (6)
C3
VCCL
C4
VCCL
C4L
VCCL
I3
I4
I4L
Memory
Block
Type
TriMatrix
Memory
Mode
ALUTs
Unit
VCCL
=
=
=
VCCL
=
=
VCCL= VCCL= VCCL=
1.1V 1.1V 1.1V 0.9V 1.1V 1.1V 0.9V
1.1V
Simple dual-port 2K × 64 (with ECC)
Min Pulse Width (Clock High Time)
Min Pulse Width (Clock Low Time )
0
1
255
800
500
210
1000 1100 1100 1800 1000 1100 1800
625 690 690 1100 625 690 1100
180
180
130
195
180
120
MHz
ps
M144K
(3), (5)
—
—
—
—
ps
Notes to Table 1–22:
(1) Use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block
performance. Use Quartus II software to report timing for this and other memory block clocking schemes.
(2) The Fmax shown for M9K degrades 2 % when you use Error Detection CRC feature on the device, except for C4L speed grade with VCCL=0.9 V. For C4L speed
grade with VCCL=0.9V, there is no degradation in Fmax when Error Detection CRC feature is used.
(3) The Fmax shown for M144K degrades 10 MHz when you use byte-enable support on M144K.
(4) The Fmax is applicable when the COMPTABILITY option is turned ON.
(5) The Fmax is applicable when the COMPTABILITY option is turned OFF. This option is turned ON by default in Quartus II software.
(6) The Fmax for EP3SL200, EP3SE260, and EP3SL340 at C2 Speed Grade is 7% slower than the C2 values shown in the table.
Configuration and JTAG Specifications
Table 1–23 lists the Stratix III Configuration Mode Specifications.
Table 1–23. Stratix III Configuration Mode Specifications (Note 1)
Programming Mode
DCLK Fmax
100
Unit
MHz
MHz
MHz
Passive Serial
Fast Passive Parallel (2)
Fast Active Serial (3)
Notes to Table 1–23:
100
40
(1) DCLK Fmax is restricted when Remote Update is enabled. For more information, refer to Remote Update Circuitry
(ALTREMOTE_UPDATE) Megafunction User Guide.
(2) Data rate must be 4× slower than the clock when decompression and/or encryption are used.
(3) For more information about the minimum and typical DCLK Fmax value in Fast Active Serial configuration, refer to
the Serial Configuration Devices Data Sheet chapter in Cyclone Device Handbook.
Table 1–24 shows the JTAG timing parameters and values for Stratix III devices. Refer
to figure for “HIGH-SPEED I/O Block” in “Glossary” for JTAG timing requirements.
Table 1–24. Stratix III JTAG Timing Parameters and Values
Symbol
Parameter
TCK clock period
Min
30
14
14
1
Max
—
—
—
—
—
—
11
14
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP
tJCH
tJCL
TCK clock high time
TCK clock low time
tJPSU (TDI)
JPSU (TMS)
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
t
3
tJPH
5
tJPCO
tJPZX
tJPXZ
JTAG port clock to output
—
—
—
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–21
Switching Characteristics
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfacing, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. For
example, Stratix III devices I/O configured with voltage referenced I/O standards can
achieve up to the stated system interfacing speed as indicated in “External Memory
Interface Specifications” on page 1–25. General-purpose I/O standards such as 3.3,
3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2 LVCMOS
at 100MHz interfacing frequency with 10pF load.
1
Actual achievable frequency depends on design- and system-specific factors. You
should perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Refer to the “Glossary” for definitions of high-speed timing specifications.
Table 1–25 shows the high-speed I/O timing for Stratix III devices.
Table 1–25. True & Emulated LVDS Specifications (Note 1), (2) (Part 1 of 3)
C2
C3, I3
C4, I4
C4L, I4L
Symbol
Conditions
fHSCLK_in
(input clock
Clock boost
factor W = 1 to 40
(3)
—
800
—
—
717
—
—
717
—
717
MHz
frequency)
fHSCLK_out
(output clock
—
5
—
800 (7)
5
717 (7)
5
717 (7)
5
—
717 (7) MHz
frequency)
Transmitter
SERDES factor
J = 3 to 10 (8)
(4)
(4)
—
—
1600
(4)
(4)
—
—
1250
(4)
(4)
—
—
1250
(4)
(4)
—
—
1250
Mbps
Mbps
SERDES factor
J = 2, Uses
(4)
(4)
(4)
(4)
fHSDR (data rate)
DDR Register
SERDES factor
J = 1, Uses SDR (4)
—
(4)
(4)
—
(4)
(4)
—
(4)
(4)
—
(4)
Mbps
Register
SERDES factor
(4)
LVDS_E_3R -
—
—
1100
311
(4)
(4)
—
—
1100
200
(4)
(4)
—
—
800
200
(4)
(4)
—
—
800
200
Mbps
Mbps
fHSDR (data rate)
J = 4 to 10
SERDES factor
(4)
LVDS_E_1R -
fHSDR (data rate)
J = 4 to 10
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–22
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table 1–25. True & Emulated LVDS Specifications (Note 1), (2) (Part 2 of 3)
C2
C3, I3
C4, I4
C4L, I4L
Symbol
Conditions
Total Jitter for
Data Rate, 600
Mbps – 1.6
Gbps
—
—
—
160
0.1
—
—
—
—
160
0.1
—
—
—
—
160
0.1
—
—
—
—
160
0.1
ps
UI
tx Jitter (5)
Total Jitter for
Data Rate, < 600
Mbps
—
TX output duty
cycle for both
True and
Emulated
Differential I/O
tDUTY
45
—
50
—
55
45
—
50
—
55
45
—
50
—
55
45
—
50
—
55
%
True Differential
I/O Standards
tRISE & tFALL
160
200
200
200
ps
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Network
tRISE & tFALL
—
—
—
—
310
460
—
—
—
—
310
500
—
—
—
—
350
500
—
—
—
—
350
500
ps
ps
Emulated
Differential I/O
Standards with
One External
Output Resistor
Network
tRISE & tFALL
True Differential
I/O Standards
TCCS
—
—
—
—
100
250
—
—
—
—
100
250
—
—
—
—
100
250
—
—
—
—
100
250
ps
ps
Emulated
Differential I/O
Standards
TCCS
Receiver
SERDES factor
J = 3 to 10
f
HSDRDPA (data
150
—
—
1600
150
—
—
1250
150
—
—
1250
150
—
—
1250
Mbp
s
rate)
SERDES factor
J = 3 to 10
(4)
(6)
(4)
(6)
(4)
(6)
(4)
(6)
Mbp
s
fHSDR (data rate)
DPA
DPA run length
Soft CDR mode
—
—
—
—
—
—
10000
300
—
—
—
—
10000
300
—
—
—
—
10000
300
—
—
—
—
10000
300
UI
Soft-CDR PPM
tolerance
PPM
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
1–23
C4L, I4L
—
Table 1–25. True & Emulated LVDS Specifications (Note 1), (2) (Part 3 of 3)
C2
C3, I3
C4, I4
Symbol
Conditions
Non DPA Mode
Sampling
Window
—
—
—
300
—
—
300
—
—
300
—
300
ps
Notes to Table 1–25:
(1) When J = 3 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate.
(4) The minimum and maximum specification is dependent on the clock source (PLL and clock pin, for example) and the clock routing resource (global, regional, or
local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.
(5) The txJitter specification is for true LVDS IO standard only.
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing the link timing closure analysis. You should consider the board skew margin,
transmitter delay margin as well as the receiver sampling margin to determine the maximum data rate supported.
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
Table 1–26. Stratix III DPA Lock Time Specifications (Note 1), (2), (3) (Part 1 of 2)
Number of
Number of
Data
repetitions
Transitions
Training
Pattern
per 256
data
Standard
in one
repetition
of training
pattern
Condition (5)
Min
Typ
Max
transition
(4)
without DPA
PLL calibration
256 data transitions
—
—
—
—
—
—
—
—
—
—
—
—
0000000000
1111111111
SPI-4
2
2
4
128
128
64
3×256 data transitions +
2×96 slow clock cycles
(6)
with DPA PLL
calibration
without DPA
PLL calibration
256 data transitions
00001111
10010000
3×256 data transitions +
2×96 slow clock cycles
(6)
with DPA PLL
calibration
Parallel Rapid
I/O
without DPA
PLL calibration
256 data transitions
3×256 data transitions +
2×96 slow clock cycles
(6)
with DPA PLL
calibration
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–24
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table 1–26. Stratix III DPA Lock Time Specifications (Note 1), (2), (3) (Part 2 of 2)
Number of
Number of
Data
repetitions
Transitions
Training
Pattern
per 256
data
Standard
in one
repetition
of training
pattern
Condition (5)
Min
Typ
Max
transition
(4)
without DPA
PLL calibration
256 data transitions
—
—
—
—
—
—
—
—
10101010
01010101
8
8
32
32
3×256 data transitions +
2×96 slow clock cycles
(6)
with DPA PLL
calibration
Miscellaneous
without DPA
PLL calibration
256 data transitions
3×256 data transitions +
2×96 slow clock cycles
(6)
with DPA PLL
calibration
Notes to Table 1–26:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0 to 1 or 1 to 0 transition.
(3) The DPA lock time stated in the table apply to both commercial and industrial grade.
(4) These are the number of repetitions for the stated training pattern to achieve 256 data transitions.
(5) PLL re-calibration is recommended for situations below to guarantee DPA locking:
■
Sparse data transitions. For example: Repeating sequence of ten 1s and ten 0s.
0 PPM frequency difference and/or 0° phase difference between clock and data.
■
(6) Slow clock = Data rate (Hz)/ Deserialization factor.
Figure 1–2. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–25
Switching Characteristics
Figure 1–3. Stratix III LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Spec
Table 1–27. Stratix III LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values
Jitter Frequency (Hz)
10,000
Jitter Amplitude
25.000
Unit
UI
F1
F2
F3
F4
17,565
25.000
UI
1,493,000
50,000,000
0.350
UI
0.350
UI
External Memory Interface Specifications
Table 1–28 through Table 1–35 list the external memory interface specifications for the
Stratix III device family.
Use Table 1–28 through Table 1–33 to perform memory interface timing analysis.
Table 1–28. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Half-Rate Controller (Note 1),
(2) (Part 1 of 2)
C2
C3, I3
C4, I4
C4L, I4L
VCCL = 1.1V
Memory Standards
Unit
V
CCL = 1.1V
533
VCCL = 1.1V
400
VCCL = 1.1V
333
VCCL = 0.9V
—
DDR3 SDRAM (3)
DDR2 SDRAM (4)
DDR SDRAM (4)
333
333
200
MHz
MHz
MHz
400
333
333
200
200
200
200
200
QDRII+ SRAM (2.5
clock cycle latency
only) (1.5 or 1.8V)(5)
400 (8)
350
300
300
300
300
300
—
MHz
MHz
QDRII SRAM
(1.5 or 1.8V)
350
167
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–26
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table 1–28. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Half-Rate Controller (Note 1),
(2) (Part 2 of 2)
C2
C3, I3
C4, I4
C4L, I4L
Memory Standards
Unit
V
CCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 0.9V
QDRII+ SRAM (36
emulated mode) (2.5
clock cycle latency
only) (1.5 or 1.8V) (5),
(6), (7)
300
250
250
250
—
MHz
QDRII SRAM (36
emulated mode) (1.5 or
1.8V) (6), (7)
300
400
250
333
250
300
250
300
—
—
MHz
MHz
RLDRAM II
(1.5 or 1.8V)
Notes to Table 1–28:
(1) The supported operating frequencies listed here are memory interface maximums for the FPGA device family. Your design’s actual achievable
performance is based on design- and system-specific factors, as well as static timing analysis of the completed design.
(2) The values apply to Column I/Os, Row I/Os, and hybrid mode interface. Column I/Os refer to Top and Bottom I/Os. Hybrid mode refers to
DQ/DQS groups wrapping over Column I/Os and Row I/Os of the device.
(3) This applies to interfaces with single chip-select discrete components and single-rank, unregistered modules.
(4) This performance specification applies for interfaces with single chip-select discrete components and single-rank unregistered modules. For
more information on a list of other supported configurations and corresponding performance specifications, refer to the External Memory PHY
Interface (ALTMEMPHY) Megafunction User Guide .
(5) The QDRII+ SRAM devices with 2.0 clock cycle latency are not supported due to hardware limitations.
(6) The performance for 36 emulated mode is lower than the performance for non 36 emulated mode due to the double-loading of the CQ/CQn
pins. Double-loading causes degradation in the signal slew rate which affects FPGA delay. Furthermore, due to the difference in slew rate, there
is a shift in the setup and hold time window. You can perform an IBIS simulation to illustrate the shift in the clock signals.
(7) For more information about 36 QDRII+/QDRII SRAM emulation mode, refer to the External Memory PHY Interface (ALTMEMPHY)
Megafunction User Guide.
(8) To achieve this data rate, Altera requires the QDRII+ SRAM device to have an echo clock tCQHCQ#H specification of 0.9ns or higher. QDRII+
devices with this specification are targeted for release later in 2009. In the interim, you can safely prototype with existing QDRII+ SRAM devices
up to 375MHz.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–27
Switching Characteristics
Table 1–29. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Full-Rate Controller (Note 1), (2),
(3), (4)
C2
C3, I3
C4, I4
C4L, I4L
Memory Standards
DDR2 SDRAM (5)
Unit
V
CCL = 1.1V
300
VCCL = 1.1V
267
VCCL = 1.1V
233
VCCL = 1.1V
VCCL = 0.9V
167
233
200
MHz
MHz
DDR SDRAM
200
200
200
167
Notes to Table 1–29:
(1) The supported operating frequencies listed here are memory interface maximums for the FPGA device family. Your design’s actual achievable
performance is based on design- and system-specific factors, as well as static timing analysis of the completed design.
(2) This performance specification applies for interfaces with single rank unregistered DIMMs and single chip-select discrete components. For
more information on a list of other supported configurations and corresponding performance specifications, refer to the External Memory PHY
Interface (ALTMEMPHY) Megafunction User Guide.
(3) The values apply to column I/Os, Rows I/Os and Hybrid mode interface. Column I/Os refers to Top and Bottom I/Os. Row I/Os refers to Left and
Right I/Os. Hybrid mode refers to DQ/DQS groups wrapping over Column I/Os and Row I/Os of the device.
(4) It may be possible to close timing at up to 33MHz higher, depending on your design and the Quartus setting used. Refer to the section on
advanced settings in External Memory PHY Interface (ALTMEMPHY) Megafunction User Guide.
(5) We recommend use of ALTMEMPHY AFI mode to achieve these quoted maximum clock rate due to lower performance of Non-AFI mode.
External Memory I/O Timing Specifications
Table 1–30 and Table 1–31 list Stratix III device timing uncertainties on the read and
write data paths. Use these specifications to determine timing margins for source
synchronous paths between the Stratix III FPGA and the external memory device.
Refer to the figure for “SW (sampling window)” in “Glossary”
.
Table 1–30. Sampling Window (SW) - Read Side (Note 1) (Part 1 of 2)
C2
C3, I3
VCCL = 1.1V
SW (ps)
C4, I4
VCCL = 1.1V
SW (ps)
C4L, I4L
VCCL = 1.1V
SW (ps)
C4L, I4L
VCCL = 0.9V
SW (ps)
V
CCL = 1.1V
SW (ps)
I/O
Standard
Memory Type
Width
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
DDR3 SDRAM (with 8 or
10 tap phase offset,
300MHz–400MHz)
1.5V
SSTL
×4, ×8
×4, ×8
172
296
234
296
257
311
257
311
257
311
DDR3 SDRAM (with
Deskew circuitry,
401MHz–533MHz)
1.5V
SSTL
300
213
—
—
—
—
—
—
—
—
DDR2 SDRAM Differential
DQS
1.8V
SSTL
×4, ×8
×4, ×8
×4, ×8
181
231
231
261
261
306
256
256
286
328
234
284
284
314
314
326
276
261
291
337
257
307
307
337
337
326
276
261
291
350
257
307
307
337
337
326
276
261
291
350
257
307
307
337
337
326
276
261
291
350
DDR2 SDRAM
Single-ended DQS
1.8V
SSTL
DDR SDRAM
Single-ended DQS
2.5V
SSTL
1.5 V
HSTL
×9, ×18,
×36
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation (2)
1.5 V
HSTL
×36
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–28
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table 1–30. Sampling Window (SW) - Read Side (Note 1) (Part 2 of 2)
C2
C3, I3
VCCL = 1.1V
SW (ps)
C4, I4
VCCL = 1.1V
SW (ps)
C4L, I4L
VCCL = 1.1V
SW (ps)
C4L, I4L
VCCL = 0.9V
SW (ps)
VCCL = 1.1V
I/O
Memory Type
Width
Standard
SW (ps)
Setup Hold Setup Hold Setup Hold Setup Hold Setup Hold
1.8 V
HSTL
×9, ×18,
×36
261
261
211
211
286
328
336
336
314
314
264
264
291
337
356
356
337
337
287
287
291
350
356
356
337
337
287
287
291
350
356
356
337
337
287
287
291
350
356
356
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation (2)
1.8 V
HSTL
×36
1.5 V
HSTL
×9, ×18
×9, ×18
RLDRAM II
1.8 V
HSTL
RLDRAM II
Notes to Table 1–30:.
(1) The values apply to Column I/Os, Row I/Os and Hybrid mode interface. Column I/Os refer to Top and Bottom I/Os. Hybrid mode refers to DQ/DQS groups
wrapping over Column I/Os and Row I/Os of the device.
(2) Please refer to the section “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” on page 8–20 in chapter 8 External Memory
Interface in Stratix III Devices for the implementation.
Table 1–31. Transmitter Channel-to-Channel Skew (TCCS) - Write Side (Note 1) (Part 1 of 2)
C2
C3, I3
C4, I4
C4L, I4L
C4L, I4L
VCCL = 0.9V
TCCS (ps)
VCCL = 1.1V
V
CCL = 1.1V
VCCL = 1.1V
TCCS (ps)
VCCL = 1.1V
TCCS (ps)
I/O
Standard
Memory Type
Width
TCCS (ps)
TCCS (ps)
Lead
Lag
Lead
Lag
Lead
Lag
Lead
Lag
Lead
Lag
DDR3 SDRAM (with
Deskew circuitry,
401MHz–533MHz)
1.5V
SSTL
×4, ×8
×4, ×8
×4, ×8
×4, ×8
×4, ×8
253
293
293
169
169
262
—
—
—
—
—
—
—
—
DDR3 SDRAM(8-tap
phase offset, 375MHz-
400MHz)
1.5V
SSTL
284
284
470
470
341
341
217
217
332
373
496
496
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DDR3 SDRAM (8-tap
phase offset, 360MHz-
375MHz)
1.5V
SSTL
—
—
DDR3 SDRAM(10-tap
phase offset, 333MHz-
360MHz)
1.5V
SSTL
258
258
528
528
258
258
528
528
DDR3 SDRAM(10-tap
phase offset, 300MHz-
333MHz)
1.5V
SSTL
DDR2 SDRAM Differential
DQS
1.8V
SSTL
×4, ×8
×4, ×8
229
316
246
168
230
318
355
239
250
346
388
260
250
346
388
260
350
446
488
360
DDR2 SDRAM Single-
ended DQS
1.8V
SSTL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–29
Switching Characteristics
Table 1–31. Transmitter Channel-to-Channel Skew (TCCS) - Write Side (Note 1) (Part 2 of 2)
C2
C3, I3
C4, I4
C4L, I4L
C4L, I4L
V
CCL = 1.1V
VCCL = 1.1V
TCCS (ps)
VCCL = 1.1V
TCCS (ps)
V
CCL = 1.1V
VCCL = 0.9V
TCCS (ps)
I/O
Standard
Memory Type
Width
TCCS (ps)
TCCS (ps)
Lead
Lag
Lead
Lag
Lead
Lag
Lead
Lag
Lead
Lag
DDR SDRAM Single-
ended DQS
2.5V
SSTL
×4, ×8
313
290
310
259
279
290
259
157
315
292
312
260
280
292
260
222
343
315
335
280
300
315
280
242
343
315
335
280
300
315
280
242
443
342
1.5 V
HSTL
×9, ×18,
×36
278
298
276
296
278
276
388
408
385
405
388
385
421
441
418
438
421
418
421
441
418
438
421
418
415
435
380
400
415
380
521
541
518
538
521
518
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation (2)
1.5 V
HSTL
×36
1.8 V
HSTL
×9, ×18,
×36
QDRII/II+ SRAM
QDRII/II+ SRAM
Emulation (2)
1.8 V
HSTL
×36
1.5 V
HSTL
×9, ×18
×9, ×18
RLDRAM II
1.8 V
HSTL
RLDRAM II
Notes to Table 1–31:
(1) The values apply to Column I/Os, Row I/Os and Hybrid mode interface. Column I/Os refer to Top and Bottom I/Os. Hybrid mode refers to DQ/DQS groups
wrapping over Column I/Os and Row I/Os of the device.
(2) Please refer to the section “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” on page 8–20 in chapter 8 External Memory
Interface in Stratix III Devices for the implementation.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–30
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
DLL and DQS Logic Block Specifications
Table 1–32 describes the DLL frequency range specifications for Stratix III devices.
Table 1–32. Stratix III DLL Frequency Range Specifications
Frequency Range (MHz)
Frequency
Number of
Delay Chains
DQS Delay
Buffer Mode (1)
Available Phase Shift
Mode
C2
C3, I3
C4, I4
C4L, I4L
0
1
90 – 150
90 – 140
90 – 120
90 – 120
22.5°, 45°, 67.5°, 90°
30°, 60°, 90°, 120°
16
12
Low
Low
120 – 200 120 – 190 120 – 170 120 – 170
2
3
150 – 240 150 – 230 150 – 200 150 – 200
180 – 300 180 – 290 180 – 250 180 – 250
36°, 72°, 108°, 144°
45°, 90°,135°, 180°
10
8
Low
Low
4
5
6
7
240 – 370 240 – 350 240 – 310 240 – 310
290 – 450 290 – 420 290 – 370 290 – 370
360 – 560 360 – 530 360 – 460 360 – 460
30°, 60°, 90°,120°
36°, 72°, 108°, 144°
45°, 90°, 135°, 180°
12
10
8
High
High
High
High
470 – 740 470 – 700 470 – 610 470 – 610 60°, 120°, 180°, 240°
6
Note to Table 1–32:
(1) Low indicates 6-bit DQS delay setting, high indicates 5-bit DQS delay setting.
Table 1–33 describes the average DQS phase offset delay per setting for Stratix III
devices.
Table 1–33. Average DQS Phase Offset Delay per Setting (Note 1), (2), (3)
Speed Grade
C2
Min
7
Typ
10
Max
13
Unit
ps
C3, I3
7
11
15
ps
C4, I4
7
11.5
11.5
16
ps
C4L, I4L
7
16
ps
Notes to Table 1–33:
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
4 to 6.
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear with a cumulative delay variation of 20ps for all speed grades. For example, when
using a C2 speed grade and applying 10° phase offset settings to a 90° phase shift at 400 MHz, the expected
minimum cumulative delay is [625 ps + (10*7 ps) - 20 ps] = 675 ps.
Table 1–34. Stratix III DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) (Note 1)
Number of DQS Delay
C2
C3, I3
C4, C4L, I4, I4L
Unit
Buffer
1
13
26
39
52
14
28
42
56
15
30
45
60
ps
ps
ps
ps
2
3
4
Note to Table 1–34:
(1) This error specification is the absolute maximum and minimum error. For example, skew on 3 DQS delay buffer in a C2 speed grade is 39ps.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–31
Switching Characteristics
Table 1–35. Stratix III Memory Output Clock Jitter Specification (Note 1), (2),(3)
C2
C3, I3
C4, I4
C4L, I4L
VCCL = 1.1V VCCL = 0.9V
VCCL = 1.1V
VCCL = 1.1V
VCCL = 1.1V
Unit
Clock
Parameter
Network Symbol
Min Max Min Max Min Max Min Max Min Max
–70 70 –85 85 –100 100 –100 100 –120 120
–150 150 –170 170 –190 190 –190 190 –230 230
Regional tJIT(duty) –80 80 –90 90 –100 100 –100 100 –140 140
Global tJIT(per) –105 105 –128 128 –150 150 –150 150 –180 180
tJIT(cc) –225 225 –255 255 –285 285 –285 285 –340 340
tJIT(duty) –120 120 –135 135 –150 150 –150 150 –180 180
Clock period jitter
Regional tJIT(per)
ps
ps
ps
ps
ps
ps
Cycle-to-cycle period jitter Regional tJIT(cc)
Duty cycle jitter
Clock period jitter
Cycle-to-cycle period jitter Global
Duty cycle jitter
Global
Notes to Table 1–35:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter & DDIO circuits clocked by a PLL output routed on
a regional or global clock network as specified. Use of regional clock networks are recommended whenever possible.
(3) The memory output clock jitter stated in the table is applicable when an input jitter of 30ps is applied.
OCT Calibration Block Specifications
Table 1–36 shows the on-chip termination calibration block specifications for
Stratix III devices.
Table 1–36. On-Chip Termination Calibration Block Specification
Symbol
Description
Min Typical Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLKclock cycles required
for OCT Rs and Rt calibration
tOCTCAL
—
1000
—
cycles
Number of OCTUSRCLKclock cycles required
for OCT code to shift out per OCT calibration block
tOCTSHIFT
tRS_RT
—
—
28
—
—
cycles
ns
Time required to dynamically switch from Rs to Rt
2.5
DCD Specifications
Table 1–37 lists the worst case duty cycle distortion for Stratix III devices. Detailed
information on duty cycle distortion will be published after characterization.
Table 1–37. Duty Cycle Distortion on Stratix III I/O Pins (Note 1)
C2
Min Max Min Max Min Max
45 55 45 55 45 55
C3
C4
Symbol
Output Duty Cycle
Unit
%
Note to Table 1–37:
(1) DCD specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated and general
purpose I/O pins.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–32
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
I/O Timing
Timing Model
TM
TM
The DirectDrive technology and MultiTrack interconnect ensure predictable
performance, accurate simulation, and accurate timing analysis across all Stratix III
device densities and speed grades. This section describes and specifies the
performance of I/Os.
All specifications except the fast model are representative of worst-case supply
voltage and junction temperature conditions. Fast model specifications are
representative of best case process, supply voltage, and junction temperature
conditions.
The timing numbers listed in the tables of this section are extracted from the
Quartus II software version 8.1.
Preliminary and Final Timing
Timing models can have either preliminary or final status. The Quartus II software
issues an informational message during the design compilation if the timing models
are preliminary. Table 1–38 shows the status of the Stratix III device timing models.
Preliminary status means that the timing models are subject to change in future
Quartus II releases. Initially, timing numbers are created using simulation results,
process data, and other known parameters. Parts of the timing models may be
correlated to silicon measurements. Various tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing models are based on simulation models that are characterized versus the
actual device measurements under all allowable operating conditions. When the
timing models are final, all or most of the Stratix III family devices have been
completely characterized and no further changes to the timing model are expected.
Table 1–38. Stratix III Device Timing Model Status
Device
Preliminary
Final
v
v
v
v
v
v
v
v
v
v
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
—
—
—
—
—
—
—
—
—
—
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–33
I/O Timing
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum voltage, and
maximum temperature for input register setup time (tsu) and hold time (th). The
Quartus II software uses the following equations to calculate tsu and th timing for
Stratix III devices input signals.
tsu =
+ data delay from input pin to input register
+ micro setup time of the input register
- clock delay from input pin to input register
th =
- data delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
Figure 1–4 shows the setup and hold timing diagram for input registers.
Figure 1–4. Input Register Setup and Hold Timing Diagram
Input Data Delay
micro t
micro t
su
h
Input Clock Delay
For output timing, different I/O standards require different baseline loading
techniques for reporting timing delays. Altera characterizes timing delays with the
required termination for each I/O standard and with 0 pF (except for PCI and PCI-X,
which use 10 pF) loading and the timing is specified up to the output pin of the FPGA
device. The Quartus II software calculates the I/O timing for each I/O standard with
a default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization. Altera
measures clock-to-output delays (tco) at worst-case process, minimum voltage, and
maximum temperature (PVT) for default loading conditions shown in Table 1–39. The
following equation describes clock pin to output pin timing for Stratix III devices.
The tco from clock pin to I/O pin =
+ delay from clock pad to I/O output register
+ IOE output register clock-to-output delay
+ delay from output register to output pin
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–34
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Figure 1–5. Output Register Clock to Output Timing Diagram
Datain
Output
Output Register
micro t
Clock
CO
Output Register to
output pin delay
Clock pad to output
Register delay
Simulation using IBIS models is required to determine the delays on the PCB traces in
addition to the output pin delay timing reported by the Quartus II software and the
timing model in the device handbook.
1. Simulate the output driver of choice into the generalized test setup, using values
from Table 1–39.
2. Record the time to VMEAS at the far end of the PCB trace.
3. Simulate the output driver of choice into the actual PCB trace and load, using the
appropriate IBIS model or capacitance value to represent the load.
4. Record the time to VMEAS at the far end of the PCB trace.
5. Compare the results of steps 2 and 4. The increase or decrease in delay should be
added to or subtracted from the I/O Standard Output Adder delays to yield the
actual worst-case propagation delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in Table 1–39
using the above equation. Figure 1–6 shows the model of the circuit that is
represented by the output timing of the Quartus II software.
Figure 1–6. Output Delay Timing Reporting Setup Modeled by Quartus II Software for Single-Ended
Outputs and Dedicated Differential Outputs (Note 1)
V
TT
V
CCIO
Output
Output
R
C
p
T
L
R
S
Output
Output
Buffer
R
D
V
n
MEAS
GND
GND
Note to Figure 1–6:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
need to be accounted for with IBIS model simulations.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–35
I/O Timing
Figure 1–7 and Figure 1–8 show the model of the circuit that is represented by the
output timing of the Quartus II software for differential outputs with single and
multiple external resistors.
Figure 1–7. Output Delay Timing Reporting Setup Modeled by Quartus II Software for Differential
Outputs with Single External Resistor
Non-Dedicated
Differential Outputs
V
MEAS
R
R
P
D
V
MEAS
Figure 1–8. Output Delay Timing Reporting Setup modeled by Quartus II Software for Differential
Outputs with Three External Resistor
Non-Dedicated
Differential Outputs
R
V
S
MEAS
R
R
P
D
R
V
S
MEAS
Table 1–39. Output Timing Measurement Methodology for Output Pins (Part 1 of 3)
Measurement
Point
Loading and Terminations
I/O Standard
RS
—
—
—
—
—
—
—
—
—
—
25
25
25
25
25
25
—
RD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RT
—
—
—
—
—
—
—
—
—
—
50
25
50
25
50
25
50
RP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VCCIO
VCCPD
VCC
VTT
—
—
—
—
—
—
—
—
—
—
CL (pF)
VMEAS (v)
1.5675
1.5675
1.425
1.425
1.1875
0.855
0.7125
0.57
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V
3.135 3.135
3.135 3.135
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.02
1.02
1.02
1.02
1.02
1.02
1.02
0
0
2.85
2.85
2.85
2.85
0
0
2.375 2.375
1.71 2.375
1.425 2.375
0
1.8-V
0
1.5-V
0
1.2-V
1.14
2.85
2.85
2.375
2.85
2.85
0
PCI
10
10
0
1.425
1.425
1.1625
1.1625
0.83
PCI-X
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
SSTL-15 CLASS I
SSTL-15 CLASS II
1.8-V HSTL CLASS I
2.325 2.325
2.325 2.325
1.25
1.25
0.90
0.90
0.75
0.75
0.90
0
1.66
1.66
2.325
2.325
0
0
0.83
1.375 2.325
1.375 2.325
0
0.6875
0.6875
0.83
0
1.66
2.325
0
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–36
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–39. Output Timing Measurement Methodology for Output Pins (Part 2 of 3)
Measurement
Point
Loading and Terminations
I/O Standard
RS
—
—
—
—
—
RD
—
—
—
—
—
RT
25
50
25
50
25
RP
—
—
—
—
—
VCCIO
VCCPD
VCC
VTT
CL (pF)
VMEAS (v)
0.83
1.8-V HSTL
CLASS II
1.66
2.325
1.02
1.02
1.02
1.02
1.02
0.90
0.75
0.75
0.60
0.60
0
0
0
0
0
1.5-V HSTL CLASS I
1.375 2.325
1.375 2.325
0.6875
0.6875
0.545
0.545
1.5-V HSTL
CLASS II
1.2-V HSTL CLASS I
1.09
1.09
2.325
2.325
1.2-V HSTL
CLASS II
Differential SSTL-2
CLASS I
25
25
25
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
25
50
25
50
25
50
25
50
25
—
—
—
—
—
—
—
—
—
—
2.325 2.325
2.325 2.325
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.25
1.25
0.90
0.90
0.90
0.90
0.75
0.75
0.60
0.60
0
0
0
0
0
0
0
0
0
0
1.1625
1.1625
0.83
Differential SSTL-2
CLASS II
Differential SSTL-18
CLASS I
1.66
1.66
1.66
1.66
2.325
2.325
2.325
2.325
Differential SSTL-18
CLASS II
0.83
1.8-V Differential
HSTL CLASS I
0.83
1.8-V Differential
HSTL CLASS II
0.83
1.5-V Differential
HSTL CLASS I
1.375 2.325
1.375 2.325
0.6875
0.6875
0.545
0.545
1.5-V Differential
HSTL CLASS II
1.2-V Differential
HSTL CLASS I
1.09
1.09
2.325
2.325
1.2-V Differential
HSTL CLASS II
LVDS
—
—
100
100
100
100
100
—
—
—
—
—
—
—
2.325 2.325
2.325 2.325
2.325 2.325
2.325 2.325
2.325 2.325
1.02
1.02
1.02
1.02
1.02
—
—
—
—
—
0
0
0
0
0
1.1625
1.1625
1.1625
1.1625
1.1625
MINI-LVDS
RSDS
—
—
LVDS_E_1R
LVDS_E_3R
—
120
170
120
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–37
I/O Timing
Table 1–39. Output Timing Measurement Methodology for Output Pins (Part 3 of 3)
Measurement
Loading and Terminations
I/O Standard
Point
RS
—
RD
RT
—
—
—
—
RP
VCCIO
VCCPD
VCC
VTT
—
—
—
—
CL (pF)
VMEAS (v)
1.1625
1.1625
1.1625
1.1625
MINI-LVDS_E_1R
MINI-LVDS_E_3R
RSDS_E_1R
100
100
100
100
120
170
120
170
2.325 2.325
2.325 2.325
2.325 2.325
2.325 2.325
1.02
1.02
1.02
1.02
0
0
0
0
120
—
RSDS_E_3R
120
Notes to Table 1–39:
(1) Hyper transport is not supported by Stratix III.
(2) LVPECL outputs are not supported by Stratix III.
(3) Quartus timing conditions can be changed using the Advanced I/O Timing feature.
(4) VCC is nominally 1.1 V less 50 mV (1.05 V).
(5) Terminated I/O standards require an additional 30 mV IR drop on VCC (1.02 V).
(6) Terminated I/O standards required an additional 50 mV IR drop on VCCIO and VCCPD
.
I/O Default Capacitive Loading
See Table 1–40 for default capacitive loading of different I/O standards.
Table 1–40. Default Loading of Different I/O Standards for Stratix III (Part 1 of 2)
Capacitive
I/O Standard
Load
Unit
3.3-V LVTTL
0
0
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
3.3-V LVCMOS
3.0-V LVTTL
0
3.0-V LVCMOS
0
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
3.0-V PCI
0
0
0
10
10
0
3.0-V PCI-X
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.2-V HSTL
0
0
0
0
0
0
0
0
Differential SSTL-2 CLASS I
Differential SSTL-2 CLASS II
Differential SSTL-18 CLASS I
0
0
0
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–38
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–40. Default Loading of Different I/O Standards for Stratix III (Part 2 of 2)
Capacitive
Load
I/O Standard
Differential SSTL-18 CLASS II
Unit
0
0
0
0
0
0
0
0
pF
pF
pF
pF
pF
pF
pF
pF
1.8-V Differential HSTL CLASS I
1.8-V Differential HSTL CLASS II
1.5-V Differential HSTL CLASS I
1.5-V Differential HSTL CLASS II
1.2-V Differential HSTL CLASS I
1.2-V Differential HSTL CLASS II
LVDS
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–39
I/O Timing
Programmable IOE Delay
Table 1–41 shows Stratix III IOE programmable delay settings. For more information
on the annotation of delays in the IOE, refer to Figure 7–7 in the Stratix III Device I/O
Features chapter in volume 1 of the Stratix III Device Handbook.
Table 1–41. Stratix III IOE Programmable Delay (Note 1)
Fast Model C2
C3
C4
C4L
I3
I4
I4L
Min
Offset
(2)
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL =
Available
Settings
Parameter
1.1V 1.1V 1.1V 1.1V 0.9V 1.1V 1.1V 1.1V 0.9V Unit
Max
Offset
Max
Max
Max
Max
Max
Max
Max
Max
Max
Max
Offset Offset Offset Offset Offset Offset Offset Offset Offset Offset
D1
D2
D3
D4
D5
D6
15
7
0
0
0
0
0
0
442
248
1625
491
452
179
491
285
1806
517
503
199
748
387
829
412
916
442
871
427
833
411
870
433
957
464
915
448
833
411
ps
ps
ps
ps
ps
ps
7
2747 3058 3371 3218 3084 3210 3540 3382 3084
15
15
6
726
764
305
872
801
337
884
930
370
844
887
354
808
850
339
845
889
354
928
977
389
887
932
371
808
850
339
Notes to Table 1–41:
(1) You can set the parameter values in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column.
(2) The minimum offset represented in the table does not include the intrinsic delay.
Programmable Output Buffer Delay
Table 1–42 lists the delay chain settings that control the rising and falling edge delays
of the output buffer. Default delay is 0 ps.
Table 1–42. Programmable Output Buffer Delay (Note 1)
Symbol
Parameter
Typical
0 (default)
50
Unit
ps
ps
Rising and/or Falling
Edge delay
DOUTBUF
100
ps
150
ps
Note to Table 1–42:
(1) You can set the programmable output buffer delay in the Quartus II software by selecting the 'Output Buffer Delay
Control' assignment to either positive, negative or both edges with the specific values as stated in the table above
in ps for the 'Output Buffer Delay' assignment.
User I/O Pin Timing
Table 1–43 through Table 1–142 show user I/O pin timing for Stratix III devices. I/O
buffer tsu, th, and tco are reported for the cases when I/O clock is driven by a non-PLL
global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For tsu, th and tco
using regional clock, add the value from the adder tables listed for each device to the
GCLK/GCLK-PLL values for the device.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–40
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
EP3SL50 I/O Timing Parameters
Table 1–43 through Table 1–46 show the maximum I/O timing parameters for
EP3SL50 devices for single-ended I/O standards.
Table 1–43 specifies EP3SL50 column pins input timing parameters for single-ended
I/O standards.
Table 1–43. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.912
1.025
0.730
-0.487
-0.912
1.025
0.730
-0.487
-0.918
1.031
0.724
-0.481
-0.918
1.031
0.724
-0.481
-0.908
1.021
0.734
-0.491
-0.926
1.041
0.716
-0.471
-0.919
1.034
0.723
-0.478
-0.859
0.974
0.783
-0.538
-0.932
1.059
0.827
-0.567
-0.932
1.059
0.827
-0.567
-0.943
1.070
0.816
-0.556
-0.943
1.070
0.816
-0.556
-0.938
1.065
0.821
-0.561
-0.960
1.089
0.801
-0.539
-0.950
1.079
0.811
-0.549
-0.898
1.027
0.863
-0.601
-1.333 -1.464 -1.705 -1.645 -1.926 -1.477 -1.702 -1.646 -1.954
1.515 1.669 1.932 1.859 2.142 1.691 1.938 1.869 2.169
1.357 1.543 1.498 1.403 1.421 1.431 1.512 1.415 1.476
-0.967 -1.102 -1.012 -0.947 -0.955 -0.986 -1.016 -0.951 -1.010
-1.333 -1.464 -1.705 -1.645 -1.926 -1.477 -1.702 -1.646 -1.954
1.515 1.669 1.932 1.859 2.142 1.691 1.938 1.869 2.169
1.357 1.543 1.498 1.403 1.421 1.431 1.512 1.415 1.476
-0.967 -1.102 -1.012 -0.947 -0.955 -0.986 -1.016 -0.951 -1.010
-1.332 -1.466 -1.704 -1.644 -1.925 -1.477 -1.707 -1.651 -1.959
1.514 1.671 1.931 1.858 2.141 1.691 1.943 1.874 2.174
1.358 1.541 1.499 1.404 1.422 1.431 1.507 1.410 1.471
-0.968 -1.100 -1.013 -0.948 -0.956 -0.986 -1.011 -0.946 -1.005
-1.332 -1.466 -1.704 -1.644 -1.925 -1.477 -1.707 -1.651 -1.959
1.514 1.671 1.931 1.858 2.141 1.691 1.943 1.874 2.174
1.358 1.541 1.499 1.404 1.422 1.431 1.507 1.410 1.471
-0.968 -1.100 -1.013 -0.948 -0.956 -0.986 -1.011 -0.946 -1.005
-1.341 -1.478 -1.723 -1.663 -1.944 -1.487 -1.718 -1.662 -1.970
1.523 1.683 1.950 1.877 2.160 1.701 1.954 1.885 2.185
1.349 1.529 1.480 1.385 1.403 1.421 1.496 1.399 1.460
-0.959 -1.088 -0.994 -0.929 -0.937 -0.976 -1.000 -0.935 -0.994
-1.381 -1.514 -1.721 -1.661 -1.942 -1.521 -1.721 -1.665 -1.973
1.563 1.719 1.948 1.875 2.158 1.735 1.957 1.888 2.188
1.309 1.493 1.482 1.387 1.405 1.387 1.493 1.396 1.457
-0.919 -1.052 -0.996 -0.931 -0.939 -0.942 -0.997 -0.932 -0.991
-1.358 -1.482 -1.651 -1.591 -1.872 -1.490 -1.655 -1.599 -1.907
1.540 1.687 1.878 1.805 2.088 1.704 1.891 1.822 2.122
1.332 1.525 1.552 1.457 1.475 1.418 1.559 1.462 1.523
-0.942 -1.084 -1.066 -1.001 -1.009 -0.973 -1.063 -0.998 -1.057
-1.281 -1.383 -1.495 -1.435 -1.716 -1.394 -1.502 -1.446 -1.754
1.463 1.588 1.722 1.649 1.932 1.608 1.738 1.669 1.969
1.409 1.624 1.708 1.613 1.631 1.514 1.712 1.615 1.676
-1.019 -1.183 -1.222 -1.157 -1.165 -1.069 -1.216 -1.151 -1.210
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
3.3-V
LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–41
I4L
Table 1–43. EP3SL50 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
1.1V
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
0.9V
=
Industrial Commercial
1.1V
1.1V
1.1V
0.9V
1.1V
tsu
th
-0.840
0.955
0.802
-0.557
-0.840
0.955
0.802
-0.557
-0.833
0.948
0.809
-0.564
-0.833
0.948
0.809
-0.564
-0.821
0.936
0.821
-0.576
-0.821
0.936
0.821
-0.576
-0.833
0.948
0.809
-0.564
-0.833
0.948
0.809
-0.564
-0.821
0.936
0.821
-0.576
-0.869
0.998
0.892
-0.630
-0.869
0.998
0.892
-0.630
-0.863
0.992
0.898
-0.636
-0.863
0.992
0.898
-0.636
-0.852
0.981
0.909
-0.647
-0.852
0.981
0.909
-0.647
-0.863
0.992
0.898
-0.636
-0.863
0.992
0.898
-0.636
-0.852
0.981
0.909
-0.647
-1.253 -1.367 -1.497 -1.437 -1.718 -1.373 -1.498 -1.442 -1.750
1.435 1.572 1.724 1.651 1.934 1.587 1.734 1.665 1.965
1.437 1.640 1.706 1.611 1.629 1.535 1.716 1.619 1.680
-1.047 -1.199 -1.220 -1.155 -1.163 -1.090 -1.220 -1.155 -1.214
-1.253 -1.367 -1.497 -1.437 -1.718 -1.373 -1.498 -1.442 -1.750
1.435 1.572 1.724 1.651 1.934 1.587 1.734 1.665 1.965
1.437 1.640 1.706 1.611 1.629 1.535 1.716 1.619 1.680
-1.047 -1.199 -1.220 -1.155 -1.163 -1.090 -1.220 -1.155 -1.214
-1.240 -1.359 -1.494 -1.432 -1.716 -1.366 -1.499 -1.441 -1.751
1.422 1.561 1.718 1.645 1.927 1.577 1.731 1.663 1.961
1.449 1.645 1.709 1.616 1.631 1.542 1.715 1.620 1.679
-1.060 -1.207 -1.226 -1.161 -1.170 -1.100 -1.223 -1.157 -1.218
-1.240 -1.359 -1.494 -1.432 -1.716 -1.366 -1.499 -1.441 -1.751
1.422 1.561 1.718 1.645 1.927 1.577 1.731 1.663 1.961
1.449 1.645 1.709 1.616 1.631 1.542 1.715 1.620 1.679
-1.060 -1.207 -1.226 -1.161 -1.170 -1.100 -1.223 -1.157 -1.218
-1.229 -1.348 -1.475 -1.413 -1.697 -1.355 -1.481 -1.423 -1.733
1.410 1.550 1.699 1.626 1.908 1.566 1.713 1.645 1.943
1.458 1.656 1.728 1.635 1.650 1.553 1.733 1.638 1.697
-1.070 -1.218 -1.245 -1.180 -1.189 -1.111 -1.241 -1.175 -1.236
-1.229 -1.348 -1.475 -1.413 -1.697 -1.355 -1.481 -1.423 -1.733
1.410 1.550 1.699 1.626 1.908 1.566 1.713 1.645 1.943
1.458 1.656 1.728 1.635 1.650 1.553 1.733 1.638 1.697
-1.070 -1.218 -1.245 -1.180 -1.189 -1.111 -1.241 -1.175 -1.236
-1.240 -1.359 -1.494 -1.432 -1.716 -1.366 -1.499 -1.441 -1.751
1.422 1.561 1.718 1.645 1.927 1.577 1.731 1.663 1.961
1.449 1.645 1.709 1.616 1.631 1.542 1.715 1.620 1.679
-1.060 -1.207 -1.226 -1.161 -1.170 -1.100 -1.223 -1.157 -1.218
-1.240 -1.359 -1.494 -1.432 -1.716 -1.366 -1.499 -1.441 -1.751
1.422 1.561 1.718 1.645 1.927 1.577 1.731 1.663 1.961
1.449 1.645 1.709 1.616 1.631 1.542 1.715 1.620 1.679
-1.060 -1.207 -1.226 -1.161 -1.170 -1.100 -1.223 -1.157 -1.218
-1.229 -1.348 -1.475 -1.413 -1.697 -1.355 -1.481 -1.423 -1.733
1.410 1.550 1.699 1.626 1.908 1.566 1.713 1.645 1.943
1.458 1.656 1.728 1.635 1.650 1.553 1.733 1.638 1.697
-1.070 -1.218 -1.245 -1.180 -1.189 -1.111 -1.241 -1.175 -1.236
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-15
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V
HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V
HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V
HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V
HSTL
CLASS II
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–42
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–43. EP3SL50 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.821
0.936
0.821
-0.576
-0.813
0.928
0.829
-0.584
-0.813
0.928
0.829
-0.584
-0.918
1.031
0.724
-0.481
-0.852
0.981
0.909
-0.647
-0.840
0.969
0.921
-0.659
-0.840
0.969
0.921
-0.659
-0.943
1.070
0.816
-0.556
-1.229 -1.348 -1.475 -1.413 -1.697 -1.355 -1.481 -1.423 -1.733
1.410 1.550 1.699 1.626 1.908 1.566 1.713 1.645 1.943
1.458 1.656 1.728 1.635 1.650 1.553 1.733 1.638 1.697
-1.070 -1.218 -1.245 -1.180 -1.189 -1.111 -1.241 -1.175 -1.236
-1.219 -1.337 -1.459 -1.397 -1.681 -1.344 -1.466 -1.408 -1.718
1.400 1.539 1.683 1.610 1.892 1.555 1.698 1.630 1.928
1.468 1.667 1.744 1.651 1.666 1.564 1.748 1.653 1.712
-1.080 -1.229 -1.261 -1.196 -1.205 -1.122 -1.256 -1.190 -1.251
-1.219 -1.337 -1.459 -1.397 -1.681 -1.344 -1.466 -1.408 -1.718
1.400 1.539 1.683 1.610 1.892 1.555 1.698 1.630 1.928
1.468 1.667 1.744 1.651 1.666 1.564 1.748 1.653 1.712
-1.080 -1.229 -1.261 -1.196 -1.205 -1.122 -1.256 -1.190 -1.251
-1.332 -1.466 -1.704 -1.644 -1.925 -1.477 -1.707 -1.651 -1.959
1.514 1.671 1.931 1.858 2.141 1.691 1.943 1.874 2.174
1.358 1.541 1.499 1.404 1.422 1.431 1.507 1.410 1.471
-0.968 -1.100 -1.013 -0.948 -0.956 -0.986 -1.011 -0.946 -1.005
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
1.2-V
HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V
HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI-
X
tsu
th
GCLK
PLL
Table 1–44 specifies EP3SL50 row pins input timing parameters for single-ended I/O
standards.
Table 1–44. EP3SL50 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.884
0.997
0.910
-0.661
-0.884
0.997
0.910
-0.661
-0.890
1.003
0.904
-0.655
-0.914
1.040
0.917
-0.656
-0.914
1.040
0.917
-0.656
-0.925
1.051
0.906
-0.645
-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875
1.476 1.619 1.864 1.796 2.057 1.645 1.878 1.814 2.090
1.554 1.774 1.924 1.808 1.834 1.768 1.931 1.777 1.885
-1.157 -1.325 -1.424 -1.339 -1.358 -1.312 -1.421 -1.297 -1.407
-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875
1.476 1.619 1.864 1.796 2.057 1.645 1.878 1.814 2.090
1.554 1.774 1.924 1.808 1.834 1.768 1.931 1.777 1.885
-1.157 -1.325 -1.424 -1.339 -1.358 -1.312 -1.421 -1.297 -1.407
-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880
1.473 1.620 1.867 1.799 2.060 1.644 1.883 1.819 2.095
1.557 1.773 1.921 1.805 1.831 1.769 1.926 1.772 1.880
-1.160 -1.324 -1.421 -1.336 -1.355 -1.313 -1.416 -1.292 -1.402
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
3.3-V
LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVTTL
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–43
I4L
Table 1–44. EP3SL50 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
1.1V
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
1.1V
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
0.9V
0.9V
tsu
th
-0.890
1.003
0.904
-0.655
-0.878
0.991
0.916
-0.667
-0.940
1.054
0.930
-0.680
-0.930
1.044
0.940
-0.690
-0.870
0.984
1.000
-0.750
-0.821
0.935
0.973
-0.723
-0.821
0.935
0.973
-0.723
-0.844
0.958
1.026
-0.776
-0.844
0.958
1.026
-0.776
-0.925
1.051
0.906
-0.645
-0.918
1.044
0.913
-0.652
-0.982
1.109
0.925
-0.663
-0.971
1.098
0.936
-0.674
-0.918
1.045
0.989
-0.727
-0.860
0.987
0.971
-0.709
-0.860
0.987
0.971
-0.709
-0.883
1.010
1.024
-0.762
-0.883
1.010
1.024
-0.762
-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880
1.473 1.620 1.867 1.799 2.060 1.644 1.883 1.819 2.095
1.557 1.773 1.921 1.805 1.831 1.769 1.926 1.772 1.880
-1.160 -1.324 -1.421 -1.336 -1.355 -1.313 -1.416 -1.292 -1.402
-1.297 -1.426 -1.652 -1.598 -1.860 -1.436 -1.654 -1.603 -1.890
1.482 1.633 1.882 1.814 2.075 1.653 1.893 1.829 2.105
1.548 1.760 1.906 1.790 1.816 1.760 1.916 1.762 1.870
-1.151 -1.311 -1.406 -1.321 -1.340 -1.304 -1.406 -1.282 -1.392
-1.369 -1.491 -1.684 -1.629 -1.895 -1.501 -1.688 -1.635 -1.926
1.554 1.698 1.914 1.845 2.111 1.718 1.928 1.862 2.141
1.551 1.770 1.914 1.799 1.828 1.772 1.922 1.804 1.879
-1.154 -1.321 -1.414 -1.330 -1.351 -1.316 -1.411 -1.325 -1.401
-1.345 -1.459 -1.616 -1.561 -1.827 -1.470 -1.623 -1.570 -1.861
1.530 1.666 1.846 1.777 2.043 1.687 1.863 1.797 2.076
1.575 1.802 1.982 1.867 1.896 1.803 1.987 1.869 1.944
-1.178 -1.353 -1.482 -1.398 -1.419 -1.347 -1.476 -1.390 -1.466
-1.266 -1.358 -1.457 -1.402 -1.668 -1.374 -1.468 -1.415 -1.706
1.451 1.565 1.687 1.618 1.884 1.591 1.708 1.642 1.921
1.654 1.903 2.141 2.026 2.055 1.899 2.142 2.024 2.099
-1.257 -1.454 -1.641 -1.557 -1.578 -1.443 -1.631 -1.545 -1.621
-1.211 -1.317 -1.432 -1.378 -1.640 -1.324 -1.437 -1.386 -1.673
1.396 1.524 1.662 1.594 1.855 1.541 1.676 1.612 1.888
1.634 1.869 2.126 2.010 2.036 1.872 2.133 1.979 2.087
-1.237 -1.420 -1.626 -1.541 -1.560 -1.416 -1.623 -1.499 -1.609
-1.211 -1.317 -1.432 -1.378 -1.640 -1.324 -1.437 -1.386 -1.673
1.396 1.524 1.662 1.594 1.855 1.541 1.676 1.612 1.888
1.634 1.869 2.126 2.010 2.036 1.872 2.133 1.979 2.087
-1.237 -1.420 -1.626 -1.541 -1.560 -1.416 -1.623 -1.499 -1.609
-1.228 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699
1.413 1.536 1.680 1.611 1.876 1.557 1.698 1.633 1.910
1.692 1.930 2.146 2.032 2.059 1.931 2.149 2.032 2.106
-1.295 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632
-1.228 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699
1.413 1.536 1.680 1.611 1.876 1.557 1.698 1.633 1.910
1.692 1.930 2.146 2.032 2.059 1.931 2.149 2.032 2.106
-1.295 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–44
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–44. EP3SL50 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.830
0.944
1.040
-0.790
-0.844
0.958
1.026
-0.776
-0.844
0.958
1.026
-0.776
-0.830
0.944
1.040
-0.790
-0.830
0.944
1.040
-0.790
-0.821
0.935
1.049
-0.799
-0.821
0.935
1.049
-0.799
-0.890
1.003
0.904
-0.655
-0.890
1.003
0.904
-0.655
-0.871
0.998
1.036
-0.774
-0.883
1.010
1.024
-0.762
-0.883
1.010
1.024
-0.762
-0.871
0.998
1.036
-0.774
-0.871
0.998
1.036
-0.774
-0.859
0.986
1.048
-0.786
-0.859
0.986
1.048
-0.786
-0.925
1.051
0.906
-0.645
-0.925
1.051
0.906
-0.645
-1.213 -1.321 -1.434 -1.378 -1.646 -1.331 -1.444 -1.390 -1.682
1.399 1.526 1.662 1.593 1.858 1.546 1.681 1.616 1.893
1.707 1.940 2.164 2.050 2.077 1.942 2.166 2.049 2.123
-1.309 -1.493 -1.666 -1.582 -1.604 -1.488 -1.658 -1.571 -1.649
-1.228 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699
1.413 1.536 1.680 1.611 1.876 1.557 1.698 1.633 1.910
1.692 1.930 2.146 2.032 2.059 1.931 2.149 2.032 2.106
-1.295 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632
-1.228 -1.331 -1.452 -1.396 -1.664 -1.342 -1.461 -1.407 -1.699
1.413 1.536 1.680 1.611 1.876 1.557 1.698 1.633 1.910
1.692 1.930 2.146 2.032 2.059 1.931 2.149 2.032 2.106
-1.295 -1.483 -1.648 -1.564 -1.586 -1.477 -1.641 -1.554 -1.632
-1.213 -1.321 -1.434 -1.378 -1.646 -1.331 -1.444 -1.390 -1.682
1.399 1.526 1.662 1.593 1.858 1.546 1.681 1.616 1.893
1.707 1.940 2.164 2.050 2.077 1.942 2.166 2.049 2.123
-1.309 -1.493 -1.666 -1.582 -1.604 -1.488 -1.658 -1.571 -1.649
-1.213 -1.321 -1.434 -1.378 -1.646 -1.331 -1.444 -1.390 -1.682
1.399 1.526 1.662 1.593 1.858 1.546 1.681 1.616 1.893
1.707 1.940 2.164 2.050 2.077 1.942 2.166 2.049 2.123
-1.309 -1.493 -1.666 -1.582 -1.604 -1.488 -1.658 -1.571 -1.649
-1.204 -1.311 -1.418 -1.362 -1.630 -1.322 -1.428 -1.374 -1.666
1.390 1.516 1.646 1.577 1.842 1.537 1.665 1.600 1.877
1.716 1.950 2.180 2.066 2.093 1.951 2.182 2.065 2.139
-1.318 -1.503 -1.682 -1.598 -1.620 -1.497 -1.674 -1.587 -1.665
-1.204 -1.311 -1.418 -1.362 -1.630 -1.322 -1.428 -1.374 -1.666
1.390 1.516 1.646 1.577 1.842 1.537 1.665 1.600 1.877
1.716 1.950 2.180 2.066 2.093 1.951 2.182 2.065 2.139
-1.318 -1.503 -1.682 -1.598 -1.620 -1.497 -1.674 -1.587 -1.665
-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880
1.473 1.620 1.867 1.799 2.060 1.644 1.883 1.819 2.095
1.557 1.773 1.921 1.805 1.831 1.769 1.926 1.772 1.880
-1.160 -1.324 -1.421 -1.336 -1.355 -1.313 -1.416 -1.292 -1.402
-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880
1.473 1.620 1.867 1.799 2.060 1.644 1.883 1.819 2.095
1.557 1.773 1.921 1.805 1.831 1.769 1.926 1.772 1.880
-1.160 -1.324 -1.421 -1.336 -1.355 -1.313 -1.416 -1.292 -1.402
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
SSTL-15
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V
HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V
HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V
HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V
HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V
HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V
HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
PCI-X
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–45
I/O Timing
Table 1–45 specifies EP3SL50 column pins output timing parameters for single-ended
I/O standards.
Table 1–45. EP3SL50 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
Industrial Commercial
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK tco
3.018
1.583
2.939
1.505
2.910
1.474
2.896
1.460
2.956
1.521
2.885
1.449
2.860
1.425
2.853
1.419
3.016
1.580
2.949
1.515
2.911
1.476
2.889
1.453
3.239
1.767
3.150
1.678
3.118
1.645
3.104
1.630
3.172
1.700
3.095
1.622
3.067
1.594
3.060
1.587
3.248
1.776
3.163
1.691
3.126
1.653
3.099
1.626
4.510 4.896 5.390 5.257 5.485 5.018 5.510 5.380 5.555
2.207 2.312 2.529 2.534 2.475 2.422 2.640 2.644 2.463
4.407 4.784 5.273 5.140 5.368 4.902 5.390 5.260 5.435
2.104 2.201 2.412 2.417 2.358 2.307 2.520 2.524 2.343
4.340 4.714 5.203 5.070 5.298 4.832 5.323 5.193 5.368
2.037 2.130 2.342 2.347 2.288 2.237 2.452 2.456 2.275
4.319 4.691 5.175 5.042 5.270 4.806 5.290 5.160 5.335
2.016 2.106 2.314 2.319 2.260 2.209 2.418 2.422 2.241
4.437 4.813 5.302 5.169 5.397 4.932 5.422 5.292 5.467
2.135 2.230 2.442 2.447 2.388 2.337 2.552 2.556 2.375
4.315 4.687 5.171 5.038 5.266 4.802 5.285 5.155 5.330
2.012 2.103 2.310 2.315 2.256 2.206 2.414 2.418 2.237
4.286 4.660 5.146 5.013 5.241 4.775 5.260 5.130 5.305
1.983 2.076 2.284 2.289 2.230 2.178 2.388 2.392 2.211
4.278 4.651 5.137 5.004 5.232 4.766 5.251 5.121 5.296
1.974 2.067 2.275 2.280 2.221 2.169 2.378 2.382 2.201
4.544 4.932 5.429 5.296 5.524 5.057 5.552 5.422 5.597
2.241 2.349 2.588 2.593 2.534 2.461 2.681 2.685 2.504
4.440 4.821 5.313 5.180 5.408 4.942 5.434 5.304 5.479
2.138 2.238 2.494 2.499 2.440 2.347 2.563 2.567 2.386
4.372 4.749 5.239 5.106 5.334 4.868 5.358 5.228 5.403
2.069 2.165 2.430 2.435 2.376 2.272 2.486 2.490 2.309
4.337 4.710 5.197 5.064 5.292 4.828 5.314 5.184 5.359
2.034 2.127 2.407 2.412 2.353 2.232 2.443 2.447 2.266
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVTTL
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVTTL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–46
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–45. EP3SL50 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK tco
2.970
1.536
2.898
1.462
2.874
1.438
2.874
1.438
3.074
1.639
2.991
1.557
2.936
1.501
2.902
1.467
3.188
1.715
3.109
1.636
3.080
1.608
3.080
1.607
3.303
1.830
3.210
1.738
3.166
1.693
3.120
1.647
4.474 4.854 5.348 5.215 5.443 4.976 5.470 5.340 5.515
2.172 2.271 2.530 2.535 2.476 2.380 2.599 2.603 2.422
4.351 4.725 5.213 5.080 5.308 4.843 5.331 5.201 5.376
2.048 2.141 2.420 2.425 2.366 2.247 2.459 2.463 2.282
4.311 4.686 5.172 5.039 5.267 4.803 5.289 5.159 5.334
2.008 2.101 2.386 2.391 2.332 2.207 2.418 2.422 2.241
4.303 4.676 5.162 5.029 5.257 4.792 5.277 5.147 5.322
1.999 2.092 2.394 2.399 2.340 2.196 2.405 2.409 2.228
4.681 5.081 5.595 5.462 5.690 5.209 5.725 5.595 5.770
2.378 2.496 2.738 2.743 2.684 2.612 2.853 2.857 2.676
4.562 4.955 5.463 5.330 5.558 5.081 5.589 5.459 5.634
2.259 2.371 2.614 2.619 2.560 2.485 2.718 2.722 2.541
4.470 4.859 5.363 5.230 5.458 4.983 5.487 5.357 5.532
2.167 2.275 2.536 2.541 2.482 2.387 2.616 2.620 2.439
4.436 4.822 5.322 5.189 5.417 4.944 5.443 5.313 5.488
2.133 2.238 2.479 2.484 2.425 2.347 2.572 2.576 2.395
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
2.5 V
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–47
I/O Timing
Table 1–45. EP3SL50 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK tco
3.188
1.754
3.090
1.656
3.008
1.573
2.983
1.548
2.912
1.477
2.907
1.472
3.129
1.694
2.997
1.562
2.953
1.518
2.941
1.507
2.906
1.471
2.902
1.467
3.431
1.959
3.320
1.848
3.233
1.760
3.200
1.727
3.136
1.663
3.126
1.654
3.398
1.926
3.217
1.744
3.180
1.707
3.174
1.701
3.123
1.651
3.116
1.644
4.876 5.290 5.813 5.680 5.908 5.427 5.951 5.821 5.996
2.573 2.707 2.956 2.961 2.902 2.833 3.081 3.085 2.904
4.724 5.132 5.652 5.519 5.747 5.268 5.785 5.655 5.830
2.421 2.548 2.804 2.809 2.750 2.673 2.915 2.919 2.738
4.597 4.994 5.508 5.375 5.603 5.124 5.638 5.508 5.683
2.293 2.409 2.663 2.668 2.609 2.527 2.766 2.770 2.589
4.536 4.928 5.433 5.300 5.528 5.053 5.557 5.427 5.602
2.233 2.344 2.584 2.589 2.530 2.457 2.686 2.690 2.509
4.448 4.834 5.334 5.201 5.429 4.956 5.456 5.326 5.501
2.145 2.250 2.502 2.507 2.448 2.360 2.585 2.589 2.408
4.442 4.828 5.327 5.194 5.422 4.949 5.449 5.319 5.494
2.139 2.244 2.496 2.501 2.442 2.353 2.578 2.582 2.401
4.814 5.217 5.741 5.608 5.836 5.357 5.884 5.754 5.929
2.512 2.635 2.895 2.900 2.841 2.762 3.014 3.018 2.837
4.571 4.963 5.470 5.337 5.565 5.089 5.598 5.468 5.643
2.267 2.378 2.626 2.631 2.572 2.493 2.726 2.730 2.549
4.490 4.883 5.390 5.257 5.485 5.009 5.515 5.385 5.560
2.187 2.299 2.564 2.569 2.510 2.413 2.643 2.647 2.466
4.484 4.876 5.381 5.248 5.476 5.002 5.507 5.377 5.552
2.181 2.291 2.557 2.562 2.503 2.406 2.635 2.639 2.458
4.436 4.822 5.320 5.187 5.415 4.943 5.442 5.312 5.487
2.133 2.238 2.498 2.503 2.444 2.347 2.571 2.575 2.394
4.416 4.801 5.300 5.167 5.395 4.922 5.421 5.291 5.466
2.112 2.216 2.495 2.500 2.441 2.326 2.549 2.553 2.372
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.8 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–48
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–45. EP3SL50 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK tco
3.108
1.674
2.986
1.551
2.933
1.497
2.912
1.477
2.926
1.491
2.929
1.494
2.910
1.475
2.905
1.470
2.944
1.509
2.925
1.490
2.926
1.491
2.909
1.474
2.905
1.470
3.341
1.869
3.206
1.733
3.165
1.692
3.131
1.658
3.139
1.666
3.142
1.669
3.122
1.649
3.115
1.642
3.159
1.686
3.138
1.666
3.141
1.668
3.121
1.648
3.117
1.645
4.768 5.171 5.684 5.551 5.779 5.304 5.818 5.688 5.863
2.466 2.588 2.841 2.846 2.787 2.709 2.949 2.953 2.772
4.549 4.940 5.444 5.311 5.539 5.065 5.570 5.440 5.615
2.246 2.355 2.617 2.622 2.563 2.469 2.698 2.702 2.521
4.473 4.863 5.370 5.237 5.465 4.990 5.497 5.367 5.542
2.170 2.279 2.563 2.568 2.509 2.394 2.625 2.629 2.448
4.434 4.820 5.320 5.187 5.415 4.941 5.440 5.310 5.485
2.131 2.236 2.528 2.533 2.474 2.345 2.569 2.573 2.392
4.442 4.828 5.328 5.195 5.423 4.947 5.445 5.315 5.490
2.138 2.243 2.520 2.525 2.466 2.349 2.573 2.577 2.396
4.446 4.832 5.332 5.199 5.427 4.950 5.449 5.319 5.494
2.142 2.247 2.526 2.531 2.472 2.353 2.577 2.581 2.400
4.425 4.810 5.310 5.177 5.405 4.929 5.427 5.297 5.472
2.120 2.226 2.499 2.504 2.445 2.332 2.555 2.559 2.378
4.410 4.794 5.293 5.160 5.388 4.912 5.410 5.280 5.455
2.105 2.209 2.497 2.502 2.443 2.315 2.537 2.541 2.360
4.465 4.851 5.351 5.218 5.446 4.970 5.469 5.339 5.514
2.161 2.266 2.550 2.555 2.496 2.373 2.596 2.600 2.419
4.443 4.829 5.329 5.196 5.424 4.948 5.446 5.316 5.491
2.139 2.244 2.526 2.531 2.472 2.351 2.574 2.578 2.397
4.451 4.838 5.339 5.206 5.434 4.958 5.457 5.327 5.502
2.147 2.253 2.546 2.551 2.492 2.361 2.585 2.589 2.408
4.427 4.813 5.314 5.181 5.409 4.932 5.432 5.302 5.477
2.123 2.228 2.521 2.526 2.467 2.335 2.560 2.564 2.383
4.423 4.809 5.309 5.176 5.404 4.928 5.428 5.298 5.473
2.119 2.224 2.516 2.521 2.462 2.331 2.556 2.560 2.379
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2mA
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
1.2 V
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS I
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–49
I/O Timing
Table 1–45. EP3SL50 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK tco
2.906
1.470
2.905
1.469
2.935
1.500
2.920
1.485
2.907
1.472
2.908
1.472
2.903
1.468
2.921
1.486
2.920
1.485
3.116
1.643
3.116
1.643
3.150
1.677
3.134
1.661
3.119
1.647
3.120
1.647
3.115
1.642
3.132
1.659
3.132
1.659
4.410 4.795 5.293 5.160 5.388 4.913 5.410 5.280 5.455
2.106 2.210 2.501 2.506 2.447 2.316 2.538 2.542 2.361
4.418 4.805 5.305 5.172 5.400 4.923 5.423 5.293 5.468
2.114 2.220 2.508 2.513 2.454 2.326 2.551 2.555 2.374
4.458 4.844 5.343 5.210 5.438 4.963 5.461 5.331 5.506
2.153 2.258 2.543 2.548 2.489 2.366 2.589 2.593 2.412
4.444 4.831 5.331 5.198 5.426 4.950 5.450 5.320 5.495
2.140 2.246 2.539 2.544 2.485 2.354 2.578 2.582 2.401
4.424 4.810 5.311 5.178 5.406 4.930 5.429 5.299 5.474
2.120 2.226 2.521 2.526 2.467 2.333 2.557 2.561 2.380
4.425 4.812 5.314 5.181 5.409 4.932 5.432 5.302 5.477
2.121 2.227 2.532 2.537 2.478 2.335 2.560 2.564 2.383
4.418 4.805 5.306 5.173 5.401 4.924 5.424 5.294 5.469
2.114 2.220 2.524 2.529 2.470 2.327 2.552 2.556 2.375
4.426 4.810 5.308 5.175 5.403 4.928 5.425 5.295 5.470
2.121 2.225 2.512 2.517 2.458 2.331 2.553 2.557 2.376
4.430 4.815 5.314 5.181 5.409 4.933 5.431 5.301 5.476
2.126 2.230 2.530 2.535 2.476 2.337 2.559 2.563 2.382
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8mA
GCLK
tco
PLL
SSTL-18
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-15
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
SSTL-15
CLASS II
GCLK tco
16mA
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–50
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–45. EP3SL50 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK tco
2.907
1.472
2.903
1.467
2.905
1.469
2.904
1.469
2.922
1.487
2.917
1.482
2.917
1.481
2.907
1.472
2.909
1.474
2.931
1.495
2.920
1.485
2.919
1.483
3.118
1.645
3.113
1.640
3.116
1.643
3.114
1.641
3.133
1.660
3.129
1.656
3.128
1.656
3.118
1.645
3.120
1.648
3.145
1.672
3.133
1.660
3.131
1.659
4.414 4.799 5.298 5.165 5.393 4.917 5.415 5.285 5.460
2.110 2.214 2.512 2.517 2.458 2.320 2.543 2.547 2.366
4.408 4.793 5.292 5.159 5.387 4.911 5.409 5.279 5.454
2.104 2.208 2.501 2.506 2.447 2.314 2.537 2.541 2.360
4.413 4.798 5.298 5.165 5.393 4.917 5.416 5.286 5.461
2.109 2.214 2.522 2.527 2.468 2.320 2.543 2.547 2.366
4.406 4.791 5.290 5.157 5.385 4.909 5.407 5.277 5.452
2.102 2.206 2.503 2.508 2.449 2.312 2.534 2.538 2.357
4.428 4.812 5.311 5.178 5.406 4.931 5.428 5.298 5.473
2.124 2.227 2.517 2.522 2.463 2.333 2.555 2.559 2.378
4.426 4.811 5.310 5.177 5.405 4.930 5.427 5.297 5.472
2.122 2.226 2.524 2.529 2.470 2.333 2.555 2.559 2.378
4.427 4.812 5.311 5.178 5.406 4.931 5.428 5.298 5.473
2.123 2.227 2.525 2.530 2.471 2.334 2.556 2.560 2.379
4.415 4.800 5.299 5.166 5.394 4.918 5.416 5.286 5.461
2.110 2.215 2.512 2.517 2.458 2.321 2.544 2.548 2.367
4.420 4.807 5.307 5.174 5.402 4.925 5.425 5.295 5.470
2.116 2.221 2.527 2.532 2.473 2.328 2.552 2.556 2.375
4.448 4.834 5.333 5.200 5.428 4.953 5.452 5.322 5.497
2.144 2.249 2.545 2.550 2.491 2.356 2.579 2.583 2.402
4.436 4.822 5.322 5.189 5.417 4.941 5.440 5.310 5.485
2.132 2.237 2.535 2.540 2.481 2.344 2.568 2.572 2.391
4.434 4.820 5.320 5.187 5.415 4.940 5.439 5.309 5.484
2.130 2.236 2.540 2.545 2.486 2.343 2.567 2.571 2.390
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
8mA
GCLK
tco
CLASS I
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
8mA
GCLK
tco
CLASS I
PLL
GCLK tco
10mA
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
GCLK
tco
CLASS II
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–51
I/O Timing
Table 1–45. EP3SL50 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK tco
2.916
1.481
2.912
1.477
2.989
1.554
2.989
1.554
3.018
1.583
2.939
1.505
2.910
1.474
2.896
1.460
3.129
1.656
3.125
1.652
3.200
1.727
3.200
1.727
3.239
1.767
3.150
1.678
3.118
1.645
3.104
1.630
4.433 4.820 5.320 5.187 5.415 4.939 5.439 5.309 5.484 ns
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
ns
ns
ns
ns
2.128 2.235 2.542 2.547 2.488 2.342 2.566 2.570 2.389
4.427 4.813 5.313 5.180 5.408 4.932 5.432 5.302 5.477
2.122 2.228 2.533 2.538 2.479 2.335 2.559 2.563 2.382
4.444 4.821 5.310 5.177 5.405 4.940 5.429 5.299 5.474
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS I
GCLK
tco
2.141 2.237 2.509 2.514 2.455 2.344 2.558 2.562 2.381 ns
4.444 4.821 5.310 5.177 5.405 4.940 5.429 5.299 5.474 ns
PLL
GCLK tco
GCLK
tco
ns
ns
ns
ns
2.141 2.237 2.509 2.514 2.455 2.344 2.558 2.562 2.381
4.510 4.896 5.390 5.257 5.485 5.018 5.510 5.380 5.555
2.207 2.312 2.529 2.534 2.475 2.422 2.640 2.644 2.463
4.407 4.784 5.273 5.140 5.368 4.902 5.390 5.260 5.435
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS II
GCLK
tco
2.104 2.201 2.412 2.417 2.358 2.307 2.520 2.524 2.343 ns
PLL
ns
ns
ns
ns
GCLK tco
4.340 4.714 5.203 5.070 5.298 4.832 5.323 5.193 5.368
2.037 2.130 2.342 2.347 2.288 2.237 2.452 2.456 2.275
4.319 4.691 5.175 5.042 5.270 4.806 5.290 5.160 5.335
2.016 2.106 2.314 2.319 2.260 2.209 2.418 2.422 2.241
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–52
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–46 specifies EP3SL50 row pins output timing parameters for single-ended I/O
standards.
Table 1–46. EP3SL50 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standar
d
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.197
1.482
3.104
1.415
3.014
1.336
3.207
1.492
3.018
1.340
3.151
1.442
3.026
1.341
2.987
1.304
3.065
1.363
2.969
1.291
3.177
1.468
3.067
1.383
3.021
1.326
3.438
1.677
3.333
1.606
3.233
1.517
3.442
1.684
3.237
1.521
3.384
1.638
3.257
1.526
3.206
1.488
3.303
1.550
3.188
1.472
3.420
1.675
3.321
1.572
3.245
1.528
4.781 5.176 5.684 5.549 5.751 5.305 5.818 5.682 5.828
2.061 2.175 2.372 2.388 2.308 2.295 2.495 2.512 2.303
4.651 5.038 5.540 5.405 5.607 5.164 5.669 5.533 5.679
1.951 2.037 2.228 2.244 2.164 2.154 2.346 2.363 2.154
4.532 4.915 5.412 5.277 5.479 5.037 5.537 5.401 5.547
1.845 1.930 2.100 2.116 2.036 2.046 2.214 2.260 2.022
4.789 5.181 5.689 5.554 5.756 5.311 5.823 5.687 5.833
2.065 2.180 2.377 2.393 2.313 2.301 2.500 2.517 2.308
4.538 4.921 5.418 5.283 5.485 5.043 5.544 5.408 5.554
1.856 1.945 2.106 2.122 2.042 2.058 2.221 2.269 2.029
4.733 5.129 5.641 5.506 5.708 5.262 5.776 5.640 5.786
2.028 2.128 2.329 2.345 2.265 2.252 2.453 2.470 2.261
4.580 4.970 5.477 5.342 5.544 5.100 5.612 5.475 5.621
1.891 1.969 2.165 2.181 2.101 2.090 2.289 2.305 2.096
4.498 4.887 5.389 5.254 5.456 5.014 5.519 5.382 5.528
1.831 1.903 2.077 2.093 2.013 2.016 2.196 2.222 2.003
4.627 5.022 5.530 5.395 5.597 5.154 5.665 5.528 5.674
1.926 2.021 2.218 2.234 2.154 2.144 2.342 2.358 2.149
4.463 4.848 5.350 5.215 5.417 4.974 5.479 5.342 5.488
1.803 1.874 2.038 2.054 1.974 1.986 2.156 2.193 1.963
4.865 5.283 5.813 5.678 5.880 5.422 5.955 5.818 5.964
2.136 2.282 2.501 2.517 2.437 2.412 2.632 2.648 2.439
4.710 5.120 5.643 5.508 5.710 5.255 5.781 5.644 5.790
2.012 2.119 2.331 2.347 2.267 2.245 2.458 2.474 2.265
4.599 5.001 5.517 5.382 5.584 5.132 5.651 5.514 5.660
1.928 2.015 2.205 2.221 2.141 2.132 2.328 2.354 2.135
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
GCLK
PLL
GCLK
3.3-V
LVTTL
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–53
I/O Timing
Table 1–46. EP3SL50 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standar
d
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.410
1.695
3.191
1.470
3.120
1.405
3.098
1.367
3.321
1.606
3.114
1.383
3.087
1.356
3.068
1.337
3.264
1.549
3.119
1.388
3.008
1.330
3.003
1.325
2.994
1.316
3.667
1.941
3.465
1.739
3.363
1.637
3.327
1.563
3.585
1.859
3.344
1.602
3.318
1.554
3.307
1.545
3.510
1.784
3.348
1.595
3.232
1.516
3.228
1.512
3.217
1.501
5.251 5.711 6.288 6.153 6.355 5.859 6.439 6.303 6.449
2.589 2.710 2.976 2.992 2.912 2.849 3.116 3.133 2.924
4.924 5.343 5.883 5.748 5.950 5.494 6.033 5.896 6.042
2.262 2.342 2.571 2.587 2.507 2.484 2.710 2.726 2.517
4.771 5.193 5.724 5.589 5.791 5.326 5.860 5.724 5.870
2.109 2.192 2.412 2.428 2.348 2.316 2.537 2.554 2.345
4.698 5.111 5.630 5.494 5.701 5.242 5.766 5.630 5.776
2.032 2.099 2.316 2.332 2.252 2.221 2.443 2.460 2.251
5.161 5.625 6.216 6.081 6.283 5.766 6.363 6.227 6.373
2.499 2.624 2.904 2.920 2.840 2.756 3.040 3.057 2.848
4.756 5.188 5.725 5.590 5.792 5.320 5.859 5.723 5.869
2.094 2.187 2.413 2.429 2.349 2.310 2.536 2.553 2.344
4.683 5.103 5.630 5.494 5.701 5.235 5.762 5.627 5.773
2.021 2.091 2.307 2.323 2.243 2.212 2.431 2.448 2.239
4.666 5.079 5.611 5.475 5.682 5.211 5.743 5.608 5.754
1.999 2.073 2.288 2.304 2.224 2.194 2.409 2.426 2.217
5.071 5.539 6.141 6.006 6.208 5.678 6.279 6.143 6.289
2.409 2.538 2.829 2.845 2.765 2.668 2.956 2.973 2.764
4.778 5.216 5.766 5.631 5.833 5.345 5.901 5.765 5.911
2.116 2.215 2.454 2.470 2.390 2.335 2.578 2.595 2.386
4.577 4.973 5.485 5.350 5.552 5.099 5.613 5.477 5.623
1.921 2.006 2.173 2.189 2.109 2.119 2.290 2.340 2.098
4.571 4.968 5.477 5.342 5.544 5.095 5.606 5.470 5.616
1.918 2.004 2.166 2.184 2.106 2.118 2.284 2.339 2.096
4.556 4.952 5.450 5.315 5.517 5.078 5.579 5.452 5.589
1.903 1.988 2.149 2.167 2.089 2.101 2.266 2.321 2.078
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2mA
4mA
6mA
8mA
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
1.8 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-2
CLASS I
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–54
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–46. EP3SL50 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standar
d
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.047
1.316
3.042
1.311
3.031
1.300
3.020
1.289
3.020
1.289
3.028
1.297
3.029
1.298
3.050
1.319
3.036
1.305
3.025
1.294
3.271
1.519
3.266
1.505
3.255
1.493
3.244
1.476
3.243
1.475
3.250
1.482
3.253
1.485
3.274
1.515
3.260
1.493
3.248
1.480
4.617 5.015 5.525 5.389 5.596 5.141 5.653 5.518 5.664
1.927 1.998 2.198 2.216 2.138 2.111 2.316 2.333 2.127
4.615 5.014 5.524 5.388 5.595 5.139 5.651 5.516 5.662
1.924 1.997 2.197 2.215 2.137 2.109 2.314 2.331 2.125
4.605 5.004 5.514 5.378 5.585 5.130 5.642 5.507 5.653
1.907 1.987 2.187 2.205 2.127 2.100 2.305 2.322 2.116
4.592 4.991 5.501 5.365 5.572 5.118 5.630 5.495 5.641
1.891 1.974 2.174 2.192 2.114 2.088 2.293 2.310 2.104
4.592 4.991 5.501 5.365 5.572 5.117 5.630 5.495 5.641
1.890 1.974 2.174 2.192 2.114 2.087 2.293 2.310 2.104
4.591 4.988 5.496 5.360 5.567 5.113 5.624 5.489 5.635
1.888 1.971 2.169 2.187 2.109 2.083 2.287 2.304 2.098
4.597 4.996 5.506 5.370 5.577 5.122 5.635 5.500 5.646
1.892 1.979 2.179 2.197 2.119 2.092 2.298 2.315 2.109
4.626 5.026 5.538 5.402 5.609 5.151 5.665 5.530 5.676
1.938 2.009 2.211 2.229 2.151 2.121 2.328 2.345 2.139
4.615 5.016 5.528 5.392 5.599 5.142 5.656 5.521 5.667
1.920 1.999 2.201 2.219 2.141 2.112 2.319 2.336 2.130
4.602 5.003 5.515 5.379 5.586 5.129 5.643 5.508 5.654
1.903 1.986 2.188 2.206 2.128 2.099 2.306 2.323 2.117
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4mA
6mA
8mA
10mA
12mA
8mA
16mA
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-18
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–55
I/O Timing
Table 1–46. EP3SL50 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standar
d
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.035
1.304
3.028
1.297
3.019
1.288
3.022
1.291
3.018
1.287
3.026
1.295
3.041
1.310
3.035
1.304
3.031
1.300
3.043
1.312
3.034
1.303
3.033
1.302
3.114
1.436
3.114
1.436
3.256
1.491
3.250
1.482
3.242
1.474
3.244
1.476
3.241
1.473
3.249
1.481
3.262
1.498
3.257
1.489
3.253
1.485
3.264
1.497
3.256
1.488
3.256
1.488
3.338
1.622
3.338
1.622
4.590 4.986 5.494 5.358 5.565 5.112 5.621 5.486 5.632
1.894 1.969 2.167 2.185 2.107 2.082 2.284 2.301 2.095
4.588 4.985 5.493 5.357 5.564 5.111 5.621 5.486 5.632
1.885 1.968 2.166 2.184 2.106 2.081 2.284 2.301 2.095
4.581 4.978 5.486 5.350 5.557 5.104 5.614 5.479 5.625
1.877 1.961 2.159 2.177 2.099 2.074 2.277 2.294 2.088
4.584 4.981 5.490 5.354 5.561 5.107 5.617 5.482 5.628
1.879 1.964 2.163 2.181 2.103 2.077 2.280 2.297 2.091
4.586 4.984 5.493 5.357 5.564 5.110 5.622 5.487 5.633
1.881 1.967 2.166 2.184 2.106 2.080 2.285 2.302 2.096
4.584 4.981 5.489 5.353 5.560 5.106 5.616 5.481 5.627
1.879 1.964 2.162 2.180 2.102 2.076 2.279 2.296 2.090
4.599 4.996 5.505 5.369 5.576 5.121 5.632 5.497 5.643
1.905 1.979 2.178 2.196 2.118 2.091 2.295 2.312 2.106
4.600 4.998 5.507 5.371 5.578 5.123 5.635 5.500 5.646
1.901 1.981 2.180 2.198 2.120 2.093 2.298 2.315 2.109
4.595 4.993 5.502 5.366 5.573 5.118 5.629 5.494 5.640
1.895 1.976 2.175 2.193 2.115 2.088 2.292 2.309 2.103
4.612 5.012 5.524 5.388 5.595 5.137 5.651 5.516 5.662
1.916 1.995 2.197 2.215 2.137 2.107 2.314 2.331 2.125
4.603 5.003 5.515 5.379 5.586 5.128 5.642 5.507 5.653
1.905 1.986 2.188 2.206 2.128 2.098 2.305 2.322 2.116
4.610 5.011 5.524 5.388 5.595 5.137 5.652 5.517 5.663
1.909 1.994 2.197 2.215 2.137 2.107 2.315 2.332 2.126
4.626 5.016 5.494 5.359 5.561 5.144 5.625 5.513 5.635
1.973 2.052 2.208 2.226 2.148 2.167 2.327 2.382 2.139
4.626 5.016 5.494 5.359 5.561 5.144 5.625 5.513 5.635
1.973 2.052 2.208 2.226 2.148 2.167 2.327 2.382 2.139
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
—
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
1.5-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V
PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–56
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–47 through Table 1–50 show the maximum I/O timing parameters for
EP3SL50 devices for differential I/O standards.
Table 1–47 specifies EP3SL50 column pins input timing parameters for differential
I/O standards.
Table 1–47. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.697
0.814
1.143
-0.892
-0.697
0.814
1.143
-0.892
-0.705
0.822
1.135
-0.884
-0.705
0.822
1.135
-0.884
-0.717
0.834
1.123
-0.872
-0.717
0.834
1.123
-0.872
-0.705
0.822
1.135
-0.884
-0.705
0.822
1.135
-0.884
-0.717
0.849
1.159
-0.893
-0.717
0.849
1.159
-0.893
-0.729
0.861
1.147
-0.881
-0.729
0.861
1.147
-0.881
-0.740
0.872
1.136
-0.870
-0.740
0.872
1.136
-0.870
-0.729
0.861
1.147
-0.881
-0.729
0.861
1.147
-0.881
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 ns
GCLK
1.257 1.389 1.522 1.454 1.740 1.398 1.532 1.469 1.777
1.821 2.053 2.279 2.166 2.172 2.063 2.288 2.173 2.219
ns
ns
LVDS
GCLK
PLL
tsu
th
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 ns
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 ns
tsu
th
GCLK
1.257 1.389 1.522 1.454 1.740 1.398 1.532 1.469 1.777
1.821 2.053 2.279 2.166 2.172 2.063 2.288 2.173 2.219
ns
ns
MINI-LVDS
GCLK
tsu
th
PLL
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
RSDS
GCLK
PLL
tsu
th
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
1.277 1.411 1.557 1.489 1.775 1.420 1.565 1.502 1.810
1.802 2.031 2.244 2.131 2.137 2.041 2.255 2.140 2.186
ns
ns
tsu
th
GCLK
PLL
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 ns
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
1.277 1.411 1.557 1.489 1.775 1.420 1.565 1.502 1.810
1.802 2.031 2.244 2.131 2.137 2.041 2.255 2.140 2.186
ns
ns
tsu
th
GCLK
PLL
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–57
I/O Timing
Table 1–47. EP3SL50 Column Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.717
0.834
1.123
-0.872
-0.717
0.834
1.123
-0.872
-0.724
0.841
1.116
-0.865
-0.724
0.841
1.116
-0.865
-0.697
0.814
1.143
-0.892
-0.697
0.814
1.143
-0.892
-0.705
0.822
1.135
-0.884
-0.740
0.872
1.136
-0.870
-0.740
0.872
1.136
-0.870
-0.746
0.878
1.130
-0.864
-0.746
0.878
1.130
-0.864
-0.717
0.849
1.159
-0.893
-0.717
0.849
1.159
-0.893
-0.729
0.861
1.147
-0.881
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
1.277 1.411 1.557 1.489 1.775 1.420 1.565 1.502 1.810
1.802 2.031 2.244 2.131 2.137 2.041 2.255 2.140 2.186
ns
ns
tsu
th
GCLK
PLL
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 ns
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
1.277 1.411 1.557 1.489 1.775 1.420 1.565 1.502 1.810
1.802 2.031 2.244 2.131 2.137 2.041 2.255 2.140 2.186
ns
ns
tsu
th
GCLK
PLL
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 ns
-1.103 -1.209 -1.329 -1.274 -1.558 -1.209 -1.324 -1.273 -1.591 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
1.290 1.419 1.560 1.492 1.779 1.427 1.565 1.501 1.811
1.790 2.026 2.244 2.129 2.138 2.037 2.260 2.142 2.190
ns
ns
tsu
th
GCLK
PLL
-1.391 -1.576 -1.743 -1.658 -1.657 -1.579 -1.749 -1.662 -1.708 ns
-1.103 -1.209 -1.329 -1.274 -1.558 -1.209 -1.324 -1.273 -1.591 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
1.290 1.419 1.560 1.492 1.779 1.427 1.565 1.501 1.811
1.790 2.026 2.244 2.129 2.138 2.037 2.260 2.142 2.190
ns
ns
tsu
th
GCLK
PLL
-1.391 -1.576 -1.743 -1.658 -1.657 -1.579 -1.749 -1.662 -1.708 ns
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
1.257 1.389 1.522 1.454 1.740 1.398 1.532 1.469 1.777
1.821 2.053 2.279 2.166 2.172 2.063 2.288 2.173 2.219
ns
ns
tsu
th
GCLK
PLL
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 ns
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
1.257 1.389 1.522 1.454 1.740 1.398 1.532 1.469 1.777
1.821 2.053 2.279 2.166 2.172 2.063 2.288 2.173 2.219
ns
ns
tsu
th
GCLK
PLL
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–58
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–48 specifies EP3SL50 row pins input timing parameters for differential I/O
standards.
Table 1–48. EP3SL50 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.919
1.042
0.882
-0.625
-0.919
1.042
0.882
-0.625
-0.919
1.042
0.882
-0.625
-0.734
0.850
1.077
-0.827
-0.734
0.850
1.077
-0.827
-0.743
0.859
1.068
-0.818
-0.743
0.859
1.068
-0.818
-0.757
0.873
1.054
-0.804
-0.939
1.077
0.896
-0.625
-0.939
1.077
0.896
-0.625
-0.939
1.077
0.896
-0.625
-0.764
0.893
1.081
-0.819
-0.764
0.893
1.081
-0.819
-0.776
0.905
1.069
-0.807
-0.776
0.905
1.069
-0.807
-0.788
0.917
1.057
-0.795
-0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 ns
GCLK
1.209 1.205 1.369 1.306 1.580 1.182 1.339 1.280 1.613
1.863 2.243 2.446 2.322 2.342 2.291 2.500 2.376 2.393
ns
ns
LVDS
GCLK
PLL
tsu
th
-1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 ns
-0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 ns
tsu
th
GCLK
1.209 1.205 1.369 1.306 1.580 1.182 1.339 1.280 1.613
1.863 2.243 2.446 2.322 2.342 2.291 2.500 2.376 2.393
ns
ns
MINI-LVDS
GCLK
tsu
th
PLL
-1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 ns
-0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 ns
tsu
th
GCLK
1.209 1.205 1.369 1.306 1.580 1.182 1.339 1.280 1.613
1.863 2.243 2.446 2.322 2.342 2.291 2.500 2.376 2.393
ns
ns
RSDS
GCLK
PLL
tsu
th
-1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 ns
-1.085 -1.186 -1.286 -1.234 -1.505 -1.193 -1.291 -1.242 -1.543 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS I
1.274 1.394 1.516 1.451 1.720 1.410 1.531 1.470 1.758
1.776 2.019 2.257 2.138 2.163 2.024 2.263 2.144 2.209
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.570 -1.756 -1.667 -1.687 -1.565 -1.751 -1.663 -1.730 ns
-1.085 -1.186 -1.286 -1.234 -1.505 -1.193 -1.291 -1.242 -1.543 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS II
1.274 1.394 1.516 1.451 1.720 1.410 1.531 1.470 1.758
1.776 2.019 2.257 2.138 2.163 2.024 2.263 2.144 2.209
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.570 -1.756 -1.667 -1.687 -1.565 -1.751 -1.663 -1.730 ns
-1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS I
1.283 1.404 1.532 1.467 1.736 1.419 1.547 1.486 1.774
1.767 2.009 2.241 2.122 2.147 2.015 2.247 2.128 2.193
ns
ns
tsu
th
GCLK
PLL
-1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 ns
-1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS II
1.283 1.404 1.532 1.467 1.736 1.419 1.547 1.486 1.774
1.767 2.009 2.241 2.122 2.147 2.015 2.247 2.128 2.193
ns
ns
tsu
th
GCLK
PLL
-1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 ns
-1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS I
1.295 1.414 1.550 1.485 1.754 1.430 1.564 1.503 1.791
1.754 1.999 2.223 2.104 2.129 2.004 2.230 2.111 2.176
ns
ns
tsu
th
GCLK
PLL
-1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–59
I/O Timing
Table 1–48. EP3SL50 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.757
0.873
1.054
-0.804
-0.743
0.859
1.068
-0.818
-0.743
0.859
1.068
-0.818
-0.757
0.873
1.054
-0.804
-0.757
0.873
1.054
-0.804
-0.756
0.872
1.045
-0.795
-0.756
0.872
1.045
-0.795
-0.788
0.917
1.057
-0.795
-0.776
0.905
1.069
-0.807
-0.776
0.905
1.069
-0.807
-0.788
0.917
1.057
-0.795
-0.788
0.917
1.057
-0.795
-0.787
0.916
1.048
-0.786
-0.787
0.916
1.048
-0.786
-1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ns
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS II
1.295 1.414 1.550 1.485 1.754 1.430 1.564 1.503 1.791
1.754 1.999 2.223 2.104 2.129 2.004 2.230 2.111 2.176
ns
ns
tsu
th
GCLK
PLL
-1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 ns
-1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS I
1.283 1.404 1.532 1.467 1.736 1.419 1.547 1.486 1.774
1.767 2.009 2.241 2.122 2.147 2.015 2.247 2.128 2.193
ns
ns
tsu
th
GCLK
PLL
-1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 ns
-1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS II
1.283 1.404 1.532 1.467 1.736 1.419 1.547 1.486 1.774
1.767 2.009 2.241 2.122 2.147 2.015 2.247 2.128 2.193
ns
ns
tsu
th
GCLK
PLL
-1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 ns
-1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS I
1.295 1.414 1.550 1.485 1.754 1.430 1.564 1.503 1.791
1.754 1.999 2.223 2.104 2.129 2.004 2.230 2.111 2.176
ns
ns
tsu
th
GCLK
PLL
-1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 ns
-1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS II
1.295 1.414 1.550 1.485 1.754 1.430 1.564 1.503 1.791
1.754 1.999 2.223 2.104 2.129 2.004 2.230 2.111 2.176
ns
ns
tsu
th
GCLK
PLL
-1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 ns
-1.112 -1.212 -1.321 -1.270 -1.540 -1.214 -1.320 -1.273 -1.573 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS I
1.300 1.422 1.554 1.489 1.759 1.434 1.563 1.502 1.792
1.739 1.983 2.212 2.092 2.118 1.993 2.224 2.103 2.169
ns
ns
tsu
th
GCLK
PLL
-1.339 -1.532 -1.708 -1.619 -1.638 -1.531 -1.709 -1.621 -1.686 ns
-1.112 -1.212 -1.321 -1.270 -1.540 -1.214 -1.320 -1.273 -1.573 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS II
1.300 1.422 1.554 1.489 1.759 1.434 1.563 1.502 1.792
1.739 1.983 2.212 2.092 2.118 1.993 2.224 2.103 2.169
ns
ns
tsu
th
GCLK
PLL
-1.339 -1.532 -1.708 -1.619 -1.638 -1.531 -1.709 -1.621 -1.686 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–60
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–49 specifies EP3SL50 Column Pins Output Timing parameters for differential
I/O standards.
Table 1–49. EP3SL50 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.010
1.310
3.006
1.306
3.010
1.310
3.006
1.306
3.010
1.310
3.006
1.306
3.037
1.337
3.027
1.327
3.027
1.327
3.020
1.320
3.019
1.319
3.041
1.341
3.226
1.491
3.229
1.494
3.226
1.491
3.229
1.494
3.226
1.491
3.229
1.494
3.259
1.524
3.249
1.514
3.249
1.514
3.243
1.508
3.241
1.506
3.263
1.528
4.551 4.950 5.459 5.320 5.538 5.075 5.584 5.446 5.604 ns
1.876 1.961 2.162 2.176 2.109 2.074 2.277 2.291 2.093 ns
4.598 5.005 5.521 5.382 5.600 5.134 5.650 5.512 5.670 ns
1.923 2.016 2.224 2.238 2.171 2.133 2.343 2.357 2.159 ns
4.551 4.950 5.459 5.320 5.538 5.075 5.584 5.446 5.604 ns
1.876 1.961 2.162 2.176 2.109 2.074 2.277 2.291 2.093 ns
4.598 5.005 5.521 5.382 5.600 5.134 5.650 5.512 5.670 ns
1.923 2.016 2.224 2.238 2.171 2.133 2.343 2.357 2.159 ns
4.551 4.950 5.459 5.320 5.538 5.075 5.584 5.446 5.604 ns
1.876 1.961 2.162 2.176 2.109 2.074 2.277 2.291 2.093 ns
4.598 5.005 5.521 5.382 5.600 5.134 5.650 5.512 5.670 ns
1.923 2.016 2.224 2.238 2.171 2.133 2.343 2.357 2.159 ns
4.622 5.028 5.543 5.404 5.622 5.155 5.670 5.532 5.690 ns
1.947 2.039 2.246 2.260 2.193 2.154 2.363 2.377 2.179 ns
4.612 5.017 5.533 5.394 5.612 5.144 5.660 5.522 5.680 ns
1.937 2.028 2.236 2.250 2.183 2.143 2.353 2.367 2.169 ns
4.615 5.021 5.537 5.398 5.616 5.149 5.665 5.527 5.685 ns
1.940 2.032 2.240 2.254 2.187 2.148 2.358 2.372 2.174 ns
4.608 5.015 5.531 5.392 5.610 5.142 5.659 5.521 5.679 ns
1.933 2.026 2.234 2.248 2.181 2.141 2.352 2.366 2.168 ns
4.605 5.012 5.528 5.389 5.607 5.139 5.655 5.517 5.675 ns
1.930 2.023 2.231 2.245 2.178 2.138 2.348 2.362 2.164 ns
4.626 5.032 5.547 5.408 5.626 5.159 5.675 5.537 5.695 ns
1.951 2.043 2.250 2.264 2.197 2.158 2.368 2.382 2.184 ns
LVDS_E_1R
LVDS_E_3R
—
—
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
GCLK
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
—
RSDS_E_1R
RSDS_E_3R
GCLK
PLL
GCLK
—
GCLK
PLL
GCLK
4mA
6mA
8mA
10mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V HSTL
CLASS II
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–61
I/O Timing
Table 1–49. EP3SL50 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK tco
3.031
1.331
3.026
1.326
3.024
1.324
3.016
1.316
3.017
1.317
3.016
1.316
3.028
1.328
3.024
1.324
3.014
1.314
3.012
1.312
3.012
1.312
3.016
1.316
3.252
1.517
3.248
1.513
3.246
1.511
3.237
1.502
3.239
1.504
3.236
1.501
3.249
1.514
3.246
1.511
3.235
1.500
3.233
1.498
3.234
1.499
3.237
1.502
4.605 5.009 5.522 5.383 5.601 5.135 5.648 5.510 5.668 ns
1.930 2.020 2.225 2.239 2.172 2.134 2.341 2.355 2.157 ns
4.605 5.009 5.523 5.384 5.602 5.136 5.650 5.512 5.670 ns
1.930 2.020 2.226 2.240 2.173 2.135 2.343 2.357 2.159 ns
4.604 5.008 5.521 5.382 5.600 5.135 5.649 5.511 5.669 ns
1.929 2.019 2.224 2.238 2.171 2.134 2.342 2.356 2.158 ns
4.594 4.998 5.512 5.373 5.591 5.125 5.639 5.501 5.659 ns
1.919 2.009 2.215 2.229 2.162 2.124 2.332 2.346 2.148 ns
4.600 5.005 5.520 5.381 5.599 5.133 5.648 5.510 5.668 ns
1.925 2.016 2.223 2.237 2.170 2.132 2.341 2.355 2.157 ns
4.583 4.986 5.498 5.359 5.577 5.112 5.624 5.486 5.644 ns
1.908 1.997 2.201 2.215 2.148 2.111 2.317 2.331 2.133 ns
4.601 5.004 5.516 5.377 5.595 5.131 5.643 5.505 5.663 ns
1.926 2.015 2.219 2.233 2.166 2.130 2.336 2.350 2.152 ns
4.602 5.006 5.520 5.381 5.599 5.133 5.647 5.509 5.667 ns
1.927 2.017 2.223 2.237 2.170 2.132 2.340 2.354 2.156 ns
4.591 4.995 5.508 5.369 5.587 5.122 5.635 5.497 5.655 ns
1.916 2.006 2.211 2.225 2.158 2.121 2.328 2.342 2.144 ns
4.589 4.992 5.506 5.367 5.585 5.120 5.633 5.495 5.653 ns
1.914 2.003 2.209 2.223 2.156 2.119 2.326 2.340 2.142 ns
4.592 4.997 5.511 5.372 5.590 5.124 5.639 5.501 5.659 ns
1.917 2.008 2.214 2.228 2.161 2.123 2.332 2.346 2.148 ns
4.589 4.992 5.505 5.366 5.584 5.119 5.632 5.494 5.652 ns
1.914 2.003 2.208 2.222 2.155 2.118 2.325 2.339 2.141 ns
4mA
6mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
DIFFERENTIAL
1.5-V HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–62
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–49. EP3SL50 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK tco
3.042
1.342
3.028
1.328
3.016
1.316
3.016
1.316
3.012
1.312
3.016
1.316
3.017
1.317
3.045
1.345
3.034
1.334
3.029
1.329
3.015
1.315
3.013
1.313
3.017
1.317
3.017
1.317
3.266
1.531
3.252
1.517
3.239
1.504
3.239
1.504
3.235
1.500
3.237
1.502
3.239
1.504
3.269
1.534
3.257
1.522
3.253
1.518
3.238
1.503
3.236
1.501
3.238
1.503
3.239
1.504
4.634 5.040 5.555 5.416 5.634 5.167 5.682 5.544 5.702 ns
1.959 2.051 2.258 2.272 2.205 2.166 2.375 2.389 2.191 ns
4.622 5.029 5.545 5.406 5.624 5.157 5.673 5.535 5.693 ns
1.947 2.040 2.248 2.262 2.195 2.156 2.366 2.380 2.182 ns
4.605 5.011 5.527 5.388 5.606 5.139 5.655 5.517 5.675 ns
1.930 2.022 2.230 2.244 2.177 2.138 2.348 2.362 2.164 ns
4.608 5.015 5.531 5.392 5.610 5.143 5.660 5.522 5.680 ns
1.933 2.026 2.234 2.248 2.181 2.142 2.353 2.367 2.169 ns
4.601 5.007 5.524 5.385 5.603 5.136 5.652 5.514 5.672 ns
1.926 2.018 2.227 2.241 2.174 2.135 2.345 2.359 2.161 ns
4.594 4.998 5.512 5.373 5.591 5.125 5.639 5.501 5.659 ns
1.919 2.009 2.215 2.229 2.162 2.124 2.332 2.346 2.148 ns
4.602 5.008 5.523 5.384 5.602 5.135 5.651 5.513 5.671 ns
1.927 2.019 2.226 2.240 2.173 2.134 2.344 2.358 2.160 ns
4.633 5.038 5.553 5.414 5.632 5.166 5.680 5.542 5.700 ns
1.958 2.049 2.256 2.270 2.203 2.165 2.373 2.387 2.189 ns
4.621 5.026 5.541 5.402 5.620 5.154 5.668 5.530 5.688 ns
1.946 2.037 2.244 2.258 2.191 2.153 2.361 2.375 2.177 ns
4.621 5.027 5.542 5.403 5.621 5.155 5.670 5.532 5.690 ns
1.946 2.038 2.245 2.259 2.192 2.154 2.363 2.377 2.179 ns
4.603 5.008 5.523 5.384 5.602 5.136 5.652 5.514 5.672 ns
1.928 2.019 2.226 2.240 2.173 2.135 2.345 2.359 2.161 ns
4.601 5.006 5.521 5.382 5.600 5.134 5.649 5.511 5.669 ns
1.926 2.017 2.224 2.238 2.171 2.133 2.342 2.356 2.158 ns
4.593 4.996 5.509 5.370 5.588 5.123 5.636 5.498 5.656 ns
1.918 2.007 2.212 2.226 2.159 2.122 2.329 2.343 2.145 ns
4.601 5.006 5.521 5.382 5.600 5.134 5.649 5.511 5.669 ns
1.926 2.017 2.224 2.238 2.171 2.133 2.342 2.356 2.158 ns
4mA
6mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
GCLK
16mA
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–63
I/O Timing
Table 1–49. EP3SL50 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK tco
3.033
1.333
3.033
1.333
3.023
1.323
3.016
1.316
3.256
1.521
3.256
1.521
3.246
1.511
3.238
1.503
4.617 5.021 5.535 5.396 5.614 5.149 5.662 5.524 5.682 ns
1.942 2.032 2.238 2.252 2.185 2.148 2.355 2.369 2.171 ns
4.617 5.021 5.535 5.396 5.614 5.149 5.662 5.524 5.682 ns
1.942 2.032 2.238 2.252 2.185 2.148 2.355 2.369 2.171 ns
4.607 5.011 5.525 5.386 5.604 5.139 5.653 5.515 5.673 ns
1.932 2.022 2.228 2.242 2.175 2.138 2.346 2.360 2.162 ns
4.593 4.996 5.509 5.370 5.588 5.123 5.636 5.498 5.656 ns
1.918 2.007 2.212 2.226 2.159 2.122 2.329 2.343 2.145 ns
8mA
10mA
12mA
16mA
GCLK
tco
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V SSTL
CLASS II
GCLK
tco
PLL
Table 1–50 specifies EP3SL50 row pins output timing parameters for differential I/O
standards.
Table 1–50. EP3SL50 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
LVDS
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK tco
2.665
1.008
3.043
1.386
3.025
1.368
2.665
1.008
3.043
1.386
3.025
1.368
2.665
1.008
2.838
1.142
3.268
1.572
3.258
1.562
2.838
1.142
3.268
1.572
3.258
1.562
2.838
1.142
3.975 4.342 4.820 4.684 4.891 4.449 4.928 4.793 4.939 ns
1.343 1.399 1.567 1.586 1.504 1.493 1.665 1.682 1.473 ns
4.622 5.029 5.547 5.404 5.603 5.160 5.681 5.537 5.667 ns
1.990 2.086 2.294 2.306 2.216 2.204 2.418 2.426 2.201 ns
4.660 5.075 5.601 5.458 5.657 5.211 5.742 5.598 5.728 ns
2.028 2.132 2.348 2.360 2.270 2.255 2.479 2.487 2.262 ns
3.975 4.342 4.820 4.684 4.891 4.449 4.928 4.793 4.939 ns
1.343 1.399 1.567 1.586 1.504 1.493 1.665 1.682 1.473 ns
4.622 5.029 5.547 5.404 5.603 5.160 5.681 5.537 5.667 ns
1.990 2.086 2.294 2.306 2.216 2.204 2.418 2.426 2.201 ns
4.660 5.075 5.601 5.458 5.657 5.211 5.742 5.598 5.728 ns
2.028 2.132 2.348 2.360 2.270 2.255 2.479 2.487 2.262 ns
3.975 4.342 4.820 4.684 4.891 4.449 4.928 4.793 4.939 ns
1.343 1.399 1.567 1.586 1.504 1.493 1.665 1.682 1.473 ns
—
—
—
—
—
—
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
GCLK
tco
PLL
GCLK tco
RSDS
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–64
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–50. EP3SL50 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
RSDS_E_1R
RSDS_E_3R
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK tco
3.043
1.386
3.025
1.368
3.079
1.402
3.065
1.388
3.061
1.384
3.077
1.400
3.066
1.389
3.063
1.386
3.074
1.397
3.064
1.387
3.050
1.373
3.047
1.370
3.044
1.367
3.268
1.572
3.258
1.562
3.311
1.595
3.297
1.581
3.293
1.577
3.308
1.592
3.298
1.582
3.295
1.579
3.305
1.589
3.296
1.580
3.282
1.566
3.278
1.562
3.276
1.560
4.622 5.029 5.547 5.404 5.603 5.160 5.681 5.537 5.667 ns
1.990 2.086 2.294 2.306 2.216 2.204 2.418 2.426 2.201 ns
4.660 5.075 5.601 5.458 5.657 5.211 5.742 5.598 5.728 ns
2.028 2.132 2.348 2.360 2.270 2.255 2.479 2.487 2.262 ns
4.706 5.119 5.644 5.501 5.700 5.254 5.781 5.637 5.767 ns
2.054 2.156 2.371 2.383 2.293 2.278 2.498 2.506 2.281 ns
4.693 5.106 5.631 5.488 5.687 5.240 5.768 5.624 5.754 ns
2.041 2.143 2.358 2.370 2.280 2.264 2.485 2.493 2.268 ns
4.691 5.106 5.632 5.489 5.688 5.240 5.770 5.626 5.756 ns
2.039 2.143 2.359 2.371 2.281 2.264 2.487 2.495 2.270 ns
4.692 5.103 5.626 5.483 5.682 5.237 5.763 5.619 5.749 ns
2.040 2.140 2.353 2.365 2.275 2.261 2.480 2.488 2.263 ns
4.688 5.099 5.623 5.480 5.679 5.234 5.760 5.616 5.746 ns
2.036 2.136 2.350 2.362 2.272 2.258 2.477 2.485 2.260 ns
4.686 5.097 5.621 5.478 5.677 5.232 5.759 5.615 5.745 ns
2.034 2.134 2.348 2.360 2.270 2.256 2.476 2.484 2.259 ns
4.687 5.098 5.620 5.477 5.676 5.231 5.757 5.613 5.743 ns
2.035 2.135 2.347 2.359 2.269 2.255 2.474 2.482 2.257 ns
4.685 5.096 5.619 5.476 5.675 5.231 5.757 5.613 5.743 ns
2.033 2.133 2.346 2.358 2.268 2.255 2.474 2.482 2.257 ns
4.670 5.081 5.605 5.462 5.661 5.216 5.742 5.598 5.728 ns
2.018 2.118 2.332 2.344 2.254 2.240 2.459 2.467 2.242 ns
4.666 5.077 5.601 5.458 5.657 5.212 5.738 5.594 5.724 ns
2.014 2.114 2.328 2.340 2.250 2.236 2.455 2.463 2.238 ns
4.667 5.080 5.604 5.461 5.660 5.215 5.742 5.598 5.728 ns
2.015 2.117 2.331 2.343 2.253 2.239 2.459 2.467 2.242 ns
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
4mA
6mA
8mA
4mA
6mA
8mA
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
10m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
12m
A
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–65
I/O Timing
Table 1–50. EP3SL50 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK tco
3.045
1.368
3.094
1.417
3.070
1.393
3.052
1.375
3.098
1.421
3.083
1.406
3.072
1.395
3.052
1.375
3.049
1.372
3.054
1.377
3.047
1.370
3.075
1.418
3.057
1.400
3.276
1.560
3.329
1.613
3.305
1.589
3.286
1.570
3.332
1.616
3.317
1.601
3.306
1.590
3.286
1.570
3.282
1.566
3.286
1.570
3.279
1.563
3.308
1.612
3.291
1.595
4.657 5.068 5.591 5.448 5.647 5.202 5.728 5.584 5.714 ns
2.005 2.105 2.318 2.330 2.240 2.226 2.445 2.453 2.228 ns
4.728 5.141 5.667 5.524 5.723 5.276 5.804 5.660 5.790 ns
2.076 2.178 2.394 2.406 2.316 2.300 2.521 2.529 2.304 ns
4.710 5.124 5.650 5.507 5.706 5.259 5.789 5.645 5.775 ns
2.058 2.161 2.377 2.389 2.299 2.283 2.506 2.514 2.289 ns
4.688 5.102 5.628 5.485 5.684 5.237 5.767 5.623 5.753 ns
2.036 2.139 2.355 2.367 2.277 2.261 2.484 2.492 2.267 ns
4.728 5.141 5.666 5.523 5.722 5.276 5.804 5.660 5.790 ns
2.076 2.178 2.393 2.405 2.315 2.300 2.521 2.529 2.304 ns
4.714 5.126 5.651 5.508 5.707 5.261 5.789 5.645 5.775 ns
2.062 2.163 2.378 2.390 2.300 2.285 2.506 2.514 2.289 ns
4.709 5.123 5.648 5.505 5.704 5.258 5.787 5.643 5.773 ns
2.057 2.160 2.375 2.387 2.297 2.282 2.504 2.512 2.287 ns
4.686 5.099 5.625 5.482 5.681 5.235 5.763 5.619 5.749 ns
2.034 2.136 2.352 2.364 2.274 2.259 2.480 2.488 2.263 ns
4.682 5.096 5.621 5.478 5.677 5.231 5.760 5.616 5.746 ns
2.030 2.133 2.348 2.360 2.270 2.255 2.477 2.485 2.260 ns
4.673 5.084 5.607 5.464 5.663 5.218 5.744 5.600 5.730 ns
2.021 2.121 2.334 2.346 2.256 2.242 2.461 2.469 2.244 ns
4.672 5.085 5.610 5.467 5.666 5.221 5.749 5.605 5.735 ns
2.020 2.122 2.337 2.349 2.259 2.245 2.466 2.474 2.249 ns
4.700 5.112 5.636 5.493 5.692 5.247 5.774 5.630 5.760 ns
2.068 2.169 2.383 2.395 2.305 2.291 2.511 2.519 2.294 ns
4.685 5.097 5.621 5.478 5.677 5.232 5.759 5.615 5.745 ns
2.053 2.154 2.368 2.380 2.290 2.276 2.496 2.504 2.279 ns
DIFFERENTIAL
1.8-V
HSTL CLASS II
16m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
4mA
6mA
8mA
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
10m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
12m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
16m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
12m
A
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–66
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–50. EP3SL50 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK tco
3.043
1.386
3.275
1.579
4.662 5.073 5.596 5.453 5.652 5.208 5.734 5.590 5.720 ns
2.030 2.130 2.343 2.355 2.265 2.252 2.471 2.479 2.254 ns
DIFFERENTIAL
2.5-V
SSTL CLASS II
16m
A
GCLK
tco
PLL
Table 1–51 and Table 1–52 show EP3SL50 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III.
Table 1–51 specifies EP3SL50 Column Pin delay adders when using the regional clock.
Table 1–51. EP3SL50 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Parameter
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.239
0.008
-0.068
1.614
0.258
0.009
-0.07
1.649
0.341 0.365
0.39
0.377 0.439 0.375 0.399 0.388 0.441
ns
ns
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.014 0.017 0.019 0.017 0.02 0.018 0.019 0.017 0.02
-0.09 -0.092 -0.094 -0.091 -0.169 -0.086 -0.087 -0.09 -0.17
2.575
2.89
3.164 3.011 3.22 2.908 3.217 3.063 3.338
Table 1–52 specifies EP3SL50 Row Pin delay adders when using the regional clock.
Table 1–52. EP3SL50 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Parameter
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.111
0.101
-0.113
-0.107
0.124
0.107
-0.127
-0.113
0.178 0.193 0.208
0.2
0.263 0.197 0.213 0.203 0.266
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.156 0.174 0.194 0.184 0.251 0.177 0.196 0.188 0.249
-0.181 -0.196 -0.213 -0.205 -0.271 -0.199 -0.217 -0.209 -0.273 ns
-0.164 -0.185 -0.213 -0.2 -0.266 -0.184 -0.212 -0.198 -0.262 ns
EP3SL70 I/O Timing Parameters
Table 1–53 through Table 1–56 show the maximum I/O timing parameters for
EP3SL70 devices for single-ended I/O standards.
Table 1–53 specifies EP3SL70 column pins input timing parameters for single-ended
I/O standards.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–67
I/O Timing
Table 1–53. EP3SL70 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
=
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.833
0.948
0.811
-0.566
-0.833
0.948
0.811
-0.566
-0.839
0.954
0.805
-0.560
-0.839
0.954
0.805
-0.560
-0.829
0.944
0.815
-0.570
-0.845
0.962
0.799
-0.552
-0.838
0.955
0.806
-0.559
-0.778
0.895
0.866
-0.619
-0.759
0.876
0.885
-0.638
-0.844
0.974
0.836
-0.577
-0.844
0.974
0.836
-0.577
-0.855
0.985
0.825
-0.566
-0.855
0.985
0.825
-0.566
-0.850
0.980
0.830
-0.571
-0.870
1.002
0.810
-0.549
-0.860
0.992
0.820
-0.559
-0.808
0.940
0.872
-0.611
-0.779
0.911
0.901
-0.640
-1.217 -1.340 -1.572 -1.515 -1.800 -1.346 -1.561 -1.510 -1.828
1.405 1.550 1.804 1.734 2.022 1.565 1.803 1.738 2.048
1.371 1.560 1.635 1.535 1.356 1.565 1.655 1.552 1.412
-0.984 -1.120 -1.144 -1.074 -0.889 -1.116 -1.153 -1.083 -0.944
-1.217 -1.340 -1.572 -1.515 -1.800 -1.346 -1.561 -1.510 -1.828
1.405 1.550 1.804 1.734 2.022 1.565 1.803 1.738 2.048
1.371 1.560 1.635 1.535 1.356 1.565 1.655 1.552 1.412
-0.984 -1.120 -1.144 -1.074 -0.889 -1.116 -1.153 -1.083 -0.944
-1.216 -1.342 -1.571 -1.514 -1.799 -1.346 -1.566 -1.515 -1.833
1.404 1.552 1.803 1.733 2.021 1.565 1.808 1.743 2.053
1.372 1.558 1.636 1.536 1.357 1.565 1.650 1.547 1.407
-0.985 -1.118 -1.145 -1.075 -0.890 -1.116 -1.148 -1.078 -0.939
-1.216 -1.342 -1.571 -1.514 -1.799 -1.346 -1.566 -1.515 -1.833
1.404 1.552 1.803 1.733 2.021 1.565 1.808 1.743 2.053
1.372 1.558 1.636 1.536 1.357 1.565 1.650 1.547 1.407
-0.985 -1.118 -1.145 -1.075 -0.890 -1.116 -1.148 -1.078 -0.939
-1.225 -1.354 -1.590 -1.533 -1.818 -1.356 -1.577 -1.526 -1.844
1.413 1.564 1.822 1.752 2.040 1.575 1.819 1.754 2.064
1.363 1.546 1.617 1.517 1.338 1.555 1.639 1.536 1.396
-0.976 -1.106 -1.126 -1.056 -0.871 -1.106 -1.137 -1.067 -0.928
-1.265 -1.390 -1.588 -1.531 -1.816 -1.390 -1.580 -1.529 -1.847
1.453 1.600 1.820 1.750 2.038 1.609 1.822 1.757 2.067
1.323 1.510 1.619 1.519 1.340 1.521 1.636 1.533 1.393
-0.936 -1.070 -1.128 -1.058 -0.873 -1.072 -1.134 -1.064 -0.925
-1.242 -1.358 -1.518 -1.461 -1.746 -1.359 -1.514 -1.463 -1.781
1.430 1.568 1.750 1.680 1.968 1.578 1.756 1.691 2.001
1.346 1.542 1.689 1.589 1.410 1.552 1.702 1.599 1.459
-0.959 -1.102 -1.198 -1.128 -0.943 -1.103 -1.200 -1.130 -0.991
-1.165 -1.259 -1.362 -1.305 -1.590 -1.263 -1.361 -1.310 -1.628
1.353 1.469 1.594 1.524 1.812 1.482 1.603 1.538 1.848
1.423 1.641 1.845 1.745 1.566 1.648 1.855 1.752 1.612
-1.036 -1.201 -1.354 -1.284 -1.099 -1.199 -1.353 -1.283 -1.144
-1.137 -1.243 -1.364 -1.307 -1.592 -1.242 -1.357 -1.306 -1.624
1.325 1.453 1.596 1.526 1.814 1.461 1.599 1.534 1.844
1.451 1.657 1.843 1.743 1.564 1.669 1.859 1.756 1.616
-1.064 -1.217 -1.352 -1.282 -1.097 -1.220 -1.357 -1.287 -1.148
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
3.3-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–68
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–53. EP3SL70 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.759
0.876
0.885
-0.638
-0.752
0.869
0.892
-0.645
-0.752
0.869
0.892
-0.645
-0.740
0.857
0.904
-0.657
-0.740
0.857
0.904
-0.657
-0.752
0.869
0.892
-0.645
-0.752
0.869
0.892
-0.645
-0.740
0.857
0.904
-0.657
-0.740
0.857
0.904
-0.657
-0.779
0.911
0.901
-0.640
-0.773
0.905
0.907
-0.646
-0.773
0.905
0.907
-0.646
-0.762
0.894
0.918
-0.657
-0.762
0.894
0.918
-0.657
-0.773
0.905
0.907
-0.646
-0.773
0.905
0.907
-0.646
-0.762
0.894
0.918
-0.657
-0.762
0.894
0.918
-0.657
-1.137 -1.243 -1.364 -1.307 -1.592 -1.242 -1.357 -1.306 -1.624
1.325 1.453 1.596 1.526 1.814 1.461 1.599 1.534 1.844
1.451 1.657 1.843 1.743 1.564 1.669 1.859 1.756 1.616
-1.064 -1.217 -1.352 -1.282 -1.097 -1.220 -1.357 -1.287 -1.148
-1.125 -1.238 -1.364 -1.305 -1.593 -1.238 -1.362 -1.308 -1.628
1.312 1.445 1.593 1.523 1.810 1.454 1.599 1.535 1.843
1.463 1.662 1.843 1.745 1.566 1.673 1.854 1.754 1.615
-1.077 -1.225 -1.355 -1.285 -1.104 -1.227 -1.357 -1.286 -1.152
-1.125 -1.238 -1.364 -1.305 -1.593 -1.238 -1.362 -1.308 -1.628
1.312 1.445 1.593 1.523 1.810 1.454 1.599 1.535 1.843
1.463 1.662 1.843 1.745 1.566 1.673 1.854 1.754 1.615
-1.077 -1.225 -1.355 -1.285 -1.104 -1.227 -1.357 -1.286 -1.152
-1.116 -1.227 -1.345 -1.286 -1.574 -1.227 -1.344 -1.290 -1.610
1.302 1.434 1.574 1.504 1.791 1.443 1.581 1.517 1.825
1.472 1.673 1.862 1.764 1.585 1.684 1.872 1.772 1.633
-1.087 -1.236 -1.374 -1.304 -1.123 -1.238 -1.375 -1.304 -1.170
-1.116 -1.227 -1.345 -1.286 -1.574 -1.227 -1.344 -1.290 -1.610
1.302 1.434 1.574 1.504 1.791 1.443 1.581 1.517 1.825
1.472 1.673 1.862 1.764 1.585 1.684 1.872 1.772 1.633
-1.087 -1.236 -1.374 -1.304 -1.123 -1.238 -1.375 -1.304 -1.170
-1.125 -1.238 -1.364 -1.305 -1.593 -1.238 -1.362 -1.308 -1.628
1.312 1.445 1.593 1.523 1.810 1.454 1.599 1.535 1.843
1.463 1.662 1.843 1.745 1.566 1.673 1.854 1.754 1.615
-1.077 -1.225 -1.355 -1.285 -1.104 -1.227 -1.357 -1.286 -1.152
-1.125 -1.238 -1.364 -1.305 -1.593 -1.238 -1.362 -1.308 -1.628
1.312 1.445 1.593 1.523 1.810 1.454 1.599 1.535 1.843
1.463 1.662 1.843 1.745 1.566 1.673 1.854 1.754 1.615
-1.077 -1.225 -1.355 -1.285 -1.104 -1.227 -1.357 -1.286 -1.152
-1.116 -1.227 -1.345 -1.286 -1.574 -1.227 -1.344 -1.290 -1.610
1.302 1.434 1.574 1.504 1.791 1.443 1.581 1.517 1.825
1.472 1.673 1.862 1.764 1.585 1.684 1.872 1.772 1.633
-1.087 -1.236 -1.374 -1.304 -1.123 -1.238 -1.375 -1.304 -1.170
-1.116 -1.227 -1.345 -1.286 -1.574 -1.227 -1.344 -1.290 -1.610
1.302 1.434 1.574 1.504 1.791 1.443 1.581 1.517 1.825
1.472 1.673 1.862 1.764 1.585 1.684 1.872 1.772 1.633
-1.087 -1.236 -1.374 -1.304 -1.123 -1.238 -1.375 -1.304 -1.170
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
SSTL-2
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-15
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–69
I/O Timing
Table 1–53. EP3SL70 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
=
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.732
0.849
0.912
-0.665
-0.732
0.849
0.912
-0.665
-0.839
0.954
0.805
-0.560
-0.750
0.882
0.930
-0.669
-0.750
0.882
0.930
-0.669
-0.855
0.985
0.825
-0.566
-1.106 -1.216 -1.329 -1.270 -1.558 -1.216 -1.329 -1.275 -1.595
1.292 1.423 1.558 1.488 1.775 1.432 1.566 1.502 1.810
1.482 1.684 1.878 1.780 1.601 1.695 1.887 1.787 1.648
-1.097 -1.247 -1.390 -1.320 -1.139 -1.249 -1.390 -1.319 -1.185
-1.106 -1.216 -1.329 -1.270 -1.558 -1.216 -1.329 -1.275 -1.595
1.292 1.423 1.558 1.488 1.775 1.432 1.566 1.502 1.810
1.482 1.684 1.878 1.780 1.601 1.695 1.887 1.787 1.648
-1.097 -1.247 -1.390 -1.320 -1.139 -1.249 -1.390 -1.319 -1.185
-1.216 -1.342 -1.571 -1.514 -1.799 -1.346 -1.566 -1.515 -1.833
1.404 1.552 1.803 1.733 2.021 1.565 1.808 1.743 2.053
1.372 1.558 1.636 1.536 1.357 1.565 1.650 1.547 1.407
-0.985 -1.118 -1.145 -1.075 -0.890 -1.116 -1.148 -1.078 -0.939
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
PCI-X
tsu
th
GCLK
PLL
Table 1–54 specifies EP3SL70 row pins input timing parameters for single-ended I/O
standards.
Table 1–54. EP3SL70 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.811
0.925
0.937
-0.688
-0.811
0.925
0.937
-0.688
-0.817
0.931
0.931
-0.682
-0.817
0.931
0.931
-0.682
-0.836
0.962
0.945
-0.684
-0.836
0.962
0.945
-0.684
-0.847
0.973
0.934
-0.673
-0.847
0.973
0.934
-0.673
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 ns
GCLK
1.371 1.505 1.747 1.679 1.951 1.526 1.756 1.693 1.982
1.582 1.801 1.915 1.799 1.814 1.796 1.923 1.804 1.865
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-1.184 -1.352 -1.415 -1.329 -1.338 -1.339 -1.411 -1.325 -1.386 ns
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763 ns
tsu
th
GCLK
1.371 1.505 1.747 1.679 1.951 1.526 1.756 1.693 1.982
1.582 1.801 1.915 1.799 1.814 1.796 1.923 1.804 1.865
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-1.184 -1.352 -1.415 -1.329 -1.338 -1.339 -1.411 -1.325 -1.386 ns
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 ns
tsu
th
GCLK
1.368 1.506 1.750 1.682 1.954 1.525 1.761 1.698 1.987
1.585 1.800 1.912 1.796 1.811 1.797 1.918 1.799 1.860
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-1.187 -1.351 -1.412 -1.326 -1.335 -1.340 -1.406 -1.320 -1.381 ns
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 ns
tsu
th
GCLK
1.368 1.506 1.750 1.682 1.954 1.525 1.761 1.698 1.987
1.585 1.800 1.912 1.796 1.811 1.797 1.918 1.799 1.860
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-1.187 -1.351 -1.412 -1.326 -1.335 -1.340 -1.406 -1.320 -1.381 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–70
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–54. EP3SL70 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.805
0.919
0.943
-0.694
-0.946
1.060
0.914
-0.666
-0.936
1.050
0.924
-0.676
-0.876
0.990
0.984
-0.736
-0.747
0.862
1.000
-0.750
-0.747
0.862
1.000
-0.750
-0.850
0.964
1.010
-0.762
-0.850
0.964
1.010
-0.762
-0.836
0.950
1.024
-0.776
-0.840
0.966
0.941
-0.680
-0.899
1.028
0.891
-0.629
-0.888
1.017
0.902
-0.640
-0.835
0.964
0.955
-0.693
-0.781
0.908
0.999
-0.737
-0.781
0.908
0.999
-0.737
-0.800
0.929
0.990
-0.728
-0.800
0.929
0.990
-0.728
-0.788
0.917
1.002
-0.740
-1.191 -1.310 -1.531 -1.478 -1.750 -1.314 -1.528 -1.479 -1.778 ns
GCLK
1.377 1.519 1.765 1.697 1.969 1.534 1.771 1.708 1.997
1.576 1.787 1.897 1.781 1.796 1.788 1.908 1.789 1.850
ns
ns
2.5 V
tsu
th
GCLK
PLL
-1.178 -1.338 -1.397 -1.311 -1.320 -1.331 -1.396 -1.310 -1.371 ns
-1.259 -1.469 -1.662 -1.607 -1.898 -1.507 -1.694 -1.641 -1.931 ns
tsu
th
GCLK
1.447 1.676 1.892 1.823 2.114 1.723 1.933 1.867 2.146
1.518 1.758 1.994 1.874 1.798 1.758 1.917 1.798 1.849
ns
ns
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
-1.121 -1.310 -1.490 -1.401 -1.322 -1.300 -1.405 -1.319 -1.370 ns
-1.235 -1.437 -1.594 -1.539 -1.830 -1.476 -1.629 -1.576 -1.866 ns
tsu
th
GCLK
1.423 1.644 1.824 1.755 2.046 1.692 1.868 1.802 2.081
1.542 1.790 2.062 1.942 1.866 1.789 1.982 1.863 1.914
ns
ns
tsu
th
GCLK
PLL
-1.145 -1.342 -1.558 -1.469 -1.390 -1.331 -1.470 -1.384 -1.435 ns
-1.156 -1.336 -1.435 -1.380 -1.671 -1.380 -1.474 -1.421 -1.711 ns
tsu
th
GCLK
1.344 1.543 1.665 1.596 1.887 1.596 1.713 1.647 1.926
1.621 1.891 2.221 2.101 2.025 1.885 2.137 2.018 2.069
ns
ns
tsu
th
GCLK
PLL
-1.224 -1.443 -1.717 -1.628 -1.549 -1.427 -1.625 -1.539 -1.590 ns
-1.105 -1.201 -1.311 -1.258 -1.530 -1.202 -1.311 -1.262 -1.561 ns
tsu
th
GCLK
1.291 1.410 1.545 1.477 1.749 1.422 1.554 1.491 1.780
1.662 1.896 2.117 2.001 2.016 1.900 2.125 2.006 2.067
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-1.264 -1.447 -1.617 -1.531 -1.540 -1.443 -1.613 -1.527 -1.588 ns
-1.105 -1.201 -1.311 -1.258 -1.530 -1.202 -1.311 -1.262 -1.561 ns
tsu
th
GCLK
1.291 1.410 1.545 1.477 1.749 1.422 1.554 1.491 1.780
1.662 1.896 2.117 2.001 2.016 1.900 2.125 2.006 2.067
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-1.264 -1.447 -1.617 -1.531 -1.540 -1.443 -1.613 -1.527 -1.588 ns
-1.118 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 ns
tsu
th
GCLK
1.306 1.514 1.658 1.589 1.879 1.562 1.703 1.638 1.915
1.659 1.918 2.223 2.104 2.029 1.917 2.144 2.026 2.076
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-1.262 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 ns
-1.118 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 ns
tsu
th
GCLK
1.306 1.514 1.658 1.589 1.879 1.562 1.703 1.638 1.915
1.659 1.918 2.223 2.104 2.029 1.917 2.144 2.026 2.076
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-1.262 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 ns
-1.105 -1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687 ns
tsu
th
GCLK
1.294 1.504 1.640 1.571 1.861 1.551 1.686 1.621 1.898
1.674 1.928 2.241 2.122 2.047 1.928 2.161 2.043 2.093
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-1.276 -1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–71
I/O Timing
Table 1–54. EP3SL70 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.850
0.964
1.010
-0.762
-0.850
0.964
1.010
-0.762
-0.836
0.950
1.024
-0.776
-0.836
0.950
1.024
-0.776
-0.827
0.941
1.033
-0.785
-0.827
0.941
1.033
-0.785
-0.817
0.931
0.931
-0.682
-0.817
0.931
0.931
-0.682
-0.800
0.929
0.990
-0.728
-0.800
0.929
0.990
-0.728
-0.788
0.917
1.002
-0.740
-0.788
0.917
1.002
-0.740
-0.776
0.905
1.014
-0.752
-0.776
0.905
1.014
-0.752
-0.847
0.973
0.934
-0.673
-0.847
0.973
0.934
-0.673
-1.118 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 ns
GCLK
1.306 1.514 1.658 1.589 1.879 1.562 1.703 1.638 1.915
1.659 1.918 2.223 2.104 2.029 1.917 2.144 2.026 2.076
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.262 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 ns
-1.118 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704 ns
tsu
th
GCLK
1.306 1.514 1.658 1.589 1.879 1.562 1.703 1.638 1.915
1.659 1.918 2.223 2.104 2.029 1.917 2.144 2.026 2.076
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.262 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601 ns
-1.105 -1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687 ns
tsu
th
GCLK
1.294 1.504 1.640 1.571 1.861 1.551 1.686 1.621 1.898
1.674 1.928 2.241 2.122 2.047 1.928 2.161 2.043 2.093
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.276 -1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618 ns
-1.105 -1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687 ns
tsu
th
GCLK
1.294 1.504 1.640 1.571 1.861 1.551 1.686 1.621 1.898
1.674 1.928 2.241 2.122 2.047 1.928 2.161 2.043 2.093
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.276 -1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618 ns
-1.096 -1.289 -1.396 -1.340 -1.633 -1.328 -1.434 -1.380 -1.671 ns
tsu
th
GCLK
1.285 1.494 1.624 1.555 1.845 1.542 1.670 1.605 1.882
1.683 1.938 2.257 2.138 2.063 1.937 2.177 2.059 2.109
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.285 -1.492 -1.756 -1.667 -1.591 -1.481 -1.668 -1.581 -1.634 ns
-1.096 -1.289 -1.396 -1.340 -1.633 -1.328 -1.434 -1.380 -1.671 ns
tsu
th
GCLK
1.285 1.494 1.624 1.555 1.845 1.542 1.670 1.605 1.882
1.683 1.938 2.257 2.138 2.063 1.937 2.177 2.059 2.109
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.285 -1.492 -1.756 -1.667 -1.591 -1.481 -1.668 -1.581 -1.634 ns
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 ns
tsu
th
GCLK
1.368 1.506 1.750 1.682 1.954 1.525 1.761 1.698 1.987
1.585 1.800 1.912 1.796 1.811 1.797 1.918 1.799 1.860
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-1.187 -1.351 -1.412 -1.326 -1.335 -1.340 -1.406 -1.320 -1.381 ns
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768 ns
tsu
th
GCLK
1.368 1.506 1.750 1.682 1.954 1.525 1.761 1.698 1.987
1.585 1.800 1.912 1.796 1.811 1.797 1.918 1.799 1.860
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-1.187 -1.351 -1.412 -1.326 -1.335 -1.340 -1.406 -1.320 -1.381 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–72
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–55 specifies EP3SL70 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–55. EP3SL70 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.064
1.553
2.985
1.474
2.956
1.444
2.942
1.430
3.002
1.490
2.931
1.419
2.906
1.395
2.899
1.388
3.062
1.550
2.995
1.483
2.957
1.445
2.935
1.423
3.283
1.738
3.194
1.649
3.162
1.617
3.148
1.603
3.216
1.671
3.139
1.594
3.111
1.566
3.104
1.559
3.292
1.747
3.207
1.662
3.170
1.625
3.143
1.598
4.557 4.943 5.437 5.303 5.531 5.064 5.556 5.426 5.600
2.181 2.288 2.504 2.508 2.475 2.397 2.615 2.620 2.463
4.454 4.831 5.320 5.186 5.414 4.948 5.436 5.306 5.480
2.077 2.176 2.387 2.391 2.358 2.281 2.495 2.500 2.343
4.387 4.761 5.250 5.116 5.344 4.878 5.369 5.239 5.413
2.010 2.106 2.317 2.321 2.288 2.211 2.428 2.433 2.275
4.366 4.738 5.222 5.088 5.316 4.852 5.336 5.206 5.380
1.989 2.083 2.289 2.293 2.260 2.185 2.394 2.399 2.241
4.484 4.860 5.349 5.215 5.443 4.978 5.468 5.338 5.512
2.108 2.205 2.416 2.420 2.388 2.311 2.527 2.532 2.375
4.362 4.734 5.218 5.084 5.312 4.848 5.331 5.201 5.375
1.986 2.079 2.285 2.289 2.256 2.181 2.390 2.395 2.237
4.333 4.707 5.193 5.059 5.287 4.821 5.306 5.176 5.350
1.957 2.052 2.260 2.264 2.230 2.154 2.365 2.370 2.211
4.325 4.698 5.184 5.050 5.278 4.812 5.297 5.167 5.341
1.949 2.043 2.251 2.255 2.221 2.144 2.355 2.360 2.201
4.591 4.979 5.476 5.342 5.570 5.103 5.598 5.468 5.642
2.215 2.324 2.543 2.547 2.534 2.435 2.657 2.662 2.504
4.487 4.868 5.360 5.226 5.454 4.988 5.480 5.350 5.524
2.111 2.212 2.427 2.431 2.440 2.321 2.538 2.543 2.386
4.419 4.796 5.286 5.152 5.380 4.914 5.404 5.274 5.448
2.043 2.141 2.353 2.357 2.376 2.247 2.462 2.467 2.309
4.384 4.757 5.244 5.110 5.338 4.874 5.360 5.230 5.404
2.008 2.102 2.311 2.315 2.353 2.207 2.419 2.424 2.266
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVTTL
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVTTL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–73
I/O Timing
Table 1–55. EP3SL70 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.016
1.505
2.944
1.432
2.920
1.408
2.920
1.408
3.120
1.609
3.037
1.526
2.982
1.470
2.948
1.437
3.232
1.687
3.153
1.608
3.124
1.579
3.124
1.579
3.347
1.802
3.254
1.709
3.210
1.665
3.164
1.619
4.521 4.901 5.395 5.261 5.489 5.022 5.516 5.386 5.560
2.145 2.246 2.462 2.466 2.476 2.355 2.575 2.580 2.422
4.398 4.772 5.260 5.126 5.354 4.889 5.377 5.247 5.421
2.021 2.117 2.327 2.331 2.366 2.222 2.435 2.440 2.282
4.358 4.733 5.219 5.085 5.313 4.849 5.335 5.205 5.379
1.982 2.077 2.286 2.290 2.332 2.182 2.394 2.399 2.241
4.350 4.723 5.209 5.075 5.303 4.838 5.323 5.193 5.367
1.974 2.068 2.276 2.280 2.340 2.171 2.382 2.387 2.228
4.728 5.128 5.642 5.508 5.736 5.255 5.771 5.641 5.815
2.352 2.473 2.709 2.713 2.684 2.588 2.830 2.835 2.676
4.609 5.002 5.510 5.376 5.604 5.127 5.635 5.505 5.679
2.233 2.347 2.577 2.581 2.560 2.460 2.694 2.699 2.541
4.517 4.906 5.410 5.276 5.504 5.029 5.533 5.403 5.577
2.141 2.251 2.477 2.481 2.482 2.362 2.592 2.597 2.439
4.483 4.869 5.369 5.235 5.463 4.990 5.489 5.359 5.533
2.107 2.214 2.436 2.440 2.425 2.322 2.548 2.553 2.395
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
2.5 V
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–74
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–55. EP3SL70 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.234
1.723
3.136
1.625
3.054
1.543
3.029
1.517
2.958
1.446
2.953
1.441
3.175
1.663
3.043
1.532
2.999
1.487
2.987
1.476
2.952
1.441
2.948
1.437
3.475
1.930
3.364
1.819
3.277
1.732
3.244
1.699
3.180
1.635
3.170
1.625
3.442
1.897
3.261
1.716
3.224
1.679
3.218
1.673
3.167
1.622
3.160
1.615
4.923 5.337 5.860 5.726 5.954 5.473 5.997 5.867 6.041
2.546 2.682 2.927 2.931 2.902 2.806 3.056 3.061 2.904
4.771 5.179 5.699 5.565 5.793 5.314 5.831 5.701 5.875
2.394 2.524 2.766 2.770 2.750 2.647 2.890 2.895 2.738
4.644 5.041 5.555 5.421 5.649 5.170 5.684 5.554 5.728
2.267 2.386 2.622 2.626 2.609 2.503 2.742 2.747 2.589
4.583 4.975 5.480 5.346 5.574 5.099 5.603 5.473 5.647
2.207 2.320 2.547 2.551 2.530 2.432 2.662 2.667 2.509
4.495 4.881 5.381 5.247 5.475 5.002 5.502 5.372 5.546
2.119 2.226 2.448 2.452 2.448 2.335 2.561 2.566 2.408
4.489 4.875 5.374 5.240 5.468 4.995 5.495 5.365 5.539
2.113 2.220 2.441 2.445 2.442 2.328 2.554 2.559 2.401
4.861 5.264 5.788 5.654 5.882 5.403 5.930 5.800 5.974
2.485 2.609 2.855 2.859 2.841 2.736 2.989 2.994 2.837
4.618 5.010 5.517 5.383 5.611 5.135 5.644 5.514 5.688
2.241 2.355 2.584 2.588 2.572 2.468 2.702 2.707 2.549
4.537 4.930 5.437 5.303 5.531 5.055 5.561 5.431 5.605
2.161 2.275 2.504 2.508 2.510 2.388 2.619 2.624 2.466
4.531 4.923 5.428 5.294 5.522 5.048 5.553 5.423 5.597
2.155 2.267 2.495 2.499 2.503 2.381 2.612 2.617 2.458
4.483 4.869 5.367 5.233 5.461 4.989 5.488 5.358 5.532
2.107 2.214 2.434 2.438 2.444 2.322 2.547 2.552 2.394
4.463 4.848 5.347 5.213 5.441 4.968 5.467 5.337 5.511
2.086 2.193 2.414 2.418 2.441 2.301 2.525 2.530 2.372
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.8 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–75
I/O Timing
Table 1–55. EP3SL70 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.154
1.643
3.032
1.520
2.979
1.467
2.958
1.447
2.972
1.460
2.975
1.463
2.956
1.445
2.951
1.440
2.990
1.478
2.971
1.459
2.972
1.460
2.955
1.443
2.951
1.440
3.385
1.840
3.250
1.705
3.209
1.664
3.175
1.630
3.183
1.638
3.186
1.641
3.166
1.621
3.159
1.614
3.203
1.658
3.182
1.637
3.185
1.640
3.165
1.620
3.161
1.616
4.815 5.218 5.731 5.597 5.825 5.350 5.864 5.734 5.908
2.439 2.563 2.798 2.802 2.787 2.683 2.923 2.928 2.772
4.596 4.987 5.491 5.357 5.585 5.111 5.616 5.486 5.660
2.220 2.332 2.558 2.562 2.563 2.444 2.674 2.679 2.521
4.520 4.910 5.417 5.283 5.511 5.036 5.543 5.413 5.587
2.144 2.255 2.484 2.488 2.509 2.369 2.602 2.607 2.448
4.481 4.867 5.367 5.233 5.461 4.987 5.486 5.356 5.530
2.105 2.212 2.434 2.438 2.474 2.320 2.545 2.550 2.392
4.489 4.875 5.375 5.241 5.469 4.993 5.491 5.361 5.535
2.113 2.220 2.442 2.446 2.466 2.325 2.550 2.555 2.396
4.493 4.879 5.379 5.245 5.473 4.996 5.495 5.365 5.539
2.117 2.224 2.446 2.450 2.472 2.329 2.554 2.559 2.400
4.472 4.857 5.357 5.223 5.451 4.975 5.473 5.343 5.517
2.095 2.202 2.424 2.428 2.445 2.308 2.532 2.537 2.378
4.457 4.841 5.340 5.206 5.434 4.958 5.456 5.326 5.500
2.080 2.186 2.407 2.411 2.443 2.291 2.514 2.519 2.360
4.512 4.898 5.398 5.264 5.492 5.016 5.515 5.385 5.559
2.136 2.243 2.465 2.469 2.496 2.349 2.574 2.579 2.419
4.490 4.876 5.376 5.242 5.470 4.994 5.492 5.362 5.536
2.114 2.221 2.443 2.447 2.472 2.327 2.551 2.556 2.397
4.498 4.885 5.386 5.252 5.480 5.004 5.503 5.373 5.547
2.122 2.230 2.453 2.457 2.492 2.337 2.562 2.567 2.408
4.474 4.860 5.361 5.227 5.455 4.978 5.478 5.348 5.522
2.097 2.205 2.428 2.432 2.467 2.311 2.536 2.541 2.383
4.470 4.856 5.356 5.222 5.450 4.974 5.474 5.344 5.518
2.093 2.201 2.423 2.427 2.462 2.307 2.532 2.537 2.379
2mA
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
1.2 V
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS I
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–76
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–55. EP3SL70 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
2.952
1.440
2.951
1.439
2.981
1.470
2.966
1.455
2.953
1.442
2.954
1.442
2.949
1.438
2.967
1.456
2.966
1.455
3.160
1.615
3.160
1.615
3.194
1.649
3.178
1.633
3.163
1.618
3.164
1.619
3.159
1.614
3.176
1.631
3.176
1.631
4.457 4.842 5.340 5.206 5.434 4.959 5.456 5.326 5.500
2.081 2.186 2.407 2.411 2.447 2.292 2.515 2.520 2.361
4.465 4.852 5.352 5.218 5.446 4.969 5.469 5.339 5.513
2.089 2.196 2.419 2.423 2.454 2.302 2.528 2.533 2.374
4.505 4.891 5.390 5.256 5.484 5.009 5.507 5.377 5.551
2.129 2.236 2.457 2.461 2.489 2.342 2.566 2.571 2.412
4.491 4.878 5.378 5.244 5.472 4.996 5.496 5.366 5.540
2.115 2.223 2.445 2.449 2.485 2.329 2.555 2.560 2.401
4.471 4.857 5.358 5.224 5.452 4.976 5.475 5.345 5.519
2.095 2.202 2.425 2.429 2.467 2.309 2.534 2.539 2.380
4.472 4.859 5.361 5.227 5.455 4.978 5.478 5.348 5.522
2.096 2.204 2.428 2.432 2.478 2.311 2.537 2.542 2.383
4.465 4.852 5.353 5.219 5.447 4.970 5.470 5.340 5.514
2.089 2.197 2.420 2.424 2.470 2.303 2.529 2.534 2.375
4.473 4.857 5.355 5.221 5.449 4.974 5.471 5.341 5.515
2.097 2.202 2.422 2.426 2.458 2.307 2.530 2.535 2.376
4.477 4.862 5.361 5.227 5.455 4.979 5.477 5.347 5.521
2.101 2.207 2.428 2.432 2.476 2.312 2.536 2.541 2.382
8mA
GCLK
tco
PLL
SSTL-18
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-15
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
SSTL-15
CLASS II
GCLK tco
16mA
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–77
I/O Timing
Table 1–55. EP3SL70 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
2.953
1.442
2.949
1.437
2.951
1.439
2.950
1.438
2.968
1.457
2.963
1.452
2.963
1.451
2.953
1.442
2.955
1.443
2.977
1.465
2.966
1.455
2.965
1.453
3.162
1.617
3.157
1.612
3.160
1.615
3.158
1.613
3.177
1.632
3.173
1.628
3.172
1.627
3.162
1.617
3.164
1.619
3.189
1.644
3.177
1.632
3.175
1.630
4.461 4.846 5.345 5.211 5.439 4.963 5.461 5.331 5.505
2.085 2.191 2.412 2.416 2.458 2.296 2.520 2.525 2.366
4.455 4.840 5.339 5.205 5.433 4.957 5.455 5.325 5.499
2.079 2.185 2.406 2.410 2.447 2.290 2.514 2.519 2.360
4.460 4.845 5.345 5.211 5.439 4.963 5.462 5.332 5.506
2.084 2.190 2.412 2.416 2.468 2.296 2.520 2.525 2.366
4.453 4.838 5.337 5.203 5.431 4.955 5.453 5.323 5.497
2.077 2.183 2.404 2.408 2.449 2.288 2.511 2.516 2.357
4.475 4.859 5.358 5.224 5.452 4.977 5.474 5.344 5.518
2.099 2.204 2.425 2.429 2.463 2.310 2.532 2.537 2.378
4.473 4.858 5.357 5.223 5.451 4.976 5.473 5.343 5.517
2.097 2.203 2.424 2.428 2.470 2.309 2.532 2.537 2.378
4.474 4.859 5.358 5.224 5.452 4.977 5.474 5.344 5.518
2.098 2.204 2.425 2.429 2.471 2.310 2.533 2.538 2.379
4.462 4.847 5.346 5.212 5.440 4.964 5.462 5.332 5.506
2.085 2.192 2.413 2.417 2.458 2.297 2.521 2.526 2.367
4.467 4.854 5.354 5.220 5.448 4.971 5.471 5.341 5.515
2.091 2.198 2.421 2.425 2.473 2.304 2.529 2.534 2.375
4.495 4.881 5.380 5.246 5.474 4.999 5.498 5.368 5.542
2.119 2.225 2.447 2.451 2.491 2.332 2.556 2.561 2.402
4.483 4.869 5.369 5.235 5.463 4.987 5.486 5.356 5.530
2.107 2.214 2.436 2.440 2.481 2.320 2.545 2.550 2.391
4.481 4.867 5.367 5.233 5.461 4.986 5.485 5.355 5.529
2.105 2.212 2.434 2.438 2.486 2.319 2.544 2.549 2.390
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS II
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–78
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–55. EP3SL70 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
2.962
1.451
2.958
1.447
3.035
1.524
3.035
1.524
3.064
1.553
2.985
1.474
2.956
1.444
2.942
1.430
3.173
1.628
3.169
1.624
3.244
1.699
3.244
1.699
3.283
1.738
3.194
1.649
3.162
1.617
3.148
1.603
4.480 4.867 5.367 5.233 5.461 4.985 5.485 5.355 5.529
2.104 2.212 2.434 2.438 2.488 2.318 2.544 2.549 2.389
4.474 4.860 5.360 5.226 5.454 4.978 5.478 5.348 5.522
2.097 2.205 2.427 2.431 2.479 2.311 2.536 2.541 2.382
4.491 4.868 5.357 5.223 5.451 4.986 5.475 5.345 5.519
2.115 2.213 2.424 2.428 2.455 2.319 2.534 2.539 2.381
4.491 4.868 5.357 5.223 5.451 4.986 5.475 5.345 5.519
2.115 2.213 2.424 2.428 2.455 2.319 2.534 2.539 2.381
4.557 4.943 5.437 5.303 5.531 5.064 5.556 5.426 5.600
2.181 2.288 2.504 2.508 2.475 2.397 2.615 2.620 2.463
4.454 4.831 5.320 5.186 5.414 4.948 5.436 5.306 5.480
2.077 2.176 2.387 2.391 2.358 2.281 2.495 2.500 2.343
4.387 4.761 5.250 5.116 5.344 4.878 5.369 5.239 5.413
2.010 2.106 2.317 2.321 2.288 2.211 2.428 2.433 2.275
4.366 4.738 5.222 5.088 5.316 4.852 5.336 5.206 5.380
1.989 2.083 2.289 2.293 2.260 2.185 2.394 2.399 2.241
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–79
I/O Timing
Table 1–56 specifies EP3SL70 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–56. EP3SL70 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.424
1.669
3.319
1.598
3.213
1.509
3.428
1.676
3.219
1.513
3.370
1.630
3.243
1.518
3.192
1.480
3.289
1.542
3.170
1.464
3.406
1.667
3.307
1.564
3.231
1.520
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.182
1.474
3.089
1.408
2.990
1.329
3.192
1.476
2.994
1.333
3.136
1.435
3.011
1.334
2.972
1.297
3.050
1.356
2.950
1.284
3.162
1.461
3.052
1.376
3.006
1.319
4.767 5.163 5.668 5.532 5.739 5.293 5.802 5.667 5.813
2.054 2.135 2.377 2.393 2.266 2.251 2.501 2.515 2.258
4.637 5.025 5.524 5.388 5.595 5.152 5.653 5.518 5.664
1.944 2.023 2.233 2.249 2.152 2.138 2.352 2.366 2.142
4.518 4.902 5.396 5.260 5.467 5.025 5.521 5.386 5.532
1.838 1.923 2.119 2.138 2.056 2.039 2.235 2.252 2.043
4.775 5.168 5.673 5.537 5.744 5.299 5.807 5.672 5.818
2.058 2.140 2.382 2.398 2.275 2.259 2.506 2.520 2.270
4.524 4.908 5.402 5.266 5.473 5.031 5.528 5.393 5.539
1.849 1.938 2.129 2.148 2.066 2.051 2.244 2.261 2.052
4.719 5.116 5.625 5.489 5.696 5.250 5.760 5.625 5.771
2.021 2.103 2.334 2.350 2.232 2.219 2.459 2.473 2.224
4.566 4.957 5.461 5.325 5.532 5.088 5.596 5.460 5.606
1.884 1.961 2.170 2.186 2.087 2.077 2.295 2.308 2.078
4.484 4.874 5.373 5.237 5.444 5.002 5.503 5.367 5.513
1.824 1.896 2.082 2.099 2.017 2.009 2.202 2.215 2.005
4.613 5.009 5.514 5.378 5.585 5.142 5.649 5.513 5.659
1.919 1.996 2.223 2.239 2.123 2.111 2.348 2.361 2.114
4.449 4.835 5.334 5.198 5.405 4.962 5.463 5.327 5.473
1.796 1.867 2.052 2.071 1.989 1.979 2.169 2.185 1.976
4.851 5.270 5.797 5.661 5.868 5.410 5.939 5.803 5.949
2.129 2.229 2.506 2.522 2.377 2.351 2.638 2.651 2.376
4.696 5.107 5.627 5.491 5.698 5.243 5.765 5.629 5.775
2.005 2.094 2.336 2.352 2.235 2.214 2.464 2.477 2.231
4.585 4.988 5.501 5.365 5.572 5.120 5.635 5.499 5.645
1.921 2.008 2.210 2.226 2.144 2.125 2.334 2.347 2.137
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
GCLK
PLL
3.3-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–80
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–56. EP3SL70 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.691
1.915
3.489
1.713
3.387
1.611
3.313
1.557
3.609
1.833
3.352
1.576
3.304
1.548
3.295
1.537
3.534
1.758
3.345
1.578
3.217
1.508
3.205
1.504
3.187
1.493
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.350
1.728
3.177
1.503
3.102
1.438
3.084
1.378
3.292
1.639
3.100
1.397
3.073
1.370
3.054
1.361
3.222
1.582
3.105
1.402
2.991
1.323
2.979
1.318
2.963
1.309
5.275 5.573 6.134 5.998 6.210 5.723 6.286 6.151 6.297
2.562 2.717 2.981 2.999 2.946 2.881 3.150 3.167 2.958
4.948 5.247 5.774 5.638 5.850 5.397 5.925 5.789 5.935
2.235 2.349 2.576 2.594 2.541 2.516 2.744 2.760 2.551
4.795 5.142 5.673 5.537 5.749 5.283 5.819 5.684 5.830
2.082 2.199 2.417 2.435 2.382 2.348 2.571 2.588 2.379
4.718 5.089 5.608 5.472 5.684 5.227 5.747 5.612 5.758
2.005 2.106 2.321 2.339 2.286 2.253 2.477 2.494 2.285
5.185 5.500 6.071 5.935 6.147 5.644 6.221 6.086 6.232
2.472 2.631 2.909 2.927 2.874 2.788 3.074 3.091 2.882
4.780 5.142 5.677 5.541 5.753 5.280 5.820 5.685 5.831
2.067 2.194 2.418 2.436 2.383 2.342 2.570 2.587 2.378
4.707 5.081 5.608 5.472 5.684 5.220 5.747 5.612 5.758
1.994 2.098 2.312 2.330 2.277 2.244 2.465 2.482 2.273
4.685 5.057 5.589 5.453 5.665 5.196 5.728 5.593 5.739
1.972 2.080 2.293 2.311 2.258 2.226 2.443 2.460 2.251
5.095 5.432 6.010 5.874 6.086 5.576 6.152 6.017 6.163
2.382 2.545 2.834 2.852 2.799 2.700 2.990 3.007 2.798
4.802 5.170 5.725 5.589 5.801 5.309 5.864 5.729 5.875
2.089 2.222 2.459 2.477 2.424 2.367 2.612 2.629 2.420
4.563 4.960 5.469 5.333 5.540 5.087 5.597 5.462 5.608
1.914 1.999 2.197 2.216 2.134 2.112 2.315 2.332 2.123
4.555 4.952 5.461 5.325 5.532 5.079 5.590 5.455 5.601
1.911 1.997 2.195 2.214 2.132 2.111 2.314 2.331 2.122
4.530 4.927 5.434 5.298 5.505 5.053 5.563 5.428 5.574
1.896 1.981 2.178 2.197 2.115 2.094 2.296 2.313 2.104
2mA
4mA
6mA
8mA
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
1.8 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
SSTL-2
CLASS I
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS II
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–81
I/O Timing
Table 1–56. EP3SL70 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.269
1.501
3.255
1.496
3.243
1.485
3.220
1.474
3.219
1.473
3.228
1.480
3.223
1.483
3.265
1.504
3.243
1.490
3.226
1.478
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.033
1.339
3.028
1.324
3.017
1.313
3.006
1.290
3.006
1.290
3.014
1.299
3.015
1.299
3.036
1.335
3.022
1.312
3.011
1.295
4.613 4.993 5.503 5.367 5.579 5.126 5.638 5.503 5.649
1.909 1.997 2.194 2.212 2.159 2.134 2.340 2.357 2.148
4.610 4.992 5.502 5.366 5.578 5.124 5.636 5.501 5.647
1.907 1.996 2.192 2.210 2.157 2.132 2.338 2.355 2.146
4.593 4.982 5.492 5.356 5.568 5.115 5.627 5.492 5.638
1.897 1.986 2.175 2.193 2.140 2.115 2.322 2.339 2.130
4.577 4.969 5.479 5.343 5.555 5.103 5.615 5.480 5.626
1.884 1.973 2.160 2.178 2.125 2.100 2.307 2.324 2.115
4.576 4.969 5.479 5.343 5.555 5.102 5.615 5.480 5.626
1.884 1.973 2.159 2.177 2.124 2.099 2.306 2.323 2.114
4.574 4.966 5.474 5.338 5.550 5.098 5.609 5.474 5.620
1.883 1.970 2.153 2.171 2.118 2.094 2.299 2.316 2.107
4.573 4.974 5.484 5.348 5.560 5.107 5.620 5.485 5.631
1.889 1.978 2.155 2.173 2.120 2.096 2.303 2.320 2.111
4.624 5.004 5.516 5.380 5.592 5.136 5.650 5.515 5.661
1.918 2.008 2.211 2.229 2.176 2.147 2.356 2.373 2.164
4.606 4.994 5.506 5.370 5.582 5.127 5.641 5.506 5.652
1.907 1.998 2.194 2.212 2.159 2.131 2.340 2.357 2.148
4.589 4.981 5.493 5.357 5.569 5.114 5.628 5.493 5.639
1.894 1.985 2.176 2.194 2.141 2.113 2.323 2.340 2.131
4mA
6mA
8mA
10mA
12mA
8mA
16mA
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-18
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–82
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–56. EP3SL70 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.241
1.486
3.229
1.480
3.217
1.472
3.219
1.474
3.214
1.471
3.218
1.479
3.248
1.492
3.238
1.487
3.233
1.483
3.247
1.494
3.235
1.486
3.233
1.486
3.300
1.614
3.300
1.614
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.021
1.314
3.014
1.302
3.005
1.289
3.008
1.292
3.004
1.288
3.012
1.296
3.027
1.321
3.021
1.309
3.017
1.305
3.029
1.320
3.020
1.308
3.019
1.305
3.076
1.429
3.076
1.429
4.580 4.964 5.472 5.336 5.548 5.097 5.606 5.471 5.617
1.882 1.968 2.156 2.174 2.121 2.098 2.302 2.319 2.110
4.571 4.963 5.471 5.335 5.547 5.096 5.606 5.471 5.617
1.880 1.967 2.148 2.166 2.113 2.090 2.295 2.312 2.103
4.563 4.956 5.464 5.328 5.540 5.089 5.599 5.464 5.610
1.873 1.960 2.140 2.158 2.105 2.082 2.287 2.304 2.095
4.565 4.959 5.468 5.332 5.544 5.092 5.602 5.467 5.613
1.876 1.963 2.143 2.161 2.108 2.085 2.290 2.307 2.098
4.563 4.962 5.471 5.335 5.547 5.095 5.607 5.472 5.618
1.878 1.966 2.143 2.161 2.108 2.085 2.291 2.308 2.099
4.558 4.959 5.467 5.331 5.543 5.091 5.601 5.466 5.612
1.876 1.963 2.134 2.152 2.099 2.078 2.280 2.297 2.088
4.591 4.974 5.483 5.347 5.559 5.106 5.617 5.482 5.628
1.891 1.978 2.171 2.189 2.136 2.110 2.316 2.333 2.124
4.587 4.976 5.485 5.349 5.561 5.108 5.620 5.485 5.631
1.892 1.980 2.167 2.185 2.132 2.107 2.313 2.330 2.121
4.581 4.971 5.480 5.344 5.556 5.103 5.614 5.479 5.625
1.887 1.975 2.161 2.179 2.126 2.101 2.307 2.324 2.115
4.602 4.990 5.502 5.366 5.578 5.122 5.636 5.501 5.647
1.904 1.994 2.189 2.207 2.154 2.124 2.333 2.350 2.141
4.591 4.981 5.493 5.357 5.569 5.113 5.627 5.492 5.638
1.895 1.985 2.177 2.195 2.142 2.113 2.322 2.339 2.130
4.595 4.989 5.502 5.366 5.578 5.122 5.637 5.502 5.648
1.902 1.993 2.183 2.201 2.148 2.119 2.329 2.346 2.137
4.588 4.978 5.480 5.342 5.550 5.105 5.610 5.474 5.621
1.966 2.045 2.237 2.256 2.174 2.160 2.357 2.374 2.165
4.588 4.978 5.480 5.342 5.550 5.105 5.610 5.474 5.621
1.966 2.045 2.237 2.256 2.174 2.160 2.357 2.374 2.165
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
—
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
1.5-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK tco
GCLK
tco
PLL
1.2-V
HSTL
CLASS I
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–83
I/O Timing
Table 1–57 through Table 1–62 show the maximum I/O timing parameters for
EP3SL70 devices for differential I/O standards.
Table 1–57 specifies EP3SL70 column pins input timing parameters for differential
I/O standards.
Table 1–57. EP3SL70 Column Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.697
0.814
1.143
-0.892
-0.697
0.814
1.143
-0.892
-0.705
0.822
1.135
-0.884
-0.705
0.822
1.135
-0.884
-0.717
0.834
1.123
-0.872
-0.717
0.834
1.123
-0.872
-0.705
0.822
1.135
-0.884
-0.705
0.822
1.135
-0.884
-0.717
0.849
1.159
-0.893
-0.717
0.849
1.159
-0.893
-0.729
0.861
1.147
-0.881
-0.729
0.861
1.147
-0.881
-0.740
0.872
1.136
-0.870
-0.740
0.872
1.136
-0.870
-0.729
0.861
1.147
-0.881
-0.729
0.861
1.147
-0.881
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 ns
GCLK
1.257 1.389 1.522 1.454 1.740 1.398 1.532 1.469 1.777
1.821 2.053 2.279 2.166 2.172 2.063 2.288 2.173 2.219
ns
ns
LVDS
tsu
th
GCLK
PLL
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 ns
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 ns
tsu
th
GCLK
1.257 1.389 1.522 1.454 1.740 1.398 1.532 1.469 1.777
1.821 2.053 2.279 2.166 2.172 2.063 2.288 2.173 2.219
ns
ns
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
1.277 1.411 1.557 1.489 1.775 1.420 1.565 1.502 1.810
1.802 2.031 2.244 2.131 2.137 2.041 2.255 2.140 2.186
ns
ns
tsu
th
GCLK
PLL
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 ns
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
1.277 1.411 1.557 1.489 1.775 1.420 1.565 1.502 1.810
1.802 2.031 2.244 2.131 2.137 2.041 2.255 2.140 2.186
ns
ns
tsu
th
GCLK
PLL
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–84
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–57. EP3SL70 Column Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.717
0.834
1.123
-0.872
-0.717
0.834
1.123
-0.872
-0.724
0.841
1.116
-0.865
-0.724
0.841
1.116
-0.865
-0.697
0.814
1.143
-0.892
-0.697
0.814
1.143
-0.892
-0.705
0.822
1.135
-0.884
-0.740
0.872
1.136
-0.870
-0.740
0.872
1.136
-0.870
-0.746
0.878
1.130
-0.864
-0.746
0.878
1.130
-0.864
-0.717
0.849
1.159
-0.893
-0.717
0.849
1.159
-0.893
-0.729
0.861
1.147
-0.881
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
1.277 1.411 1.557 1.489 1.775 1.420 1.565 1.502 1.810
1.802 2.031 2.244 2.131 2.137 2.041 2.255 2.140 2.186
ns
ns
tsu
th
GCLK
PLL
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 ns
-1.091 -1.204 -1.329 -1.272 -1.559 -1.205 -1.329 -1.275 -1.595 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
1.277 1.411 1.557 1.489 1.775 1.420 1.565 1.502 1.810
1.802 2.031 2.244 2.131 2.137 2.041 2.255 2.140 2.186
ns
ns
tsu
th
GCLK
PLL
-1.404 -1.584 -1.746 -1.661 -1.661 -1.586 -1.749 -1.661 -1.709 ns
-1.103 -1.209 -1.329 -1.274 -1.558 -1.209 -1.324 -1.273 -1.591 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
1.290 1.419 1.560 1.492 1.779 1.427 1.565 1.501 1.811
1.790 2.026 2.244 2.129 2.138 2.037 2.260 2.142 2.190
ns
ns
tsu
th
GCLK
PLL
-1.391 -1.576 -1.743 -1.658 -1.657 -1.579 -1.749 -1.662 -1.708 ns
-1.103 -1.209 -1.329 -1.274 -1.558 -1.209 -1.324 -1.273 -1.591 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
1.290 1.419 1.560 1.492 1.779 1.427 1.565 1.501 1.811
1.790 2.026 2.244 2.129 2.138 2.037 2.260 2.142 2.190
ns
ns
tsu
th
GCLK
PLL
-1.391 -1.576 -1.743 -1.658 -1.657 -1.579 -1.749 -1.662 -1.708 ns
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
1.257 1.389 1.522 1.454 1.740 1.398 1.532 1.469 1.777
1.821 2.053 2.279 2.166 2.172 2.063 2.288 2.173 2.219
ns
ns
tsu
th
GCLK
PLL
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 ns
-1.072 -1.182 -1.294 -1.237 -1.524 -1.183 -1.296 -1.242 -1.562 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
1.257 1.389 1.522 1.454 1.740 1.398 1.532 1.469 1.777
1.821 2.053 2.279 2.166 2.172 2.063 2.288 2.173 2.219
ns
ns
tsu
th
GCLK
PLL
-1.424 -1.606 -1.781 -1.696 -1.696 -1.608 -1.782 -1.694 -1.742 ns
-1.082 -1.193 -1.310 -1.253 -1.540 -1.194 -1.311 -1.257 -1.577 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
1.267 1.400 1.538 1.470 1.756 1.409 1.547 1.484 1.792
1.811 2.042 2.263 2.150 2.156 2.052 2.273 2.158 2.204
ns
ns
tsu
th
GCLK
PLL
-1.414 -1.595 -1.765 -1.680 -1.680 -1.597 -1.767 -1.679 -1.727 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–85
I/O Timing
Table 1–58 specifies EP3SL70 row pins input timing parameters for differential I/O
standards.
Table 1–58. EP3SL70 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.919
1.042
0.882
-0.625
-0.919
1.042
0.882
-0.625
-0.919
1.042
0.882
-0.625
-0.734
0.850
1.077
-0.827
-0.734
0.850
1.077
-0.827
-0.743
0.859
1.068
-0.818
-0.743
0.859
1.068
-0.818
-0.757
0.873
1.054
-0.804
-0.939
1.077
0.896
-0.625
-0.939
1.077
0.896
-0.625
-0.939
1.077
0.896
-0.625
-0.764
0.893
1.081
-0.819
-0.764
0.893
1.081
-0.819
-0.776
0.905
1.069
-0.807
-0.776
0.905
1.069
-0.807
-0.788
0.917
1.057
-0.795
-0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 ns
GCLK
1.209 1.205 1.369 1.306 1.580 1.182 1.339 1.280 1.613
1.863 2.243 2.446 2.322 2.342 2.291 2.500 2.376 2.393
ns
ns
LVDS
tsu
th
GCLK
PLL
-1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 ns
-0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 ns
tsu
th
GCLK
1.209 1.205 1.369 1.306 1.580 1.182 1.339 1.280 1.613
1.863 2.243 2.446 2.322 2.342 2.291 2.500 2.376 2.393
ns
ns
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
-1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 ns
-0.988 -0.952 -1.089 -1.040 -1.316 -0.916 -1.048 -1.000 -1.349 ns
tsu
th
GCLK
1.209 1.205 1.369 1.306 1.580 1.182 1.339 1.280 1.613
1.863 2.243 2.446 2.322 2.342 2.291 2.500 2.376 2.393
ns
ns
tsu
th
GCLK
PLL
-1.430 -1.749 -1.896 -1.802 -1.817 -1.783 -1.936 -1.843 -1.865 ns
-1.085 -1.186 -1.286 -1.234 -1.505 -1.193 -1.291 -1.242 -1.543 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS I
1.274 1.394 1.516 1.451 1.720 1.410 1.531 1.470 1.758
1.776 2.019 2.257 2.138 2.163 2.024 2.263 2.144 2.209
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.570 -1.756 -1.667 -1.687 -1.565 -1.751 -1.663 -1.730 ns
-1.085 -1.186 -1.286 -1.234 -1.505 -1.193 -1.291 -1.242 -1.543 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS II
1.274 1.394 1.516 1.451 1.720 1.410 1.531 1.470 1.758
1.776 2.019 2.257 2.138 2.163 2.024 2.263 2.144 2.209
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.570 -1.756 -1.667 -1.687 -1.565 -1.751 -1.663 -1.730 ns
-1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS I
1.283 1.404 1.532 1.467 1.736 1.419 1.547 1.486 1.774
1.767 2.009 2.241 2.122 2.147 2.015 2.247 2.128 2.193
ns
ns
tsu
th
GCLK
PLL
-1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 ns
-1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS II
1.283 1.404 1.532 1.467 1.736 1.419 1.547 1.486 1.774
1.767 2.009 2.241 2.122 2.147 2.015 2.247 2.128 2.193
ns
ns
tsu
th
GCLK
PLL
-1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 ns
-1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS I
1.295 1.414 1.550 1.485 1.754 1.430 1.564 1.503 1.791
1.754 1.999 2.223 2.104 2.129 2.004 2.230 2.111 2.176
ns
ns
tsu
th
GCLK
PLL
-1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–86
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–58. EP3SL70 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.757
0.873
1.054
-0.804
-0.743
0.859
1.068
-0.818
-0.743
0.859
1.068
-0.818
-0.757
0.873
1.054
-0.804
-0.757
0.873
1.054
-0.804
-0.756
0.872
1.045
-0.795
-0.756
0.872
1.045
-0.795
-0.788
0.917
1.057
-0.795
-0.776
0.905
1.069
-0.807
-0.776
0.905
1.069
-0.807
-0.788
0.917
1.057
-0.795
-0.788
0.917
1.057
-0.795
-0.787
0.916
1.048
-0.786
-0.787
0.916
1.048
-0.786
-1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ns
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS II
1.295 1.414 1.550 1.485 1.754 1.430 1.564 1.503 1.791
1.754 1.999 2.223 2.104 2.129 2.004 2.230 2.111 2.176
ns
ns
tsu
th
GCLK
PLL
-1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 ns
-1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS I
1.283 1.404 1.532 1.467 1.736 1.419 1.547 1.486 1.774
1.767 2.009 2.241 2.122 2.147 2.015 2.247 2.128 2.193
ns
ns
tsu
th
GCLK
PLL
-1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 ns
-1.094 -1.196 -1.302 -1.250 -1.521 -1.202 -1.307 -1.258 -1.559 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS II
1.283 1.404 1.532 1.467 1.736 1.419 1.547 1.486 1.774
1.767 2.009 2.241 2.122 2.147 2.015 2.247 2.128 2.193
ns
ns
tsu
th
GCLK
PLL
-1.366 -1.560 -1.740 -1.651 -1.671 -1.556 -1.735 -1.647 -1.714 ns
-1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS I
1.295 1.414 1.550 1.485 1.754 1.430 1.564 1.503 1.791
1.754 1.999 2.223 2.104 2.129 2.004 2.230 2.111 2.176
ns
ns
tsu
th
GCLK
PLL
-1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 ns
-1.107 -1.206 -1.320 -1.268 -1.539 -1.213 -1.324 -1.275 -1.576 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS II
1.295 1.414 1.550 1.485 1.754 1.430 1.564 1.503 1.791
1.754 1.999 2.223 2.104 2.129 2.004 2.230 2.111 2.176
ns
ns
tsu
th
GCLK
PLL
-1.354 -1.550 -1.722 -1.633 -1.653 -1.545 -1.718 -1.630 -1.697 ns
-1.112 -1.212 -1.321 -1.270 -1.540 -1.214 -1.320 -1.273 -1.573 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS I
1.300 1.422 1.554 1.489 1.759 1.434 1.563 1.502 1.792
1.739 1.983 2.212 2.092 2.118 1.993 2.224 2.103 2.169
ns
ns
tsu
th
GCLK
PLL
-1.339 -1.532 -1.708 -1.619 -1.638 -1.531 -1.709 -1.621 -1.686 ns
-1.112 -1.212 -1.321 -1.270 -1.540 -1.214 -1.320 -1.273 -1.573 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS II
1.300 1.422 1.554 1.489 1.759 1.434 1.563 1.502 1.792
1.739 1.983 2.212 2.092 2.118 1.993 2.224 2.103 2.169
ns
ns
tsu
th
GCLK
PLL
-1.339 -1.532 -1.708 -1.619 -1.638 -1.531 -1.709 -1.621 -1.686 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–87
I/O Timing
Table 1–59 specifies EP3SL70 Column Pins Output Timing parameters for differential
I/O standards.
Table 1–59. EP3SL70 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.010
1.310
3.006
1.306
3.010
1.310
3.006
1.306
3.010
1.310
3.006
1.306
3.037
1.337
3.027
1.327
3.027
1.327
3.020
1.320
3.019
1.319
3.041
1.341
3.226
1.491
3.229
1.494
3.226
1.491
3.229
1.494
3.226
1.491
3.229
1.494
3.259
1.524
3.249
1.514
3.249
1.514
3.243
1.508
3.241
1.506
3.263
1.528
4.551 4.950 5.459 5.320 5.538 5.075 5.584 5.446 5.604
1.876 1.961 2.162 2.176 2.109 2.074 2.277 2.291 2.093
4.598 5.005 5.521 5.382 5.600 5.134 5.650 5.512 5.670
1.923 2.016 2.224 2.238 2.171 2.133 2.343 2.357 2.159
4.551 4.950 5.459 5.320 5.538 5.075 5.584 5.446 5.604
—
—
LVDS_E_1R
LVDS_E_3R
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
1.876 1.961 2.162 2.176 2.109 2.074 2.277 2.291 2.093 ns
ns
GCLK
4.598 5.005 5.521 5.382 5.600 5.134 5.650 5.512 5.670
1.923 2.016 2.224 2.238 2.171 2.133 2.343 2.357 2.159 ns
ns
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
4.551 4.950 5.459 5.320 5.538 5.075 5.584 5.446 5.604
1.876 1.961 2.162 2.176 2.109 2.074 2.277 2.291 2.093 ns
ns
—
RSDS_E_1R
RSDS_E_3R
GCLK
PLL
GCLK
4.598 5.005 5.521 5.382 5.600 5.134 5.650 5.512 5.670
1.923 2.016 2.224 2.238 2.171 2.133 2.343 2.357 2.159 ns
ns
—
GCLK
PLL
GCLK
4.622 5.028 5.543 5.404 5.622 5.155 5.670 5.532 5.690
1.947 2.039 2.246 2.260 2.193 2.154 2.363 2.377 2.179 ns
ns
4mA
6mA
8mA
GCLK
PLL
GCLK
4.612 5.017 5.533 5.394 5.612 5.144 5.660 5.522 5.680
1.937 2.028 2.236 2.250 2.183 2.143 2.353 2.367 2.169 ns
ns
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
4.615 5.021 5.537 5.398 5.616 5.149 5.665 5.527 5.685
1.940 2.032 2.240 2.254 2.187 2.148 2.358 2.372 2.174 ns
ns
GCLK
PLL
GCLK
4.608 5.015 5.531 5.392 5.610 5.142 5.659 5.521 5.679
1.933 2.026 2.234 2.248 2.181 2.141 2.352 2.366 2.168 ns
10m
A
GCLK
PLL
GCLK
ns
ns
ns
ns
4.605 5.012 5.528 5.389 5.607 5.139 5.655 5.517 5.675
1.930 2.023 2.231 2.245 2.178 2.138 2.348 2.362 2.164
4.626 5.032 5.547 5.408 5.626 5.159 5.675 5.537 5.695
1.951 2.043 2.250 2.264 2.197 2.158 2.368 2.382 2.184
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
16m
A
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–88
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–59. EP3SL70 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.031
1.331
3.026
1.326
3.024
1.324
3.016
1.316
3.017
1.317
3.016
1.316
3.028
1.328
3.024
1.324
3.014
1.314
3.012
1.312
3.012
1.312
3.016
1.316
3.252
1.517
3.248
1.513
3.246
1.511
3.237
1.502
3.239
1.504
3.236
1.501
3.249
1.514
3.246
1.511
3.235
1.500
3.233
1.498
3.234
1.499
3.237
1.502
4.605 5.009 5.522 5.383 5.601 5.135 5.648 5.510 5.668
1.930 2.020 2.225 2.239 2.172 2.134 2.341 2.355 2.157
4.605 5.009 5.523 5.384 5.602 5.136 5.650 5.512 5.670
1.930 2.020 2.226 2.240 2.173 2.135 2.343 2.357 2.159
4.604 5.008 5.521 5.382 5.600 5.135 5.649 5.511 5.669
1.929 2.019 2.224 2.238 2.171 2.134 2.342 2.356 2.158
4.594 4.998 5.512 5.373 5.591 5.125 5.639 5.501 5.659
1.919 2.009 2.215 2.229 2.162 2.124 2.332 2.346 2.148
4.600 5.005 5.520 5.381 5.599 5.133 5.648 5.510 5.668
1.925 2.016 2.223 2.237 2.170 2.132 2.341 2.355 2.157
4.583 4.986 5.498 5.359 5.577 5.112 5.624 5.486 5.644
1.908 1.997 2.201 2.215 2.148 2.111 2.317 2.331 2.133
4.601 5.004 5.516 5.377 5.595 5.131 5.643 5.505 5.663
1.926 2.015 2.219 2.233 2.166 2.130 2.336 2.350 2.152
4.602 5.006 5.520 5.381 5.599 5.133 5.647 5.509 5.667
1.927 2.017 2.223 2.237 2.170 2.132 2.340 2.354 2.156
4.591 4.995 5.508 5.369 5.587 5.122 5.635 5.497 5.655
1.916 2.006 2.211 2.225 2.158 2.121 2.328 2.342 2.144
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
4.589 4.992 5.506 5.367 5.585 5.120 5.633 5.495 5.653 ns
ns
10m
A
GCLK
PLL
1.914 2.003 2.209 2.223 2.156 2.119 2.326 2.340 2.142
4.592 4.997 5.511 5.372 5.590 5.124 5.639 5.501 5.659 ns
ns
GCLK
12m
A
GCLK
PLL
1.917 2.008 2.214 2.228 2.161 2.123 2.332 2.346 2.148
4.589 4.992 5.505 5.366 5.584 5.119 5.632 5.494 5.652 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
16m
A
GCLK
PLL
ns
1.914 2.003 2.208 2.222 2.155 2.118 2.325 2.339 2.141
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–89
I/O Timing
Table 1–59. EP3SL70 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.042
1.342
3.028
1.328
3.016
1.316
3.016
1.316
3.012
1.312
3.016
1.316
3.017
1.317
3.045
1.345
3.034
1.334
3.029
1.329
3.015
1.315
3.013
1.313
3.017
1.317
3.017
1.317
3.266
1.531
3.252
1.517
3.239
1.504
3.239
1.504
3.235
1.500
3.237
1.502
3.239
1.504
3.269
1.534
3.257
1.522
3.253
1.518
3.238
1.503
3.236
1.501
3.238
1.503
3.239
1.504
4.634 5.040 5.555 5.416 5.634 5.167 5.682 5.544 5.702
1.959 2.051 2.258 2.272 2.205 2.166 2.375 2.389 2.191
4.622 5.029 5.545 5.406 5.624 5.157 5.673 5.535 5.693
1.947 2.040 2.248 2.262 2.195 2.156 2.366 2.380 2.182
4.605 5.011 5.527 5.388 5.606 5.139 5.655 5.517 5.675
1.930 2.022 2.230 2.244 2.177 2.138 2.348 2.362 2.164
4.608 5.015 5.531 5.392 5.610 5.143 5.660 5.522 5.680
1.933 2.026 2.234 2.248 2.181 2.142 2.353 2.367 2.169
4.601 5.007 5.524 5.385 5.603 5.136 5.652 5.514 5.672
1.926 2.018 2.227 2.241 2.174 2.135 2.345 2.359 2.161
4.594 4.998 5.512 5.373 5.591 5.125 5.639 5.501 5.659
1.919 2.009 2.215 2.229 2.162 2.124 2.332 2.346 2.148
4.602 5.008 5.523 5.384 5.602 5.135 5.651 5.513 5.671
1.927 2.019 2.226 2.240 2.173 2.134 2.344 2.358 2.160
4.633 5.038 5.553 5.414 5.632 5.166 5.680 5.542 5.700
1.958 2.049 2.256 2.270 2.203 2.165 2.373 2.387 2.189
4.621 5.026 5.541 5.402 5.620 5.154 5.668 5.530 5.688
1.946 2.037 2.244 2.258 2.191 2.153 2.361 2.375 2.177
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
8mA
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
4.621 5.027 5.542 5.403 5.621 5.155 5.670 5.532 5.690 ns
ns
GCLK
PLL
1.946 2.038 2.245 2.259 2.192 2.154 2.363 2.377 2.179
4.603 5.008 5.523 5.384 5.602 5.136 5.652 5.514 5.672 ns
ns
GCLK
10m
A
GCLK
PLL
1.928 2.019 2.226 2.240 2.173 2.135 2.345 2.359 2.161
4.601 5.006 5.521 5.382 5.600 5.134 5.649 5.511 5.669 ns
ns
GCLK
12m
A
GCLK
PLL
1.926 2.017 2.224 2.238 2.171 2.133 2.342 2.356 2.158
4.593 4.996 5.509 5.370 5.588 5.123 5.636 5.498 5.656 ns
ns
GCLK
8mA
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
1.918 2.007 2.212 2.226 2.159 2.122 2.329 2.343 2.145
4.601 5.006 5.521 5.382 5.600 5.134 5.649 5.511 5.669 ns
GCLK
16m
A
GCLK
PLL
ns
1.926 2.017 2.224 2.238 2.171 2.133 2.342 2.356 2.158
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–90
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–59. EP3SL70 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.033
1.333
3.033
1.333
3.023
1.323
3.016
1.316
3.256
1.521
3.256
1.521
3.246
1.511
3.238
1.503
4.617 5.021 5.535 5.396 5.614 5.149 5.662 5.524 5.682
1.942 2.032 2.238 2.252 2.185 2.148 2.355 2.369 2.171
4.617 5.021 5.535 5.396 5.614 5.149 5.662 5.524 5.682
1.942 2.032 2.238 2.252 2.185 2.148 2.355 2.369 2.171
4.607 5.011 5.525 5.386 5.604 5.139 5.653 5.515 5.673
1.932 2.022 2.228 2.242 2.175 2.138 2.346 2.360 2.162
4.593 4.996 5.509 5.370 5.588 5.123 5.636 5.498 5.656
1.918 2.007 2.212 2.226 2.159 2.122 2.329 2.343 2.145
8mA
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
16m
A
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–91
I/O Timing
Table 1–60 specifies EP3SL70 Row Pins Output Timing parameters for differential I/O
standards.
Table 1–60. EP3SL70 Row Pins output Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
LVDS
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
2.665
1.008
3.043
1.386
3.025
1.368
2.665
1.008
3.043
1.386
3.025
1.368
2.665
1.008
3.043
1.386
3.025
1.368
3.079
1.402
3.065
1.388
3.061
1.384
3.077
1.400
2.838
1.142
3.268
1.572
3.258
1.562
2.838
1.142
3.268
1.572
3.258
1.562
2.838
1.142
3.268
1.572
3.258
1.562
3.311
1.595
3.297
1.581
3.293
1.577
3.308
1.592
3.975 4.342 4.820 4.684 4.891 4.449 4.928 4.793 4.939
1.343 1.399 1.567 1.586 1.504 1.493 1.665 1.682 1.473
4.622 5.029 5.547 5.404 5.603 5.160 5.681 5.537 5.667
1.990 2.086 2.294 2.306 2.216 2.204 2.418 2.426 2.201
4.660 5.075 5.601 5.458 5.657 5.211 5.742 5.598 5.728
2.028 2.132 2.348 2.360 2.270 2.255 2.479 2.487 2.262
3.975 4.342 4.820 4.684 4.891 4.449 4.928 4.793 4.939
1.343 1.399 1.567 1.586 1.504 1.493 1.665 1.682 1.473
4.622 5.029 5.547 5.404 5.603 5.160 5.681 5.537 5.667
1.990 2.086 2.294 2.306 2.216 2.204 2.418 2.426 2.201
4.660 5.075 5.601 5.458 5.657 5.211 5.742 5.598 5.728
2.028 2.132 2.348 2.360 2.270 2.255 2.479 2.487 2.262
3.975 4.342 4.820 4.684 4.891 4.449 4.928 4.793 4.939
1.343 1.399 1.567 1.586 1.504 1.493 1.665 1.682 1.473
4.622 5.029 5.547 5.404 5.603 5.160 5.681 5.537 5.667
1.990 2.086 2.294 2.306 2.216 2.204 2.418 2.426 2.201
4.660 5.075 5.601 5.458 5.657 5.211 5.742 5.598 5.728
2.028 2.132 2.348 2.360 2.270 2.255 2.479 2.487 2.262
4.706 5.119 5.644 5.501 5.700 5.254 5.781 5.637 5.767
2.054 2.156 2.371 2.383 2.293 2.278 2.498 2.506 2.281
4.693 5.106 5.631 5.488 5.687 5.240 5.768 5.624 5.754
2.041 2.143 2.358 2.370 2.280 2.264 2.485 2.493 2.268
4.691 5.106 5.632 5.489 5.688 5.240 5.770 5.626 5.756
2.039 2.143 2.359 2.371 2.281 2.264 2.487 2.495 2.270
4.692 5.103 5.626 5.483 5.682 5.237 5.763 5.619 5.749
2.040 2.140 2.353 2.365 2.275 2.261 2.480 2.488 2.263
—
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
—
GCLK
tco
PLL
GCLK tco
RSDS
—
GCLK
tco
PLL
GCLK tco
RSDS_E_1R
RSDS_E_3R
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
4mA
6mA
8mA
4mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–92
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–60. EP3SL70 Row Pins output Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.066
1.389
3.063
1.386
3.074
1.397
3.064
1.387
3.050
1.373
3.047
1.370
3.044
1.367
3.045
1.368
3.094
1.417
3.070
1.393
3.052
1.375
3.098
1.421
3.083
1.406
3.298
1.582
3.295
1.579
3.305
1.589
3.296
1.580
3.282
1.566
3.278
1.562
3.276
1.560
3.276
1.560
3.329
1.613
3.305
1.589
3.286
1.570
3.332
1.616
3.317
1.601
4.688 5.099 5.623 5.480 5.679 5.234 5.760 5.616 5.746
2.036 2.136 2.350 2.362 2.272 2.258 2.477 2.485 2.260
4.686 5.097 5.621 5.478 5.677 5.232 5.759 5.615 5.745
2.034 2.134 2.348 2.360 2.270 2.256 2.476 2.484 2.259
4.687 5.098 5.620 5.477 5.676 5.231 5.757 5.613 5.743
2.035 2.135 2.347 2.359 2.269 2.255 2.474 2.482 2.257
4.685 5.096 5.619 5.476 5.675 5.231 5.757 5.613 5.743
2.033 2.133 2.346 2.358 2.268 2.255 2.474 2.482 2.257
4.670 5.081 5.605 5.462 5.661 5.216 5.742 5.598 5.728
2.018 2.118 2.332 2.344 2.254 2.240 2.459 2.467 2.242
4.666 5.077 5.601 5.458 5.657 5.212 5.738 5.594 5.724
2.014 2.114 2.328 2.340 2.250 2.236 2.455 2.463 2.238
4.667 5.080 5.604 5.461 5.660 5.215 5.742 5.598 5.728
2.015 2.117 2.331 2.343 2.253 2.239 2.459 2.467 2.242
4.657 5.068 5.591 5.448 5.647 5.202 5.728 5.584 5.714
2.005 2.105 2.318 2.330 2.240 2.226 2.445 2.453 2.228
4.728 5.141 5.667 5.524 5.723 5.276 5.804 5.660 5.790
2.076 2.178 2.394 2.406 2.316 2.300 2.521 2.529 2.304
4.710 5.124 5.650 5.507 5.706 5.259 5.789 5.645 5.775
2.058 2.161 2.377 2.389 2.299 2.283 2.506 2.514 2.289
4.688 5.102 5.628 5.485 5.684 5.237 5.767 5.623 5.753
2.036 2.139 2.355 2.367 2.277 2.261 2.484 2.492 2.267
4.728 5.141 5.666 5.523 5.722 5.276 5.804 5.660 5.790
2.076 2.178 2.393 2.405 2.315 2.300 2.521 2.529 2.304
4.714 5.126 5.651 5.508 5.707 5.261 5.789 5.645 5.775
2.062 2.163 2.378 2.390 2.300 2.285 2.506 2.514 2.289
DIFFERENTIAL
1.5-V
HSTL CLASS I
6mA
8mA
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
10m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
12m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS II
16m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
4mA
6mA
8mA
4mA
6mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–93
I/O Timing
Table 1–60. EP3SL70 Row Pins output Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.072
1.395
3.052
1.375
3.049
1.372
3.054
1.377
3.047
1.370
3.075
1.418
3.057
1.400
3.043
1.386
3.306
1.590
3.286
1.570
3.282
1.566
3.286
1.570
3.279
1.563
3.308
1.612
3.291
1.595
3.275
1.579
4.709 5.123 5.648 5.505 5.704 5.258 5.787 5.643 5.773
2.057 2.160 2.375 2.387 2.297 2.282 2.504 2.512 2.287
4.686 5.099 5.625 5.482 5.681 5.235 5.763 5.619 5.749
2.034 2.136 2.352 2.364 2.274 2.259 2.480 2.488 2.263
4.682 5.096 5.621 5.478 5.677 5.231 5.760 5.616 5.746
2.030 2.133 2.348 2.360 2.270 2.255 2.477 2.485 2.260
4.673 5.084 5.607 5.464 5.663 5.218 5.744 5.600 5.730
2.021 2.121 2.334 2.346 2.256 2.242 2.461 2.469 2.244
4.672 5.085 5.610 5.467 5.666 5.221 5.749 5.605 5.735
2.020 2.122 2.337 2.349 2.259 2.245 2.466 2.474 2.249
4.700 5.112 5.636 5.493 5.692 5.247 5.774 5.630 5.760
2.068 2.169 2.383 2.395 2.305 2.291 2.511 2.519 2.294
4.685 5.097 5.621 5.478 5.677 5.232 5.759 5.615 5.745
2.053 2.154 2.368 2.380 2.290 2.276 2.496 2.504 2.279
4.662 5.073 5.596 5.453 5.652 5.208 5.734 5.590 5.720
2.030 2.130 2.343 2.355 2.265 2.252 2.471 2.479 2.254
DIFFERENTIAL
1.8-V
SSTL CLASS I
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
10m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
12m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
16m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
12m
A
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS II
16m
A
GCLK
tco
PLL
Table 1–61 and Table 1–62 show EP3SL70 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
Table 1–61 specifies EP3SL70 Column Pin delay adders when using the regional clock.
Table 1–61. EP3SL70 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.158
-0.014
-0.114
1.642
0.168
-0.012
-0.116
1.675
0.225 0.241 0.257 0.247 0.313 0.244 0.258 0.252 0.315
-0.007 -0.003 -0.002 -0.005 0.191 -0.003 -0.003 -0.004 0.191
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
-0.137 -0.139 -0.141 -0.137 -0.215 -0.132 -0.133 -0.136 -0.215 ns
2.599 2.912 3.223 3.071 3.22 2.931 3.238 3.083 3.338 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–94
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–62 specifies EP3SL70 Row Pin delay adders when using the regional clock.
Table 1–62. EP3SL70 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.111
0.099
-0.113
-0.107
0.123
0.105
-0.127
-0.112
0.177 0.192 0.207 0.198 0.263 0.194 0.212 0.201 0.266
0.156 0.175 0.195 0.185 0.263 0.177 0.195 0.188 0.263
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
-0.183 -0.198 -0.213 -0.205 -0.272 -0.202 -0.216 -0.21 -0.273 ns
-0.164 -0.185 -0.202 -0.193 -0.258 -0.184 -0.204 -0.197 -0.257 ns
EP3SL110 I/O Timing Parameters
Table 1–63 through Table 1–67 show the maximum I/O timing parameters for
EP3SL110 devices for single-ended I/O standards.
Table 1–63 specifies EP3SL110 column pins input timing parameters for single-ended
I/O standards.
Table 1–63. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.941
1.061
0.747
-0.499
-0.941
1.061
0.747
-0.499
-0.947
1.067
0.741
-0.493
-0.947
1.067
0.741
-0.493
-0.937
1.057
0.751
-0.503
-1.032
1.163
0.771
-0.504
-1.032
1.163
0.771
-0.504
-1.043
1.174
0.760
-0.493
-1.043
1.174
0.760
-0.493
-1.038
1.169
0.765
-0.498
-1.486 -1.625 -1.875 -1.811 -2.056 -1.553 -1.778 -1.818 -2.171 ns
GCLK
1.672 1.836 2.108 2.030 2.287 1.780 2.031 2.046 2.394
1.257 1.422 1.476 1.387 1.379 1.423 1.491 1.401 1.439
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-0.858 -0.973 -0.975 -0.917 -0.896 -0.965 -0.980 -0.920 -0.953 ns
-1.486 -1.625 -1.875 -1.811 -2.056 -1.553 -1.778 -1.818 -2.171 ns
tsu
th
GCLK
1.672 1.836 2.108 2.030 2.287 1.780 2.031 2.046 2.394
1.257 1.422 1.476 1.387 1.379 1.423 1.491 1.401 1.439
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-0.858 -0.973 -0.975 -0.917 -0.896 -0.965 -0.980 -0.920 -0.953 ns
-1.485 -1.627 -1.874 -1.810 -2.055 -1.553 -1.783 -1.823 -2.176 ns
tsu
th
GCLK
1.671 1.838 2.107 2.029 2.286 1.780 2.036 2.051 2.399
1.258 1.420 1.477 1.388 1.380 1.423 1.486 1.396 1.434
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-0.859 -0.971 -0.976 -0.918 -0.897 -0.965 -0.975 -0.915 -0.948 ns
-1.485 -1.627 -1.874 -1.810 -2.055 -1.553 -1.783 -1.823 -2.176 ns
tsu
th
GCLK
1.671 1.838 2.107 2.029 2.286 1.780 2.036 2.051 2.399
1.258 1.420 1.477 1.388 1.380 1.423 1.486 1.396 1.434
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-0.859 -0.971 -0.976 -0.918 -0.897 -0.965 -0.975 -0.915 -0.948 ns
-1.494 -1.639 -1.893 -1.829 -2.074 -1.563 -1.794 -1.834 -2.187 ns
tsu
th
GCLK
1.680 1.850 2.126 2.048 2.305 1.790 2.047 2.062 2.410
1.249 1.408 1.458 1.369 1.361 1.413 1.475 1.385 1.423
ns
ns
2.5 V
tsu
th
GCLK
PLL
-0.850 -0.959 -0.957 -0.899 -0.878 -0.955 -0.964 -0.904 -0.937 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–95
I4L
Table 1–63. EP3SL110 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
1.1V
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
1.1V
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
0.9V
0.9V
tsu
th
-0.953
1.075
0.733
-0.483
-0.946
1.068
0.740
-0.490
-0.886
1.008
0.800
-0.550
-0.867
0.989
0.819
-0.569
-0.867
0.989
0.819
-0.569
-0.860
0.982
0.826
-0.576
-0.860
0.982
0.826
-0.576
-0.848
0.970
0.838
-0.588
-0.848
0.970
0.838
-0.588
-1.060
1.193
0.743
-0.474
-1.050
1.183
0.753
-0.484
-0.998
1.131
0.805
-0.536
-0.969
1.102
0.834
-0.565
-0.969
1.102
0.834
-0.565
-0.963
1.096
0.840
-0.571
-0.963
1.096
0.840
-0.571
-0.952
1.085
0.851
-0.582
-0.952
1.085
0.851
-0.582
-1.534 -1.675 -1.891 -1.827 -2.072 -1.597 -1.797 -1.837 -2.190 ns
GCLK
1.720 1.886 2.124 2.046 2.303 1.824 2.050 2.065 2.413
1.209 1.372 1.460 1.371 1.363 1.379 1.472 1.382 1.420
ns
ns
1.8 V
tsu
th
GCLK
PLL
-0.810 -0.923 -0.959 -0.901 -0.880 -0.921 -0.961 -0.901 -0.934 ns
-1.511 -1.643 -1.821 -1.757 -2.002 -1.566 -1.731 -1.771 -2.124 ns
tsu
th
GCLK
1.697 1.854 2.054 1.976 2.233 1.793 1.984 1.999 2.347
1.232 1.404 1.530 1.441 1.433 1.410 1.538 1.448 1.486
ns
ns
1.5 V
1.2 V
tsu
th
GCLK
PLL
-0.833 -0.955 -1.029 -0.971 -0.950 -0.952 -1.027 -0.967 -1.000 ns
-1.434 -1.544 -1.665 -1.601 -1.846 -1.470 -1.578 -1.618 -1.971 ns
tsu
th
GCLK
1.620 1.755 1.898 1.820 2.077 1.697 1.831 1.846 2.194
1.309 1.503 1.686 1.597 1.589 1.506 1.691 1.601 1.639
ns
ns
tsu
th
GCLK
PLL
-0.910 -1.054 -1.185 -1.127 -1.106 -1.048 -1.180 -1.120 -1.153 ns
-1.406 -1.528 -1.667 -1.603 -1.848 -1.449 -1.574 -1.614 -1.967 ns
tsu
th
GCLK
1.592 1.739 1.900 1.822 2.079 1.676 1.827 1.842 2.190
1.337 1.519 1.684 1.595 1.587 1.527 1.695 1.605 1.643
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-0.938 -1.070 -1.183 -1.125 -1.104 -1.069 -1.184 -1.124 -1.157 ns
-1.406 -1.528 -1.667 -1.603 -1.848 -1.449 -1.574 -1.614 -1.967 ns
tsu
th
GCLK
1.592 1.739 1.900 1.822 2.079 1.676 1.827 1.842 2.190
1.337 1.519 1.684 1.595 1.587 1.527 1.695 1.605 1.643
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-0.938 -1.070 -1.183 -1.125 -1.104 -1.069 -1.184 -1.124 -1.157 ns
-1.393 -1.520 -1.664 -1.598 -1.849 -1.445 -1.579 -1.613 -1.968 ns
tsu
th
GCLK
1.579 1.728 1.894 1.816 2.075 1.669 1.827 1.840 2.186
1.350 1.527 1.687 1.600 1.589 1.534 1.694 1.606 1.642
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-0.951 -1.081 -1.189 -1.131 -1.111 -1.079 -1.187 -1.126 -1.161 ns
-1.393 -1.520 -1.664 -1.598 -1.849 -1.445 -1.579 -1.613 -1.968 ns
tsu
th
GCLK
1.579 1.728 1.894 1.816 2.075 1.669 1.827 1.840 2.186
1.350 1.527 1.687 1.600 1.589 1.534 1.694 1.606 1.642
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-0.951 -1.081 -1.189 -1.131 -1.111 -1.079 -1.187 -1.126 -1.161 ns
-1.382 -1.509 -1.645 -1.579 -1.830 -1.434 -1.561 -1.595 -1.950 ns
tsu
th
GCLK
1.567 1.717 1.875 1.797 2.056 1.658 1.809 1.822 2.168
1.361 1.538 1.706 1.619 1.608 1.545 1.712 1.624 1.660
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-0.963 -1.092 -1.208 -1.150 -1.130 -1.090 -1.205 -1.144 -1.179 ns
-1.382 -1.509 -1.645 -1.579 -1.830 -1.434 -1.561 -1.595 -1.950 ns
tsu
th
GCLK
1.567 1.717 1.875 1.797 2.056 1.658 1.809 1.822 2.168
1.361 1.538 1.706 1.619 1.608 1.545 1.712 1.624 1.660
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.963 -1.092 -1.208 -1.150 -1.130 -1.090 -1.205 -1.144 -1.179 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–96
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–63. EP3SL110 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.860
0.982
0.826
-0.576
-0.860
0.982
0.826
-0.576
-0.848
0.970
0.838
-0.588
-0.848
0.970
0.838
-0.588
-0.840
0.962
0.846
-0.596
-0.840
0.962
0.846
-0.596
-0.947
1.067
0.741
-0.493
-0.963
1.096
0.840
-0.571
-0.963
1.096
0.840
-0.571
-0.952
1.085
0.851
-0.582
-0.952
1.085
0.851
-0.582
-0.940
1.073
0.863
-0.594
-0.940
1.073
0.863
-0.594
-1.043
1.174
0.760
-0.493
-1.393 -1.520 -1.664 -1.598 -1.849 -1.445 -1.579 -1.613 -1.968 ns
GCLK
1.579 1.728 1.894 1.816 2.075 1.669 1.827 1.840 2.186
1.350 1.527 1.687 1.600 1.589 1.534 1.694 1.606 1.642
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.951 -1.081 -1.189 -1.131 -1.111 -1.079 -1.187 -1.126 -1.161 ns
-1.393 -1.520 -1.664 -1.598 -1.849 -1.445 -1.579 -1.613 -1.968 ns
tsu
th
GCLK
1.579 1.728 1.894 1.816 2.075 1.669 1.827 1.840 2.186
1.350 1.527 1.687 1.600 1.589 1.534 1.694 1.606 1.642
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.951 -1.081 -1.189 -1.131 -1.111 -1.079 -1.187 -1.126 -1.161 ns
-1.382 -1.509 -1.645 -1.579 -1.830 -1.434 -1.561 -1.595 -1.950 ns
tsu
th
GCLK
1.567 1.717 1.875 1.797 2.056 1.658 1.809 1.822 2.168
1.361 1.538 1.706 1.619 1.608 1.545 1.712 1.624 1.660
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.963 -1.092 -1.208 -1.150 -1.130 -1.090 -1.205 -1.144 -1.179 ns
-1.382 -1.509 -1.645 -1.579 -1.830 -1.434 -1.561 -1.595 -1.950 ns
tsu
th
GCLK
1.567 1.717 1.875 1.797 2.056 1.658 1.809 1.822 2.168
1.361 1.538 1.706 1.619 1.608 1.545 1.712 1.624 1.660
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.963 -1.092 -1.208 -1.150 -1.130 -1.090 -1.205 -1.144 -1.179 ns
-1.372 -1.498 -1.629 -1.563 -1.814 -1.423 -1.546 -1.580 -1.935 ns
tsu
th
GCLK
1.557 1.706 1.859 1.781 2.040 1.647 1.794 1.807 2.153
1.371 1.549 1.722 1.635 1.624 1.556 1.727 1.639 1.675
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.973 -1.103 -1.224 -1.166 -1.146 -1.101 -1.220 -1.159 -1.194 ns
-1.372 -1.498 -1.629 -1.563 -1.814 -1.423 -1.546 -1.580 -1.935 ns
tsu
th
GCLK
1.557 1.706 1.859 1.781 2.040 1.647 1.794 1.807 2.153
1.371 1.549 1.722 1.635 1.624 1.556 1.727 1.639 1.675
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-0.973 -1.103 -1.224 -1.166 -1.146 -1.101 -1.220 -1.159 -1.194 ns
-1.485 -1.627 -1.874 -1.810 -2.055 -1.553 -1.783 -1.823 -2.176 ns
tsu
th
GCLK
1.671 1.838 2.107 2.029 2.286 1.780 2.036 2.051 2.399
1.258 1.420 1.477 1.388 1.380 1.423 1.486 1.396 1.434
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-0.859 -0.971 -0.976 -0.918 -0.897 -0.965 -0.975 -0.915 -0.948 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–97
I/O Timing
Table 1–64 specifies EP3SL110 row pins input timing parameters for single-ended
I/O standards.
Table 1–64. EP3SL110 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.910
1.025
0.992
-0.741
-0.910
1.025
0.992
-0.741
-0.916
1.031
0.986
-0.735
-0.916
1.031
0.986
-0.735
-0.904
1.019
0.998
-0.747
-0.873
0.990
0.968
-0.716
-0.863
0.980
0.978
-0.726
-0.803
0.920
1.038
-0.786
-0.883
1.015
1.013
-0.746
-0.883
1.015
1.013
-0.746
-0.894
1.026
1.002
-0.735
-0.894
1.026
1.002
-0.735
-0.887
1.019
1.009
-0.742
-0.918
1.051
0.977
-0.709
-0.907
1.040
0.988
-0.720
-0.854
0.987
1.041
-0.773
-1.252 -1.441 -1.559 -1.604 -1.843 -1.465 -1.551 -1.605 -1.881
1.440 1.648 1.792 1.822 2.066 1.682 1.794 1.831 2.104
1.646 1.862 1.976 1.860 1.804 1.870 1.998 1.880 1.856
-1.246 -1.412 -1.475 -1.388 -1.322 -1.411 -1.486 -1.398 -1.371
-1.252 -1.441 -1.559 -1.604 -1.843 -1.465 -1.551 -1.605 -1.881
1.440 1.648 1.792 1.822 2.066 1.682 1.794 1.831 2.104
1.646 1.862 1.976 1.860 1.804 1.870 1.998 1.880 1.856
-1.246 -1.412 -1.475 -1.388 -1.322 -1.411 -1.486 -1.398 -1.371
-1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886
1.437 1.649 1.795 1.825 2.069 1.681 1.799 1.836 2.109
1.649 1.861 1.973 1.857 1.801 1.871 1.993 1.875 1.851
-1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366
-1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886
1.437 1.649 1.795 1.825 2.069 1.681 1.799 1.836 2.109
1.649 1.861 1.973 1.857 1.801 1.871 1.993 1.875 1.851
-1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366
-1.258 -1.455 -1.577 -1.622 -1.861 -1.473 -1.566 -1.620 -1.896
1.446 1.662 1.810 1.840 2.084 1.690 1.809 1.846 2.119
1.640 1.848 1.958 1.842 1.786 1.862 1.983 1.865 1.841
-1.240 -1.398 -1.457 -1.370 -1.304 -1.403 -1.471 -1.383 -1.356
-1.298 -1.402 -1.575 -1.530 -1.859 -1.402 -1.567 -1.526 -1.897
1.486 1.612 1.808 1.751 2.082 1.622 1.810 1.756 2.120
1.600 1.815 1.960 1.844 1.788 1.829 1.982 1.864 1.840
-1.200 -1.365 -1.459 -1.372 -1.306 -1.370 -1.470 -1.382 -1.355
-1.274 -1.370 -1.507 -1.462 -1.791 -1.371 -1.502 -1.461 -1.832
1.462 1.580 1.740 1.683 2.014 1.591 1.745 1.691 2.055
1.624 1.847 2.028 1.912 1.856 1.860 2.047 1.929 1.905
-1.224 -1.397 -1.527 -1.440 -1.374 -1.401 -1.535 -1.447 -1.420
-1.195 -1.269 -1.348 -1.303 -1.632 -1.275 -1.347 -1.306 -1.677
1.383 1.479 1.581 1.524 1.855 1.495 1.590 1.536 1.900
1.703 1.948 2.187 2.071 2.015 1.956 2.202 2.084 2.060
-1.303 -1.498 -1.686 -1.599 -1.533 -1.497 -1.690 -1.602 -1.575
GCLK
3.3-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–98
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–64. EP3SL110 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.847
0.963
1.055
-0.803
-0.847
0.963
1.055
-0.803
-0.777
0.894
1.064
-0.812
-0.777
0.894
1.064
-0.812
-0.763
0.880
1.078
-0.826
-0.777
0.894
1.064
-0.812
-0.777
0.894
1.064
-0.812
-0.763
0.880
1.078
-0.826
-0.763
0.880
1.078
-0.826
-0.828
0.961
1.067
-0.799
-0.828
0.961
1.067
-0.799
-0.819
0.952
1.076
-0.808
-0.819
0.952
1.076
-0.808
-0.807
0.940
1.088
-0.820
-0.819
0.952
1.076
-0.808
-0.819
0.952
1.076
-0.808
-0.807
0.940
1.088
-0.820
-0.807
0.940
1.088
-0.820
-1.172 -1.346 -1.357 -1.402 -1.641 -1.361 -1.349 -1.403 -1.679
1.360 1.553 1.590 1.620 1.864 1.578 1.592 1.629 1.902
1.726 1.957 2.178 2.062 2.006 1.974 2.200 2.082 2.058
-1.326 -1.507 -1.677 -1.590 -1.524 -1.515 -1.688 -1.600 -1.573
-1.172 -1.346 -1.357 -1.402 -1.641 -1.361 -1.349 -1.403 -1.679
1.360 1.553 1.590 1.620 1.864 1.578 1.592 1.629 1.902
1.726 1.957 2.178 2.062 2.006 1.974 2.200 2.082 2.058
-1.326 -1.507 -1.677 -1.590 -1.524 -1.515 -1.688 -1.600 -1.573
-1.157 -1.244 -1.346 -1.300 -1.630 -1.246 -1.343 -1.300 -1.672
1.345 1.452 1.576 1.519 1.849 1.463 1.583 1.529 1.891
1.741 1.975 2.192 2.077 2.019 1.988 2.209 2.092 2.067
-1.341 -1.527 -1.693 -1.606 -1.541 -1.531 -1.700 -1.611 -1.586
-1.157 -1.244 -1.346 -1.300 -1.630 -1.246 -1.343 -1.300 -1.672
1.345 1.452 1.576 1.519 1.849 1.463 1.583 1.529 1.891
1.741 1.975 2.192 2.077 2.019 1.988 2.209 2.092 2.067
-1.341 -1.527 -1.693 -1.606 -1.541 -1.531 -1.700 -1.611 -1.586
-1.144 -1.234 -1.328 -1.282 -1.612 -1.235 -1.326 -1.283 -1.655
1.333 1.442 1.558 1.501 1.831 1.452 1.566 1.512 1.874
1.756 1.985 2.210 2.095 2.037 1.999 2.226 2.109 2.084
-1.355 -1.537 -1.711 -1.624 -1.559 -1.542 -1.717 -1.628 -1.603
-1.157 -1.244 -1.346 -1.300 -1.630 -1.246 -1.343 -1.300 -1.672
1.345 1.452 1.576 1.519 1.849 1.463 1.583 1.529 1.891
1.741 1.975 2.192 2.077 2.019 1.988 2.209 2.092 2.067
-1.341 -1.527 -1.693 -1.606 -1.541 -1.531 -1.700 -1.611 -1.586
-1.157 -1.244 -1.346 -1.300 -1.630 -1.246 -1.343 -1.300 -1.672
1.345 1.452 1.576 1.519 1.849 1.463 1.583 1.529 1.891
1.741 1.975 2.192 2.077 2.019 1.988 2.209 2.092 2.067
-1.341 -1.527 -1.693 -1.606 -1.541 -1.531 -1.700 -1.611 -1.586
-1.144 -1.234 -1.328 -1.282 -1.612 -1.235 -1.326 -1.283 -1.655
1.333 1.442 1.558 1.501 1.831 1.452 1.566 1.512 1.874
1.756 1.985 2.210 2.095 2.037 1.999 2.226 2.109 2.084
-1.355 -1.537 -1.711 -1.624 -1.559 -1.542 -1.717 -1.628 -1.603
-1.144 -1.234 -1.328 -1.282 -1.612 -1.235 -1.326 -1.283 -1.655
1.333 1.442 1.558 1.501 1.831 1.452 1.566 1.512 1.874
1.756 1.985 2.210 2.095 2.037 1.999 2.226 2.109 2.084
-1.355 -1.537 -1.711 -1.624 -1.559 -1.542 -1.717 -1.628 -1.603
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-15
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–99
I/O Timing
Table 1–64. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.754
0.871
1.087
-0.835
-0.754
0.871
1.087
-0.835
-0.916
1.031
0.986
-0.735
-0.916
1.031
0.986
-0.735
-0.795
0.928
1.100
-0.832
-0.795
0.928
1.100
-0.832
-0.894
1.026
1.002
-0.735
-0.894
1.026
1.002
-0.735
-1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639
1.324 1.432 1.542 1.485 1.815 1.443 1.550 1.496 1.858
1.765 1.995 2.226 2.111 2.053 2.008 2.242 2.125 2.100
-1.364 -1.547 -1.727 -1.640 -1.575 -1.551 -1.733 -1.644 -1.619
-1.135 -1.224 -1.312 -1.266 -1.596 -1.226 -1.310 -1.267 -1.639
1.324 1.432 1.542 1.485 1.815 1.443 1.550 1.496 1.858
1.765 1.995 2.226 2.111 2.053 2.008 2.242 2.125 2.100
-1.364 -1.547 -1.727 -1.640 -1.575 -1.551 -1.733 -1.644 -1.619
-1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886
1.437 1.649 1.795 1.825 2.069 1.681 1.799 1.836 2.109
1.649 1.861 1.973 1.857 1.801 1.871 1.993 1.875 1.851
-1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366
-1.249 -1.442 -1.562 -1.607 -1.846 -1.464 -1.556 -1.610 -1.886
1.437 1.649 1.795 1.825 2.069 1.681 1.799 1.836 2.109
1.649 1.861 1.973 1.857 1.801 1.871 1.993 1.875 1.851
-1.249 -1.411 -1.472 -1.385 -1.319 -1.412 -1.481 -1.393 -1.366
GCLK
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
PCI-X
tsu
th
GCLK
PLL
Table 1–65 specifies EP3SL110 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–65. EP3SL110 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.198
1.575
3.119
1.496
3.089
1.467
3.075
1.453
3.443
1.757
3.354
1.668
3.322
1.636
3.308
1.622
4.777 5.173 5.678 5.539 5.818 5.301 5.805 5.669 5.893
2.219 2.336 2.565 2.563 2.529 2.444 2.674 2.673 2.515
4.673 5.061 5.561 5.422 5.701 5.185 5.685 5.549 5.773
2.116 2.224 2.448 2.446 2.412 2.328 2.554 2.553 2.395
4.606 4.991 5.491 5.352 5.631 5.115 5.618 5.482 5.706
2.049 2.154 2.378 2.376 2.342 2.258 2.487 2.486 2.328
4.585 4.968 5.463 5.324 5.603 5.089 5.584 5.448 5.672
2.028 2.131 2.350 2.348 2.314 2.232 2.454 2.453 2.295
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVTTL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–100
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–65. EP3SL110 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.135
1.513
3.064
1.442
3.040
1.417
3.033
1.410
3.195
1.573
3.128
1.506
3.090
1.468
3.068
1.446
3.150
1.527
3.077
1.455
3.053
1.431
3.053
1.431
3.376
1.690
3.299
1.613
3.271
1.585
3.264
1.578
3.452
1.766
3.367
1.681
3.330
1.644
3.303
1.617
3.392
1.706
3.313
1.627
3.284
1.598
3.284
1.598
4.704 5.090 5.590 5.451 5.730 5.215 5.717 5.581 5.805
2.146 2.253 2.477 2.475 2.441 2.358 2.586 2.585 2.427
4.582 4.964 5.459 5.320 5.599 5.085 5.580 5.444 5.668
2.024 2.127 2.346 2.344 2.310 2.228 2.449 2.448 2.290
4.553 4.937 5.434 5.295 5.574 5.058 5.555 5.419 5.643
1.995 2.100 2.321 2.319 2.285 2.201 2.424 2.423 2.265
4.545 4.928 5.425 5.286 5.565 5.048 5.545 5.409 5.633
1.987 2.091 2.312 2.310 2.276 2.192 2.415 2.414 2.256
4.811 5.209 5.717 5.578 5.857 5.339 5.847 5.711 5.935
2.253 2.372 2.604 2.602 2.568 2.483 2.716 2.715 2.557
4.707 5.097 5.601 5.462 5.741 5.225 5.728 5.592 5.816
2.149 2.261 2.488 2.486 2.452 2.368 2.598 2.597 2.439
4.639 5.026 5.527 5.388 5.667 5.151 5.652 5.516 5.740
2.081 2.189 2.414 2.412 2.378 2.294 2.522 2.521 2.363
4.604 4.987 5.485 5.346 5.625 5.111 5.609 5.473 5.697
2.046 2.150 2.372 2.370 2.336 2.254 2.478 2.477 2.319
4.741 5.131 5.636 5.497 5.776 5.259 5.765 5.629 5.853
2.183 2.294 2.523 2.521 2.487 2.402 2.634 2.633 2.475
4.617 5.002 5.501 5.362 5.641 5.126 5.625 5.489 5.713
2.060 2.165 2.388 2.386 2.352 2.269 2.495 2.494 2.336
4.578 4.962 5.460 5.321 5.600 5.086 5.584 5.448 5.672
2.020 2.126 2.347 2.345 2.311 2.229 2.453 2.452 2.294
4.570 4.953 5.450 5.311 5.590 5.075 5.572 5.436 5.660
2.012 2.116 2.337 2.335 2.301 2.218 2.441 2.440 2.282
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVTTL
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVCMOS
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–101
I/O Timing
Table 1–65. EP3SL110 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.254
1.631
3.171
1.548
3.115
1.493
3.082
1.459
3.368
1.745
3.270
1.647
3.188
1.565
3.162
1.540
3.091
1.469
3.086
1.464
3.507
1.821
3.414
1.728
3.370
1.684
3.324
1.638
3.635
1.949
3.524
1.838
3.437
1.751
3.404
1.718
3.340
1.654
3.330
1.644
4.948 5.358 5.883 5.744 6.023 5.492 6.020 5.884 6.108
2.390 2.521 2.770 2.768 2.734 2.635 2.889 2.888 2.730
4.829 5.232 5.751 5.612 5.891 5.364 5.884 5.748 5.972
2.271 2.395 2.638 2.636 2.602 2.507 2.753 2.752 2.594
4.737 5.136 5.651 5.512 5.791 5.266 5.782 5.646 5.870
2.179 2.299 2.538 2.536 2.502 2.409 2.651 2.650 2.492
4.703 5.099 5.610 5.471 5.750 5.226 5.738 5.602 5.826
2.145 2.262 2.497 2.495 2.461 2.370 2.607 2.606 2.448
5.142 5.567 6.101 5.962 6.241 5.710 6.246 6.110 6.334
2.585 2.730 2.988 2.986 2.952 2.853 3.115 3.114 2.956
4.990 5.409 5.940 5.801 6.080 5.551 6.080 5.944 6.168
2.433 2.572 2.827 2.825 2.791 2.694 2.949 2.948 2.790
4.863 5.271 5.796 5.657 5.936 5.407 5.932 5.796 6.020
2.306 2.434 2.683 2.681 2.647 2.550 2.802 2.801 2.643
4.803 5.205 5.721 5.582 5.861 5.336 5.852 5.716 5.940
2.245 2.368 2.608 2.606 2.572 2.479 2.721 2.720 2.562
4.715 5.111 5.622 5.483 5.762 5.239 5.751 5.615 5.839
2.157 2.274 2.509 2.507 2.473 2.382 2.620 2.619 2.461
4.709 5.105 5.615 5.476 5.755 5.232 5.744 5.608 5.832
2.151 2.268 2.502 2.500 2.466 2.375 2.613 2.612 2.454
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
2.5 V
GCLK tco
12mA
16mA
2mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
1.8 V
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–102
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–65. EP3SL110 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.308
1.686
3.177
1.554
3.132
1.510
3.121
1.498
3.086
1.463
3.082
1.459
3.288
1.665
3.165
1.543
3.112
1.490
3.092
1.469
3.105
1.483
3.108
1.486
3.090
1.467
3.602
1.916
3.421
1.735
3.384
1.698
3.378
1.692
3.327
1.641
3.320
1.634
3.545
1.859
3.410
1.724
3.369
1.683
3.335
1.649
3.343
1.657
3.346
1.660
3.326
1.640
5.081 5.494 6.029 5.890 6.169 5.640 6.179 6.043 6.267
2.523 2.657 2.916 2.914 2.880 2.783 3.048 3.047 2.889
4.837 5.240 5.758 5.619 5.898 5.372 5.892 5.756 5.980
2.280 2.403 2.645 2.643 2.609 2.515 2.762 2.761 2.603
4.757 5.160 5.678 5.539 5.818 5.292 5.809 5.673 5.897
2.199 2.323 2.565 2.563 2.529 2.435 2.679 2.678 2.520
4.751 5.152 5.669 5.530 5.809 5.285 5.802 5.666 5.890
2.193 2.316 2.556 2.554 2.520 2.428 2.671 2.670 2.512
4.703 5.099 5.608 5.469 5.748 5.226 5.737 5.601 5.825
2.145 2.262 2.495 2.493 2.459 2.369 2.606 2.605 2.447
4.682 5.078 5.588 5.449 5.728 5.205 5.715 5.579 5.803
2.125 2.241 2.475 2.473 2.439 2.348 2.585 2.584 2.426
5.035 5.448 5.972 5.833 6.112 5.587 6.113 5.977 6.201
2.477 2.611 2.859 2.857 2.823 2.730 2.982 2.981 2.823
4.816 5.217 5.732 5.593 5.872 5.348 5.864 5.728 5.952
2.258 2.380 2.619 2.617 2.583 2.491 2.734 2.733 2.575
4.740 5.140 5.658 5.519 5.798 5.273 5.792 5.656 5.880
2.182 2.303 2.545 2.543 2.509 2.416 2.661 2.660 2.502
4.701 5.097 5.608 5.469 5.748 5.224 5.735 5.599 5.823
2.143 2.260 2.495 2.493 2.459 2.367 2.604 2.603 2.445
4.709 5.105 5.616 5.477 5.756 5.229 5.740 5.604 5.828
2.151 2.268 2.503 2.501 2.467 2.373 2.609 2.608 2.450
4.713 5.109 5.620 5.481 5.760 5.233 5.744 5.608 5.832
2.155 2.272 2.507 2.505 2.471 2.376 2.613 2.612 2.454
4.691 5.087 5.598 5.459 5.738 5.212 5.722 5.586 5.810
2.134 2.250 2.485 2.483 2.449 2.355 2.591 2.590 2.432
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.2 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–103
I/O Timing
Table 1–65. EP3SL110 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.085
1.462
3.123
1.501
3.104
1.482
3.105
1.483
3.088
1.466
3.085
1.462
3.085
1.463
3.084
1.462
3.115
1.492
3.100
1.477
3.087
1.464
3.087
1.465
3.083
1.460
3.319
1.633
3.363
1.677
3.342
1.656
3.345
1.659
3.325
1.639
3.321
1.635
3.320
1.634
3.320
1.634
3.354
1.668
3.338
1.652
3.323
1.637
3.324
1.638
3.319
1.633
4.676 5.071 5.581 5.442 5.721 5.195 5.704 5.568 5.792
2.119 2.234 2.468 2.466 2.432 2.338 2.574 2.573 2.415
4.732 5.128 5.639 5.500 5.779 5.253 5.764 5.628 5.852
2.174 2.291 2.526 2.524 2.490 2.396 2.633 2.632 2.474
4.710 5.106 5.617 5.478 5.757 5.231 5.741 5.605 5.829
2.152 2.269 2.504 2.502 2.468 2.374 2.610 2.609 2.451
4.718 5.115 5.627 5.488 5.767 5.241 5.752 5.616 5.840
2.160 2.278 2.514 2.512 2.478 2.384 2.621 2.620 2.462
4.693 5.090 5.602 5.463 5.742 5.215 5.726 5.590 5.814
2.136 2.253 2.489 2.487 2.453 2.358 2.596 2.595 2.437
4.689 5.086 5.597 5.458 5.737 5.211 5.722 5.586 5.810
2.132 2.249 2.484 2.482 2.448 2.354 2.592 2.591 2.433
4.677 5.071 5.581 5.442 5.721 5.196 5.705 5.569 5.793
2.119 2.235 2.468 2.466 2.432 2.339 2.574 2.573 2.415
4.685 5.081 5.593 5.454 5.733 5.206 5.718 5.582 5.806
2.127 2.245 2.480 2.478 2.444 2.349 2.587 2.586 2.428
4.725 5.121 5.631 5.492 5.771 5.246 5.756 5.620 5.844
2.167 2.284 2.518 2.516 2.482 2.389 2.625 2.624 2.466
4.711 5.108 5.619 5.480 5.759 5.233 5.745 5.609 5.833
2.153 2.271 2.506 2.504 2.470 2.376 2.614 2.613 2.455
4.691 5.087 5.599 5.460 5.739 5.213 5.724 5.588 5.812
2.133 2.250 2.486 2.484 2.450 2.356 2.593 2.592 2.434
4.692 5.089 5.602 5.463 5.742 5.215 5.727 5.591 5.815
2.134 2.252 2.489 2.487 2.453 2.358 2.596 2.595 2.437
4.685 5.082 5.594 5.455 5.734 5.207 5.719 5.583 5.807
2.127 2.245 2.481 2.479 2.445 2.350 2.588 2.587 2.429
SSTL-2
CLASS II
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
SSTL-18
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-15
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–104
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–65. EP3SL110 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.101
1.478
3.100
1.477
3.087
1.464
3.082
1.460
3.084
1.462
3.083
1.461
3.102
1.479
3.097
1.474
3.096
1.474
3.087
1.464
3.088
1.466
3.110
1.488
3.100
1.477
3.336
1.650
3.336
1.650
3.322
1.636
3.317
1.631
3.320
1.634
3.318
1.632
3.337
1.651
3.333
1.647
3.332
1.646
3.322
1.636
3.324
1.638
3.349
1.663
3.337
1.651
4.693 5.087 5.596 5.457 5.736 5.211 5.720 5.584 5.808
2.135 2.250 2.483 2.481 2.447 2.354 2.589 2.588 2.430
4.697 5.092 5.602 5.463 5.742 5.216 5.726 5.590 5.814
2.139 2.255 2.489 2.487 2.453 2.359 2.595 2.594 2.436
4.681 5.076 5.586 5.447 5.726 5.200 5.710 5.574 5.798
2.123 2.239 2.473 2.471 2.437 2.343 2.579 2.578 2.420
4.675 5.070 5.580 5.441 5.720 5.194 5.704 5.568 5.792
2.117 2.233 2.467 2.465 2.431 2.337 2.573 2.572 2.414
4.680 5.075 5.586 5.447 5.726 5.200 5.710 5.574 5.798
2.122 2.238 2.473 2.471 2.437 2.343 2.580 2.579 2.421
4.673 5.068 5.578 5.439 5.718 5.192 5.701 5.565 5.789
2.115 2.231 2.465 2.463 2.429 2.335 2.571 2.570 2.412
4.695 5.089 5.599 5.460 5.739 5.214 5.722 5.586 5.810
2.137 2.252 2.486 2.484 2.450 2.357 2.592 2.591 2.433
4.693 5.088 5.598 5.459 5.738 5.213 5.722 5.586 5.810
2.135 2.251 2.485 2.483 2.449 2.356 2.591 2.590 2.432
4.694 5.089 5.599 5.460 5.739 5.214 5.723 5.587 5.811
2.136 2.252 2.486 2.484 2.450 2.357 2.592 2.591 2.433
4.681 5.077 5.587 5.448 5.727 5.201 5.711 5.575 5.799
2.124 2.240 2.474 2.472 2.438 2.344 2.580 2.579 2.421
4.687 5.083 5.595 5.456 5.735 5.208 5.719 5.583 5.807
2.129 2.247 2.482 2.480 2.446 2.351 2.589 2.588 2.430
4.715 5.110 5.621 5.482 5.761 5.236 5.746 5.610 5.834
2.157 2.274 2.508 2.506 2.472 2.379 2.616 2.615 2.457
4.703 5.099 5.610 5.471 5.750 5.224 5.735 5.599 5.823
2.145 2.262 2.497 2.495 2.461 2.367 2.604 2.603 2.445
8mA
GCLK
tco
PLL
SSTL-15
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–105
I/O Timing
Table 1–65. EP3SL110 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.098
1.476
3.096
1.473
3.092
1.469
3.169
1.546
3.169
1.546
3.198
1.575
3.119
1.496
3.089
1.467
3.075
1.453
3.335
1.649
3.333
1.647
3.329
1.643
3.404
1.718
3.404
1.718
3.443
1.757
3.354
1.668
3.322
1.636
3.308
1.622
4.701 5.097 5.608 5.469 5.748 5.223 5.734 5.598 5.822
2.143 2.260 2.495 2.493 2.459 2.366 2.603 2.602 2.444
4.700 5.097 5.608 5.469 5.748 5.222 5.734 5.598 5.822
2.142 2.260 2.495 2.493 2.459 2.365 2.603 2.602 2.444
4.693 5.090 5.601 5.462 5.741 5.215 5.726 5.590 5.814
2.136 2.253 2.488 2.486 2.452 2.358 2.596 2.595 2.437
4.711 5.098 5.598 5.459 5.738 5.223 5.724 5.588 5.812
2.153 2.261 2.485 2.483 2.449 2.366 2.593 2.592 2.434
4.711 5.098 5.598 5.459 5.738 5.223 5.724 5.588 5.812
2.153 2.261 2.485 2.483 2.449 2.366 2.593 2.592 2.434
4.777 5.173 5.678 5.539 5.818 5.301 5.805 5.669 5.893
2.219 2.336 2.565 2.563 2.529 2.444 2.674 2.673 2.515
4.673 5.061 5.561 5.422 5.701 5.185 5.685 5.549 5.773
2.116 2.224 2.448 2.446 2.412 2.328 2.554 2.553 2.395
4.606 4.991 5.491 5.352 5.631 5.115 5.618 5.482 5.706
2.049 2.154 2.378 2.376 2.342 2.258 2.487 2.486 2.328
4.585 4.968 5.463 5.324 5.603 5.089 5.584 5.448 5.672
2.028 2.131 2.350 2.348 2.314 2.232 2.454 2.453 2.295
1.5-V
HSTL
CLASS II
16mA
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–106
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–66 specifies EP3SL110 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–66. EP3SL110 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.481
1.650
3.376
1.545
3.270
1.439
3.485
1.654
3.276
1.445
3.427
1.596
3.300
1.469
3.249
1.418
3.346
1.515
3.227
1.396
3.463
1.632
3.365
1.534
3.288
1.457
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.182
1.457
3.116
1.364
3.037
1.265
3.184
1.467
3.041
1.269
3.143
1.411
3.042
1.286
3.005
1.247
3.064
1.325
2.992
1.225
3.169
1.437
3.084
1.327
3.027
1.281
4.833 5.216 5.678 5.579 5.814 5.256 5.802 5.703 5.896
2.051 2.136 2.329 2.349 2.337 2.239 2.435 2.454 2.331
4.703 5.078 5.533 5.434 5.669 5.143 5.653 5.554 5.747
1.921 1.998 2.184 2.204 2.192 2.098 2.286 2.305 2.182
4.584 4.955 5.405 5.306 5.541 5.044 5.521 5.422 5.615
1.802 1.875 2.056 2.076 2.064 1.971 2.154 2.173 2.050
4.841 5.221 5.682 5.583 5.818 5.264 5.806 5.707 5.900
2.059 2.141 2.333 2.353 2.341 2.245 2.439 2.458 2.335
4.590 4.961 5.411 5.312 5.548 5.056 5.528 5.429 5.622
1.808 1.881 2.062 2.082 2.070 1.977 2.161 2.180 2.057
4.785 5.169 5.634 5.535 5.770 5.224 5.760 5.661 5.854
2.003 2.089 2.285 2.305 2.293 2.196 2.393 2.412 2.289
4.632 5.010 5.470 5.371 5.606 5.082 5.596 5.496 5.689
1.850 1.930 2.121 2.141 2.129 2.034 2.229 2.247 2.124
4.550 4.927 5.382 5.283 5.518 5.014 5.503 5.403 5.596
1.768 1.847 2.033 2.053 2.041 1.948 2.136 2.154 2.031
4.679 5.062 5.524 5.425 5.660 5.115 5.649 5.549 5.742
1.897 1.982 2.175 2.195 2.183 2.088 2.282 2.300 2.177
4.515 4.888 5.343 5.244 5.479 4.984 5.463 5.363 5.556
1.733 1.808 1.994 2.014 2.002 1.908 2.096 2.114 1.991
4.917 5.323 5.806 5.707 5.942 5.356 5.939 5.839 6.032
2.135 2.243 2.457 2.477 2.465 2.356 2.572 2.590 2.467
4.762 5.160 5.636 5.537 5.772 5.219 5.765 5.665 5.858
1.980 2.080 2.287 2.307 2.295 2.189 2.398 2.416 2.293
4.651 5.041 5.510 5.411 5.646 5.130 5.635 5.535 5.728
1.869 1.961 2.161 2.181 2.169 2.066 2.268 2.286 2.163
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
GCLK
PLL
3.3-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–107
I/O Timing
Table 1–66. EP3SL110 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.706
1.879
3.504
1.677
3.402
1.575
3.328
1.501
3.624
1.797
3.366
1.539
3.319
1.492
3.310
1.483
3.549
1.722
3.360
1.533
3.274
1.443
3.262
1.431
3.244
1.413
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.438
1.670
3.213
1.445
3.148
1.380
3.088
1.320
3.349
1.581
3.107
1.339
3.080
1.312
3.071
1.303
3.292
1.524
3.112
1.344
3.031
1.266
3.026
1.254
3.017
1.238
5.298 5.747 6.303 6.177 6.439 5.888 6.445 6.318 6.538
2.521 2.672 2.932 2.952 2.937 2.793 3.056 3.075 2.949
4.971 5.378 5.898 5.772 6.034 5.523 6.039 5.911 6.131
2.194 2.303 2.527 2.547 2.532 2.428 2.650 2.668 2.542
4.818 5.228 5.739 5.613 5.875 5.355 5.866 5.739 5.959
2.041 2.153 2.368 2.388 2.373 2.260 2.477 2.496 2.370
4.741 5.134 5.642 5.516 5.778 5.260 5.772 5.645 5.865
1.964 2.059 2.271 2.291 2.276 2.165 2.383 2.402 2.276
5.208 5.660 6.231 6.105 6.367 5.795 6.369 6.242 6.462
2.431 2.585 2.860 2.880 2.865 2.700 2.980 2.999 2.873
4.803 5.223 5.740 5.614 5.876 5.349 5.865 5.738 5.958
2.026 2.148 2.369 2.389 2.374 2.254 2.476 2.495 2.369
4.730 5.127 5.634 5.508 5.770 5.251 5.760 5.633 5.853
1.953 2.052 2.263 2.283 2.268 2.156 2.371 2.390 2.264
4.708 5.109 5.615 5.489 5.751 5.233 5.738 5.611 5.831
1.931 2.034 2.244 2.264 2.249 2.138 2.349 2.368 2.242
5.118 5.574 6.156 6.030 6.292 5.707 6.285 6.158 6.378
2.341 2.499 2.785 2.805 2.790 2.612 2.896 2.915 2.789
4.825 5.251 5.781 5.655 5.917 5.374 5.907 5.780 6.000
2.048 2.176 2.410 2.430 2.415 2.279 2.518 2.537 2.411
4.629 5.013 5.478 5.379 5.616 5.117 5.597 5.498 5.692
1.847 1.933 2.129 2.149 2.137 2.033 2.230 2.249 2.126
4.621 5.005 5.476 5.371 5.614 5.116 5.596 5.491 5.691
1.839 1.925 2.121 2.141 2.129 2.025 2.223 2.242 2.119
4.596 4.980 5.459 5.344 5.597 5.099 5.578 5.464 5.673
1.814 1.900 2.094 2.114 2.102 1.999 2.196 2.215 2.092
2mA
4mA
6mA
8mA
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
1.8 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-2
CLASS I
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–108
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–66. EP3SL110 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.284
1.457
3.270
1.443
3.258
1.431
3.235
1.408
3.234
1.407
3.243
1.416
3.238
1.411
3.280
1.453
3.258
1.431
3.241
1.414
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.049
1.281
3.034
1.266
3.023
1.255
2.999
1.231
2.999
1.231
3.009
1.241
3.004
1.235
3.045
1.277
3.022
1.254
3.005
1.237
4.636 5.022 5.516 5.390 5.652 5.141 5.635 5.508 5.728
1.859 1.947 2.145 2.165 2.150 2.046 2.246 2.265 2.139
4.633 5.020 5.514 5.388 5.650 5.139 5.633 5.506 5.726
1.856 1.945 2.143 2.163 2.148 2.044 2.244 2.263 2.137
4.616 5.003 5.497 5.371 5.633 5.122 5.617 5.490 5.710
1.839 1.928 2.126 2.146 2.131 2.027 2.228 2.247 2.121
4.600 4.987 5.482 5.356 5.618 5.107 5.602 5.475 5.695
1.823 1.912 2.111 2.131 2.116 2.012 2.213 2.232 2.106
4.599 4.986 5.481 5.355 5.617 5.106 5.601 5.474 5.694
1.822 1.911 2.110 2.130 2.116 2.011 2.212 2.231 2.106
4.597 4.982 5.475 5.349 5.611 5.101 5.594 5.467 5.687
1.820 1.907 2.104 2.124 2.111 2.006 2.205 2.224 2.100
4.596 4.983 5.477 5.351 5.613 5.103 5.598 5.471 5.691
1.819 1.908 2.106 2.126 2.121 2.008 2.209 2.228 2.111
4.647 5.036 5.533 5.407 5.669 5.154 5.651 5.524 5.744
1.870 1.961 2.162 2.182 2.167 2.059 2.262 2.281 2.155
4.629 5.019 5.516 5.390 5.652 5.138 5.635 5.508 5.728
1.852 1.944 2.145 2.165 2.150 2.043 2.246 2.265 2.139
4.612 5.001 5.498 5.372 5.634 5.120 5.618 5.491 5.711
1.835 1.926 2.127 2.147 2.132 2.025 2.229 2.248 2.122
4mA
6mA
8mA
10mA
12mA
8mA
16mA
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-18
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–109
I/O Timing
Table 1–66. EP3SL110 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.256
1.429
3.244
1.417
3.232
1.405
3.234
1.407
3.229
1.402
3.234
1.406
3.263
1.436
3.253
1.426
3.248
1.421
3.262
1.435
3.250
1.423
3.248
1.421
3.357
1.526
3.357
1.526
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.024
1.256
3.012
1.244
2.999
1.231
3.001
1.233
2.994
1.226
3.001
1.232
3.031
1.263
3.019
1.251
3.015
1.247
3.030
1.262
3.018
1.250
3.014
1.246
3.137
1.351
3.137
1.351
4.603 4.987 5.478 5.352 5.614 5.105 5.597 5.470 5.690
1.826 1.912 2.107 2.127 2.112 2.010 2.208 2.227 2.101
4.594 4.979 5.470 5.344 5.606 5.097 5.590 5.463 5.683
1.817 1.904 2.099 2.119 2.108 2.002 2.201 2.220 2.097
4.585 4.970 5.462 5.336 5.598 5.089 5.582 5.455 5.675
1.808 1.895 2.091 2.111 2.101 1.994 2.193 2.212 2.090
4.588 4.973 5.465 5.339 5.601 5.092 5.585 5.458 5.678
1.811 1.898 2.094 2.114 2.105 1.997 2.196 2.215 2.093
4.586 4.972 5.465 5.339 5.601 5.092 5.586 5.459 5.679
1.809 1.897 2.094 2.114 2.108 1.997 2.197 2.216 2.098
4.581 4.964 5.457 5.330 5.595 5.083 5.575 5.448 5.670
1.804 1.889 2.085 2.105 2.104 1.988 2.186 2.205 2.092
4.614 5.000 5.493 5.367 5.629 5.117 5.611 5.484 5.704
1.837 1.925 2.122 2.142 2.127 2.022 2.222 2.241 2.115
4.610 4.996 5.489 5.363 5.625 5.114 5.608 5.481 5.701
1.833 1.921 2.118 2.138 2.123 2.019 2.219 2.238 2.112
4.604 4.990 5.483 5.357 5.619 5.108 5.602 5.475 5.695
1.827 1.915 2.112 2.132 2.117 2.013 2.213 2.232 2.106
4.625 5.014 5.511 5.385 5.647 5.131 5.628 5.501 5.721
1.848 1.939 2.140 2.160 2.145 2.036 2.239 2.258 2.132
4.614 5.002 5.499 5.373 5.635 5.120 5.617 5.490 5.710
1.837 1.927 2.128 2.148 2.133 2.025 2.228 2.247 2.121
4.618 5.007 5.505 5.379 5.641 5.126 5.624 5.497 5.717
1.841 1.932 2.134 2.154 2.139 2.031 2.235 2.254 2.128
4.654 5.031 5.518 5.390 5.656 5.165 5.639 5.511 5.734
1.872 1.951 2.138 2.158 2.146 2.051 2.242 2.261 2.138
4.654 5.031 5.518 5.390 5.656 5.165 5.639 5.511 5.734
1.872 1.951 2.138 2.158 2.146 2.051 2.242 2.261 2.138
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
—
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
1.5-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–110
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–67 through Table 1–72 show the maximum I/O timing parameters for
EP3SL110 devices for differential I/O standards.
Table 1–67 specifies EP3SL110 column pins input timing parameters for differential
I/O standards.
Table 1–67. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.978
1.104
0.967
-0.707
-0.978
1.104
0.967
-0.707
-0.978
1.104
0.967
-0.707
-0.794
0.913
1.151
-0.898
-0.794
0.913
1.151
-0.898
-0.802
0.921
1.143
-0.890
-0.802
0.921
1.143
-0.890
-0.814
0.933
1.131
-0.878
-1.006
1.152
1.001
-0.719
-1.006
1.152
1.001
-0.719
-1.006
1.152
1.001
-0.719
-0.829
0.967
1.178
-0.904
-0.829
0.967
1.178
-0.904
-0.841
0.979
1.166
-0.892
-0.841
0.979
1.166
-0.892
-0.852
0.990
1.155
-0.881
-1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632
1.371 1.387 1.564 1.502 1.860 1.361 1.634 1.471 1.898
1.885 2.230 2.404 2.293 2.197 2.284 2.556 2.353 2.249
-1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718
-1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632
1.371 1.387 1.564 1.502 1.860 1.361 1.634 1.471 1.898
1.885 2.230 2.404 2.293 2.197 2.284 2.556 2.353 2.249
-1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718
-1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632
1.371 1.387 1.564 1.502 1.860 1.361 1.634 1.471 1.898
1.885 2.230 2.404 2.293 2.197 2.284 2.556 2.353 2.249
-1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718
-1.228 -1.334 -1.445 -1.387 -1.743 -1.333 -1.443 -1.391 -1.786
1.416 1.546 1.677 1.610 1.964 1.554 1.684 1.621 2.007
1.808 2.031 2.245 2.139 2.048 2.049 2.266 2.155 2.095
-1.405 -1.576 -1.742 -1.661 -1.565 -1.587 -1.753 -1.668 -1.609
-1.228 -1.334 -1.445 -1.387 -1.743 -1.333 -1.443 -1.391 -1.786
1.416 1.546 1.677 1.610 1.964 1.554 1.684 1.621 2.007
1.808 2.031 2.245 2.139 2.048 2.049 2.266 2.155 2.095
-1.405 -1.576 -1.742 -1.661 -1.565 -1.587 -1.753 -1.668 -1.609
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
GCLK
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–111
I/O Timing
Table 1–67. EP3SL110 Column Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.814
0.933
1.131
-0.878
-0.802
0.921
1.143
-0.890
-0.802
0.921
1.143
-0.890
-0.814
0.933
1.131
-0.878
-0.814
0.933
1.131
-0.878
-0.821
0.940
1.124
-0.871
-0.821
0.940
1.124
-0.871
-0.852
0.990
1.155
-0.881
-0.841
0.979
1.166
-0.892
-0.841
0.979
1.166
-0.892
-0.852
0.990
1.155
-0.881
-0.852
0.990
1.155
-0.881
-0.858
0.996
1.149
-0.875
-0.858
0.996
1.149
-0.875
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576
-1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815
1.449 1.576 1.715 1.648 2.003 1.583 1.717 1.653 2.041
1.777 2.004 2.210 2.102 2.014 2.023 2.238 2.124 2.066
-1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575
-1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815
1.449 1.576 1.715 1.648 2.003 1.583 1.717 1.653 2.041
1.777 2.004 2.210 2.102 2.014 2.023 2.238 2.124 2.066
-1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
Table 1–68 specifies EP3SL110 parameters for differential I/O standards.
Table 1–68. EP3SL110 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
tsu
th
-0.919
1.043
0.959
-0.698
-0.950
1.092
0.987
-0.708
-1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442
1.245 1.237 1.395 1.339 1.672 1.207 1.358 1.303 1.711
1.949 2.324 2.527 2.403 2.334 2.384 2.597 2.470 2.387
-1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853
GCLK
LVDS
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–112
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–68. EP3SL110 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.919
1.043
0.959
-0.698
-0.919
1.043
0.959
-0.698
-0.724
0.841
1.154
-0.900
-0.724
0.841
1.154
-0.900
-0.733
0.850
1.145
-0.891
-0.733
0.850
1.145
-0.891
-0.747
0.864
1.131
-0.877
-0.747
0.864
1.131
-0.877
-0.733
0.850
1.145
-0.891
-0.950
1.092
0.987
-0.708
-0.950
1.092
0.987
-0.708
-0.765
0.898
1.172
-0.902
-0.765
0.898
1.172
-0.902
-0.777
0.910
1.160
-0.890
-0.777
0.910
1.160
-0.890
-0.789
0.922
1.148
-0.878
-0.789
0.922
1.148
-0.878
-0.777
0.910
1.160
-0.890
-1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442
1.245 1.237 1.395 1.339 1.672 1.207 1.358 1.303 1.711
1.949 2.324 2.527 2.403 2.334 2.384 2.597 2.470 2.387
-1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853
-1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442
1.245 1.237 1.395 1.339 1.672 1.207 1.358 1.303 1.711
1.949 2.324 2.527 2.403 2.334 2.384 2.597 2.470 2.387
-1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853
-1.113 -1.210 -1.304 -1.254 -1.583 -1.211 -1.303 -1.255 -1.626
1.302 1.420 1.535 1.474 1.802 1.429 1.543 1.483 1.846
1.862 2.100 2.338 2.219 2.155 2.117 2.360 2.238 2.203
-1.458 -1.649 -1.837 -1.746 -1.674 -1.657 -1.847 -1.753 -1.718
-1.113 -1.210 -1.304 -1.254 -1.583 -1.211 -1.303 -1.255 -1.626
1.302 1.420 1.535 1.474 1.802 1.429 1.543 1.483 1.846
1.862 2.100 2.338 2.219 2.155 2.117 2.360 2.238 2.203
-1.458 -1.649 -1.837 -1.746 -1.674 -1.657 -1.847 -1.753 -1.718
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702
GCLK
MINI-LVDS
tsu
th
GCLK
PLL
tsu
th
GCLK
RSDS
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS I
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–113
I/O Timing
Table 1–68. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.733
0.850
1.145
-0.891
-0.747
0.864
1.131
-0.877
-0.747
0.864
1.131
-0.877
-0.756
0.873
1.122
-0.868
-0.756
0.873
1.122
-0.868
-0.777
0.910
1.160
-0.890
-0.789
0.922
1.148
-0.878
-0.789
0.922
1.148
-0.878
-0.798
0.931
1.139
-0.869
-0.798
0.931
1.139
-0.869
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685
-1.145 -1.241 -1.345 -1.296 -1.623 -1.238 -1.337 -1.291 -1.661
1.336 1.454 1.579 1.518 1.847 1.459 1.582 1.521 1.886
1.825 2.064 2.293 2.173 2.110 2.086 2.321 2.197 2.163
-1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.805 -1.711 -1.674
-1.145 -1.241 -1.345 -1.296 -1.623 -1.238 -1.337 -1.291 -1.661
1.336 1.454 1.579 1.518 1.847 1.459 1.582 1.521 1.886
1.825 2.064 2.293 2.173 2.110 2.086 2.321 2.197 2.163
-1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.805 -1.711 -1.674
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS II
tsu
th
GCLK
PLL
Table 1–69 specifies EP3SL110 Column Pins Output Timing parameters for differential
I/O standards.
Table 1–69. EP3SL110 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.100
1.308
3.096
1.304
3.100
1.308
3.096
1.304
3.330
1.480
3.333
1.483
3.330
1.480
3.333
1.483
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277
—
—
—
—
LVDS_E_1R
LVDS_E_3R
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
GCLK
PLL
GCLK
MINI-
LVDS_E_3R
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–114
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–69. EP3SL110 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.100
1.308
3.096
1.304
3.127
1.335
3.117
1.325
3.117
1.325
3.110
1.318
3.109
1.317
3.131
1.339
3.121
1.329
3.116
1.324
3.114
1.322
3.106
1.314
3.107
1.315
3.106
1.314
3.330
1.480
3.333
1.483
3.363
1.513
3.353
1.503
3.353
1.503
3.347
1.497
3.345
1.495
3.367
1.517
3.356
1.506
3.352
1.502
3.350
1.500
3.341
1.491
3.343
1.493
3.340
1.490
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277
4.758 5.157 5.670 5.531 5.815 5.280 5.792 5.656 5.889
1.956 2.056 2.272 2.283 2.310 2.161 2.379 2.389 2.297
4.748 5.146 5.660 5.521 5.805 5.269 5.782 5.646 5.879
1.946 2.045 2.262 2.273 2.300 2.150 2.369 2.379 2.287
4.751 5.150 5.664 5.525 5.809 5.274 5.787 5.651 5.884
1.949 2.049 2.266 2.277 2.304 2.155 2.374 2.384 2.292
4.744 5.144 5.658 5.519 5.803 5.267 5.781 5.645 5.878
1.942 2.043 2.260 2.271 2.298 2.148 2.368 2.378 2.286
4.741 5.141 5.655 5.516 5.800 5.264 5.777 5.641 5.874
1.939 2.040 2.257 2.268 2.295 2.145 2.364 2.374 2.282
4.762 5.161 5.674 5.535 5.819 5.284 5.797 5.661 5.894
1.960 2.060 2.276 2.287 2.314 2.165 2.384 2.394 2.302
4.741 5.138 5.649 5.510 5.794 5.260 5.770 5.634 5.867
1.939 2.037 2.251 2.262 2.289 2.141 2.357 2.367 2.275
4.741 5.138 5.650 5.511 5.795 5.261 5.772 5.636 5.869
1.939 2.037 2.252 2.263 2.290 2.142 2.359 2.369 2.277
4.740 5.137 5.648 5.509 5.793 5.260 5.771 5.635 5.868
1.938 2.036 2.250 2.261 2.288 2.141 2.358 2.368 2.276
4.730 5.127 5.639 5.500 5.784 5.250 5.761 5.625 5.858
1.928 2.026 2.241 2.252 2.279 2.131 2.348 2.358 2.266
4.736 5.134 5.647 5.508 5.792 5.258 5.770 5.634 5.867
1.934 2.033 2.249 2.260 2.287 2.139 2.357 2.367 2.275
4.719 5.115 5.625 5.486 5.770 5.237 5.746 5.610 5.843
1.917 2.014 2.227 2.238 2.265 2.118 2.333 2.343 2.251
RSDS_E_1R
RSDS_E_3R
—
GCLK
PLL
GCLK
—
GCLK
PLL
GCLK
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
10mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–115
I/O Timing
Table 1–69. EP3SL110 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.118
1.326
3.114
1.322
3.104
1.312
3.102
1.310
3.102
1.310
3.106
1.314
3.132
1.340
3.118
1.326
3.106
1.314
3.106
1.314
3.102
1.310
3.106
1.314
3.107
1.315
3.353
1.503
3.350
1.500
3.339
1.489
3.337
1.487
3.338
1.488
3.341
1.491
3.370
1.520
3.356
1.506
3.343
1.493
3.343
1.493
3.339
1.489
3.341
1.491
3.343
1.493
4.737 5.133 5.643 5.504 5.788 5.256 5.765 5.629 5.862
1.935 2.032 2.245 2.256 2.283 2.137 2.352 2.362 2.270
4.738 5.135 5.647 5.508 5.792 5.258 5.769 5.633 5.866
1.936 2.034 2.249 2.260 2.287 2.139 2.356 2.366 2.274
4.727 5.124 5.635 5.496 5.780 5.247 5.757 5.621 5.854
1.925 2.023 2.237 2.248 2.275 2.128 2.344 2.354 2.262
4.725 5.121 5.633 5.494 5.778 5.245 5.755 5.619 5.852
1.923 2.020 2.235 2.246 2.273 2.126 2.342 2.352 2.260
4.728 5.126 5.638 5.499 5.783 5.249 5.761 5.625 5.858
1.926 2.025 2.240 2.251 2.278 2.130 2.348 2.358 2.266
4.725 5.121 5.632 5.493 5.777 5.244 5.754 5.618 5.851
1.923 2.020 2.234 2.245 2.272 2.125 2.341 2.351 2.259
4.770 5.169 5.682 5.543 5.827 5.292 5.804 5.668 5.901
1.968 2.068 2.284 2.295 2.322 2.173 2.391 2.401 2.309
4.758 5.158 5.672 5.533 5.817 5.282 5.795 5.659 5.892
1.956 2.057 2.274 2.285 2.312 2.163 2.382 2.392 2.300
4.741 5.140 5.654 5.515 5.799 5.264 5.777 5.641 5.874
1.939 2.039 2.256 2.267 2.294 2.145 2.364 2.374 2.282
4.744 5.144 5.658 5.519 5.803 5.268 5.782 5.646 5.879
1.942 2.043 2.260 2.271 2.298 2.149 2.369 2.379 2.287
4.737 5.136 5.651 5.512 5.796 5.261 5.774 5.638 5.871
1.935 2.035 2.253 2.264 2.291 2.142 2.361 2.371 2.279
4.730 5.127 5.639 5.500 5.784 5.250 5.761 5.625 5.858
1.928 2.026 2.241 2.252 2.279 2.131 2.348 2.358 2.266
4.738 5.137 5.650 5.511 5.795 5.260 5.773 5.637 5.870
1.936 2.036 2.252 2.263 2.290 2.141 2.360 2.370 2.278
4mA
6mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16mA
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–116
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–69. EP3SL110 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.135
1.343
3.124
1.332
3.119
1.327
3.105
1.313
3.103
1.311
3.107
1.315
3.107
1.315
3.123
1.331
3.123
1.331
3.113
1.321
3.106
1.314
3.373
1.523
3.361
1.511
3.357
1.507
3.342
1.492
3.340
1.490
3.342
1.492
3.343
1.493
3.360
1.510
3.360
1.510
3.350
1.500
3.342
1.492
4.769 5.167 5.680 5.541 5.825 5.291 5.802 5.666 5.899
1.967 2.066 2.282 2.293 2.320 2.172 2.389 2.399 2.307
4.757 5.155 5.668 5.529 5.813 5.279 5.790 5.654 5.887
1.955 2.054 2.270 2.281 2.308 2.160 2.377 2.387 2.295
4.757 5.156 5.669 5.530 5.814 5.280 5.792 5.656 5.889
1.955 2.055 2.271 2.282 2.309 2.161 2.379 2.389 2.297
4.739 5.137 5.650 5.511 5.795 5.261 5.774 5.638 5.871
1.937 2.036 2.252 2.263 2.290 2.142 2.361 2.371 2.279
4.737 5.135 5.648 5.509 5.793 5.259 5.771 5.635 5.868
1.935 2.034 2.250 2.261 2.288 2.140 2.358 2.368 2.276
4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855
1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263
4.737 5.135 5.648 5.509 5.793 5.259 5.771 5.635 5.868
1.935 2.034 2.250 2.261 2.288 2.140 2.358 2.368 2.276
4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881
1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289
4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881
1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289
4.743 5.140 5.652 5.513 5.797 5.264 5.775 5.639 5.872
1.941 2.039 2.254 2.265 2.292 2.145 2.362 2.372 2.280
4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855
1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263
4mA
6mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
GCLK
16mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
10mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–117
I/O Timing
Table 1–70 specifies EP3SL110 Row Pins Output Timing parameters for differential
I/O standards.
Table 1–70. EP3SL110 Row Pins output Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
LVDS
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
GCLK tco
2.711
0.934
3.106
1.326
3.088
1.308
2.711
0.934
3.106
1.326
3.088
1.308
2.711
0.934
3.106
1.326
3.088
1.308
3.132
1.352
3.118
1.338
3.114
1.334
3.130
1.350
2.894
1.059
3.342
1.503
3.332
1.493
2.894
1.059
3.342
1.503
3.332
1.493
2.894
1.059
3.342
1.503
3.332
1.493
3.375
1.536
3.361
1.522
3.357
1.518
3.372
1.533
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
—
GCLK
tco
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 ns
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863 ns
PLL
GCLK tco
—
GCLK
tco
ns
ns
ns
ns
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
—
GCLK
tco
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 ns
PLL
ns
ns
ns
ns
ns
GCLK tco
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802
MINI-
LVDS_E_3R
—
GCLK
tco
PLL
GCLK tco
RSDS
—
GCLK
tco
PLL
GCLK tco
RSDS_E_1R
RSDS_E_3R
—
GCLK
tco
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222 ns
PLL
ns
ns
ns
ns
GCLK tco
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283
4.783 5.187 5.698 5.562 5.817 5.313 5.826 5.689 5.892
1.993 2.096 2.309 2.322 2.325 2.204 2.420 2.430 2.312
—
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
4mA
6mA
8mA
4mA
GCLK
tco
PLL
GCLK tco
4.770 5.174 5.685 5.549 5.804 5.299 5.813 5.676 5.879 ns
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
ns
ns
ns
ns
ns
1.980 2.083 2.296 2.309 2.312 2.190 2.407 2.417 2.299
4.768 5.174 5.686 5.550 5.805 5.299 5.815 5.678 5.881
1.978 2.083 2.297 2.310 2.313 2.190 2.409 2.419 2.301
4.769 5.171 5.680 5.544 5.799 5.296 5.808 5.671 5.874
1.979 2.080 2.291 2.304 2.307 2.187 2.402 2.412 2.294
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–118
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–70. EP3SL110 Row Pins output Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
GCLK tco
3.119
1.339
3.116
1.336
3.127
1.347
3.117
1.337
3.103
1.323
3.100
1.320
3.097
1.317
3.098
1.318
3.147
1.367
3.123
1.343
3.106
1.326
3.151
1.371
3.136
1.356
3.362
1.523
3.359
1.520
3.369
1.530
3.360
1.521
3.346
1.507
3.342
1.503
3.340
1.501
3.340
1.501
3.393
1.554
3.369
1.530
3.350
1.511
3.396
1.557
3.381
1.542
4.765 5.167 5.677 5.541 5.796 5.293 5.805 5.668 5.871
1.975 2.076 2.288 2.301 2.304 2.184 2.399 2.409 2.291
DIFFERENTIAL
1.5-V
HSTL CLASS I
6mA
8mA
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
4mA
6mA
GCLK
tco
PLL
GCLK tco
4.763 5.165 5.675 5.539 5.794 5.291 5.804 5.667 5.870 ns
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
ns
ns
ns
ns
1.973 2.074 2.286 2.299 2.302 2.182 2.398 2.408 2.290
4.764 5.166 5.674 5.538 5.793 5.291 5.802 5.665 5.868
1.974 2.075 2.285 2.298 2.301 2.182 2.396 2.406 2.288
4.762 5.164 5.673 5.537 5.792 5.290 5.802 5.665 5.868
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
1.972 2.073 2.284 2.297 2.300 2.181 2.396 2.406 2.288 ns
4.747 5.149 5.659 5.523 5.778 5.275 5.787 5.650 5.853 ns
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
ns
ns
ns
ns
1.957 2.058 2.270 2.283 2.286 2.166 2.381 2.391 2.273
4.743 5.145 5.655 5.519 5.774 5.271 5.783 5.646 5.849
1.953 2.054 2.266 2.279 2.282 2.162 2.377 2.387 2.269
4.744 5.148 5.658 5.522 5.777 5.274 5.787 5.650 5.853
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
1.954 2.057 2.269 2.282 2.285 2.165 2.381 2.391 2.273 ns
PLL
ns
ns
ns
ns
GCLK tco
4.734 5.136 5.645 5.509 5.764 5.261 5.773 5.636 5.839
1.944 2.045 2.256 2.269 2.272 2.152 2.367 2.377 2.259
4.805 5.209 5.721 5.585 5.840 5.335 5.849 5.712 5.915
2.015 2.118 2.332 2.345 2.348 2.226 2.443 2.453 2.335
DIFFERENTIAL
1.8-V
HSTL CLASS II
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
4.787 5.192 5.704 5.568 5.823 5.318 5.834 5.697 5.900 ns
1.997 2.101 2.315 2.328 2.331 2.209 2.428 2.438 2.320 ns
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
ns
ns
ns
ns
GCLK tco
4.765 5.170 5.682 5.546 5.801 5.296 5.812 5.675 5.878
1.975 2.079 2.293 2.306 2.309 2.187 2.406 2.416 2.298
4.805 5.209 5.720 5.584 5.839 5.335 5.849 5.712 5.915
2.015 2.118 2.331 2.344 2.347 2.226 2.443 2.453 2.335
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
4.791 5.194 5.705 5.569 5.824 5.320 5.834 5.697 5.900 ns
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
ns
2.001 2.103 2.316 2.329 2.332 2.211 2.428 2.438 2.320
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–119
I/O Timing
Table 1–70. EP3SL110 Row Pins output Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
GCLK tco
3.125
1.345
3.105
1.325
3.102
1.322
3.107
1.327
3.100
1.320
3.138
1.358
3.120
1.340
3.106
1.326
3.370
1.531
3.350
1.511
3.346
1.507
3.350
1.511
3.343
1.504
3.382
1.543
3.365
1.526
3.349
1.510
4.786 5.191 5.702 5.566 5.821 5.317 5.832 5.695 5.898
1.996 2.100 2.313 2.326 2.329 2.208 2.426 2.436 2.318
DIFFERENTIAL
1.8-V
SSTL CLASS I
8mA
GCLK
tco
PLL
GCLK tco
4.763 5.167 5.679 5.543 5.798 5.294 5.808 5.671 5.874 ns
DIFFERENTIAL
1.8-V
SSTL CLASS I
10mA
12mA
8mA
GCLK
tco
ns
ns
ns
ns
1.973 2.076 2.290 2.303 2.306 2.185 2.402 2.412 2.294
4.759 5.164 5.675 5.539 5.794 5.290 5.805 5.668 5.871
1.969 2.073 2.286 2.299 2.302 2.181 2.399 2.409 2.291
4.750 5.152 5.661 5.525 5.780 5.277 5.789 5.652 5.855
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
GCLK
tco
1.960 2.061 2.272 2.285 2.288 2.168 2.383 2.393 2.275 ns
4.749 5.153 5.664 5.528 5.783 5.280 5.794 5.657 5.860 ns
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
16mA
8mA
GCLK
tco
ns
ns
ns
ns
1.959 2.062 2.275 2.288 2.291 2.171 2.388 2.398 2.280
4.787 5.190 5.700 5.564 5.819 5.316 5.829 5.692 5.895
1.997 2.099 2.311 2.324 2.327 2.207 2.423 2.433 2.315
4.772 5.175 5.685 5.549 5.804 5.301 5.814 5.677 5.880
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
12mA
16mA
GCLK
tco
1.982 2.084 2.296 2.309 2.312 2.192 2.408 2.418 2.300 ns
PLL
ns
ns
GCLK tco
4.749 5.151 5.660 5.524 5.779 5.277 5.789 5.652 5.855
1.959 2.060 2.271 2.284 2.287 2.168 2.383 2.393 2.275
DIFFERENTIAL
2.5-V
SSTL CLASS II
GCLK
tco
PLL
Table 1–71 and Table 1–72 show EP3SL110 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
Table 1–71 specifies EP3SL110 Column Pin delay adders when using the regional
clock.
Table 1–71. EP3SL110 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.186
2.391
-0.374
-2.001
0.171
2.371
-0.162
-1.786
0.245 0.255 0.268 0.261 0.393 0.248 0.277 0.267 0.364
3.577 4.036 4.418 4.225 4.574 4.044 4.442 4.246 4.635
-0.226 -0.233 -0.244 -0.239 -0.367 -0.111 -0.123 -0.116 -0.296
-2.669 -2.844 -2.996 -2.879 -2.722 -2.699 -3.067 -2.798 -2.773
ns
ns
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–120
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–72 specifies EP3SL110 Row Pin delay adders when using the regional clock.
Table 1–72. EP3SL110 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.086
0.075
-0.072
-0.063
0.109
0.075
-0.097
-0.065
0.158
0.16
0.161 0.159 0.281 0.137 0.153 0.153 0.285
ns
ns
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.117 0.123 0.129 0.125 0.222 0.113 0.118 0.114 0.226
-0.137 -0.135 -0.116 -0.134 -0.24 -0.11 -0.104 -0.124 -0.244
-0.097
-0.1 -0.104 -0.101 -0.198 -0.088 -0.09 -0.088 -0.201
EP3SL150 I/O Timing Parameters
Table 1–73 through Table 1–76 show the maximum I/O timing parameters for
EP3SL150 devices for single-ended I/O standards.
Table 1–73 specifies EP3SL150 column pins input timing parameters for single-ended
I/O standards.
Table 1–73. EP3SL150 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.036
1.154
0.708
-0.459
-1.036
1.154
0.708
-0.459
-1.042
1.160
0.702
-0.453
-1.042
1.160
0.702
-0.453
-1.032
1.150
0.712
-0.463
-1.079
1.214
0.731
-0.463
-1.079
1.214
0.731
-0.463
-1.090
1.225
0.720
-0.452
-1.090
1.225
0.720
-0.452
-1.085
1.220
0.725
-0.457
-1.538 -1.647 -1.930 -1.866 -2.197 -1.700 -1.935 -1.874 -2.155 ns
GCLK
1.730 1.858 2.168 2.089 2.423 1.922 2.182 2.106 2.378
1.217 1.392 1.435 1.347 1.339 1.383 1.451 1.360 1.398
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-0.818 -0.943 -0.935 -0.877 -0.856 -0.924 -0.940 -0.880 -0.912 ns
-1.538 -1.647 -1.930 -1.866 -2.197 -1.700 -1.935 -1.874 -2.155 ns
tsu
th
GCLK
1.730 1.858 2.168 2.089 2.423 1.922 2.182 2.106 2.378
1.217 1.392 1.435 1.347 1.339 1.383 1.451 1.360 1.398
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-0.818 -0.943 -0.935 -0.877 -0.856 -0.924 -0.940 -0.880 -0.912 ns
-1.537 -1.649 -1.929 -1.865 -2.196 -1.700 -1.940 -1.879 -2.160 ns
tsu
th
GCLK
1.729 1.860 2.167 2.088 2.422 1.922 2.187 2.111 2.383
1.218 1.390 1.436 1.348 1.340 1.383 1.446 1.355 1.393
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-0.819 -0.941 -0.936 -0.878 -0.857 -0.924 -0.935 -0.875 -0.907 ns
-1.537 -1.649 -1.929 -1.865 -2.196 -1.700 -1.940 -1.879 -2.160 ns
tsu
th
GCLK
1.729 1.860 2.167 2.088 2.422 1.922 2.187 2.111 2.383
1.218 1.390 1.436 1.348 1.340 1.383 1.446 1.355 1.393
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-0.819 -0.941 -0.936 -0.878 -0.857 -0.924 -0.935 -0.875 -0.907 ns
-1.546 -1.661 -1.948 -1.884 -2.215 -1.710 -1.951 -1.890 -2.171 ns
tsu
th
GCLK
1.738 1.872 2.186 2.107 2.441 1.932 2.198 2.122 2.394
1.209 1.378 1.417 1.329 1.321 1.373 1.435 1.344 1.382
ns
ns
2.5 V
tsu
th
GCLK
PLL
-0.810 -0.929 -0.917 -0.859 -0.838 -0.914 -0.924 -0.864 -0.896 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–121
I4L
Table 1–73. EP3SL150 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
1.1V
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.050
1.170
0.694
-0.443
-1.043
1.163
0.701
-0.450
-0.983
1.103
0.761
-0.510
-0.964
1.084
0.780
-0.529
-0.964
1.084
0.780
-0.529
-0.957
1.077
0.787
-0.536
-0.957
1.077
0.787
-0.536
-0.945
1.065
0.799
-0.548
-0.945
1.065
0.799
-0.548
-1.107
1.244
0.703
-0.433
-1.097
1.234
0.713
-0.443
-1.045
1.182
0.765
-0.495
-1.016
1.153
0.794
-0.524
-1.016
1.153
0.794
-0.524
-1.010
1.147
0.800
-0.530
-1.010
1.147
0.800
-0.530
-0.999
1.136
0.811
-0.541
-0.999
1.136
0.811
-0.541
-1.586 -1.697 -1.946 -1.882 -2.213 -1.744 -1.954 -1.893 -2.174 ns
GCLK
1.778 1.908 2.184 2.105 2.439 1.966 2.201 2.125 2.397
1.169 1.342 1.419 1.331 1.323 1.339 1.432 1.341 1.379
ns
ns
1.8 V
tsu
th
GCLK
PLL
-0.770 -0.893 -0.919 -0.861 -0.840 -0.880 -0.921 -0.861 -0.893 ns
-1.563 -1.665 -1.876 -1.812 -2.143 -1.713 -1.888 -1.827 -2.108 ns
tsu
th
GCLK
1.755 1.876 2.114 2.035 2.369 1.935 2.135 2.059 2.331
1.192 1.374 1.489 1.401 1.393 1.370 1.498 1.407 1.445
ns
ns
1.5 V
1.2 V
tsu
th
GCLK
PLL
-0.793 -0.925 -0.989 -0.931 -0.910 -0.911 -0.987 -0.927 -0.959 ns
-1.486 -1.566 -1.720 -1.656 -1.987 -1.617 -1.735 -1.674 -1.955 ns
tsu
th
GCLK
1.678 1.777 1.958 1.879 2.213 1.839 1.982 1.906 2.178
1.269 1.473 1.645 1.557 1.549 1.466 1.651 1.560 1.598
ns
ns
tsu
th
GCLK
PLL
-0.870 -1.024 -1.145 -1.087 -1.066 -1.007 -1.140 -1.080 -1.112 ns
-1.458 -1.550 -1.722 -1.658 -1.989 -1.596 -1.731 -1.670 -1.951 ns
tsu
th
GCLK
1.650 1.761 1.960 1.881 2.215 1.818 1.978 1.902 2.174
1.297 1.489 1.643 1.555 1.547 1.487 1.655 1.564 1.602
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-0.898 -1.040 -1.143 -1.085 -1.064 -1.028 -1.144 -1.084 -1.116 ns
-1.458 -1.550 -1.722 -1.658 -1.989 -1.596 -1.731 -1.670 -1.951 ns
tsu
th
GCLK
1.650 1.761 1.960 1.881 2.215 1.818 1.978 1.902 2.174
1.297 1.489 1.643 1.555 1.547 1.487 1.655 1.564 1.602
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-0.898 -1.040 -1.143 -1.085 -1.064 -1.028 -1.144 -1.084 -1.116 ns
-1.445 -1.542 -1.719 -1.653 -1.987 -1.589 -1.732 -1.669 -1.952 ns
tsu
th
GCLK
1.637 1.750 1.954 1.875 2.208 1.808 1.975 1.900 2.170
1.310 1.497 1.646 1.560 1.549 1.494 1.654 1.565 1.601
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-0.911 -1.051 -1.149 -1.091 -1.071 -1.038 -1.147 -1.086 -1.120 ns
-1.445 -1.542 -1.719 -1.653 -1.987 -1.589 -1.732 -1.669 -1.952 ns
tsu
th
GCLK
1.637 1.750 1.954 1.875 2.208 1.808 1.975 1.900 2.170
1.310 1.497 1.646 1.560 1.549 1.494 1.654 1.565 1.601
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-0.911 -1.051 -1.149 -1.091 -1.071 -1.038 -1.147 -1.086 -1.120 ns
-1.434 -1.531 -1.700 -1.634 -1.968 -1.578 -1.714 -1.651 -1.934 ns
tsu
th
GCLK
1.625 1.739 1.935 1.856 2.189 1.797 1.957 1.882 2.152
1.321 1.508 1.665 1.579 1.568 1.505 1.672 1.583 1.619
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-0.923 -1.062 -1.168 -1.110 -1.090 -1.049 -1.165 -1.104 -1.138 ns
-1.434 -1.531 -1.700 -1.634 -1.968 -1.578 -1.714 -1.651 -1.934 ns
tsu
th
GCLK
1.625 1.739 1.935 1.856 2.189 1.797 1.957 1.882 2.152
1.321 1.508 1.665 1.579 1.568 1.505 1.672 1.583 1.619
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.923 -1.062 -1.168 -1.110 -1.090 -1.049 -1.165 -1.104 -1.138 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–122
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–73. EP3SL150 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.957
1.077
0.787
-0.536
-0.957
1.077
0.787
-0.536
-0.945
1.065
0.799
-0.548
-0.945
1.065
0.799
-0.548
-0.937
1.057
0.807
-0.556
-0.937
1.057
0.807
-0.556
-1.042
1.160
0.702
-0.453
-1.010
1.147
0.800
-0.530
-1.010
1.147
0.800
-0.530
-0.999
1.136
0.811
-0.541
-0.999
1.136
0.811
-0.541
-0.987
1.124
0.823
-0.553
-0.987
1.124
0.823
-0.553
-1.090
1.225
0.720
-0.452
-1.445 -1.542 -1.719 -1.653 -1.987 -1.589 -1.732 -1.669 -1.952 ns
GCLK
1.637 1.750 1.954 1.875 2.208 1.808 1.975 1.900 2.170
1.310 1.497 1.646 1.560 1.549 1.494 1.654 1.565 1.601
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.911 -1.051 -1.149 -1.091 -1.071 -1.038 -1.147 -1.086 -1.120 ns
-1.445 -1.542 -1.719 -1.653 -1.987 -1.589 -1.732 -1.669 -1.952 ns
tsu
th
GCLK
1.637 1.750 1.954 1.875 2.208 1.808 1.975 1.900 2.170
1.310 1.497 1.646 1.560 1.549 1.494 1.654 1.565 1.601
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.911 -1.051 -1.149 -1.091 -1.071 -1.038 -1.147 -1.086 -1.120 ns
-1.434 -1.531 -1.700 -1.634 -1.968 -1.578 -1.714 -1.651 -1.934 ns
tsu
th
GCLK
1.625 1.739 1.935 1.856 2.189 1.797 1.957 1.882 2.152
1.321 1.508 1.665 1.579 1.568 1.505 1.672 1.583 1.619
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.923 -1.062 -1.168 -1.110 -1.090 -1.049 -1.165 -1.104 -1.138 ns
-1.434 -1.531 -1.700 -1.634 -1.968 -1.578 -1.714 -1.651 -1.934 ns
tsu
th
GCLK
1.625 1.739 1.935 1.856 2.189 1.797 1.957 1.882 2.152
1.321 1.508 1.665 1.579 1.568 1.505 1.672 1.583 1.619
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.923 -1.062 -1.168 -1.110 -1.090 -1.049 -1.165 -1.104 -1.138 ns
-1.424 -1.520 -1.684 -1.618 -1.952 -1.567 -1.699 -1.636 -1.919 ns
tsu
th
GCLK
1.615 1.728 1.919 1.840 2.173 1.786 1.942 1.867 2.137
1.331 1.519 1.681 1.595 1.584 1.516 1.687 1.598 1.634
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.933 -1.073 -1.184 -1.126 -1.106 -1.060 -1.180 -1.119 -1.153 ns
-1.424 -1.520 -1.684 -1.618 -1.952 -1.567 -1.699 -1.636 -1.919 ns
tsu
th
GCLK
1.615 1.728 1.919 1.840 2.173 1.786 1.942 1.867 2.137
1.331 1.519 1.681 1.595 1.584 1.516 1.687 1.598 1.634
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-0.933 -1.073 -1.184 -1.126 -1.106 -1.060 -1.180 -1.119 -1.153 ns
-1.537 -1.649 -1.929 -1.865 -2.196 -1.700 -1.940 -1.879 -2.160 ns
tsu
th
GCLK
1.729 1.860 2.167 2.088 2.422 1.922 2.187 2.111 2.383
1.218 1.390 1.436 1.348 1.340 1.383 1.446 1.355 1.393
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-0.819 -0.941 -0.936 -0.878 -0.857 -0.924 -0.935 -0.875 -0.907 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–123
I/O Timing
Table 1–74 specifies EP3SL150 row pins input timing parameters for single-ended
I/O standards.
Table 1–74. EP3SL150 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.925
1.040
0.988
-0.737
-0.925
1.040
0.988
-0.737
-0.931
1.046
0.982
-0.731
-0.931
1.046
0.982
-0.731
-0.919
1.034
0.994
-0.743
-0.949
1.065
0.964
-0.712
-0.939
1.055
0.974
-0.722
-0.879
0.995
1.034
-0.782
-0.964
1.094
1.009
-0.741
-0.964
1.094
1.009
-0.741
-0.975
1.105
0.998
-0.730
-0.975
1.105
0.998
-0.730
-0.968
1.098
1.005
-0.737
-1.000
1.131
0.966
-0.698
-0.989
1.120
0.977
-0.709
-0.936
1.067
1.030
-0.762
-1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993
1.544 1.677 1.910 1.851 2.173 1.698 1.917 1.860 2.212
1.642 1.858 1.971 1.855 1.796 1.865 1.993 1.875 1.848
-1.241 -1.407 -1.471 -1.383 -1.314 -1.407 -1.482 -1.393 -1.363
-1.360 -1.470 -1.682 -1.633 -1.954 -1.480 -1.679 -1.634 -1.993
1.544 1.677 1.910 1.851 2.173 1.698 1.917 1.860 2.212
1.642 1.858 1.971 1.855 1.796 1.865 1.993 1.875 1.848
-1.241 -1.407 -1.471 -1.383 -1.314 -1.407 -1.482 -1.393 -1.363
GCLK
3.3-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
-1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998 ns
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217
1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843
-1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358
-1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998
1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217
1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843
-1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358
-1.366 -1.484 -1.700 -1.651 -1.972 -1.488 -1.694 -1.649 -2.008
1.550 1.691 1.928 1.869 2.191 1.706 1.932 1.875 2.227
1.636 1.844 1.953 1.837 1.778 1.857 1.978 1.860 1.833
-1.235 -1.393 -1.453 -1.365 -1.296 -1.399 -1.467 -1.378 -1.348
-1.406 -1.530 -1.590 -1.662 -1.875 -1.521 -1.582 -1.663 -1.913
1.590 1.738 1.824 1.880 2.098 1.739 1.826 1.889 2.137
1.589 1.806 1.955 1.835 1.780 1.824 1.977 1.854 1.832
-1.190 -1.356 -1.455 -1.362 -1.298 -1.366 -1.466 -1.372 -1.347
-1.382 -1.498 -1.522 -1.594 -1.807 -1.490 -1.517 -1.598 -1.848
1.566 1.706 1.756 1.812 2.030 1.708 1.761 1.824 2.072
1.613 1.838 2.023 1.903 1.848 1.855 2.042 1.919 1.897
-1.214 -1.388 -1.523 -1.430 -1.366 -1.397 -1.531 -1.437 -1.412
3.0-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
-1.303 -1.397 -1.363 -1.435 -1.648 -1.394 -1.362 -1.443 -1.693 ns
GCLK
ns
ns
1.487 1.605 1.597 1.653 1.871 1.612 1.606 1.669 1.917
1.692 1.939 2.182 2.062 2.007 1.951 2.197 2.074 2.052
tsu
th
GCLK
PLL
-1.293 -1.489 -1.682 -1.589 -1.525 -1.493 -1.686 -1.592 -1.567 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–124
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–74. EP3SL150 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
tsu
th
-0.862
0.978
1.051
-0.799
-0.862
0.978
1.051
-0.799
-0.853
0.969
1.060
-0.808
-0.853
0.969
1.060
-0.808
-0.839
0.955
1.074
-0.822
-0.853
0.969
1.060
-0.808
-0.853
0.969
1.060
-0.808
-0.839
0.955
1.074
-0.822
-0.839
0.955
1.074
-0.822
-0.910
1.041
1.063
-0.794
-0.910
1.041
1.063
-0.794
-0.901
1.032
1.065
-0.797
-0.901
1.032
1.065
-0.797
-0.889
1.020
1.077
-0.809
-0.901
1.032
1.065
-0.797
-0.901
1.032
1.065
-0.797
-0.889
1.020
1.077
-0.809
-0.889
1.020
1.077
-0.809
-1.280 -1.375 -1.480 -1.431 -1.752 -1.376 -1.477 -1.432 -1.791
1.464 1.582 1.708 1.649 1.971 1.594 1.715 1.658 2.010
1.722 1.953 2.173 2.057 1.998 1.969 2.195 2.077 2.050
-1.321 -1.502 -1.673 -1.585 -1.516 -1.511 -1.684 -1.595 -1.565
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
tsu
th
-1.280 -1.375 -1.480 -1.431 -1.752 -1.376 -1.477 -1.432 -1.791 ns
GCLK
ns
ns
1.464 1.582 1.708 1.649 1.971 1.594 1.715 1.658 2.010
1.722 1.953 2.173 2.057 1.998 1.969 2.195 2.077 2.050
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-1.321 -1.502 -1.673 -1.585 -1.516 -1.511 -1.684 -1.595 -1.565 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.265 -1.370 -1.361 -1.429 -1.646 -1.362 -1.358 -1.435 -1.688
1.449 1.576 1.592 1.646 1.865 1.578 1.599 1.660 1.908
1.730 1.966 2.187 2.068 2.011 1.983 2.204 2.082 2.059
-1.331 -1.518 -1.689 -1.596 -1.533 -1.527 -1.696 -1.601 -1.578
-1.265 -1.370 -1.361 -1.429 -1.646 -1.362 -1.358 -1.435 -1.688
1.449 1.576 1.592 1.646 1.865 1.578 1.599 1.660 1.908
1.730 1.966 2.187 2.068 2.011 1.983 2.204 2.082 2.059
-1.331 -1.518 -1.689 -1.596 -1.533 -1.527 -1.696 -1.601 -1.578
-1.250 -1.360 -1.343 -1.411 -1.628 -1.351 -1.341 -1.418 -1.671
1.435 1.566 1.574 1.628 1.847 1.567 1.582 1.643 1.891
1.745 1.976 2.205 2.086 2.029 1.994 2.221 2.099 2.076
-1.345 -1.528 -1.707 -1.614 -1.551 -1.538 -1.713 -1.618 -1.595
-1.265 -1.370 -1.361 -1.429 -1.646 -1.362 -1.358 -1.435 -1.688
1.449 1.576 1.592 1.646 1.865 1.578 1.599 1.660 1.908
1.730 1.966 2.187 2.068 2.011 1.983 2.204 2.082 2.059
-1.331 -1.518 -1.689 -1.596 -1.533 -1.527 -1.696 -1.601 -1.578
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-15
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
-1.265 -1.370 -1.361 -1.429 -1.646 -1.362 -1.358 -1.435 -1.688 ns
GCLK
ns
ns
1.449 1.576 1.592 1.646 1.865 1.578 1.599 1.660 1.908
1.730 1.966 2.187 2.068 2.011 1.983 2.204 2.082 2.059
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.331 -1.518 -1.689 -1.596 -1.533 -1.527 -1.696 -1.601 -1.578 ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.250 -1.360 -1.343 -1.411 -1.628 -1.351 -1.341 -1.418 -1.671
1.435 1.566 1.574 1.628 1.847 1.567 1.582 1.643 1.891
1.745 1.976 2.205 2.086 2.029 1.994 2.221 2.099 2.076
-1.345 -1.528 -1.707 -1.614 -1.551 -1.538 -1.713 -1.618 -1.595
-1.250 -1.360 -1.343 -1.411 -1.628 -1.351 -1.341 -1.418 -1.671
1.435 1.566 1.574 1.628 1.847 1.567 1.582 1.643 1.891
1.745 1.976 2.205 2.086 2.029 1.994 2.221 2.099 2.076
-1.345 -1.528 -1.707 -1.614 -1.551 -1.538 -1.713 -1.618 -1.595
GCLK
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–125
I/O Timing
Table 1–74. EP3SL150 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
tsu
th
-0.830
0.946
1.083
-0.831
-0.830
0.946
1.083
-0.831
-0.931
1.046
0.982
-0.731
-0.931
1.046
0.982
-0.731
-0.877
1.008
1.089
-0.821
-0.877
1.008
1.089
-0.821
-0.975
1.105
0.998
-0.730
-0.975
1.105
0.998
-0.730
-1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655
1.426 1.556 1.558 1.612 1.831 1.558 1.566 1.627 1.875
1.754 1.986 2.221 2.102 2.045 2.003 2.237 2.115 2.092
-1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611
GCLK
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
-1.241 -1.350 -1.327 -1.395 -1.612 -1.342 -1.325 -1.402 -1.655 ns
GCLK
ns
ns
1.426 1.556 1.558 1.612 1.831 1.558 1.566 1.627 1.875
1.754 1.986 2.221 2.102 2.045 2.003 2.237 2.115 2.092
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.354 -1.538 -1.723 -1.630 -1.567 -1.547 -1.729 -1.634 -1.611 ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998
1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217
1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843
-1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358
-1.357 -1.471 -1.685 -1.636 -1.957 -1.479 -1.684 -1.639 -1.998
1.541 1.678 1.913 1.854 2.176 1.697 1.922 1.865 2.217
1.645 1.857 1.968 1.852 1.793 1.866 1.988 1.870 1.843
-1.244 -1.406 -1.468 -1.380 -1.311 -1.408 -1.477 -1.388 -1.358
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
PCI-X
tsu
th
GCLK
PLL
Table 1–75 specifies EP3SL150 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–75. EP3SL150 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.198
1.553
3.119
1.474
3.089
1.445
3.075
1.431
3.443
1.734
3.354
1.645
3.322
1.613
3.308
1.599
4.777 5.155 5.678 5.539 5.818 5.301 5.805 5.669 5.862
4mA
GCLK
tco
2.513
2.197 2.314 2.565 2.541 2.527 2.422 2.652 2.651
PLL
GCLK tco
4.673 5.043 5.561 5.422 5.701 5.185 5.685 5.549 5.742
8mA
GCLK
tco
2.393
2.094 2.202 2.448 2.424 2.410 2.306 2.532 2.531
PLL
3.3-V
LVTTL
GCLK tco
4.606 4.973 5.491 5.352 5.631 5.115 5.618 5.482 5.674
12mA
16mA
GCLK
tco
2.326
2.027 2.132 2.378 2.354 2.340 2.236 2.465 2.464
PLL
GCLK tco
4.585 4.950 5.463 5.324 5.603 5.089 5.584 5.448 5.640
GCLK
tco
2.292
2.006 2.109 2.350 2.326 2.312 2.210 2.432 2.431
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–126
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–75. EP3SL150 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.135
1.491
3.064
1.420
3.040
1.395
3.033
1.388
3.195
1.551
3.128
1.484
3.090
1.446
3.068
1.424
3.150
1.505
3.077
1.433
3.053
1.409
3.053
1.409
3.376
1.667
3.299
1.590
3.271
1.562
3.264
1.555
3.452
1.743
3.367
1.658
3.330
1.621
3.303
1.594
3.392
1.683
3.313
1.604
3.284
1.575
3.284
1.575
4.704 5.072 5.590 5.451 5.730 5.215 5.717 5.581 5.774
4mA
GCLK
tco
2.425
2.124 2.231 2.477 2.453 2.439 2.336 2.564 2.563
PLL
GCLK tco
4.582 4.946 5.459 5.320 5.599 5.085 5.580 5.444 5.636
8mA
GCLK
tco
2.288
2.002 2.105 2.346 2.322 2.308 2.206 2.427 2.426
PLL
3.3-V
LVCMOS
GCLK tco
4.553 4.919 5.434 5.295 5.574 5.058 5.555 5.419 5.610
12mA
16mA
4mA
GCLK
tco
2.263
1.973 2.078 2.321 2.297 2.283 2.179 2.402 2.401
PLL
GCLK tco
4.545 4.910 5.425 5.286 5.565 5.048 5.545 5.409 5.600
GCLK
tco
2.253
1.965 2.069 2.312 2.288 2.274 2.170 2.393 2.392
PLL
GCLK tco
4.811 5.191 5.717 5.578 5.857 5.339 5.847 5.711 5.903
GCLK
tco
2.555
2.231 2.350 2.604 2.580 2.566 2.461 2.694 2.693
PLL
GCLK tco
4.707 5.079 5.601 5.462 5.741 5.225 5.728 5.592 5.785
8mA
GCLK
tco
2.436
2.127 2.239 2.488 2.464 2.450 2.346 2.576 2.575
PLL
3.0-V
LVTTL
GCLK tco
4.639 5.008 5.527 5.388 5.667 5.151 5.652 5.516 5.708
12mA
16mA
4mA
GCLK
tco
2.360
2.059 2.167 2.414 2.390 2.376 2.272 2.500 2.499
PLL
GCLK tco
4.604 4.969 5.485 5.346 5.625 5.111 5.609 5.473 5.665
GCLK
tco
2.317
2.024 2.128 2.372 2.348 2.334 2.232 2.456 2.455
PLL
GCLK tco
4.741 5.113 5.636 5.497 5.776 5.259 5.765 5.629 5.821
GCLK
tco
2.473
2.161 2.272 2.523 2.499 2.485 2.380 2.612 2.611
PLL
GCLK tco
4.617 4.984 5.501 5.362 5.641 5.126 5.625 5.489 5.681
8mA
GCLK
tco
2.333
2.038 2.143 2.388 2.364 2.350 2.247 2.473 2.472
PLL
3.0-V
LVCMOS
GCLK tco
4.578 4.944 5.460 5.321 5.600 5.086 5.584 5.448 5.640
12mA
16mA
GCLK
tco
2.292
1.998 2.104 2.347 2.323 2.309 2.207 2.431 2.430
PLL
GCLK tco
4.570 4.935 5.450 5.311 5.590 5.075 5.572 5.436 5.627
GCLK
tco
2.280
1.990 2.094 2.337 2.313 2.299 2.196 2.419 2.418
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–127
I/O Timing
Table 1–75. EP3SL150 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.254
1.609
3.171
1.526
3.115
1.471
3.082
1.437
3.368
1.723
3.270
1.625
3.188
1.543
3.162
1.518
3.091
1.447
3.086
1.442
3.507
1.798
3.414
1.705
3.370
1.661
3.324
1.615
3.635
1.926
3.524
1.815
3.437
1.728
3.404
1.695
3.340
1.631
3.330
1.621
4.948 5.340 5.883 5.744 6.023 5.492 6.020 5.884 6.075
4mA
GCLK
tco
2.728
2.368 2.499 2.770 2.746 2.732 2.613 2.867 2.866
PLL
GCLK tco
4.829 5.214 5.751 5.612 5.891 5.364 5.884 5.748 5.940
8mA
GCLK
tco
2.592
2.249 2.373 2.638 2.614 2.600 2.485 2.731 2.730
PLL
2.5 V
GCLK tco
4.737 5.118 5.651 5.512 5.791 5.266 5.782 5.646 5.838
12mA
16mA
2mA
GCLK
tco
2.490
2.157 2.277 2.538 2.514 2.500 2.387 2.629 2.628
PLL
GCLK tco
4.703 5.081 5.610 5.471 5.750 5.226 5.738 5.602 5.794
GCLK
tco
2.446
2.123 2.240 2.497 2.473 2.459 2.348 2.585 2.584
PLL
GCLK tco
5.142 5.549 6.101 5.962 6.241 5.710 6.246 6.110 6.303
GCLK
tco
2.954
2.563 2.708 2.988 2.964 2.950 2.831 3.093 3.092
PLL
GCLK tco
4.990 5.391 5.940 5.801 6.080 5.551 6.080 5.944 6.137
4mA
GCLK
tco
2.788
2.411 2.550 2.827 2.803 2.789 2.672 2.927 2.926
PLL
GCLK tco
4.863 5.253 5.796 5.657 5.936 5.407 5.932 5.796 5.988
6mA
GCLK
tco
2.640
2.284 2.412 2.683 2.659 2.645 2.528 2.780 2.779
PLL
1.8 V
GCLK tco
4.803 5.187 5.721 5.582 5.861 5.336 5.852 5.716 5.908
8mA
GCLK
tco
2.560
2.223 2.346 2.608 2.584 2.570 2.457 2.699 2.698
PLL
GCLK tco
4.715 5.093 5.622 5.483 5.762 5.239 5.751 5.615 5.807
10mA
12mA
GCLK
tco
2.459
2.135 2.252 2.509 2.485 2.471 2.360 2.598 2.597
PLL
GCLK tco
4.709 5.087 5.615 5.476 5.755 5.232 5.744 5.608 5.800
GCLK
tco
2.452
2.129 2.246 2.502 2.478 2.464 2.353 2.591 2.590
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–128
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–75. EP3SL150 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.308
1.664
3.177
1.532
3.132
1.488
3.121
1.476
3.086
1.441
3.082
1.437
3.288
1.643
3.165
1.521
3.112
1.468
3.092
1.447
3.105
1.461
3.108
1.464
3.090
1.445
3.602
1.893
3.421
1.712
3.384
1.675
3.378
1.669
3.327
1.618
3.320
1.611
3.545
1.836
3.410
1.701
3.369
1.660
3.335
1.626
3.343
1.634
3.346
1.637
3.326
1.617
5.081 5.476 6.029 5.890 6.169 5.640 6.179 6.043 6.236
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
8mA
10mA
12mA
GCLK
tco
2.887
2.501 2.635 2.916 2.892 2.878 2.761 3.026 3.025
PLL
GCLK tco
4.837 5.222 5.758 5.619 5.898 5.372 5.892 5.756 5.948
GCLK
tco
2.600
2.258 2.381 2.645 2.621 2.607 2.493 2.740 2.739
PLL
GCLK tco
4.757 5.142 5.678 5.539 5.818 5.292 5.809 5.673 5.865
GCLK
tco
2.517
2.177 2.301 2.565 2.541 2.527 2.413 2.657 2.656
PLL
1.5 V
GCLK tco
4.751 5.134 5.669 5.530 5.809 5.285 5.802 5.666 5.857
GCLK
tco
2.510
2.171 2.294 2.556 2.532 2.518 2.406 2.649 2.648
PLL
GCLK tco
4.703 5.081 5.608 5.469 5.748 5.226 5.737 5.601 5.793
GCLK
tco
2.445
2.123 2.240 2.495 2.471 2.457 2.347 2.584 2.583
PLL
GCLK tco
4.682 5.060 5.588 5.449 5.728 5.205 5.715 5.579 5.771
GCLK
tco
2.423
2.103 2.219 2.475 2.451 2.437 2.326 2.563 2.562
PLL
GCLK tco
5.035 5.430 5.972 5.833 6.112 5.587 6.113 5.977 6.171
GCLK
tco
2.821
2.455 2.589 2.859 2.835 2.821 2.708 2.960 2.959
PLL
GCLK tco
4.816 5.199 5.732 5.593 5.872 5.348 5.864 5.728 5.920
GCLK
tco
2.572
2.236 2.358 2.619 2.595 2.581 2.469 2.712 2.711
PLL
1.2 V
GCLK tco
4.740 5.122 5.658 5.519 5.798 5.273 5.792 5.656 5.847
GCLK
tco
2.500
2.160 2.281 2.545 2.521 2.507 2.394 2.639 2.638
PLL
GCLK tco
4.701 5.079 5.608 5.469 5.748 5.224 5.735 5.599 5.791
GCLK
tco
2.443
2.121 2.238 2.495 2.471 2.457 2.345 2.582 2.581
PLL
GCLK tco
4.709 5.087 5.616 5.477 5.756 5.229 5.740 5.604 5.795
GCLK
tco
2.448
2.129 2.246 2.503 2.479 2.465 2.351 2.587 2.586
PLL
GCLK tco
4.713 5.091 5.620 5.481 5.760 5.233 5.744 5.608 5.799
SSTL-2
CLASS I
GCLK
tco
2.452
2.133 2.250 2.507 2.483 2.469 2.354 2.591 2.590
PLL
GCLK tco
4.691 5.069 5.598 5.459 5.738 5.212 5.722 5.586 5.777
GCLK
tco
2.430
2.112 2.228 2.485 2.461 2.447 2.333 2.569 2.568
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–129
I/O Timing
Table 1–75. EP3SL150 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.085
1.440
3.123
1.479
3.104
1.460
3.105
1.461
3.088
1.444
3.085
1.440
3.085
1.441
3.084
1.440
3.115
1.470
3.100
1.455
3.087
1.442
3.087
1.443
3.083
1.438
3.319
1.610
3.363
1.654
3.342
1.633
3.345
1.636
3.325
1.616
3.321
1.612
3.320
1.611
3.320
1.611
3.354
1.645
3.338
1.629
3.323
1.614
3.324
1.615
3.319
1.610
4.676 5.053 5.581 5.442 5.721 5.195 5.704 5.568 5.759
SSTL-2
CLASS II
16mA
4mA
GCLK
tco
2.412
2.097 2.212 2.468 2.444 2.430 2.316 2.552 2.551
PLL
GCLK tco
4.732 5.110 5.639 5.500 5.779 5.253 5.764 5.628 5.818
GCLK
tco
2.472
2.152 2.269 2.526 2.502 2.488 2.374 2.611 2.610
PLL
GCLK tco
4.710 5.088 5.617 5.478 5.757 5.231 5.741 5.605 5.796
6mA
GCLK
tco
2.449
2.130 2.247 2.504 2.480 2.466 2.352 2.588 2.587
PLL
GCLK tco
4.718 5.097 5.627 5.488 5.767 5.241 5.752 5.616 5.807
SSTL-18
CLASS I
8mA
GCLK
tco
2.460
2.138 2.256 2.514 2.490 2.476 2.362 2.599 2.598
PLL
GCLK tco
4.693 5.072 5.602 5.463 5.742 5.215 5.726 5.590 5.782
10mA
12mA
8mA
GCLK
tco
2.434
2.114 2.231 2.489 2.465 2.451 2.336 2.574 2.573
PLL
GCLK tco
4.689 5.068 5.597 5.458 5.737 5.211 5.722 5.586 5.778
GCLK
tco
2.430
2.110 2.227 2.484 2.460 2.446 2.332 2.570 2.569
PLL
GCLK tco
4.677 5.053 5.581 5.442 5.721 5.196 5.705 5.569 5.760
GCLK
tco
2.413
2.097 2.213 2.468 2.444 2.430 2.317 2.552 2.551
PLL
SSTL-18
CLASS II
GCLK tco
4.685 5.063 5.593 5.454 5.733 5.206 5.718 5.582 5.773
16mA
4mA
GCLK
tco
2.426
2.105 2.223 2.480 2.456 2.442 2.327 2.565 2.564
PLL
GCLK tco
4.725 5.103 5.631 5.492 5.771 5.246 5.756 5.620 5.811
GCLK
tco
2.464
2.145 2.262 2.518 2.494 2.480 2.367 2.603 2.602
PLL
GCLK tco
4.711 5.090 5.619 5.480 5.759 5.233 5.745 5.609 5.800
6mA
GCLK
tco
2.453
2.131 2.249 2.506 2.482 2.468 2.354 2.592 2.591
PLL
GCLK tco
4.691 5.069 5.599 5.460 5.739 5.213 5.724 5.588 5.779
SSTL-15
CLASS I
8mA
GCLK
tco
2.432
2.111 2.228 2.486 2.462 2.448 2.334 2.571 2.570
PLL
GCLK tco
4.692 5.071 5.602 5.463 5.742 5.215 5.727 5.591 5.782
10mA
12mA
GCLK
tco
2.435
2.112 2.230 2.489 2.465 2.451 2.336 2.574 2.573
PLL
GCLK tco
4.685 5.064 5.594 5.455 5.734 5.207 5.719 5.583 5.774
GCLK
tco
2.427
2.105 2.223 2.481 2.457 2.443 2.328 2.566 2.565
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–130
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–75. EP3SL150 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.101
1.456
3.100
1.455
3.087
1.442
3.082
1.438
3.084
1.440
3.083
1.439
3.102
1.457
3.097
1.452
3.096
1.452
3.087
1.442
3.088
1.444
3.110
1.466
3.100
1.455
3.336
1.627
3.336
1.627
3.322
1.613
3.317
1.608
3.320
1.611
3.318
1.609
3.337
1.628
3.333
1.624
3.332
1.623
3.322
1.613
3.324
1.615
3.349
1.640
3.337
1.628
4.693 5.069 5.596 5.457 5.736 5.211 5.720 5.584 5.775
8mA
GCLK
tco
2.428
2.113 2.228 2.483 2.459 2.445 2.332 2.567 2.566
PLL
SSTL-15
CLASS II
GCLK tco
4.697 5.074 5.602 5.463 5.742 5.216 5.726 5.590 5.781
16mA
4mA
GCLK
tco
2.434
2.117 2.233 2.489 2.465 2.451 2.337 2.573 2.572
PLL
GCLK tco
4.681 5.058 5.586 5.447 5.726 5.200 5.710 5.574 5.765
GCLK
tco
2.418
2.101 2.217 2.473 2.449 2.435 2.321 2.557 2.556
PLL
GCLK tco
4.675 5.052 5.580 5.441 5.720 5.194 5.704 5.568 5.759
6mA
GCLK
tco
2.412
2.095 2.211 2.467 2.443 2.429 2.315 2.551 2.550
PLL
GCLK tco
4.680 5.057 5.586 5.447 5.726 5.200 5.710 5.574 5.765
1.8-V
HSTL
CLASS I
8mA
GCLK
tco
2.418
2.100 2.216 2.473 2.449 2.435 2.321 2.558 2.557
PLL
GCLK tco
4.673 5.050 5.578 5.439 5.718 5.192 5.701 5.565 5.756
10mA
12mA
16mA
4mA
GCLK
tco
2.409
2.093 2.209 2.465 2.441 2.427 2.313 2.549 2.548
PLL
GCLK tco
4.695 5.071 5.599 5.460 5.739 5.214 5.722 5.586 5.777
GCLK
tco
2.430
2.115 2.230 2.486 2.462 2.448 2.335 2.570 2.569
PLL
GCLK tco
4.693 5.070 5.598 5.459 5.738 5.213 5.722 5.586 5.777
1.8-V
HSTL
CLASS II
GCLK
tco
2.430
2.113 2.229 2.485 2.461 2.447 2.334 2.569 2.568
PLL
GCLK tco
4.694 5.071 5.599 5.460 5.739 5.214 5.723 5.587 5.778
GCLK
tco
2.431
2.114 2.230 2.486 2.462 2.448 2.335 2.570 2.569
PLL
GCLK tco
4.681 5.059 5.587 5.448 5.727 5.201 5.711 5.575 5.766
6mA
GCLK
tco
2.419
2.102 2.218 2.474 2.450 2.436 2.322 2.558 2.557
PLL
GCLK tco
4.687 5.065 5.595 5.456 5.735 5.208 5.719 5.583 5.774
1.5-V
HSTL
CLASS I
8mA
GCLK
tco
2.427
2.107 2.225 2.482 2.458 2.444 2.329 2.567 2.566
PLL
GCLK tco
4.715 5.092 5.621 5.482 5.761 5.236 5.746 5.610 5.801
10mA
12mA
GCLK
tco
2.454
2.135 2.252 2.508 2.484 2.470 2.357 2.594 2.593
PLL
GCLK tco
4.703 5.081 5.610 5.471 5.750 5.224 5.735 5.599 5.790
GCLK
tco
2.443
2.123 2.240 2.497 2.473 2.459 2.345 2.582 2.581
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–131
I/O Timing
Table 1–75. EP3SL150 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.098
1.454
3.096
1.451
3.092
1.447
3.169
1.524
3.169
1.524
3.198
1.553
3.119
1.474
3.089
1.445
3.075
1.431
3.335
1.626
3.333
1.624
3.329
1.620
3.404
1.695
3.404
1.695
3.443
1.734
3.354
1.645
3.322
1.613
3.308
1.599
4.701 5.079 5.608 5.469 5.748 5.223 5.734 5.598 5.789
1.5-V
HSTL
CLASS II
16mA
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
2.442
2.121 2.238 2.495 2.471 2.457 2.344 2.581 2.580
PLL
GCLK tco
4.700 5.079 5.608 5.469 5.748 5.222 5.734 5.598 5.788
GCLK
tco
2.442
2.120 2.238 2.495 2.471 2.457 2.343 2.581 2.580
PLL
GCLK tco
4.693 5.072 5.601 5.462 5.741 5.215 5.726 5.590 5.781
GCLK
tco
2.434
2.114 2.231 2.488 2.464 2.450 2.336 2.574 2.573
PLL
GCLK tco
4.711 5.080 5.598 5.459 5.738 5.223 5.724 5.588 5.780
1.2-V
HSTL
CLASS I
GCLK
tco
2.432
2.131 2.239 2.485 2.461 2.447 2.344 2.571 2.570
PLL
GCLK tco
4.711 5.080 5.598 5.459 5.738 5.223 5.724 5.588 5.780
GCLK
tco
2.432
2.131 2.239 2.485 2.461 2.447 2.344 2.571 2.570
PLL
GCLK tco
4.777 5.155 5.678 5.539 5.818 5.301 5.805 5.669 5.862
GCLK
tco
2.513
2.197 2.314 2.565 2.541 2.527 2.422 2.652 2.651
PLL
GCLK tco
4.673 5.043 5.561 5.422 5.701 5.185 5.685 5.549 5.742
1.2-V
HSTL
CLASS II
GCLK
tco
2.393
2.094 2.202 2.448 2.424 2.410 2.306 2.532 2.531
PLL
GCLK tco
4.606 4.973 5.491 5.352 5.631 5.115 5.618 5.482 5.674
3.0-V PCI
GCLK
tco
2.326
2.027 2.132 2.378 2.354 2.340 2.236 2.465 2.464
PLL
GCLK tco
4.585 4.950 5.463 5.324 5.603 5.089 5.584 5.448 5.640
3.0-V
PCI-X
—
GCLK
tco
2.292
2.006 2.109 2.350 2.326 2.312 2.210 2.432 2.431
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–132
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–76 specifies EP3SL150 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–76. EP3SL150 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.466
1.606
3.361
1.535
3.271
1.446
3.470
1.613
3.275
1.450
3.412
1.567
3.285
1.455
3.242
1.417
3.331
1.479
3.226
1.401
3.448
1.604
3.350
1.501
3.282
1.457
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.214
1.420
3.121
1.354
3.042
1.275
3.224
1.422
3.046
1.279
3.168
1.381
3.047
1.280
3.010
1.243
3.082
1.302
2.997
1.230
3.194
1.407
3.089
1.322
3.038
1.265
4.819 5.204 5.693 5.566 5.831 5.325 5.817 5.689 5.913
1.985 2.065 2.256 2.277 2.285 2.167 2.360 2.380 2.277
4.689 5.066 5.548 5.421 5.686 5.184 5.668 5.540 5.764
1.875 1.954 2.142 2.163 2.171 2.054 2.245 2.265 2.162
4.570 4.943 5.420 5.293 5.558 5.057 5.536 5.408 5.632
1.769 1.854 2.046 2.067 2.075 1.955 2.145 2.165 2.062
4.827 5.209 5.697 5.570 5.835 5.331 5.821 5.693 5.917
1.989 2.071 2.265 2.286 2.294 2.175 2.372 2.392 2.289
4.576 4.949 5.427 5.301 5.564 5.063 5.543 5.417 5.639
1.780 1.869 2.056 2.077 2.085 1.967 2.154 2.174 2.071
4.771 5.157 5.649 5.522 5.787 5.282 5.775 5.647 5.871
1.952 2.034 2.222 2.243 2.251 2.135 2.326 2.346 2.243
4.618 4.998 5.485 5.358 5.623 5.120 5.611 5.482 5.706
1.815 1.892 2.077 2.098 2.106 1.993 2.181 2.200 2.097
4.536 4.915 5.397 5.270 5.535 5.034 5.518 5.389 5.613
1.755 1.827 2.007 2.028 2.036 1.925 2.107 2.127 2.024
4.665 5.050 5.539 5.412 5.677 5.174 5.664 5.535 5.759
1.850 1.927 2.113 2.134 2.142 2.026 2.217 2.236 2.133
4.502 4.876 5.358 5.231 5.496 4.994 5.478 5.349 5.573
1.727 1.798 1.979 2.000 2.008 1.895 2.079 2.098 1.995
4.903 5.311 5.821 5.694 5.959 5.442 5.954 5.825 6.049
2.060 2.160 2.367 2.388 2.396 2.267 2.478 2.498 2.395
4.748 5.148 5.651 5.524 5.789 5.275 5.780 5.651 5.875
1.936 2.025 2.225 2.246 2.254 2.130 2.334 2.353 2.250
4.637 5.029 5.525 5.398 5.663 5.152 5.650 5.521 5.745
1.852 1.939 2.134 2.155 2.163 2.041 2.239 2.259 2.156
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
GCLK
PLL
3.3-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–133
I4L
Table 1–76. EP3SL150 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
1.1V
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.699
1.850
3.497
1.648
3.395
1.546
3.321
1.508
3.617
1.768
3.359
1.525
3.312
1.499
3.303
1.488
3.542
1.693
3.353
1.529
3.270
1.445
3.266
1.441
3.255
1.430
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.431
1.655
3.206
1.430
3.141
1.365
3.081
1.327
3.342
1.566
3.100
1.343
3.073
1.316
3.064
1.297
3.285
1.509
3.105
1.348
3.036
1.269
3.031
1.264
3.022
1.255
5.291 5.740 6.296 6.169 6.434 5.882 6.438 6.310 6.534
2.491 2.527 2.770 2.796 2.799 2.776 2.888 2.913 2.805
4.964 5.371 5.891 5.764 6.029 5.517 6.032 5.903 6.127
2.164 2.201 2.410 2.436 2.439 2.411 2.527 2.551 2.443
4.811 5.221 5.732 5.605 5.870 5.349 5.859 5.731 5.955
2.011 2.096 2.310 2.336 2.339 2.243 2.421 2.446 2.338
4.734 5.127 5.635 5.508 5.773 5.254 5.765 5.637 5.861
1.937 2.043 2.244 2.270 2.273 2.148 2.349 2.374 2.266
5.201 5.653 6.224 6.097 6.362 5.789 6.362 6.234 6.458
2.401 2.454 2.707 2.733 2.736 2.683 2.823 2.848 2.740
4.796 5.216 5.733 5.606 5.871 5.343 5.858 5.730 5.954
1.996 2.096 2.313 2.339 2.342 2.237 2.422 2.447 2.339
4.723 5.120 5.627 5.502 5.765 5.245 5.753 5.625 5.849
1.923 2.035 2.244 2.270 2.273 2.139 2.349 2.374 2.266
4.701 5.102 5.608 5.483 5.746 5.227 5.731 5.606 5.827
1.905 2.010 2.225 2.251 2.254 2.121 2.330 2.355 2.247
5.111 5.567 6.149 6.022 6.287 5.701 6.278 6.150 6.374
2.311 2.386 2.646 2.672 2.675 2.595 2.754 2.779 2.671
4.818 5.244 5.774 5.647 5.912 5.368 5.900 5.772 5.996
2.018 2.124 2.361 2.387 2.390 2.262 2.466 2.491 2.383
4.620 5.004 5.495 5.369 5.631 5.123 5.614 5.488 5.708
1.845 1.930 2.124 2.145 2.153 2.028 2.225 2.245 2.142
4.617 5.002 5.493 5.367 5.628 5.122 5.613 5.487 5.706
1.842 1.928 2.122 2.143 2.151 2.027 2.224 2.244 2.141
4.602 4.986 5.476 5.350 5.611 5.105 5.595 5.469 5.688
1.827 1.912 2.105 2.126 2.134 2.010 2.206 2.226 2.123
2mA
4mA
6mA
8mA
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
1.8 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
SSTL-2
CLASS I
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS II
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–134
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–76. EP3SL150 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.277
1.452
3.263
1.447
3.251
1.436
3.228
1.425
3.227
1.424
3.236
1.431
3.231
1.434
3.273
1.455
3.251
1.441
3.234
1.429
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.042
1.276
3.027
1.271
3.016
1.260
2.992
1.249
2.992
1.249
3.002
1.257
2.996
1.258
3.038
1.279
3.015
1.265
2.998
1.254
4.629 5.031 5.512 5.397 5.647 5.135 5.631 5.516 5.724
1.856 1.947 2.139 2.165 2.168 2.041 2.240 2.265 2.157
4.626 5.030 5.511 5.396 5.646 5.133 5.629 5.514 5.722
1.854 1.946 2.138 2.164 2.167 2.039 2.238 2.263 2.155
4.609 5.020 5.501 5.386 5.636 5.116 5.620 5.505 5.713
1.844 1.936 2.128 2.154 2.157 2.030 2.229 2.254 2.146
4.593 5.007 5.488 5.373 5.623 5.101 5.608 5.493 5.701
1.831 1.923 2.115 2.141 2.144 2.018 2.217 2.242 2.134
4.592 5.007 5.488 5.373 5.623 5.100 5.608 5.493 5.701
1.831 1.923 2.115 2.141 2.144 2.017 2.217 2.242 2.134
4.590 5.004 5.483 5.368 5.618 5.095 5.602 5.487 5.695
1.830 1.920 2.110 2.136 2.139 2.013 2.211 2.236 2.128
4.589 5.012 5.493 5.378 5.628 5.097 5.613 5.498 5.706
1.836 1.928 2.120 2.146 2.149 2.022 2.222 2.247 2.139
4.640 5.042 5.526 5.410 5.664 5.148 5.644 5.528 5.740
1.865 1.958 2.152 2.178 2.181 2.051 2.252 2.277 2.169
4.622 5.032 5.515 5.400 5.650 5.132 5.634 5.519 5.727
1.854 1.948 2.142 2.168 2.171 2.042 2.243 2.268 2.160
4.605 5.019 5.502 5.387 5.637 5.114 5.621 5.506 5.714
1.841 1.935 2.129 2.155 2.158 2.029 2.230 2.255 2.147
4mA
6mA
8mA
10mA
12mA
8mA
16mA
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-18
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–135
I4L
Table 1–76. EP3SL150 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
1.1V
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.249
1.437
3.237
1.431
3.225
1.423
3.227
1.425
3.222
1.422
3.226
1.430
3.256
1.443
3.246
1.438
3.241
1.434
3.255
1.445
3.243
1.437
3.241
1.437
3.376
1.551
3.376
1.551
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.017
1.264
3.005
1.257
2.992
1.248
2.994
1.251
2.987
1.247
2.993
1.255
3.024
1.270
3.012
1.264
3.008
1.260
3.023
1.272
3.011
1.263
3.007
1.262
3.142
1.375
3.142
1.375
4.596 5.002 5.481 5.366 5.616 5.099 5.599 5.484 5.692
1.829 1.918 2.108 2.134 2.137 2.012 2.208 2.233 2.125
4.587 5.001 5.480 5.365 5.615 5.091 5.599 5.484 5.692
1.827 1.917 2.107 2.133 2.136 2.011 2.208 2.233 2.125
4.578 4.994 5.473 5.358 5.608 5.083 5.592 5.477 5.685
1.820 1.910 2.100 2.126 2.129 2.004 2.201 2.226 2.118
4.581 4.997 5.477 5.362 5.612 5.086 5.595 5.480 5.688
1.823 1.913 2.104 2.130 2.133 2.007 2.204 2.229 2.121
4.579 5.000 5.480 5.365 5.615 5.086 5.600 5.485 5.693
1.825 1.916 2.107 2.133 2.136 2.010 2.209 2.234 2.126
4.574 4.997 5.476 5.361 5.611 5.077 5.594 5.479 5.687
1.823 1.913 2.103 2.129 2.132 2.006 2.203 2.228 2.120
4.607 5.012 5.492 5.377 5.627 5.111 5.610 5.495 5.703
1.838 1.928 2.119 2.145 2.148 2.021 2.219 2.244 2.136
4.603 5.014 5.494 5.379 5.629 5.108 5.613 5.498 5.706
1.839 1.930 2.121 2.147 2.150 2.023 2.222 2.247 2.139
4.597 5.009 5.489 5.374 5.624 5.102 5.607 5.492 5.700
1.834 1.925 2.116 2.142 2.145 2.018 2.216 2.241 2.133
4.618 5.028 5.511 5.396 5.646 5.125 5.629 5.514 5.722
1.851 1.944 2.138 2.164 2.167 2.037 2.238 2.263 2.155
4.607 5.019 5.502 5.387 5.637 5.114 5.620 5.505 5.713
1.842 1.935 2.129 2.155 2.158 2.028 2.229 2.254 2.146
4.611 5.027 5.511 5.396 5.646 5.120 5.630 5.515 5.723
1.849 1.943 2.138 2.164 2.167 2.037 2.239 2.264 2.156
4.672 5.050 5.535 5.409 5.670 5.171 5.656 5.530 5.749
1.897 1.976 2.164 2.185 2.193 2.076 2.267 2.287 2.184
4.672 5.050 5.535 5.409 5.670 5.171 5.656 5.530 5.749
1.897 1.976 2.164 2.185 2.193 2.076 2.267 2.287 2.184
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
—
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
1.5-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK tco
GCLK
tco
PLL
1.2-V
HSTL
CLASS I
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–136
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–77 through Table 1–77 show the maximum I/O timing parameters for
EP3SL150 devices for differential I/O standards.
Table 1–77 specifies EP3SL150 column pins input timing parameters for differential
I/O standards.
Table 1–77. EP3SL150 Column Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.978
1.104
0.967
-0.707
-0.978
1.104
0.967
-0.707
-0.978
1.104
0.967
-0.707
-0.794
0.913
1.151
-0.898
-0.794
0.913
1.151
-0.898
-0.802
0.921
1.143
-0.890
-0.802
0.921
1.143
-0.890
-0.814
0.933
1.131
-0.878
-1.006
1.152
1.001
-0.719
-1.006
1.152
1.001
-0.719
-1.006
1.152
1.001
-0.719
-0.829
0.967
1.178
-0.904
-0.829
0.967
1.178
-0.904
-0.841
0.979
1.166
-0.892
-0.841
0.979
1.166
-0.892
-0.852
0.990
1.155
-0.881
-1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632
1.371 1.387 1.564 1.502 1.860 1.361 1.634 1.471 1.898
1.885 2.230 2.404 2.293 2.197 2.284 2.556 2.353 2.249
-1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718
-1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632
1.371 1.387 1.564 1.502 1.860 1.361 1.634 1.471 1.898
1.885 2.230 2.404 2.293 2.197 2.284 2.556 2.353 2.249
-1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718
-1.151 -1.135 -1.286 -1.233 -1.594 -1.098 -1.339 -1.193 -1.632
1.371 1.387 1.564 1.502 1.860 1.361 1.634 1.471 1.898
1.885 2.230 2.404 2.293 2.197 2.284 2.556 2.353 2.249
-1.450 -1.735 -1.855 -1.769 -1.669 -1.780 -1.984 -1.818 -1.718
-1.228 -1.334 -1.445 -1.387 -1.743 -1.333 -1.443 -1.391 -1.786
1.416 1.546 1.677 1.610 1.964 1.554 1.684 1.621 2.007
1.808 2.031 2.245 2.139 2.048 2.049 2.266 2.155 2.095
-1.405 -1.576 -1.742 -1.661 -1.565 -1.587 -1.753 -1.668 -1.609
-1.228 -1.334 -1.445 -1.387 -1.743 -1.333 -1.443 -1.391 -1.786
1.416 1.546 1.677 1.610 1.964 1.554 1.684 1.621 2.007
1.808 2.031 2.245 2.139 2.048 2.049 2.266 2.155 2.095
-1.405 -1.576 -1.742 -1.661 -1.565 -1.587 -1.753 -1.668 -1.609
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
GCLK
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–137
I/O Timing
Table 1–77. EP3SL150 Column Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.814
0.933
1.131
-0.878
-0.802
0.921
1.143
-0.890
-0.802
0.921
1.143
-0.890
-0.814
0.933
1.131
-0.878
-0.814
0.933
1.131
-0.878
-0.821
0.940
1.124
-0.871
-0.821
0.940
1.124
-0.871
-0.852
0.990
1.155
-0.881
-0.841
0.979
1.166
-0.892
-0.841
0.979
1.166
-0.892
-0.852
0.990
1.155
-0.881
-0.852
0.990
1.155
-0.881
-0.858
0.996
1.149
-0.875
-0.858
0.996
1.149
-0.875
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594
-1.238 -1.345 -1.461 -1.403 -1.759 -1.344 -1.458 -1.406 -1.801
1.426 1.557 1.693 1.626 1.980 1.565 1.699 1.636 2.022
1.798 2.020 2.229 2.123 2.032 2.038 2.251 2.140 2.080
-1.395 -1.565 -1.726 -1.645 -1.549 -1.576 -1.738 -1.653 -1.594
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576
-1.247 -1.356 -1.480 -1.422 -1.778 -1.355 -1.476 -1.424 -1.819
1.436 1.568 1.712 1.645 1.999 1.576 1.717 1.654 2.040
1.789 2.009 2.210 2.104 2.013 2.027 2.233 2.122 2.062
-1.385 -1.554 -1.707 -1.626 -1.530 -1.565 -1.720 -1.635 -1.576
-1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815
1.449 1.576 1.715 1.648 2.003 1.583 1.717 1.653 2.041
1.777 2.004 2.210 2.102 2.014 2.023 2.238 2.124 2.066
-1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575
-1.259 -1.361 -1.480 -1.424 -1.777 -1.359 -1.471 -1.422 -1.815
1.449 1.576 1.715 1.648 2.003 1.583 1.717 1.653 2.041
1.777 2.004 2.210 2.102 2.014 2.023 2.238 2.124 2.066
-1.372 -1.546 -1.704 -1.623 -1.526 -1.558 -1.720 -1.636 -1.575
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–138
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–78 specifies EP3SL150 row pins input timing parameters for differential I/O
standards.
Table 1–78. EP3SL150 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.919
1.043
0.959
-0.698
-0.919
1.043
0.959
-0.698
-0.919
1.043
0.959
-0.698
-0.724
0.841
1.154
-0.900
-0.724
0.841
1.154
-0.900
-0.733
0.850
1.145
-0.891
-0.733
0.850
1.145
-0.891
-0.747
0.864
1.131
-0.877
-0.950
1.092
0.987
-0.708
-0.950
1.092
0.987
-0.708
-0.950
1.092
0.987
-0.708
-0.765
0.898
1.172
-0.902
-0.765
0.898
1.172
-0.902
-0.777
0.910
1.160
-0.890
-0.777
0.910
1.160
-0.890
-0.789
0.922
1.148
-0.878
-1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442
1.245 1.237 1.395 1.339 1.672 1.207 1.358 1.303 1.711
1.949 2.324 2.527 2.403 2.334 2.384 2.597 2.470 2.387
-1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853
-1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442
1.245 1.237 1.395 1.339 1.672 1.207 1.358 1.303 1.711
1.949 2.324 2.527 2.403 2.334 2.384 2.597 2.470 2.387
-1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853
-1.021 -0.981 -1.115 -1.070 -1.404 -0.940 -1.066 -1.023 -1.442
1.245 1.237 1.395 1.339 1.672 1.207 1.358 1.303 1.711
1.949 2.324 2.527 2.403 2.334 2.384 2.597 2.470 2.387
-1.513 -1.828 -1.977 -1.881 -1.804 -1.875 -2.032 -1.933 -1.853
-1.113 -1.210 -1.304 -1.254 -1.583 -1.211 -1.303 -1.255 -1.626
1.302 1.420 1.535 1.474 1.802 1.429 1.543 1.483 1.846
1.862 2.100 2.338 2.219 2.155 2.117 2.360 2.238 2.203
-1.458 -1.649 -1.837 -1.746 -1.674 -1.657 -1.847 -1.753 -1.718
-1.113 -1.210 -1.304 -1.254 -1.583 -1.211 -1.303 -1.255 -1.626
1.302 1.420 1.535 1.474 1.802 1.429 1.543 1.483 1.846
1.862 2.100 2.338 2.219 2.155 2.117 2.360 2.238 2.203
-1.458 -1.649 -1.837 -1.746 -1.674 -1.657 -1.847 -1.753 -1.718
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
GCLK
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS I
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–139
I4L
Table 1–78. EP3SL150 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
tsu
th
-0.747
0.864
-0.789
0.922
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879
DIFFERENTIAL
1.8-V
HSTL CLASS II
GCLK
PLL
ns
tsu
1.131
1.148
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170
th
tsu
th
-0.877
-0.733
0.850
1.145
-0.891
-0.733
0.850
1.145
-0.891
-0.747
0.864
1.131
-0.877
-0.747
0.864
1.131
-0.877
-0.756
0.873
1.122
-0.868
-0.756
0.873
1.122
-0.868
-0.878
-0.777
0.910
1.160
-0.890
-0.777
0.910
1.160
-0.890
-0.789
0.922
1.148
-0.878
-0.789
0.922
1.148
-0.878
-0.798
0.931
1.139
-0.869
-0.798
0.931
1.139
-0.869
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702
-1.122 -1.220 -1.320 -1.270 -1.599 -1.220 -1.319 -1.271 -1.642
1.311 1.430 1.551 1.490 1.818 1.438 1.559 1.499 1.862
1.853 2.090 2.322 2.203 2.139 2.108 2.344 2.222 2.187
-1.449 -1.639 -1.821 -1.730 -1.658 -1.648 -1.831 -1.737 -1.702
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685
-1.131 -1.230 -1.338 -1.288 -1.617 -1.231 -1.336 -1.288 -1.659
1.321 1.440 1.569 1.508 1.836 1.449 1.576 1.516 1.879
1.840 2.080 2.304 2.185 2.121 2.097 2.327 2.205 2.170
-1.437 -1.629 -1.803 -1.712 -1.640 -1.637 -1.814 -1.720 -1.685
-1.145 -1.241 -1.345 -1.296 -1.623 -1.238 -1.337 -1.291 -1.661
1.336 1.454 1.579 1.518 1.847 1.459 1.582 1.521 1.886
1.825 2.064 2.293 2.173 2.110 2.086 2.321 2.197 2.163
-1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.805 -1.711 -1.674
-1.145 -1.241 -1.345 -1.296 -1.623 -1.238 -1.337 -1.291 -1.661
1.336 1.454 1.579 1.518 1.847 1.459 1.582 1.521 1.886
1.825 2.064 2.293 2.173 2.110 2.086 2.321 2.197 2.163
-1.422 -1.611 -1.789 -1.698 -1.625 -1.623 -1.805 -1.711 -1.674
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS II
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–140
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–79 specifies EP3SL150 Column Pins Output Timing parameters for differential
I/O standards.
Table 1–79. EP3SL150 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
3.330
1.480
3.333
1.483
3.330
1.480
3.333
1.483
3.330
1.480
3.333
1.483
3.363
1.513
3.353
1.503
3.353
1.503
3.347
1.497
3.345
1.495
3.367
1.517
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.100
1.308
3.096
1.304
3.100
1.308
3.096
1.304
3.100
1.308
3.096
1.304
3.127
1.335
3.117
1.325
3.117
1.325
3.110
1.318
3.109
1.317
3.131
1.339
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
—
—
LVDS_E_1R
LVDS_E_3R
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 ns
ns
GCLK
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 ns
ns
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
4.687 5.079 5.586 5.447 5.731 5.200 5.706 5.570 5.803
1.885 1.978 2.188 2.199 2.226 2.081 2.293 2.303 2.211 ns
ns
—
RSDS_E_1R
RSDS_E_3R
GCLK
PLL
GCLK
4.734 5.134 5.648 5.509 5.793 5.259 5.772 5.636 5.869
1.932 2.033 2.250 2.261 2.288 2.140 2.359 2.369 2.277 ns
ns
—
GCLK
PLL
GCLK
4.758 5.157 5.670 5.531 5.815 5.280 5.792 5.656 5.889
1.956 2.056 2.272 2.283 2.310 2.161 2.379 2.389 2.297 ns
ns
4mA
6mA
8mA
10mA
12mA
16mA
GCLK
PLL
GCLK
4.748 5.146 5.660 5.521 5.805 5.269 5.782 5.646 5.879
1.946 2.045 2.262 2.273 2.300 2.150 2.369 2.379 2.287 ns
ns
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
4.751 5.150 5.664 5.525 5.809 5.274 5.787 5.651 5.884
1.949 2.049 2.266 2.277 2.304 2.155 2.374 2.384 2.292 ns
ns
GCLK
PLL
GCLK
4.744 5.144 5.658 5.519 5.803 5.267 5.781 5.645 5.878
1.942 2.043 2.260 2.271 2.298 2.148 2.368 2.378 2.286 ns
GCLK
PLL
GCLK
ns
ns
ns
ns
4.741 5.141 5.655 5.516 5.800 5.264 5.777 5.641 5.874
1.939 2.040 2.257 2.268 2.295 2.145 2.364 2.374 2.282
4.762 5.161 5.674 5.535 5.819 5.284 5.797 5.661 5.894
1.960 2.060 2.276 2.287 2.314 2.165 2.384 2.394 2.302
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–141
I/O Timing
Table 1–79. EP3SL150 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
3.356
1.506
3.352
1.502
3.350
1.500
3.341
1.491
3.343
1.493
3.340
1.490
3.353
1.503
3.350
1.500
3.339
1.489
3.337
1.487
3.338
1.488
3.341
1.491
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.121
1.329
3.116
1.324
3.114
1.322
3.106
1.314
3.107
1.315
3.106
1.314
3.118
1.326
3.114
1.322
3.104
1.312
3.102
1.310
3.102
1.310
3.106
1.314
4.741 5.138 5.649 5.510 5.794 5.260 5.770 5.634 5.867
1.939 2.037 2.251 2.262 2.289 2.141 2.357 2.367 2.275
4.741 5.138 5.650 5.511 5.795 5.261 5.772 5.636 5.869
1.939 2.037 2.252 2.263 2.290 2.142 2.359 2.369 2.277
4.740 5.137 5.648 5.509 5.793 5.260 5.771 5.635 5.868
1.938 2.036 2.250 2.261 2.288 2.141 2.358 2.368 2.276
4.730 5.127 5.639 5.500 5.784 5.250 5.761 5.625 5.858
1.928 2.026 2.241 2.252 2.279 2.131 2.348 2.358 2.266
4.736 5.134 5.647 5.508 5.792 5.258 5.770 5.634 5.867
1.934 2.033 2.249 2.260 2.287 2.139 2.357 2.367 2.275
4.719 5.115 5.625 5.486 5.770 5.237 5.746 5.610 5.843
1.917 2.014 2.227 2.238 2.265 2.118 2.333 2.343 2.251
4.737 5.133 5.643 5.504 5.788 5.256 5.765 5.629 5.862
1.935 2.032 2.245 2.256 2.283 2.137 2.352 2.362 2.270
4.738 5.135 5.647 5.508 5.792 5.258 5.769 5.633 5.866
1.936 2.034 2.249 2.260 2.287 2.139 2.356 2.366 2.274
4.727 5.124 5.635 5.496 5.780 5.247 5.757 5.621 5.854
1.925 2.023 2.237 2.248 2.275 2.128 2.344 2.354 2.262
4mA
6mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
4.725 5.121 5.633 5.494 5.778 5.245 5.755 5.619 5.852 ns
ns
10mA
12mA
16mA
GCLK
PLL
1.923 2.020 2.235 2.246 2.273 2.126 2.342 2.352 2.260
4.728 5.126 5.638 5.499 5.783 5.249 5.761 5.625 5.858 ns
ns
GCLK
GCLK
PLL
1.926 2.025 2.240 2.251 2.278 2.130 2.348 2.358 2.266
4.725 5.121 5.632 5.493 5.777 5.244 5.754 5.618 5.851 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
GCLK
PLL
ns
1.923 2.020 2.234 2.245 2.272 2.125 2.341 2.351 2.259
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–142
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–79. EP3SL150 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
3.370
1.520
3.356
1.506
3.343
1.493
3.343
1.493
3.339
1.489
3.341
1.491
3.343
1.493
3.373
1.523
3.361
1.511
3.357
1.507
3.342
1.492
3.340
1.490
3.342
1.492
3.343
1.493
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.132
1.340
3.118
1.326
3.106
1.314
3.106
1.314
3.102
1.310
3.106
1.314
3.107
1.315
3.135
1.343
3.124
1.332
3.119
1.327
3.105
1.313
3.103
1.311
3.107
1.315
3.107
1.315
4.770 5.169 5.682 5.543 5.827 5.292 5.804 5.668 5.901
1.968 2.068 2.284 2.295 2.322 2.173 2.391 2.401 2.309
4.758 5.158 5.672 5.533 5.817 5.282 5.795 5.659 5.892
1.956 2.057 2.274 2.285 2.312 2.163 2.382 2.392 2.300
4.741 5.140 5.654 5.515 5.799 5.264 5.777 5.641 5.874
1.939 2.039 2.256 2.267 2.294 2.145 2.364 2.374 2.282
4.744 5.144 5.658 5.519 5.803 5.268 5.782 5.646 5.879
1.942 2.043 2.260 2.271 2.298 2.149 2.369 2.379 2.287
4.737 5.136 5.651 5.512 5.796 5.261 5.774 5.638 5.871
1.935 2.035 2.253 2.264 2.291 2.142 2.361 2.371 2.279
4.730 5.127 5.639 5.500 5.784 5.250 5.761 5.625 5.858
1.928 2.026 2.241 2.252 2.279 2.131 2.348 2.358 2.266
4.738 5.137 5.650 5.511 5.795 5.260 5.773 5.637 5.870
1.936 2.036 2.252 2.263 2.290 2.141 2.360 2.370 2.278
4.769 5.167 5.680 5.541 5.825 5.291 5.802 5.666 5.899
1.967 2.066 2.282 2.293 2.320 2.172 2.389 2.399 2.307
4.757 5.155 5.668 5.529 5.813 5.279 5.790 5.654 5.887
1.955 2.054 2.270 2.281 2.308 2.160 2.377 2.387 2.295
4mA
6mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
4.757 5.156 5.669 5.530 5.814 5.280 5.792 5.656 5.889 ns
ns
8mA
GCLK
PLL
1.955 2.055 2.271 2.282 2.309 2.161 2.379 2.389 2.297
4.739 5.137 5.650 5.511 5.795 5.261 5.774 5.638 5.871 ns
ns
GCLK
10mA
12mA
8mA
GCLK
PLL
1.937 2.036 2.252 2.263 2.290 2.142 2.361 2.371 2.279
4.737 5.135 5.648 5.509 5.793 5.259 5.771 5.635 5.868 ns
ns
GCLK
GCLK
PLL
1.935 2.034 2.250 2.261 2.288 2.140 2.358 2.368 2.276
4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855 ns
ns
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263
4.737 5.135 5.648 5.509 5.793 5.259 5.771 5.635 5.868 ns
GCLK
16mA
GCLK
PLL
ns
1.935 2.034 2.250 2.261 2.288 2.140 2.358 2.368 2.276
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–143
I/O Timing
Table 1–79. EP3SL150 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
3.360
1.510
3.360
1.510
3.350
1.500
3.342
1.492
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.123
1.331
3.123
1.331
3.113
1.321
3.106
1.314
4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881
1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289
4.753 5.150 5.662 5.523 5.807 5.274 5.784 5.648 5.881
1.951 2.049 2.264 2.275 2.302 2.155 2.371 2.381 2.289
4.743 5.140 5.652 5.513 5.797 5.264 5.775 5.639 5.872
1.941 2.039 2.254 2.265 2.292 2.145 2.362 2.372 2.280
4.729 5.125 5.636 5.497 5.781 5.248 5.758 5.622 5.855
1.927 2.024 2.238 2.249 2.276 2.129 2.345 2.355 2.263
8mA
10mA
12mA
16mA
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–144
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–80 specifies EP3SL150 Row Pins Output Timing parameters for differential
I/O standards.
Table 1–80. EP3SL150 Row Pins output Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
LVDS
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
2.711
0.934
3.106
1.326
3.088
1.308
2.711
0.934
3.106
1.326
3.088
1.308
2.711
0.934
3.106
1.326
3.088
1.308
3.132
1.352
3.118
1.338
3.114
1.334
2.894
1.059
3.342
1.503
3.332
1.493
2.894
1.059
3.342
1.503
3.332
1.493
2.894
1.059
3.342
1.503
3.332
1.493
3.375
1.536
3.361
1.522
3.357
1.518
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283
4.033 4.387 4.843 4.717 4.978 4.486 4.943 4.816 5.035
1.248 1.300 1.459 1.480 1.491 1.379 1.542 1.561 1.459
4.709 5.107 5.611 5.475 5.730 5.229 5.736 5.599 5.802
1.919 2.016 2.222 2.235 2.238 2.120 2.330 2.340 2.222
4.747 5.153 5.665 5.529 5.784 5.280 5.797 5.660 5.863
1.957 2.062 2.276 2.289 2.292 2.171 2.391 2.401 2.283
4.783 5.187 5.698 5.562 5.817 5.313 5.826 5.689 5.892
1.993 2.096 2.309 2.322 2.325 2.204 2.420 2.430 2.312
4.770 5.174 5.685 5.549 5.804 5.299 5.813 5.676 5.879
1.980 2.083 2.296 2.309 2.312 2.190 2.407 2.417 2.299
4.768 5.174 5.686 5.550 5.805 5.299 5.815 5.678 5.881
1.978 2.083 2.297 2.310 2.313 2.190 2.409 2.419 2.301
—
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
—
GCLK
tco
PLL
GCLK tco
RSDS
—
GCLK
tco
PLL
GCLK tco
RSDS_E_1R
RSDS_E_3R
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–145
I/O Timing
Table 1–80. EP3SL150 Row Pins output Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.130
1.350
3.119
1.339
3.116
1.336
3.127
1.347
3.117
1.337
3.103
1.323
3.100
1.320
3.097
1.317
3.098
1.318
3.147
1.367
3.123
1.343
3.106
1.326
3.372
1.533
3.362
1.523
3.359
1.520
3.369
1.530
3.360
1.521
3.346
1.507
3.342
1.503
3.340
1.501
3.340
1.501
3.393
1.554
3.369
1.530
3.350
1.511
4.769 5.171 5.680 5.544 5.799 5.296 5.808 5.671 5.874
1.979 2.080 2.291 2.304 2.307 2.187 2.402 2.412 2.294
4.765 5.167 5.677 5.541 5.796 5.293 5.805 5.668 5.871
1.975 2.076 2.288 2.301 2.304 2.184 2.399 2.409 2.291
4.763 5.165 5.675 5.539 5.794 5.291 5.804 5.667 5.870
1.973 2.074 2.286 2.299 2.302 2.182 2.398 2.408 2.290
4.764 5.166 5.674 5.538 5.793 5.291 5.802 5.665 5.868
1.974 2.075 2.285 2.298 2.301 2.182 2.396 2.406 2.288
4.762 5.164 5.673 5.537 5.792 5.290 5.802 5.665 5.868
1.972 2.073 2.284 2.297 2.300 2.181 2.396 2.406 2.288
4.747 5.149 5.659 5.523 5.778 5.275 5.787 5.650 5.853
1.957 2.058 2.270 2.283 2.286 2.166 2.381 2.391 2.273
4.743 5.145 5.655 5.519 5.774 5.271 5.783 5.646 5.849
1.953 2.054 2.266 2.279 2.282 2.162 2.377 2.387 2.269
4.744 5.148 5.658 5.522 5.777 5.274 5.787 5.650 5.853
1.954 2.057 2.269 2.282 2.285 2.165 2.381 2.391 2.273
4.734 5.136 5.645 5.509 5.764 5.261 5.773 5.636 5.839
1.944 2.045 2.256 2.269 2.272 2.152 2.367 2.377 2.259
4.805 5.209 5.721 5.585 5.840 5.335 5.849 5.712 5.915
2.015 2.118 2.332 2.345 2.348 2.226 2.443 2.453 2.335
4.787 5.192 5.704 5.568 5.823 5.318 5.834 5.697 5.900
1.997 2.101 2.315 2.328 2.331 2.209 2.428 2.438 2.320
4.765 5.170 5.682 5.546 5.801 5.296 5.812 5.675 5.878
1.975 2.079 2.293 2.306 2.309 2.187 2.406 2.416 2.298
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–146
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–80. EP3SL150 Row Pins output Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.151
1.371
3.136
1.356
3.125
1.345
3.105
1.325
3.102
1.322
3.107
1.327
3.100
1.320
3.138
1.358
3.120
1.340
3.106
1.326
3.396
1.557
3.381
1.542
3.370
1.531
3.350
1.511
3.346
1.507
3.350
1.511
3.343
1.504
3.382
1.543
3.365
1.526
3.349
1.510
4.805 5.209 5.720 5.584 5.839 5.335 5.849 5.712 5.915
2.015 2.118 2.331 2.344 2.347 2.226 2.443 2.453 2.335
4.791 5.194 5.705 5.569 5.824 5.320 5.834 5.697 5.900
2.001 2.103 2.316 2.329 2.332 2.211 2.428 2.438 2.320
4.786 5.191 5.702 5.566 5.821 5.317 5.832 5.695 5.898
1.996 2.100 2.313 2.326 2.329 2.208 2.426 2.436 2.318
4.763 5.167 5.679 5.543 5.798 5.294 5.808 5.671 5.874
1.973 2.076 2.290 2.303 2.306 2.185 2.402 2.412 2.294
4.759 5.164 5.675 5.539 5.794 5.290 5.805 5.668 5.871
1.969 2.073 2.286 2.299 2.302 2.181 2.399 2.409 2.291
4.750 5.152 5.661 5.525 5.780 5.277 5.789 5.652 5.855
1.960 2.061 2.272 2.285 2.288 2.168 2.383 2.393 2.275
4.749 5.153 5.664 5.528 5.783 5.280 5.794 5.657 5.860
1.959 2.062 2.275 2.288 2.291 2.171 2.388 2.398 2.280
4.787 5.190 5.700 5.564 5.819 5.316 5.829 5.692 5.895
1.997 2.099 2.311 2.324 2.327 2.207 2.423 2.433 2.315
4.772 5.175 5.685 5.549 5.804 5.301 5.814 5.677 5.880
1.982 2.084 2.296 2.309 2.312 2.192 2.408 2.418 2.300
4.749 5.151 5.660 5.524 5.779 5.277 5.789 5.652 5.855
1.959 2.060 2.271 2.284 2.287 2.168 2.383 2.393 2.275
4mA
6mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
16mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Table 1–81 and Table 1–82 show EP3SL150 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
Table 1–81 specifies EP3SL150 Column Pin delay adders when using the regional
clock.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–147
I/O Timing
Table 1–81. EP3SL150 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
ns
ns
ns
ns
0.198
2.453
-0.374
-2.017
0.152
2.426
-0.152
-1.798
0.22
0.258
0.27
0.262 0.393 0.244 0.271 0.261 0.495
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.654 4.098 4.422 4.224 4.664 4.106 4.447 4.101 4.707
-0.216 -0.232 -0.248 -0.227 -0.367 -0.11 -0.127 -0.106 -0.303
-2.68 -2.859 -3.011 -2.872 -2.715 -2.714 -3.082 -2.791 -2.766
Table 1–82 specifies EP3SL150 Row Pin delay adders when using the regional clock.
Table 1–82. EP3SL150 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
RCLK input adder
0.107
0.074
-0.093
-0.063
0.115
0.075
-0.103
-0.065
0.164 0.165 0.167 0.165 0.285 0.158 0.159 0.158 0.29
0.116 0.123 0.129 0.126 0.218 0.114 0.118 0.114 0.223
-0.137 -0.136 -0.133 -0.134 -0.257 -0.125 -0.121 -0.122 -0.261
-0.097 -0.102 -0.103 -0.102 -0.198 -0.088 -0.089 -0.088 -0.202
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
EP3SL200 I/O Timing Parameters
Table 1–83 through Table 1–86 show the maximum I/O timing parameters for
EP3SL200 devices for single-ended I/O standards.
Table 1–83 specifies EP3SL200 column pins input timing parameters for single-ended
I/O standards.
Table 1–83. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.222
1.356
0.710
-0.440
-1.222
1.356
0.710
-0.440
-1.228
1.362
0.704
-0.434
-1.283
1.436
0.726
-0.435
-1.283
1.436
0.726
-0.435
-1.294
1.447
0.715
-0.424
-1.958 -2.003 -2.310 -2.232 -2.701 -2.026 -2.284 -2.244 -2.703 ns
GCLK
2.194 2.245 2.576 2.483 2.958 2.278 2.560 2.505 2.961
1.290 1.374 1.412 1.311 1.322 1.373 1.519 1.320 1.381
ns
ns
3.3-V
LVTTL
tsu
th
GCLK
PLL
-0.824 -0.891 -0.876 -0.806 -0.797 -0.879 -0.967 -0.806 -0.853 ns
-1.958 -2.003 -2.310 -2.232 -2.701 -2.026 -2.284 -2.244 -2.703 ns
tsu
th
GCLK
2.194 2.245 2.576 2.483 2.958 2.278 2.560 2.505 2.961
1.290 1.374 1.412 1.311 1.322 1.373 1.519 1.320 1.381
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-0.824 -0.891 -0.876 -0.806 -0.797 -0.879 -0.967 -0.806 -0.853 ns
-1.957 -2.005 -2.309 -2.231 -2.700 -2.026 -2.289 -2.249 -2.708 ns
tsu
th
GCLK
2.193 2.247 2.575 2.482 2.957 2.278 2.565 2.510 2.966
1.291 1.372 1.413 1.312 1.323 1.373 1.514 1.315 1.376
ns
ns
3.0-V
LVTTL
tsu
th
GCLK
PLL
-0.825 -0.889 -0.877 -0.807 -0.798 -0.879 -0.962 -0.801 -0.848 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–148
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–83. EP3SL200 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.228
1.362
0.704
-0.434
-1.218
1.352
0.714
-0.444
-1.234
1.370
0.696
-0.424
-1.227
1.363
0.703
-0.431
-1.167
1.303
0.763
-0.491
-1.148
1.284
0.782
-0.510
-1.148
1.284
0.782
-0.510
-1.141
1.277
0.789
-0.517
-1.141
1.277
0.789
-0.517
-1.294
1.447
0.715
-0.424
-1.289
1.442
0.720
-0.429
-1.309
1.464
0.698
-0.405
-1.299
1.454
0.708
-0.415
-1.247
1.402
0.760
-0.467
-1.218
1.373
0.789
-0.496
-1.218
1.373
0.789
-0.496
-1.212
1.367
0.795
-0.502
-1.212
1.367
0.795
-0.502
-1.957 -2.005 -2.309 -2.231 -2.700 -2.026 -2.289 -2.249 -2.708 ns
GCLK
2.193 2.247 2.575 2.482 2.957 2.278 2.565 2.510 2.966
1.291 1.372 1.413 1.312 1.323 1.373 1.514 1.315 1.376
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-0.825 -0.889 -0.877 -0.807 -0.798 -0.879 -0.962 -0.801 -0.848 ns
-1.966 -2.017 -2.328 -2.250 -2.719 -2.036 -2.300 -2.260 -2.719 ns
tsu
th
GCLK
2.202 2.259 2.594 2.501 2.976 2.288 2.576 2.521 2.977
1.282 1.360 1.394 1.293 1.304 1.363 1.503 1.304 1.365
ns
ns
2.5 V
tsu
th
GCLK
PLL
-0.816 -0.877 -0.858 -0.788 -0.779 -0.869 -0.951 -0.790 -0.837 ns
-2.006 -2.053 -2.326 -2.248 -2.717 -2.070 -2.303 -2.263 -2.722 ns
tsu
th
GCLK
2.242 2.295 2.592 2.499 2.974 2.322 2.579 2.524 2.980
1.242 1.324 1.396 1.295 1.306 1.329 1.500 1.301 1.362
ns
ns
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
-0.776 -0.841 -0.860 -0.790 -0.781 -0.835 -0.948 -0.787 -0.834 ns
-1.983 -2.021 -2.256 -2.178 -2.647 -2.039 -2.237 -2.197 -2.656 ns
tsu
th
GCLK
2.219 2.263 2.522 2.429 2.904 2.291 2.513 2.458 2.914
1.265 1.356 1.466 1.365 1.376 1.360 1.566 1.367 1.428
ns
ns
tsu
th
GCLK
PLL
-0.799 -0.873 -0.930 -0.860 -0.851 -0.866 -1.014 -0.853 -0.900 ns
-1.906 -1.922 -2.100 -2.022 -2.491 -1.943 -2.084 -2.044 -2.503 ns
tsu
th
GCLK
2.142 2.164 2.366 2.273 2.748 2.195 2.360 2.305 2.761
1.342 1.455 1.622 1.521 1.532 1.456 1.719 1.520 1.581
ns
ns
tsu
th
GCLK
PLL
-0.876 -0.972 -1.086 -1.016 -1.007 -0.962 -1.167 -1.006 -1.053 ns
-1.878 -1.906 -2.102 -2.024 -2.493 -1.922 -2.080 -2.040 -2.499 ns
tsu
th
GCLK
2.114 2.148 2.368 2.275 2.750 2.174 2.356 2.301 2.757
1.370 1.471 1.620 1.519 1.530 1.477 1.723 1.524 1.585
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-0.904 -0.988 -1.084 -1.014 -1.005 -0.983 -1.171 -1.010 -1.057 ns
-1.878 -1.906 -2.102 -2.024 -2.493 -1.922 -2.080 -2.040 -2.499 ns
tsu
th
GCLK
2.114 2.148 2.368 2.275 2.750 2.174 2.356 2.301 2.757
1.370 1.471 1.620 1.519 1.530 1.477 1.723 1.524 1.585
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-0.904 -0.988 -1.084 -1.014 -1.005 -0.983 -1.171 -1.010 -1.057 ns
-1.866 -1.901 -2.102 -2.022 -2.494 -1.918 -2.085 -2.042 -2.503 ns
tsu
th
GCLK
2.101 2.140 2.365 2.272 2.746 2.167 2.356 2.302 2.756
1.383 1.479 1.623 1.524 1.532 1.484 1.718 1.525 1.584
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-0.917 -0.999 -1.090 -1.020 -1.012 -0.993 -1.171 -1.012 -1.061 ns
-1.866 -1.901 -2.102 -2.022 -2.494 -1.918 -2.085 -2.042 -2.503 ns
tsu
th
GCLK
2.101 2.140 2.365 2.272 2.746 2.167 2.356 2.302 2.756
1.383 1.479 1.623 1.524 1.532 1.484 1.718 1.525 1.584
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-0.917 -0.999 -1.090 -1.020 -1.012 -0.993 -1.171 -1.012 -1.061 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–149
I/O Timing
Table 1–83. EP3SL200 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.129
1.265
0.801
-0.529
-1.129
1.265
0.801
-0.529
-1.141
1.277
0.789
-0.517
-1.141
1.277
0.789
-0.517
-1.129
1.265
0.801
-0.529
-1.129
1.265
0.801
-0.529
-1.121
1.257
0.809
-0.537
-1.121
1.257
0.809
-0.537
-1.228
1.362
0.704
-0.434
-1.201
1.356
0.806
-0.513
-1.201
1.356
0.806
-0.513
-1.212
1.367
0.795
-0.502
-1.212
1.367
0.795
-0.502
-1.201
1.356
0.806
-0.513
-1.201
1.356
0.806
-0.513
-1.189
1.344
0.818
-0.525
-1.189
1.344
0.818
-0.525
-1.294
1.447
0.715
-0.424
-1.857 -1.890 -2.083 -2.003 -2.475 -1.907 -2.067 -2.024 -2.485 ns
GCLK
2.092 2.129 2.346 2.253 2.727 2.156 2.338 2.284 2.738
1.394 1.490 1.642 1.543 1.551 1.495 1.736 1.543 1.602
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-0.929 -1.010 -1.109 -1.039 -1.031 -1.004 -1.189 -1.030 -1.079 ns
-1.857 -1.890 -2.083 -2.003 -2.475 -1.907 -2.067 -2.024 -2.485 ns
tsu
th
GCLK
2.092 2.129 2.346 2.253 2.727 2.156 2.338 2.284 2.738
1.394 1.490 1.642 1.543 1.551 1.495 1.736 1.543 1.602
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.929 -1.010 -1.109 -1.039 -1.031 -1.004 -1.189 -1.030 -1.079 ns
-1.866 -1.901 -2.102 -2.022 -2.494 -1.918 -2.085 -2.042 -2.503 ns
tsu
th
GCLK
2.101 2.140 2.365 2.272 2.746 2.167 2.356 2.302 2.756
1.383 1.479 1.623 1.524 1.532 1.484 1.718 1.525 1.584
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.917 -0.999 -1.090 -1.020 -1.012 -0.993 -1.171 -1.012 -1.061 ns
-1.866 -1.901 -2.102 -2.022 -2.494 -1.918 -2.085 -2.042 -2.503 ns
tsu
th
GCLK
2.101 2.140 2.365 2.272 2.746 2.167 2.356 2.302 2.756
1.383 1.479 1.623 1.524 1.532 1.484 1.718 1.525 1.584
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.917 -0.999 -1.090 -1.020 -1.012 -0.993 -1.171 -1.012 -1.061 ns
-1.857 -1.890 -2.083 -2.003 -2.475 -1.907 -2.067 -2.024 -2.485 ns
tsu
th
GCLK
2.092 2.129 2.346 2.253 2.727 2.156 2.338 2.284 2.738
1.394 1.490 1.642 1.543 1.551 1.495 1.736 1.543 1.602
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.929 -1.010 -1.109 -1.039 -1.031 -1.004 -1.189 -1.030 -1.079 ns
-1.857 -1.890 -2.083 -2.003 -2.475 -1.907 -2.067 -2.024 -2.485 ns
tsu
th
GCLK
2.092 2.129 2.346 2.253 2.727 2.156 2.338 2.284 2.738
1.394 1.490 1.642 1.543 1.551 1.495 1.736 1.543 1.602
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.929 -1.010 -1.109 -1.039 -1.031 -1.004 -1.189 -1.030 -1.079 ns
-1.847 -1.879 -2.067 -1.987 -2.459 -1.896 -2.052 -2.009 -2.470 ns
tsu
th
GCLK
2.082 2.118 2.330 2.237 2.711 2.145 2.323 2.269 2.723
1.404 1.501 1.658 1.559 1.567 1.506 1.751 1.558 1.617
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.939 -1.021 -1.125 -1.055 -1.047 -1.015 -1.204 -1.045 -1.094 ns
-1.847 -1.879 -2.067 -1.987 -2.459 -1.896 -2.052 -2.009 -2.470 ns
tsu
th
GCLK
2.082 2.118 2.330 2.237 2.711 2.145 2.323 2.269 2.723
1.404 1.501 1.658 1.559 1.567 1.506 1.751 1.558 1.617
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-0.939 -1.021 -1.125 -1.055 -1.047 -1.015 -1.204 -1.045 -1.094 ns
-1.957 -2.005 -2.309 -2.231 -2.700 -2.026 -2.289 -2.249 -2.708 ns
tsu
th
GCLK
2.193 2.247 2.575 2.482 2.957 2.278 2.565 2.510 2.966
1.291 1.372 1.413 1.312 1.323 1.373 1.514 1.315 1.376
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-0.825 -0.889 -0.877 -0.807 -0.798 -0.879 -0.962 -0.801 -0.848 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–150
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–84 specifies EP3SL200 row pins input timing parameters for single-ended
I/O standards.
Table 1–84. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.298
1.432
0.915
-0.638
-1.298
1.432
0.915
-0.638
-1.304
1.438
0.909
-0.632
-1.304
1.438
0.909
-0.632
-1.292
1.426
0.921
-0.644
-1.322
1.457
0.891
-0.613
-1.312
1.447
0.901
-0.623
-1.252
1.387
0.961
-0.683
-1.321
1.473
0.938
-0.643
-1.321
1.473
0.938
-0.643
-1.332
1.484
0.927
-0.632
-1.332
1.484
0.927
-0.632
-1.325
1.477
0.934
-0.639
-1.354
1.507
0.902
-0.606
-1.343
1.496
0.913
-0.617
-1.290
1.443
0.966
-0.670
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
2.210 2.223 2.633 2.541 2.966 2.384 2.665 2.541 2.966
1.671 1.862 1.969 1.850 1.775 1.751 1.869 1.850 1.775
-1.193 -1.362 -1.413 -1.326 -1.239 -1.241 -1.304 -1.326 -1.239
-1.972 -1.978 -2.368 -2.291 -2.712 -2.132 -2.388 -2.291 -2.712
2.210 2.223 2.633 2.541 2.966 2.384 2.665 2.541 2.966
1.671 1.862 1.969 1.850 1.775 1.751 1.869 1.850 1.775
-1.193 -1.362 -1.413 -1.326 -1.239 -1.241 -1.304 -1.326 -1.239
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
2.207 2.224 2.636 2.544 2.969 2.383 2.670 2.544 2.969
1.674 1.861 1.966 1.847 1.772 1.752 1.864 1.847 1.772
-1.196 -1.361 -1.410 -1.323 -1.236 -1.242 -1.299 -1.323 -1.236
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
2.207 2.224 2.636 2.544 2.969 2.383 2.670 2.544 2.969
1.674 1.861 1.966 1.847 1.772 1.752 1.864 1.847 1.772
-1.196 -1.361 -1.410 -1.323 -1.236 -1.242 -1.299 -1.323 -1.236
-1.978 -1.992 -2.386 -2.309 -2.730 -2.140 -2.403 -2.309 -2.730
2.216 2.237 2.651 2.559 2.984 2.392 2.680 2.559 2.984
1.665 1.848 1.951 1.832 1.757 1.743 1.854 1.832 1.757
-1.187 -1.348 -1.395 -1.308 -1.221 -1.233 -1.289 -1.308 -1.221
-2.017 -2.051 -2.384 -2.307 -2.728 -2.173 -2.404 -2.307 -2.728
2.254 2.297 2.649 2.557 2.982 2.425 2.681 2.557 2.982
1.625 1.722 1.945 1.834 1.742 1.710 1.853 1.834 1.742
-1.147 -1.225 -1.388 -1.310 -1.206 -1.200 -1.288 -1.310 -1.206
-1.993 -2.019 -2.316 -2.239 -2.660 -2.142 -2.339 -2.239 -2.660
2.230 2.265 2.581 2.489 2.914 2.394 2.616 2.489 2.914
1.649 1.754 2.013 1.902 1.810 1.741 1.918 1.902 1.810
-1.171 -1.257 -1.456 -1.378 -1.274 -1.231 -1.353 -1.378 -1.274
-1.914 -1.918 -2.157 -2.080 -2.501 -2.046 -2.184 -2.080 -2.501
2.151 2.164 2.422 2.330 2.755 2.298 2.461 2.330 2.755
1.728 1.855 2.172 2.061 1.969 1.837 2.073 2.061 1.969
-1.250 -1.358 -1.615 -1.537 -1.433 -1.327 -1.508 -1.537 -1.433
GCLK
3.3-V
LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–151
I/O Timing
Table 1–84. EP3SL200 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.235
1.370
0.978
-0.700
-1.235
1.370
0.978
-0.700
-1.226
1.361
0.987
-0.709
-1.226
1.361
0.987
-0.709
-1.212
1.347
1.001
-0.723
-1.226
1.361
0.987
-0.709
-1.226
1.361
0.987
-0.709
-1.212
1.347
1.001
-0.723
-1.212
1.347
1.001
-0.723
-1.266
1.419
0.992
-0.696
-1.266
1.419
0.992
-0.696
-1.255
1.408
1.001
-0.705
-1.255
1.408
1.001
-0.705
-1.243
1.396
1.013
-0.717
-1.255
1.408
1.001
-0.705
-1.255
1.408
1.001
-0.705
-1.243
1.396
1.013
-0.717
-1.243
1.396
1.013
-0.717
-1.892 -1.883 -2.166 -2.089 -2.510 -2.028 -2.186 -2.089 -2.510
2.130 2.128 2.431 2.339 2.764 2.280 2.463 2.339 2.764
1.751 1.957 2.171 2.052 1.977 1.855 2.071 2.052 1.977
-1.273 -1.457 -1.615 -1.528 -1.441 -1.345 -1.506 -1.528 -1.441
-1.892 -1.883 -2.166 -2.089 -2.510 -2.028 -2.186 -2.089 -2.510
2.130 2.128 2.431 2.339 2.764 2.280 2.463 2.339 2.764
1.751 1.957 2.171 2.052 1.977 1.855 2.071 2.052 1.977
-1.273 -1.457 -1.615 -1.528 -1.441 -1.345 -1.506 -1.528 -1.441
-1.876 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497
2.113 2.137 2.415 2.323 2.747 2.264 2.451 2.323 2.747
1.766 1.882 2.174 2.064 1.973 1.869 2.080 2.064 1.973
-1.288 -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441
-1.876 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497
2.113 2.137 2.415 2.323 2.747 2.264 2.451 2.323 2.747
1.766 1.882 2.174 2.064 1.973 1.869 2.080 2.064 1.973
-1.288 -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441
-1.863 -1.883 -2.134 -2.056 -2.479 -2.003 -2.160 -2.056 -2.479
2.101 2.127 2.397 2.305 2.729 2.253 2.434 2.305 2.729
1.781 1.892 2.192 2.082 1.991 1.880 2.097 2.082 1.991
-1.302 -1.397 -1.638 -1.560 -1.459 -1.372 -1.535 -1.560 -1.459
-1.876 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497
2.113 2.137 2.415 2.323 2.747 2.264 2.451 2.323 2.747
1.766 1.882 2.174 2.064 1.973 1.869 2.080 2.064 1.973
-1.288 -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441
-1.876 -1.893 -2.152 -2.074 -2.497 -2.014 -2.177 -2.074 -2.497
2.113 2.137 2.415 2.323 2.747 2.264 2.451 2.323 2.747
1.766 1.882 2.174 2.064 1.973 1.869 2.080 2.064 1.973
-1.288 -1.387 -1.620 -1.542 -1.441 -1.361 -1.518 -1.542 -1.441
-1.863 -1.883 -2.134 -2.056 -2.479 -2.003 -2.160 -2.056 -2.479
2.101 2.127 2.397 2.305 2.729 2.253 2.434 2.305 2.729
1.781 1.892 2.192 2.082 1.991 1.880 2.097 2.082 1.991
-1.302 -1.397 -1.638 -1.560 -1.459 -1.372 -1.535 -1.560 -1.459
-1.863 -1.883 -2.134 -2.056 -2.479 -2.003 -2.160 -2.056 -2.479
2.101 2.127 2.397 2.305 2.729 2.253 2.434 2.305 2.729
1.781 1.892 2.192 2.082 1.991 1.880 2.097 2.082 1.991
-1.302 -1.397 -1.638 -1.560 -1.459 -1.372 -1.535 -1.560 -1.459
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-15
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–152
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–84. EP3SL200 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.203
1.338
1.010
-0.732
-1.203
1.338
1.010
-0.732
-1.304
1.438
0.909
-0.632
-1.304
1.438
0.909
-0.632
-1.231
1.384
1.025
-0.729
-1.231
1.384
1.025
-0.729
-1.332
1.484
0.927
-0.632
-1.332
1.484
0.927
-0.632
-1.854 -1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463
2.092 2.117 2.381 2.289 2.713 2.244 2.418 2.289 2.713
1.790 1.902 2.208 2.098 2.007 1.889 2.113 2.098 2.007
-1.311 -1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475
-1.854 -1.873 -2.118 -2.040 -2.463 -1.994 -2.144 -2.040 -2.463
2.092 2.117 2.381 2.289 2.713 2.244 2.418 2.289 2.713
1.790 1.902 2.208 2.098 2.007 1.889 2.113 2.098 2.007
-1.311 -1.407 -1.654 -1.576 -1.475 -1.381 -1.551 -1.576 -1.475
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
2.207 2.224 2.636 2.544 2.969 2.383 2.670 2.544 2.969
1.674 1.861 1.966 1.847 1.772 1.752 1.864 1.847 1.772
-1.196 -1.361 -1.410 -1.323 -1.236 -1.242 -1.299 -1.323 -1.236
-1.969 -1.979 -2.371 -2.294 -2.715 -2.131 -2.393 -2.294 -2.715
2.207 2.224 2.636 2.544 2.969 2.383 2.670 2.544 2.969
1.674 1.861 1.966 1.847 1.772 1.752 1.864 1.847 1.772
-1.196 -1.361 -1.410 -1.323 -1.236 -1.242 -1.299 -1.323 -1.236
GCLK
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
PCI-X
tsu
th
GCLK
PLL
Table 1–85 specifies EP3SL200 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–85. EP3SL200 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.475
1.631
3.396
1.552
3.366
1.522
3.352
1.508
3.747
1.820
3.658
1.731
3.626
1.699
3.612
1.685
5.436 5.640 6.177 6.023 6.436 5.779 6.315 6.162 6.514
2.330 2.414 2.639 2.650 2.757 2.526 2.726 2.748 2.598
5.332 5.528 6.060 5.906 6.319 5.663 6.195 6.042 6.394
2.226 2.302 2.522 2.533 2.589 2.410 2.606 2.628 2.478
5.265 5.458 5.990 5.836 6.249 5.593 6.128 5.975 6.327
2.159 2.232 2.452 2.463 2.489 2.340 2.539 2.561 2.411
5.244 5.435 5.962 5.808 6.221 5.567 6.094 5.941 6.293
2.138 2.209 2.424 2.435 2.446 2.314 2.506 2.528 2.378
4mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
3.3-V
LVTTL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–153
I/O Timing
Table 1–85. EP3SL200 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.412
1.568
3.341
1.497
3.317
1.473
3.310
1.466
3.472
1.628
3.405
1.561
3.367
1.523
3.345
1.501
3.427
1.583
3.354
1.510
3.330
1.486
3.330
1.486
3.680
1.753
3.603
1.676
3.575
1.648
3.568
1.641
3.756
1.829
3.671
1.744
3.634
1.707
3.607
1.680
3.696
1.769
3.617
1.690
3.588
1.661
3.588
1.661
5.363 5.557 6.089 5.935 6.348 5.693 6.227 6.074 6.426
2.257 2.331 2.552 2.562 2.635 2.440 2.638 2.660 2.510
5.241 5.431 5.958 5.804 6.217 5.563 6.090 5.937 6.289
2.135 2.205 2.420 2.431 2.437 2.310 2.501 2.523 2.373
5.212 5.404 5.933 5.779 6.192 5.536 6.065 5.912 6.264
2.106 2.178 2.394 2.406 2.378 2.283 2.476 2.498 2.348
5.204 5.395 5.924 5.770 6.183 5.526 6.055 5.902 6.254
2.098 2.169 2.385 2.397 2.358 2.273 2.467 2.489 2.339
5.470 5.676 6.216 6.062 6.475 5.817 6.357 6.204 6.556
2.364 2.450 2.698 2.689 2.817 2.564 2.768 2.790 2.640
5.366 5.564 6.100 5.946 6.359 5.703 6.238 6.085 6.437
2.260 2.338 2.604 2.573 2.664 2.450 2.650 2.672 2.522
5.298 5.493 6.026 5.872 6.285 5.629 6.162 6.009 6.361
2.192 2.267 2.540 2.499 2.562 2.376 2.574 2.596 2.446
5.263 5.454 5.984 5.830 6.243 5.589 6.119 5.966 6.318
2.157 2.228 2.517 2.457 2.512 2.336 2.530 2.552 2.402
5.400 5.598 6.135 5.981 6.394 5.737 6.275 6.122 6.474
2.294 2.372 2.640 2.608 2.718 2.484 2.686 2.708 2.558
5.276 5.469 6.000 5.846 6.259 5.604 6.135 5.982 6.334
2.170 2.243 2.530 2.473 2.536 2.351 2.547 2.569 2.419
5.237 5.429 5.959 5.805 6.218 5.564 6.094 5.941 6.293
2.131 2.203 2.496 2.432 2.465 2.311 2.505 2.527 2.377
5.229 5.420 5.949 5.795 6.208 5.553 6.082 5.929 6.281
2.123 2.194 2.504 2.422 2.466 2.300 2.493 2.515 2.365
4mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
3.3-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVTTL
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVCMOS
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–154
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–85. EP3SL200 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.531
1.687
3.448
1.604
3.392
1.548
3.359
1.515
3.645
1.801
3.547
1.703
3.465
1.621
3.439
1.595
3.368
1.524
3.363
1.519
3.811
1.884
3.718
1.791
3.674
1.747
3.628
1.701
3.939
2.012
3.828
1.901
3.741
1.814
3.708
1.781
3.644
1.717
3.634
1.707
5.607 5.825 6.382 6.228 6.641 5.970 6.530 6.377 6.729
2.501 2.599 2.848 2.855 3.000 2.717 2.941 2.963 2.813
5.488 5.699 6.250 6.096 6.509 5.842 6.394 6.241 6.593
2.382 2.473 2.724 2.723 2.803 2.589 2.805 2.827 2.677
5.396 5.603 6.150 5.996 6.409 5.744 6.292 6.139 6.491
2.290 2.377 2.646 2.623 2.663 2.491 2.703 2.725 2.575
5.362 5.566 6.109 5.955 6.368 5.704 6.248 6.095 6.447
2.256 2.340 2.589 2.582 2.613 2.451 2.659 2.681 2.531
5.801 6.034 6.600 6.446 6.859 6.188 6.756 6.603 6.955
2.695 2.808 3.066 3.073 3.327 2.935 3.167 3.189 3.039
5.649 5.876 6.439 6.285 6.698 6.029 6.590 6.437 6.789
2.543 2.650 2.914 2.912 3.077 2.776 3.001 3.023 2.873
5.522 5.738 6.295 6.141 6.554 5.885 6.442 6.289 6.641
2.416 2.512 2.773 2.768 2.873 2.632 2.854 2.876 2.726
5.462 5.672 6.220 6.066 6.479 5.814 6.362 6.209 6.561
2.356 2.446 2.694 2.693 2.763 2.561 2.773 2.795 2.645
5.374 5.578 6.121 5.967 6.380 5.717 6.261 6.108 6.460
2.268 2.352 2.612 2.594 2.633 2.464 2.672 2.694 2.544
5.368 5.572 6.114 5.960 6.373 5.710 6.254 6.101 6.453
2.262 2.346 2.606 2.587 2.628 2.457 2.665 2.687 2.537
4mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
2.5 V
GCLK tco
12mA
16mA
2mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
1.8 V
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–155
I/O Timing
Table 1–85. EP3SL200 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.585
1.741
3.454
1.610
3.409
1.565
3.398
1.554
3.363
1.519
3.359
1.515
3.565
1.721
3.442
1.598
3.389
1.545
3.369
1.525
3.382
1.538
3.385
1.541
3.367
1.523
3.906
1.979
3.725
1.798
3.688
1.761
3.682
1.755
3.631
1.704
3.624
1.697
3.849
1.922
3.714
1.787
3.673
1.746
3.639
1.712
3.647
1.720
3.650
1.723
3.630
1.703
5.740 5.961 6.528 6.374 6.787 6.118 6.689 6.536 6.888
2.634 2.735 3.005 3.001 3.215 2.865 3.100 3.122 2.972
5.496 5.707 6.257 6.103 6.516 5.850 6.402 6.249 6.601
2.390 2.481 2.736 2.730 2.812 2.597 2.814 2.836 2.686
5.416 5.627 6.177 6.023 6.436 5.770 6.319 6.166 6.518
2.310 2.401 2.674 2.650 2.705 2.517 2.731 2.753 2.603
5.410 5.619 6.168 6.014 6.427 5.763 6.312 6.159 6.511
2.304 2.393 2.667 2.641 2.690 2.510 2.723 2.745 2.595
5.362 5.566 6.107 5.953 6.366 5.704 6.247 6.094 6.446
2.256 2.340 2.608 2.580 2.620 2.451 2.658 2.680 2.530
5.341 5.545 6.087 5.933 6.346 5.683 6.225 6.072 6.424
2.235 2.319 2.605 2.560 2.596 2.430 2.637 2.659 2.509
5.694 5.915 6.471 6.317 6.730 6.065 6.623 6.470 6.822
2.588 2.689 2.951 2.944 3.139 2.812 3.034 3.056 2.906
5.475 5.684 6.231 6.077 6.490 5.826 6.374 6.221 6.573
2.369 2.458 2.727 2.704 2.782 2.573 2.786 2.808 2.658
5.399 5.607 6.157 6.003 6.416 5.751 6.302 6.149 6.501
2.293 2.381 2.673 2.630 2.681 2.498 2.713 2.735 2.585
5.360 5.564 6.107 5.953 6.366 5.702 6.245 6.092 6.444
2.254 2.338 2.638 2.580 2.631 2.449 2.656 2.678 2.528
5.368 5.572 6.115 5.961 6.374 5.707 6.250 6.097 6.449
2.262 2.346 2.630 2.588 2.644 2.454 2.661 2.683 2.533
5.372 5.576 6.119 5.965 6.378 5.711 6.254 6.101 6.453
2.266 2.350 2.636 2.592 2.652 2.458 2.665 2.687 2.537
5.350 5.554 6.097 5.943 6.356 5.690 6.232 6.079 6.431
2.244 2.328 2.609 2.570 2.610 2.437 2.643 2.665 2.515
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.2 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–156
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–85. EP3SL200 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.362
1.518
3.400
1.556
3.381
1.537
3.382
1.538
3.365
1.521
3.362
1.518
3.362
1.518
3.361
1.517
3.392
1.548
3.377
1.533
3.364
1.520
3.364
1.520
3.360
1.516
3.623
1.696
3.667
1.740
3.646
1.719
3.649
1.722
3.629
1.702
3.625
1.698
3.624
1.697
3.624
1.697
3.658
1.731
3.642
1.715
3.627
1.700
3.628
1.701
3.623
1.696
5.335 5.538 6.080 5.926 6.339 5.673 6.214 6.061 6.413
2.229 2.312 2.607 2.553 2.591 2.420 2.626 2.648 2.498
5.391 5.595 6.138 5.984 6.397 5.731 6.274 6.121 6.473
2.285 2.369 2.660 2.611 2.674 2.478 2.685 2.707 2.557
5.369 5.573 6.116 5.962 6.375 5.709 6.251 6.098 6.450
2.263 2.347 2.636 2.589 2.639 2.456 2.662 2.684 2.534
5.377 5.582 6.126 5.972 6.385 5.719 6.262 6.109 6.461
2.271 2.356 2.656 2.599 2.656 2.466 2.673 2.695 2.545
5.352 5.557 6.101 5.947 6.360 5.693 6.236 6.083 6.435
2.246 2.331 2.631 2.574 2.616 2.440 2.648 2.670 2.520
5.348 5.553 6.096 5.942 6.355 5.689 6.232 6.079 6.431
2.242 2.327 2.626 2.569 2.608 2.436 2.644 2.666 2.516
5.336 5.538 6.080 5.926 6.339 5.674 6.215 6.062 6.414
2.230 2.312 2.611 2.553 2.590 2.421 2.626 2.648 2.498
5.344 5.548 6.092 5.938 6.351 5.684 6.228 6.075 6.427
2.238 2.322 2.618 2.565 2.586 2.431 2.639 2.661 2.511
5.384 5.588 6.130 5.976 6.389 5.724 6.266 6.113 6.465
2.278 2.362 2.653 2.603 2.655 2.471 2.677 2.699 2.549
5.370 5.575 6.118 5.964 6.377 5.711 6.255 6.102 6.454
2.264 2.349 2.649 2.591 2.639 2.458 2.666 2.688 2.538
5.350 5.554 6.098 5.944 6.357 5.691 6.234 6.081 6.433
2.244 2.328 2.631 2.571 2.611 2.438 2.645 2.667 2.517
5.351 5.556 6.101 5.947 6.360 5.693 6.237 6.084 6.436
2.245 2.330 2.642 2.574 2.616 2.440 2.648 2.670 2.520
5.344 5.549 6.093 5.939 6.352 5.685 6.229 6.076 6.428
2.238 2.323 2.634 2.566 2.605 2.432 2.640 2.662 2.512
SSTL-2
CLASS II
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
SSTL-18
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-15
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–157
I/O Timing
Table 1–85. EP3SL200 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.378
1.534
3.377
1.533
3.364
1.520
3.359
1.515
3.361
1.517
3.360
1.516
3.379
1.535
3.374
1.530
3.373
1.529
3.364
1.520
3.365
1.521
3.387
1.543
3.377
1.533
3.640
1.713
3.640
1.713
3.626
1.699
3.621
1.694
3.624
1.697
3.622
1.695
3.641
1.714
3.637
1.710
3.636
1.709
3.626
1.699
3.628
1.701
3.653
1.726
3.641
1.714
5.352 5.554 6.095 5.941 6.354 5.689 6.230 6.077 6.429
2.246 2.328 2.622 2.568 2.613 2.436 2.641 2.663 2.513
5.356 5.559 6.101 5.947 6.360 5.694 6.236 6.083 6.435
2.250 2.333 2.640 2.574 2.628 2.441 2.647 2.669 2.519
5.340 5.543 6.085 5.931 6.344 5.678 6.220 6.067 6.419
2.234 2.317 2.622 2.558 2.601 2.425 2.631 2.653 2.503
5.334 5.537 6.079 5.925 6.338 5.672 6.214 6.061 6.413
2.228 2.311 2.611 2.552 2.586 2.419 2.625 2.647 2.497
5.339 5.542 6.085 5.931 6.344 5.678 6.220 6.067 6.419
2.233 2.316 2.632 2.558 2.603 2.425 2.632 2.654 2.504
5.332 5.535 6.077 5.923 6.336 5.670 6.211 6.058 6.410
2.226 2.309 2.613 2.550 2.576 2.417 2.623 2.645 2.495
5.354 5.556 6.098 5.944 6.357 5.692 6.232 6.079 6.431
2.248 2.330 2.627 2.571 2.613 2.439 2.644 2.666 2.516
5.352 5.555 6.097 5.943 6.356 5.691 6.232 6.079 6.431
2.246 2.329 2.634 2.570 2.616 2.438 2.643 2.665 2.515
5.353 5.556 6.098 5.944 6.357 5.692 6.233 6.080 6.432
2.247 2.330 2.635 2.571 2.617 2.439 2.644 2.666 2.516
5.340 5.544 6.086 5.932 6.345 5.679 6.221 6.068 6.420
2.234 2.318 2.622 2.559 2.598 2.426 2.632 2.654 2.504
5.346 5.550 6.094 5.940 6.353 5.686 6.229 6.076 6.428
2.240 2.324 2.637 2.567 2.608 2.433 2.641 2.663 2.513
5.374 5.577 6.120 5.966 6.379 5.714 6.256 6.103 6.455
2.268 2.351 2.655 2.593 2.638 2.461 2.668 2.690 2.540
5.362 5.566 6.109 5.955 6.368 5.702 6.245 6.092 6.444
2.256 2.340 2.645 2.582 2.624 2.449 2.656 2.678 2.528
8mA
16mA
4mA
GCLK
tco
PLL
SSTL-15
CLASS II
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–158
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–85. EP3SL200 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.375
1.531
3.373
1.529
3.369
1.525
3.446
1.602
3.446
1.602
3.475
1.631
3.396
1.552
3.366
1.522
3.352
1.508
3.639
1.712
3.637
1.710
3.633
1.706
3.708
1.781
3.708
1.781
3.747
1.820
3.658
1.731
3.626
1.699
3.612
1.685
5.360 5.564 6.107 5.953 6.366 5.701 6.244 6.091 6.443
2.254 2.338 2.650 2.580 2.623 2.448 2.655 2.677 2.527
5.359 5.564 6.107 5.953 6.366 5.700 6.244 6.091 6.443
2.253 2.338 2.652 2.580 2.621 2.447 2.655 2.677 2.527
5.352 5.557 6.100 5.946 6.359 5.693 6.236 6.083 6.435
2.246 2.331 2.643 2.573 2.611 2.440 2.648 2.670 2.520
5.370 5.565 6.097 5.943 6.356 5.701 6.234 6.081 6.433
2.264 2.339 2.619 2.570 2.580 2.448 2.645 2.667 2.517
5.370 5.565 6.097 5.943 6.356 5.701 6.234 6.081 6.433
2.264 2.339 2.619 2.570 2.580 2.448 2.645 2.667 2.517
5.436 5.640 6.177 6.023 6.436 5.779 6.315 6.162 6.514
2.330 2.414 2.639 2.650 2.757 2.526 2.726 2.748 2.598
5.332 5.528 6.060 5.906 6.319 5.663 6.195 6.042 6.394
2.226 2.302 2.522 2.533 2.589 2.410 2.606 2.628 2.478
5.265 5.458 5.990 5.836 6.249 5.593 6.128 5.975 6.327
2.159 2.232 2.452 2.463 2.489 2.340 2.539 2.561 2.411
5.244 5.435 5.962 5.808 6.221 5.567 6.094 5.941 6.293
2.138 2.209 2.424 2.435 2.446 2.314 2.506 2.528 2.378
1.5-V
HSTL
CLASS II
16mA
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–159
I/O Timing
Table 1–86 specifies EP3SL200 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–86. EP3SL200 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.902
1.768
3.813
1.663
3.724
1.560
3.906
1.772
3.728
1.564
3.848
1.714
3.733
1.587
3.695
1.536
3.767
1.633
3.679
1.515
3.884
1.750
3.785
1.651
3.735
1.575
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.639
1.551
3.548
1.468
3.469
1.389
3.649
1.561
3.473
1.393
3.593
1.505
3.474
1.394
3.437
1.357
3.507
1.419
3.424
1.344
3.619
1.531
3.516
1.436
3.463
1.379
5.663 5.916 6.397 6.238 6.709 6.053 6.634 6.238 6.709
2.210 2.317 2.505 2.518 2.444 2.409 2.649 2.518 2.444
5.533 5.778 6.283 6.124 6.565 5.912 6.485 6.124 6.565
2.080 2.179 2.361 2.374 2.300 2.268 2.500 2.374 2.300
5.414 5.655 6.187 6.028 6.437 5.785 6.353 6.028 6.437
1.961 2.056 2.233 2.246 2.172 2.147 2.368 2.246 2.172
5.671 5.921 6.406 6.247 6.714 6.059 6.639 6.247 6.714
2.218 2.322 2.510 2.523 2.449 2.415 2.654 2.523 2.449
5.420 5.661 6.197 6.038 6.443 5.794 6.360 6.038 6.443
1.967 2.062 2.239 2.252 2.178 2.159 2.375 2.252 2.178
5.615 5.869 6.363 6.204 6.666 6.010 6.592 6.204 6.666
2.162 2.270 2.462 2.475 2.401 2.366 2.607 2.475 2.401
5.463 5.710 6.218 6.059 6.502 5.848 6.428 6.059 6.502
2.010 2.111 2.298 2.311 2.237 2.204 2.443 2.311 2.237
5.395 5.627 6.148 5.989 6.414 5.762 6.335 5.989 6.414
1.928 2.028 2.210 2.223 2.149 2.118 2.350 2.223 2.149
5.510 5.762 6.254 6.095 6.555 5.902 6.481 6.095 6.555
2.057 2.163 2.351 2.364 2.290 2.258 2.496 2.364 2.290
5.368 5.588 6.120 5.961 6.375 5.722 6.295 5.961 6.375
1.893 1.989 2.171 2.184 2.110 2.087 2.310 2.184 2.110
5.748 6.023 6.508 6.349 6.838 6.170 6.771 6.349 6.838
2.295 2.424 2.634 2.647 2.573 2.526 2.786 2.647 2.573
5.593 5.860 6.366 6.207 6.668 6.003 6.597 6.207 6.668
2.140 2.261 2.464 2.477 2.403 2.359 2.612 2.477 2.403
5.492 5.741 6.275 6.116 6.542 5.880 6.467 6.116 6.542
2.029 2.142 2.338 2.351 2.277 2.236 2.482 2.351 2.277
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
GCLK
PLL
3.3-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–160
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–86. EP3SL200 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
4.170
2.018
3.968
1.816
3.866
1.714
3.792
1.640
4.088
1.936
3.831
1.679
3.783
1.631
3.774
1.622
4.013
1.861
3.824
1.672
3.723
1.561
3.719
1.555
3.708
1.544
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.863
1.795
3.638
1.570
3.573
1.505
3.521
1.445
3.774
1.706
3.537
1.464
3.510
1.437
3.496
1.428
3.717
1.649
3.542
1.469
3.463
1.383
3.458
1.378
3.449
1.369
6.174 6.451 7.093 6.933 7.278 6.617 7.250 6.933 7.278
2.703 2.852 3.121 3.130 3.066 2.995 3.095 3.130 3.066
5.848 6.083 6.688 6.528 6.873 6.252 6.844 6.528 6.873
2.377 2.484 2.716 2.725 2.661 2.630 2.734 2.725 2.661
5.694 5.933 6.529 6.369 6.714 6.084 6.671 6.369 6.714
2.223 2.334 2.557 2.566 2.502 2.462 2.628 2.566 2.502
5.617 5.840 6.433 6.273 6.618 5.989 6.577 6.273 6.618
2.146 2.241 2.461 2.470 2.406 2.367 2.556 2.470 2.406
6.084 6.365 7.021 6.861 7.206 6.524 7.174 6.861 7.206
2.613 2.766 3.049 3.058 2.994 2.902 3.030 3.058 2.994
5.679 5.928 6.530 6.370 6.715 6.078 6.670 6.370 6.715
2.208 2.329 2.558 2.567 2.503 2.456 2.629 2.567 2.503
5.606 5.832 6.424 6.264 6.609 5.980 6.565 6.264 6.609
2.135 2.233 2.452 2.461 2.397 2.358 2.556 2.461 2.397
5.584 5.814 6.405 6.245 6.590 5.962 6.543 6.245 6.590
2.113 2.215 2.433 2.442 2.378 2.340 2.537 2.442 2.378
5.994 6.279 6.946 6.786 7.131 6.436 7.090 6.786 7.131
2.523 2.680 2.974 2.983 2.919 2.814 2.961 2.983 2.919
5.701 5.956 6.571 6.411 6.756 6.103 6.712 6.411 6.756
2.230 2.357 2.599 2.608 2.544 2.481 2.673 2.608 2.544
5.485 5.713 6.265 6.106 6.510 5.855 6.429 6.106 6.510
2.006 2.114 2.306 2.319 2.245 2.220 2.444 2.319 2.245
5.482 5.705 6.263 6.104 6.502 5.854 6.422 6.104 6.502
1.999 2.106 2.298 2.311 2.237 2.219 2.437 2.311 2.237
5.467 5.680 6.246 6.087 6.475 5.837 6.395 6.087 6.475
1.984 2.081 2.271 2.284 2.210 2.202 2.413 2.284 2.210
2mA
4mA
6mA
8mA
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
1.8 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-2
CLASS I
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–161
I/O Timing
Table 1–86. EP3SL200 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.748
1.596
3.734
1.582
3.722
1.570
3.699
1.547
3.698
1.546
3.707
1.555
3.702
1.550
3.744
1.592
3.722
1.570
3.705
1.553
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.474
1.406
3.465
1.391
3.454
1.380
3.443
1.363
3.443
1.363
3.451
1.371
3.452
1.372
3.473
1.402
3.459
1.379
3.448
1.368
5.512 5.727 6.306 6.146 6.491 5.870 6.440 6.146 6.491
2.041 2.128 2.334 2.343 2.279 2.248 2.447 2.343 2.279
5.509 5.725 6.304 6.144 6.489 5.868 6.438 6.144 6.489
2.038 2.126 2.332 2.341 2.277 2.246 2.445 2.341 2.277
5.492 5.708 6.287 6.127 6.472 5.857 6.422 6.127 6.472
2.021 2.109 2.315 2.324 2.260 2.229 2.436 2.324 2.260
5.476 5.692 6.272 6.112 6.457 5.845 6.407 6.112 6.457
2.005 2.093 2.300 2.309 2.245 2.214 2.424 2.309 2.245
5.475 5.691 6.271 6.111 6.456 5.844 6.406 6.111 6.456
2.004 2.092 2.299 2.308 2.244 2.213 2.424 2.308 2.244
5.473 5.687 6.265 6.105 6.450 5.840 6.399 6.105 6.450
2.002 2.088 2.293 2.302 2.238 2.208 2.418 2.302 2.238
5.472 5.688 6.267 6.107 6.458 5.849 6.408 6.107 6.458
2.001 2.093 2.295 2.304 2.240 2.214 2.429 2.304 2.240
5.523 5.741 6.323 6.163 6.508 5.883 6.456 6.163 6.508
2.052 2.142 2.351 2.360 2.296 2.261 2.459 2.360 2.296
5.505 5.724 6.306 6.146 6.491 5.869 6.440 6.146 6.491
2.034 2.125 2.334 2.343 2.279 2.245 2.450 2.343 2.279
5.488 5.706 6.288 6.128 6.473 5.856 6.423 6.128 6.473
2.017 2.107 2.316 2.325 2.261 2.227 2.437 2.325 2.261
4mA
6mA
8mA
10mA
12mA
8mA
16mA
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-18
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–162
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–86. EP3SL200 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.720
1.568
3.708
1.556
3.696
1.544
3.698
1.546
3.693
1.541
3.697
1.545
3.727
1.575
3.717
1.565
3.712
1.560
3.726
1.574
3.714
1.562
3.712
1.560
3.829
1.665
3.829
1.665
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.458
1.381
3.451
1.371
3.442
1.362
3.445
1.365
3.441
1.361
3.449
1.369
3.464
1.388
3.458
1.378
3.454
1.374
3.466
1.387
3.457
1.377
3.456
1.376
3.569
1.489
3.569
1.489
5.479 5.692 6.268 6.108 6.453 5.839 6.402 6.108 6.453
2.008 2.093 2.296 2.305 2.241 2.212 2.415 2.305 2.241
5.470 5.684 6.260 6.100 6.445 5.838 6.395 6.100 6.445
1.999 2.085 2.288 2.297 2.233 2.204 2.415 2.297 2.233
5.462 5.675 6.252 6.092 6.438 5.831 6.387 6.092 6.438
1.991 2.076 2.280 2.289 2.225 2.196 2.408 2.289 2.225
5.464 5.678 6.255 6.095 6.442 5.834 6.390 6.095 6.442
1.993 2.079 2.283 2.292 2.228 2.199 2.411 2.292 2.228
5.462 5.677 6.255 6.095 6.445 5.837 6.395 6.095 6.445
1.991 2.081 2.283 2.292 2.228 2.202 2.416 2.292 2.228
5.457 5.669 6.246 6.086 6.441 5.833 6.389 6.086 6.441
1.986 2.078 2.274 2.283 2.219 2.198 2.410 2.283 2.219
5.490 5.705 6.283 6.123 6.468 5.848 6.416 6.123 6.468
2.019 2.106 2.311 2.320 2.256 2.224 2.426 2.320 2.256
5.486 5.701 6.279 6.119 6.464 5.850 6.413 6.119 6.464
2.015 2.102 2.307 2.316 2.252 2.221 2.429 2.316 2.252
5.480 5.695 6.273 6.113 6.458 5.845 6.407 6.113 6.458
2.009 2.096 2.301 2.310 2.246 2.215 2.423 2.310 2.246
5.501 5.719 6.301 6.141 6.486 5.864 6.433 6.141 6.486
2.030 2.120 2.329 2.338 2.274 2.238 2.445 2.338 2.274
5.490 5.707 6.289 6.129 6.474 5.855 6.422 6.129 6.474
2.019 2.108 2.317 2.326 2.262 2.227 2.436 2.326 2.262
5.494 5.712 6.295 6.135 6.480 5.864 6.429 6.135 6.480
2.023 2.113 2.323 2.332 2.268 2.233 2.446 2.332 2.268
5.537 5.731 6.305 6.146 6.519 5.903 6.453 6.146 6.519
2.054 2.132 2.315 2.328 2.267 2.268 2.474 2.328 2.267
5.537 5.731 6.305 6.146 6.519 5.903 6.453 6.146 6.519
2.054 2.132 2.315 2.328 2.267 2.268 2.474 2.328 2.267
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
—
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
1.5-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–163
I/O Timing
Table 1–87 through Table 1–90 show the maximum I/O timing parameters for
EP3SL200 devices for differential I/O standards.
Table 1–87 specifies EP3SL200 column pins input timing parameters for differential
I/O standards.
Table 1–87. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.153
1.289
1.103
-0.824
-1.153
1.289
1.103
-0.824
-1.161
1.297
1.095
-0.816
-1.161
1.297
1.095
-0.816
-1.173
1.309
1.083
-0.804
-1.173
1.309
1.083
-0.804
-1.161
1.297
1.095
-0.816
-1.161
1.297
1.095
-0.816
-1.221
1.376
1.122
-0.821
-1.221
1.376
1.122
-0.821
-1.233
1.388
1.110
-0.809
-1.233
1.388
1.110
-0.809
-1.244
1.399
1.099
-0.798
-1.244
1.399
1.099
-0.798
-1.233
1.388
1.110
-0.809
-1.233
1.388
1.110
-0.809
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
GCLK
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096
ns
ns
LVDS
tsu
th
GCLK
PLL
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
tsu
th
GCLK
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096
ns
ns
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
-1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
2.133 2.172 2.365 2.272 2.746 2.199 2.388 2.272 2.746
1.863 1.964 2.172 2.064 2.061 1.976 2.184 2.064 2.061
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 ns
-1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
2.133 2.172 2.365 2.272 2.746 2.199 2.388 2.272 2.746
1.863 1.964 2.172 2.064 2.061 1.976 2.184 2.064 2.061
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–164
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–87. EP3SL200 Column Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.173
1.309
1.083
-0.804
-1.173
1.309
1.083
-0.804
-1.180
1.316
1.076
-0.797
-1.180
1.316
1.076
-0.797
-1.153
1.289
1.103
-0.824
-1.153
1.289
1.103
-0.824
-1.161
1.297
1.095
-0.816
-1.244
1.399
1.099
-0.798
-1.244
1.399
1.099
-0.798
-1.250
1.405
1.093
-0.792
-1.250
1.405
1.093
-0.792
-1.221
1.376
1.122
-0.821
-1.221
1.376
1.122
-0.821
-1.233
1.388
1.110
-0.809
-1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
2.133 2.172 2.365 2.272 2.746 2.199 2.388 2.272 2.746
1.863 1.964 2.172 2.064 2.061 1.976 2.184 2.064 2.061
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 ns
-1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
2.133 2.172 2.365 2.272 2.746 2.199 2.388 2.272 2.746
1.863 1.964 2.172 2.064 2.061 1.976 2.184 2.064 2.061
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 ns
-1.910 -1.938 -2.102 -2.024 -2.493 -1.954 -2.112 -2.024 -2.493 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
2.146 2.180 2.368 2.275 2.750 2.206 2.388 2.275 2.750
1.851 1.959 2.172 2.062 2.062 1.972 2.189 2.062 2.062
ns
ns
tsu
th
GCLK
PLL
-1.371 -1.463 -1.621 -1.542 -1.523 -1.464 -1.626 -1.542 -1.523 ns
-1.910 -1.938 -2.102 -2.024 -2.493 -1.954 -2.112 -2.024 -2.493 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
2.146 2.180 2.368 2.275 2.750 2.206 2.388 2.275 2.750
1.851 1.959 2.172 2.062 2.062 1.972 2.189 2.062 2.062
ns
ns
tsu
th
GCLK
PLL
-1.371 -1.463 -1.621 -1.542 -1.523 -1.464 -1.626 -1.542 -1.523 ns
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096
ns
ns
tsu
th
GCLK
PLL
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096
ns
ns
tsu
th
GCLK
PLL
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–165
I/O Timing
Table 1–88 specifies EP3SL200 row pins input timing parameters for differential I/O
standards.
Table 1–88. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.332
1.476
0.869
-0.581
-1.332
1.476
0.869
-0.581
-1.332
1.476
0.869
-0.581
-1.137
1.274
1.064
-0.783
-1.137
1.274
1.064
-0.783
-1.146
1.283
1.055
-0.774
-1.146
1.283
1.055
-0.774
-1.401
1.563
0.886
-0.578
-1.401
1.563
0.886
-0.578
-1.401
1.563
0.886
-0.578
-1.216
1.369
1.071
-0.772
-1.216
1.369
1.071
-0.772
-1.228
1.381
1.059
-0.760
-1.228
1.381
1.059
-0.760
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
GCLK
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297
ns
ns
LVDS
tsu
th
GCLK
PLL
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
tsu
th
GCLK
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297
ns
ns
MINI-LVDS
GCLK
tsu
th
PLL
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
tsu
th
GCLK
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297
ns
ns
RSDS
GCLK
tsu
th
PLL
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 ns
tsu
th
GCLK
2.088 2.122 2.297 2.206 2.656 2.156 2.330 2.206 2.656
1.866 1.981 2.216 2.098 2.118 1.985 2.221 2.098 2.118
ns
ns
tsu
th
GCLK
PLL
DIFFERENTIAL
1.2-V
HSTL CLASS I
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 ns
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 ns
tsu
th
GCLK
2.088 2.122 2.297 2.206 2.656 2.156 2.330 2.206 2.656
1.866 1.981 2.216 2.098 2.118 1.985 2.221 2.098 2.118
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
tsu
th
GCLK
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102
ns
ns
tsu
th
GCLK
PLL
DIFFERENTIAL
1.5-V
HSTL CLASS I
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
tsu
th
GCLK
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–166
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–88. EP3SL200 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.160
1.297
1.041
-0.760
-1.160
1.297
1.041
-0.760
-1.146
1.283
1.055
-0.774
-1.146
1.283
1.055
-0.774
-1.160
1.297
1.041
-0.760
-1.160
1.297
1.041
-0.760
-1.169
1.306
1.032
-0.751
-1.169
1.306
1.032
-0.751
-1.240
1.393
1.047
-0.748
-1.240
1.393
1.047
-0.748
-1.228
1.381
1.059
-0.760
-1.228
1.381
1.059
-0.760
-1.240
1.393
1.047
-0.748
-1.240
1.393
1.047
-0.748
-1.249
1.402
1.038
-0.739
-1.249
1.402
1.038
-0.739
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
GCLK
GCLK
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084
ns
ns
tsu
th
DIFFERENTIAL
1.8-V
HSTL CLASS I
PLL
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
tsu
th
GCLK
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084
ns
ns
tsu
th
GCLK
PLL
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
tsu
th
GCLK
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102
ns
ns
tsu
th
GCLK
PLL
DIFFERENTIAL
1.5-V
SSTL CLASS I
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
tsu
th
GCLK
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
tsu
th
GCLK
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084
ns
ns
tsu
th
GCLK
PLL
DIFFERENTIAL
1.8-V
SSTL CLASS I
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
tsu
th
GCLK
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084
ns
ns
tsu
th
GCLK
PLL
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 ns
tsu
th
GCLK
2.121 2.156 2.341 2.250 2.701 2.186 2.369 2.250 2.701
1.829 1.945 2.171 2.052 2.073 1.954 2.182 2.052 2.073
ns
ns
tsu
th
GCLK
PLL
DIFFERENTIAL
2.5-V
SSTL CLASS I
-1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 ns
-1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 ns
tsu
th
GCLK
2.121 2.156 2.341 2.250 2.701 2.186 2.369 2.250 2.701
1.829 1.945 2.171 2.052 2.073 1.954 2.182 2.052 2.073
ns
ns
tsu
th
GCLK
PLL
-1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–167
I/O Timing
Table 1–89 specifies EP3SL200 Column Pins Output Timing parameters for differential
I/O standards.
Table 1–89. EP3SL200 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.460
1.374
3.456
1.370
3.460
1.374
3.456
1.370
3.460
1.374
3.456
1.370
3.487
1.401
3.477
1.391
3.477
1.391
3.470
1.384
3.469
1.383
3.491
1.405
3.730
1.562
3.733
1.565
3.730
1.562
3.733
1.565
3.730
1.562
3.733
1.565
3.763
1.595
3.753
1.585
3.753
1.585
3.747
1.579
3.745
1.577
3.767
1.599
5.480 5.686 6.242 6.079 6.486 5.828 6.383 6.079 6.486
1.992 2.073 2.282 2.291 2.242 2.188 2.399 2.291 2.242
5.527 5.741 6.304 6.141 6.548 5.887 6.449 6.141 6.548
2.039 2.128 2.344 2.353 2.304 2.247 2.465 2.353 2.304
5.480 5.686 6.242 6.079 6.486 5.828 6.383 6.079 6.486
—
—
LVDS_E_1R
LVDS_E_3R
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
1.992 2.073 2.282 2.291 2.242 2.188 2.399 2.291 2.242 ns
ns
GCLK
5.527 5.741 6.304 6.141 6.548 5.887 6.449 6.141 6.548
2.039 2.128 2.344 2.353 2.304 2.247 2.465 2.353 2.304 ns
ns
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
5.480 5.686 6.242 6.079 6.486 5.828 6.383 6.079 6.486
1.992 2.073 2.282 2.291 2.242 2.188 2.399 2.291 2.242 ns
ns
—
RSDS_E_1R
RSDS_E_3R
GCLK
PLL
GCLK
5.527 5.741 6.304 6.141 6.548 5.887 6.449 6.141 6.548
2.039 2.128 2.344 2.353 2.304 2.247 2.465 2.353 2.304 ns
ns
—
GCLK
PLL
GCLK
5.551 5.764 6.326 6.163 6.570 5.908 6.469 6.163 6.570
2.063 2.151 2.366 2.375 2.326 2.268 2.485 2.375 2.326 ns
ns
4mA
6mA
8mA
GCLK
PLL
GCLK
5.541 5.753 6.316 6.153 6.560 5.897 6.459 6.153 6.560
2.053 2.140 2.356 2.365 2.316 2.257 2.475 2.365 2.316 ns
ns
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
5.544 5.757 6.320 6.157 6.564 5.902 6.464 6.157 6.564
2.056 2.144 2.360 2.369 2.320 2.262 2.480 2.369 2.320 ns
ns
GCLK
PLL
GCLK
5.537 5.751 6.314 6.151 6.558 5.895 6.458 6.151 6.558
2.049 2.138 2.354 2.363 2.314 2.255 2.474 2.363 2.314 ns
10m
A
GCLK
PLL
GCLK
ns
ns
ns
ns
5.534 5.748 6.311 6.148 6.555 5.892 6.454 6.148 6.555
2.046 2.135 2.351 2.360 2.311 2.252 2.470 2.360 2.311
5.555 5.768 6.330 6.167 6.574 5.912 6.474 6.167 6.574
2.067 2.155 2.370 2.379 2.330 2.272 2.490 2.379 2.330
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
16m
A
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–168
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–89. EP3SL200 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.481
1.395
3.476
1.390
3.474
1.388
3.466
1.380
3.467
1.381
3.466
1.380
3.478
1.392
3.474
1.388
3.464
1.378
3.462
1.376
3.462
1.376
3.466
1.380
3.756
1.588
3.752
1.584
3.750
1.582
3.741
1.573
3.743
1.575
3.740
1.572
3.753
1.585
3.750
1.582
3.739
1.571
3.737
1.569
3.738
1.570
3.741
1.573
5.534 5.745 6.305 6.142 6.549 5.888 6.447 6.142 6.549
2.046 2.132 2.345 2.354 2.305 2.248 2.463 2.354 2.305
5.534 5.745 6.306 6.143 6.550 5.889 6.449 6.143 6.550
2.046 2.132 2.346 2.355 2.306 2.249 2.465 2.355 2.306
5.533 5.744 6.304 6.141 6.548 5.888 6.448 6.141 6.548
2.045 2.131 2.344 2.353 2.304 2.248 2.464 2.353 2.304
5.523 5.734 6.295 6.132 6.539 5.878 6.438 6.132 6.539
2.035 2.121 2.335 2.344 2.295 2.238 2.454 2.344 2.295
5.529 5.741 6.303 6.140 6.547 5.886 6.447 6.140 6.547
2.041 2.128 2.343 2.352 2.303 2.246 2.463 2.352 2.303
5.512 5.722 6.281 6.118 6.525 5.865 6.423 6.118 6.525
2.024 2.109 2.321 2.330 2.281 2.225 2.439 2.330 2.281
5.530 5.740 6.299 6.136 6.543 5.884 6.442 6.136 6.543
2.042 2.127 2.339 2.348 2.299 2.244 2.458 2.348 2.299
5.531 5.742 6.303 6.140 6.547 5.886 6.446 6.140 6.547
2.043 2.129 2.343 2.352 2.303 2.246 2.462 2.352 2.303
5.520 5.731 6.291 6.128 6.535 5.875 6.434 6.128 6.535
2.032 2.118 2.331 2.340 2.291 2.235 2.450 2.340 2.291
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
5.518 5.728 6.289 6.126 6.533 5.873 6.432 6.126 6.533 ns
ns
10m
A
GCLK
PLL
2.030 2.115 2.329 2.338 2.289 2.233 2.448 2.338 2.289
5.521 5.733 6.294 6.131 6.538 5.877 6.438 6.131 6.538 ns
ns
GCLK
12m
A
GCLK
PLL
2.033 2.120 2.334 2.343 2.294 2.237 2.454 2.343 2.294
5.518 5.728 6.288 6.125 6.532 5.872 6.431 6.125 6.532 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
16m
A
GCLK
PLL
ns
2.030 2.115 2.328 2.337 2.288 2.232 2.447 2.337 2.288
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–169
I/O Timing
Table 1–89. EP3SL200 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.492
1.406
3.478
1.392
3.466
1.380
3.466
1.380
3.462
1.376
3.466
1.380
3.467
1.381
3.495
1.409
3.484
1.398
3.479
1.393
3.465
1.379
3.463
1.377
3.467
1.381
3.467
1.381
3.770
1.602
3.756
1.588
3.743
1.575
3.743
1.575
3.739
1.571
3.741
1.573
3.743
1.575
3.773
1.605
3.761
1.593
3.757
1.589
3.742
1.574
3.740
1.572
3.742
1.574
3.743
1.575
5.563 5.776 6.338 6.175 6.582 5.920 6.481 6.175 6.582
2.075 2.163 2.378 2.387 2.338 2.280 2.497 2.387 2.338
5.551 5.765 6.328 6.165 6.572 5.910 6.472 6.165 6.572
2.063 2.152 2.368 2.377 2.328 2.270 2.488 2.377 2.328
5.534 5.747 6.310 6.147 6.554 5.892 6.454 6.147 6.554
2.046 2.134 2.350 2.359 2.310 2.252 2.470 2.359 2.310
5.537 5.751 6.314 6.151 6.558 5.896 6.459 6.151 6.558
2.049 2.138 2.354 2.363 2.314 2.256 2.475 2.363 2.314
5.530 5.743 6.307 6.144 6.551 5.889 6.451 6.144 6.551
2.042 2.130 2.347 2.356 2.307 2.249 2.467 2.356 2.307
5.523 5.734 6.295 6.132 6.539 5.878 6.438 6.132 6.539
2.035 2.121 2.335 2.344 2.295 2.238 2.454 2.344 2.295
5.531 5.744 6.306 6.143 6.550 5.888 6.450 6.143 6.550
2.043 2.131 2.346 2.355 2.306 2.248 2.466 2.355 2.306
5.562 5.774 6.336 6.173 6.580 5.919 6.479 6.173 6.580
2.074 2.161 2.376 2.385 2.336 2.279 2.495 2.385 2.336
5.550 5.762 6.324 6.161 6.568 5.907 6.467 6.161 6.568
2.062 2.149 2.364 2.373 2.324 2.267 2.483 2.373 2.324
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
8mA
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
5.550 5.763 6.325 6.162 6.569 5.908 6.469 6.162 6.569 ns
ns
GCLK
PLL
2.062 2.150 2.365 2.374 2.325 2.268 2.485 2.374 2.325
5.532 5.744 6.306 6.143 6.550 5.889 6.451 6.143 6.550 ns
ns
GCLK
10m
A
GCLK
PLL
2.044 2.131 2.346 2.355 2.306 2.249 2.467 2.355 2.306
5.530 5.742 6.304 6.141 6.548 5.887 6.448 6.141 6.548 ns
ns
GCLK
12m
A
GCLK
PLL
2.042 2.129 2.344 2.353 2.304 2.247 2.464 2.353 2.304
5.522 5.732 6.292 6.129 6.536 5.876 6.435 6.129 6.536 ns
ns
GCLK
8mA
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
2.034 2.119 2.332 2.341 2.292 2.236 2.451 2.341 2.292
5.530 5.742 6.304 6.141 6.548 5.887 6.448 6.141 6.548 ns
GCLK
16m
A
GCLK
PLL
ns
2.042 2.129 2.344 2.353 2.304 2.247 2.464 2.353 2.304
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–170
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–89. EP3SL200 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.483
1.397
3.483
1.397
3.473
1.387
3.466
1.380
3.760
1.592
3.760
1.592
3.750
1.582
3.742
1.574
5.546 5.757 6.318 6.155 6.562 5.902 6.461 6.155 6.562
2.058 2.144 2.358 2.367 2.318 2.262 2.477 2.367 2.318
5.546 5.757 6.318 6.155 6.562 5.902 6.461 6.155 6.562
2.058 2.144 2.358 2.367 2.318 2.262 2.477 2.367 2.318
5.536 5.747 6.308 6.145 6.552 5.892 6.452 6.145 6.552
2.048 2.134 2.348 2.357 2.308 2.252 2.468 2.357 2.308
5.522 5.732 6.292 6.129 6.536 5.876 6.435 6.129 6.536
2.034 2.119 2.332 2.341 2.292 2.236 2.451 2.341 2.292
8mA
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
16m
A
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–171
I/O Timing
Table 1–90 specifies EP3SL200 Row Pins Output Timing parameters for differential
I/O standards.
Table 1–90. EP3SL200 Row Pins output Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.149
1.067
3.527
1.445
3.509
1.427
3.149
1.067
3.527
1.445
3.509
1.427
3.149
1.067
3.527
1.445
3.509
1.427
3.553
1.481
3.539
1.467
3.535
1.463
3.372
1.206
3.802
1.636
3.792
1.626
3.372
1.206
3.802
1.636
3.792
1.626
3.372
1.206
3.802
1.636
3.792
1.626
3.835
1.679
3.821
1.665
3.817
1.661
4.930 5.111 5.636 5.477 5.864 5.235 5.760 5.477 5.864
1.444 1.503 1.675 1.692 1.626 1.599 1.774 1.692 1.626
5.588 5.798 6.363 6.197 6.576 5.946 6.513 6.197 6.576
2.102 2.190 2.402 2.412 2.338 2.310 2.527 2.412 2.338
5.626 5.844 6.417 6.251 6.630 5.997 6.574 6.251 6.630
2.140 2.236 2.456 2.466 2.392 2.361 2.588 2.466 2.392
4.930 5.111 5.636 5.477 5.864 5.235 5.760 5.477 5.864
1.444 1.503 1.675 1.692 1.626 1.599 1.774 1.692 1.626
5.588 5.798 6.363 6.197 6.576 5.946 6.513 6.197 6.576
2.102 2.190 2.402 2.412 2.338 2.310 2.527 2.412 2.338
5.626 5.844 6.417 6.251 6.630 5.997 6.574 6.251 6.630
2.140 2.236 2.456 2.466 2.392 2.361 2.588 2.466 2.392
4.930 5.111 5.636 5.477 5.864 5.235 5.760 5.477 5.864
1.444 1.503 1.675 1.692 1.626 1.599 1.774 1.692 1.626
5.588 5.798 6.363 6.197 6.576 5.946 6.513 6.197 6.576
2.102 2.190 2.402 2.412 2.338 2.310 2.527 2.412 2.338
5.626 5.844 6.417 6.251 6.630 5.997 6.574 6.251 6.630
2.140 2.236 2.456 2.466 2.392 2.361 2.588 2.466 2.392
5.662 5.878 6.450 6.284 6.663 6.030 6.603 6.284 6.663
2.186 2.280 2.499 2.509 2.435 2.404 2.627 2.509 2.435
5.649 5.865 6.437 6.271 6.650 6.016 6.590 6.271 6.650
2.173 2.267 2.486 2.496 2.422 2.390 2.614 2.496 2.422
5.647 5.865 6.438 6.272 6.651 6.016 6.592 6.272 6.651
2.171 2.267 2.487 2.497 2.423 2.390 2.616 2.497 2.423
LVDS
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
—
GCLK
tco
PLL
GCLK tco
RSDS
—
GCLK
tco
PLL
GCLK tco
RSDS_E_1R
RSDS_E_3R
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–172
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–90. EP3SL200 Row Pins output Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.551
1.479
3.540
1.468
3.537
1.465
3.548
1.476
3.538
1.466
3.524
1.452
3.521
1.449
3.518
1.446
3.519
1.447
3.568
1.496
3.544
1.472
3.526
1.454
3.832
1.676
3.822
1.666
3.819
1.663
3.829
1.673
3.820
1.664
3.806
1.650
3.802
1.646
3.800
1.644
3.800
1.644
3.853
1.697
3.829
1.673
3.810
1.654
5.648 5.862 6.432 6.266 6.645 6.013 6.585 6.266 6.645
2.172 2.264 2.481 2.491 2.417 2.387 2.609 2.491 2.417
5.644 5.858 6.429 6.263 6.642 6.010 6.582 6.263 6.642
2.168 2.260 2.478 2.488 2.414 2.384 2.606 2.488 2.414
5.642 5.856 6.427 6.261 6.640 6.008 6.581 6.261 6.640
2.166 2.258 2.476 2.486 2.412 2.382 2.605 2.486 2.412
5.643 5.857 6.426 6.260 6.639 6.007 6.579 6.260 6.639
2.167 2.259 2.475 2.485 2.411 2.381 2.603 2.485 2.411
5.641 5.855 6.425 6.259 6.638 6.007 6.579 6.259 6.638
2.165 2.257 2.474 2.484 2.410 2.381 2.603 2.484 2.410
5.626 5.840 6.411 6.245 6.624 5.992 6.564 6.245 6.624
2.150 2.242 2.460 2.470 2.396 2.366 2.588 2.470 2.396
5.622 5.836 6.407 6.241 6.620 5.988 6.560 6.241 6.620
2.146 2.238 2.456 2.466 2.392 2.362 2.584 2.466 2.392
5.623 5.839 6.410 6.244 6.623 5.991 6.564 6.244 6.623
2.147 2.241 2.459 2.469 2.395 2.365 2.588 2.469 2.395
5.613 5.827 6.397 6.231 6.610 5.978 6.550 6.231 6.610
2.137 2.229 2.446 2.456 2.382 2.352 2.574 2.456 2.382
5.684 5.900 6.473 6.307 6.686 6.052 6.626 6.307 6.686
2.208 2.302 2.522 2.532 2.458 2.426 2.650 2.532 2.458
5.666 5.883 6.456 6.290 6.669 6.035 6.611 6.290 6.669
2.190 2.285 2.505 2.515 2.441 2.409 2.635 2.515 2.441
5.644 5.861 6.434 6.268 6.647 6.013 6.589 6.268 6.647
2.168 2.263 2.483 2.493 2.419 2.387 2.613 2.493 2.419
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–173
I/O Timing
Table 1–90. EP3SL200 Row Pins output Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.572
1.500
3.557
1.485
3.546
1.474
3.526
1.454
3.523
1.451
3.528
1.456
3.521
1.449
3.559
1.477
3.541
1.459
3.527
1.445
3.856
1.700
3.841
1.685
3.830
1.674
3.810
1.654
3.806
1.650
3.810
1.654
3.803
1.647
3.842
1.676
3.825
1.659
3.809
1.643
5.684 5.900 6.472 6.306 6.685 6.052 6.626 6.306 6.685
2.208 2.302 2.521 2.531 2.457 2.426 2.650 2.531 2.457
5.670 5.885 6.457 6.291 6.670 6.037 6.611 6.291 6.670
2.194 2.287 2.506 2.516 2.442 2.411 2.635 2.516 2.442
5.665 5.882 6.454 6.288 6.667 6.034 6.609 6.288 6.667
2.189 2.284 2.503 2.513 2.439 2.408 2.633 2.513 2.439
5.642 5.858 6.431 6.265 6.644 6.011 6.585 6.265 6.644
2.166 2.260 2.480 2.490 2.416 2.385 2.609 2.490 2.416
5.638 5.855 6.427 6.261 6.640 6.007 6.582 6.261 6.640
2.162 2.257 2.476 2.486 2.412 2.381 2.606 2.486 2.412
5.629 5.843 6.413 6.247 6.626 5.994 6.566 6.247 6.626
2.153 2.245 2.462 2.472 2.398 2.368 2.590 2.472 2.398
5.628 5.844 6.416 6.250 6.629 5.997 6.571 6.250 6.629
2.152 2.246 2.465 2.475 2.401 2.371 2.595 2.475 2.401
5.666 5.881 6.452 6.286 6.665 6.033 6.606 6.286 6.665
2.180 2.273 2.491 2.501 2.427 2.397 2.620 2.501 2.427
5.651 5.866 6.437 6.271 6.650 6.018 6.591 6.271 6.650
2.165 2.258 2.476 2.486 2.412 2.382 2.605 2.486 2.412
5.628 5.842 6.412 6.246 6.625 5.994 6.566 6.246 6.625
2.142 2.234 2.451 2.461 2.387 2.358 2.580 2.461 2.387
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
16mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
PLL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS II
GCLK
tco
PLL
Table 1–91 and Table 1–92 show EP3SL200 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–174
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–91 specifies EP3SL200 Column Pin delay adders when using the regional
clock.
Table 1–91. EP3SL200 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.204
0.036
-0.211
1.904
0.235
0.046
-0.234
1.965
0.378 0.378 0.403 0.392 0.509 0.387 0.411 0.392 0.509
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.078 0.078 -0.047 -0.038 -0.036 0.085 -0.046 -0.038 -0.036 ns
-0.332 -0.328 -0.34 -0.334 -0.464 -0.327 -0.339 -0.334 -0.464 ns
3.193 3.323 3.688 3.496 3.804 3.351 3.716 3.496 3.804
ns
Table 1–92 specifies EP3SL200 Row Pin delay adders when using the regional clock.
Table 1–92. EP3SL200 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL=
0.9V
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
RCLK input adder
0.272
0.14
0.301
0.149
-0.306
-0.15
0.446 0.424 0.473
0.46
0.547 0.454 0.481
0.46
0.547
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.226 0.216 0.235 0.226 0.306 0.232 0.254 0.226 0.306
-0.278
-0.15
-0.418 -0.434 -0.486 -0.472 -0.592 -0.464 -0.493 -0.472 -0.592 ns
-0.227 -0.233 -0.254 -0.243 -0.322 -0.243 -0.258 -0.243 -0.322 ns
EP3SL340 I/O Timing Parameters
Table 1–93 through Table 1–96 show the maximum I/O timing parameters for
EP3SL340 devices for single-ended I/O standards.
Table 1–93 specifies EP3SL340 column pins input timing parameters for single-ended
I/O standards.
Table 1–93. EP3SL340 Column Pins Input Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.469
1.600
0.630
-0.359
-1.469
1.600
0.630
-0.359
-1.445
1.594
0.633
-0.343
-1.445
1.594
0.633
-0.343
-2.196 -2.240 -2.531 -2.574 -2.974 -2.425 -2.680 -2.476 -3.011 ns
GCLK
2.424 2.477 2.791 2.819 3.231 2.670 2.949 2.735 3.269
1.173 1.252 1.305 1.231 1.218 1.246 1.315 1.198 1.271
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-0.708 -0.768 -0.767 -0.728 -0.694 -0.751 -0.765 -0.680 -0.744 ns
-2.196 -2.240 -2.531 -2.574 -2.974 -2.425 -2.680 -2.476 -3.011 ns
tsu
th
GCLK
2.424 2.477 2.791 2.819 3.231 2.670 2.949 2.735 3.269
1.173 1.252 1.305 1.231 1.218 1.246 1.315 1.198 1.271
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-0.708 -0.768 -0.767 -0.728 -0.694 -0.751 -0.765 -0.680 -0.744 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–175
I/O Timing
Table 1–93. EP3SL340 Column Pins Input Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.475
1.606
0.624
-0.353
-1.475
1.606
0.624
-0.353
-1.465
1.596
0.634
-0.363
-1.483
1.616
0.616
-0.343
-1.476
1.609
0.623
-0.350
-1.416
1.549
0.683
-0.410
-1.397
1.530
0.702
-0.429
-1.397
1.530
0.702
-0.429
-1.390
1.523
0.709
-0.436
-1.456
1.605
0.622
-0.332
-1.456
1.605
0.622
-0.332
-1.451
1.600
0.627
-0.337
-1.471
1.622
0.605
-0.313
-1.461
1.612
0.615
-0.323
-1.409
1.560
0.667
-0.375
-1.380
1.531
0.696
-0.404
-1.380
1.531
0.696
-0.404
-1.374
1.525
0.702
-0.410
-2.195 -2.242 -2.530 -2.573 -2.973 -2.425 -2.685 -2.481 -3.016 ns
GCLK
2.423 2.479 2.790 2.818 3.230 2.670 2.954 2.740 3.274
1.174 1.250 1.306 1.232 1.219 1.246 1.310 1.193 1.266
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-0.709 -0.766 -0.768 -0.729 -0.695 -0.751 -0.760 -0.675 -0.739 ns
-2.195 -2.242 -2.530 -2.573 -2.973 -2.425 -2.685 -2.481 -3.016 ns
tsu
th
GCLK
2.423 2.479 2.790 2.818 3.230 2.670 2.954 2.740 3.274
1.174 1.250 1.306 1.232 1.219 1.246 1.310 1.193 1.266
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-0.709 -0.766 -0.768 -0.729 -0.695 -0.751 -0.760 -0.675 -0.739 ns
-2.204 -2.254 -2.549 -2.592 -2.992 -2.435 -2.696 -2.492 -3.027 ns
tsu
th
GCLK
2.432 2.491 2.809 2.837 3.249 2.680 2.965 2.751 3.285
1.165 1.238 1.287 1.213 1.200 1.236 1.299 1.182 1.255
ns
ns
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
-0.700 -0.754 -0.749 -0.710 -0.676 -0.741 -0.749 -0.664 -0.728 ns
-2.244 -2.290 -2.547 -2.590 -2.990 -2.469 -2.699 -2.495 -3.030 ns
tsu
th
GCLK
2.472 2.527 2.807 2.835 3.247 2.714 2.968 2.754 3.288
1.125 1.202 1.289 1.215 1.202 1.202 1.296 1.179 1.252
ns
ns
tsu
th
GCLK
PLL
-0.660 -0.718 -0.751 -0.712 -0.678 -0.707 -0.746 -0.661 -0.725 ns
-2.221 -2.258 -2.477 -2.520 -2.920 -2.438 -2.633 -2.429 -2.964 ns
tsu
th
GCLK
2.449 2.495 2.737 2.765 3.177 2.683 2.902 2.688 3.222
1.148 1.234 1.359 1.285 1.272 1.233 1.362 1.245 1.318
ns
ns
tsu
th
GCLK
PLL
-0.683 -0.750 -0.821 -0.782 -0.748 -0.738 -0.812 -0.727 -0.791 ns
-2.144 -2.159 -2.321 -2.364 -2.764 -2.342 -2.480 -2.276 -2.811 ns
tsu
th
GCLK
2.372 2.396 2.581 2.609 3.021 2.587 2.749 2.535 3.069
1.225 1.333 1.515 1.441 1.428 1.329 1.515 1.398 1.471
ns
ns
tsu
th
GCLK
PLL
-0.760 -0.849 -0.977 -0.938 -0.904 -0.834 -0.965 -0.880 -0.944 ns
-2.116 -2.143 -2.323 -2.366 -2.766 -2.321 -2.476 -2.272 -2.807 ns
tsu
th
GCLK
2.344 2.380 2.583 2.611 3.023 2.566 2.745 2.531 3.065
1.253 1.349 1.513 1.439 1.426 1.350 1.519 1.402 1.475
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-0.788 -0.865 -0.975 -0.936 -0.902 -0.855 -0.969 -0.884 -0.948 ns
-2.116 -2.143 -2.323 -2.366 -2.766 -2.321 -2.476 -2.272 -2.807 ns
tsu
th
GCLK
2.344 2.380 2.583 2.611 3.023 2.566 2.745 2.531 3.065
1.253 1.349 1.513 1.439 1.426 1.350 1.519 1.402 1.475
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-0.788 -0.865 -0.975 -0.936 -0.902 -0.855 -0.969 -0.884 -0.948 ns
-2.104 -2.138 -2.323 -2.361 -2.767 -2.314 -2.477 -2.274 -2.811 ns
tsu
th
GCLK
2.331 2.372 2.580 2.605 3.019 2.556 2.742 2.532 3.064
1.266 1.357 1.516 1.444 1.428 1.357 1.518 1.403 1.474
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-0.801 -0.876 -0.981 -0.942 -0.909 -0.865 -0.972 -0.886 -0.952 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–176
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–93. EP3SL340 Column Pins Input Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.390
1.523
0.709
-0.436
-1.378
1.511
0.721
-0.448
-1.378
1.511
0.721
-0.448
-1.390
1.523
0.709
-0.436
-1.390
1.523
0.709
-0.436
-1.378
1.511
0.721
-0.448
-1.378
1.511
0.721
-0.448
-1.370
1.503
0.729
-0.456
-1.370
1.503
0.729
-0.456
-1.374
1.525
0.702
-0.410
-1.363
1.514
0.713
-0.421
-1.363
1.514
0.713
-0.421
-1.374
1.525
0.702
-0.410
-1.374
1.525
0.702
-0.410
-1.363
1.514
0.713
-0.421
-1.363
1.514
0.713
-0.421
-1.351
1.502
0.725
-0.433
-1.351
1.502
0.725
-0.433
-2.104 -2.138 -2.323 -2.361 -2.767 -2.314 -2.477 -2.274 -2.811 ns
GCLK
2.331 2.372 2.580 2.605 3.019 2.556 2.742 2.532 3.064
1.266 1.357 1.516 1.444 1.428 1.357 1.518 1.403 1.474
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-0.801 -0.876 -0.981 -0.942 -0.909 -0.865 -0.972 -0.886 -0.952 ns
-2.095 -2.127 -2.304 -2.342 -2.748 -2.303 -2.459 -2.256 -2.793 ns
tsu
th
GCLK
2.322 2.361 2.561 2.586 3.000 2.545 2.724 2.514 3.046
1.277 1.368 1.535 1.463 1.447 1.368 1.536 1.421 1.492
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-0.813 -0.887 -1.000 -0.961 -0.928 -0.876 -0.990 -0.904 -0.970 ns
-2.095 -2.127 -2.304 -2.342 -2.748 -2.303 -2.459 -2.256 -2.793 ns
tsu
th
GCLK
2.322 2.361 2.561 2.586 3.000 2.545 2.724 2.514 3.046
1.277 1.368 1.535 1.463 1.447 1.368 1.536 1.421 1.492
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.813 -0.887 -1.000 -0.961 -0.928 -0.876 -0.990 -0.904 -0.970 ns
-2.104 -2.138 -2.323 -2.361 -2.767 -2.314 -2.477 -2.274 -2.811 ns
tsu
th
GCLK
2.331 2.372 2.580 2.605 3.019 2.556 2.742 2.532 3.064
1.266 1.357 1.516 1.444 1.428 1.357 1.518 1.403 1.474
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.801 -0.876 -0.981 -0.942 -0.909 -0.865 -0.972 -0.886 -0.952 ns
-2.104 -2.138 -2.323 -2.361 -2.767 -2.314 -2.477 -2.274 -2.811 ns
tsu
th
GCLK
2.331 2.372 2.580 2.605 3.019 2.556 2.742 2.532 3.064
1.266 1.357 1.516 1.444 1.428 1.357 1.518 1.403 1.474
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.801 -0.876 -0.981 -0.942 -0.909 -0.865 -0.972 -0.886 -0.952 ns
-2.095 -2.127 -2.304 -2.342 -2.748 -2.303 -2.459 -2.256 -2.793 ns
tsu
th
GCLK
2.322 2.361 2.561 2.586 3.000 2.545 2.724 2.514 3.046
1.277 1.368 1.535 1.463 1.447 1.368 1.536 1.421 1.492
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.813 -0.887 -1.000 -0.961 -0.928 -0.876 -0.990 -0.904 -0.970 ns
-2.095 -2.127 -2.304 -2.342 -2.748 -2.303 -2.459 -2.256 -2.793 ns
tsu
th
GCLK
2.322 2.361 2.561 2.586 3.000 2.545 2.724 2.514 3.046
1.277 1.368 1.535 1.463 1.447 1.368 1.536 1.421 1.492
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.813 -0.887 -1.000 -0.961 -0.928 -0.876 -0.990 -0.904 -0.970 ns
-2.085 -2.116 -2.288 -2.326 -2.732 -2.292 -2.444 -2.241 -2.778 ns
tsu
th
GCLK
2.312 2.350 2.545 2.570 2.984 2.534 2.709 2.499 3.031
1.287 1.379 1.551 1.479 1.463 1.379 1.551 1.436 1.507
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.823 -0.898 -1.016 -0.977 -0.944 -0.887 -1.005 -0.919 -0.985 ns
-2.085 -2.116 -2.288 -2.326 -2.732 -2.292 -2.444 -2.241 -2.778 ns
tsu
th
GCLK
2.312 2.350 2.545 2.570 2.984 2.534 2.709 2.499 3.031
1.287 1.379 1.551 1.479 1.463 1.379 1.551 1.436 1.507
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-0.823 -0.898 -1.016 -0.977 -0.944 -0.887 -1.005 -0.919 -0.985 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–177
I/O Timing
Table 1–93. EP3SL340 Column Pins Input Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.475
1.606
0.624
-0.353
-1.456
1.605
0.622
-0.332
-2.195 -2.242 -2.530 -2.573 -2.973 -2.425 -2.685 -2.481 -3.016 ns
GCLK
2.423 2.479 2.790 2.818 3.230 2.670 2.954 2.740 3.274
1.174 1.250 1.306 1.232 1.219 1.246 1.310 1.193 1.266
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-0.709 -0.766 -0.768 -0.729 -0.695 -0.751 -0.760 -0.675 -0.739 ns
Table 1–94 specifies EP3SL340 row pins input timing parameters for single-ended
I/O standards.
Table 1–94. EP3SL340 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.239
1.362
0.879
-0.615
-1.239
1.362
0.879
-0.615
-1.245
1.368
0.873
-0.609
-1.245
1.368
0.873
-0.609
-1.233
1.356
0.885
-0.621
-1.251
1.377
0.827
-0.562
-1.296
1.435
0.945
-0.660
-1.296
1.435
0.945
-0.660
-1.307
1.446
0.934
-0.649
-1.307
1.446
0.934
-0.649
-1.300
1.439
0.941
-0.656
-1.343
1.482
0.910
-0.624
-1.925 -1.956 -2.199 -2.135 -2.587 -1.973 -2.204 -2.142 -2.522
2.137 2.177 2.442 2.366 2.822 2.205 2.456 2.382 2.763
1.670 1.687 1.786 1.680 1.689 1.689 1.807 1.695 1.746
-1.216 -1.217 -1.263 -1.188 -1.178 -1.208 -1.273 -1.193 -1.231
-1.925 -1.956 -2.199 -2.135 -2.587 -1.973 -2.204 -2.142 -2.522
2.137 2.177 2.442 2.366 2.822 2.205 2.456 2.382 2.763
1.670 1.687 1.786 1.680 1.689 1.689 1.807 1.695 1.746
-1.216 -1.217 -1.263 -1.188 -1.178 -1.208 -1.273 -1.193 -1.231
-1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
2.134 2.178 2.445 2.369 2.825 2.204 2.461 2.387 2.768
1.673 1.686 1.783 1.677 1.686 1.690 1.802 1.690 1.741
-1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
-1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
2.134 2.178 2.445 2.369 2.825 2.204 2.461 2.387 2.768
1.673 1.686 1.783 1.677 1.686 1.690 1.802 1.690 1.741
-1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
-1.931 -1.970 -2.217 -2.153 -2.605 -1.981 -2.219 -2.157 -2.537
2.143 2.191 2.460 2.384 2.840 2.213 2.471 2.397 2.778
1.664 1.673 1.768 1.662 1.671 1.681 1.792 1.680 1.731
-1.210 -1.203 -1.245 -1.170 -1.160 -1.200 -1.258 -1.178 -1.216
-1.980 -1.995 -2.204 -2.138 -2.582 -2.003 -2.208 -2.153 -2.621
2.193 2.216 2.447 2.369 2.817 2.234 2.461 2.393 2.859
1.624 1.634 1.857 1.742 1.565 1.620 1.886 1.762 1.619
-1.170 -1.164 -1.330 -1.246 -1.060 -1.140 -1.347 -1.255 -1.107
GCLK
3.3-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
2.5 V
1.8 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–178
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–94. EP3SL340 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.241
1.367
0.837
-0.572
-1.181
1.307
0.897
-0.632
-1.176
1.300
0.942
-0.677
-1.176
1.300
0.942
-0.677
-1.155
1.281
0.923
-0.658
-1.155
1.281
0.923
-0.658
-1.141
1.267
0.937
-0.672
-1.155
1.281
0.923
-0.658
-1.155
1.281
0.923
-0.658
-1.332
1.471
0.921
-0.635
-1.279
1.418
0.974
-0.688
-1.242
1.382
1.000
-0.714
-1.242
1.382
1.000
-0.714
-1.244
1.383
1.009
-0.723
-1.244
1.383
1.009
-0.723
-1.232
1.371
1.021
-0.735
-1.244
1.383
1.009
-0.723
-1.244
1.383
1.009
-0.723
-1.956 -1.963 -2.136 -2.070 -2.514 -1.972 -2.143 -2.088 -2.556
2.169 2.184 2.379 2.301 2.749 2.203 2.396 2.328 2.794
1.648 1.666 1.925 1.810 1.633 1.651 1.951 1.827 1.684
-1.194 -1.196 -1.398 -1.314 -1.128 -1.171 -1.412 -1.320 -1.172
-1.877 -1.862 -1.977 -1.911 -2.355 -1.876 -1.988 -1.933 -2.401
2.090 2.083 2.220 2.142 2.590 2.107 2.241 2.173 2.639
1.727 1.767 2.084 1.969 1.792 1.747 2.106 1.982 1.839
-1.273 -1.297 -1.557 -1.473 -1.287 -1.267 -1.567 -1.475 -1.327
-1.845 -1.861 -1.997 -1.933 -2.385 -1.869 -2.002 -1.940 -2.320
2.057 2.082 2.240 2.164 2.620 2.101 2.254 2.180 2.561
1.750 1.782 1.988 1.882 1.891 1.793 2.009 1.897 1.948
-1.296 -1.312 -1.465 -1.390 -1.380 -1.312 -1.475 -1.395 -1.433
-1.845 -1.861 -1.997 -1.933 -2.385 -1.869 -2.002 -1.940 -2.320
2.057 2.082 2.240 2.164 2.620 2.101 2.254 2.180 2.561
1.750 1.782 1.988 1.882 1.891 1.793 2.009 1.897 1.948
-1.296 -1.312 -1.465 -1.390 -1.380 -1.312 -1.475 -1.395 -1.433
-1.839 -1.835 -1.972 -1.905 -2.351 -1.844 -1.981 -1.925 -2.394
2.052 2.054 2.213 2.135 2.582 2.073 2.231 2.164 2.628
1.765 1.794 2.086 1.972 1.796 1.779 2.110 1.988 1.846
-1.311 -1.326 -1.562 -1.478 -1.295 -1.301 -1.574 -1.482 -1.338
-1.839 -1.835 -1.972 -1.905 -2.351 -1.844 -1.981 -1.925 -2.394
2.052 2.054 2.213 2.135 2.582 2.073 2.231 2.164 2.628
1.765 1.794 2.086 1.972 1.796 1.779 2.110 1.988 1.846
-1.311 -1.326 -1.562 -1.478 -1.295 -1.301 -1.574 -1.482 -1.338
-1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377
2.038 2.044 2.195 2.117 2.564 2.062 2.214 2.147 2.611
1.778 1.804 2.104 1.990 1.814 1.790 2.127 2.005 1.863
-1.323 -1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355
-1.839 -1.835 -1.972 -1.905 -2.351 -1.844 -1.981 -1.925 -2.394
2.052 2.054 2.213 2.135 2.582 2.073 2.231 2.164 2.628
1.765 1.794 2.086 1.972 1.796 1.779 2.110 1.988 1.846
-1.311 -1.326 -1.562 -1.478 -1.295 -1.301 -1.574 -1.482 -1.338
-1.839 -1.835 -1.972 -1.905 -2.351 -1.844 -1.981 -1.925 -2.394
2.052 2.054 2.213 2.135 2.582 2.073 2.231 2.164 2.628
1.765 1.794 2.086 1.972 1.796 1.779 2.110 1.988 1.846
-1.311 -1.326 -1.562 -1.478 -1.295 -1.301 -1.574 -1.482 -1.338
GCLK
1.5 V
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2 V
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-15
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–179
I/O Timing
Table 1–94. EP3SL340 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.141
1.267
0.937
-0.672
-1.141
1.267
0.937
-0.672
-1.132
1.258
0.946
-0.681
-1.132
1.258
0.946
-0.681
-1.245
1.368
0.873
-0.609
-1.245
1.368
0.873
-0.609
-1.232
1.371
1.021
-0.735
-1.232
1.371
1.021
-0.735
-1.220
1.359
1.033
-0.747
-1.220
1.359
1.033
-0.747
-1.307
1.446
0.934
-0.649
-1.307
1.446
0.934
-0.649
-1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377
2.038 2.044 2.195 2.117 2.564 2.062 2.214 2.147 2.611
1.778 1.804 2.104 1.990 1.814 1.790 2.127 2.005 1.863
-1.323 -1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355
-1.824 -1.825 -1.954 -1.887 -2.333 -1.833 -1.964 -1.908 -2.377
2.038 2.044 2.195 2.117 2.564 2.062 2.214 2.147 2.611
1.778 1.804 2.104 1.990 1.814 1.790 2.127 2.005 1.863
-1.323 -1.336 -1.580 -1.496 -1.313 -1.312 -1.591 -1.499 -1.355
-1.815 -1.815 -1.938 -1.871 -2.317 -1.824 -1.948 -1.892 -2.361
2.029 2.034 2.179 2.101 2.548 2.053 2.198 2.131 2.595
1.787 1.814 2.120 2.006 1.830 1.799 2.143 2.021 1.879
-1.332 -1.346 -1.596 -1.512 -1.329 -1.321 -1.607 -1.515 -1.371
-1.815 -1.815 -1.938 -1.871 -2.317 -1.824 -1.948 -1.892 -2.361
2.029 2.034 2.179 2.101 2.548 2.053 2.198 2.131 2.595
1.787 1.814 2.120 2.006 1.830 1.799 2.143 2.021 1.879
-1.332 -1.346 -1.596 -1.512 -1.329 -1.321 -1.607 -1.515 -1.371
-1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
2.134 2.178 2.445 2.369 2.825 2.204 2.461 2.387 2.768
1.673 1.686 1.783 1.677 1.686 1.690 1.802 1.690 1.741
-1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
-1.922 -1.957 -2.202 -2.138 -2.590 -1.972 -2.209 -2.147 -2.527
2.134 2.178 2.445 2.369 2.825 2.204 2.461 2.387 2.768
1.673 1.686 1.783 1.677 1.686 1.690 1.802 1.690 1.741
-1.219 -1.216 -1.260 -1.185 -1.175 -1.209 -1.268 -1.188 -1.226
GCLK
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
PCI-X
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–180
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–95 specifies EP3SL340 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–95. EP3SL340 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.593
1.692
3.514
1.613
3.484
1.583
3.470
1.569
3.530
1.629
3.459
1.558
3.435
1.534
3.428
1.527
3.590
1.689
3.523
1.622
3.485
1.584
3.463
1.562
3.920
1.892
3.831
1.803
3.799
1.771
3.785
1.757
3.853
1.825
3.776
1.748
3.748
1.720
3.741
1.713
3.929
1.901
3.844
1.816
3.807
1.779
3.780
1.752
5.689 5.892 6.444 6.307 6.698 5.998 6.612 6.451 6.779
2.426 2.517 2.749 2.744 2.731 2.634 2.865 2.862 2.726
5.585 5.780 6.327 6.190 6.581 5.882 6.492 6.331 6.659
2.322 2.405 2.632 2.627 2.614 2.518 2.745 2.742 2.606
5.518 5.710 6.257 6.120 6.511 5.812 6.425 6.264 6.592
2.255 2.335 2.562 2.557 2.544 2.448 2.678 2.674 2.539
5.497 5.687 6.229 6.092 6.483 5.786 6.391 6.231 6.559
2.234 2.312 2.534 2.529 2.516 2.422 2.644 2.640 2.505
5.616 5.809 6.356 6.219 6.610 5.912 6.524 6.363 6.691
2.353 2.434 2.661 2.657 2.643 2.548 2.777 2.774 2.638
5.494 5.683 6.225 6.088 6.479 5.782 6.387 6.226 6.554
2.231 2.308 2.530 2.525 2.512 2.418 2.640 2.636 2.501
5.465 5.656 6.200 6.063 6.454 5.755 6.362 6.201 6.529
2.202 2.281 2.505 2.499 2.487 2.391 2.615 2.610 2.476
5.457 5.647 6.191 6.054 6.445 5.745 6.352 6.192 6.520
2.194 2.272 2.496 2.490 2.478 2.381 2.605 2.600 2.466
5.723 5.928 6.483 6.346 6.737 6.036 6.654 6.493 6.821
2.460 2.553 2.788 2.803 2.770 2.672 2.907 2.903 2.768
5.619 5.816 6.367 6.230 6.621 5.922 6.535 6.375 6.703
2.356 2.441 2.672 2.709 2.654 2.558 2.788 2.785 2.649
5.551 5.745 6.293 6.156 6.547 5.848 6.459 6.299 6.627
2.288 2.370 2.598 2.645 2.580 2.484 2.712 2.708 2.573
5.516 5.706 6.251 6.114 6.505 5.808 6.416 6.255 6.583
2.253 2.331 2.556 2.622 2.538 2.444 2.669 2.665 2.530
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVTTL
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVTTL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–181
I/O Timing
Table 1–95. EP3SL340 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.545
1.644
3.472
1.571
3.448
1.547
3.448
1.547
3.649
1.748
3.566
1.665
3.510
1.609
3.477
1.576
3.869
1.841
3.790
1.762
3.761
1.733
3.761
1.733
3.984
1.956
3.891
1.863
3.847
1.819
3.801
1.773
5.653 5.850 6.402 6.265 6.656 5.956 6.572 6.411 6.739
2.390 2.475 2.707 2.745 2.689 2.592 2.825 2.821 2.686
5.529 5.721 6.267 6.130 6.521 5.823 6.432 6.272 6.600
2.266 2.346 2.572 2.635 2.554 2.459 2.685 2.681 2.546
5.490 5.681 6.226 6.089 6.480 5.783 6.391 6.230 6.558
2.227 2.306 2.531 2.601 2.513 2.419 2.644 2.640 2.505
5.482 5.672 6.216 6.079 6.470 5.772 6.379 6.218 6.546
2.219 2.297 2.521 2.609 2.503 2.408 2.632 2.627 2.493
5.860 6.077 6.649 6.512 6.903 6.189 6.827 6.666 6.994
2.597 2.702 2.954 2.953 2.936 2.825 3.080 3.075 2.941
5.741 5.951 6.517 6.380 6.771 6.061 6.691 6.530 6.858
2.478 2.576 2.822 2.829 2.804 2.697 2.944 2.940 2.805
5.649 5.855 6.417 6.280 6.671 5.963 6.589 6.428 6.756
2.386 2.480 2.722 2.751 2.704 2.599 2.842 2.838 2.703
5.615 5.818 6.376 6.239 6.630 5.923 6.545 6.384 6.712
2.352 2.443 2.681 2.694 2.663 2.559 2.798 2.794 2.659
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
2.5 V
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–182
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–95. EP3SL340 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.763
1.862
3.665
1.764
3.583
1.682
3.557
1.656
3.486
1.585
3.481
1.580
3.703
1.802
3.572
1.671
3.527
1.626
3.516
1.615
3.481
1.580
3.477
1.576
4.112
2.084
4.001
1.973
3.914
1.886
3.881
1.853
3.817
1.789
3.807
1.779
4.079
2.051
3.898
1.870
3.861
1.833
3.855
1.827
3.804
1.776
3.797
1.769
6.054 6.286 6.867 6.730 7.121 6.407 7.053 6.892 7.220
2.791 2.911 3.172 3.171 3.154 3.043 3.306 3.303 3.167
5.902 6.128 6.706 6.569 6.960 6.248 6.887 6.726 7.054
2.639 2.753 3.011 3.019 2.993 2.884 3.140 3.137 3.001
5.775 5.990 6.562 6.425 6.816 6.104 6.739 6.579 6.907
2.512 2.615 2.867 2.878 2.849 2.740 2.992 2.988 2.853
5.715 5.924 6.487 6.350 6.741 6.033 6.659 6.498 6.826
2.452 2.549 2.792 2.799 2.774 2.669 2.912 2.908 2.773
5.627 5.830 6.388 6.251 6.642 5.936 6.558 6.397 6.725
2.364 2.455 2.693 2.717 2.675 2.572 2.811 2.807 2.672
5.621 5.824 6.381 6.244 6.635 5.929 6.551 6.390 6.718
2.358 2.449 2.686 2.711 2.668 2.565 2.804 2.800 2.665
5.993 6.213 6.795 6.658 7.049 6.337 6.986 6.825 7.153
2.730 2.838 3.100 3.110 3.082 2.973 3.239 3.236 3.100
5.749 5.959 6.524 6.387 6.778 6.069 6.699 6.539 6.867
2.486 2.584 2.829 2.841 2.811 2.705 2.952 2.948 2.813
5.669 5.879 6.444 6.307 6.698 5.989 6.616 6.456 6.784
2.406 2.504 2.749 2.779 2.731 2.625 2.869 2.865 2.730
5.663 5.871 6.435 6.298 6.689 5.982 6.609 6.448 6.776
2.400 2.496 2.740 2.772 2.722 2.618 2.862 2.857 2.723
5.615 5.818 6.374 6.237 6.628 5.923 6.544 6.383 6.711
2.352 2.443 2.679 2.713 2.661 2.559 2.797 2.793 2.658
5.594 5.797 6.354 6.217 6.608 5.902 6.522 6.362 6.690
2.331 2.422 2.659 2.710 2.641 2.538 2.775 2.771 2.636
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.8 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–183
I/O Timing
Table 1–95. EP3SL340 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.683
1.782
3.560
1.659
3.507
1.606
3.487
1.586
3.500
1.599
3.503
1.602
3.485
1.584
3.480
1.579
3.518
1.617
3.499
1.598
3.500
1.599
3.483
1.582
3.480
1.579
4.022
1.994
3.887
1.859
3.846
1.818
3.812
1.784
3.820
1.792
3.823
1.795
3.803
1.775
3.796
1.768
3.840
1.812
3.819
1.791
3.822
1.794
3.802
1.774
3.798
1.770
5.947 6.167 6.738 6.601 6.992 6.284 6.920 6.759 7.087
2.684 2.792 3.043 3.056 3.025 2.920 3.173 3.171 3.034
5.728 5.936 6.498 6.361 6.752 6.045 6.671 6.511 6.839
2.465 2.561 2.803 2.832 2.785 2.681 2.924 2.920 2.785
5.652 5.859 6.424 6.287 6.678 5.970 6.599 6.438 6.766
2.389 2.484 2.729 2.778 2.711 2.606 2.852 2.847 2.713
5.613 5.816 6.374 6.237 6.628 5.921 6.542 6.381 6.709
2.350 2.441 2.679 2.743 2.661 2.557 2.795 2.791 2.656
5.621 5.824 6.382 6.245 6.636 5.926 6.547 6.386 6.714
2.358 2.449 2.687 2.735 2.669 2.562 2.800 2.795 2.661
5.625 5.828 6.386 6.249 6.640 5.930 6.551 6.390 6.718
2.362 2.453 2.691 2.741 2.673 2.566 2.804 2.799 2.665
5.603 5.806 6.364 6.227 6.618 5.909 6.529 6.368 6.696
2.340 2.431 2.669 2.714 2.651 2.545 2.782 2.777 2.643
5.588 5.790 6.347 6.210 6.601 5.892 6.511 6.351 6.679
2.325 2.415 2.652 2.712 2.634 2.528 2.764 2.759 2.625
5.644 5.847 6.405 6.268 6.659 5.950 6.571 6.410 6.738
2.381 2.472 2.710 2.765 2.692 2.586 2.824 2.818 2.685
5.622 5.825 6.383 6.246 6.637 5.928 6.548 6.387 6.715
2.359 2.450 2.688 2.741 2.670 2.564 2.801 2.796 2.662
5.630 5.834 6.393 6.256 6.647 5.938 6.559 6.398 6.726
2.367 2.459 2.698 2.761 2.680 2.574 2.812 2.807 2.673
5.605 5.809 6.368 6.231 6.622 5.912 6.533 6.373 6.701
2.342 2.434 2.673 2.736 2.655 2.548 2.786 2.782 2.647
5.601 5.805 6.363 6.226 6.617 5.908 6.529 6.369 6.697
2.338 2.430 2.668 2.731 2.650 2.544 2.782 2.778 2.643
2mA
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
1.2 V
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS I
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–184
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–95. EP3SL340 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.480
1.579
3.479
1.578
3.510
1.609
3.495
1.594
3.482
1.581
3.482
1.581
3.478
1.577
3.496
1.595
3.495
1.594
3.797
1.769
3.797
1.769
3.831
1.803
3.815
1.787
3.800
1.772
3.801
1.773
3.796
1.768
3.813
1.785
3.813
1.785
5.589 5.790 6.347 6.210 6.601 5.893 6.512 6.351 6.679
2.326 2.415 2.652 2.716 2.634 2.529 2.765 2.760 2.626
5.597 5.800 6.359 6.222 6.613 5.903 6.525 6.364 6.692
2.334 2.425 2.664 2.723 2.646 2.539 2.778 2.773 2.639
5.637 5.840 6.397 6.260 6.651 5.943 6.563 6.402 6.730
2.374 2.465 2.702 2.758 2.684 2.579 2.816 2.811 2.677
5.623 5.827 6.385 6.248 6.639 5.930 6.552 6.391 6.719
2.360 2.452 2.690 2.754 2.672 2.566 2.805 2.800 2.666
5.603 5.806 6.365 6.228 6.619 5.910 6.531 6.370 6.698
2.340 2.431 2.670 2.736 2.652 2.546 2.784 2.779 2.645
5.604 5.808 6.368 6.231 6.622 5.912 6.534 6.373 6.701
2.341 2.433 2.673 2.747 2.655 2.548 2.787 2.782 2.648
5.597 5.801 6.360 6.223 6.614 5.904 6.526 6.365 6.693
2.334 2.426 2.665 2.739 2.647 2.540 2.779 2.774 2.640
5.605 5.806 6.362 6.225 6.616 5.908 6.527 6.366 6.694
2.342 2.431 2.667 2.727 2.649 2.544 2.780 2.775 2.641
5.609 5.811 6.368 6.231 6.622 5.913 6.533 6.372 6.700
2.346 2.436 2.673 2.745 2.655 2.549 2.786 2.781 2.647
8mA
GCLK
tco
PLL
SSTL-18
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-15
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
SSTL-15
CLASS II
GCLK tco
16mA
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–185
I/O Timing
Table 1–95. EP3SL340 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.482
1.581
3.477
1.576
3.479
1.578
3.478
1.577
3.497
1.596
3.492
1.591
3.491
1.590
3.482
1.581
3.483
1.582
3.505
1.604
3.495
1.594
3.493
1.592
3.799
1.771
3.794
1.766
3.797
1.769
3.795
1.767
3.814
1.786
3.810
1.782
3.809
1.781
3.799
1.771
3.801
1.773
3.826
1.798
3.814
1.786
3.812
1.784
5.593 5.795 6.352 6.215 6.606 5.897 6.517 6.356 6.684
2.330 2.420 2.657 2.727 2.639 2.533 2.770 2.765 2.631
5.587 5.789 6.346 6.209 6.600 5.891 6.511 6.350 6.678
2.324 2.414 2.651 2.716 2.633 2.527 2.764 2.759 2.625
5.592 5.794 6.352 6.215 6.606 5.897 6.517 6.357 6.685
2.329 2.419 2.657 2.737 2.639 2.533 2.770 2.765 2.631
5.585 5.787 6.344 6.207 6.598 5.889 6.508 6.348 6.676
2.322 2.412 2.649 2.718 2.631 2.525 2.761 2.756 2.622
5.607 5.808 6.365 6.228 6.619 5.911 6.529 6.369 6.697
2.344 2.433 2.670 2.732 2.652 2.547 2.782 2.777 2.643
5.605 5.807 6.364 6.227 6.618 5.910 6.529 6.368 6.696
2.342 2.432 2.669 2.739 2.651 2.546 2.782 2.777 2.643
5.606 5.808 6.365 6.228 6.619 5.911 6.530 6.369 6.697
2.343 2.433 2.670 2.740 2.652 2.547 2.783 2.778 2.644
5.593 5.796 6.353 6.216 6.607 5.898 6.518 6.357 6.685
2.330 2.421 2.658 2.727 2.640 2.534 2.771 2.766 2.632
5.599 5.802 6.361 6.224 6.615 5.905 6.526 6.366 6.694
2.336 2.427 2.666 2.742 2.648 2.541 2.779 2.774 2.640
5.627 5.829 6.387 6.250 6.641 5.933 6.553 6.393 6.721
2.364 2.454 2.692 2.760 2.674 2.569 2.806 2.801 2.667
5.615 5.818 6.376 6.239 6.630 5.921 6.542 6.381 6.709
2.352 2.443 2.681 2.750 2.663 2.557 2.795 2.790 2.656
5.613 5.816 6.374 6.237 6.628 5.920 6.541 6.380 6.708
2.350 2.441 2.679 2.755 2.661 2.556 2.794 2.789 2.655
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS II
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–186
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–95. EP3SL340 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.491
1.590
3.487
1.586
3.564
1.663
3.564
1.663
3.593
1.692
3.514
1.613
3.484
1.583
3.470
1.569
3.810
1.782
3.806
1.778
3.881
1.853
3.881
1.853
3.920
1.892
3.831
1.803
3.799
1.771
3.785
1.757
5.612 5.816 6.374 6.237 6.628 5.919 6.541 6.380 6.708
2.349 2.441 2.679 2.757 2.661 2.555 2.794 2.788 2.655
5.605 5.809 6.367 6.230 6.621 5.912 6.533 6.373 6.701
2.342 2.434 2.672 2.748 2.654 2.548 2.786 2.781 2.647
5.623 5.817 6.364 6.227 6.618 5.920 6.531 6.370 6.698
2.360 2.442 2.669 2.724 2.651 2.556 2.784 2.780 2.645
5.623 5.817 6.364 6.227 6.618 5.920 6.531 6.370 6.698
2.360 2.442 2.669 2.724 2.651 2.556 2.784 2.780 2.645
5.689 5.892 6.444 6.307 6.698 5.998 6.612 6.451 6.779
2.426 2.517 2.749 2.744 2.731 2.634 2.865 2.862 2.726
5.585 5.780 6.327 6.190 6.581 5.882 6.492 6.331 6.659
2.322 2.405 2.632 2.627 2.614 2.518 2.745 2.742 2.606
5.518 5.710 6.257 6.120 6.511 5.812 6.425 6.264 6.592
2.255 2.335 2.562 2.557 2.544 2.448 2.678 2.674 2.539
5.497 5.687 6.229 6.092 6.483 5.786 6.391 6.231 6.559
2.234 2.312 2.534 2.529 2.516 2.422 2.644 2.640 2.505
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–187
I/O Timing
Table 1–96 specifies EP3SL340 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–96. EP3SL340 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.781
1.782
3.681
1.677
3.592
1.575
3.785
1.786
3.596
1.579
3.727
1.728
3.601
1.601
3.563
1.550
3.646
1.647
3.547
1.530
3.763
1.764
3.665
1.666
3.603
1.589
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.479
1.562
3.413
1.496
3.334
1.417
3.481
1.564
3.338
1.421
3.440
1.523
3.339
1.422
3.302
1.385
3.361
1.444
3.289
1.372
3.466
1.549
3.381
1.464
3.324
1.407
5.469 5.657 6.238 6.095 6.481 5.741 6.370 6.120 6.565
2.243 2.285 2.559 2.570 2.578 2.386 2.666 2.671 2.594
5.339 5.519 6.093 5.950 6.336 5.628 6.221 6.005 6.416
2.113 2.174 2.414 2.425 2.433 2.273 2.517 2.522 2.445
5.220 5.398 5.965 5.822 6.208 5.529 6.089 5.905 6.284
1.994 2.074 2.286 2.297 2.305 2.174 2.385 2.390 2.313
5.477 5.662 6.242 6.099 6.485 5.749 6.374 6.132 6.569
2.251 2.291 2.563 2.574 2.582 2.394 2.670 2.675 2.598
5.226 5.413 5.971 5.828 6.214 5.541 6.096 5.914 6.291
2.000 2.089 2.292 2.303 2.311 2.186 2.392 2.397 2.320
5.421 5.610 6.194 6.051 6.437 5.709 6.328 6.086 6.523
2.195 2.254 2.515 2.526 2.534 2.354 2.624 2.629 2.552
5.269 5.451 6.030 5.887 6.273 5.567 6.164 5.940 6.358
2.043 2.112 2.351 2.362 2.370 2.212 2.460 2.464 2.387
5.188 5.371 5.942 5.799 6.185 5.499 6.071 5.867 6.265
1.961 2.047 2.263 2.274 2.282 2.144 2.367 2.371 2.294
5.316 5.503 6.084 5.941 6.327 5.600 6.217 5.976 6.411
2.090 2.147 2.405 2.416 2.424 2.245 2.513 2.517 2.440
5.161 5.342 5.903 5.760 6.146 5.469 6.031 5.838 6.225
1.926 2.018 2.224 2.235 2.243 2.114 2.327 2.331 2.254
5.554 5.764 6.366 6.223 6.609 5.841 6.507 6.238 6.701
2.328 2.380 2.687 2.698 2.706 2.486 2.803 2.807 2.730
5.399 5.601 6.196 6.053 6.439 5.704 6.333 6.093 6.527
2.173 2.245 2.517 2.528 2.536 2.349 2.629 2.633 2.556
5.288 5.483 6.070 5.927 6.313 5.615 6.203 5.999 6.397
2.062 2.159 2.391 2.402 2.410 2.260 2.499 2.503 2.426
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
GCLK
PLL
3.3-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–188
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–96. EP3SL340 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.942
1.925
3.756
1.739
3.674
1.657
3.654
1.637
3.885
1.868
3.671
1.654
3.645
1.628
3.634
1.617
3.798
1.781
3.675
1.658
3.591
1.575
3.587
1.570
3.576
1.559
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.692
1.785
3.519
1.562
3.444
1.495
3.426
1.469
3.634
1.696
3.442
1.485
3.415
1.458
3.396
1.439
3.564
1.639
3.447
1.490
3.328
1.411
3.323
1.406
3.314
1.397
5.817 6.193 6.841 6.698 7.084 6.248 6.991 6.682 7.186
2.574 2.860 3.162 3.173 3.192 2.985 3.287 3.292 3.203
5.527 5.824 6.436 6.293 6.679 5.922 6.585 6.320 6.779
2.284 2.491 2.757 2.768 2.787 2.620 2.881 2.885 2.796
5.427 5.674 6.277 6.134 6.520 5.808 6.412 6.215 6.607
2.184 2.341 2.598 2.609 2.628 2.452 2.708 2.713 2.624
5.370 5.595 6.180 6.037 6.423 5.752 6.318 6.143 6.513
2.127 2.259 2.501 2.512 2.531 2.361 2.614 2.619 2.530
5.745 6.106 6.769 6.626 7.012 6.169 6.915 6.617 7.110
2.502 2.773 3.090 3.101 3.120 2.892 3.211 3.216 3.127
5.423 5.669 6.278 6.135 6.521 5.805 6.411 6.216 6.606
2.180 2.336 2.599 2.610 2.629 2.446 2.707 2.712 2.623
5.355 5.587 6.172 6.029 6.415 5.745 6.306 6.143 6.501
2.112 2.251 2.493 2.504 2.523 2.354 2.602 2.607 2.518
5.338 5.562 6.153 6.010 6.396 5.721 6.284 6.124 6.479
2.095 2.226 2.474 2.485 2.504 2.330 2.580 2.585 2.496
5.666 6.020 6.694 6.551 6.937 6.100 6.831 6.548 7.026
2.423 2.687 3.015 3.026 3.045 2.804 3.127 3.132 3.043
5.440 5.697 6.319 6.176 6.562 5.834 6.453 6.260 6.648
2.197 2.364 2.640 2.651 2.670 2.471 2.749 2.754 2.665
5.278 5.474 6.038 5.895 6.281 5.602 6.165 5.985 6.360
2.039 2.150 2.359 2.370 2.378 2.247 2.461 2.466 2.389
5.275 5.472 6.030 5.887 6.273 5.601 6.158 5.984 6.353
2.032 2.148 2.351 2.362 2.370 2.246 2.454 2.459 2.382
5.260 5.456 6.003 5.860 6.246 5.584 6.131 5.966 6.326
2.017 2.132 2.324 2.335 2.343 2.229 2.427 2.432 2.355
2mA
4mA
6mA
8mA
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
1.8 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-2
CLASS I
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–189
I/O Timing
Table 1–96. EP3SL340 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.598
1.581
3.593
1.576
3.582
1.565
3.571
1.554
3.570
1.553
3.577
1.560
3.580
1.563
3.601
1.584
3.587
1.570
3.575
1.558
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.375
1.418
3.370
1.413
3.359
1.402
3.348
1.391
3.348
1.391
3.356
1.399
3.357
1.400
3.378
1.421
3.364
1.407
3.353
1.396
5.289 5.499 6.054 5.911 6.297 5.651 6.181 6.034 6.376
2.046 2.163 2.375 2.386 2.405 2.260 2.477 2.482 2.393
5.287 5.498 6.052 5.909 6.295 5.649 6.179 6.032 6.374
2.044 2.162 2.373 2.384 2.403 2.258 2.475 2.480 2.391
5.277 5.488 6.035 5.895 6.278 5.640 6.163 6.023 6.358
2.034 2.152 2.356 2.367 2.386 2.249 2.459 2.464 2.375
5.264 5.475 6.020 5.882 6.263 5.628 6.148 6.011 6.343
2.021 2.139 2.341 2.352 2.371 2.237 2.444 2.449 2.360
5.264 5.475 6.019 5.882 6.262 5.627 6.147 6.011 6.342
2.021 2.139 2.340 2.351 2.370 2.236 2.443 2.448 2.359
5.263 5.472 6.013 5.877 6.256 5.623 6.140 6.005 6.335
2.020 2.136 2.334 2.345 2.364 2.232 2.436 2.441 2.352
5.269 5.480 6.015 5.887 6.258 5.632 6.144 6.016 6.339
2.026 2.144 2.336 2.347 2.366 2.241 2.440 2.445 2.356
5.298 5.510 6.071 5.928 6.314 5.661 6.197 6.046 6.392
2.055 2.174 2.392 2.403 2.422 2.270 2.493 2.498 2.409
5.287 5.500 6.054 5.911 6.297 5.652 6.181 6.037 6.376
2.044 2.164 2.375 2.386 2.405 2.261 2.477 2.482 2.393
5.274 5.487 6.036 5.896 6.279 5.639 6.164 6.024 6.359
2.031 2.151 2.357 2.368 2.387 2.248 2.460 2.465 2.376
4mA
6mA
8mA
10mA
12mA
8mA
16mA
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-18
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–190
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–96. EP3SL340 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.583
1.566
3.577
1.560
3.569
1.552
3.571
1.554
3.568
1.551
3.576
1.559
3.589
1.572
3.584
1.567
3.580
1.563
3.591
1.574
3.583
1.566
3.583
1.566
3.697
1.680
3.697
1.680
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.363
1.406
3.356
1.399
3.347
1.390
3.350
1.393
3.346
1.389
3.354
1.397
3.369
1.412
3.363
1.406
3.359
1.402
3.371
1.414
3.362
1.405
3.361
1.404
3.434
1.517
3.434
1.517
5.262 5.470 6.016 5.875 6.259 5.622 6.143 6.002 6.338
2.019 2.134 2.337 2.348 2.367 2.231 2.439 2.444 2.355
5.260 5.469 6.008 5.874 6.251 5.621 6.136 6.002 6.331
2.017 2.133 2.329 2.340 2.359 2.230 2.432 2.437 2.348
5.253 5.462 6.000 5.867 6.243 5.614 6.128 5.995 6.323
2.010 2.126 2.321 2.332 2.351 2.223 2.424 2.429 2.340
5.256 5.465 6.003 5.871 6.246 5.617 6.131 5.998 6.326
2.013 2.129 2.324 2.335 2.354 2.226 2.427 2.432 2.343
5.258 5.468 6.003 5.874 6.246 5.620 6.132 6.003 6.327
2.015 2.132 2.324 2.335 2.354 2.229 2.428 2.433 2.344
5.256 5.465 5.994 5.870 6.237 5.616 6.121 5.997 6.316
2.013 2.129 2.315 2.326 2.345 2.225 2.417 2.422 2.333
5.271 5.480 6.031 5.888 6.274 5.631 6.157 6.013 6.352
2.028 2.144 2.352 2.363 2.382 2.240 2.453 2.458 2.369
5.272 5.482 6.027 5.888 6.270 5.633 6.154 6.016 6.349
2.029 2.146 2.348 2.359 2.378 2.242 2.450 2.455 2.366
5.267 5.477 6.021 5.883 6.264 5.628 6.148 6.010 6.343
2.024 2.141 2.342 2.353 2.372 2.237 2.444 2.449 2.360
5.284 5.496 6.049 5.906 6.292 5.647 6.174 6.032 6.369
2.041 2.160 2.370 2.381 2.400 2.256 2.470 2.475 2.386
5.275 5.487 6.037 5.896 6.280 5.638 6.163 6.023 6.358
2.032 2.151 2.358 2.369 2.388 2.247 2.459 2.464 2.375
5.282 5.495 6.043 5.905 6.286 5.647 6.170 6.033 6.365
2.039 2.159 2.364 2.375 2.394 2.256 2.466 2.471 2.382
5.330 5.520 6.047 5.904 6.299 5.650 6.177 6.027 6.372
2.087 2.196 2.378 2.386 2.387 2.295 2.482 2.493 2.401
5.330 5.520 6.047 5.904 6.299 5.650 6.177 6.027 6.372
2.087 2.196 2.378 2.386 2.387 2.295 2.482 2.493 2.401
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
—
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
1.5-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–191
I/O Timing
Table 1–97 through Table 1–100 show the maximum I/O timing parameters for
EP3SL340 devices for differential I/O standards.
Table 1–97 specifies EP3SL340 column pins input timing parameters for differential
I/O standards.
Table 1–97. EP3SL340 Column Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.278
1.414
0.857
-0.582
-1.278
1.414
0.857
-0.582
-1.278
1.414
0.857
-0.582
-1.094
1.223
1.041
-0.773
-1.094
1.223
1.041
-0.773
-1.102
1.231
1.033
-0.765
-1.102
1.231
1.033
-0.765
-1.114
1.243
1.021
-0.753
-1.335
1.489
0.885
-0.589
-1.335
1.489
0.885
-0.589
-1.335
1.489
0.885
-0.589
-1.158
1.304
1.062
-0.774
-1.158
1.304
1.062
-0.774
-1.170
1.316
1.050
-0.762
-1.170
1.316
1.050
-0.762
-1.181
1.327
1.039
-0.751
-1.674 -1.607 -1.788 -1.721 -2.204 -1.580 -2.013 -1.689 -2.242
1.926 1.873 2.080 2.002 2.485 1.857 2.327 1.981 2.527
1.872 2.050 2.211 2.107 1.975 2.104 2.409 2.165 2.031
-1.382 -1.537 -1.640 -1.565 -1.423 -1.579 -1.804 -1.612 -1.474
-1.674 -1.607 -1.788 -1.721 -2.204 -1.580 -2.013 -1.689 -2.242
1.926 1.873 2.080 2.002 2.485 1.857 2.327 1.981 2.527
1.872 2.050 2.211 2.107 1.975 2.104 2.409 2.165 2.031
-1.382 -1.537 -1.640 -1.565 -1.423 -1.579 -1.804 -1.612 -1.474
-1.674 -1.607 -1.788 -1.721 -2.204 -1.580 -2.013 -1.689 -2.242
1.926 1.873 2.080 2.002 2.485 1.857 2.327 1.981 2.527
1.872 2.050 2.211 2.107 1.975 2.104 2.409 2.165 2.031
-1.382 -1.537 -1.640 -1.565 -1.423 -1.579 -1.804 -1.612 -1.474
-1.787 -1.806 -1.947 -1.875 -2.353 -1.815 -1.953 -1.887 -2.396
2.006 2.032 2.193 2.110 2.589 2.050 2.208 2.131 2.636
1.759 1.851 2.052 1.953 1.826 1.869 2.073 1.967 1.877
-1.302 -1.378 -1.527 -1.457 -1.319 -1.386 -1.537 -1.462 -1.365
-1.787 -1.806 -1.947 -1.875 -2.353 -1.815 -1.953 -1.887 -2.396
2.006 2.032 2.193 2.110 2.589 2.050 2.208 2.131 2.636
1.759 1.851 2.052 1.953 1.826 1.869 2.073 1.967 1.877
-1.302 -1.378 -1.527 -1.457 -1.319 -1.386 -1.537 -1.462 -1.365
-1.797 -1.817 -1.963 -1.891 -2.369 -1.826 -1.968 -1.902 -2.411
2.016 2.043 2.209 2.126 2.605 2.061 2.223 2.146 2.651
1.749 1.840 2.036 1.937 1.810 1.858 2.058 1.952 1.862
-1.292 -1.367 -1.511 -1.441 -1.303 -1.375 -1.522 -1.447 -1.350
-1.797 -1.817 -1.963 -1.891 -2.369 -1.826 -1.968 -1.902 -2.411
2.016 2.043 2.209 2.126 2.605 2.061 2.223 2.146 2.651
1.749 1.840 2.036 1.937 1.810 1.858 2.058 1.952 1.862
-1.292 -1.367 -1.511 -1.441 -1.303 -1.375 -1.522 -1.447 -1.350
-1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429
2.025 2.054 2.228 2.145 2.624 2.072 2.241 2.164 2.669
1.740 1.829 2.017 1.918 1.791 1.847 2.040 1.934 1.844
-1.283 -1.356 -1.492 -1.422 -1.284 -1.364 -1.504 -1.429 -1.332
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
GCLK
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–192
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–97. EP3SL340 Column Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.114
1.243
1.021
-0.753
-1.102
1.231
1.033
-0.765
-1.102
1.231
1.033
-0.765
-1.114
1.243
1.021
-0.753
-1.114
1.243
1.021
-0.753
-1.121
1.250
1.014
-0.746
-1.121
1.250
1.014
-0.746
-1.181
1.327
1.039
-0.751
-1.170
1.316
1.050
-0.762
-1.170
1.316
1.050
-0.762
-1.181
1.327
1.039
-0.751
-1.181
1.327
1.039
-0.751
-1.187
1.333
1.033
-0.745
-1.187
1.333
1.033
-0.745
-1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429
2.025 2.054 2.228 2.145 2.624 2.072 2.241 2.164 2.669
1.740 1.829 2.017 1.918 1.791 1.847 2.040 1.934 1.844
-1.283 -1.356 -1.492 -1.422 -1.284 -1.364 -1.504 -1.429 -1.332
-1.797 -1.817 -1.963 -1.891 -2.369 -1.826 -1.968 -1.902 -2.411
2.016 2.043 2.209 2.126 2.605 2.061 2.223 2.146 2.651
1.749 1.840 2.036 1.937 1.810 1.858 2.058 1.952 1.862
-1.292 -1.367 -1.511 -1.441 -1.303 -1.375 -1.522 -1.447 -1.350
-1.797 -1.817 -1.963 -1.891 -2.369 -1.826 -1.968 -1.902 -2.411
2.016 2.043 2.209 2.126 2.605 2.061 2.223 2.146 2.651
1.749 1.840 2.036 1.937 1.810 1.858 2.058 1.952 1.862
-1.292 -1.367 -1.511 -1.441 -1.303 -1.375 -1.522 -1.447 -1.350
-1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429
2.025 2.054 2.228 2.145 2.624 2.072 2.241 2.164 2.669
1.740 1.829 2.017 1.918 1.791 1.847 2.040 1.934 1.844
-1.283 -1.356 -1.492 -1.422 -1.284 -1.364 -1.504 -1.429 -1.332
-1.806 -1.828 -1.982 -1.910 -2.388 -1.837 -1.986 -1.920 -2.429
2.025 2.054 2.228 2.145 2.624 2.072 2.241 2.164 2.669
1.740 1.829 2.017 1.918 1.791 1.847 2.040 1.934 1.844
-1.283 -1.356 -1.492 -1.422 -1.284 -1.364 -1.504 -1.429 -1.332
-1.818 -1.833 -1.982 -1.912 -2.387 -1.841 -1.981 -1.918 -2.425
2.038 2.062 2.231 2.148 2.628 2.079 2.241 2.163 2.670
1.728 1.824 2.017 1.916 1.792 1.843 2.045 1.936 1.848
-1.270 -1.348 -1.489 -1.419 -1.280 -1.357 -1.504 -1.430 -1.331
-1.818 -1.833 -1.982 -1.912 -2.387 -1.841 -1.981 -1.918 -2.425
2.038 2.062 2.231 2.148 2.628 2.079 2.241 2.163 2.670
1.728 1.824 2.017 1.916 1.792 1.843 2.045 1.936 1.848
-1.270 -1.348 -1.489 -1.419 -1.280 -1.357 -1.504 -1.430 -1.331
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–193
I/O Timing
Table 1–98 specifies EP3SL340 row pins input timing parameters for differential I/O
standards.
Table 1–98. EP3SL340 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.246
1.380
0.822
-0.548
-1.246
1.380
0.822
-0.548
-1.246
1.380
0.822
-0.548
-1.051
1.178
1.007
-0.740
-1.051
1.178
1.007
-0.740
-1.060
1.187
0.998
-0.731
-1.060
1.187
0.998
-0.731
-1.074
1.201
0.984
-0.717
-1.308
1.458
0.846
-0.552
-1.308
1.458
0.846
-0.552
-1.308
1.458
0.846
-0.552
-1.123
1.264
1.021
-0.736
-1.123
1.264
1.021
-0.736
-1.135
1.276
1.009
-0.724
-1.135
1.276
1.009
-0.724
-1.147
1.288
0.997
-0.712
-1.577 -1.488 -1.656 -1.595 -2.046 -1.456 -1.615 -1.558 -2.087
1.832 1.758 1.950 1.878 2.332 1.738 1.920 1.853 2.374
1.911 2.121 2.309 2.193 2.091 2.181 2.377 2.260 2.149
-1.422 -1.604 -1.736 -1.650 -1.536 -1.651 -1.790 -1.702 -1.588
-1.577 -1.488 -1.656 -1.595 -2.046 -1.456 -1.615 -1.558 -2.087
1.832 1.758 1.950 1.878 2.332 1.738 1.920 1.853 2.374
1.911 2.121 2.309 2.193 2.091 2.181 2.377 2.260 2.149
-1.422 -1.604 -1.736 -1.650 -1.536 -1.651 -1.790 -1.702 -1.588
-1.577 -1.488 -1.656 -1.595 -2.046 -1.456 -1.615 -1.558 -2.087
1.832 1.758 1.950 1.878 2.332 1.738 1.920 1.853 2.374
1.911 2.121 2.309 2.193 2.091 2.181 2.377 2.260 2.149
-1.422 -1.604 -1.736 -1.650 -1.536 -1.651 -1.790 -1.702 -1.588
-1.707 -1.717 -1.845 -1.779 -2.225 -1.727 -1.852 -1.790 -2.271
1.926 1.941 2.090 2.013 2.462 1.960 2.105 2.033 2.509
1.776 1.887 2.110 1.999 1.902 1.904 2.130 2.018 1.955
-1.321 -1.415 -1.586 -1.505 -1.396 -1.423 -1.595 -1.512 -1.443
-1.707 -1.717 -1.845 -1.779 -2.225 -1.727 -1.852 -1.790 -2.271
1.926 1.941 2.090 2.013 2.462 1.960 2.105 2.033 2.509
1.776 1.887 2.110 1.999 1.902 1.904 2.130 2.018 1.955
-1.321 -1.415 -1.586 -1.505 -1.396 -1.423 -1.595 -1.512 -1.443
-1.716 -1.727 -1.861 -1.795 -2.241 -1.736 -1.868 -1.806 -2.287
1.935 1.951 2.106 2.029 2.478 1.969 2.121 2.049 2.525
1.767 1.877 2.094 1.983 1.886 1.895 2.114 2.002 1.939
-1.312 -1.405 -1.570 -1.489 -1.380 -1.414 -1.579 -1.496 -1.427
-1.716 -1.727 -1.861 -1.795 -2.241 -1.736 -1.868 -1.806 -2.287
1.935 1.951 2.106 2.029 2.478 1.969 2.121 2.049 2.525
1.767 1.877 2.094 1.983 1.886 1.895 2.114 2.002 1.939
-1.312 -1.405 -1.570 -1.489 -1.380 -1.414 -1.579 -1.496 -1.427
-1.725 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304
1.944 1.961 2.124 2.047 2.496 1.980 2.138 2.066 2.542
1.754 1.867 2.076 1.965 1.868 1.884 2.097 1.985 1.922
-1.300 -1.395 -1.552 -1.471 -1.362 -1.403 -1.562 -1.479 -1.410
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
GCLK
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
DIFFERENTIAL
1.2-V
HSTL CLASS I
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
DIFFERENTIAL
1.5-V
HSTL CLASS I
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS I
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–194
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–98. EP3SL340 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.074
1.201
0.984
-0.717
-1.060
1.187
0.998
-0.731
-1.060
1.187
0.998
-0.731
-1.074
1.201
0.984
-0.717
-1.074
1.201
0.984
-0.717
-1.083
1.210
0.985
-0.718
-1.083
1.210
0.985
-0.718
-1.147
1.288
0.997
-0.712
-1.135
1.276
1.009
-0.724
-1.135
1.276
1.009
-0.724
-1.147
1.288
0.997
-0.712
-1.147
1.288
0.997
-0.712
-1.156
1.297
0.998
-0.713
-1.156
1.297
0.998
-0.713
-1.725 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304
1.944 1.961 2.124 2.047 2.496 1.980 2.138 2.066 2.542
1.754 1.867 2.076 1.965 1.868 1.884 2.097 1.985 1.922
-1.300 -1.395 -1.552 -1.471 -1.362 -1.403 -1.562 -1.479 -1.410
-1.716 -1.727 -1.861 -1.795 -2.241 -1.736 -1.868 -1.806 -2.287
1.935 1.951 2.106 2.029 2.478 1.969 2.121 2.049 2.525
1.767 1.877 2.094 1.983 1.886 1.895 2.114 2.002 1.939
-1.312 -1.405 -1.570 -1.489 -1.380 -1.414 -1.579 -1.496 -1.427
-1.716 -1.727 -1.861 -1.795 -2.241 -1.736 -1.868 -1.806 -2.287
1.935 1.951 2.106 2.029 2.478 1.969 2.121 2.049 2.525
1.767 1.877 2.094 1.983 1.886 1.895 2.114 2.002 1.939
-1.312 -1.405 -1.570 -1.489 -1.380 -1.414 -1.579 -1.496 -1.427
-1.725 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304
1.944 1.961 2.124 2.047 2.496 1.980 2.138 2.066 2.542
1.754 1.867 2.076 1.965 1.868 1.884 2.097 1.985 1.922
-1.300 -1.395 -1.552 -1.471 -1.362 -1.403 -1.562 -1.479 -1.410
-1.725 -1.737 -1.879 -1.813 -2.259 -1.747 -1.885 -1.823 -2.304
1.944 1.961 2.124 2.047 2.496 1.980 2.138 2.066 2.542
1.754 1.867 2.076 1.965 1.868 1.884 2.097 1.985 1.922
-1.300 -1.395 -1.552 -1.471 -1.362 -1.403 -1.562 -1.479 -1.410
-1.739 -1.748 -1.886 -1.821 -2.265 -1.754 -1.886 -1.826 -2.306
1.959 1.975 2.134 2.057 2.507 1.990 2.144 2.071 2.549
1.749 1.861 2.075 1.963 1.867 1.883 2.101 1.987 1.925
-1.295 -1.387 -1.548 -1.467 -1.357 -1.399 -1.563 -1.480 -1.409
-1.739 -1.748 -1.886 -1.821 -2.265 -1.754 -1.886 -1.826 -2.306
1.959 1.975 2.134 2.057 2.507 1.990 2.144 2.071 2.549
1.749 1.861 2.075 1.963 1.867 1.883 2.101 1.987 1.925
-1.295 -1.387 -1.548 -1.467 -1.357 -1.399 -1.563 -1.480 -1.409
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
DIFFERENTIAL
2.5-V
SSTL CLASS I
tsu
th
GCLK
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–195
I/O Timing
Table 1–99 specifies EP3SL340 Column Pins Output Timing parameters for differential
I/O standards.
Table 1–99. EP3SL340 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.438
1.427
3.434
1.423
3.438
1.427
3.434
1.423
3.438
1.427
3.434
1.423
3.465
1.454
3.455
1.444
3.455
1.444
3.448
1.437
3.447
1.436
3.469
1.458
3.700
1.606
3.703
1.609
3.700
1.606
3.703
1.609
3.700
1.606
3.703
1.609
3.733
1.639
3.723
1.629
3.723
1.629
3.717
1.623
3.715
1.621
3.737
1.643
5.415 5.607 6.143 5.991 6.399 5.739 6.274 6.122 6.475
2.089 2.181 2.406 2.407 2.475 2.287 2.511 2.514 2.459
5.462 5.662 6.205 6.053 6.461 5.798 6.340 6.188 6.541
2.136 2.236 2.468 2.469 2.537 2.346 2.577 2.580 2.525
5.415 5.607 6.143 5.991 6.399 5.739 6.274 6.122 6.475
—
—
LVDS_E_1R
LVDS_E_3R
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
2.089 2.181 2.406 2.407 2.475 2.287 2.511 2.514 2.459 ns
ns
GCLK
5.462 5.662 6.205 6.053 6.461 5.798 6.340 6.188 6.541
2.136 2.236 2.468 2.469 2.537 2.346 2.577 2.580 2.525 ns
ns
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
5.415 5.607 6.143 5.991 6.399 5.739 6.274 6.122 6.475
2.089 2.181 2.406 2.407 2.475 2.287 2.511 2.514 2.459 ns
ns
—
RSDS_E_1R
RSDS_E_3R
GCLK
PLL
GCLK
5.462 5.662 6.205 6.053 6.461 5.798 6.340 6.188 6.541
2.136 2.236 2.468 2.469 2.537 2.346 2.577 2.580 2.525 ns
ns
—
GCLK
PLL
GCLK
5.486 5.685 6.227 6.075 6.483 5.819 6.360 6.208 6.561
2.160 2.259 2.490 2.491 2.559 2.367 2.597 2.600 2.545 ns
ns
4mA
6mA
8mA
10mA
12mA
16mA
GCLK
PLL
GCLK
5.476 5.674 6.217 6.065 6.473 5.808 6.350 6.198 6.551
2.150 2.248 2.480 2.481 2.549 2.356 2.587 2.590 2.535 ns
ns
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
5.479 5.678 6.221 6.069 6.477 5.813 6.355 6.203 6.556
2.153 2.252 2.484 2.485 2.553 2.361 2.592 2.595 2.540 ns
ns
GCLK
PLL
GCLK
5.472 5.672 6.215 6.063 6.471 5.806 6.349 6.197 6.550
2.146 2.246 2.478 2.479 2.547 2.354 2.586 2.589 2.534 ns
GCLK
PLL
GCLK
ns
ns
ns
ns
5.469 5.669 6.212 6.060 6.468 5.803 6.345 6.193 6.546
2.143 2.243 2.475 2.476 2.544 2.351 2.582 2.585 2.530
5.490 5.689 6.231 6.079 6.487 5.823 6.365 6.213 6.566
2.164 2.263 2.494 2.495 2.563 2.371 2.602 2.605 2.550
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–196
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–99. EP3SL340 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.459
1.448
3.454
1.443
3.452
1.441
3.444
1.433
3.445
1.434
3.444
1.433
3.456
1.445
3.452
1.441
3.442
1.431
3.440
1.429
3.440
1.429
3.444
1.433
3.726
1.632
3.722
1.628
3.720
1.626
3.711
1.617
3.713
1.619
3.710
1.616
3.723
1.629
3.720
1.626
3.709
1.615
3.707
1.613
3.708
1.614
3.711
1.617
5.469 5.666 6.206 6.054 6.462 5.799 6.338 6.186 6.539
2.143 2.240 2.469 2.470 2.538 2.347 2.575 2.578 2.523
5.469 5.666 6.207 6.055 6.463 5.800 6.340 6.188 6.541
2.143 2.240 2.470 2.471 2.539 2.348 2.577 2.580 2.525
5.468 5.665 6.205 6.053 6.461 5.799 6.339 6.187 6.540
2.142 2.239 2.468 2.469 2.537 2.347 2.576 2.579 2.524
5.458 5.655 6.196 6.044 6.452 5.789 6.329 6.177 6.530
2.132 2.229 2.459 2.460 2.528 2.337 2.566 2.569 2.514
5.464 5.662 6.204 6.052 6.460 5.797 6.338 6.186 6.539
2.138 2.236 2.467 2.468 2.536 2.345 2.575 2.578 2.523
5.447 5.643 6.182 6.030 6.438 5.776 6.314 6.162 6.515
2.121 2.217 2.445 2.446 2.514 2.324 2.551 2.554 2.499
5.465 5.661 6.200 6.048 6.456 5.795 6.333 6.181 6.534
2.139 2.235 2.463 2.464 2.532 2.343 2.570 2.573 2.518
5.466 5.663 6.204 6.052 6.460 5.797 6.337 6.185 6.538
2.140 2.237 2.467 2.468 2.536 2.345 2.574 2.577 2.522
5.455 5.652 6.192 6.040 6.448 5.786 6.325 6.173 6.526
2.129 2.226 2.455 2.456 2.524 2.334 2.562 2.565 2.510
4mA
6mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
5.453 5.649 6.190 6.038 6.446 5.784 6.323 6.171 6.524 ns
ns
10mA
12mA
16mA
GCLK
PLL
2.127 2.223 2.453 2.454 2.522 2.332 2.560 2.563 2.508
5.456 5.654 6.195 6.043 6.451 5.788 6.329 6.177 6.530 ns
ns
GCLK
GCLK
PLL
2.130 2.228 2.458 2.459 2.527 2.336 2.566 2.569 2.514
5.453 5.649 6.189 6.037 6.445 5.783 6.322 6.170 6.523 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
GCLK
PLL
ns
2.127 2.223 2.452 2.453 2.521 2.331 2.559 2.562 2.507
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–197
I/O Timing
Table 1–99. EP3SL340 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.470
1.459
3.456
1.445
3.444
1.433
3.444
1.433
3.440
1.429
3.444
1.433
3.445
1.434
3.473
1.462
3.462
1.451
3.457
1.446
3.443
1.432
3.441
1.430
3.445
1.434
3.445
1.434
3.740
1.646
3.726
1.632
3.713
1.619
3.713
1.619
3.709
1.615
3.711
1.617
3.713
1.619
3.743
1.649
3.731
1.637
3.727
1.633
3.712
1.618
3.710
1.616
3.712
1.618
3.713
1.619
5.498 5.697 6.239 6.087 6.495 5.831 6.372 6.220 6.573
2.172 2.271 2.502 2.503 2.571 2.379 2.609 2.612 2.557
5.486 5.686 6.229 6.077 6.485 5.821 6.363 6.211 6.564
2.160 2.260 2.492 2.493 2.561 2.369 2.600 2.603 2.548
5.469 5.668 6.211 6.059 6.467 5.803 6.345 6.193 6.546
2.143 2.242 2.474 2.475 2.543 2.351 2.582 2.585 2.530
5.472 5.672 6.215 6.063 6.471 5.807 6.350 6.198 6.551
2.146 2.246 2.478 2.479 2.547 2.355 2.587 2.590 2.535
5.465 5.664 6.208 6.056 6.464 5.800 6.342 6.190 6.543
2.139 2.238 2.471 2.472 2.540 2.348 2.579 2.582 2.527
5.458 5.655 6.196 6.044 6.452 5.789 6.329 6.177 6.530
2.132 2.229 2.459 2.460 2.528 2.337 2.566 2.569 2.514
5.466 5.665 6.207 6.055 6.463 5.799 6.341 6.189 6.542
2.140 2.239 2.470 2.471 2.539 2.347 2.578 2.581 2.526
5.497 5.695 6.237 6.085 6.493 5.830 6.370 6.218 6.571
2.171 2.269 2.500 2.501 2.569 2.378 2.607 2.610 2.555
5.485 5.683 6.225 6.073 6.481 5.818 6.358 6.206 6.559
2.159 2.257 2.488 2.489 2.557 2.366 2.595 2.598 2.543
4mA
6mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
5.485 5.684 6.226 6.074 6.482 5.819 6.360 6.208 6.561 ns
ns
8mA
GCLK
PLL
2.159 2.258 2.489 2.490 2.558 2.367 2.597 2.600 2.545
5.467 5.665 6.207 6.055 6.463 5.800 6.342 6.190 6.543 ns
ns
GCLK
10mA
12mA
8mA
GCLK
PLL
2.141 2.239 2.470 2.471 2.539 2.348 2.579 2.582 2.527
5.465 5.663 6.205 6.053 6.461 5.798 6.339 6.187 6.540 ns
ns
GCLK
GCLK
PLL
2.139 2.237 2.468 2.469 2.537 2.346 2.576 2.579 2.524
5.457 5.653 6.193 6.041 6.449 5.787 6.326 6.174 6.527 ns
ns
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
2.131 2.227 2.456 2.457 2.525 2.335 2.563 2.566 2.511
5.465 5.663 6.205 6.053 6.461 5.798 6.339 6.187 6.540 ns
GCLK
16mA
GCLK
PLL
ns
2.139 2.237 2.468 2.469 2.537 2.346 2.576 2.579 2.524
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–198
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–99. EP3SL340 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.461
1.450
3.461
1.450
3.451
1.440
3.444
1.433
3.730
1.636
3.730
1.636
3.720
1.626
3.712
1.618
5.481 5.678 6.219 6.067 6.475 5.813 6.352 6.200 6.553
2.155 2.252 2.482 2.483 2.551 2.361 2.589 2.592 2.537
5.481 5.678 6.219 6.067 6.475 5.813 6.352 6.200 6.553
2.155 2.252 2.482 2.483 2.551 2.361 2.589 2.592 2.537
5.471 5.668 6.209 6.057 6.465 5.803 6.343 6.191 6.544
2.145 2.242 2.472 2.473 2.541 2.351 2.580 2.583 2.528
5.457 5.653 6.193 6.041 6.449 5.787 6.326 6.174 6.527
2.131 2.227 2.456 2.457 2.525 2.335 2.563 2.566 2.511
8mA
10mA
12mA
16mA
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–199
I/O Timing
Table 1–100 specifies EP3SL340 Row Pins Output Timing parameters for differential
I/O standards.
Table 1–100. EP3SL340 Row Pins output Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.022
1.063
3.414
1.455
3.396
1.437
3.022
1.063
3.414
1.455
3.396
1.437
3.022
1.063
3.414
1.455
3.396
1.437
3.440
1.491
3.426
1.477
3.422
1.473
3.234
1.193
3.678
1.637
3.668
1.627
3.234
1.193
3.678
1.637
3.668
1.627
3.234
1.193
3.678
1.637
3.668
1.627
3.711
1.680
3.697
1.666
3.693
1.662
4.714 4.872 5.362 5.217 5.602 4.981 5.467 5.326 5.662
1.445 1.501 1.678 1.690 1.735 1.583 1.761 1.772 1.704
5.396 5.588 6.125 5.972 6.349 5.722 6.255 6.105 6.425
2.127 2.217 2.441 2.445 2.482 2.324 2.549 2.551 2.467
5.434 5.634 6.179 6.026 6.403 5.773 6.316 6.166 6.486
2.165 2.263 2.495 2.499 2.536 2.375 2.610 2.612 2.528
4.714 4.872 5.362 5.217 5.602 4.981 5.467 5.326 5.662
1.445 1.501 1.678 1.690 1.735 1.583 1.761 1.772 1.704
5.396 5.588 6.125 5.972 6.349 5.722 6.255 6.105 6.425
2.127 2.217 2.441 2.445 2.482 2.324 2.549 2.551 2.467
5.434 5.634 6.179 6.026 6.403 5.773 6.316 6.166 6.486
2.165 2.263 2.495 2.499 2.536 2.375 2.610 2.612 2.528
4.714 4.872 5.362 5.217 5.602 4.981 5.467 5.326 5.662
1.445 1.501 1.678 1.690 1.735 1.583 1.761 1.772 1.704
5.396 5.588 6.125 5.972 6.349 5.722 6.255 6.105 6.425
2.127 2.217 2.441 2.445 2.482 2.324 2.549 2.551 2.467
5.434 5.634 6.179 6.026 6.403 5.773 6.316 6.166 6.486
2.165 2.263 2.495 2.499 2.536 2.375 2.610 2.612 2.528
5.470 5.668 6.212 6.059 6.436 5.806 6.345 6.195 6.515
2.211 2.307 2.538 2.542 2.579 2.418 2.649 2.651 2.567
5.457 5.655 6.199 6.046 6.423 5.792 6.332 6.182 6.502
2.198 2.294 2.525 2.529 2.566 2.404 2.636 2.638 2.554
5.455 5.655 6.200 6.047 6.424 5.792 6.334 6.184 6.504
2.196 2.294 2.526 2.530 2.567 2.404 2.638 2.640 2.556
LVDS
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
—
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
—
GCLK
tco
PLL
GCLK tco
RSDS
—
GCLK
tco
PLL
GCLK tco
RSDS_E_1R
RSDS_E_3R
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–200
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–100. EP3SL340 Row Pins output Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.438
1.489
3.427
1.478
3.424
1.475
3.435
1.486
3.425
1.476
3.411
1.462
3.408
1.459
3.405
1.456
3.406
1.457
3.455
1.506
3.431
1.482
3.414
1.465
3.708
1.677
3.698
1.667
3.695
1.664
3.705
1.674
3.696
1.665
3.682
1.651
3.678
1.647
3.676
1.645
3.676
1.645
3.729
1.698
3.705
1.674
3.686
1.655
5.456 5.652 6.194 6.041 6.418 5.789 6.327 6.177 6.497
2.197 2.291 2.520 2.524 2.561 2.401 2.631 2.633 2.549
5.452 5.648 6.191 6.038 6.415 5.786 6.324 6.174 6.494
2.193 2.287 2.517 2.521 2.558 2.398 2.628 2.630 2.546
5.450 5.646 6.189 6.036 6.413 5.784 6.323 6.173 6.493
2.191 2.285 2.515 2.519 2.556 2.396 2.627 2.629 2.545
5.451 5.647 6.188 6.035 6.412 5.784 6.321 6.171 6.491
2.192 2.286 2.514 2.518 2.555 2.396 2.625 2.627 2.543
5.449 5.645 6.187 6.034 6.411 5.783 6.321 6.171 6.491
2.190 2.284 2.513 2.517 2.554 2.395 2.625 2.627 2.543
5.434 5.630 6.173 6.020 6.397 5.768 6.306 6.156 6.476
2.175 2.269 2.499 2.503 2.540 2.380 2.610 2.612 2.528
5.430 5.626 6.169 6.016 6.393 5.764 6.302 6.152 6.472
2.171 2.265 2.495 2.499 2.536 2.376 2.606 2.608 2.524
5.431 5.629 6.172 6.019 6.396 5.767 6.306 6.156 6.476
2.172 2.268 2.498 2.502 2.539 2.379 2.610 2.612 2.528
5.421 5.617 6.159 6.006 6.383 5.754 6.292 6.142 6.462
2.162 2.256 2.485 2.489 2.526 2.366 2.596 2.598 2.514
5.492 5.690 6.235 6.082 6.459 5.828 6.368 6.218 6.538
2.233 2.329 2.561 2.565 2.602 2.440 2.672 2.674 2.590
5.474 5.673 6.218 6.065 6.442 5.811 6.353 6.203 6.523
2.215 2.312 2.544 2.548 2.585 2.423 2.657 2.659 2.575
5.452 5.651 6.196 6.043 6.420 5.789 6.331 6.181 6.501
2.193 2.290 2.522 2.526 2.563 2.401 2.635 2.637 2.553
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–201
I/O Timing
Table 1–100. EP3SL340 Row Pins output Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.459
1.510
3.444
1.495
3.433
1.484
3.413
1.464
3.410
1.461
3.415
1.466
3.408
1.459
3.446
1.487
3.428
1.469
3.414
1.455
3.732
1.701
3.717
1.686
3.706
1.675
3.686
1.655
3.682
1.651
3.686
1.655
3.679
1.648
3.718
1.677
3.701
1.660
3.685
1.644
5.492 5.690 6.234 6.081 6.458 5.828 6.368 6.218 6.538
2.233 2.329 2.560 2.564 2.601 2.440 2.672 2.674 2.590
5.478 5.675 6.219 6.066 6.443 5.813 6.353 6.203 6.523
2.219 2.314 2.545 2.549 2.586 2.425 2.657 2.659 2.575
5.473 5.672 6.216 6.063 6.440 5.810 6.351 6.201 6.521
2.214 2.311 2.542 2.546 2.583 2.422 2.655 2.657 2.573
5.450 5.648 6.193 6.040 6.417 5.787 6.327 6.177 6.497
2.191 2.287 2.519 2.523 2.560 2.399 2.631 2.633 2.549
5.446 5.645 6.189 6.036 6.413 5.783 6.324 6.174 6.494
2.187 2.284 2.515 2.519 2.556 2.395 2.628 2.630 2.546
5.437 5.633 6.175 6.022 6.399 5.770 6.308 6.158 6.478
2.178 2.272 2.501 2.505 2.542 2.382 2.612 2.614 2.530
5.436 5.634 6.178 6.025 6.402 5.773 6.313 6.163 6.483
2.177 2.273 2.504 2.508 2.545 2.385 2.617 2.619 2.535
5.474 5.671 6.214 6.061 6.438 5.809 6.348 6.198 6.518
2.205 2.300 2.530 2.534 2.571 2.411 2.642 2.644 2.560
5.459 5.656 6.199 6.046 6.423 5.794 6.333 6.183 6.503
2.190 2.285 2.515 2.519 2.556 2.396 2.627 2.629 2.545
5.436 5.632 6.174 6.021 6.398 5.770 6.308 6.158 6.478
2.167 2.261 2.490 2.494 2.531 2.372 2.602 2.604 2.520
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
PLL
GCLK tco
16mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
PLL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS II
GCLK
tco
PLL
Table 1–101 and Table 1–102 show EP3SL340 regional (RCLK) clock adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–202
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–101 specifies EP3SL340 Column Pin delay adders when using the regional
clock.
Table 1–101. EP3SL340 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
ns
ns
0.318
2.716
-0.341
-2.36
0.171
2.739
-0.107
-2.128
0.255 0.247 0.257 0.244 0.369 0.37 0.253 0.232 0.336
4.379 4.508 4.926 4.717 5.376 4.508 4.94 4.89 5.434
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
-0.18 -0.169 -0.171 -0.167 -0.362 -0.03 -0.043 -0.034 -0.287 ns
ns
-3.344 -3.384 -3.571 -3.487 -3.545 -3.246 -3.636 -3.357 -3.544
Table 1–102 specifies EP3SL340 Row Pin delay adders when using the regional clock.
Table 1–102. EP3SL340 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
ns
ns
ns
ns
0.075
0.157
-0.052
-0.157
0.079
0.151
-0.066
-0.139
0.133 0.124 0.125 0.124 0.307 0.117 0.116 0.117 0.31
0.262 0.274 0.306 0.288 0.464 0.268 0.291 0.278 0.46
-0.107 -0.098 -0.127 -0.129 -0.282 -0.082 -0.118 -0.085 -0.285
-0.232 -0.248 -0.272 -0.259 -0.422 -0.252 -0.256 -0.244 -0.444
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
EP3SE50 I/O Timing Parameters
Table 1–103 through Table 1–106 show the maximum I/O timing parameters for
EP3SE50 devices for single-ended I/O standards.
Table 1–103 specifies EP3SE50 column pins input timing parameters for single-ended
I/O standards.
Table 1–103. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.911
1.025
0.664
-0.421
-0.911
1.025
0.664
-0.421
-0.933
1.062
0.680
-0.422
-0.933
1.062
0.680
-0.422
-1.342 -1.477 -1.720 -1.659 -1.949 -1.491 -1.718 -1.662 -1.976 ns
GCLK
1.524 1.682 1.947 1.872 2.165 1.705 1.955 1.884 2.193
1.158 1.326 1.384 1.294 1.304 1.324 1.397 1.302 1.361
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-0.773 -0.891 -0.897 -0.838 -0.836 -0.880 -0.901 -0.838 -0.890 ns
-1.342 -1.477 -1.720 -1.659 -1.949 -1.491 -1.718 -1.662 -1.976 ns
tsu
th
GCLK
1.524 1.682 1.947 1.872 2.165 1.705 1.955 1.884 2.193
1.158 1.326 1.384 1.294 1.304 1.324 1.397 1.302 1.361
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-0.773 -0.891 -0.897 -0.838 -0.836 -0.880 -0.901 -0.838 -0.890 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–203
I/O Timing
Table 1–103. EP3SE50 Column Pins Input Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.917
1.031
0.658
-0.415
-0.917
1.031
0.658
-0.415
-0.907
1.021
0.668
-0.425
-0.925
1.041
0.650
-0.405
-0.918
1.034
0.657
-0.412
-0.858
0.974
0.717
-0.472
-0.839
0.955
0.736
-0.491
-0.839
0.955
0.736
-0.491
-0.832
0.948
0.743
-0.498
-0.944
1.073
0.669
-0.411
-0.944
1.073
0.669
-0.411
-0.939
1.068
0.674
-0.416
-0.961
1.092
0.652
-0.392
-0.951
1.082
0.662
-0.402
-0.899
1.030
0.714
-0.454
-0.870
1.001
0.743
-0.483
-0.870
1.001
0.743
-0.483
-0.864
0.995
0.749
-0.489
-1.341 -1.479 -1.719 -1.658 -1.948 -1.491 -1.723 -1.667 -1.981 ns
GCLK
1.523 1.684 1.946 1.871 2.164 1.705 1.960 1.889 2.198
1.159 1.324 1.385 1.295 1.305 1.324 1.392 1.297 1.356
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-0.774 -0.889 -0.898 -0.839 -0.837 -0.880 -0.896 -0.833 -0.885 ns
-1.341 -1.479 -1.719 -1.658 -1.948 -1.491 -1.723 -1.667 -1.981 ns
tsu
th
GCLK
1.523 1.684 1.946 1.871 2.164 1.705 1.960 1.889 2.198
1.159 1.324 1.385 1.295 1.305 1.324 1.392 1.297 1.356
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-0.774 -0.889 -0.898 -0.839 -0.837 -0.880 -0.896 -0.833 -0.885 ns
-1.350 -1.491 -1.738 -1.677 -1.967 -1.501 -1.734 -1.678 -1.992 ns
tsu
th
GCLK
1.532 1.696 1.965 1.890 2.183 1.715 1.971 1.900 2.209
1.150 1.312 1.366 1.276 1.286 1.314 1.381 1.286 1.345
ns
ns
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
-0.765 -0.877 -0.879 -0.820 -0.818 -0.870 -0.885 -0.822 -0.874 ns
-1.390 -1.527 -1.736 -1.675 -1.965 -1.535 -1.737 -1.681 -1.995 ns
tsu
th
GCLK
1.572 1.732 1.963 1.888 2.181 1.749 1.974 1.903 2.212
1.110 1.276 1.368 1.278 1.288 1.280 1.378 1.283 1.342
ns
ns
tsu
th
GCLK
PLL
-0.725 -0.841 -0.881 -0.822 -0.820 -0.836 -0.882 -0.819 -0.871 ns
-1.367 -1.495 -1.666 -1.605 -1.895 -1.504 -1.671 -1.615 -1.929 ns
tsu
th
GCLK
1.549 1.700 1.893 1.818 2.111 1.718 1.908 1.837 2.146
1.133 1.308 1.438 1.348 1.358 1.311 1.444 1.349 1.408
ns
ns
tsu
th
GCLK
PLL
-0.748 -0.873 -0.951 -0.892 -0.890 -0.867 -0.948 -0.885 -0.937 ns
-1.290 -1.396 -1.510 -1.449 -1.739 -1.408 -1.518 -1.462 -1.776 ns
tsu
th
GCLK
1.472 1.601 1.737 1.662 1.955 1.622 1.755 1.684 1.993
1.210 1.407 1.594 1.504 1.514 1.407 1.597 1.502 1.561
ns
ns
tsu
th
GCLK
PLL
-0.825 -0.972 -1.107 -1.048 -1.046 -0.963 -1.101 -1.038 -1.090 ns
-1.262 -1.380 -1.512 -1.451 -1.741 -1.387 -1.514 -1.458 -1.772 ns
tsu
th
GCLK
1.444 1.585 1.739 1.664 1.957 1.601 1.751 1.680 1.989
1.238 1.423 1.592 1.502 1.512 1.428 1.601 1.506 1.565
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-0.853 -0.988 -1.105 -1.046 -1.044 -0.984 -1.105 -1.042 -1.094 ns
-1.262 -1.380 -1.512 -1.451 -1.741 -1.387 -1.514 -1.458 -1.772 ns
tsu
th
GCLK
1.444 1.585 1.739 1.664 1.957 1.601 1.751 1.680 1.989
1.238 1.423 1.592 1.502 1.512 1.428 1.601 1.506 1.565
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-0.853 -0.988 -1.105 -1.046 -1.044 -0.984 -1.105 -1.042 -1.094 ns
-1.249 -1.372 -1.509 -1.446 -1.739 -1.380 -1.515 -1.457 -1.773 ns
tsu
th
GCLK
1.431 1.574 1.733 1.658 1.950 1.591 1.748 1.678 1.985
1.251 1.431 1.595 1.507 1.514 1.435 1.600 1.507 1.564
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-0.866 -0.999 -1.111 -1.052 -1.051 -0.994 -1.108 -1.044 -1.098 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–204
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–103. EP3SE50 Column Pins Input Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.832
0.948
0.743
-0.498
-0.820
0.936
0.755
-0.510
-0.820
0.936
0.755
-0.510
-0.832
0.948
0.743
-0.498
-0.832
0.948
0.743
-0.498
-0.820
0.936
0.755
-0.510
-0.820
0.936
0.755
-0.510
-0.812
0.928
0.763
-0.518
-0.812
0.928
0.763
-0.518
-0.864
0.995
0.749
-0.489
-0.853
0.984
0.760
-0.500
-0.853
0.984
0.760
-0.500
-0.864
0.995
0.749
-0.489
-0.864
0.995
0.749
-0.489
-0.853
0.984
0.760
-0.500
-0.853
0.984
0.760
-0.500
-0.841
0.972
0.772
-0.512
-0.841
0.972
0.772
-0.512
-1.249 -1.372 -1.509 -1.446 -1.739 -1.380 -1.515 -1.457 -1.773 ns
GCLK
1.431 1.574 1.733 1.658 1.950 1.591 1.748 1.678 1.985
1.251 1.431 1.595 1.507 1.514 1.435 1.600 1.507 1.564
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-0.866 -0.999 -1.111 -1.052 -1.051 -0.994 -1.108 -1.044 -1.098 ns
-1.238 -1.361 -1.490 -1.427 -1.720 -1.369 -1.497 -1.439 -1.755 ns
tsu
th
GCLK
1.419 1.563 1.714 1.639 1.931 1.580 1.730 1.660 1.967
1.262 1.442 1.614 1.526 1.533 1.446 1.618 1.525 1.582
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-0.878 -1.010 -1.130 -1.071 -1.070 -1.005 -1.126 -1.062 -1.116 ns
-1.238 -1.361 -1.490 -1.427 -1.720 -1.369 -1.497 -1.439 -1.755 ns
tsu
th
GCLK
1.419 1.563 1.714 1.639 1.931 1.580 1.730 1.660 1.967
1.262 1.442 1.614 1.526 1.533 1.446 1.618 1.525 1.582
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.878 -1.010 -1.130 -1.071 -1.070 -1.005 -1.126 -1.062 -1.116 ns
-1.249 -1.372 -1.509 -1.446 -1.739 -1.380 -1.515 -1.457 -1.773 ns
tsu
th
GCLK
1.431 1.574 1.733 1.658 1.950 1.591 1.748 1.678 1.985
1.251 1.431 1.595 1.507 1.514 1.435 1.600 1.507 1.564
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.866 -0.999 -1.111 -1.052 -1.051 -0.994 -1.108 -1.044 -1.098 ns
-1.249 -1.372 -1.509 -1.446 -1.739 -1.380 -1.515 -1.457 -1.773 ns
tsu
th
GCLK
1.431 1.574 1.733 1.658 1.950 1.591 1.748 1.678 1.985
1.251 1.431 1.595 1.507 1.514 1.435 1.600 1.507 1.564
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.866 -0.999 -1.111 -1.052 -1.051 -0.994 -1.108 -1.044 -1.098 ns
-1.238 -1.361 -1.490 -1.427 -1.720 -1.369 -1.497 -1.439 -1.755 ns
tsu
th
GCLK
1.419 1.563 1.714 1.639 1.931 1.580 1.730 1.660 1.967
1.262 1.442 1.614 1.526 1.533 1.446 1.618 1.525 1.582
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.878 -1.010 -1.130 -1.071 -1.070 -1.005 -1.126 -1.062 -1.116 ns
-1.238 -1.361 -1.490 -1.427 -1.720 -1.369 -1.497 -1.439 -1.755 ns
tsu
th
GCLK
1.419 1.563 1.714 1.639 1.931 1.580 1.730 1.660 1.967
1.262 1.442 1.614 1.526 1.533 1.446 1.618 1.525 1.582
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.878 -1.010 -1.130 -1.071 -1.070 -1.005 -1.126 -1.062 -1.116 ns
-1.228 -1.350 -1.474 -1.411 -1.704 -1.358 -1.482 -1.424 -1.740 ns
tsu
th
GCLK
1.409 1.552 1.698 1.623 1.915 1.569 1.715 1.645 1.952
1.272 1.453 1.630 1.542 1.549 1.457 1.633 1.540 1.597
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.888 -1.021 -1.146 -1.087 -1.086 -1.016 -1.141 -1.077 -1.131 ns
-1.228 -1.350 -1.474 -1.411 -1.704 -1.358 -1.482 -1.424 -1.740 ns
tsu
th
GCLK
1.409 1.552 1.698 1.623 1.915 1.569 1.715 1.645 1.952
1.272 1.453 1.630 1.542 1.549 1.457 1.633 1.540 1.597
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-0.888 -1.021 -1.146 -1.087 -1.086 -1.016 -1.141 -1.077 -1.131 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–205
I/O Timing
Table 1–103. EP3SE50 Column Pins Input Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.917
1.031
0.658
-0.415
-0.944
1.073
0.669
-0.411
-1.341 -1.479 -1.719 -1.658 -1.948 -1.491 -1.723 -1.667 -1.981 ns
GCLK
1.523 1.684 1.946 1.871 2.164 1.705 1.960 1.889 2.198
1.159 1.324 1.385 1.295 1.305 1.324 1.392 1.297 1.356
ns
ns
3.0-V |
PCI-X
tsu
th
GCLK
PLL
-0.774 -0.889 -0.898 -0.839 -0.837 -0.880 -0.896 -0.833 -0.885 ns
Table 1–104 specifies EP3SE50 row pins input timing parameters for single-ended
I/O standards.
Table 1–104. EP3SE50 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.896
1.009
0.952
-0.703
-0.896
1.009
0.952
-0.703
-0.902
1.015
0.946
-0.697
-0.902
1.015
0.946
-0.697
-0.890
1.003
0.958
-0.709
-0.869
0.986
0.890
-0.640
-0.926
1.052
0.960
-0.700
-0.926
1.052
0.960
-0.700
-0.937
1.063
0.949
-0.689
-0.937
1.063
0.949
-0.689
-0.930
1.056
0.956
-0.696
-0.907
1.035
0.886
-0.623
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 ns
GCLK
1.494 1.640 1.888 1.819 2.111 1.667 1.903 1.836 2.144
1.597 1.816 1.931 1.813 1.843 1.809 1.936 1.818 1.895
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-1.199 -1.367 -1.429 -1.343 -1.366 -1.351 -1.425 -1.339 -1.415 ns
-1.311 -1.433 -1.658 -1.605 -1.896 -1.451 -1.663 -1.612 -1.927 ns
tsu
th
GCLK
1.494 1.640 1.888 1.819 2.111 1.667 1.903 1.836 2.144
1.597 1.816 1.931 1.813 1.843 1.809 1.936 1.818 1.895
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-1.199 -1.367 -1.429 -1.343 -1.366 -1.351 -1.425 -1.339 -1.415 ns
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 ns
tsu
th
GCLK
1.491 1.641 1.891 1.822 2.114 1.666 1.908 1.841 2.149
1.600 1.815 1.928 1.810 1.840 1.810 1.931 1.813 1.890
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-1.202 -1.366 -1.426 -1.340 -1.363 -1.352 -1.420 -1.334 -1.410 ns
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 ns
tsu
th
GCLK
1.491 1.641 1.891 1.822 2.114 1.666 1.908 1.841 2.149
1.600 1.815 1.928 1.810 1.840 1.810 1.931 1.813 1.890
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-1.202 -1.366 -1.426 -1.340 -1.363 -1.352 -1.420 -1.334 -1.410 ns
-1.317 -1.447 -1.676 -1.623 -1.914 -1.459 -1.678 -1.627 -1.942 ns
tsu
th
GCLK
1.500 1.654 1.906 1.837 2.129 1.675 1.918 1.851 2.159
1.591 1.802 1.913 1.795 1.825 1.801 1.921 1.803 1.880
ns
ns
2.5 V
1.8 V
tsu
th
GCLK
PLL
-1.193 -1.353 -1.411 -1.325 -1.348 -1.343 -1.410 -1.324 -1.400 ns
-1.272 -1.388 -1.573 -1.523 -1.797 -1.395 -1.573 -1.526 -1.829 ns
tsu
th
GCLK
1.458 1.596 1.807 1.742 2.015 1.614 1.817 1.754 2.048
1.510 1.730 1.876 1.758 1.788 1.729 1.881 1.762 1.840
ns
ns
tsu
th
GCLK
PLL
-1.112 -1.280 -1.373 -1.287 -1.309 -1.271 -1.369 -1.282 -1.358 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–206
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–104. EP3SE50 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.859
0.976
0.900
-0.650
-0.799
0.916
0.960
-0.710
-0.833
0.947
1.015
-0.765
-0.833
0.947
1.015
-0.765
-0.773
0.890
0.986
-0.736
-0.773
0.890
0.986
-0.736
-0.759
0.876
1.000
-0.750
-0.773
0.890
0.986
-0.736
-0.773
0.890
0.986
-0.736
-0.896
1.024
0.897
-0.634
-0.843
0.971
0.950
-0.687
-0.872
0.999
1.014
-0.753
-0.872
0.999
1.014
-0.753
-0.808
0.936
0.985
-0.722
-0.808
0.936
0.985
-0.722
-0.796
0.924
0.997
-0.734
-0.808
0.936
0.985
-0.722
-0.808
0.936
0.985
-0.722
-1.248 -1.356 -1.505 -1.455 -1.729 -1.364 -1.508 -1.461 -1.764 ns
GCLK
1.434 1.564 1.739 1.674 1.947 1.583 1.752 1.689 1.983
1.534 1.762 1.944 1.826 1.856 1.760 1.946 1.827 1.905
ns
ns
1.5 V
tsu
th
GCLK
PLL
-1.136 -1.312 -1.441 -1.355 -1.377 -1.302 -1.434 -1.347 -1.423 ns
-1.169 -1.255 -1.346 -1.296 -1.570 -1.268 -1.353 -1.306 -1.609 ns
tsu
th
GCLK
1.355 1.463 1.580 1.515 1.788 1.487 1.597 1.534 1.828
1.613 1.863 2.103 1.985 2.015 1.856 2.101 1.982 2.060
ns
ns
1.2 V
tsu
th
GCLK
PLL
-1.215 -1.413 -1.600 -1.514 -1.536 -1.398 -1.589 -1.502 -1.578 ns
-1.231 -1.338 -1.456 -1.403 -1.694 -1.347 -1.461 -1.410 -1.725 ns
tsu
th
GCLK
1.414 1.545 1.686 1.617 1.909 1.563 1.701 1.634 1.942
1.677 1.911 2.133 2.015 2.045 1.913 2.138 2.020 2.097
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-1.279 -1.462 -1.631 -1.545 -1.568 -1.455 -1.627 -1.541 -1.617 ns
-1.231 -1.338 -1.456 -1.403 -1.694 -1.347 -1.461 -1.410 -1.725 ns
tsu
th
GCLK
1.414 1.545 1.686 1.617 1.909 1.563 1.701 1.634 1.942
1.677 1.911 2.133 2.015 2.045 1.913 2.138 2.020 2.097
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-1.279 -1.462 -1.631 -1.545 -1.568 -1.455 -1.627 -1.541 -1.617 ns
-1.131 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 ns
tsu
th
GCLK
1.317 1.436 1.575 1.510 1.782 1.455 1.590 1.527 1.819
1.651 1.890 2.108 1.991 2.019 1.888 2.108 1.990 2.067
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-1.253 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 ns
-1.131 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 ns
tsu
th
GCLK
1.317 1.436 1.575 1.510 1.782 1.455 1.590 1.527 1.819
1.651 1.890 2.108 1.991 2.019 1.888 2.108 1.990 2.067
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-1.253 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 ns
-1.118 -1.220 -1.326 -1.275 -1.550 -1.228 -1.332 -1.283 -1.587 ns
tsu
th
GCLK
1.305 1.426 1.557 1.492 1.764 1.444 1.573 1.510 1.802
1.666 1.900 2.126 2.009 2.037 1.899 2.125 2.007 2.084
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-1.267 -1.452 -1.625 -1.539 -1.562 -1.443 -1.616 -1.528 -1.606 ns
-1.131 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 ns
tsu
th
GCLK
1.317 1.436 1.575 1.510 1.782 1.455 1.590 1.527 1.819
1.651 1.890 2.108 1.991 2.019 1.888 2.108 1.990 2.067
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.253 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 ns
-1.131 -1.230 -1.344 -1.293 -1.568 -1.239 -1.349 -1.300 -1.604 ns
tsu
th
GCLK
1.317 1.436 1.575 1.510 1.782 1.455 1.590 1.527 1.819
1.651 1.890 2.108 1.991 2.019 1.888 2.108 1.990 2.067
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.253 -1.442 -1.607 -1.521 -1.544 -1.432 -1.599 -1.511 -1.589 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–207
I/O Timing
Table 1–104. EP3SE50 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.759
0.876
1.000
-0.750
-0.759
0.876
1.000
-0.750
-0.750
0.867
1.009
-0.759
-0.750
0.867
1.009
-0.759
-0.902
1.015
0.946
-0.697
-0.902
1.015
0.946
-0.697
-0.796
0.924
0.997
-0.734
-0.796
0.924
0.997
-0.734
-0.784
0.912
1.009
-0.746
-0.784
0.912
1.009
-0.746
-0.937
1.063
0.949
-0.689
-0.937
1.063
0.949
-0.689
-1.118 -1.220 -1.326 -1.275 -1.550 -1.228 -1.332 -1.283 -1.587 ns
GCLK
1.305 1.426 1.557 1.492 1.764 1.444 1.573 1.510 1.802
1.666 1.900 2.126 2.009 2.037 1.899 2.125 2.007 2.084
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.267 -1.452 -1.625 -1.539 -1.562 -1.443 -1.616 -1.528 -1.606 ns
-1.118 -1.220 -1.326 -1.275 -1.550 -1.228 -1.332 -1.283 -1.587 ns
tsu
th
GCLK
1.305 1.426 1.557 1.492 1.764 1.444 1.573 1.510 1.802
1.666 1.900 2.126 2.009 2.037 1.899 2.125 2.007 2.084
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.267 -1.452 -1.625 -1.539 -1.562 -1.443 -1.616 -1.528 -1.606 ns
-1.109 -1.210 -1.310 -1.259 -1.534 -1.219 -1.316 -1.267 -1.571 ns
tsu
th
GCLK
1.296 1.416 1.541 1.476 1.748 1.435 1.557 1.494 1.786
1.675 1.910 2.142 2.025 2.053 1.908 2.141 2.023 2.100
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.276 -1.462 -1.641 -1.555 -1.578 -1.452 -1.632 -1.544 -1.622 ns
-1.109 -1.210 -1.310 -1.259 -1.534 -1.219 -1.316 -1.267 -1.571 ns
tsu
th
GCLK
1.296 1.416 1.541 1.476 1.748 1.435 1.557 1.494 1.786
1.675 1.910 2.142 2.025 2.053 1.908 2.141 2.023 2.100
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.276 -1.462 -1.641 -1.555 -1.578 -1.452 -1.632 -1.544 -1.622 ns
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 ns
tsu
th
GCLK
1.491 1.641 1.891 1.822 2.114 1.666 1.908 1.841 2.149
1.600 1.815 1.928 1.810 1.840 1.810 1.931 1.813 1.890
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-1.202 -1.366 -1.426 -1.340 -1.363 -1.352 -1.420 -1.334 -1.410 ns
-1.308 -1.434 -1.661 -1.608 -1.899 -1.450 -1.668 -1.617 -1.932 ns
tsu
th
GCLK
1.491 1.641 1.891 1.822 2.114 1.666 1.908 1.841 2.149
1.600 1.815 1.928 1.810 1.840 1.810 1.931 1.813 1.890
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-1.202 -1.366 -1.426 -1.340 -1.363 -1.352 -1.420 -1.334 -1.410 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–208
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–105 specifies EP3SE50 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–105. EP3SE50 Column Pins output Timing Parameters (Part 1 of 6)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.314
1.791
3.225
1.702
3.192
1.670
3.177
1.656
3.247
1.724
3.169
1.647
3.141
1.619
3.134
1.612
3.323
1.800
3.238
1.715
3.200
1.678
3.173
1.651
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.092
1.609
3.014
1.530
2.983
1.500
2.969
1.486
3.030
1.546
2.958
1.475
2.934
1.451
2.928
1.444
3.089
1.606
3.024
1.539
2.985
1.501
2.962
1.479
4.588 4.978 5.471 5.338 5.574 5.100 5.594 5.461 5.645
2.258 2.371 2.595 2.594 2.538 2.481 2.704 2.707 2.528
4.485 4.867 5.354 5.221 5.457 4.985 5.474 5.341 5.525
2.154 2.259 2.478 2.477 2.421 2.365 2.584 2.587 2.408
4.418 4.796 5.284 5.151 5.387 4.915 5.406 5.273 5.457
2.087 2.189 2.408 2.407 2.351 2.295 2.517 2.520 2.341
4.397 4.772 5.256 5.123 5.359 4.887 5.372 5.239 5.423
2.066 2.166 2.380 2.379 2.323 2.269 2.483 2.486 2.307
4.516 4.896 5.384 5.251 5.487 5.015 5.506 5.373 5.557
2.185 2.288 2.507 2.506 2.450 2.395 2.616 2.619 2.440
4.393 4.769 5.252 5.119 5.355 4.884 5.368 5.235 5.419
2.063 2.162 2.376 2.375 2.319 2.265 2.479 2.482 2.303
4.364 4.742 5.226 5.093 5.329 4.856 5.342 5.209 5.393
2.034 2.135 2.351 2.350 2.294 2.238 2.454 2.457 2.278
4.355 4.733 5.217 5.084 5.320 4.847 5.332 5.199 5.383
2.026 2.126 2.342 2.341 2.285 2.228 2.444 2.447 2.268
4.622 5.015 5.530 5.397 5.633 5.139 5.635 5.502 5.686
2.292 2.407 2.634 2.633 2.577 2.519 2.746 2.749 2.570
4.519 4.904 5.436 5.303 5.539 5.025 5.517 5.384 5.568
2.188 2.295 2.518 2.517 2.461 2.405 2.627 2.630 2.451
4.450 4.831 5.372 5.239 5.475 4.950 5.440 5.307 5.491
2.120 2.224 2.444 2.443 2.387 2.331 2.551 2.554 2.375
4.415 4.793 5.349 5.216 5.452 4.910 5.397 5.264 5.448
2.085 2.185 2.402 2.401 2.345 2.291 2.508 2.511 2.332
4mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
3.3-V
LVTTL
GCLK
12mA
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
8mA
GCLK
PLL
3.3-V
LVCMOS
GCLK
12mA
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
8mA
GCLK
PLL
3.0-V
LVTTL
GCLK
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–209
I/O Timing
Table 1–105. EP3SE50 Column Pins output Timing Parameters (Part 2 of 6)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.262
1.740
3.183
1.661
3.155
1.632
3.154
1.632
3.377
1.855
3.285
1.762
3.240
1.718
3.194
1.672
3.506
1.983
3.395
1.872
3.307
1.785
3.274
1.752
3.210
1.688
3.201
1.678
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.045
1.561
2.971
1.488
2.947
1.464
2.947
1.464
3.148
1.665
3.066
1.582
3.010
1.526
2.976
1.493
3.263
1.779
3.165
1.681
3.082
1.599
3.057
1.573
2.986
1.502
2.981
1.497
4.553 4.937 5.472 5.339 5.575 5.058 5.553 5.420 5.604
2.222 2.329 2.553 2.552 2.496 2.439 2.664 2.667 2.488
4.429 4.807 5.362 5.229 5.465 4.925 5.413 5.280 5.464
2.098 2.200 2.418 2.417 2.361 2.306 2.524 2.527 2.348
4.389 4.767 5.328 5.195 5.431 4.885 5.372 5.239 5.423
2.059 2.160 2.377 2.376 2.320 2.266 2.483 2.486 2.307
4.380 4.758 5.336 5.203 5.439 4.874 5.359 5.226 5.410
2.051 2.151 2.367 2.366 2.310 2.255 2.471 2.474 2.295
4.759 5.162 5.680 5.547 5.783 5.290 5.807 5.674 5.858
2.429 2.556 2.800 2.799 2.743 2.672 2.919 2.922 2.743
4.640 5.037 5.556 5.423 5.659 5.163 5.672 5.539 5.723
2.310 2.430 2.668 2.667 2.611 2.544 2.783 2.786 2.607
4.548 4.941 5.478 5.345 5.581 5.065 5.570 5.437 5.621
2.218 2.334 2.568 2.567 2.511 2.446 2.681 2.684 2.505
4.514 4.904 5.421 5.288 5.524 5.025 5.526 5.393 5.577
2.184 2.297 2.527 2.526 2.470 2.406 2.637 2.640 2.461
4.954 5.373 5.898 5.765 6.001 5.511 6.035 5.902 6.086
2.623 2.765 3.018 3.017 2.961 2.890 3.145 3.148 2.969
4.802 5.214 5.746 5.613 5.849 5.351 5.869 5.736 5.920
2.471 2.607 2.857 2.856 2.800 2.731 2.979 2.982 2.803
4.674 5.075 5.605 5.472 5.708 5.205 5.720 5.587 5.771
2.344 2.469 2.713 2.712 2.656 2.587 2.831 2.834 2.655
4.614 5.010 5.526 5.393 5.629 5.135 5.640 5.507 5.691
2.284 2.403 2.638 2.637 2.581 2.516 2.751 2.754 2.575
4.526 4.916 5.444 5.311 5.547 5.038 5.539 5.406 5.590
2.196 2.309 2.539 2.538 2.482 2.419 2.650 2.653 2.474
4.520 4.910 5.438 5.305 5.541 5.031 5.532 5.399 5.583
2.190 2.303 2.532 2.531 2.475 2.412 2.643 2.646 2.467
4mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
12mA
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
8mA
GCLK
PLL
2.5 V
GCLK
12mA
16mA
2mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
4mA
GCLK
PLL
GCLK
6mA
GCLK
PLL
1.8 V
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
GCLK
PLL
GCLK
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–210
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–105. EP3SE50 Column Pins output Timing Parameters (Part 3 of 6)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.473
1.950
3.291
1.769
3.254
1.732
3.248
1.726
3.198
1.675
3.191
1.668
3.416
1.893
3.280
1.758
3.239
1.717
3.205
1.683
3.213
1.691
3.216
1.694
3.196
1.674
3.189
1.667
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.203
1.719
3.071
1.588
3.027
1.543
3.016
1.532
2.980
1.497
2.976
1.493
3.183
1.699
3.060
1.576
3.006
1.523
2.986
1.503
3.000
1.516
3.003
1.519
2.984
1.501
2.979
1.496
4.893 5.301 5.837 5.704 5.940 5.440 5.968 5.835 6.019
2.562 2.692 2.946 2.945 2.889 2.820 3.078 3.081 2.902
4.648 5.044 5.568 5.435 5.671 5.171 5.680 5.547 5.731
2.318 2.438 2.675 2.674 2.618 2.552 2.791 2.794 2.615
4.568 4.965 5.506 5.373 5.609 5.091 5.597 5.464 5.648
2.238 2.358 2.595 2.594 2.538 2.472 2.708 2.711 2.532
4.562 4.957 5.499 5.366 5.602 5.084 5.589 5.456 5.640
2.232 2.350 2.586 2.585 2.529 2.465 2.701 2.704 2.525
4.514 4.904 5.440 5.307 5.543 5.025 5.525 5.392 5.576
2.184 2.297 2.525 2.524 2.468 2.406 2.636 2.639 2.460
4.493 4.882 5.437 5.304 5.540 5.004 5.503 5.370 5.554
2.163 2.276 2.505 2.504 2.448 2.385 2.614 2.617 2.438
4.847 5.254 5.783 5.650 5.886 5.387 5.903 5.770 5.954
2.516 2.646 2.889 2.888 2.832 2.767 3.012 3.015 2.836
4.627 5.021 5.559 5.426 5.662 5.147 5.652 5.519 5.703
2.297 2.415 2.649 2.648 2.592 2.528 2.763 2.766 2.587
4.551 4.945 5.505 5.372 5.608 5.072 5.579 5.446 5.630
2.221 2.338 2.575 2.574 2.518 2.453 2.691 2.694 2.515
4.512 4.902 5.470 5.337 5.573 5.023 5.523 5.390 5.574
2.182 2.295 2.525 2.524 2.468 2.404 2.634 2.637 2.458
4.519 4.909 5.462 5.329 5.565 5.027 5.527 5.394 5.578
2.190 2.303 2.533 2.532 2.476 2.409 2.639 2.642 2.463
4.523 4.913 5.468 5.335 5.571 5.031 5.531 5.398 5.582
2.194 2.307 2.537 2.536 2.480 2.413 2.643 2.646 2.467
4.501 4.892 5.441 5.308 5.544 5.010 5.509 5.376 5.560
2.172 2.285 2.515 2.514 2.458 2.392 2.621 2.624 2.445
4.486 4.875 5.439 5.306 5.542 4.993 5.491 5.358 5.542
2.157 2.269 2.498 2.497 2.441 2.375 2.603 2.606 2.427
2mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
1.5 V
GCLK
8mA
GCLK
PLL
GCLK
10mA
12mA
2mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
4mA
GCLK
PLL
1.2 V
GCLK
6mA
GCLK
PLL
GCLK
8mA
GCLK
PLL
GCLK
8mA
GCLK
PLL
GCLK
SSTL-2
CLASS I
10mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–211
I/O Timing
Table 1–105. EP3SE50 Column Pins output Timing Parameters (Part 4 of 6)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.233
1.711
3.213
1.690
3.215
1.693
3.195
1.673
3.192
1.669
3.190
1.668
3.190
1.668
3.224
1.702
3.208
1.686
3.194
1.671
3.194
1.672
3.189
1.667
3.206
1.684
3.206
1.684
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.018
1.534
2.999
1.515
3.000
1.516
2.983
1.499
2.979
1.496
2.979
1.496
2.978
1.495
3.009
1.526
2.994
1.511
2.981
1.498
2.981
1.498
2.977
1.494
2.995
1.512
2.994
1.511
4.542 4.932 5.492 5.359 5.595 5.051 5.550 5.417 5.601
2.213 2.326 2.556 2.555 2.499 2.433 2.663 2.666 2.487
4.520 4.910 5.468 5.335 5.571 5.029 5.528 5.395 5.579
2.191 2.304 2.534 2.533 2.477 2.411 2.640 2.643 2.464
4.528 4.919 5.488 5.355 5.591 5.039 5.539 5.406 5.590
2.199 2.313 2.544 2.543 2.487 2.421 2.651 2.654 2.475
4.504 4.894 5.463 5.330 5.566 5.013 5.514 5.381 5.565
2.174 2.288 2.519 2.518 2.462 2.395 2.625 2.628 2.449
4.500 4.890 5.458 5.325 5.561 5.009 5.510 5.377 5.561
2.170 2.284 2.514 2.513 2.457 2.391 2.621 2.624 2.445
4.487 4.876 5.443 5.310 5.546 4.994 5.492 5.359 5.543
2.158 2.269 2.498 2.497 2.441 2.376 2.604 2.607 2.428
4.495 4.886 5.450 5.317 5.553 5.004 5.505 5.372 5.556
2.166 2.279 2.510 2.509 2.453 2.386 2.617 2.620 2.441
4.534 4.924 5.485 5.352 5.588 5.044 5.543 5.410 5.594
2.206 2.319 2.548 2.547 2.491 2.426 2.655 2.658 2.479
4.521 4.912 5.481 5.348 5.584 5.032 5.532 5.399 5.583
2.192 2.306 2.536 2.535 2.479 2.413 2.644 2.647 2.468
4.501 4.892 5.463 5.330 5.566 5.011 5.511 5.378 5.562
2.172 2.285 2.516 2.515 2.459 2.393 2.623 2.626 2.447
4.502 4.893 5.474 5.341 5.577 5.013 5.514 5.381 5.565
2.173 2.287 2.519 2.518 2.462 2.395 2.626 2.629 2.450
4.495 4.886 5.466 5.333 5.569 5.005 5.506 5.373 5.557
2.166 2.280 2.511 2.510 2.454 2.387 2.618 2.621 2.442
4.502 4.891 5.454 5.321 5.557 5.009 5.507 5.374 5.558
2.174 2.285 2.513 2.512 2.456 2.391 2.619 2.622 2.443
4.507 4.896 5.472 5.339 5.575 5.015 5.513 5.380 5.564
2.178 2.290 2.519 2.518 2.462 2.396 2.625 2.628 2.449
4mA
6mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-18
CLASS I
8mA
GCLK
PLL
GCLK
10mA
12mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-18
CLASS II
GCLK
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
GCLK
SSTL-15
CLASS I
8mA
GCLK
PLL
GCLK
10mA
12mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS II
GCLK
16mA
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–212
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–105. EP3SE50 Column Pins output Timing Parameters (Part 5 of 6)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.192
1.670
3.187
1.665
3.190
1.668
3.188
1.666
3.207
1.685
3.203
1.681
3.203
1.680
3.192
1.670
3.195
1.672
3.219
1.697
3.207
1.685
3.206
1.683
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.981
1.498
2.976
1.493
2.978
1.495
2.978
1.494
2.996
1.513
2.991
1.508
2.990
1.507
2.981
1.498
2.983
1.499
3.004
1.521
2.994
1.511
2.992
1.509
4.491 4.880 5.454 5.321 5.557 4.998 5.497 5.364 5.548
2.162 2.274 2.503 2.502 2.446 2.380 2.609 2.612 2.433
4.485 4.874 5.443 5.310 5.546 4.992 5.491 5.358 5.542
2.156 2.268 2.497 2.496 2.440 2.374 2.603 2.606 2.427
4.490 4.880 5.464 5.331 5.567 4.998 5.497 5.364 5.548
2.161 2.273 2.503 2.502 2.446 2.380 2.609 2.612 2.433
4.483 4.872 5.445 5.312 5.548 4.990 5.488 5.355 5.539
2.154 2.266 2.495 2.494 2.438 2.372 2.600 2.603 2.424
4.505 4.893 5.459 5.326 5.562 5.011 5.509 5.376 5.560
2.176 2.287 2.516 2.515 2.459 2.394 2.621 2.624 2.445
4.503 4.892 5.466 5.333 5.569 5.011 5.509 5.376 5.560
2.174 2.286 2.515 2.514 2.458 2.393 2.621 2.624 2.445
4.504 4.893 5.467 5.334 5.570 5.012 5.510 5.377 5.561
2.175 2.287 2.516 2.515 2.459 2.394 2.622 2.625 2.446
4.491 4.881 5.454 5.321 5.557 4.999 5.498 5.365 5.549
2.162 2.275 2.504 2.503 2.447 2.381 2.610 2.613 2.434
4.497 4.887 5.469 5.336 5.572 5.006 5.506 5.373 5.557
2.168 2.281 2.512 2.511 2.455 2.388 2.618 2.621 2.442
4.525 4.915 5.487 5.354 5.590 5.034 5.533 5.400 5.584
2.196 2.308 2.538 2.537 2.481 2.416 2.645 2.648 2.469
4.513 4.903 5.477 5.344 5.580 5.022 5.522 5.389 5.573
2.184 2.297 2.527 2.526 2.470 2.404 2.634 2.637 2.458
4.511 4.902 5.482 5.349 5.585 5.021 5.521 5.388 5.572
2.182 2.295 2.525 2.524 2.468 2.403 2.633 2.636 2.457
4mA
6mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
8mA
GCLK
PLL
CLASS I
GCLK
10mA
12mA
16mA
4mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
GCLK
6mA
GCLK
PLL
GCLK
1.5-V
HSTL
8mA
GCLK
PLL
CLASS I
GCLK
10mA
12mA
16mA
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.5-V
HSTL
GCLK
PLL
CLASS II
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–213
I/O Timing
Table 1–105. EP3SE50 Column Pins output Timing Parameters (Part 6 of 6)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.203
1.681
3.199
1.677
3.274
1.752
3.274
1.752
3.314
1.791
3.225
1.702
3.192
1.670
3.177
1.656
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.990
1.507
2.986
1.503
3.063
1.580
3.063
1.580
3.092
1.609
3.014
1.530
2.983
1.500
2.969
1.486
4.509 4.901 5.484 5.351 5.587 5.020 5.520 5.387 5.571
2.181 2.295 2.525 2.524 2.468 2.402 2.633 2.636 2.457
4.503 4.894 5.475 5.342 5.578 5.013 5.513 5.380 5.564
2.174 2.288 2.518 2.517 2.461 2.395 2.625 2.628 2.449
4.522 4.903 5.451 5.318 5.554 5.022 5.512 5.379 5.563
2.192 2.296 2.515 2.514 2.458 2.403 2.623 2.626 2.447
4.522 4.903 5.451 5.318 5.554 5.022 5.512 5.379 5.563
2.192 2.296 2.515 2.514 2.458 2.403 2.623 2.626 2.447
4.588 4.978 5.471 5.338 5.574 5.100 5.594 5.461 5.645
2.258 2.371 2.595 2.594 2.538 2.481 2.704 2.707 2.528
4.485 4.867 5.354 5.221 5.457 4.985 5.474 5.341 5.525
2.154 2.259 2.478 2.477 2.421 2.365 2.584 2.587 2.408
4.418 4.796 5.284 5.151 5.387 4.915 5.406 5.273 5.457
2.087 2.189 2.408 2.407 2.351 2.295 2.517 2.520 2.341
4.397 4.772 5.256 5.123 5.359 4.887 5.372 5.239 5.423
2.066 2.166 2.380 2.379 2.323 2.269 2.483 2.486 2.307
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.2-V
HSTL
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.2-V
HSTL
CLASS II
GCLK
PLL
GCLK
3.0-V PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
Table 1–106 specifies EP3SE50 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–106. EP3SE50 Row Pins output Timing Parameters (Part 1 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Clock
Units
Standard
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.395
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
3.161
1.488
3.095
1.395
3.016
1.314
4.722 5.117 5.622 5.486 5.755 5.247 5.754 5.618 5.832
2.101 2.185 2.381 2.400 2.349 2.304 2.505 2.523 2.344
4.612 5.005 5.508 5.372 5.611 5.134 5.638 5.502 5.683
1.971 2.047 2.237 2.256 2.205 2.163 2.356 2.374 2.195
4.506 4.905 5.412 5.276 5.483 5.035 5.539 5.403 5.551
1.852 1.924 2.109 2.128 2.077 2.036 2.224 2.242 2.063
4mA
8mA
12mA
GCLK
PLL
1.692
GCLK
3.324
3.3-V
LVTTL
GCLK
PLL
1.587
GCLK
3.235
GCLK
PLL
1.493
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–214
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–106. EP3SE50 Row Pins output Timing Parameters (Part 2 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.402
1.696
3.239
1.497
3.356
1.638
3.244
1.511
3.206
1.464
3.268
1.557
3.190
1.448
3.393
1.674
3.290
1.575
3.246
1.504
3.663
1.863
3.461
1.677
3.359
1.595
3.285
1.575
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.163
1.498
3.020
1.318
3.122
1.442
3.021
1.319
2.984
1.282
3.043
1.356
2.971
1.269
3.148
1.468
3.063
1.361
3.006
1.312
3.405
1.650
3.180
1.477
3.115
1.402
3.055
1.384
4.726 5.122 5.631 5.495 5.760 5.255 5.766 5.630 5.837
2.109 2.190 2.386 2.405 2.354 2.310 2.510 2.528 2.349
4.517 4.920 5.422 5.286 5.489 5.047 5.548 5.412 5.558
1.858 1.930 2.115 2.134 2.083 2.042 2.231 2.249 2.070
4.689 5.085 5.588 5.452 5.712 5.215 5.720 5.584 5.790
2.053 2.138 2.338 2.357 2.306 2.261 2.463 2.481 2.302
4.552 4.943 5.443 5.307 5.548 5.073 5.575 5.438 5.625
1.900 1.979 2.174 2.193 2.142 2.099 2.299 2.316 2.137
4.492 4.878 5.373 5.237 5.460 5.005 5.501 5.365 5.532
1.818 1.896 2.086 2.105 2.054 2.013 2.206 2.223 2.044
4.587 4.978 5.479 5.343 5.601 5.107 5.611 5.474 5.678
1.947 2.031 2.227 2.246 2.195 2.153 2.352 2.369 2.190
4.464 4.849 5.345 5.209 5.421 4.975 5.473 5.336 5.492
1.783 1.857 2.047 2.066 2.015 1.973 2.166 2.183 2.004
4.797 5.211 5.733 5.597 5.884 5.347 5.872 5.736 5.968
2.185 2.292 2.510 2.529 2.478 2.421 2.642 2.659 2.480
4.673 5.076 5.591 5.455 5.714 5.210 5.728 5.591 5.794
2.030 2.129 2.340 2.359 2.308 2.254 2.468 2.485 2.306
4.589 4.990 5.500 5.364 5.588 5.121 5.633 5.497 5.664
1.919 2.010 2.214 2.233 2.182 2.131 2.338 2.355 2.176
5.253 5.717 6.292 6.156 6.368 5.867 6.444 6.308 6.461
2.459 2.597 2.849 2.868 2.787 2.729 2.984 3.002 2.793
4.926 5.349 5.887 5.751 5.963 5.502 6.038 5.901 6.054
2.168 2.271 2.489 2.508 2.427 2.403 2.623 2.640 2.431
4.773 5.199 5.728 5.592 5.804 5.334 5.865 5.729 5.882
2.069 2.166 2.388 2.407 2.326 2.289 2.517 2.535 2.326
4.696 5.106 5.632 5.496 5.708 5.239 5.771 5.635 5.788
2.012 2.113 2.323 2.342 2.261 2.233 2.445 2.463 2.254
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
2mA
4mA
6mA
8mA
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V
LVTTL
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.8 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–215
I/O Timing
Table 1–106. EP3SE50 Row Pins output Timing Parameters (Part 3 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.581
1.806
3.324
1.592
3.276
1.566
3.267
1.555
3.506
1.719
3.317
1.596
3.234
1.492
3.230
1.488
3.219
1.477
3.241
1.519
3.227
1.514
3.215
1.503
3.192
1.492
3.191
1.491
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.316
1.592
3.074
1.400
3.047
1.373
3.038
1.354
3.259
1.522
3.079
1.405
3.010
1.308
3.005
1.303
2.996
1.294
3.016
1.333
3.001
1.328
2.990
1.317
2.966
1.306
2.966
1.306
5.163 5.631 6.220 6.084 6.296 5.774 6.368 6.232 6.385
2.387 2.524 2.786 2.805 2.724 2.650 2.919 2.937 2.728
4.758 5.194 5.729 5.593 5.805 5.328 5.864 5.728 5.881
2.065 2.166 2.392 2.411 2.330 2.286 2.518 2.536 2.327
4.685 5.098 5.623 5.487 5.699 5.230 5.759 5.623 5.776
1.996 2.105 2.323 2.342 2.261 2.226 2.445 2.463 2.254
4.663 5.080 5.604 5.468 5.680 5.212 5.737 5.601 5.754
1.980 2.081 2.304 2.323 2.242 2.202 2.426 2.444 2.235
5.073 5.545 6.145 6.009 6.221 5.686 6.284 6.148 6.301
2.308 2.456 2.725 2.744 2.663 2.582 2.850 2.868 2.659
4.780 5.222 5.770 5.634 5.846 5.353 5.906 5.770 5.923
2.082 2.194 2.440 2.459 2.378 2.315 2.562 2.580 2.371
4.582 4.981 5.490 5.354 5.556 5.108 5.619 5.483 5.627
1.899 1.984 2.183 2.202 2.150 2.100 2.301 2.318 2.139
4.579 4.979 5.488 5.352 5.548 5.107 5.618 5.482 5.620
1.896 1.982 2.181 2.200 2.142 2.099 2.300 2.317 2.132
4.564 4.963 5.471 5.335 5.521 5.090 5.600 5.464 5.593
1.881 1.966 2.164 2.183 2.115 2.082 2.282 2.299 2.105
4.591 4.993 5.505 5.369 5.581 5.120 5.634 5.498 5.651
1.931 2.017 2.218 2.237 2.156 2.132 2.336 2.354 2.145
4.588 4.991 5.503 5.367 5.579 5.118 5.632 5.496 5.649
1.929 2.016 2.217 2.236 2.155 2.130 2.334 2.352 2.143
4.571 4.974 5.486 5.350 5.562 5.101 5.616 5.480 5.633
1.919 2.006 2.207 2.226 2.145 2.121 2.325 2.343 2.134
4.555 4.958 5.471 5.335 5.547 5.086 5.601 5.465 5.618
1.906 1.993 2.194 2.213 2.132 2.109 2.313 2.331 2.122
4.554 4.957 5.470 5.334 5.546 5.085 5.600 5.464 5.617
1.906 1.993 2.194 2.213 2.132 2.108 2.313 2.331 2.122
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
4mA
6mA
8mA
10mA
12mA
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-2
CLASS I
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-18
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–216
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–106. EP3SE50 Row Pins output Timing Parameters (Part 4 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.200
1.498
3.198
1.501
3.237
1.522
3.215
1.508
3.198
1.496
3.213
1.504
3.201
1.498
3.189
1.490
3.191
1.492
3.186
1.489
3.194
1.497
3.220
1.510
3.210
1.505
3.205
1.501
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.976
1.314
2.975
1.315
3.012
1.336
2.989
1.322
2.972
1.311
2.991
1.321
2.979
1.314
2.966
1.305
2.968
1.308
2.964
1.304
2.972
1.312
2.998
1.327
2.986
1.321
2.982
1.317
4.552 4.953 5.464 5.328 5.540 5.080 5.593 5.457 5.610
1.905 1.990 2.189 2.208 2.127 2.104 2.307 2.325 2.116
4.551 4.954 5.466 5.330 5.542 5.082 5.597 5.461 5.614
1.911 1.998 2.199 2.218 2.137 2.113 2.318 2.336 2.127
4.602 5.007 5.522 5.386 5.598 5.133 5.650 5.514 5.667
1.940 2.028 2.231 2.250 2.169 2.142 2.348 2.366 2.157
4.584 4.990 5.505 5.369 5.581 5.117 5.634 5.498 5.651
1.929 2.018 2.221 2.240 2.159 2.133 2.339 2.357 2.148
4.567 4.972 5.487 5.351 5.563 5.099 5.617 5.481 5.634
1.916 2.005 2.208 2.227 2.146 2.120 2.326 2.344 2.135
4.558 4.958 5.467 5.331 5.543 5.084 5.596 5.460 5.613
1.904 1.988 2.187 2.206 2.125 2.103 2.304 2.322 2.113
4.549 4.950 5.459 5.323 5.535 5.076 5.589 5.453 5.606
1.902 1.987 2.186 2.205 2.124 2.102 2.304 2.322 2.113
4.541 4.941 5.451 5.315 5.527 5.068 5.581 5.445 5.598
1.895 1.980 2.179 2.198 2.117 2.095 2.297 2.315 2.106
4.543 4.944 5.454 5.318 5.530 5.071 5.584 5.448 5.601
1.898 1.983 2.183 2.202 2.121 2.098 2.300 2.318 2.109
4.541 4.943 5.454 5.318 5.530 5.071 5.585 5.449 5.602
1.900 1.986 2.186 2.205 2.124 2.101 2.305 2.323 2.114
4.536 4.935 5.445 5.309 5.521 5.062 5.574 5.438 5.591
1.898 1.983 2.182 2.201 2.120 2.097 2.299 2.317 2.108
4.569 4.971 5.482 5.346 5.558 5.096 5.610 5.474 5.627
1.913 1.998 2.198 2.217 2.136 2.112 2.315 2.333 2.124
4.565 4.967 5.478 5.342 5.554 5.093 5.607 5.471 5.624
1.914 2.000 2.200 2.219 2.138 2.114 2.318 2.336 2.127
4.559 4.961 5.472 5.336 5.548 5.087 5.601 5.465 5.618
1.909 1.995 2.195 2.214 2.133 2.109 2.312 2.330 2.121
8mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
SSTL-15
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.8-V
HSTL
CLASS II
GCLK
PLL
GCLK
GCLK
PLL
GCLK
1.5-V
HSTL
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–217
I/O Timing
Table 1–106. EP3SE50 Row Pins output Timing Parameters (Part 5 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Clock
Units
Standard
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.219
1.512
3.207
1.504
3.205
1.504
3.340
1.598
3.340
1.598
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.997
1.329
2.985
1.320
2.982
1.319
3.116
1.414
3.116
1.414
4.580 4.985 5.500 5.364 5.576 5.110 5.627 5.491 5.644
1.926 2.014 2.217 2.236 2.155 2.128 2.334 2.352 2.143
4.569 4.973 5.488 5.352 5.564 5.099 5.616 5.480 5.633
1.917 2.005 2.208 2.227 2.146 2.119 2.325 2.343 2.134
4.573 4.978 5.494 5.358 5.570 5.105 5.623 5.487 5.640
1.924 2.013 2.217 2.236 2.155 2.128 2.335 2.353 2.144
4.634 5.027 5.530 5.394 5.578 5.156 5.661 5.525 5.651
1.951 2.030 2.223 2.242 2.160 2.148 2.343 2.360 2.151
4.634 5.027 5.530 5.394 5.578 5.156 5.661 5.525 5.651
1.951 2.030 2.223 2.242 2.160 2.148 2.343 2.360 2.151
4mA
6mA
8mA
—
GCLK
PLL
GCLK
1.2-V
HSTL
CLASS I
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
Table 1–117 through Table 1–110 show the maximum I/O timing parameters for
EP3SE50 devices for differential I/O standards.
Table 1–107 specifies EP3SE50 column pins input timing parameters for differential
I/O standards.
Table 1–107. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.730
0.848
1.120
-0.867
-0.730
0.848
1.120
-0.867
-0.738
0.856
1.112
-0.859
-0.738
0.856
1.112
-0.859
-0.751
0.884
1.138
-0.870
-0.751
0.884
1.138
-0.870
-0.763
0.896
1.126
-0.858
-0.763
0.896
1.126
-0.858
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 ns
GCLK
1.299 1.436 1.571 1.501 1.798 1.446 1.583 1.516 1.835
1.796 2.027 2.253 2.141 2.145 2.036 2.262 2.145 2.193
ns
ns
LVDS
tsu
th
GCLK
PLL
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 ns
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 ns
tsu
th
GCLK
1.299 1.436 1.571 1.501 1.798 1.446 1.583 1.516 1.835
1.796 2.027 2.253 2.141 2.145 2.036 2.262 2.145 2.193
ns
ns
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 ns
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 ns
tsu
th
GCLK
1.309 1.447 1.587 1.517 1.814 1.457 1.598 1.531 1.850
1.786 2.016 2.237 2.125 2.129 2.025 2.247 2.130 2.178
ns
ns
tsu
th
GCLK
PLL
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 ns
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
1.309 1.447 1.587 1.517 1.814 1.457 1.598 1.531 1.850
1.786 2.016 2.237 2.125 2.129 2.025 2.247 2.130 2.178
ns
ns
tsu
th
GCLK
PLL
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–218
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–107. EP3SE50 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.750
0.868
1.100
-0.847
-0.750
0.868
1.100
-0.847
-0.738
0.856
1.112
-0.859
-0.738
0.856
1.112
-0.859
-0.750
0.868
1.100
-0.847
-0.750
0.868
1.100
-0.847
-0.757
0.875
1.093
-0.840
-0.757
0.875
1.093
-0.840
-0.730
0.848
1.120
-0.867
-0.774
0.907
1.115
-0.847
-0.774
0.907
1.115
-0.847
-0.763
0.896
1.126
-0.858
-0.763
0.896
1.126
-0.858
-0.774
0.907
1.115
-0.847
-0.774
0.907
1.115
-0.847
-0.780
0.913
1.109
-0.841
-0.780
0.913
1.109
-0.841
-0.751
0.884
1.138
-0.870
-1.133 -1.250 -1.376 -1.319 -1.616 -1.252 -1.377 -1.323 -1.650 ns
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
1.319 1.458 1.606 1.536 1.833 1.468 1.616 1.549 1.868
1.777 2.005 2.218 2.106 2.110 2.014 2.229 2.112 2.160
ns
ns
tsu
th
GCLK
PLL
-1.377 -1.556 -1.717 -1.634 -1.631 -1.558 -1.721 -1.632 -1.677 ns
-1.133 -1.250 -1.376 -1.319 -1.616 -1.252 -1.377 -1.323 -1.650 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
1.319 1.458 1.606 1.536 1.833 1.468 1.616 1.549 1.868
1.777 2.005 2.218 2.106 2.110 2.014 2.229 2.112 2.160
ns
ns
tsu
th
GCLK
PLL
-1.377 -1.556 -1.717 -1.634 -1.631 -1.558 -1.721 -1.632 -1.677 ns
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
1.309 1.447 1.587 1.517 1.814 1.457 1.598 1.531 1.850
1.786 2.016 2.237 2.125 2.129 2.025 2.247 2.130 2.178
ns
ns
tsu
th
GCLK
PLL
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 ns
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
1.309 1.447 1.587 1.517 1.814 1.457 1.598 1.531 1.850
1.786 2.016 2.237 2.125 2.129 2.025 2.247 2.130 2.178
ns
ns
tsu
th
GCLK
PLL
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 ns
-1.133 -1.250 -1.376 -1.319 -1.616 -1.252 -1.377 -1.323 -1.650 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
1.319 1.458 1.606 1.536 1.833 1.468 1.616 1.549 1.868
1.777 2.005 2.218 2.106 2.110 2.014 2.229 2.112 2.160
ns
ns
tsu
th
GCLK
PLL
-1.377 -1.556 -1.717 -1.634 -1.631 -1.558 -1.721 -1.632 -1.677 ns
-1.133 -1.250 -1.376 -1.319 -1.616 -1.252 -1.377 -1.323 -1.650 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
1.319 1.458 1.606 1.536 1.833 1.468 1.616 1.549 1.868
1.777 2.005 2.218 2.106 2.110 2.014 2.229 2.112 2.160
ns
ns
tsu
th
GCLK
PLL
-1.377 -1.556 -1.717 -1.634 -1.631 -1.558 -1.721 -1.632 -1.677 ns
-1.145 -1.255 -1.376 -1.321 -1.615 -1.256 -1.372 -1.321 -1.646 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
1.332 1.466 1.609 1.539 1.837 1.475 1.616 1.548 1.869
1.765 2.000 2.218 2.104 2.111 2.010 2.234 2.114 2.164
ns
ns
tsu
th
GCLK
PLL
-1.364 -1.548 -1.714 -1.631 -1.627 -1.551 -1.721 -1.633 -1.676 ns
-1.145 -1.255 -1.376 -1.321 -1.615 -1.256 -1.372 -1.321 -1.646 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
1.332 1.466 1.609 1.539 1.837 1.475 1.616 1.548 1.869
1.765 2.000 2.218 2.104 2.111 2.010 2.234 2.114 2.164
ns
ns
tsu
th
GCLK
PLL
-1.364 -1.548 -1.714 -1.631 -1.627 -1.551 -1.721 -1.633 -1.676 ns
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
1.299 1.436 1.571 1.501 1.798 1.446 1.583 1.516 1.835
1.796 2.027 2.253 2.141 2.145 2.036 2.262 2.145 2.193
ns
ns
tsu
th
GCLK
PLL
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–219
I/O Timing
Table 1–107. EP3SE50 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.730
0.848
1.120
-0.867
-0.738
0.856
1.112
-0.859
-0.751
0.884
1.138
-0.870
-0.763
0.896
1.126
-0.858
-1.114 -1.228 -1.341 -1.284 -1.581 -1.230 -1.344 -1.290 -1.617 ns
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
1.299 1.436 1.571 1.501 1.798 1.446 1.583 1.516 1.835
1.796 2.027 2.253 2.141 2.145 2.036 2.262 2.145 2.193
ns
ns
tsu
th
GCLK
PLL
-1.397 -1.578 -1.752 -1.669 -1.666 -1.580 -1.754 -1.665 -1.710 ns
-1.124 -1.239 -1.357 -1.300 -1.597 -1.241 -1.359 -1.305 -1.632 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
1.309 1.447 1.587 1.517 1.814 1.457 1.598 1.531 1.850
1.786 2.016 2.237 2.125 2.129 2.025 2.247 2.130 2.178
ns
ns
tsu
th
GCLK
PLL
-1.387 -1.567 -1.736 -1.653 -1.650 -1.569 -1.739 -1.650 -1.695 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–220
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–108 specifies EP3SE50 row pins input timing parameters for differential I/O
standards.
Table 1–108. EP3SE50 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.925
1.048
0.886
-0.626
-0.925
1.048
0.886
-0.626
-0.925
1.048
0.886
-0.626
-0.740
0.856
1.081
-0.828
-0.740
0.856
1.081
-0.828
-0.749
0.865
1.072
-0.819
-0.749
0.865
1.072
-0.819
-0.763
0.879
1.058
-0.805
-0.948
1.086
0.901
-0.628
-0.948
1.086
0.901
-0.628
-0.948
1.086
0.901
-0.628
-0.773
0.902
1.086
-0.822
-0.773
0.902
1.086
-0.822
-0.785
0.914
1.074
-0.810
-0.785
0.914
1.074
-0.810
-0.797
0.926
1.062
-0.798
-1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 ns
GCLK
1.223 1.219 1.381 1.322 1.601 1.199 1.353 1.296 1.634
1.866 2.244 2.450 2.324 2.344 2.289 2.502 2.376 2.396
ns
ns
LVDS
tsu
th
GCLK
PLL
-1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 ns
-1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 ns
tsu
th
GCLK
1.223 1.219 1.381 1.322 1.601 1.199 1.353 1.296 1.634
1.866 2.244 2.450 2.324 2.344 2.289 2.502 2.376 2.396
ns
ns
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
-1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 ns
-1.004 -0.967 -1.102 -1.057 -1.337 -0.933 -1.060 -1.017 -1.369 ns
tsu
th
GCLK
1.223 1.219 1.381 1.322 1.601 1.199 1.353 1.296 1.634
1.866 2.244 2.450 2.324 2.344 2.289 2.502 2.376 2.396
ns
ns
tsu
th
GCLK
PLL
-1.432 -1.750 -1.897 -1.803 -1.817 -1.782 -1.937 -1.842 -1.867 ns
-1.101 -1.201 -1.301 -1.251 -1.526 -1.210 -1.307 -1.259 -1.563 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
1.288 1.408 1.531 1.467 1.741 1.427 1.548 1.486 1.779
1.779 2.020 2.261 2.140 2.165 2.022 2.265 2.144 2.212
ns
ns
tsu
th
GCLK
PLL
-1.377 -1.571 -1.757 -1.668 -1.687 -1.564 -1.752 -1.662 -1.732 ns
-1.101 -1.201 -1.301 -1.251 -1.526 -1.210 -1.307 -1.259 -1.563 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
1.288 1.408 1.531 1.467 1.741 1.427 1.548 1.486 1.779
1.779 2.020 2.261 2.140 2.165 2.022 2.265 2.144 2.212
ns
ns
tsu
th
GCLK
PLL
-1.377 -1.571 -1.757 -1.668 -1.687 -1.564 -1.752 -1.662 -1.732 ns
-1.110 -1.211 -1.317 -1.267 -1.542 -1.219 -1.323 -1.275 -1.579 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
1.297 1.418 1.547 1.483 1.757 1.436 1.564 1.502 1.795
1.770 2.010 2.245 2.124 2.149 2.013 2.249 2.128 2.196
ns
ns
tsu
th
GCLK
PLL
-1.368 -1.561 -1.741 -1.652 -1.671 -1.555 -1.736 -1.646 -1.716 ns
-1.110 -1.211 -1.317 -1.267 -1.542 -1.219 -1.323 -1.275 -1.579 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
1.297 1.418 1.547 1.483 1.757 1.436 1.564 1.502 1.795
1.770 2.010 2.245 2.124 2.149 2.013 2.249 2.128 2.196
ns
ns
tsu
th
GCLK
PLL
-1.368 -1.561 -1.741 -1.652 -1.671 -1.555 -1.736 -1.646 -1.716 ns
-1.123 -1.221 -1.335 -1.285 -1.560 -1.230 -1.340 -1.292 -1.596 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
1.309 1.428 1.565 1.501 1.775 1.447 1.581 1.519 1.812
1.757 2.000 2.227 2.106 2.131 2.002 2.232 2.111 2.179
ns
ns
tsu
th
GCLK
PLL
-1.356 -1.551 -1.723 -1.634 -1.653 -1.544 -1.719 -1.629 -1.699 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–221
I/O Timing
Table 1–108. EP3SE50 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-0.763
0.879
1.058
-0.805
-0.749
0.865
1.072
-0.819
-0.749
0.865
1.072
-0.819
-0.763
0.879
1.058
-0.805
-0.763
0.879
1.058
-0.805
-0.762
0.878
1.049
-0.796
-0.762
0.878
1.049
-0.796
-0.797
0.926
1.062
-0.798
-0.785
0.914
1.074
-0.810
-0.785
0.914
1.074
-0.810
-0.797
0.926
1.062
-0.798
-0.797
0.926
1.062
-0.798
-0.796
0.925
1.053
-0.789
-0.796
0.925
1.053
-0.789
-1.123 -1.221 -1.335 -1.285 -1.560 -1.230 -1.340 -1.292 -1.596 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
1.309 1.428 1.565 1.501 1.775 1.447 1.581 1.519 1.812
1.757 2.000 2.227 2.106 2.131 2.002 2.232 2.111 2.179
ns
ns
tsu
th
GCLK
PLL
-1.356 -1.551 -1.723 -1.634 -1.653 -1.544 -1.719 -1.629 -1.699 ns
-1.110 -1.211 -1.317 -1.267 -1.542 -1.219 -1.323 -1.275 -1.579 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
1.297 1.418 1.547 1.483 1.757 1.436 1.564 1.502 1.795
1.770 2.010 2.245 2.124 2.149 2.013 2.249 2.128 2.196
ns
ns
tsu
th
GCLK
PLL
-1.368 -1.561 -1.741 -1.652 -1.671 -1.555 -1.736 -1.646 -1.716 ns
-1.110 -1.211 -1.317 -1.267 -1.542 -1.219 -1.323 -1.275 -1.579 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
1.297 1.418 1.547 1.483 1.757 1.436 1.564 1.502 1.795
1.770 2.010 2.245 2.124 2.149 2.013 2.249 2.128 2.196
ns
ns
tsu
th
GCLK
PLL
-1.368 -1.561 -1.741 -1.652 -1.671 -1.555 -1.736 -1.646 -1.716 ns
-1.123 -1.221 -1.335 -1.285 -1.560 -1.230 -1.340 -1.292 -1.596 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
1.309 1.428 1.565 1.501 1.775 1.447 1.581 1.519 1.812
1.757 2.000 2.227 2.106 2.131 2.002 2.232 2.111 2.179
ns
ns
tsu
th
GCLK
PLL
-1.356 -1.551 -1.723 -1.634 -1.653 -1.544 -1.719 -1.629 -1.699 ns
-1.123 -1.221 -1.335 -1.285 -1.560 -1.230 -1.340 -1.292 -1.596 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
1.309 1.428 1.565 1.501 1.775 1.447 1.581 1.519 1.812
1.757 2.000 2.227 2.106 2.131 2.002 2.232 2.111 2.179
ns
ns
tsu
th
GCLK
PLL
-1.356 -1.551 -1.723 -1.634 -1.653 -1.544 -1.719 -1.629 -1.699 ns
-1.128 -1.227 -1.336 -1.287 -1.561 -1.231 -1.336 -1.290 -1.593 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
1.314 1.436 1.569 1.505 1.780 1.451 1.580 1.518 1.813
1.742 1.984 2.216 2.094 2.120 1.991 2.226 2.103 2.172
ns
ns
tsu
th
GCLK
PLL
-1.341 -1.533 -1.709 -1.620 -1.638 -1.530 -1.710 -1.620 -1.688 ns
-1.128 -1.227 -1.336 -1.287 -1.561 -1.231 -1.336 -1.290 -1.593 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
1.314 1.436 1.569 1.505 1.780 1.451 1.580 1.518 1.813
1.742 1.984 2.216 2.094 2.120 1.991 2.226 2.103 2.172
ns
ns
tsu
th
GCLK
PLL
-1.341 -1.533 -1.709 -1.620 -1.638 -1.530 -1.710 -1.620 -1.688 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–222
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–109 specifies EP3SE50 Column Pins Output Timing parameters for differential
I/O standards.
Table 1–109. EP3SE50 Column Pins Output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.049
1.335
3.045
1.331
3.049
1.335
3.045
1.331
3.049
1.335
3.045
1.331
3.076
1.362
3.066
1.352
3.066
1.352
3.059
1.345
3.058
1.344
3.080
1.366
3.267
1.514
3.270
1.517
3.267
1.514
3.270
1.517
3.267
1.514
3.270
1.517
3.300
1.547
3.290
1.537
3.290
1.537
3.284
1.531
3.282
1.529
3.304
1.551
4.596 4.998 5.509 5.368 5.597 5.124 5.636 5.496 5.663
1.903 1.989 2.191 2.203 2.139 2.102 2.305 2.320 2.125
4.643 5.053 5.571 5.430 5.659 5.183 5.702 5.562 5.729
1.950 2.044 2.253 2.265 2.201 2.161 2.371 2.386 2.191
4.596 4.998 5.509 5.368 5.597 5.124 5.636 5.496 5.663
—
—
LVDS_E_1R
LVDS_E_3R
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
1.903 1.989 2.191 2.203 2.139 2.102 2.305 2.320 2.125 ns
ns
GCLK
4.643 5.053 5.571 5.430 5.659 5.183 5.702 5.562 5.729
1.950 2.044 2.253 2.265 2.201 2.161 2.371 2.386 2.191 ns
ns
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
4.596 4.998 5.509 5.368 5.597 5.124 5.636 5.496 5.663
1.903 1.989 2.191 2.203 2.139 2.102 2.305 2.320 2.125 ns
ns
—
RSDS_E_1R
RSDS_E_3R
GCLK
PLL
GCLK
4.643 5.053 5.571 5.430 5.659 5.183 5.702 5.562 5.729
1.950 2.044 2.253 2.265 2.201 2.161 2.371 2.386 2.191 ns
ns
—
GCLK
PLL
GCLK
4.667 5.076 5.593 5.452 5.681 5.204 5.722 5.582 5.749
1.974 2.067 2.275 2.287 2.223 2.182 2.391 2.406 2.211 ns
ns
4mA
6mA
8mA
GCLK
PLL
GCLK
4.657 5.065 5.583 5.442 5.671 5.193 5.712 5.572 5.739
1.964 2.056 2.265 2.277 2.213 2.171 2.381 2.396 2.201 ns
ns
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
4.660 5.069 5.587 5.446 5.675 5.198 5.717 5.577 5.744
1.967 2.060 2.269 2.281 2.217 2.176 2.386 2.401 2.206 ns
ns
GCLK
PLL
GCLK
4.653 5.063 5.581 5.440 5.669 5.191 5.711 5.571 5.738
1.960 2.054 2.263 2.275 2.211 2.169 2.380 2.395 2.200 ns
10m
A
GCLK
PLL
GCLK
ns
ns
ns
ns
4.650 5.060 5.578 5.437 5.666 5.188 5.707 5.567 5.734
1.957 2.051 2.260 2.272 2.208 2.166 2.376 2.391 2.196
4.671 5.080 5.597 5.456 5.685 5.208 5.727 5.587 5.754
1.978 2.071 2.279 2.291 2.227 2.186 2.396 2.411 2.216
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
16m
A
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–223
I/O Timing
Table 1–109. EP3SE50 Column Pins Output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.070
1.356
3.065
1.351
3.063
1.349
3.055
1.341
3.056
1.342
3.055
1.341
3.067
1.353
3.063
1.349
3.053
1.339
3.051
1.337
3.051
1.337
3.055
1.341
3.293
1.540
3.289
1.536
3.287
1.534
3.278
1.525
3.280
1.527
3.277
1.524
3.290
1.537
3.287
1.534
3.276
1.523
3.274
1.521
3.275
1.522
3.278
1.525
4.650 5.057 5.572 5.431 5.660 5.184 5.700 5.560 5.727
1.957 2.048 2.254 2.266 2.202 2.162 2.369 2.384 2.189
4.650 5.057 5.573 5.432 5.661 5.185 5.702 5.562 5.729
1.957 2.048 2.255 2.267 2.203 2.163 2.371 2.386 2.191
4.649 5.056 5.571 5.430 5.659 5.184 5.701 5.561 5.728
1.956 2.047 2.253 2.265 2.201 2.162 2.370 2.385 2.190
4.639 5.046 5.562 5.421 5.650 5.174 5.691 5.551 5.718
1.946 2.037 2.244 2.256 2.192 2.152 2.360 2.375 2.180
4.645 5.053 5.570 5.429 5.658 5.182 5.700 5.560 5.727
1.952 2.044 2.252 2.264 2.200 2.160 2.369 2.384 2.189
4.628 5.034 5.548 5.407 5.636 5.161 5.676 5.536 5.703
1.935 2.025 2.230 2.242 2.178 2.139 2.345 2.360 2.165
4.646 5.052 5.566 5.425 5.654 5.180 5.695 5.555 5.722
1.953 2.043 2.248 2.260 2.196 2.158 2.364 2.379 2.184
4.647 5.054 5.570 5.429 5.658 5.182 5.699 5.559 5.726
1.954 2.045 2.252 2.264 2.200 2.160 2.368 2.383 2.188
4.636 5.043 5.558 5.417 5.646 5.171 5.687 5.547 5.714
1.943 2.034 2.240 2.252 2.188 2.149 2.356 2.371 2.176
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
4.634 5.040 5.556 5.415 5.644 5.169 5.685 5.545 5.712 ns
ns
10m
A
GCLK
PLL
1.941 2.031 2.238 2.250 2.186 2.147 2.354 2.369 2.174
4.637 5.045 5.561 5.420 5.649 5.173 5.691 5.551 5.718 ns
ns
GCLK
12m
A
GCLK
PLL
1.944 2.036 2.243 2.255 2.191 2.151 2.360 2.375 2.180
4.634 5.040 5.555 5.414 5.643 5.168 5.684 5.544 5.711 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
16m
A
GCLK
PLL
ns
1.941 2.031 2.237 2.249 2.185 2.146 2.353 2.368 2.173
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–224
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–109. EP3SE50 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.081
1.367
3.067
1.353
3.055
1.341
3.055
1.341
3.051
1.337
3.055
1.341
3.056
1.342
3.084
1.370
3.073
1.359
3.068
1.354
3.054
1.340
3.052
1.338
3.056
1.342
3.056
1.342
3.307
1.554
3.293
1.540
3.280
1.527
3.280
1.527
3.276
1.523
3.278
1.525
3.280
1.527
3.310
1.557
3.298
1.545
3.294
1.541
3.279
1.526
3.277
1.524
3.279
1.526
3.280
1.527
4.679 5.088 5.605 5.464 5.693 5.216 5.734 5.594 5.761
1.986 2.079 2.287 2.299 2.235 2.194 2.403 2.418 2.223
4.667 5.077 5.595 5.454 5.683 5.206 5.725 5.585 5.752
1.974 2.068 2.277 2.289 2.225 2.184 2.394 2.409 2.214
4.650 5.059 5.577 5.436 5.665 5.188 5.707 5.567 5.734
1.957 2.050 2.259 2.271 2.207 2.166 2.376 2.391 2.196
4.653 5.063 5.581 5.440 5.669 5.192 5.712 5.572 5.739
1.960 2.054 2.263 2.275 2.211 2.170 2.381 2.396 2.201
4.646 5.055 5.574 5.433 5.662 5.185 5.704 5.564 5.731
1.953 2.046 2.256 2.268 2.204 2.163 2.373 2.388 2.193
4.639 5.046 5.562 5.421 5.650 5.174 5.691 5.551 5.718
1.946 2.037 2.244 2.256 2.192 2.152 2.360 2.375 2.180
4.647 5.056 5.573 5.432 5.661 5.184 5.703 5.563 5.730
1.954 2.047 2.255 2.267 2.203 2.162 2.372 2.387 2.192
4.678 5.086 5.603 5.462 5.691 5.215 5.732 5.592 5.759
1.985 2.077 2.285 2.297 2.233 2.193 2.401 2.416 2.221
4.666 5.074 5.591 5.450 5.679 5.203 5.720 5.580 5.747
1.973 2.065 2.273 2.285 2.221 2.181 2.389 2.404 2.209
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
8mA
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
4.666 5.075 5.592 5.451 5.680 5.204 5.722 5.582 5.749 ns
ns
GCLK
PLL
1.973 2.066 2.274 2.286 2.222 2.182 2.391 2.406 2.211
4.648 5.056 5.573 5.432 5.661 5.185 5.704 5.564 5.731 ns
ns
GCLK
10m
A
GCLK
PLL
1.955 2.047 2.255 2.267 2.203 2.163 2.373 2.388 2.193
4.646 5.054 5.571 5.430 5.659 5.183 5.701 5.561 5.728 ns
ns
GCLK
12m
A
GCLK
PLL
1.953 2.045 2.253 2.265 2.201 2.161 2.370 2.385 2.190
4.638 5.044 5.559 5.418 5.647 5.172 5.688 5.548 5.715 ns
ns
GCLK
8mA
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
1.945 2.035 2.241 2.253 2.189 2.150 2.357 2.372 2.177
4.646 5.054 5.571 5.430 5.659 5.183 5.701 5.561 5.728 ns
GCLK
16m
A
GCLK
PLL
ns
1.953 2.045 2.253 2.265 2.201 2.161 2.370 2.385 2.190
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–225
I/O Timing
Table 1–109. EP3SE50 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.072
1.358
3.072
1.358
3.062
1.348
3.055
1.341
3.297
1.544
3.297
1.544
3.287
1.534
3.279
1.526
4.662 5.069 5.585 5.444 5.673 5.198 5.714 5.574 5.741
1.969 2.060 2.267 2.279 2.215 2.176 2.383 2.398 2.203
4.662 5.069 5.585 5.444 5.673 5.198 5.714 5.574 5.741
1.969 2.060 2.267 2.279 2.215 2.176 2.383 2.398 2.203
4.652 5.059 5.575 5.434 5.663 5.188 5.705 5.565 5.732
1.959 2.050 2.257 2.269 2.205 2.166 2.374 2.389 2.194
4.638 5.044 5.559 5.418 5.647 5.172 5.688 5.548 5.715
1.945 2.035 2.241 2.253 2.189 2.150 2.357 2.372 2.177
8mA
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
16m
A
GCLK
PLL
Table 1–110 specifies EP3SE50 Row Pins Output Timing parameters for differential
I/O standards.
Table 1–110. EP3SE50 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
2.671
1.003
3.049
1.381
3.031
1.363
2.671
1.003
3.049
1.381
3.031
1.363
2.671
1.003
2.845
1.137
3.275
1.567
3.265
1.557
2.845
1.137
3.275
1.567
3.265
1.557
2.845
1.137
3.986 4.355 4.833 4.698 4.909 4.463 4.943 4.807 4.960
1.339 1.394 1.563 1.582 1.501 1.491 1.661 1.679 1.470
4.633 5.042 5.560 5.418 5.621 5.174 5.696 5.551 5.688
1.986 2.081 2.290 2.302 2.213 2.202 2.414 2.423 2.198
4.671 5.088 5.614 5.472 5.675 5.225 5.757 5.612 5.749
2.024 2.127 2.344 2.356 2.267 2.253 2.475 2.484 2.259
3.986 4.355 4.833 4.698 4.909 4.463 4.943 4.807 4.960
1.339 1.394 1.563 1.582 1.501 1.491 1.661 1.679 1.470
4.633 5.042 5.560 5.418 5.621 5.174 5.696 5.551 5.688
1.986 2.081 2.290 2.302 2.213 2.202 2.414 2.423 2.198
4.671 5.088 5.614 5.472 5.675 5.225 5.757 5.612 5.749
2.024 2.127 2.344 2.356 2.267 2.253 2.475 2.484 2.259
3.986 4.355 4.833 4.698 4.909 4.463 4.943 4.807 4.960
1.339 1.394 1.563 1.582 1.501 1.491 1.661 1.679 1.470
LVDS
—
—
—
—
—
—
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
GCLK
tco
PLL
GCLK tco
RSDS
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–226
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–110. EP3SE50 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
RSDS_E_1R
RSDS_E_3R
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.049
1.381
3.031
1.363
3.085
1.407
3.071
1.393
3.067
1.389
3.083
1.405
3.072
1.394
3.069
1.391
3.080
1.402
3.070
1.392
3.056
1.378
3.053
1.375
3.050
1.372
3.275
1.567
3.265
1.557
3.318
1.600
3.304
1.586
3.300
1.582
3.315
1.597
3.305
1.587
3.302
1.584
3.312
1.594
3.303
1.585
3.289
1.571
3.285
1.567
3.283
1.565
4.633 5.042 5.560 5.418 5.621 5.174 5.696 5.551 5.688
1.986 2.081 2.290 2.302 2.213 2.202 2.414 2.423 2.198
4.671 5.088 5.614 5.472 5.675 5.225 5.757 5.612 5.749
2.024 2.127 2.344 2.356 2.267 2.253 2.475 2.484 2.259
4.717 5.132 5.657 5.515 5.718 5.268 5.796 5.651 5.788
2.060 2.161 2.377 2.389 2.300 2.286 2.504 2.513 2.288
4.704 5.119 5.644 5.502 5.705 5.254 5.783 5.638 5.775
2.047 2.148 2.364 2.376 2.287 2.272 2.491 2.500 2.275
4.702 5.119 5.645 5.503 5.706 5.254 5.785 5.640 5.777
2.045 2.148 2.365 2.377 2.288 2.272 2.493 2.502 2.277
4.703 5.116 5.639 5.497 5.700 5.251 5.778 5.633 5.770
2.046 2.145 2.359 2.371 2.282 2.269 2.486 2.495 2.270
4.699 5.112 5.636 5.494 5.697 5.248 5.775 5.630 5.767
2.042 2.141 2.356 2.368 2.279 2.266 2.483 2.492 2.267
4.697 5.110 5.634 5.492 5.695 5.246 5.774 5.629 5.766
2.040 2.139 2.354 2.366 2.277 2.264 2.482 2.491 2.266
4.698 5.111 5.633 5.491 5.694 5.245 5.772 5.627 5.764
2.041 2.140 2.353 2.365 2.276 2.263 2.480 2.489 2.264
4.696 5.109 5.632 5.490 5.693 5.245 5.772 5.627 5.764
2.039 2.138 2.352 2.364 2.275 2.263 2.480 2.489 2.264
4.681 5.094 5.618 5.476 5.679 5.230 5.757 5.612 5.749
2.024 2.123 2.338 2.350 2.261 2.248 2.465 2.474 2.249
4.677 5.090 5.614 5.472 5.675 5.226 5.753 5.608 5.745
2.020 2.119 2.334 2.346 2.257 2.244 2.461 2.470 2.245
4.678 5.093 5.617 5.475 5.678 5.229 5.757 5.612 5.749
2.021 2.122 2.337 2.349 2.260 2.247 2.465 2.474 2.249
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
4mA
6mA
8mA
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–227
I/O Timing
Table 1–110. EP3SE50 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.051
1.373
3.100
1.422
3.076
1.398
3.058
1.380
3.104
1.426
3.089
1.411
3.078
1.400
3.058
1.380
3.055
1.377
3.060
1.382
3.053
1.375
3.081
1.413
3.063
1.395
3.283
1.565
3.336
1.618
3.312
1.594
3.293
1.575
3.339
1.621
3.324
1.606
3.313
1.595
3.293
1.575
3.289
1.571
3.293
1.575
3.286
1.568
3.315
1.607
3.298
1.590
4.668 5.081 5.604 5.462 5.665 5.216 5.743 5.598 5.735
2.011 2.110 2.324 2.336 2.247 2.234 2.451 2.460 2.235
4.739 5.154 5.680 5.538 5.741 5.290 5.819 5.674 5.811
2.082 2.183 2.400 2.412 2.323 2.308 2.527 2.536 2.311
4.721 5.137 5.663 5.521 5.724 5.273 5.804 5.659 5.796
2.064 2.166 2.383 2.395 2.306 2.291 2.512 2.521 2.296
4.699 5.115 5.641 5.499 5.702 5.251 5.782 5.637 5.774
2.042 2.144 2.361 2.373 2.284 2.269 2.490 2.499 2.274
4.739 5.154 5.679 5.537 5.740 5.290 5.819 5.674 5.811
2.082 2.183 2.399 2.411 2.322 2.308 2.527 2.536 2.311
4.725 5.139 5.664 5.522 5.725 5.275 5.804 5.659 5.796
2.068 2.168 2.384 2.396 2.307 2.293 2.512 2.521 2.296
4.720 5.136 5.661 5.519 5.722 5.272 5.802 5.657 5.794
2.063 2.165 2.381 2.393 2.304 2.290 2.510 2.519 2.294
4.697 5.112 5.638 5.496 5.699 5.249 5.778 5.633 5.770
2.040 2.141 2.358 2.370 2.281 2.267 2.486 2.495 2.270
4.693 5.109 5.634 5.492 5.695 5.245 5.775 5.630 5.767
2.036 2.138 2.354 2.366 2.277 2.263 2.483 2.492 2.267
4.684 5.097 5.620 5.478 5.681 5.232 5.759 5.614 5.751
2.027 2.126 2.340 2.352 2.263 2.250 2.467 2.476 2.251
4.683 5.098 5.623 5.481 5.684 5.235 5.764 5.619 5.756
2.026 2.127 2.343 2.355 2.266 2.253 2.472 2.481 2.256
4.711 5.125 5.649 5.507 5.710 5.261 5.789 5.644 5.781
2.064 2.164 2.379 2.391 2.302 2.289 2.507 2.516 2.291
4.696 5.110 5.634 5.492 5.695 5.246 5.774 5.629 5.766
2.049 2.149 2.364 2.376 2.287 2.274 2.492 2.501 2.276
DIFFERENTIAL
1.8-V
HSTL CLASS II
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
PLL
GCLK tco
16mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
2.5-V SSTL
CLASS I
PLL
GCLK tco
12mA
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–228
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–110. EP3SE50 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
GCLK tco
3.049
1.381
3.282
1.574
4.673 5.086 5.609 5.467 5.670 5.222 5.749 5.604 5.741
2.026 2.125 2.339 2.351 2.262 2.250 2.467 2.476 2.251
DIFFERENTIAL
2.5-V
SSTL CLASS II
16mA
GCLK
tco
PLL
Table 1–111 and Table 1–112 show EP3SE50 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
Table 1–111 specifies EP3SE50 Column Pin delay adders when using the regional
clock in Stratix III devices.
Table 1–111. EP3SE50 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL=
0.9V
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
RCLK input adder
0.152
-0.001
-0.116
0.164
-0.001
-0.119
0.22
0.237
0.25
0.244
0.31
0.24
0.254
0.246
0.312
ns
ns
ns
RCLK PLL input adder
RCLK output adder
-0.003 -0.004 -0.004 -0.004 -0.006 -0.003 -0.004 -0.004 -0.006
-0.134 -0.136 -0.17 -0.171 -0.249 -0.131 -0.13 -0.13 -0.216
2.61 2.926 3.238 3.084 3.298 2.943 3.254 3.098 3.374
RCLK PLL output
adder
1.647
1.684
ns
Table 1–112 specifies EP3SE50 Row Pin delay adders when using the regional clock in
Stratix III devices.
Table 1–112. EP3SE50 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.113
0.13
0.125
0.14
0.182 0.197 0.212 0.205 0.274 0.201 0.215 0.21 0.275
0.213 0.241 0.267 0.255 0.385 0.244 0.27 0.256 0.386
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
-0.116
-0.137
-0.129
-0.143
-0.186 -0.202 -0.218 -0.209 -0.28 -0.206 -0.221 -0.214 -0.283 ns
-0.193 -0.214 -0.236 -0.225 -0.295 -0.215 -0.237 -0.226 -0.297 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–229
I/O Timing
EP3SE80 I/O Timing Parameters
Table 1–113 through Table 1–116 show the maximum I/O timing parameters for
EP3SE80 devices for single-ended I/O standards.
Table 1–113 specifies EP3SE80 column pins input timing parameters for single-ended
I/O standards.
Table 1–113. EP3SE80 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.122
1.249
0.716
-0.451
-1.122
1.249
0.716
-0.451
-1.128
1.255
0.710
-0.445
-1.128
1.255
0.710
-0.445
-1.118
1.245
0.720
-0.455
-1.136
1.265
0.702
-0.435
-1.129
1.258
0.709
-0.442
-1.069
1.198
0.769
-0.502
-1.177
1.323
0.735
-0.450
-1.177
1.323
0.735
-0.450
-1.188
1.334
0.724
-0.439
-1.188
1.334
0.724
-0.439
-1.183
1.329
0.729
-0.444
-1.205
1.353
0.707
-0.420
-1.195
1.343
0.717
-0.430
-1.143
1.291
0.769
-0.482
-1.686 -1.840 -2.102 -2.031 -2.409 -1.864 -2.110 -2.042 -2.443 ns
GCLK
1.893 2.074 2.356 2.268 2.655 2.108 2.374 2.291 2.689
1.226 1.399 1.461 1.368 1.385 1.396 1.473 1.377 1.441
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-0.803 -0.925 -0.933 -0.872 -0.872 -0.912 -0.935 -0.871 -0.925 ns
-1.686 -1.840 -2.102 -2.031 -2.409 -1.864 -2.110 -2.042 -2.443 ns
tsu
th
GCLK
1.893 2.074 2.356 2.268 2.655 2.108 2.374 2.291 2.689
1.226 1.399 1.461 1.368 1.385 1.396 1.473 1.377 1.441
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-0.803 -0.925 -0.933 -0.872 -0.872 -0.912 -0.935 -0.871 -0.925 ns
-1.685 -1.842 -2.101 -2.030 -2.408 -1.864 -2.115 -2.047 -2.448 ns
tsu
th
GCLK
1.892 2.076 2.355 2.267 2.654 2.108 2.379 2.296 2.694
1.227 1.397 1.462 1.369 1.386 1.396 1.468 1.372 1.436
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-0.804 -0.923 -0.934 -0.873 -0.873 -0.912 -0.930 -0.866 -0.920 ns
-1.685 -1.842 -2.101 -2.030 -2.408 -1.864 -2.115 -2.047 -2.448 ns
tsu
th
GCLK
1.892 2.076 2.355 2.267 2.654 2.108 2.379 2.296 2.694
1.227 1.397 1.462 1.369 1.386 1.396 1.468 1.372 1.436
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-0.804 -0.923 -0.934 -0.873 -0.873 -0.912 -0.930 -0.866 -0.920 ns
-1.694 -1.854 -2.120 -2.049 -2.427 -1.874 -2.126 -2.058 -2.459 ns
tsu
th
GCLK
1.901 2.088 2.374 2.286 2.673 2.118 2.390 2.307 2.705
1.218 1.385 1.443 1.350 1.367 1.386 1.457 1.361 1.425
ns
ns
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
-0.795 -0.911 -0.915 -0.854 -0.854 -0.902 -0.919 -0.855 -0.909 ns
-1.734 -1.890 -2.118 -2.047 -2.425 -1.908 -2.129 -2.061 -2.462 ns
tsu
th
GCLK
1.941 2.124 2.372 2.284 2.671 2.152 2.393 2.310 2.708
1.178 1.349 1.445 1.352 1.369 1.352 1.454 1.358 1.422
ns
ns
tsu
th
GCLK
PLL
-0.755 -0.875 -0.917 -0.856 -0.856 -0.868 -0.916 -0.852 -0.906 ns
-1.711 -1.858 -2.048 -1.977 -2.355 -1.877 -2.063 -1.995 -2.396 ns
tsu
th
GCLK
1.918 2.092 2.302 2.214 2.601 2.121 2.327 2.244 2.642
1.201 1.381 1.515 1.422 1.439 1.383 1.520 1.424 1.488
ns
ns
tsu
th
GCLK
PLL
-0.778 -0.907 -0.987 -0.926 -0.926 -0.899 -0.982 -0.918 -0.972 ns
-1.634 -1.759 -1.892 -1.821 -2.199 -1.781 -1.910 -1.842 -2.243 ns
tsu
th
GCLK
1.841 1.993 2.146 2.058 2.445 2.025 2.174 2.091 2.489
1.278 1.480 1.671 1.578 1.595 1.479 1.673 1.577 1.641
ns
ns
tsu
th
GCLK
PLL
-0.855 -1.006 -1.143 -1.082 -1.082 -0.995 -1.135 -1.071 -1.125 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–230
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–113. EP3SE80 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.050
1.179
0.788
-0.521
-1.050
1.179
0.788
-0.521
-1.043
1.172
0.795
-0.528
-1.043
1.172
0.795
-0.528
-1.031
1.160
0.807
-0.540
-1.031
1.160
0.807
-0.540
-1.043
1.172
0.795
-0.528
-1.043
1.172
0.795
-0.528
-1.031
1.160
0.807
-0.540
-1.114
1.262
0.798
-0.511
-1.114
1.262
0.798
-0.511
-1.108
1.256
0.804
-0.517
-1.108
1.256
0.804
-0.517
-1.097
1.245
0.815
-0.528
-1.097
1.245
0.815
-0.528
-1.108
1.256
0.804
-0.517
-1.108
1.256
0.804
-0.517
-1.097
1.245
0.815
-0.528
-1.606 -1.743 -1.894 -1.823 -2.201 -1.760 -1.906 -1.838 -2.239 ns
GCLK
1.813 1.977 2.148 2.060 2.447 2.004 2.170 2.087 2.485
1.306 1.496 1.669 1.576 1.593 1.500 1.677 1.581 1.645
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-0.883 -1.022 -1.141 -1.080 -1.080 -1.016 -1.139 -1.075 -1.129 ns
-1.606 -1.743 -1.894 -1.823 -2.201 -1.760 -1.906 -1.838 -2.239 ns
tsu
th
GCLK
1.813 1.977 2.148 2.060 2.447 2.004 2.170 2.087 2.485
1.306 1.496 1.669 1.576 1.593 1.500 1.677 1.581 1.645
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-0.883 -1.022 -1.141 -1.080 -1.080 -1.016 -1.139 -1.075 -1.129 ns
-1.593 -1.735 -1.891 -1.818 -2.199 -1.753 -1.907 -1.837 -2.240 ns
tsu
th
GCLK
1.800 1.966 2.142 2.054 2.440 1.994 2.167 2.085 2.481
1.319 1.504 1.672 1.581 1.595 1.507 1.676 1.582 1.644
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-0.896 -1.033 -1.147 -1.086 -1.087 -1.026 -1.142 -1.077 -1.133 ns
-1.593 -1.735 -1.891 -1.818 -2.199 -1.753 -1.907 -1.837 -2.240 ns
tsu
th
GCLK
1.800 1.966 2.142 2.054 2.440 1.994 2.167 2.085 2.481
1.319 1.504 1.672 1.581 1.595 1.507 1.676 1.582 1.644
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-0.896 -1.033 -1.147 -1.086 -1.087 -1.026 -1.142 -1.077 -1.133 ns
-1.582 -1.724 -1.872 -1.799 -2.180 -1.742 -1.889 -1.819 -2.222 ns
tsu
th
GCLK
1.788 1.955 2.123 2.035 2.421 1.983 2.149 2.067 2.463
1.330 1.515 1.691 1.600 1.614 1.518 1.694 1.600 1.662
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-0.908 -1.044 -1.166 -1.105 -1.106 -1.037 -1.160 -1.095 -1.151 ns
-1.582 -1.724 -1.872 -1.799 -2.180 -1.742 -1.889 -1.819 -2.222 ns
tsu
th
GCLK
1.788 1.955 2.123 2.035 2.421 1.983 2.149 2.067 2.463
1.330 1.515 1.691 1.600 1.614 1.518 1.694 1.600 1.662
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.908 -1.044 -1.166 -1.105 -1.106 -1.037 -1.160 -1.095 -1.151 ns
-1.593 -1.735 -1.891 -1.818 -2.199 -1.753 -1.907 -1.837 -2.240 ns
tsu
th
GCLK
1.800 1.966 2.142 2.054 2.440 1.994 2.167 2.085 2.481
1.319 1.504 1.672 1.581 1.595 1.507 1.676 1.582 1.644
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.896 -1.033 -1.147 -1.086 -1.087 -1.026 -1.142 -1.077 -1.133 ns
-1.593 -1.735 -1.891 -1.818 -2.199 -1.753 -1.907 -1.837 -2.240 ns
tsu
th
GCLK
1.800 1.966 2.142 2.054 2.440 1.994 2.167 2.085 2.481
1.319 1.504 1.672 1.581 1.595 1.507 1.676 1.582 1.644
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.896 -1.033 -1.147 -1.086 -1.087 -1.026 -1.142 -1.077 -1.133 ns
-1.582 -1.724 -1.872 -1.799 -2.180 -1.742 -1.889 -1.819 -2.222 ns
tsu
th
GCLK
1.788 1.955 2.123 2.035 2.421 1.983 2.149 2.067 2.463
1.330 1.515 1.691 1.600 1.614 1.518 1.694 1.600 1.662
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.908 -1.044 -1.166 -1.105 -1.106 -1.037 -1.160 -1.095 -1.151 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–231
I/O Timing
Table 1–113. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.031
1.160
0.807
-0.540
-1.023
1.152
0.815
-0.548
-1.023
1.152
0.815
-0.548
-1.128
1.255
0.710
-0.445
-1.097
1.245
0.815
-0.528
-1.085
1.233
0.827
-0.540
-1.085
1.233
0.827
-0.540
-1.188
1.334
0.724
-0.439
-1.582 -1.724 -1.872 -1.799 -2.180 -1.742 -1.889 -1.819 -2.222 ns
GCLK
1.788 1.955 2.123 2.035 2.421 1.983 2.149 2.067 2.463
1.330 1.515 1.691 1.600 1.614 1.518 1.694 1.600 1.662
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.908 -1.044 -1.166 -1.105 -1.106 -1.037 -1.160 -1.095 -1.151 ns
-1.572 -1.713 -1.856 -1.783 -2.164 -1.731 -1.874 -1.804 -2.207 ns
tsu
th
GCLK
1.778 1.944 2.107 2.019 2.405 1.972 2.134 2.052 2.448
1.340 1.526 1.707 1.616 1.630 1.529 1.709 1.615 1.677
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.918 -1.055 -1.182 -1.121 -1.122 -1.048 -1.175 -1.110 -1.166 ns
-1.572 -1.713 -1.856 -1.783 -2.164 -1.731 -1.874 -1.804 -2.207 ns
tsu
th
GCLK
1.778 1.944 2.107 2.019 2.405 1.972 2.134 2.052 2.448
1.340 1.526 1.707 1.616 1.630 1.529 1.709 1.615 1.677
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-0.918 -1.055 -1.182 -1.121 -1.122 -1.048 -1.175 -1.110 -1.166 ns
-1.685 -1.842 -2.101 -2.030 -2.408 -1.864 -2.115 -2.047 -2.448 ns
tsu
th
GCLK
1.892 2.076 2.355 2.267 2.654 2.108 2.379 2.296 2.694
1.227 1.397 1.462 1.369 1.386 1.396 1.468 1.372 1.436
ns
ns
3.0-V PCI-X
tsu
th
GCLK
PLL
-0.804 -0.923 -0.934 -0.873 -0.873 -0.912 -0.930 -0.866 -0.920 ns
Table 1–114 specifies EP3SE80 row pins input timing parameters for single-ended
I/O standards.
Table 1–114. EP3SE80 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.922
1.045
1.087
-0.825
-0.922
1.045
1.087
-0.825
-0.928
1.051
1.081
-0.819
-0.964
1.103
1.110
-0.830
-0.964
1.103
1.110
-0.830
-0.975
1.114
1.099
-0.819
-1.369 -1.481 -1.595 -1.647 -1.890 -1.492 -1.697 -1.649 -1.929
1.566 1.703 1.842 1.878 2.128 1.725 1.950 1.890 2.168
1.770 2.000 1.985 2.004 1.799 2.012 2.003 2.024 1.850
-1.353 -1.532 -1.470 -1.513 -1.300 -1.533 -1.477 -1.523 -1.349
-1.369 -1.481 -1.595 -1.647 -1.890 -1.492 -1.697 -1.649 -1.929
1.566 1.703 1.842 1.878 2.128 1.725 1.950 1.890 2.168
1.770 2.000 1.985 2.004 1.799 2.012 2.003 2.024 1.850
-1.353 -1.532 -1.470 -1.513 -1.300 -1.533 -1.477 -1.523 -1.349
-1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934
1.563 1.704 1.845 1.881 2.131 1.724 1.955 1.895 2.173
1.773 1.999 1.982 2.001 1.796 2.013 1.998 2.019 1.845
-1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344
GCLK
3.3-V LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V LVTTL
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–232
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–114. EP3SE80 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.928
1.051
1.081
-0.819
-0.916
1.039
1.093
-0.831
-0.973
1.097
0.974
-0.714
-0.963
1.087
0.984
-0.724
-0.903
1.027
1.044
-0.784
-0.859
0.983
1.151
-0.888
-0.859
0.983
1.151
-0.888
-0.877
1.001
1.070
-0.810
-0.877
1.001
1.070
-0.810
-0.975
1.114
1.099
-0.819
-0.968
1.107
1.106
-0.826
-1.027
1.167
0.984
-0.705
-1.016
1.156
0.995
-0.716
-0.963
1.103
1.048
-0.769
-0.910
1.050
1.165
-0.884
-0.910
1.050
1.165
-0.884
-0.928
1.068
1.083
-0.804
-0.928
1.068
1.083
-0.804
-1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934
1.563 1.704 1.845 1.881 2.131 1.724 1.955 1.895 2.173
1.773 1.999 1.982 2.001 1.796 2.013 1.998 2.019 1.845
-1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344
-1.375 -1.495 -1.613 -1.665 -1.908 -1.500 -1.712 -1.664 -1.944
1.572 1.717 1.860 1.896 2.146 1.733 1.965 1.905 2.183
1.764 1.986 1.967 1.986 1.781 2.004 1.988 2.009 1.835
-1.347 -1.518 -1.452 -1.495 -1.282 -1.525 -1.462 -1.508 -1.334
-1.441 -1.555 -1.741 -1.689 -1.906 -1.560 -1.739 -1.691 -1.945
1.638 1.777 1.984 1.920 2.144 1.792 1.992 1.931 2.184
1.606 1.824 1.969 1.854 1.783 1.837 1.987 1.870 1.834
-1.192 -1.359 -1.454 -1.366 -1.284 -1.362 -1.461 -1.373 -1.333
-1.417 -1.523 -1.673 -1.621 -1.838 -1.529 -1.674 -1.626 -1.880
1.614 1.745 1.916 1.852 2.076 1.761 1.927 1.866 2.119
1.630 1.856 2.037 1.922 1.851 1.868 2.052 1.935 1.899
-1.216 -1.391 -1.522 -1.434 -1.352 -1.393 -1.526 -1.438 -1.398
-1.338 -1.422 -1.514 -1.462 -1.679 -1.433 -1.519 -1.471 -1.725
1.535 1.644 1.757 1.693 1.917 1.665 1.772 1.711 1.964
1.709 1.957 2.196 2.081 2.010 1.964 2.207 2.090 2.054
-1.295 -1.492 -1.681 -1.593 -1.511 -1.489 -1.681 -1.593 -1.553
-1.289 -1.386 -1.393 -1.445 -1.688 -1.388 -1.495 -1.447 -1.727
1.486 1.608 1.640 1.676 1.926 1.621 1.748 1.688 1.966
1.850 2.095 2.187 2.206 2.001 2.116 2.205 2.226 2.052
-1.433 -1.627 -1.672 -1.715 -1.502 -1.637 -1.679 -1.725 -1.551
-1.289 -1.386 -1.393 -1.445 -1.688 -1.388 -1.495 -1.447 -1.727
1.486 1.608 1.640 1.676 1.926 1.621 1.748 1.688 1.966
1.850 2.095 2.187 2.206 2.001 2.116 2.205 2.226 2.052
-1.433 -1.627 -1.672 -1.715 -1.502 -1.637 -1.679 -1.725 -1.551
-1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720
1.497 1.615 1.750 1.686 1.911 1.631 1.762 1.702 1.955
1.747 1.984 2.201 2.087 2.014 1.996 2.214 2.098 2.061
-1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564
-1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720
1.497 1.615 1.750 1.686 1.911 1.631 1.762 1.702 1.955
1.747 1.984 2.201 2.087 2.014 1.996 2.214 2.098 2.061
-1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
2.5 V
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–233
I/O Timing
Table 1–114. EP3SE80 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.863
0.987
1.084
-0.824
-0.877
1.001
1.070
-0.810
-0.877
1.001
1.070
-0.810
-0.863
0.987
1.084
-0.824
-0.863
0.987
1.084
-0.824
-0.854
0.978
1.093
-0.833
-0.854
0.978
1.093
-0.833
-0.928
1.051
1.081
-0.819
-0.928
1.051
1.081
-0.819
-0.916
1.056
1.095
-0.816
-0.928
1.068
1.083
-0.804
-0.928
1.068
1.083
-0.804
-0.916
1.056
1.095
-0.816
-0.916
1.056
1.095
-0.816
-0.904
1.044
1.107
-0.828
-0.904
1.044
1.107
-0.828
-0.975
1.114
1.099
-0.819
-0.975
1.114
1.099
-0.819
-1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703
1.483 1.605 1.732 1.668 1.893 1.620 1.745 1.685 1.938
1.762 1.994 2.219 2.105 2.032 2.007 2.231 2.115 2.078
-1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581
-1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720
1.497 1.615 1.750 1.686 1.911 1.631 1.762 1.702 1.955
1.747 1.984 2.201 2.087 2.014 1.996 2.214 2.098 2.061
-1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564
-1.300 -1.395 -1.509 -1.456 -1.677 -1.401 -1.512 -1.463 -1.720
1.497 1.615 1.750 1.686 1.911 1.631 1.762 1.702 1.955
1.747 1.984 2.201 2.087 2.014 1.996 2.214 2.098 2.061
-1.333 -1.521 -1.688 -1.600 -1.519 -1.523 -1.691 -1.602 -1.564
-1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703
1.483 1.605 1.732 1.668 1.893 1.620 1.745 1.685 1.938
1.762 1.994 2.219 2.105 2.032 2.007 2.231 2.115 2.078
-1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581
-1.285 -1.385 -1.491 -1.438 -1.659 -1.390 -1.495 -1.446 -1.703
1.483 1.605 1.732 1.668 1.893 1.620 1.745 1.685 1.938
1.762 1.994 2.219 2.105 2.032 2.007 2.231 2.115 2.078
-1.347 -1.531 -1.706 -1.618 -1.537 -1.534 -1.708 -1.619 -1.581
-1.276 -1.375 -1.475 -1.422 -1.643 -1.381 -1.479 -1.430 -1.687
1.474 1.595 1.716 1.652 1.877 1.611 1.729 1.669 1.922
1.771 2.004 2.235 2.121 2.048 2.016 2.247 2.131 2.094
-1.356 -1.541 -1.722 -1.634 -1.553 -1.543 -1.724 -1.635 -1.597
-1.276 -1.375 -1.475 -1.422 -1.643 -1.381 -1.479 -1.430 -1.687
1.474 1.595 1.716 1.652 1.877 1.611 1.729 1.669 1.922
1.771 2.004 2.235 2.121 2.048 2.016 2.247 2.131 2.094
-1.356 -1.541 -1.722 -1.634 -1.553 -1.543 -1.724 -1.635 -1.597
-1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934
1.563 1.704 1.845 1.881 2.131 1.724 1.955 1.895 2.173
1.773 1.999 1.982 2.001 1.796 2.013 1.998 2.019 1.845
-1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344
-1.366 -1.482 -1.598 -1.650 -1.893 -1.491 -1.702 -1.654 -1.934
1.563 1.704 1.845 1.881 2.131 1.724 1.955 1.895 2.173
1.773 1.999 1.982 2.001 1.796 2.013 1.998 2.019 1.845
-1.356 -1.531 -1.467 -1.510 -1.297 -1.534 -1.472 -1.518 -1.344
GCLK
SSTL-15
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
PCI-X
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–234
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–115 specifies EP3SE80 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–115. EP3SE80 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.617
1.758
3.494
1.669
3.459
1.637
3.445
1.623
3.526
1.691
3.436
1.614
3.408
1.586
3.401
1.579
3.628
1.767
3.506
1.682
3.467
1.645
3.440
1.618
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.333
1.573
3.243
1.494
3.213
1.465
3.199
1.451
3.275
1.511
3.188
1.440
3.164
1.415
3.157
1.408
3.338
1.571
3.252
1.504
3.214
1.466
3.192
1.444
5.038 5.451 5.972 5.826 6.157 5.587 6.111 5.967 6.240
2.222 2.334 2.556 2.558 2.503 2.446 2.669 2.671 2.493
4.871 5.284 5.804 5.658 5.989 5.418 5.938 5.794 6.067
2.119 2.222 2.439 2.441 2.386 2.330 2.549 2.551 2.373
4.797 5.199 5.704 5.558 5.889 5.328 5.835 5.691 5.965
2.052 2.152 2.369 2.371 2.316 2.260 2.482 2.484 2.306
4.776 5.176 5.675 5.527 5.859 5.302 5.801 5.657 5.931
2.031 2.129 2.341 2.343 2.288 2.234 2.449 2.451 2.273
4.929 5.334 5.850 5.704 6.035 5.466 5.986 5.842 6.115
2.149 2.251 2.468 2.470 2.415 2.360 2.581 2.583 2.405
4.773 5.172 5.671 5.523 5.855 5.298 5.797 5.653 5.927
2.027 2.125 2.337 2.339 2.284 2.230 2.444 2.446 2.268
4.744 5.145 5.646 5.498 5.830 5.271 5.772 5.628 5.902
1.998 2.098 2.312 2.314 2.259 2.203 2.419 2.421 2.243
4.736 5.136 5.637 5.489 5.821 5.261 5.762 5.618 5.892
1.990 2.089 2.303 2.305 2.250 2.194 2.410 2.412 2.234
5.079 5.494 6.032 5.886 6.217 5.630 6.160 6.016 6.289
2.256 2.370 2.595 2.597 2.542 2.485 2.711 2.713 2.535
4.911 5.326 5.879 5.733 6.064 5.463 5.987 5.843 6.116
2.152 2.259 2.479 2.481 2.426 2.370 2.593 2.595 2.417
4.830 5.234 5.777 5.631 5.962 5.364 5.874 5.730 6.003
2.084 2.187 2.405 2.407 2.352 2.296 2.517 2.519 2.341
4.795 5.195 5.727 5.581 5.912 5.324 5.826 5.682 5.956
2.049 2.148 2.363 2.365 2.310 2.256 2.473 2.475 2.297
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVTTL
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVTTL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–235
I/O Timing
Table 1–115. EP3SE80 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.544
1.707
3.450
1.628
3.421
1.599
3.421
1.599
3.691
1.822
3.566
1.729
3.507
1.685
3.461
1.639
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.286
1.525
3.201
1.453
3.177
1.429
3.177
1.429
3.405
1.629
3.298
1.546
3.239
1.491
3.206
1.457
4.969 5.379 5.933 5.787 6.118 5.514 6.040 5.896 6.169
2.186 2.292 2.514 2.516 2.461 2.404 2.629 2.631 2.453
4.808 5.210 5.751 5.605 5.936 5.339 5.842 5.698 5.972
2.063 2.163 2.379 2.381 2.326 2.271 2.490 2.492 2.314
4.769 5.170 5.680 5.534 5.865 5.299 5.801 5.657 5.931
2.023 2.124 2.338 2.340 2.285 2.231 2.448 2.450 2.272
4.761 5.161 5.681 5.535 5.866 5.288 5.789 5.645 5.919
2.015 2.114 2.328 2.330 2.275 2.220 2.436 2.438 2.260
5.223 5.658 6.215 6.069 6.400 5.805 6.365 6.221 6.494
2.393 2.519 2.761 2.763 2.708 2.637 2.884 2.886 2.708
5.050 5.474 6.018 5.872 6.203 5.613 6.155 6.011 6.284
2.274 2.393 2.629 2.631 2.576 2.509 2.748 2.750 2.572
4.928 5.344 5.878 5.732 6.063 5.479 6.005 5.861 6.134
2.182 2.297 2.529 2.531 2.476 2.411 2.646 2.648 2.470
4.894 5.307 5.828 5.682 6.013 5.439 5.955 5.811 6.085
2.148 2.260 2.488 2.490 2.435 2.372 2.602 2.604 2.426
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
2.5 V
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–236
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–115. EP3SE80 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.873
1.950
3.713
1.839
3.595
1.752
3.541
1.719
3.477
1.655
3.467
1.645
3.822
1.917
3.573
1.736
3.521
1.699
3.515
1.693
3.464
1.642
3.457
1.635
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.582
1.743
3.437
1.645
3.335
1.563
3.286
1.538
3.215
1.467
3.210
1.462
3.500
1.684
3.301
1.552
3.256
1.508
3.245
1.496
3.210
1.461
3.206
1.457
5.517 5.976 6.542 6.396 6.727 6.137 6.700 6.556 6.829
2.588 2.728 2.979 2.981 2.926 2.855 3.110 3.112 2.934
5.301 5.735 6.292 6.146 6.477 5.884 6.443 6.299 6.572
2.436 2.570 2.818 2.820 2.765 2.696 2.944 2.946 2.768
5.100 5.530 6.088 5.942 6.273 5.677 6.224 6.080 6.353
2.309 2.432 2.674 2.676 2.621 2.552 2.797 2.799 2.621
5.004 5.434 5.978 5.832 6.163 5.573 6.109 5.965 6.238
2.248 2.366 2.599 2.601 2.546 2.481 2.716 2.718 2.540
4.906 5.319 5.848 5.702 6.033 5.452 5.968 5.824 6.098
2.160 2.272 2.500 2.502 2.447 2.384 2.615 2.617 2.439
4.900 5.313 5.843 5.697 6.028 5.445 5.961 5.817 6.091
2.154 2.266 2.493 2.495 2.440 2.377 2.608 2.610 2.432
5.432 5.873 6.430 6.284 6.615 6.026 6.587 6.443 6.716
2.526 2.655 2.907 2.909 2.854 2.785 3.043 3.045 2.867
5.059 5.482 6.027 5.881 6.212 5.622 6.162 6.018 6.291
2.283 2.401 2.636 2.638 2.583 2.517 2.757 2.759 2.581
4.948 5.368 5.920 5.774 6.105 5.505 6.035 5.891 6.164
2.202 2.321 2.556 2.558 2.503 2.437 2.674 2.676 2.498
4.942 5.360 5.905 5.759 6.090 5.498 6.022 5.878 6.151
2.196 2.314 2.547 2.549 2.494 2.430 2.666 2.668 2.490
4.894 5.307 5.835 5.689 6.020 5.439 5.954 5.810 6.084
2.148 2.260 2.486 2.488 2.433 2.371 2.601 2.603 2.425
4.873 5.286 5.811 5.665 5.996 5.418 5.932 5.788 6.062
2.128 2.239 2.466 2.468 2.413 2.350 2.580 2.582 2.404
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.8 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–237
I/O Timing
Table 1–115. EP3SE80 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.744
1.860
3.547
1.725
3.506
1.684
3.472
1.650
3.480
1.658
3.483
1.661
3.463
1.641
3.456
1.634
3.500
1.678
3.479
1.657
3.482
1.660
3.462
1.640
3.458
1.636
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.464
1.663
3.289
1.541
3.236
1.488
3.216
1.467
3.229
1.481
3.232
1.484
3.214
1.465
3.209
1.460
3.247
1.499
3.228
1.480
3.229
1.481
3.212
1.464
3.209
1.460
5.345 5.777 6.354 6.208 6.539 5.937 6.499 6.355 6.628
2.480 2.609 2.850 2.852 2.797 2.732 2.977 2.979 2.801
5.016 5.443 5.997 5.851 6.182 5.583 6.118 5.974 6.247
2.261 2.378 2.610 2.612 2.557 2.493 2.729 2.731 2.553
4.931 5.348 5.896 5.750 6.081 5.486 6.009 5.865 6.139
2.185 2.301 2.536 2.538 2.483 2.418 2.656 2.658 2.480
4.892 5.305 5.846 5.700 6.031 5.437 5.952 5.808 6.082
2.146 2.258 2.486 2.488 2.433 2.369 2.599 2.601 2.423
4.900 5.313 5.859 5.713 6.044 5.442 5.957 5.813 6.087
2.154 2.266 2.494 2.496 2.441 2.375 2.604 2.606 2.428
4.904 5.317 5.867 5.721 6.052 5.446 5.961 5.817 6.091
2.158 2.270 2.498 2.500 2.445 2.378 2.608 2.610 2.432
4.882 5.295 5.825 5.679 6.010 5.425 5.939 5.795 6.069
2.137 2.248 2.476 2.478 2.423 2.357 2.586 2.588 2.410
4.867 5.279 5.806 5.660 5.991 5.408 5.921 5.777 6.051
2.122 2.232 2.459 2.461 2.406 2.340 2.569 2.571 2.393
4.923 5.336 5.889 5.743 6.074 5.466 5.981 5.837 6.111
2.177 2.289 2.517 2.519 2.464 2.398 2.628 2.630 2.452
4.901 5.314 5.854 5.708 6.039 5.444 5.958 5.814 6.088
2.155 2.267 2.495 2.497 2.442 2.376 2.605 2.607 2.429
4.909 5.323 5.871 5.725 6.056 5.454 5.969 5.825 6.099
2.163 2.276 2.505 2.507 2.452 2.386 2.616 2.618 2.440
4.884 5.298 5.831 5.685 6.016 5.428 5.943 5.799 6.073
2.139 2.251 2.480 2.482 2.427 2.360 2.591 2.593 2.415
4.880 5.294 5.823 5.677 6.008 5.424 5.939 5.795 6.069
2.135 2.247 2.475 2.477 2.422 2.356 2.587 2.589 2.411
2mA
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
1.2 V
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS I
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–238
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–115. EP3SE80 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.457
1.635
3.457
1.635
3.491
1.669
3.475
1.653
3.460
1.638
3.461
1.639
3.456
1.634
3.473
1.651
3.473
1.651
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.209
1.461
3.208
1.460
3.239
1.490
3.224
1.475
3.211
1.462
3.211
1.463
3.207
1.458
3.225
1.476
3.224
1.475
4.868 5.279 5.805 5.659 5.990 5.409 5.922 5.778 6.052
2.122 2.233 2.459 2.461 2.406 2.341 2.569 2.571 2.393
4.876 5.289 5.805 5.657 5.989 5.419 5.935 5.791 6.065
2.130 2.243 2.471 2.473 2.418 2.351 2.582 2.584 2.406
4.916 5.329 5.870 5.724 6.055 5.459 5.973 5.829 6.103
2.170 2.282 2.509 2.511 2.456 2.391 2.620 2.622 2.444
4.902 5.316 5.854 5.708 6.039 5.446 5.962 5.818 6.092
2.156 2.269 2.497 2.499 2.444 2.378 2.609 2.611 2.433
4.882 5.295 5.826 5.680 6.011 5.426 5.941 5.797 6.071
2.136 2.248 2.477 2.479 2.424 2.358 2.588 2.590 2.412
4.883 5.297 5.831 5.685 6.016 5.428 5.944 5.800 6.074
2.137 2.250 2.480 2.482 2.427 2.360 2.591 2.593 2.415
4.876 5.290 5.820 5.674 6.005 5.420 5.936 5.792 6.066
2.130 2.243 2.472 2.474 2.419 2.352 2.583 2.585 2.407
4.884 5.295 5.828 5.682 6.013 5.424 5.937 5.793 6.067
2.138 2.248 2.474 2.476 2.421 2.356 2.584 2.586 2.408
4.888 5.300 5.843 5.697 6.028 5.429 5.943 5.799 6.073
2.142 2.253 2.480 2.482 2.427 2.361 2.590 2.592 2.414
8mA
GCLK
tco
PLL
SSTL-18
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-15
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
SSTL-15
CLASS II
GCLK tco
16mA
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–239
I/O Timing
Table 1–115. EP3SE80 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.459
1.637
3.454
1.632
3.457
1.635
3.455
1.633
3.474
1.652
3.470
1.648
3.469
1.647
3.459
1.637
3.461
1.639
3.486
1.664
3.474
1.652
3.472
1.650
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.211
1.462
3.206
1.458
3.208
1.460
3.207
1.459
3.226
1.477
3.221
1.472
3.220
1.472
3.211
1.462
3.212
1.464
3.234
1.486
3.224
1.475
3.222
1.474
4.872 5.284 5.816 5.670 6.001 5.413 5.927 5.783 6.057
2.126 2.237 2.464 2.466 2.411 2.345 2.574 2.576 2.398
4.866 5.278 5.801 5.655 5.986 5.407 5.921 5.777 6.051
2.120 2.231 2.458 2.460 2.405 2.339 2.568 2.570 2.392
4.871 5.283 5.818 5.672 6.003 5.413 5.927 5.783 6.057
2.125 2.236 2.464 2.466 2.411 2.345 2.575 2.577 2.399
4.864 5.276 5.791 5.645 5.976 5.405 5.918 5.774 6.048
2.118 2.229 2.456 2.458 2.403 2.337 2.566 2.568 2.390
4.886 5.297 5.828 5.682 6.013 5.427 5.939 5.795 6.069
2.140 2.250 2.477 2.479 2.424 2.359 2.587 2.589 2.411
4.884 5.296 5.831 5.685 6.016 5.426 5.939 5.795 6.069
2.138 2.249 2.476 2.478 2.423 2.358 2.586 2.588 2.410
4.885 5.297 5.832 5.686 6.017 5.427 5.940 5.796 6.070
2.139 2.250 2.477 2.479 2.424 2.359 2.587 2.589 2.411
4.872 5.285 5.813 5.667 5.998 5.414 5.928 5.784 6.058
2.127 2.238 2.465 2.467 2.412 2.346 2.575 2.577 2.399
4.878 5.291 5.823 5.677 6.008 5.421 5.936 5.792 6.066
2.132 2.245 2.473 2.475 2.420 2.353 2.584 2.586 2.408
4.906 5.318 5.853 5.707 6.038 5.449 5.963 5.819 6.093
2.160 2.272 2.499 2.501 2.446 2.381 2.611 2.613 2.435
4.894 5.307 5.839 5.693 6.024 5.437 5.952 5.808 6.082
2.148 2.260 2.488 2.490 2.435 2.369 2.599 2.601 2.423
4.892 5.305 5.838 5.692 6.023 5.436 5.951 5.807 6.081
2.146 2.258 2.486 2.488 2.433 2.368 2.598 2.600 2.422
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
8mA
GCLK
tco
CLASS I
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
8mA
GCLK
tco
CLASS I
PLL
GCLK tco
10mA
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
GCLK
tco
CLASS II
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–240
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–115. EP3SE80 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.470
1.648
3.466
1.644
3.541
1.719
3.541
1.719
3.617
1.758
3.494
1.669
3.459
1.637
3.445
1.623
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.220
1.471
3.216
1.467
3.293
1.544
3.293
1.544
3.333
1.573
3.243
1.494
3.213
1.465
3.199
1.451
4.891 5.305 5.836 5.690 6.021 5.435 5.951 5.807 6.081
2.145 2.258 2.486 2.488 2.433 2.367 2.598 2.600 2.422
4.884 5.298 5.826 5.680 6.011 5.428 5.943 5.799 6.073
2.139 2.251 2.479 2.481 2.426 2.360 2.591 2.593 2.415
4.902 5.306 5.810 5.662 5.994 5.436 5.941 5.797 6.071
2.156 2.259 2.476 2.478 2.423 2.368 2.588 2.590 2.412
4.902 5.306 5.810 5.662 5.994 5.436 5.941 5.797 6.071
2.156 2.259 2.476 2.478 2.423 2.368 2.588 2.590 2.412
5.038 5.451 5.972 5.826 6.157 5.587 6.111 5.967 6.240
2.222 2.334 2.556 2.558 2.503 2.446 2.669 2.671 2.493
4.871 5.284 5.804 5.658 5.989 5.418 5.938 5.794 6.067
2.119 2.222 2.439 2.441 2.386 2.330 2.549 2.551 2.373
4.797 5.199 5.704 5.558 5.889 5.328 5.835 5.691 5.965
2.052 2.152 2.369 2.371 2.316 2.260 2.482 2.484 2.306
4.776 5.176 5.675 5.527 5.859 5.302 5.801 5.657 5.931
2.031 2.129 2.341 2.343 2.288 2.234 2.449 2.451 2.273
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
Table 1–116 specifies EP3SE80 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–116. EP3SE80 Row Pins output Timing Parameters (Part 1 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Clock
Units
Standard
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.493
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
3.238
1.439
3.156
1.346
3.077
1.247
4.856 5.245 5.757 5.609 5.907 5.368 5.891 5.735 5.990
2.039 2.121 2.343 2.334 2.309 2.226 2.430 2.441 2.301
4.726 5.107 5.612 5.464 5.762 5.227 5.742 5.586 5.841
1.909 1.983 2.198 2.189 2.195 2.085 2.281 2.292 2.186
4.607 4.984 5.484 5.348 5.634 5.107 5.610 5.468 5.709
1.790 1.860 2.070 2.061 2.099 1.958 2.149 2.160 2.086
4mA
8mA
12mA
GCLK
PLL
1.634
3.3-V
LVTTL
GCLK
3.399
GCLK
PLL
1.529
GCLK
3.310
GCLK
PLL
1.423
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–241
I/O Timing
Table 1–116. EP3SE80 Row Pins output Timing Parameters (Part 2 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.497
1.638
3.314
1.429
3.439
1.580
3.319
1.453
3.281
1.402
3.358
1.499
3.265
1.380
3.475
1.616
3.377
1.518
3.321
1.441
3.722
1.862
3.520
1.660
3.418
1.558
3.379
1.497
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.248
1.449
3.081
1.251
3.192
1.393
3.082
1.268
3.045
1.229
3.106
1.307
3.032
1.207
3.218
1.419
3.124
1.309
3.067
1.263
3.451
1.652
3.229
1.427
3.161
1.362
3.136
1.315
4.864 5.250 5.761 5.613 5.911 5.374 5.895 5.739 5.994
2.047 2.126 2.347 2.338 2.318 2.232 2.434 2.445 2.313
4.613 4.999 5.490 5.358 5.640 5.119 5.617 5.477 5.716
1.796 1.866 2.076 2.067 2.109 1.964 2.156 2.167 2.095
4.808 5.198 5.713 5.565 5.863 5.325 5.849 5.693 5.948
1.991 2.074 2.299 2.290 2.275 2.183 2.388 2.399 2.267
4.655 5.039 5.549 5.401 5.699 5.163 5.685 5.528 5.783
1.838 1.915 2.135 2.126 2.130 2.021 2.224 2.234 2.121
4.582 4.957 5.461 5.313 5.611 5.077 5.592 5.435 5.690
1.756 1.832 2.047 2.038 2.060 1.935 2.131 2.141 2.048
4.702 5.091 5.603 5.455 5.753 5.217 5.738 5.581 5.836
1.885 1.967 2.189 2.180 2.166 2.075 2.277 2.287 2.157
4.554 4.928 5.422 5.281 5.572 5.047 5.552 5.401 5.650
1.721 1.793 2.008 1.999 2.032 1.895 2.091 2.101 2.019
4.940 5.352 5.885 5.737 6.035 5.485 6.028 5.871 6.126
2.123 2.228 2.471 2.462 2.420 2.343 2.567 2.577 2.419
4.785 5.189 5.715 5.567 5.865 5.318 5.854 5.697 5.952
1.968 2.065 2.301 2.292 2.278 2.176 2.393 2.403 2.274
4.679 5.070 5.589 5.441 5.739 5.195 5.724 5.567 5.822
1.857 1.946 2.175 2.166 2.187 2.053 2.263 2.273 2.180
5.326 5.781 6.360 6.212 6.510 5.922 6.504 6.356 6.611
2.507 2.657 2.761 2.937 2.944 2.780 2.883 3.062 2.957
4.999 5.412 5.955 5.807 6.105 5.557 6.098 5.949 6.204
2.180 2.288 2.401 2.532 2.539 2.415 2.522 2.655 2.550
4.846 5.262 5.796 5.648 5.946 5.389 5.925 5.777 6.032
2.027 2.138 2.301 2.373 2.380 2.247 2.416 2.483 2.378
4.770 5.176 5.699 5.552 5.849 5.300 5.831 5.683 5.938
1.950 2.044 2.235 2.276 2.297 2.152 2.344 2.389 2.290
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
2mA
4mA
6mA
8mA
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
1.8 V
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–242
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–116. EP3SE80 Row Pins output Timing Parameters (Part 3 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.640
1.780
3.396
1.522
3.370
1.488
3.359
1.477
3.565
1.705
3.400
1.518
3.309
1.427
3.305
1.415
3.294
1.397
3.323
1.441
3.318
1.436
3.307
1.425
3.296
1.414
3.295
1.413
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.362
1.563
3.152
1.331
3.125
1.304
3.106
1.285
3.305
1.506
3.157
1.336
3.071
1.248
3.066
1.236
3.057
1.220
3.085
1.264
3.080
1.259
3.069
1.248
3.058
1.237
3.058
1.237
5.236 5.694 6.288 6.140 6.438 5.829 6.428 6.280 6.535
2.417 2.570 2.698 2.865 2.872 2.687 2.818 2.986 2.881
4.831 5.257 5.797 5.649 5.947 5.383 5.924 5.776 6.031
2.012 2.133 2.304 2.374 2.381 2.241 2.417 2.482 2.377
4.758 5.168 5.691 5.552 5.841 5.293 5.819 5.677 5.926
1.939 2.037 2.235 2.268 2.297 2.143 2.344 2.377 2.290
4.738 5.143 5.672 5.533 5.822 5.269 5.797 5.658 5.904
1.917 2.019 2.216 2.249 2.278 2.125 2.325 2.355 2.271
5.146 5.608 6.213 6.065 6.363 5.741 6.344 6.196 6.451
2.327 2.484 2.637 2.790 2.797 2.599 2.749 2.902 2.797
4.853 5.285 5.838 5.690 5.988 5.408 5.966 5.818 6.073
2.034 2.161 2.352 2.415 2.422 2.266 2.461 2.524 2.419
4.672 5.060 5.557 5.426 5.707 5.180 5.686 5.548 5.785
1.835 1.918 2.143 2.134 2.177 2.020 2.225 2.236 2.166
4.669 5.058 5.549 5.424 5.699 5.179 5.679 5.547 5.778
1.827 1.910 2.135 2.126 2.175 2.012 2.218 2.229 2.165
4.654 5.042 5.522 5.407 5.672 5.162 5.652 5.529 5.751
1.802 1.885 2.108 2.099 2.158 1.986 2.191 2.202 2.147
4.689 5.080 5.578 5.447 5.724 5.199 5.698 5.568 5.802
1.849 1.934 2.130 2.151 2.192 2.035 2.235 2.254 2.181
4.687 5.079 5.577 5.446 5.723 5.197 5.696 5.566 5.800
1.847 1.933 2.129 2.150 2.191 2.033 2.233 2.252 2.179
4.677 5.069 5.567 5.436 5.713 5.188 5.687 5.557 5.791
1.837 1.923 2.119 2.140 2.181 2.024 2.224 2.243 2.170
4.664 5.056 5.554 5.423 5.700 5.176 5.675 5.545 5.779
1.824 1.910 2.106 2.127 2.168 2.012 2.212 2.231 2.158
4.664 5.056 5.554 5.423 5.700 5.175 5.675 5.545 5.779
1.824 1.910 2.106 2.127 2.168 2.011 2.212 2.231 2.158
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
4mA
6mA
8mA
10mA
12mA
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-2
CLASS I
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–243
I/O Timing
Table 1–116. EP3SE80 Row Pins output Timing Parameters (Part 4 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.302
1.420
3.305
1.423
3.326
1.444
3.312
1.430
3.300
1.418
3.308
1.426
3.302
1.420
3.294
1.412
3.296
1.414
3.293
1.411
3.301
1.419
3.314
1.432
3.309
1.427
3.305
1.423
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.066
1.245
3.067
1.246
3.088
1.267
3.074
1.253
3.063
1.242
3.073
1.252
3.066
1.245
3.057
1.236
3.060
1.239
3.056
1.235
3.064
1.243
3.079
1.258
3.073
1.252
3.069
1.248
4.663 5.053 5.549 5.418 5.695 5.171 5.669 5.539 5.773
1.823 1.907 2.101 2.122 2.163 2.007 2.206 2.225 2.152
4.669 5.061 5.559 5.428 5.705 5.180 5.680 5.550 5.784
1.829 1.915 2.111 2.132 2.173 2.016 2.217 2.236 2.163
4.698 5.091 5.591 5.460 5.740 5.209 5.710 5.580 5.817
1.858 1.946 2.143 2.167 2.205 2.046 2.247 2.268 2.193
4.687 5.081 5.581 5.450 5.727 5.200 5.701 5.571 5.805
1.847 1.935 2.133 2.154 2.195 2.036 2.238 2.257 2.184
4.674 5.068 5.568 5.437 5.714 5.187 5.688 5.558 5.792
1.834 1.922 2.120 2.141 2.182 2.023 2.225 2.244 2.171
4.662 5.051 5.547 5.416 5.693 5.170 5.666 5.536 5.770
1.822 1.905 2.099 2.120 2.161 2.006 2.203 2.222 2.149
4.660 5.050 5.546 5.415 5.692 5.169 5.666 5.536 5.770
1.820 1.904 2.098 2.119 2.160 2.005 2.203 2.222 2.149
4.653 5.043 5.539 5.408 5.685 5.162 5.659 5.529 5.763
1.813 1.897 2.091 2.112 2.153 1.998 2.196 2.215 2.142
4.656 5.046 5.543 5.412 5.689 5.165 5.662 5.532 5.766
1.816 1.900 2.095 2.116 2.157 2.001 2.199 2.218 2.145
4.658 5.049 5.546 5.415 5.692 5.168 5.667 5.537 5.771
1.818 1.903 2.098 2.119 2.160 2.004 2.204 2.223 2.150
4.656 5.046 5.542 5.411 5.688 5.164 5.661 5.531 5.765
1.816 1.900 2.094 2.115 2.156 2.000 2.198 2.217 2.144
4.671 5.061 5.558 5.427 5.704 5.179 5.677 5.547 5.781
1.831 1.915 2.110 2.131 2.172 2.015 2.214 2.233 2.160
4.672 5.063 5.560 5.429 5.706 5.181 5.680 5.550 5.784
1.832 1.917 2.112 2.133 2.174 2.017 2.217 2.236 2.163
4.667 5.058 5.555 5.424 5.701 5.176 5.674 5.544 5.778
1.827 1.912 2.107 2.128 2.169 2.012 2.211 2.230 2.157
8mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5-V
HSTL
CLASS I
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–244
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–116. EP3SE80 Row Pins output Timing Parameters (Part 5 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Clock
Units
Standard
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
3.316
1.434
3.308
1.426
3.308
1.426
3.415
1.510
3.415
1.510
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.081
1.260
3.072
1.251
3.071
1.250
3.177
1.333
3.177
1.333
4.684 5.077 5.577 5.446 5.723 5.195 5.696 5.566 5.800
1.844 1.931 2.129 2.150 2.191 2.031 2.233 2.252 2.179
4.675 5.068 5.568 5.437 5.714 5.186 5.687 5.557 5.791
1.835 1.922 2.120 2.141 2.182 2.022 2.224 2.243 2.170
4.682 5.076 5.577 5.446 5.723 5.195 5.697 5.567 5.801
1.842 1.930 2.129 2.150 2.191 2.031 2.234 2.253 2.180
4.724 5.106 5.581 5.466 5.731 5.228 5.698 5.590 5.810
1.860 1.936 2.152 2.143 2.217 2.038 2.252 2.248 2.208
4.724 5.106 5.581 5.466 5.731 5.228 5.698 5.590 5.810
1.860 1.936 2.152 2.143 2.217 2.038 2.252 2.248 2.208
4mA
6mA
8mA
—
GCLK
PLL
1.2-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
Table 1–117 through Table 1–120 show the maximum I/O timing parameters for
EP3SE80 devices for differential I/O standards.
Table 1–117 specifies EP3SE80 column pins input timing parameters for differential
I/O standards.
Table 1–117. EP3SE80 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.997
1.133
0.960
-0.691
-0.997
1.133
0.960
-0.691
-0.997
1.133
0.960
-0.691
-0.813
0.942
1.144
-0.882
-1.029
1.184
0.994
-0.701
-1.029
1.184
0.994
-0.701
-1.029
1.184
0.994
-0.701
-0.852
0.999
1.171
-0.886
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
1.415 1.436 1.618 1.551 1.927 1.411 1.858 1.524 1.966
1.879 2.224 2.401 2.288 2.194 2.277 2.567 2.345 2.245
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
1.415 1.436 1.618 1.551 1.927 1.411 1.858 1.524 1.966
1.879 2.224 2.401 2.288 2.194 2.277 2.567 2.345 2.245
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
1.415 1.436 1.618 1.551 1.927 1.411 1.858 1.524 1.966
1.879 2.224 2.401 2.288 2.194 2.277 2.567 2.345 2.245
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837
1.460 1.595 1.731 1.659 2.031 1.604 1.739 1.674 2.075
1.802 2.025 2.242 2.134 2.045 2.042 2.260 2.147 2.091
-1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
MINI-LVDS
RSDS
GCLK
tsu
th
GCLK
PLL
tsu
th
tsu
th
GCLK
GCLK
tsu
th
DIFFERENTIAL
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–245
I/O Timing
Table 1–117. EP3SE80 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.813
0.942
1.144
-0.882
-0.821
0.950
1.136
-0.874
-0.821
0.950
1.136
-0.874
-0.833
0.962
1.124
-0.862
-0.833
0.962
1.124
-0.862
-0.821
0.950
1.136
-0.874
-0.821
0.950
1.136
-0.874
-0.833
0.962
1.124
-0.862
-0.833
0.962
1.124
-0.862
-0.852
0.999
1.171
-0.886
-0.864
1.011
1.159
-0.874
-0.864
1.011
1.159
-0.874
-0.875
1.022
1.148
-0.863
-0.875
1.022
1.148
-0.863
-0.864
1.011
1.159
-0.874
-0.864
1.011
1.159
-0.874
-0.875
1.022
1.148
-0.863
-0.875
1.022
1.148
-0.863
-1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837
1.460 1.595 1.731 1.659 2.031 1.604 1.739 1.674 2.075
1.802 2.025 2.242 2.134 2.045 2.042 2.260 2.147 2.091
-1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588
-1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852
1.470 1.606 1.747 1.675 2.047 1.615 1.754 1.689 2.090
1.792 2.014 2.226 2.118 2.029 2.031 2.245 2.132 2.076
-1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573
-1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852
1.470 1.606 1.747 1.675 2.047 1.615 1.754 1.689 2.090
1.792 2.014 2.226 2.118 2.029 2.031 2.245 2.132 2.076
-1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573
-1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870
1.480 1.617 1.766 1.694 2.066 1.626 1.772 1.707 2.108
1.783 2.003 2.207 2.099 2.010 2.020 2.227 2.114 2.058
-1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555
-1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870
1.480 1.617 1.766 1.694 2.066 1.626 1.772 1.707 2.108
1.783 2.003 2.207 2.099 2.010 2.020 2.227 2.114 2.058
-1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555
-1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852
1.470 1.606 1.747 1.675 2.047 1.615 1.754 1.689 2.090
1.792 2.014 2.226 2.118 2.029 2.031 2.245 2.132 2.076
-1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573
-1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852
1.470 1.606 1.747 1.675 2.047 1.615 1.754 1.689 2.090
1.792 2.014 2.226 2.118 2.029 2.031 2.245 2.132 2.076
-1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573
-1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870
1.480 1.617 1.766 1.694 2.066 1.626 1.772 1.707 2.108
1.783 2.003 2.207 2.099 2.010 2.020 2.227 2.114 2.058
-1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555
-1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870
1.480 1.617 1.766 1.694 2.066 1.626 1.772 1.707 2.108
1.783 2.003 2.207 2.099 2.010 2.020 2.227 2.114 2.058
-1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–246
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–117. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.840
0.969
1.117
-0.855
-0.840
0.969
1.117
-0.855
-0.881
1.028
1.142
-0.857
-0.881
1.028
1.142
-0.857
-1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866
1.493 1.625 1.769 1.697 2.070 1.633 1.772 1.706 2.109
1.771 1.998 2.207 2.097 2.011 2.016 2.232 2.116 2.062
-1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554
-1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866
1.493 1.625 1.769 1.697 2.070 1.633 1.772 1.706 2.109
1.771 1.998 2.207 2.097 2.011 2.016 2.232 2.116 2.062
-1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–247
I/O Timing
Table 1–118 specifies EP3SE80 row pins input timing parameters for differential I/O
standards.
Table 1–118. EP3SE80 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.944
1.077
0.961
-0.691
-0.944
1.077
0.961
-0.691
-0.944
1.077
0.961
-0.691
-0.749
0.875
1.156
-0.893
-0.749
0.875
1.156
-0.893
-0.758
0.884
1.147
-0.884
-0.758
0.884
1.147
-0.884
-0.772
0.898
1.133
-0.870
-0.979
1.130
0.989
-0.700
-0.979
1.130
0.989
-0.700
-0.979
1.130
0.989
-0.700
-0.794
0.936
1.174
-0.894
-0.794
0.936
1.174
-0.894
-0.806
0.948
1.162
-0.882
-0.806
0.948
1.162
-0.882
-0.818
0.960
1.150
-0.870
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
GCLK
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
tsu
th
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493 ns
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
-1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677
1.345 1.468 1.587 1.524 1.867 1.479 1.597 1.535 1.912
1.864 2.104 2.344 2.224 2.163 2.120 2.362 2.240 2.210
-1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709
-1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677
1.345 1.468 1.587 1.524 1.867 1.479 1.597 1.535 1.912
1.864 2.104 2.344 2.224 2.163 2.120 2.362 2.240 2.210
-1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
ns
ns
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177
tsu
th
GCLK
PLL
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–248
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–118. EP3SE80 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
tsu
th
-0.772
0.898
1.133
-0.870
-0.758
0.884
1.147
-0.884
-0.758
0.884
1.147
-0.884
-0.772
0.898
1.133
-0.870
-0.772
0.898
1.133
-0.870
-0.781
0.907
1.124
-0.861
-0.781
0.907
1.124
-0.861
-0.818
0.960
1.150
-0.870
-0.806
0.948
1.162
-0.882
-0.806
0.948
1.162
-0.882
-0.818
0.960
1.150
-0.870
-0.818
0.960
1.150
-0.870
-0.827
0.969
1.141
-0.861
-0.827
0.969
1.141
-0.861
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 ns
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
ns
ns
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194
tsu
th
GCLK
PLL
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676
-1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712
1.379 1.502 1.631 1.568 1.912 1.509 1.636 1.573 1.952
1.827 2.068 2.299 2.178 2.118 2.089 2.323 2.199 2.170
-1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
-1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712 ns
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
ns
ns
1.379 1.502 1.631 1.568 1.912 1.509 1.636 1.573 1.952
1.827 2.068 2.299 2.178 2.118 2.089 2.323 2.199 2.170
tsu
th
GCLK
PLL
-1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–249
I/O Timing
Table 1–119 specifies EP3SE80 Column Pins Output Timing parameters for differential
I/O standards.
Table 1–119. EP3SE80 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.152
1.328
3.148
1.324
3.152
1.328
3.148
1.324
3.152
1.328
3.148
1.324
3.179
1.355
3.169
1.345
3.169
1.345
3.162
1.338
3.161
1.337
3.183
1.359
3.387
1.502
3.390
1.505
3.387
1.502
3.390
1.505
3.387
1.502
3.390
1.505
3.420
1.535
3.410
1.525
3.410
1.525
3.404
1.519
3.402
1.517
3.424
1.539
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
—
—
LVDS_E_1R
LVDS_E_3R
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns
ns
GCLK
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns
ns
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns
ns
—
RSDS_E_1R
RSDS_E_3R
GCLK
PLL
GCLK
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns
ns
—
GCLK
PLL
GCLK
4.828 5.233 5.750 5.610 5.910 5.358 5.875 5.736 5.985
1.984 2.084 2.298 2.309 2.335 2.190 2.407 2.417 2.323 ns
ns
4mA
6mA
8mA
GCLK
PLL
GCLK
4.818 5.222 5.740 5.600 5.900 5.347 5.865 5.726 5.975
1.974 2.073 2.288 2.299 2.325 2.179 2.397 2.407 2.313 ns
ns
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
4.821 5.226 5.744 5.604 5.904 5.352 5.870 5.731 5.980
1.977 2.077 2.292 2.303 2.329 2.184 2.402 2.412 2.318 ns
ns
GCLK
PLL
GCLK
4.814 5.220 5.738 5.598 5.898 5.345 5.864 5.725 5.974
1.970 2.071 2.286 2.297 2.323 2.177 2.396 2.406 2.312 ns
10m
A
GCLK
PLL
GCLK
ns
ns
ns
ns
4.811 5.217 5.735 5.595 5.895 5.342 5.860 5.721 5.970
1.967 2.068 2.283 2.294 2.320 2.174 2.392 2.402 2.308
4.832 5.237 5.754 5.614 5.914 5.362 5.880 5.741 5.990
1.988 2.088 2.302 2.313 2.339 2.194 2.412 2.422 2.328
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
16m
A
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–250
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–119. EP3SE80 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.173
1.349
3.168
1.344
3.166
1.342
3.158
1.334
3.159
1.335
3.158
1.334
3.170
1.346
3.166
1.342
3.156
1.332
3.154
1.330
3.154
1.330
3.158
1.334
3.413
1.528
3.409
1.524
3.407
1.522
3.398
1.513
3.400
1.515
3.397
1.512
3.410
1.525
3.407
1.522
3.396
1.511
3.394
1.509
3.395
1.510
3.398
1.513
4.811 5.214 5.729 5.589 5.889 5.338 5.853 5.714 5.963
1.967 2.065 2.277 2.288 2.314 2.170 2.385 2.395 2.301
4.811 5.214 5.730 5.590 5.890 5.339 5.855 5.716 5.965
1.967 2.065 2.278 2.289 2.315 2.171 2.387 2.397 2.303
4.810 5.213 5.728 5.588 5.888 5.338 5.854 5.715 5.964
1.966 2.064 2.276 2.287 2.313 2.170 2.386 2.396 2.302
4.800 5.203 5.719 5.579 5.879 5.328 5.844 5.705 5.954
1.956 2.054 2.267 2.278 2.304 2.160 2.376 2.386 2.292
4.806 5.210 5.727 5.587 5.887 5.336 5.853 5.714 5.963
1.962 2.061 2.275 2.286 2.312 2.168 2.385 2.395 2.301
4.789 5.191 5.705 5.565 5.865 5.315 5.829 5.690 5.939
1.945 2.042 2.253 2.264 2.290 2.147 2.361 2.371 2.277
4.807 5.209 5.723 5.583 5.883 5.334 5.848 5.709 5.958
1.963 2.060 2.271 2.282 2.308 2.166 2.380 2.390 2.296
4.808 5.211 5.727 5.587 5.887 5.336 5.852 5.713 5.962
1.964 2.062 2.275 2.286 2.312 2.168 2.384 2.394 2.300
4.797 5.200 5.715 5.575 5.875 5.325 5.840 5.701 5.950
1.953 2.051 2.263 2.274 2.300 2.157 2.372 2.382 2.288
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
4.795 5.197 5.713 5.573 5.873 5.323 5.838 5.699 5.948 ns
ns
10m
A
GCLK
PLL
1.951 2.048 2.261 2.272 2.298 2.155 2.370 2.380 2.286
4.798 5.202 5.718 5.578 5.878 5.327 5.844 5.705 5.954 ns
ns
GCLK
12m
A
GCLK
PLL
1.954 2.053 2.266 2.277 2.303 2.159 2.376 2.386 2.292
4.795 5.197 5.712 5.572 5.872 5.322 5.837 5.698 5.947 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
16m
A
GCLK
PLL
ns
1.951 2.048 2.260 2.271 2.297 2.154 2.369 2.379 2.285
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–251
I/O Timing
Table 1–119. EP3SE80 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.184
1.360
3.170
1.346
3.158
1.334
3.158
1.334
3.154
1.330
3.158
1.334
3.159
1.335
3.187
1.363
3.176
1.352
3.171
1.347
3.157
1.333
3.155
1.331
3.159
1.335
3.159
1.335
3.427
1.542
3.413
1.528
3.400
1.515
3.400
1.515
3.396
1.511
3.398
1.513
3.400
1.515
3.430
1.545
3.418
1.533
3.414
1.529
3.399
1.514
3.397
1.512
3.399
1.514
3.400
1.515
4.840 5.245 5.762 5.622 5.922 5.370 5.887 5.748 5.997
1.996 2.096 2.310 2.321 2.347 2.202 2.419 2.429 2.335
4.828 5.234 5.752 5.612 5.912 5.360 5.878 5.739 5.988
1.984 2.085 2.300 2.311 2.337 2.192 2.410 2.420 2.326
4.811 5.216 5.734 5.594 5.894 5.342 5.860 5.721 5.970
1.967 2.067 2.282 2.293 2.319 2.174 2.392 2.402 2.308
4.814 5.220 5.738 5.598 5.898 5.346 5.865 5.726 5.975
1.970 2.071 2.286 2.297 2.323 2.178 2.397 2.407 2.313
4.807 5.212 5.731 5.591 5.891 5.339 5.857 5.718 5.967
1.963 2.063 2.279 2.290 2.316 2.171 2.389 2.399 2.305
4.800 5.203 5.719 5.579 5.879 5.328 5.844 5.705 5.954
1.956 2.054 2.267 2.278 2.304 2.160 2.376 2.386 2.292
4.808 5.213 5.730 5.590 5.890 5.338 5.856 5.717 5.966
1.964 2.064 2.278 2.289 2.315 2.170 2.388 2.398 2.304
4.839 5.243 5.760 5.620 5.920 5.369 5.885 5.746 5.995
1.995 2.094 2.308 2.319 2.345 2.201 2.417 2.427 2.333
4.827 5.231 5.748 5.608 5.908 5.357 5.873 5.734 5.983
1.983 2.082 2.296 2.307 2.333 2.189 2.405 2.415 2.321
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
8mA
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
4.827 5.232 5.749 5.609 5.909 5.358 5.875 5.736 5.985 ns
ns
GCLK
PLL
1.983 2.083 2.297 2.308 2.334 2.190 2.407 2.417 2.323
4.809 5.213 5.730 5.590 5.890 5.339 5.857 5.718 5.967 ns
ns
GCLK
10m
A
GCLK
PLL
1.965 2.064 2.278 2.289 2.315 2.171 2.389 2.399 2.305
4.807 5.211 5.728 5.588 5.888 5.337 5.854 5.715 5.964 ns
ns
GCLK
12m
A
GCLK
PLL
1.963 2.062 2.276 2.287 2.313 2.169 2.386 2.396 2.302
4.799 5.201 5.716 5.576 5.876 5.326 5.841 5.702 5.951 ns
ns
GCLK
8mA
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
1.955 2.052 2.264 2.275 2.301 2.158 2.373 2.383 2.289
4.807 5.211 5.728 5.588 5.888 5.337 5.854 5.715 5.964 ns
GCLK
16m
A
GCLK
PLL
ns
1.963 2.062 2.276 2.287 2.313 2.169 2.386 2.396 2.302
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–252
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–119. EP3SE80 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.175
1.351
3.175
1.351
3.165
1.341
3.158
1.334
3.417
1.532
3.417
1.532
3.407
1.522
3.399
1.514
4.823 5.226 5.742 5.602 5.902 5.352 5.867 5.728 5.977
1.979 2.077 2.290 2.301 2.327 2.184 2.399 2.409 2.315
4.823 5.226 5.742 5.602 5.902 5.352 5.867 5.728 5.977
1.979 2.077 2.290 2.301 2.327 2.184 2.399 2.409 2.315
4.813 5.216 5.732 5.592 5.892 5.342 5.858 5.719 5.968
1.969 2.067 2.280 2.291 2.317 2.174 2.390 2.400 2.306
4.799 5.201 5.716 5.576 5.876 5.326 5.841 5.702 5.951
1.955 2.052 2.264 2.275 2.301 2.158 2.373 2.383 2.289
8mA
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
16m
A
GCLK
PLL
Table 1–120 specifies EP3SE80 Row Pins Output Timing parameters for differential
I/O standards.
Table 1–120. EP3SE80 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
LVDS
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
2.744
0.931
3.136
1.333
3.118
1.315
2.744
0.931
3.136
1.333
3.118
1.315
2.744
0.931
2.932
1.057
3.376
1.511
3.366
1.501
2.932
1.057
3.376
1.511
3.366
1.501
2.932
1.057
4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107
1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456
4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871
1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229
4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932
1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290
4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107
1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456
4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871
1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229
4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932
1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290
4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107
1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456
—
—
—
—
—
—
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
GCLK
tco
PLL
GCLK tco
RSDS
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–253
I/O Timing
Table 1–120. EP3SE80 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
RSDS_E_1R
RSDS_E_3R
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.136
1.333
3.118
1.315
3.162
1.359
3.148
1.345
3.144
1.341
3.160
1.357
3.149
1.346
3.146
1.343
3.376
1.511
3.366
1.501
3.409
1.544
3.395
1.530
3.391
1.526
3.406
1.541
3.396
1.531
3.393
1.528
4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871
1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229
4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932
1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290
4.828 5.236 5.751 5.613 5.884 5.365 5.880 5.742 5.961
2.004 2.106 2.318 2.332 2.330 2.217 2.433 2.442 2.319
4.815 5.223 5.738 5.600 5.871 5.351 5.867 5.729 5.948
1.991 2.093 2.305 2.319 2.317 2.203 2.420 2.429 2.306
4.813 5.223 5.739 5.601 5.872 5.351 5.869 5.731 5.950
1.989 2.093 2.306 2.320 2.318 2.203 2.422 2.431 2.308
4.814 5.220 5.733 5.595 5.866 5.348 5.862 5.724 5.943
1.990 2.090 2.300 2.314 2.312 2.200 2.415 2.424 2.301
4.810 5.216 5.730 5.592 5.863 5.345 5.859 5.721 5.940
1.986 2.086 2.297 2.311 2.309 2.197 2.412 2.421 2.298
4.808 5.214 5.728 5.590 5.861 5.343 5.858 5.720 5.939
1.984 2.084 2.295 2.309 2.307 2.195 2.411 2.420 2.297
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
4mA
6mA
8mA
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–254
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–120. EP3SE80 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.157
1.354
3.147
1.344
3.133
1.330
3.130
1.327
3.127
1.324
3.128
1.325
3.177
1.374
3.153
1.350
3.136
1.333
3.403
1.538
3.394
1.529
3.380
1.515
3.376
1.511
3.374
1.509
3.374
1.509
3.427
1.562
3.403
1.538
3.384
1.519
4.809 5.215 5.727 5.589 5.860 5.343 5.856 5.718 5.937
1.985 2.085 2.294 2.308 2.306 2.195 2.409 2.418 2.295
4.807 5.213 5.726 5.588 5.859 5.342 5.856 5.718 5.937
1.983 2.083 2.293 2.307 2.305 2.194 2.409 2.418 2.295
4.792 5.198 5.712 5.574 5.845 5.327 5.841 5.703 5.922
1.968 2.068 2.279 2.293 2.291 2.179 2.394 2.403 2.280
4.788 5.194 5.708 5.570 5.841 5.323 5.837 5.699 5.918
1.964 2.064 2.275 2.289 2.287 2.175 2.390 2.399 2.276
4.789 5.197 5.711 5.573 5.844 5.326 5.841 5.703 5.922
1.965 2.067 2.278 2.292 2.290 2.178 2.394 2.403 2.280
4.779 5.185 5.698 5.560 5.831 5.313 5.827 5.689 5.908
1.955 2.055 2.265 2.279 2.277 2.165 2.380 2.389 2.266
4.850 5.258 5.774 5.636 5.907 5.387 5.903 5.765 5.984
2.026 2.128 2.341 2.355 2.353 2.239 2.456 2.465 2.342
4.832 5.241 5.757 5.619 5.890 5.370 5.888 5.750 5.969
2.008 2.111 2.324 2.338 2.336 2.222 2.441 2.450 2.327
4.810 5.219 5.735 5.597 5.868 5.348 5.866 5.728 5.947
1.986 2.089 2.302 2.316 2.314 2.200 2.419 2.428 2.305
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–255
I/O Timing
Table 1–120. EP3SE80 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.181
1.378
3.166
1.363
3.155
1.352
3.135
1.332
3.132
1.329
3.137
1.334
3.130
1.327
3.168
1.365
3.150
1.347
3.136
1.333
3.430
1.565
3.415
1.550
3.404
1.539
3.384
1.519
3.380
1.515
3.384
1.519
3.377
1.512
3.416
1.551
3.399
1.534
3.383
1.518
4.850 5.258 5.773 5.635 5.906 5.387 5.903 5.765 5.984
2.026 2.128 2.340 2.354 2.352 2.239 2.456 2.465 2.342
4.836 5.243 5.758 5.620 5.891 5.372 5.888 5.750 5.969
2.012 2.113 2.325 2.339 2.337 2.224 2.441 2.450 2.327
4.831 5.240 5.755 5.617 5.888 5.369 5.886 5.748 5.967
2.007 2.110 2.322 2.336 2.334 2.221 2.439 2.448 2.325
4.808 5.216 5.732 5.594 5.865 5.346 5.862 5.724 5.943
1.984 2.086 2.299 2.313 2.311 2.198 2.415 2.424 2.301
4.804 5.213 5.728 5.590 5.861 5.342 5.859 5.721 5.940
1.980 2.083 2.295 2.309 2.307 2.194 2.412 2.421 2.298
4.795 5.201 5.714 5.576 5.847 5.329 5.843 5.705 5.924
1.971 2.071 2.281 2.295 2.293 2.181 2.396 2.405 2.282
4.794 5.202 5.717 5.579 5.850 5.332 5.848 5.710 5.929
1.970 2.072 2.284 2.298 2.296 2.184 2.401 2.410 2.287
4.832 5.239 5.753 5.615 5.886 5.368 5.883 5.745 5.964
2.008 2.109 2.320 2.334 2.332 2.220 2.436 2.445 2.322
4.817 5.224 5.738 5.600 5.871 5.353 5.868 5.730 5.949
1.993 2.094 2.305 2.319 2.317 2.205 2.421 2.430 2.307
4.794 5.200 5.713 5.575 5.846 5.329 5.843 5.705 5.924
1.970 2.070 2.280 2.294 2.292 2.181 2.396 2.405 2.282
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V SSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
1.8-V SSTL
CLASS II
PLL
GCLK tco
16mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
2.5-V SSTL
CLASS I
PLL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V SSTL
CLASS II
GCLK
tco
PLL
Table 1–121 and Table 1–122 show EP3SE80 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–256
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–121 specifies EP3SE80 Column Pin delay adders when using the regional
clock.
Table 1–121. EP3SE80 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
RCLK input adder
0.251
1.895
-0.069
-1.545
0.187
1.982
0.253
-1.367
0.308 0.239 0.389 0.103 0.176 0.199 0.102 0.099 0.172
2.923 3.16 3.601 4.28 4.913 3.261 4.491 4.295 4.833
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.551 0.865 0.693 -0.059 -0.119 1.06 0.135 0.066 -0.046
-1.715 -1.587 -1.976 -3.145 -3.116 -1.541 -3.343 -3.027 -3.123
Table 1–122 specifies EP3SE80 Row Pin delay adders when using the regional clock.
Table 1–122. EP3SE80 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
RCLK input adder
0.014
0.116
0.004
-0.089
0.014
0.122
0.003
-0.089
0.018 0.005 -0.022
0.0
0.052 -0.004 -0.014 -0.008 0.056
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.192 0.206 0.231 0.217 0.367 0.198 0.223 0.21 0.371
0.029 0.042 0.056 0.039 -0.021 0.047 0.061 0.049 -0.025
-0.145 -0.161 -0.197 -0.169 -0.332 -0.151 -0.186 -0.157 -0.333
EP3SE110 I/O Timing Parameters
Table 1–123 through Table 1–126 show the maximum I/O timing parameters for
EP3SE110 for single-ended I/O standards.
Table 1–123 specifies EP3SE110 column pins input timing parameters for single-ended
I/O standards.
Table 1–123. EP3SE110 Column Pins Input Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.058
1.189
0.711
-0.447
-1.058
1.189
0.711
-0.447
-1.105
1.254
0.730
-0.446
-1.105
1.254
0.730
-0.446
-1.586 -1.732 -1.990 -1.922 -2.307 -1.750 -1.992 -1.928 -2.340 ns
GCLK
1.799 1.971 2.252 2.168 2.560 1.998 2.264 2.184 2.595
1.221 1.394 1.456 1.363 1.379 1.392 1.467 1.372 1.436
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-0.799 -0.921 -0.929 -0.868 -0.867 -0.908 -0.930 -0.867 -0.920 ns
-1.586 -1.732 -1.990 -1.922 -2.307 -1.750 -1.992 -1.928 -2.340 ns
tsu
th
GCLK
1.799 1.971 2.252 2.168 2.560 1.998 2.264 2.184 2.595
1.221 1.394 1.456 1.363 1.379 1.392 1.467 1.372 1.436
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-0.799 -0.921 -0.929 -0.868 -0.867 -0.908 -0.930 -0.867 -0.920 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–257
I/O Timing
Table 1–123. EP3SE110 Column Pins Input Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.064
1.195
0.705
-0.441
-1.064
1.195
0.705
-0.441
-1.054
1.185
0.715
-0.451
-1.070
1.203
0.697
-0.431
-1.063
1.196
0.704
-0.438
-1.003
1.136
0.764
-0.498
-0.984
1.117
0.783
-0.517
-0.984
1.117
0.783
-0.517
-0.977
1.110
0.790
-0.524
-1.116
1.265
0.719
-0.435
-1.116
1.265
0.719
-0.435
-1.111
1.260
0.724
-0.440
-1.131
1.282
0.702
-0.416
-1.121
1.272
0.712
-0.426
-1.069
1.220
0.764
-0.478
-1.040
1.191
0.793
-0.507
-1.040
1.191
0.793
-0.507
-1.034
1.185
0.799
-0.513
-1.585 -1.734 -1.989 -1.921 -2.306 -1.750 -1.997 -1.933 -2.345 ns
GCLK
1.798 1.973 2.251 2.167 2.559 1.998 2.269 2.189 2.600
1.222 1.392 1.457 1.364 1.380 1.392 1.462 1.367 1.431
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-0.800 -0.919 -0.930 -0.869 -0.868 -0.908 -0.925 -0.862 -0.915 ns
-1.585 -1.734 -1.989 -1.921 -2.306 -1.750 -1.997 -1.933 -2.345 ns
tsu
th
GCLK
1.798 1.973 2.251 2.167 2.559 1.998 2.269 2.189 2.600
1.222 1.392 1.457 1.364 1.380 1.392 1.462 1.367 1.431
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-0.800 -0.919 -0.930 -0.869 -0.868 -0.908 -0.925 -0.862 -0.915 ns
-1.594 -1.746 -2.008 -1.940 -2.325 -1.760 -2.008 -1.944 -2.356 ns
tsu
th
GCLK
1.807 1.985 2.270 2.186 2.578 2.008 2.280 2.200 2.611
1.213 1.380 1.438 1.345 1.361 1.382 1.451 1.356 1.420
ns
ns
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
-0.791 -0.907 -0.911 -0.850 -0.849 -0.898 -0.914 -0.851 -0.904 ns
-1.634 -1.782 -2.006 -1.938 -2.323 -1.794 -2.011 -1.947 -2.359 ns
tsu
th
GCLK
1.847 2.021 2.268 2.184 2.576 2.042 2.283 2.203 2.614
1.173 1.344 1.440 1.347 1.363 1.348 1.448 1.353 1.417
ns
ns
tsu
th
GCLK
PLL
-0.751 -0.871 -0.913 -0.852 -0.851 -0.864 -0.911 -0.848 -0.901 ns
-1.611 -1.750 -1.936 -1.868 -2.253 -1.763 -1.945 -1.881 -2.293 ns
tsu
th
GCLK
1.824 1.989 2.198 2.114 2.506 2.011 2.217 2.137 2.548
1.196 1.376 1.510 1.417 1.433 1.379 1.514 1.419 1.483
ns
ns
tsu
th
GCLK
PLL
-0.774 -0.903 -0.983 -0.922 -0.921 -0.895 -0.977 -0.914 -0.967 ns
-1.534 -1.651 -1.780 -1.712 -2.097 -1.667 -1.792 -1.728 -2.140 ns
tsu
th
GCLK
1.747 1.890 2.042 1.958 2.350 1.915 2.064 1.984 2.395
1.273 1.475 1.666 1.573 1.589 1.475 1.667 1.572 1.636
ns
ns
tsu
th
GCLK
PLL
-0.851 -1.002 -1.139 -1.078 -1.077 -0.991 -1.130 -1.067 -1.120 ns
-1.506 -1.635 -1.782 -1.714 -2.099 -1.646 -1.788 -1.724 -2.136 ns
tsu
th
GCLK
1.719 1.874 2.044 1.960 2.352 1.894 2.060 1.980 2.391
1.301 1.491 1.664 1.571 1.587 1.496 1.671 1.576 1.640
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-0.879 -1.018 -1.137 -1.076 -1.075 -1.012 -1.134 -1.071 -1.124 ns
-1.506 -1.635 -1.782 -1.714 -2.099 -1.646 -1.788 -1.724 -2.136 ns
tsu
th
GCLK
1.719 1.874 2.044 1.960 2.352 1.894 2.060 1.980 2.391
1.301 1.491 1.664 1.571 1.587 1.496 1.671 1.576 1.640
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-0.879 -1.018 -1.137 -1.076 -1.075 -1.012 -1.134 -1.071 -1.124 ns
-1.494 -1.630 -1.782 -1.712 -2.100 -1.642 -1.793 -1.726 -2.140 ns
tsu
th
GCLK
1.706 1.866 2.041 1.957 2.348 1.887 2.060 1.981 2.390
1.314 1.499 1.667 1.576 1.589 1.503 1.670 1.577 1.639
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-0.892 -1.029 -1.143 -1.082 -1.082 -1.022 -1.137 -1.073 -1.128 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–258
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–123. EP3SE110 Column Pins Input Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-0.977
1.110
0.790
-0.524
-0.965
1.098
0.802
-0.536
-0.965
1.098
0.802
-0.536
-0.977
1.110
0.790
-0.524
-0.977
1.110
0.790
-0.524
-0.965
1.098
0.802
-0.536
-0.965
1.098
0.802
-0.536
-0.957
1.090
0.810
-0.544
-0.957
1.090
0.810
-0.544
-1.034
1.185
0.799
-0.513
-1.023
1.174
0.810
-0.524
-1.023
1.174
0.810
-0.524
-1.034
1.185
0.799
-0.513
-1.034
1.185
0.799
-0.513
-1.023
1.174
0.810
-0.524
-1.023
1.174
0.810
-0.524
-1.011
1.162
0.822
-0.536
-1.011
1.162
0.822
-0.536
-1.494 -1.630 -1.782 -1.712 -2.100 -1.642 -1.793 -1.726 -2.140 ns
GCLK
1.706 1.866 2.041 1.957 2.348 1.887 2.060 1.981 2.390
1.314 1.499 1.667 1.576 1.589 1.503 1.670 1.577 1.639
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-0.892 -1.029 -1.143 -1.082 -1.082 -1.022 -1.137 -1.073 -1.128 ns
-1.485 -1.619 -1.763 -1.693 -2.081 -1.631 -1.775 -1.708 -2.122 ns
tsu
th
GCLK
1.696 1.855 2.022 1.938 2.329 1.876 2.042 1.963 2.372
1.325 1.510 1.686 1.595 1.608 1.514 1.688 1.595 1.657
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-0.904 -1.040 -1.162 -1.101 -1.101 -1.033 -1.155 -1.091 -1.146 ns
-1.485 -1.619 -1.763 -1.693 -2.081 -1.631 -1.775 -1.708 -2.122 ns
tsu
th
GCLK
1.696 1.855 2.022 1.938 2.329 1.876 2.042 1.963 2.372
1.325 1.510 1.686 1.595 1.608 1.514 1.688 1.595 1.657
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.904 -1.040 -1.162 -1.101 -1.101 -1.033 -1.155 -1.091 -1.146 ns
-1.494 -1.630 -1.782 -1.712 -2.100 -1.642 -1.793 -1.726 -2.140 ns
tsu
th
GCLK
1.706 1.866 2.041 1.957 2.348 1.887 2.060 1.981 2.390
1.314 1.499 1.667 1.576 1.589 1.503 1.670 1.577 1.639
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.892 -1.029 -1.143 -1.082 -1.082 -1.022 -1.137 -1.073 -1.128 ns
-1.494 -1.630 -1.782 -1.712 -2.100 -1.642 -1.793 -1.726 -2.140 ns
tsu
th
GCLK
1.706 1.866 2.041 1.957 2.348 1.887 2.060 1.981 2.390
1.314 1.499 1.667 1.576 1.589 1.503 1.670 1.577 1.639
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.892 -1.029 -1.143 -1.082 -1.082 -1.022 -1.137 -1.073 -1.128 ns
-1.485 -1.619 -1.763 -1.693 -2.081 -1.631 -1.775 -1.708 -2.122 ns
tsu
th
GCLK
1.696 1.855 2.022 1.938 2.329 1.876 2.042 1.963 2.372
1.325 1.510 1.686 1.595 1.608 1.514 1.688 1.595 1.657
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.904 -1.040 -1.162 -1.101 -1.101 -1.033 -1.155 -1.091 -1.146 ns
-1.485 -1.619 -1.763 -1.693 -2.081 -1.631 -1.775 -1.708 -2.122 ns
tsu
th
GCLK
1.696 1.855 2.022 1.938 2.329 1.876 2.042 1.963 2.372
1.325 1.510 1.686 1.595 1.608 1.514 1.688 1.595 1.657
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.904 -1.040 -1.162 -1.101 -1.101 -1.033 -1.155 -1.091 -1.146 ns
-1.475 -1.608 -1.747 -1.677 -2.065 -1.620 -1.760 -1.693 -2.107 ns
tsu
th
GCLK
1.686 1.844 2.006 1.922 2.313 1.865 2.027 1.948 2.357
1.335 1.521 1.702 1.611 1.624 1.525 1.703 1.610 1.672
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.914 -1.051 -1.178 -1.117 -1.117 -1.044 -1.170 -1.106 -1.161 ns
-1.475 -1.608 -1.747 -1.677 -2.065 -1.620 -1.760 -1.693 -2.107 ns
tsu
th
GCLK
1.686 1.844 2.006 1.922 2.313 1.865 2.027 1.948 2.357
1.335 1.521 1.702 1.611 1.624 1.525 1.703 1.610 1.672
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-0.914 -1.051 -1.178 -1.117 -1.117 -1.044 -1.170 -1.106 -1.161 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–259
I/O Timing
Table 1–123. EP3SE110 Column Pins Input Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.064
1.195
0.705
-0.441
-1.116
1.265
0.719
-0.435
-1.585 -1.734 -1.989 -1.921 -2.306 -1.750 -1.997 -1.933 -2.345 ns
GCLK
1.798 1.973 2.251 2.167 2.559 1.998 2.269 2.189 2.600
1.222 1.392 1.457 1.364 1.380 1.392 1.462 1.367 1.431
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-0.800 -0.919 -0.930 -0.869 -0.868 -0.908 -0.925 -0.862 -0.915 ns
Table 1–124 specifies EP3SE110 row pins input timing parameters for single-ended
I/O standards.
Table 1–124. EP3SE110 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.917
1.041
1.022
-0.762
-0.917
1.041
1.022
-0.762
-0.923
1.047
1.016
-0.756
-0.923
1.047
1.016
-0.756
-0.911
1.035
1.028
-0.768
-0.987
1.112
1.040
-0.777
-0.960
1.099
1.000
-0.722
-0.960
1.099
1.000
-0.722
-0.971
1.110
0.989
-0.711
-0.971
1.110
0.989
-0.711
-0.964
1.103
0.996
-0.718
-1.042
1.182
1.054
-0.773
-1.364 -1.476 -1.736 -1.642 -2.026 -1.488 -1.737 -1.683 -2.064
1.561 1.698 1.978 1.873 2.261 1.720 1.989 1.922 2.300
1.632 1.851 1.964 1.893 1.808 1.901 1.982 1.864 1.859
-1.218 -1.386 -1.449 -1.406 -1.309 -1.426 -1.456 -1.368 -1.357
-1.364 -1.476 -1.736 -1.642 -2.026 -1.488 -1.737 -1.683 -2.064
1.561 1.698 1.978 1.873 2.261 1.720 1.989 1.922 2.300
1.632 1.851 1.964 1.893 1.808 1.901 1.982 1.864 1.859
-1.218 -1.386 -1.449 -1.406 -1.309 -1.426 -1.456 -1.368 -1.357
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
1.558 1.699 1.981 1.876 2.264 1.719 1.994 1.927 2.305
1.635 1.850 1.961 1.890 1.805 1.902 1.977 1.859 1.854
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
1.558 1.699 1.981 1.876 2.264 1.719 1.994 1.927 2.305
1.635 1.850 1.961 1.890 1.805 1.902 1.977 1.859 1.854
GCLK
3.3-V
LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.3-V
LVCMOS
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVTTL
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352 ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.370 -1.490 -1.754 -1.660 -2.044 -1.496 -1.752 -1.698 -2.079
1.567 1.712 1.996 1.891 2.279 1.728 2.004 1.937 2.315
1.626 1.837 1.946 1.875 1.790 1.893 1.967 1.849 1.844
-1.212 -1.372 -1.431 -1.388 -1.291 -1.418 -1.441 -1.353 -1.342
-1.456 -1.570 -1.756 -1.705 -2.042 -1.576 -1.754 -1.707 -2.080
1.653 1.793 1.999 1.936 2.277 1.808 2.007 1.948 2.316
1.703 1.929 1.948 1.963 1.900 1.946 1.966 1.848 1.952
-1.286 -1.461 -1.433 -1.472 -1.399 -1.468 -1.440 -1.352 -1.447
GCLK
2.5 V
1.8 V
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–260
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–124. EP3SE110 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
tsu
th
-0.977
1.102
1.050
-0.787
-0.917
1.042
1.110
-0.847
-0.854
0.979
1.085
-0.824
-0.854
0.979
1.085
-0.824
-0.891
1.016
1.136
-0.873
-0.891
1.016
1.136
-0.873
-0.877
1.002
1.150
-0.887
-0.891
1.016
1.136
-0.873
-0.891
1.016
1.136
-0.873
-1.031
1.171
1.065
-0.784
-0.978
1.118
1.118
-0.837
-0.906
1.046
1.054
-0.775
-0.906
1.046
1.054
-0.775
-0.943
1.083
1.153
-0.872
-0.943
1.083
1.153
-0.872
-0.931
1.071
1.165
-0.884
-0.943
1.083
1.153
-0.872
-0.943
1.083
1.153
-0.872
-1.432 -1.538 -1.688 -1.637 -1.974 -1.545 -1.689 -1.642 -2.015
1.629 1.761 1.931 1.868 2.209 1.777 1.942 1.883 2.251
1.727 1.961 2.016 2.031 1.968 1.977 2.031 1.913 2.017
-1.310 -1.493 -1.501 -1.540 -1.467 -1.499 -1.505 -1.417 -1.512
GCLK
1.5 V
tsu
th
GCLK
PLL
tsu
th
-1.353 -1.437 -1.529 -1.478 -1.815 -1.449 -1.534 -1.487 -1.860 ns
GCLK
ns
ns
1.550 1.660 1.772 1.709 2.050 1.681 1.787 1.728 2.096
1.806 2.062 2.175 2.190 2.127 2.073 2.186 2.068 2.172
1.2 V
tsu
th
GCLK
PLL
-1.389 -1.594 -1.660 -1.699 -1.626 -1.595 -1.660 -1.572 -1.667 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.284 -1.381 -1.534 -1.440 -1.824 -1.384 -1.535 -1.481 -1.862
1.481 1.603 1.776 1.671 2.059 1.616 1.787 1.720 2.098
1.712 1.946 2.166 2.095 2.010 2.005 2.184 2.066 2.061
-1.298 -1.481 -1.651 -1.608 -1.511 -1.530 -1.658 -1.570 -1.559
-1.284 -1.381 -1.534 -1.440 -1.824 -1.384 -1.535 -1.481 -1.862
1.481 1.603 1.776 1.671 2.059 1.616 1.787 1.720 2.098
1.712 1.946 2.166 2.095 2.010 2.005 2.184 2.066 2.061
-1.298 -1.481 -1.651 -1.608 -1.511 -1.530 -1.658 -1.570 -1.559
-1.315 -1.410 -1.524 -1.472 -1.811 -1.417 -1.530 -1.479 -1.853
1.512 1.631 1.765 1.702 2.042 1.647 1.778 1.719 2.085
1.844 2.087 2.180 2.193 2.129 2.102 2.193 2.076 2.177
-1.427 -1.621 -1.667 -1.704 -1.632 -1.627 -1.670 -1.581 -1.676
-1.315 -1.410 -1.524 -1.472 -1.811 -1.417 -1.530 -1.479 -1.853
1.512 1.631 1.765 1.702 2.042 1.647 1.778 1.719 2.085
1.844 2.087 2.180 2.193 2.129 2.102 2.193 2.076 2.177
-1.427 -1.621 -1.667 -1.704 -1.632 -1.627 -1.670 -1.581 -1.676
GCLK
SSTL-2
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-2
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
SSTL-18
CLASS II
tsu
th
GCLK
PLL
tsu
th
-1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836 ns
GCLK
ns
ns
1.498 1.621 1.747 1.684 2.024 1.636 1.761 1.702 2.068
1.857 2.097 2.198 2.211 2.147 2.113 2.210 2.093 2.194
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693 ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.315 -1.410 -1.524 -1.472 -1.811 -1.417 -1.530 -1.479 -1.853
1.512 1.631 1.765 1.702 2.042 1.647 1.778 1.719 2.085
1.844 2.087 2.180 2.193 2.129 2.102 2.193 2.076 2.177
-1.427 -1.621 -1.667 -1.704 -1.632 -1.627 -1.670 -1.581 -1.676
-1.315 -1.410 -1.524 -1.472 -1.811 -1.417 -1.530 -1.479 -1.853
1.512 1.631 1.765 1.702 2.042 1.647 1.778 1.719 2.085
1.844 2.087 2.180 2.193 2.129 2.102 2.193 2.076 2.177
-1.427 -1.621 -1.667 -1.704 -1.632 -1.627 -1.670 -1.581 -1.676
GCLK
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–261
I4L
Table 1–124. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
1.1V
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
tsu
th
-0.877
1.002
1.150
-0.887
-0.877
1.002
1.150
-0.887
-0.868
0.993
1.159
-0.896
-0.868
0.993
1.159
-0.896
-0.923
1.047
1.016
-0.756
-0.923
1.047
1.016
-0.756
-0.931
1.071
1.165
-0.884
-0.931
1.071
1.165
-0.884
-0.919
1.059
1.177
-0.896
-0.919
1.059
1.177
-0.896
-0.971
1.110
0.989
-0.711
-0.971
1.110
0.989
-0.711
-1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836
1.498 1.621 1.747 1.684 2.024 1.636 1.761 1.702 2.068
1.857 2.097 2.198 2.211 2.147 2.113 2.210 2.093 2.194
-1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693
GCLK
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
-1.300 -1.400 -1.506 -1.454 -1.793 -1.406 -1.513 -1.462 -1.836 ns
GCLK
ns
ns
1.498 1.621 1.747 1.684 2.024 1.636 1.761 1.702 2.068
1.857 2.097 2.198 2.211 2.147 2.113 2.210 2.093 2.194
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.439 -1.631 -1.685 -1.722 -1.650 -1.638 -1.687 -1.598 -1.693 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.291 -1.390 -1.490 -1.438 -1.777 -1.397 -1.497 -1.446 -1.820
1.489 1.611 1.731 1.668 2.008 1.627 1.745 1.686 2.052
1.866 2.107 2.214 2.227 2.163 2.122 2.226 2.109 2.210
-1.448 -1.641 -1.701 -1.738 -1.666 -1.647 -1.703 -1.614 -1.709
-1.291 -1.390 -1.490 -1.438 -1.777 -1.397 -1.497 -1.446 -1.820
1.489 1.611 1.731 1.668 2.008 1.627 1.745 1.686 2.052
1.866 2.107 2.214 2.227 2.163 2.122 2.226 2.109 2.210
-1.448 -1.641 -1.701 -1.738 -1.666 -1.647 -1.703 -1.614 -1.709
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
1.558 1.699 1.981 1.876 2.264 1.719 1.994 1.927 2.305
1.635 1.850 1.961 1.890 1.805 1.902 1.977 1.859 1.854
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
1.558 1.699 1.981 1.876 2.264 1.719 1.994 1.927 2.305
1.635 1.850 1.961 1.890 1.805 1.902 1.977 1.859 1.854
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
GCLK
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V PCI
tsu
th
GCLK
PLL
tsu
th
GCLK
3.0-V
PCI-X
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–262
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–125 specifies EP3SE110 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–125. EP3SE110 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
UnitS
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.367
1.573
3.262
1.494
3.202
1.465
3.181
1.451
3.309
1.511
3.177
1.440
3.135
1.415
3.122
1.408
3.372
1.571
3.268
1.504
3.216
1.466
3.180
1.444
3.653
1.759
3.530
1.670
3.451
1.638
3.426
1.624
3.562
1.692
3.422
1.615
3.383
1.587
3.370
1.580
3.664
1.768
3.542
1.683
3.467
1.646
3.430
1.619
5.079 5.492 6.016 5.868 6.200 5.630 6.154 6.010 6.284
2.224 2.334 2.556 2.558 2.503 2.446 2.669 2.671 2.493
4.912 5.325 5.848 5.700 6.032 5.461 5.981 5.837 6.111
2.121 2.222 2.439 2.441 2.386 2.330 2.549 2.551 2.373
4.832 5.234 5.748 5.600 5.932 5.363 5.876 5.732 6.006
2.054 2.152 2.369 2.371 2.316 2.260 2.482 2.484 2.306
4.776 5.184 5.705 5.557 5.889 5.317 5.835 5.691 5.965
2.033 2.129 2.341 2.343 2.288 2.234 2.449 2.451 2.273
4.970 5.375 5.894 5.746 6.078 5.509 6.029 5.885 6.159
2.151 2.251 2.468 2.470 2.415 2.360 2.581 2.583 2.405
4.769 5.174 5.696 5.548 5.880 5.308 5.828 5.684 5.958
2.029 2.125 2.337 2.339 2.284 2.230 2.444 2.446 2.268
4.727 5.126 5.637 5.489 5.821 5.254 5.765 5.621 5.895
2.000 2.098 2.312 2.314 2.259 2.203 2.419 2.421 2.243
4.706 5.105 5.616 5.468 5.800 5.231 5.741 5.597 5.871
1.992 2.089 2.303 2.305 2.250 2.194 2.410 2.412 2.234
5.120 5.535 6.076 5.928 6.260 5.673 6.203 6.059 6.333
2.258 2.370 2.595 2.597 2.542 2.485 2.711 2.713 2.535
4.952 5.367 5.923 5.775 6.107 5.506 6.030 5.886 6.160
2.154 2.259 2.479 2.481 2.426 2.370 2.593 2.595 2.417
4.863 5.268 5.821 5.673 6.005 5.400 5.917 5.773 6.047
2.086 2.187 2.405 2.407 2.352 2.296 2.517 2.519 2.341
4.793 5.197 5.771 5.623 5.955 5.330 5.847 5.703 5.977
2.051 2.148 2.363 2.365 2.310 2.256 2.473 2.475 2.297
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVTTL
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVTTL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–263
I/O Timing
Table 1–125. EP3SE110 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
UnitS
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.320
1.525
3.194
1.453
3.144
1.429
3.138
1.429
3.439
1.629
3.332
1.546
3.248
1.491
3.220
1.457
3.580
1.708
3.443
1.629
3.393
1.600
3.384
1.600
3.727
1.823
3.602
1.730
3.502
1.686
3.475
1.640
5.010 5.420 5.977 5.829 6.161 5.557 6.083 5.939 6.213
2.188 2.292 2.514 2.516 2.461 2.404 2.629 2.631 2.453
4.815 5.221 5.795 5.647 5.979 5.355 5.872 5.728 6.002
2.065 2.163 2.379 2.381 2.326 2.271 2.490 2.492 2.314
4.761 5.163 5.724 5.576 5.908 5.294 5.807 5.663 5.937
2.025 2.124 2.338 2.340 2.285 2.231 2.448 2.450 2.272
4.733 5.133 5.725 5.577 5.909 5.263 5.776 5.632 5.906
2.017 2.114 2.328 2.330 2.275 2.220 2.436 2.438 2.260
5.264 5.699 6.259 6.111 6.443 5.848 6.408 6.264 6.538
2.395 2.519 2.761 2.763 2.708 2.637 2.884 2.886 2.708
5.091 5.515 6.062 5.914 6.246 5.656 6.198 6.054 6.328
2.276 2.393 2.629 2.631 2.576 2.509 2.748 2.750 2.572
4.962 5.379 5.922 5.774 6.106 5.516 6.048 5.904 6.178
2.184 2.297 2.529 2.531 2.476 2.411 2.646 2.648 2.470
4.894 5.312 5.872 5.724 6.056 5.450 5.984 5.840 6.114
2.150 2.260 2.488 2.490 2.435 2.372 2.602 2.604 2.426
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
2.5 V
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–264
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–125. EP3SE110 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
UnitS
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.616
1.743
3.471
1.645
3.369
1.563
3.286
1.538
3.232
1.467
3.226
1.462
3.534
1.684
3.335
1.552
3.260
1.508
3.254
1.496
3.213
1.461
3.176
1.457
3.909
1.951
3.749
1.840
3.631
1.753
3.577
1.720
3.486
1.656
3.481
1.646
3.858
1.918
3.609
1.737
3.517
1.700
3.510
1.694
3.474
1.643
3.438
1.636
5.558 6.017 6.586 6.438 6.770 6.180 6.743 6.599 6.873
2.590 2.728 2.979 2.981 2.926 2.855 3.110 3.112 2.934
5.342 5.776 6.336 6.188 6.520 5.927 6.486 6.342 6.616
2.438 2.570 2.818 2.820 2.765 2.696 2.944 2.946 2.768
5.141 5.571 6.132 5.984 6.316 5.720 6.267 6.123 6.397
2.311 2.432 2.674 2.676 2.621 2.552 2.797 2.799 2.621
5.045 5.475 6.022 5.874 6.206 5.616 6.152 6.008 6.282
2.250 2.366 2.599 2.601 2.546 2.481 2.716 2.718 2.540
4.918 5.339 5.892 5.744 6.076 5.477 6.008 5.864 6.138
2.162 2.272 2.500 2.502 2.447 2.384 2.615 2.617 2.439
4.905 5.325 5.887 5.739 6.071 5.464 5.996 5.852 6.126
2.156 2.266 2.493 2.495 2.440 2.377 2.608 2.610 2.432
5.473 5.914 6.474 6.326 6.658 6.069 6.630 6.486 6.760
2.528 2.655 2.907 2.909 2.854 2.785 3.043 3.045 2.867
5.100 5.523 6.071 5.923 6.255 5.665 6.205 6.061 6.335
2.285 2.401 2.636 2.638 2.583 2.517 2.757 2.759 2.581
4.986 5.403 5.964 5.816 6.148 5.542 6.078 5.934 6.208
2.204 2.321 2.556 2.558 2.503 2.437 2.674 2.676 2.498
4.977 5.393 5.949 5.801 6.133 5.532 6.065 5.921 6.195
2.198 2.314 2.547 2.549 2.494 2.430 2.666 2.668 2.490
4.892 5.310 5.879 5.731 6.063 5.448 5.981 5.837 6.111
2.150 2.260 2.486 2.488 2.433 2.371 2.601 2.603 2.425
4.864 5.276 5.855 5.707 6.039 5.410 5.938 5.794 6.068
2.130 2.239 2.466 2.468 2.413 2.350 2.580 2.582 2.404
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.8 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–265
I/O Timing
Table 1–125. EP3SE110 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
UnitS
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.498
1.663
3.288
1.541
3.246
1.488
3.197
1.467
3.233
1.481
3.237
1.484
3.205
1.465
3.189
1.460
3.255
1.499
3.228
1.480
3.225
1.481
3.195
1.464
3.188
1.460
3.780
1.861
3.573
1.726
3.502
1.685
3.462
1.651
3.484
1.659
3.489
1.662
3.457
1.642
3.437
1.635
3.508
1.679
3.480
1.658
3.479
1.661
3.447
1.641
3.440
1.637
5.386 5.818 6.398 6.250 6.582 5.980 6.542 6.398 6.672
2.482 2.609 2.850 2.852 2.797 2.732 2.977 2.979 2.801
5.057 5.484 6.041 5.893 6.225 5.626 6.161 6.017 6.291
2.263 2.378 2.610 2.612 2.557 2.493 2.729 2.731 2.553
4.964 5.378 5.940 5.792 6.124 5.515 6.045 5.901 6.175
2.187 2.301 2.536 2.538 2.483 2.418 2.656 2.658 2.480
4.879 5.293 5.890 5.742 6.074 5.431 5.964 5.820 6.094
2.148 2.258 2.486 2.488 2.433 2.369 2.599 2.601 2.423
4.908 5.322 5.903 5.755 6.087 5.453 5.979 5.835 6.109
2.156 2.266 2.494 2.496 2.441 2.375 2.604 2.606 2.428
4.914 5.327 5.911 5.763 6.095 5.459 5.985 5.841 6.115
2.160 2.270 2.498 2.500 2.445 2.378 2.608 2.610 2.432
4.880 5.293 5.869 5.721 6.053 5.424 5.951 5.807 6.081
2.139 2.248 2.476 2.478 2.423 2.357 2.586 2.588 2.410
4.853 5.264 5.850 5.702 6.034 5.395 5.920 5.776 6.050
2.124 2.232 2.459 2.461 2.406 2.340 2.569 2.571 2.393
4.935 5.348 5.933 5.785 6.117 5.480 6.006 5.862 6.136
2.179 2.289 2.517 2.519 2.464 2.398 2.628 2.630 2.452
4.905 5.317 5.898 5.750 6.082 5.449 5.975 5.831 6.105
2.157 2.267 2.495 2.497 2.442 2.376 2.605 2.607 2.429
4.912 5.326 5.915 5.767 6.099 5.458 5.986 5.842 6.116
2.165 2.276 2.505 2.507 2.452 2.386 2.616 2.618 2.440
4.876 5.290 5.875 5.727 6.059 5.422 5.948 5.804 6.078
2.141 2.251 2.480 2.482 2.427 2.360 2.591 2.593 2.415
4.869 5.283 5.867 5.719 6.051 5.415 5.942 5.798 6.072
2.137 2.247 2.475 2.477 2.422 2.356 2.587 2.589 2.411
2mA
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
1.2 V
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS I
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–266
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–125. EP3SE110 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
UnitS
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.187
1.461
3.174
1.460
3.241
1.490
3.212
1.475
3.188
1.462
3.181
1.463
3.174
1.458
3.218
1.476
3.211
1.475
3.436
1.636
3.423
1.636
3.495
1.670
3.466
1.654
3.440
1.639
3.433
1.640
3.425
1.635
3.467
1.652
3.462
1.652
4.850 5.261 5.849 5.701 6.033 5.392 5.916 5.772 6.046
2.124 2.233 2.459 2.461 2.406 2.341 2.569 2.571 2.393
4.846 5.259 5.845 5.697 6.029 5.390 5.917 5.773 6.047
2.132 2.243 2.471 2.473 2.418 2.351 2.582 2.584 2.406
4.921 5.333 5.914 5.766 6.098 5.465 5.990 5.846 6.120
2.172 2.282 2.509 2.511 2.456 2.391 2.620 2.622 2.444
4.898 5.311 5.898 5.750 6.082 5.444 5.970 5.826 6.100
2.158 2.269 2.497 2.499 2.444 2.378 2.609 2.611 2.433
4.868 5.281 5.870 5.722 6.054 5.414 5.940 5.796 6.070
2.138 2.248 2.477 2.479 2.424 2.358 2.588 2.590 2.412
4.861 5.275 5.875 5.727 6.059 5.408 5.935 5.791 6.065
2.139 2.250 2.480 2.482 2.427 2.360 2.591 2.593 2.415
4.851 5.265 5.864 5.716 6.048 5.397 5.924 5.780 6.054
2.132 2.243 2.472 2.474 2.419 2.352 2.583 2.585 2.407
4.878 5.288 5.872 5.724 6.056 5.418 5.942 5.798 6.072
2.140 2.248 2.474 2.476 2.421 2.356 2.584 2.586 2.408
4.880 5.292 5.887 5.739 6.071 5.423 5.948 5.804 6.078
2.144 2.253 2.480 2.482 2.427 2.361 2.590 2.592 2.414
8mA
GCLK
tco
PLL
SSTL-18
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-15
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
SSTL-15
CLASS II
GCLK tco
16mA
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–267
I/O Timing
Table 1–125. EP3SE110 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
UnitS
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.189
1.462
3.180
1.458
3.178
1.460
3.171
1.459
3.215
1.477
3.204
1.472
3.202
1.472
3.185
1.462
3.182
1.464
3.218
1.486
3.201
1.475
3.192
1.474
3.439
1.638
3.429
1.633
3.428
1.636
3.419
1.634
3.465
1.653
3.454
1.649
3.453
1.648
3.435
1.638
3.432
1.640
3.472
1.665
3.453
1.653
3.444
1.651
4.855 5.267 5.860 5.712 6.044 5.398 5.923 5.779 6.053
2.128 2.237 2.464 2.466 2.411 2.345 2.574 2.576 2.398
4.844 5.256 5.845 5.697 6.029 5.387 5.912 5.768 6.042
2.122 2.231 2.458 2.460 2.405 2.339 2.568 2.570 2.392
4.847 5.259 5.862 5.714 6.046 5.390 5.916 5.772 6.046
2.127 2.236 2.464 2.466 2.411 2.345 2.575 2.577 2.399
4.829 5.240 5.835 5.687 6.019 5.370 5.894 5.750 6.024
2.120 2.229 2.456 2.458 2.403 2.337 2.566 2.568 2.390
4.877 5.287 5.872 5.724 6.056 5.418 5.941 5.797 6.071
2.142 2.250 2.477 2.479 2.424 2.359 2.587 2.589 2.411
4.871 5.282 5.875 5.727 6.059 5.413 5.937 5.793 6.067
2.140 2.249 2.476 2.478 2.423 2.358 2.586 2.588 2.410
4.871 5.283 5.876 5.728 6.060 5.414 5.938 5.794 6.068
2.141 2.250 2.477 2.479 2.424 2.359 2.587 2.589 2.411
4.852 5.263 5.857 5.709 6.041 5.394 5.919 5.775 6.049
2.129 2.238 2.465 2.467 2.412 2.346 2.575 2.577 2.399
4.852 5.265 5.867 5.719 6.051 5.396 5.922 5.778 6.052
2.134 2.245 2.473 2.475 2.420 2.353 2.584 2.586 2.408
4.893 5.304 5.897 5.749 6.081 5.437 5.960 5.816 6.090
2.162 2.272 2.499 2.501 2.446 2.381 2.611 2.613 2.435
4.875 5.287 5.883 5.735 6.067 5.419 5.944 5.800 6.074
2.150 2.260 2.488 2.490 2.435 2.369 2.599 2.601 2.423
4.866 5.279 5.882 5.734 6.066 5.411 5.937 5.793 6.067
2.148 2.258 2.486 2.488 2.433 2.368 2.598 2.600 2.422
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS II
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–268
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–125. EP3SE110 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
UnitS
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.186
1.471
3.181
1.467
3.259
1.544
3.259
1.544
3.367
1.573
3.262
1.494
3.202
1.465
3.181
1.451
3.437
1.649
3.432
1.645
3.507
1.720
3.507
1.720
3.653
1.759
3.530
1.670
3.451
1.638
3.426
1.624
4.861 5.274 5.880 5.732 6.064 5.406 5.933 5.789 6.063
2.147 2.258 2.486 2.488 2.433 2.367 2.598 2.600 2.422
4.853 5.267 5.870 5.722 6.054 5.398 5.925 5.781 6.055
2.141 2.251 2.479 2.481 2.426 2.360 2.591 2.593 2.415
4.867 5.270 5.839 5.691 6.023 5.401 5.916 5.772 6.046
2.158 2.259 2.476 2.478 2.423 2.368 2.588 2.590 2.412
4.867 5.270 5.839 5.691 6.023 5.401 5.916 5.772 6.046
2.158 2.259 2.476 2.478 2.423 2.368 2.588 2.590 2.412
5.079 5.492 6.016 5.868 6.200 5.630 6.154 6.010 6.284
2.224 2.334 2.556 2.558 2.503 2.446 2.669 2.671 2.493
4.912 5.325 5.848 5.700 6.032 5.461 5.981 5.837 6.111
2.121 2.222 2.439 2.441 2.386 2.330 2.549 2.551 2.373
4.832 5.234 5.748 5.600 5.932 5.363 5.876 5.732 6.006
2.054 2.152 2.369 2.371 2.316 2.260 2.482 2.484 2.306
4.776 5.184 5.705 5.557 5.889 5.317 5.835 5.691 5.965
2.033 2.129 2.341 2.343 2.288 2.234 2.449 2.451 2.273
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
Table 1–126 specifies EP3SE110 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–126. EP3SE110 Row Pins output Timing Parameters (Part 1 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
3.208
1.452
3.142
1.359
3.063
1.260
3.456
1.625
3.385
1.554
3.296
1.465
4.797 5.180 5.703 5.543 5.850 5.304 5.827 5.696 5.930
2.008 2.086 2.326 2.346 2.347 2.239 2.435 2.455 2.342
4.687 5.069 5.589 5.429 5.736 5.191 5.712 5.581 5.815
1.898 1.975 2.181 2.201 2.202 2.098 2.286 2.306 2.193
4.581 4.969 5.493 5.333 5.640 5.092 5.612 5.481 5.715
1.792 1.875 2.053 2.073 2.074 1.971 2.154 2.174 2.061
4mA
8mA
12mA
GCLK
PLL
3.3-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–269
I4L
Table 1–126. EP3SE110 Row Pins output Timing Parameters (Part 2 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.210
1.462
3.067
1.264
3.169
1.406
3.068
1.281
3.031
1.242
3.090
1.320
3.018
1.220
3.195
1.432
3.110
1.322
3.053
1.276
3.458
1.663
3.233
1.438
3.168
1.373
3.108
1.313
3.463
1.632
3.300
1.469
3.417
1.586
3.305
1.474
3.267
1.436
3.329
1.498
3.251
1.420
3.454
1.623
3.351
1.520
3.307
1.476
3.730
1.874
3.528
1.672
3.426
1.570
3.352
1.496
4.801 5.186 5.712 5.552 5.859 5.312 5.839 5.708 5.942
2.012 2.092 2.330 2.350 2.351 2.245 2.439 2.459 2.346
4.592 4.984 5.503 5.343 5.650 5.104 5.621 5.490 5.724
1.803 1.890 2.059 2.079 2.080 1.977 2.161 2.181 2.068
4.764 5.149 5.669 5.509 5.816 5.272 5.793 5.662 5.896
1.975 2.055 2.282 2.302 2.303 2.196 2.393 2.413 2.300
4.627 5.007 5.524 5.364 5.671 5.130 5.648 5.516 5.750
1.838 1.913 2.118 2.138 2.139 2.034 2.229 2.248 2.135
4.567 4.942 5.454 5.294 5.601 5.062 5.574 5.443 5.677
1.778 1.848 2.030 2.050 2.051 1.948 2.136 2.155 2.042
4.662 5.042 5.560 5.400 5.707 5.163 5.684 5.552 5.786
1.873 1.948 2.172 2.192 2.193 2.088 2.282 2.301 2.188
4.539 4.913 5.426 5.266 5.573 5.032 5.546 5.414 5.648
1.750 1.819 1.991 2.011 2.012 1.908 2.096 2.115 2.002
4.872 5.275 5.814 5.654 5.961 5.404 5.945 5.814 6.048
2.083 2.181 2.454 2.474 2.475 2.356 2.572 2.591 2.478
4.748 5.140 5.672 5.512 5.819 5.267 5.801 5.669 5.903
1.959 2.046 2.284 2.304 2.305 2.189 2.398 2.417 2.304
4.664 5.054 5.581 5.421 5.728 5.178 5.706 5.575 5.809
1.875 1.960 2.158 2.178 2.179 2.066 2.268 2.287 2.174
5.334 5.790 6.350 6.220 6.500 5.931 6.493 6.365 6.600
2.520 2.669 2.929 2.949 2.954 2.792 3.056 3.075 2.967
5.007 5.421 5.945 5.815 6.095 5.566 6.087 5.958 6.193
2.193 2.300 2.524 2.544 2.549 2.427 2.650 2.668 2.560
4.854 5.271 5.786 5.656 5.936 5.398 5.914 5.786 6.021
2.040 2.150 2.365 2.385 2.390 2.259 2.477 2.496 2.388
4.777 5.177 5.691 5.559 5.839 5.303 5.820 5.692 5.927
1.963 2.056 2.268 2.288 2.293 2.164 2.383 2.402 2.294
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
2mA
4mA
6mA
8mA
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
1.8 V
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–270
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–126. EP3SE110 Row Pins output Timing Parameters (Part 3 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.369
1.574
3.127
1.332
3.100
1.305
3.091
1.296
3.312
1.517
3.132
1.337
3.057
1.261
3.052
1.249
3.043
1.234
3.069
1.274
3.054
1.259
3.043
1.248
3.030
1.228
3.030
1.228
3.648
1.792
3.390
1.534
3.343
1.487
3.334
1.478
3.573
1.717
3.384
1.528
3.295
1.464
3.291
1.460
3.280
1.449
3.308
1.452
3.294
1.438
3.282
1.426
3.267
1.404
3.266
1.403
5.244 5.703 6.278 6.148 6.428 5.838 6.417 6.289 6.524
2.430 2.582 2.857 2.877 2.882 2.699 2.980 2.999 2.891
4.839 5.266 5.787 5.657 5.937 5.392 5.913 5.785 6.020
2.025 2.145 2.366 2.386 2.391 2.253 2.476 2.495 2.387
4.766 5.170 5.691 5.551 5.834 5.294 5.816 5.685 5.916
1.952 2.049 2.260 2.280 2.285 2.155 2.371 2.390 2.282
4.744 5.152 5.672 5.532 5.815 5.276 5.797 5.666 5.897
1.930 2.031 2.241 2.261 2.266 2.137 2.349 2.368 2.260
5.154 5.617 6.203 6.073 6.353 5.750 6.333 6.205 6.440
2.340 2.496 2.782 2.802 2.807 2.611 2.896 2.915 2.807
4.861 5.294 5.828 5.698 5.978 5.417 5.955 5.827 6.062
2.047 2.173 2.407 2.427 2.432 2.278 2.518 2.537 2.429
4.657 5.045 5.571 5.411 5.718 5.165 5.692 5.561 5.795
1.868 1.951 2.126 2.146 2.147 2.033 2.230 2.250 2.137
4.654 5.043 5.569 5.409 5.716 5.164 5.691 5.560 5.794
1.865 1.949 2.118 2.138 2.139 2.025 2.223 2.243 2.130
4.639 5.027 5.552 5.392 5.699 5.147 5.673 5.542 5.776
1.850 1.933 2.097 2.111 2.112 1.999 2.202 2.221 2.103
4.672 5.065 5.586 5.433 5.729 5.184 5.707 5.576 5.807
1.858 1.944 2.142 2.162 2.167 2.045 2.246 2.265 2.157
4.669 5.063 5.585 5.431 5.728 5.182 5.705 5.574 5.805
1.855 1.942 2.140 2.160 2.165 2.043 2.244 2.263 2.155
4.652 5.046 5.575 5.414 5.718 5.165 5.696 5.565 5.796
1.838 1.925 2.123 2.143 2.148 2.026 2.228 2.247 2.139
4.636 5.030 5.562 5.399 5.705 5.150 5.684 5.553 5.784
1.822 1.909 2.108 2.128 2.133 2.011 2.213 2.232 2.124
4.635 5.029 5.562 5.398 5.705 5.149 5.684 5.553 5.784
1.821 1.908 2.107 2.127 2.132 2.010 2.213 2.232 2.123
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
4mA
6mA
8mA
10mA
12mA
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-2
CLASS I
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–271
I4L
Table 1–126. EP3SE110 Row Pins output Timing Parameters (Part 4 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.038
1.236
3.039
1.237
3.065
1.270
3.046
1.247
3.035
1.233
3.045
1.249
3.038
1.237
3.029
1.227
3.032
1.230
3.028
1.226
3.036
1.234
3.051
1.256
3.045
1.244
3.041
1.240
3.273
1.411
3.276
1.413
3.304
1.448
3.283
1.426
3.271
1.409
3.280
1.424
3.273
1.412
3.265
1.402
3.267
1.404
3.264
1.401
3.272
1.409
3.287
1.431
3.280
1.421
3.276
1.416
4.633 5.025 5.557 5.392 5.700 5.144 5.678 5.547 5.778
1.819 1.904 2.102 2.121 2.126 2.005 2.207 2.226 2.116
4.639 5.031 5.567 5.400 5.710 5.150 5.689 5.558 5.789
1.818 1.905 2.112 2.123 2.128 2.007 2.218 2.237 2.120
4.683 5.079 5.599 5.450 5.742 5.197 5.719 5.588 5.819
1.869 1.958 2.159 2.179 2.184 2.058 2.262 2.281 2.173
4.665 5.062 5.589 5.433 5.732 5.181 5.710 5.579 5.810
1.851 1.941 2.142 2.162 2.167 2.042 2.246 2.265 2.157
4.648 5.044 5.576 5.415 5.719 5.163 5.697 5.566 5.797
1.834 1.923 2.124 2.144 2.149 2.024 2.229 2.248 2.140
4.639 5.030 5.555 5.395 5.698 5.148 5.675 5.544 5.775
1.825 1.909 2.104 2.124 2.129 2.009 2.208 2.227 2.119
4.630 5.022 5.554 5.387 5.697 5.140 5.675 5.544 5.775
1.816 1.901 2.099 2.116 2.121 2.001 2.204 2.223 2.112
4.623 5.013 5.547 5.380 5.690 5.132 5.668 5.537 5.768
1.807 1.892 2.092 2.108 2.113 1.993 2.197 2.216 2.104
4.626 5.016 5.551 5.384 5.694 5.135 5.671 5.540 5.771
1.810 1.895 2.096 2.111 2.116 1.996 2.200 2.219 2.107
4.628 5.019 5.554 5.387 5.697 5.138 5.676 5.545 5.776
1.808 1.894 2.099 2.111 2.116 1.996 2.205 2.224 2.108
4.626 5.016 5.550 5.383 5.693 5.134 5.670 5.539 5.770
1.805 1.890 2.095 2.106 2.107 1.991 2.199 2.218 2.097
4.650 5.043 5.566 5.410 5.709 5.160 5.686 5.555 5.786
1.836 1.922 2.119 2.139 2.144 2.021 2.222 2.241 2.133
4.646 5.039 5.568 5.406 5.711 5.157 5.689 5.558 5.789
1.832 1.918 2.115 2.135 2.140 2.018 2.219 2.238 2.130
4.640 5.033 5.563 5.400 5.706 5.151 5.683 5.552 5.783
1.826 1.912 2.109 2.129 2.134 2.012 2.213 2.232 2.124
8mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5-V
HSTL
CLASS I
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–272
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–126. EP3SE110 Row Pins output Timing Parameters (Part 5 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.053
1.255
3.044
1.243
3.043
1.241
3.163
1.354
3.163
1.354
3.287
1.430
3.279
1.418
3.279
1.416
3.401
1.570
3.401
1.570
4.661 5.057 5.585 5.428 5.728 5.174 5.705 5.574 5.805
1.847 1.936 2.137 2.157 2.162 2.035 2.239 2.258 2.150
4.650 5.045 5.576 5.416 5.719 5.163 5.696 5.565 5.796
1.836 1.924 2.125 2.145 2.150 2.024 2.228 2.247 2.139
4.654 5.050 5.585 5.422 5.728 5.169 5.706 5.575 5.806
1.840 1.929 2.131 2.151 2.156 2.030 2.235 2.254 2.146
4.709 5.091 5.611 5.451 5.758 5.213 5.734 5.603 5.837
1.920 1.997 2.156 2.167 2.156 2.061 2.263 2.282 2.149
4.709 5.091 5.611 5.451 5.758 5.213 5.734 5.603 5.837
1.920 1.997 2.156 2.167 2.156 2.061 2.263 2.282 2.149
4mA
6mA
8mA
—
GCLK
PLL
1.2-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
Table 1–127 through Table 1–130 show the maximum I/O timing parameters for
EP3SE110 devices for differential I/O standards.
Table 1–127 specifies EP3SE110 column pins input timing parameters for differential
I/O standards.
Table 1–127. EP3SE110 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.997
1.133
0.960
-0.691
-0.997
1.133
0.960
-0.691
-0.997
1.133
0.960
-0.691
-0.813
0.942
1.144
-0.882
-1.029
1.184
0.994
-0.701
-1.029
1.184
0.994
-0.701
-1.029
1.184
0.994
-0.701
-0.852
0.999
1.171
-0.886
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
1.415 1.436 1.618 1.551 1.927 1.411 1.858 1.524 1.966
1.879 2.224 2.401 2.288 2.194 2.277 2.567 2.345 2.245
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683
1.415 1.436 1.618 1.551 1.927 1.411 1.858 1.524 1.966
1.879 2.224 2.401 2.288 2.194 2.277 2.567 2.345 2.245
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
MINI-LVDS
RSDS
GCLK
tsu
th
GCLK
PLL
tsu
th
-1.181 -1.169 -1.324 -1.269 -1.645 -1.133 -1.542 -1.230 -1.683 ns
ns
ns
1.415 1.436 1.618 1.551 1.927 1.411 1.858 1.524 1.966
1.879 2.224 2.401 2.288 2.194 2.277 2.567 2.345 2.245
tsu
th
GCLK
GCLK
-1.428 -1.714 -1.834 -1.749 -1.648 -1.756 -1.968 -1.795 -1.697 ns
ns
ns
ns
ns
tsu
th
-1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837
1.460 1.595 1.731 1.659 2.031 1.604 1.739 1.674 2.075
1.802 2.025 2.242 2.134 2.045 2.042 2.260 2.147 2.091
-1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588
DIFFERENTIAL
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–273
I/O Timing
Table 1–127. EP3SE110 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
tsu
th
-0.813
0.942
1.144
-0.882
-0.821
0.950
1.136
-0.874
-0.821
0.950
1.136
-0.874
-0.833
0.962
1.124
-0.862
-0.833
0.962
1.124
-0.862
-0.821
0.950
1.136
-0.874
-0.821
0.950
1.136
-0.874
-0.833
0.962
1.124
-0.862
-0.833
0.962
1.124
-0.862
-0.852
0.999
1.171
-0.886
-0.864
1.011
1.159
-0.874
-0.864
1.011
1.159
-0.874
-0.875
1.022
1.148
-0.863
-0.875
1.022
1.148
-0.863
-0.864
1.011
1.159
-0.874
-0.864
1.011
1.159
-0.874
-0.875
1.022
1.148
-0.863
-0.875
1.022
1.148
-0.863
-1.258 -1.368 -1.483 -1.423 -1.794 -1.368 -1.482 -1.428 -1.837
1.460 1.595 1.731 1.659 2.031 1.604 1.739 1.674 2.075
1.802 2.025 2.242 2.134 2.045 2.042 2.260 2.147 2.091
-1.383 -1.555 -1.721 -1.641 -1.544 -1.563 -1.729 -1.645 -1.588
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
-1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 ns
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
ns
ns
1.470 1.606 1.747 1.675 2.047 1.615 1.754 1.689 2.090
1.792 2.014 2.226 2.118 2.029 2.031 2.245 2.132 2.076
tsu
th
GCLK
PLL
-1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852
1.470 1.606 1.747 1.675 2.047 1.615 1.754 1.689 2.090
1.792 2.014 2.226 2.118 2.029 2.031 2.245 2.132 2.076
-1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573
-1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870
1.480 1.617 1.766 1.694 2.066 1.626 1.772 1.707 2.108
1.783 2.003 2.207 2.099 2.010 2.020 2.227 2.114 2.058
-1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555
-1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870
1.480 1.617 1.766 1.694 2.066 1.626 1.772 1.707 2.108
1.783 2.003 2.207 2.099 2.010 2.020 2.227 2.114 2.058
-1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555
-1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852
1.470 1.606 1.747 1.675 2.047 1.615 1.754 1.689 2.090
1.792 2.014 2.226 2.118 2.029 2.031 2.245 2.132 2.076
-1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
-1.268 -1.379 -1.499 -1.439 -1.810 -1.379 -1.497 -1.443 -1.852 ns
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
ns
ns
1.470 1.606 1.747 1.675 2.047 1.615 1.754 1.689 2.090
1.792 2.014 2.226 2.118 2.029 2.031 2.245 2.132 2.076
tsu
th
GCLK
PLL
-1.373 -1.544 -1.705 -1.625 -1.528 -1.552 -1.714 -1.630 -1.573 ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870
1.480 1.617 1.766 1.694 2.066 1.626 1.772 1.707 2.108
1.783 2.003 2.207 2.099 2.010 2.020 2.227 2.114 2.058
-1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555
-1.277 -1.390 -1.518 -1.458 -1.829 -1.390 -1.515 -1.461 -1.870
1.480 1.617 1.766 1.694 2.066 1.626 1.772 1.707 2.108
1.783 2.003 2.207 2.099 2.010 2.020 2.227 2.114 2.058
-1.363 -1.533 -1.686 -1.606 -1.509 -1.541 -1.696 -1.612 -1.555
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–274
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–127. EP3SE110 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
tsu
th
-0.840
0.969
1.117
-0.855
-0.840
0.969
1.117
-0.855
-0.881
1.028
1.142
-0.857
-0.881
1.028
1.142
-0.857
-1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866
1.493 1.625 1.769 1.697 2.070 1.633 1.772 1.706 2.109
1.771 1.998 2.207 2.097 2.011 2.016 2.232 2.116 2.062
-1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
tsu
th
GCLK
PLL
tsu
th
-1.289 -1.395 -1.518 -1.460 -1.828 -1.394 -1.510 -1.459 -1.866 ns
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
ns
ns
1.493 1.625 1.769 1.697 2.070 1.633 1.772 1.706 2.109
1.771 1.998 2.207 2.097 2.011 2.016 2.232 2.116 2.062
tsu
th
GCLK
PLL
-1.350 -1.525 -1.683 -1.603 -1.505 -1.534 -1.696 -1.613 -1.554 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–275
I/O Timing
Table 1–128 specifies EP3SE110 row pins input timing parameters for differential I/O
standards
Table 1–128. EP3SE110 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu
th
-0.944
1.077
0.961
-0.691
-0.944
1.077
0.961
-0.691
-0.944
1.077
0.961
-0.691
-0.749
0.875
1.156
-0.893
-0.749
0.875
1.156
-0.893
-0.758
0.884
1.147
-0.884
-0.758
0.884
1.147
-0.884
-0.772
0.898
1.133
-0.870
-0.979
1.130
0.989
-0.700
-0.979
1.130
0.989
-0.700
-0.979
1.130
0.989
-0.700
-0.794
0.936
1.174
-0.894
-0.794
0.936
1.174
-0.894
-0.806
0.948
1.162
-0.882
-0.806
0.948
1.162
-0.882
-0.818
0.960
1.150
-0.870
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
-1.054 -1.015 -1.154 -1.107 -1.454 -0.975 -1.107 -1.061 -1.493
1.288 1.285 1.447 1.389 1.737 1.257 1.412 1.355 1.777
1.951 2.328 2.533 2.408 2.342 2.387 2.599 2.472 2.394
-1.502 -1.818 -1.968 -1.871 -1.796 -1.862 -2.019 -1.921 -1.844
-1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677
1.345 1.468 1.587 1.524 1.867 1.479 1.597 1.535 1.912
1.864 2.104 2.344 2.224 2.163 2.120 2.362 2.240 2.210
-1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709
-1.145 -1.244 -1.343 -1.291 -1.633 -1.246 -1.344 -1.293 -1.677
1.345 1.468 1.587 1.524 1.867 1.479 1.597 1.535 1.912
1.864 2.104 2.344 2.224 2.163 2.120 2.362 2.240 2.210
-1.447 -1.639 -1.828 -1.736 -1.666 -1.644 -1.834 -1.741 -1.709
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676
GCLK
LVDS
tsu
th
GCLK
PLL
tsu
th
GCLK
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
tsu
th
GCLK
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS I
tsu
th
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–276
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–128. EP3SE110 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
GCLK tsu
th
-0.772
0.898
-0.818
0.960
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945
DIFFERENTIAL
1.8-V
HSTL CLASS II
GCLK
tsu
ns
1.133
1.150
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177
PLL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th
-0.870
-0.758
0.884
1.147
-0.884
-0.758
0.884
1.147
-0.884
-0.772
0.898
1.133
-0.870
-0.772
0.898
1.133
-0.870
-0.781
0.907
1.124
-0.861
-0.781
0.907
1.124
-0.861
-0.870
-0.806
0.948
1.162
-0.882
-0.806
0.948
1.162
-0.882
-0.818
0.960
1.150
-0.870
-0.818
0.960
1.150
-0.870
-0.827
0.969
1.141
-0.861
-0.827
0.969
1.141
-0.861
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676
-1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712
1.379 1.502 1.631 1.568 1.912 1.509 1.636 1.573 1.952
1.827 2.068 2.299 2.178 2.118 2.089 2.323 2.199 2.170
-1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665
-1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712
1.379 1.502 1.631 1.568 1.912 1.509 1.636 1.573 1.952
1.827 2.068 2.299 2.178 2.118 2.089 2.323 2.199 2.170
-1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665
tsu
GCLK
th
DIFFERENTIAL
1.5-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS II
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS I
tsu
th
GCLK
PLL
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS II
tsu
th
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–277
I/O Timing
Table 1–129 specifies EP3SE110 Column Pins Output Timing parameters for
differential I/O standards.
Table 1–129. EP3SE110 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.152
1.328
3.148
1.324
3.152
1.328
3.148
1.324
3.152
1.328
3.148
1.324
3.179
1.355
3.169
1.345
3.169
1.345
3.162
1.338
3.161
1.337
3.183
1.359
3.387
1.502
3.390
1.505
3.387
1.502
3.390
1.505
3.387
1.502
3.390
1.505
3.420
1.535
3.410
1.525
3.410
1.525
3.404
1.519
3.402
1.517
3.424
1.539
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
LVDS_E_1R
LVDS_E_3R
—
—
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns
ns
GCLK
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns
ns
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
4.757 5.155 5.666 5.526 5.826 5.278 5.789 5.650 5.899
1.913 2.006 2.214 2.225 2.251 2.110 2.321 2.331 2.237 ns
ns
RSDS_E_1R
RSDS_E_3R
—
GCLK
PLL
GCLK
4.804 5.210 5.728 5.588 5.888 5.337 5.855 5.716 5.965
1.960 2.061 2.276 2.287 2.313 2.169 2.387 2.397 2.303 ns
ns
—
GCLK
PLL
GCLK
4.828 5.233 5.750 5.610 5.910 5.358 5.875 5.736 5.985
1.984 2.084 2.298 2.309 2.335 2.190 2.407 2.417 2.323 ns
ns
4mA
6mA
8mA
GCLK
PLL
GCLK
4.818 5.222 5.740 5.600 5.900 5.347 5.865 5.726 5.975
1.974 2.073 2.288 2.299 2.325 2.179 2.397 2.407 2.313 ns
ns
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
4.821 5.226 5.744 5.604 5.904 5.352 5.870 5.731 5.980
1.977 2.077 2.292 2.303 2.329 2.184 2.402 2.412 2.318 ns
ns
GCLK
PLL
GCLK
4.814 5.220 5.738 5.598 5.898 5.345 5.864 5.725 5.974
1.970 2.071 2.286 2.297 2.323 2.177 2.396 2.406 2.312 ns
10m
A
GCLK
PLL
GCLK
ns
ns
ns
ns
4.811 5.217 5.735 5.595 5.895 5.342 5.860 5.721 5.970
1.967 2.068 2.283 2.294 2.320 2.174 2.392 2.402 2.308
4.832 5.237 5.754 5.614 5.914 5.362 5.880 5.741 5.990
1.988 2.088 2.302 2.313 2.339 2.194 2.412 2.422 2.328
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
16m
A
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–278
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–129. EP3SE110 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.173
1.349
3.168
1.344
3.166
1.342
3.158
1.334
3.159
1.335
3.158
1.334
3.170
1.346
3.166
1.342
3.156
1.332
3.154
1.330
3.154
1.330
3.158
1.334
3.413
1.528
3.409
1.524
3.407
1.522
3.398
1.513
3.400
1.515
3.397
1.512
3.410
1.525
3.407
1.522
3.396
1.511
3.394
1.509
3.395
1.510
3.398
1.513
4.811 5.214 5.729 5.589 5.889 5.338 5.853 5.714 5.963
1.967 2.065 2.277 2.288 2.314 2.170 2.385 2.395 2.301
4.811 5.214 5.730 5.590 5.890 5.339 5.855 5.716 5.965
1.967 2.065 2.278 2.289 2.315 2.171 2.387 2.397 2.303
4.810 5.213 5.728 5.588 5.888 5.338 5.854 5.715 5.964
1.966 2.064 2.276 2.287 2.313 2.170 2.386 2.396 2.302
4.800 5.203 5.719 5.579 5.879 5.328 5.844 5.705 5.954
1.956 2.054 2.267 2.278 2.304 2.160 2.376 2.386 2.292
4.806 5.210 5.727 5.587 5.887 5.336 5.853 5.714 5.963
1.962 2.061 2.275 2.286 2.312 2.168 2.385 2.395 2.301
4.789 5.191 5.705 5.565 5.865 5.315 5.829 5.690 5.939
1.945 2.042 2.253 2.264 2.290 2.147 2.361 2.371 2.277
4.807 5.209 5.723 5.583 5.883 5.334 5.848 5.709 5.958
1.963 2.060 2.271 2.282 2.308 2.166 2.380 2.390 2.296
4.808 5.211 5.727 5.587 5.887 5.336 5.852 5.713 5.962
1.964 2.062 2.275 2.286 2.312 2.168 2.384 2.394 2.300
4.797 5.200 5.715 5.575 5.875 5.325 5.840 5.701 5.950
1.953 2.051 2.263 2.274 2.300 2.157 2.372 2.382 2.288
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
4.795 5.197 5.713 5.573 5.873 5.323 5.838 5.699 5.948 ns
ns
10m
A
GCLK
PLL
1.951 2.048 2.261 2.272 2.298 2.155 2.370 2.380 2.286
4.798 5.202 5.718 5.578 5.878 5.327 5.844 5.705 5.954 ns
ns
GCLK
12m
A
GCLK
PLL
1.954 2.053 2.266 2.277 2.303 2.159 2.376 2.386 2.292
4.795 5.197 5.712 5.572 5.872 5.322 5.837 5.698 5.947 ns
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
16m
A
GCLK
PLL
ns
1.951 2.048 2.260 2.271 2.297 2.154 2.369 2.379 2.285
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–279
I/O Timing
Table 1–129. EP3SE110 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.184
1.360
3.170
1.346
3.158
1.334
3.158
1.334
3.154
1.330
3.158
1.334
3.159
1.335
3.187
1.363
3.176
1.352
3.171
1.347
3.157
1.333
3.155
1.331
3.159
1.335
3.159
1.335
3.427
1.542
3.413
1.528
3.400
1.515
3.400
1.515
3.396
1.511
3.398
1.513
3.400
1.515
3.430
1.545
3.418
1.533
3.414
1.529
3.399
1.514
3.397
1.512
3.399
1.514
3.400
1.515
4.840 5.245 5.762 5.622 5.922 5.370 5.887 5.748 5.997
1.996 2.096 2.310 2.321 2.347 2.202 2.419 2.429 2.335
4.828 5.234 5.752 5.612 5.912 5.360 5.878 5.739 5.988
1.984 2.085 2.300 2.311 2.337 2.192 2.410 2.420 2.326
4.811 5.216 5.734 5.594 5.894 5.342 5.860 5.721 5.970
1.967 2.067 2.282 2.293 2.319 2.174 2.392 2.402 2.308
4.814 5.220 5.738 5.598 5.898 5.346 5.865 5.726 5.975
1.970 2.071 2.286 2.297 2.323 2.178 2.397 2.407 2.313
4.807 5.212 5.731 5.591 5.891 5.339 5.857 5.718 5.967
1.963 2.063 2.279 2.290 2.316 2.171 2.389 2.399 2.305
4.800 5.203 5.719 5.579 5.879 5.328 5.844 5.705 5.954
1.956 2.054 2.267 2.278 2.304 2.160 2.376 2.386 2.292
4.808 5.213 5.730 5.590 5.890 5.338 5.856 5.717 5.966
1.964 2.064 2.278 2.289 2.315 2.170 2.388 2.398 2.304
4.839 5.243 5.760 5.620 5.920 5.369 5.885 5.746 5.995
1.995 2.094 2.308 2.319 2.345 2.201 2.417 2.427 2.333
4.827 5.231 5.748 5.608 5.908 5.357 5.873 5.734 5.983
1.983 2.082 2.296 2.307 2.333 2.189 2.405 2.415 2.321
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
8mA
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
4.827 5.232 5.749 5.609 5.909 5.358 5.875 5.736 5.985 ns
ns
GCLK
PLL
1.983 2.083 2.297 2.308 2.334 2.190 2.407 2.417 2.323
4.809 5.213 5.730 5.590 5.890 5.339 5.857 5.718 5.967 ns
ns
GCLK
10m
A
GCLK
PLL
1.965 2.064 2.278 2.289 2.315 2.171 2.389 2.399 2.305
4.807 5.211 5.728 5.588 5.888 5.337 5.854 5.715 5.964 ns
ns
GCLK
12m
A
GCLK
PLL
1.963 2.062 2.276 2.287 2.313 2.169 2.386 2.396 2.302
4.799 5.201 5.716 5.576 5.876 5.326 5.841 5.702 5.951 ns
ns
GCLK
8mA
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS II
1.955 2.052 2.264 2.275 2.301 2.158 2.373 2.383 2.289
4.807 5.211 5.728 5.588 5.888 5.337 5.854 5.715 5.964 ns
GCLK
16m
A
GCLK
PLL
ns
1.963 2.062 2.276 2.287 2.313 2.169 2.386 2.396 2.302
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–280
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–129. EP3SE110 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
I/O Standard
Clock
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.175
1.351
3.175
1.351
3.165
1.341
3.158
1.334
3.417
1.532
3.417
1.532
3.407
1.522
3.399
1.514
4.823 5.226 5.742 5.602 5.902 5.352 5.867 5.728 5.977
1.979 2.077 2.290 2.301 2.327 2.184 2.399 2.409 2.315
4.823 5.226 5.742 5.602 5.902 5.352 5.867 5.728 5.977
1.979 2.077 2.290 2.301 2.327 2.184 2.399 2.409 2.315
4.813 5.216 5.732 5.592 5.892 5.342 5.858 5.719 5.968
1.969 2.067 2.280 2.291 2.317 2.174 2.390 2.400 2.306
4.799 5.201 5.716 5.576 5.876 5.326 5.841 5.702 5.951
1.955 2.052 2.264 2.275 2.301 2.158 2.373 2.383 2.289
8mA
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
16m
A
GCLK
PLL
Table 1–130 specifies EP3SE110 Row Pins Output Timing parameters for differential
I/O standards.
Table 1–130. EP3SE110 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
LVDS
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
2.744
0.931
3.136
1.333
3.118
1.315
2.744
0.931
3.136
1.333
3.118
1.315
2.744
0.931
2.932
1.057
3.376
1.511
3.366
1.501
2.932
1.057
3.376
1.511
3.366
1.501
2.932
1.057
4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107
1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456
4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871
1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229
4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932
1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290
4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107
1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456
4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871
1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229
4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932
1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290
4.083 4.440 4.901 4.771 5.049 4.540 5.002 4.873 5.107
1.249 1.300 1.458 1.480 1.486 1.382 1.545 1.563 1.456
—
—
—
—
—
—
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
GCLK
tco
PLL
GCLK tco
RSDS
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–281
I/O Timing
Table 1–130. EP3SE110 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
RSDS_E_1R
RSDS_E_3R
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.136
1.333
3.118
1.315
3.162
1.359
3.148
1.345
3.144
1.341
3.160
1.357
3.149
1.346
3.146
1.343
3.157
1.354
3.147
1.344
3.133
1.330
3.130
1.327
3.127
1.324
3.376
1.511
3.366
1.501
3.409
1.544
3.395
1.530
3.391
1.526
3.406
1.541
3.396
1.531
3.393
1.528
3.403
1.538
3.394
1.529
3.380
1.515
3.376
1.511
3.374
1.509
4.754 5.156 5.664 5.526 5.797 5.281 5.790 5.652 5.871
1.930 2.026 2.231 2.245 2.243 2.133 2.343 2.352 2.229
4.792 5.202 5.718 5.580 5.851 5.332 5.851 5.713 5.932
1.968 2.072 2.285 2.299 2.297 2.184 2.404 2.413 2.290
4.828 5.236 5.751 5.613 5.884 5.365 5.880 5.742 5.961
2.004 2.106 2.318 2.332 2.330 2.217 2.433 2.442 2.319
4.815 5.223 5.738 5.600 5.871 5.351 5.867 5.729 5.948
1.991 2.093 2.305 2.319 2.317 2.203 2.420 2.429 2.306
4.813 5.223 5.739 5.601 5.872 5.351 5.869 5.731 5.950
1.989 2.093 2.306 2.320 2.318 2.203 2.422 2.431 2.308
4.814 5.220 5.733 5.595 5.866 5.348 5.862 5.724 5.943
1.990 2.090 2.300 2.314 2.312 2.200 2.415 2.424 2.301
4.810 5.216 5.730 5.592 5.863 5.345 5.859 5.721 5.940
1.986 2.086 2.297 2.311 2.309 2.197 2.412 2.421 2.298
4.808 5.214 5.728 5.590 5.861 5.343 5.858 5.720 5.939
1.984 2.084 2.295 2.309 2.307 2.195 2.411 2.420 2.297
4.809 5.215 5.727 5.589 5.860 5.343 5.856 5.718 5.937
1.985 2.085 2.294 2.308 2.306 2.195 2.409 2.418 2.295
4.807 5.213 5.726 5.588 5.859 5.342 5.856 5.718 5.937
1.983 2.083 2.293 2.307 2.305 2.194 2.409 2.418 2.295
4.792 5.198 5.712 5.574 5.845 5.327 5.841 5.703 5.922
1.968 2.068 2.279 2.293 2.291 2.179 2.394 2.403 2.280
4.788 5.194 5.708 5.570 5.841 5.323 5.837 5.699 5.918
1.964 2.064 2.275 2.289 2.287 2.175 2.390 2.399 2.276
4.789 5.197 5.711 5.573 5.844 5.326 5.841 5.703 5.922
1.965 2.067 2.278 2.292 2.290 2.178 2.394 2.403 2.280
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
4mA
6mA
8mA
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–282
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–130. EP3SE110 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.128
1.325
3.177
1.374
3.153
1.350
3.136
1.333
3.181
1.378
3.166
1.363
3.155
1.352
3.135
1.332
3.132
1.329
3.137
1.334
3.130
1.327
3.168
1.365
3.150
1.347
3.374
1.509
3.427
1.562
3.403
1.538
3.384
1.519
3.430
1.565
3.415
1.550
3.404
1.539
3.384
1.519
3.380
1.515
3.384
1.519
3.377
1.512
3.416
1.551
3.399
1.534
4.779 5.185 5.698 5.560 5.831 5.313 5.827 5.689 5.908
1.955 2.055 2.265 2.279 2.277 2.165 2.380 2.389 2.266
4.850 5.258 5.774 5.636 5.907 5.387 5.903 5.765 5.984
2.026 2.128 2.341 2.355 2.353 2.239 2.456 2.465 2.342
4.832 5.241 5.757 5.619 5.890 5.370 5.888 5.750 5.969
2.008 2.111 2.324 2.338 2.336 2.222 2.441 2.450 2.327
4.810 5.219 5.735 5.597 5.868 5.348 5.866 5.728 5.947
1.986 2.089 2.302 2.316 2.314 2.200 2.419 2.428 2.305
4.850 5.258 5.773 5.635 5.906 5.387 5.903 5.765 5.984
2.026 2.128 2.340 2.354 2.352 2.239 2.456 2.465 2.342
4.836 5.243 5.758 5.620 5.891 5.372 5.888 5.750 5.969
2.012 2.113 2.325 2.339 2.337 2.224 2.441 2.450 2.327
4.831 5.240 5.755 5.617 5.888 5.369 5.886 5.748 5.967
2.007 2.110 2.322 2.336 2.334 2.221 2.439 2.448 2.325
4.808 5.216 5.732 5.594 5.865 5.346 5.862 5.724 5.943
1.984 2.086 2.299 2.313 2.311 2.198 2.415 2.424 2.301
4.804 5.213 5.728 5.590 5.861 5.342 5.859 5.721 5.940
1.980 2.083 2.295 2.309 2.307 2.194 2.412 2.421 2.298
4.795 5.201 5.714 5.576 5.847 5.329 5.843 5.705 5.924
1.971 2.071 2.281 2.295 2.293 2.181 2.396 2.405 2.282
4.794 5.202 5.717 5.579 5.850 5.332 5.848 5.710 5.929
1.970 2.072 2.284 2.298 2.296 2.184 2.401 2.410 2.287
4.832 5.239 5.753 5.615 5.886 5.368 5.883 5.745 5.964
2.008 2.109 2.320 2.334 2.332 2.220 2.436 2.445 2.322
4.817 5.224 5.738 5.600 5.871 5.353 5.868 5.730 5.949
1.993 2.094 2.305 2.319 2.317 2.205 2.421 2.430 2.307
DIFFERENTIAL
1.8-V
HSTL CLASS II
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
1.8-V SSTL
CLASS II
PLL
GCLK tco
16mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
2.5-V SSTL
CLASS I
PLL
GCLK tco
12mA
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–283
I/O Timing
Table 1–130. EP3SE110 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
GCLK tco
3.136
1.333
3.383
1.518
4.794 5.200 5.713 5.575 5.846 5.329 5.843 5.705 5.924
1.970 2.070 2.280 2.294 2.292 2.181 2.396 2.405 2.282
DIFFERENTIAL
2.5-V SSTL
CLASS II
16mA
GCLK
tco
PLL
Table 1–131 and Table 1–132 show EP3SE110 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
Table 1–131 specifies EP3SE110 Column Pin delay adders when using the regional
clock.
Table 1–131. EP3SE110 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
RCLK input adder
0.111
2.506
-0.281
-2.121
0.14
0.19 0.103 0.105 0.103 0.177 0.085 0.101 0.098 0.146
3.782 4.081 4.579 4.381 4.923 4.222 4.603 4.401 4.984
-0.079 -0.074 -0.074 -0.072 -0.128 0.056 0.051 0.054 -0.055
-2.75 -2.908 -3.127 -3.057 -3.165 -2.959 -3.157 -2.903 -3.172
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
2.513
-0.062
-1.833
Table 1–132 specifies EP3SE110 Row Pin delay adders when using the regional clock.
Table 1–132. EP3SE110 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
-0.003
0.116
0.02
-0.002
0.122
0.019
-0.105
0.001 -0.012 -0.01 -0.017 0.078 -0.02 -0.02 -0.016 0.08
0.192 0.212 0.227 0.217 0.375 0.198 0.219 0.209 0.379
0.027 0.041 0.044 0.048 -0.038 0.051 0.057 0.051 -0.04
-0.162 -0.179 -0.194 -0.185 -0.322 -0.167 -0.183 -0.175 -0.324
ns
ns
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
-0.103
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–284
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
EP3SE260 I/O Timing Parameters
Table 1–133 through Table 1–137 show the maximum I/O timing parameters for
EP3SE260 devices for single-ended I/O standards.
Table 1–133 specifies EP3SE260 column pins input timing parameters for single-ended
I/O standards.
Table 1–133. EP3SE260 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.329
1.461
0.738
-0.467
-1.329
1.461
0.738
-0.467
-1.335
1.467
0.732
-0.461
-1.335
1.467
0.732
-0.461
-1.325
1.457
0.742
-0.471
-1.343
1.477
0.726
-0.453
-1.336
1.470
0.733
-0.460
-1.276
1.410
0.793
-0.520
-1.318
1.469
0.744
-0.454
-1.318
1.469
0.744
-0.454
-1.329
1.480
0.733
-0.443
-1.329
1.480
0.733
-0.443
-1.324
1.475
0.738
-0.448
-1.346
1.499
0.716
-0.424
-1.336
1.489
0.726
-0.434
-1.284
1.437
0.778
-0.486
-2.028 -2.073 -2.419 -2.337 -2.790 -2.185 -2.453 -2.376 -2.824 ns
GCLK
2.259 2.313 2.679 2.583 3.042 2.432 2.723 2.632 3.077
1.309 1.392 1.407 1.317 1.438 1.452 1.420 1.326 1.491
ns
ns
3.3-V LVTTL
tsu
th
GCLK
PLL
-0.843 -0.909 -0.869 -0.810 -0.909 -0.955 -0.871 -0.809 -0.957 ns
-2.028 -2.073 -2.419 -2.337 -2.790 -2.185 -2.453 -2.376 -2.824 ns
tsu
th
GCLK
2.259 2.313 2.679 2.583 3.042 2.432 2.723 2.632 3.077
1.309 1.392 1.407 1.317 1.438 1.452 1.420 1.326 1.491
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-0.843 -0.909 -0.869 -0.810 -0.909 -0.955 -0.871 -0.809 -0.957 ns
-2.027 -2.075 -2.418 -2.336 -2.789 -2.185 -2.458 -2.381 -2.829 ns
tsu
th
GCLK
2.258 2.315 2.678 2.582 3.041 2.432 2.728 2.637 3.082
1.310 1.390 1.408 1.318 1.439 1.452 1.415 1.321 1.486
ns
ns
3.0-V LVTTL
tsu
th
GCLK
PLL
-0.844 -0.907 -0.870 -0.811 -0.910 -0.955 -0.866 -0.804 -0.952 ns
-2.027 -2.075 -2.418 -2.336 -2.789 -2.185 -2.458 -2.381 -2.829 ns
tsu
th
GCLK
2.258 2.315 2.678 2.582 3.041 2.432 2.728 2.637 3.082
1.310 1.390 1.408 1.318 1.439 1.452 1.415 1.321 1.486
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-0.844 -0.907 -0.870 -0.811 -0.910 -0.955 -0.866 -0.804 -0.952 ns
-2.036 -2.087 -2.437 -2.355 -2.808 -2.195 -2.469 -2.392 -2.840 ns
tsu
th
GCLK
2.267 2.327 2.697 2.601 3.060 2.442 2.739 2.648 3.093
1.301 1.378 1.389 1.299 1.420 1.442 1.404 1.310 1.475
ns
ns
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
-0.835 -0.895 -0.851 -0.792 -0.891 -0.945 -0.855 -0.793 -0.941 ns
-2.076 -2.123 -2.435 -2.353 -2.806 -2.229 -2.472 -2.395 -2.843 ns
tsu
th
GCLK
2.307 2.363 2.695 2.599 3.058 2.476 2.742 2.651 3.096
1.261 1.342 1.391 1.301 1.422 1.408 1.401 1.307 1.472
ns
ns
tsu
th
GCLK
PLL
-0.795 -0.859 -0.853 -0.794 -0.893 -0.911 -0.852 -0.790 -0.938 ns
-2.053 -2.091 -2.365 -2.283 -2.736 -2.198 -2.406 -2.329 -2.777 ns
tsu
th
GCLK
2.284 2.331 2.625 2.529 2.988 2.445 2.676 2.585 3.030
1.284 1.374 1.461 1.371 1.492 1.439 1.467 1.373 1.538
ns
ns
tsu
th
GCLK
PLL
-0.818 -0.891 -0.923 -0.864 -0.963 -0.942 -0.918 -0.856 -1.004 ns
-1.976 -1.992 -2.209 -2.127 -2.580 -2.102 -2.253 -2.176 -2.624 ns
tsu
th
GCLK
2.207 2.232 2.469 2.373 2.832 2.349 2.523 2.432 2.877
1.361 1.473 1.617 1.527 1.648 1.535 1.620 1.526 1.691
ns
ns
tsu
th
GCLK
PLL
-0.895 -0.990 -1.079 -1.020 -1.119 -1.038 -1.071 -1.009 -1.157 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–285
I/O Timing
Table 1–133. EP3SE260 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.257
1.391
0.812
-0.539
-1.257
1.391
0.812
-0.539
-1.250
1.384
0.819
-0.546
-1.250
1.384
0.819
-0.546
-1.238
1.372
0.831
-0.558
-1.238
1.372
0.831
-0.558
-1.250
1.384
0.819
-0.546
-1.250
1.384
0.819
-0.546
-1.238
1.372
0.831
-0.558
-1.255
1.408
0.807
-0.515
-1.255
1.408
0.807
-0.515
-1.249
1.402
0.813
-0.521
-1.249
1.402
0.813
-0.521
-1.238
1.391
0.824
-0.532
-1.238
1.391
0.824
-0.532
-1.249
1.402
0.813
-0.521
-1.249
1.402
0.813
-0.521
-1.238
1.391
0.824
-0.532
-1.948 -1.976 -2.211 -2.129 -2.582 -2.081 -2.249 -2.172 -2.620 ns
GCLK
2.179 2.216 2.471 2.375 2.834 2.328 2.519 2.428 2.873
1.389 1.489 1.615 1.525 1.646 1.556 1.624 1.530 1.695
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-0.923 -1.006 -1.077 -1.018 -1.117 -1.059 -1.075 -1.013 -1.161 ns
-1.948 -1.976 -2.211 -2.129 -2.582 -2.081 -2.249 -2.172 -2.620 ns
tsu
th
GCLK
2.179 2.216 2.471 2.375 2.834 2.328 2.519 2.428 2.873
1.389 1.489 1.615 1.525 1.646 1.556 1.624 1.530 1.695
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-0.923 -1.006 -1.077 -1.018 -1.117 -1.059 -1.075 -1.013 -1.161 ns
-1.935 -1.968 -2.208 -2.124 -2.580 -2.074 -2.250 -2.171 -2.621 ns
tsu
th
GCLK
2.166 2.205 2.465 2.369 2.827 2.318 2.516 2.426 2.869
1.402 1.497 1.618 1.530 1.645 1.560 1.623 1.531 1.691
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-0.936 -1.017 -1.083 -1.024 -1.121 -1.066 -1.078 -1.015 -1.162 ns
-1.935 -1.968 -2.208 -2.124 -2.580 -2.074 -2.250 -2.171 -2.621 ns
tsu
th
GCLK
2.166 2.205 2.465 2.369 2.827 2.318 2.516 2.426 2.869
1.402 1.497 1.618 1.530 1.645 1.560 1.623 1.531 1.691
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-0.936 -1.017 -1.083 -1.024 -1.121 -1.066 -1.078 -1.015 -1.162 ns
-1.924 -1.957 -2.189 -2.105 -2.561 -2.063 -2.232 -2.153 -2.603 ns
tsu
th
GCLK
2.154 2.194 2.446 2.350 2.808 2.307 2.498 2.408 2.851
1.413 1.508 1.637 1.549 1.664 1.571 1.641 1.549 1.709
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-0.948 -1.028 -1.102 -1.043 -1.140 -1.077 -1.096 -1.033 -1.180 ns
-1.924 -1.957 -2.189 -2.105 -2.561 -2.063 -2.232 -2.153 -2.603 ns
tsu
th
GCLK
2.154 2.194 2.446 2.350 2.808 2.307 2.498 2.408 2.851
1.413 1.508 1.637 1.549 1.664 1.571 1.641 1.549 1.709
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.948 -1.028 -1.102 -1.043 -1.140 -1.077 -1.096 -1.033 -1.180 ns
-1.935 -1.968 -2.208 -2.124 -2.580 -2.074 -2.250 -2.171 -2.621 ns
tsu
th
GCLK
2.166 2.205 2.465 2.369 2.827 2.318 2.516 2.426 2.869
1.402 1.497 1.618 1.530 1.645 1.560 1.623 1.531 1.691
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.936 -1.017 -1.083 -1.024 -1.121 -1.066 -1.078 -1.015 -1.162 ns
-1.935 -1.968 -2.208 -2.124 -2.580 -2.074 -2.250 -2.171 -2.621 ns
tsu
th
GCLK
2.166 2.205 2.465 2.369 2.827 2.318 2.516 2.426 2.869
1.402 1.497 1.618 1.530 1.645 1.560 1.623 1.531 1.691
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.936 -1.017 -1.083 -1.024 -1.121 -1.066 -1.078 -1.015 -1.162 ns
-1.924 -1.957 -2.189 -2.105 -2.561 -2.063 -2.232 -2.153 -2.603 ns
tsu
th
GCLK
2.154 2.194 2.446 2.350 2.808 2.307 2.498 2.408 2.851
1.413 1.508 1.637 1.549 1.664 1.571 1.641 1.549 1.709
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.948 -1.028 -1.102 -1.043 -1.140 -1.077 -1.096 -1.033 -1.180 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–286
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–133. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.238
1.372
0.831
-0.558
-1.230
1.364
0.839
-0.566
-1.230
1.364
0.839
-0.566
-1.335
1.467
0.732
-0.461
-1.238
1.391
0.824
-0.532
-1.226
1.379
0.836
-0.544
-1.226
1.379
0.836
-0.544
-1.329
1.480
0.733
-0.443
-1.924 -1.957 -2.189 -2.105 -2.561 -2.063 -2.232 -2.153 -2.603 ns
GCLK
2.154 2.194 2.446 2.350 2.808 2.307 2.498 2.408 2.851
1.413 1.508 1.637 1.549 1.664 1.571 1.641 1.549 1.709
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-0.948 -1.028 -1.102 -1.043 -1.140 -1.077 -1.096 -1.033 -1.180 ns
-1.914 -1.946 -2.173 -2.089 -2.545 -2.052 -2.217 -2.138 -2.588 ns
tsu
th
GCLK
2.144 2.183 2.430 2.334 2.792 2.296 2.483 2.393 2.836
1.423 1.519 1.653 1.565 1.680 1.582 1.656 1.564 1.724
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-0.958 -1.039 -1.118 -1.059 -1.156 -1.088 -1.111 -1.048 -1.195 ns
-1.914 -1.946 -2.173 -2.089 -2.545 -2.052 -2.217 -2.138 -2.588 ns
tsu
th
GCLK
2.144 2.183 2.430 2.334 2.792 2.296 2.483 2.393 2.836
1.423 1.519 1.653 1.565 1.680 1.582 1.656 1.564 1.724
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-0.958 -1.039 -1.118 -1.059 -1.156 -1.088 -1.111 -1.048 -1.195 ns
-2.027 -2.075 -2.418 -2.336 -2.789 -2.185 -2.458 -2.381 -2.829 ns
tsu
th
GCLK
2.258 2.315 2.678 2.582 3.041 2.432 2.728 2.637 3.082
1.310 1.390 1.408 1.318 1.439 1.452 1.415 1.321 1.486
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-0.844 -0.907 -0.870 -0.811 -0.910 -0.955 -0.866 -0.804 -0.952 ns
Table 1–134 specifies EP3SE260 row pins input timing parameters for single-ended
I/O standards.
Table 1–134. EP3SE260 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.219
1.355
0.983
-0.704
-1.219
1.355
0.983
-0.704
-1.225
1.361
0.977
-0.698
-1.374
1.524
0.983
-0.685
-1.374
1.524
0.983
-0.685
-1.385
1.535
0.972
-0.674
-2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643 ns
GCLK
2.293 2.233 2.553 2.431 2.902 2.260 2.659 2.431 2.902
1.749 1.864 1.862 1.767 1.884 1.864 1.883 1.767 1.884
ns
ns
3.3-V
LVTTL
tsu
th
GCLK
PLL
-1.268 -1.363 -1.309 -1.247 -1.343 -1.352 -1.318 -1.247 -1.343 ns
-2.059 -1.988 -2.283 -2.177 -2.643 -2.003 -2.382 -2.177 -2.643 ns
tsu
th
GCLK
2.293 2.233 2.553 2.431 2.902 2.260 2.659 2.431 2.902
1.749 1.864 1.862 1.767 1.884 1.864 1.883 1.767 1.884
ns
ns
3.3-V
LVCMOS
tsu
th
GCLK
PLL
-1.268 -1.363 -1.309 -1.247 -1.343 -1.352 -1.318 -1.247 -1.343 ns
-2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646 ns
tsu
th
GCLK
2.290 2.234 2.556 2.434 2.905 2.259 2.664 2.434 2.905
1.752 1.863 1.859 1.764 1.881 1.865 1.878 1.764 1.881
ns
ns
3.0-V
LVTTL
tsu
th
GCLK
PLL
-1.271 -1.362 -1.306 -1.244 -1.340 -1.353 -1.313 -1.244 -1.340 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–287
I/O Timing
Table 1–134. EP3SE260 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.225
1.361
0.977
-0.698
-1.213
1.349
0.989
-0.710
-1.283
1.421
0.968
-0.688
-1.273
1.411
0.978
-0.698
-1.213
1.351
1.038
-0.758
-1.155
1.292
1.047
-0.767
-1.155
1.292
1.047
-0.767
-1.187
1.325
1.064
-0.784
-1.187
1.325
1.064
-0.784
-1.385
1.535
0.972
-0.674
-1.378
1.528
0.979
-0.681
-1.435
1.586
0.896
-0.599
-1.424
1.575
0.907
-0.610
-1.371
1.522
0.960
-0.663
-1.320
1.471
1.038
-0.739
-1.320
1.471
1.038
-0.739
-1.336
1.487
0.995
-0.698
-1.336
1.487
0.995
-0.698
-2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646 ns
GCLK
2.290 2.234 2.556 2.434 2.905 2.259 2.664 2.434 2.905
1.752 1.863 1.859 1.764 1.881 1.865 1.878 1.764 1.881
ns
ns
3.0-V
LVCMOS
tsu
th
GCLK
PLL
-1.271 -1.362 -1.306 -1.244 -1.340 -1.353 -1.313 -1.244 -1.340 ns
-2.065 -2.002 -2.301 -2.195 -2.661 -2.011 -2.397 -2.195 -2.661 ns
tsu
th
GCLK
2.299 2.247 2.571 2.449 2.920 2.268 2.674 2.449 2.920
1.743 1.850 1.844 1.749 1.866 1.856 1.868 1.749 1.866
ns
ns
2.5 V
1.8 V
1.5 V
1.2 V
tsu
th
GCLK
PLL
-1.262 -1.349 -1.291 -1.229 -1.325 -1.344 -1.303 -1.229 -1.325 ns
-2.130 -2.167 -2.360 -2.314 -2.765 -2.088 -2.409 -2.314 -2.765 ns
tsu
th
GCLK
2.364 2.410 2.627 2.565 3.018 2.344 2.687 2.565 3.018
1.617 1.714 1.860 1.741 1.759 1.830 1.861 1.741 1.759
ns
ns
tsu
th
GCLK
PLL
-1.139 -1.216 -1.307 -1.221 -1.223 -1.318 -1.296 -1.221 -1.223 ns
-2.106 -2.135 -2.292 -2.246 -2.697 -2.057 -2.344 -2.246 -2.697 ns
tsu
th
GCLK
2.340 2.378 2.559 2.497 2.950 2.313 2.622 2.497 2.950
1.641 1.746 1.928 1.809 1.827 1.861 1.926 1.809 1.827
ns
ns
tsu
th
GCLK
PLL
-1.163 -1.248 -1.375 -1.289 -1.291 -1.349 -1.361 -1.289 -1.291 ns
-2.027 -2.034 -2.133 -2.087 -2.538 -1.961 -2.189 -2.087 -2.538 ns
tsu
th
GCLK
2.261 2.277 2.400 2.338 2.791 2.217 2.467 2.338 2.791
1.720 1.847 2.087 1.968 1.986 1.957 2.081 1.968 1.986
ns
ns
tsu
th
GCLK
PLL
-1.242 -1.349 -1.534 -1.448 -1.450 -1.445 -1.516 -1.448 -1.450 ns
-1.979 -1.893 -2.081 -1.975 -2.441 -1.899 -2.180 -1.975 -2.441 ns
tsu
th
GCLK
2.213 2.138 2.351 2.229 2.700 2.156 2.457 2.229 2.700
1.829 1.959 2.064 1.969 2.086 1.968 2.085 1.969 2.086
ns
ns
SSTL-2
CLASS I
tsu
th
GCLK
PLL
-1.348 -1.458 -1.511 -1.449 -1.545 -1.456 -1.520 -1.449 -1.545 ns
-1.979 -1.893 -2.081 -1.975 -2.441 -1.899 -2.180 -1.975 -2.441 ns
tsu
th
GCLK
2.213 2.138 2.351 2.229 2.700 2.156 2.457 2.229 2.700
1.829 1.959 2.064 1.969 2.086 1.968 2.085 1.969 2.086
ns
ns
SSTL-2
CLASS II
tsu
th
GCLK
PLL
-1.348 -1.458 -1.511 -1.449 -1.545 -1.456 -1.520 -1.449 -1.545 ns
-1.989 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 ns
tsu
th
GCLK
2.223 2.248 2.393 2.331 2.783 2.185 2.457 2.331 2.783
1.758 1.874 2.092 1.974 1.990 1.986 2.088 1.974 1.990
ns
ns
SSTL-18
CLASS I
tsu
th
GCLK
PLL
-1.280 -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 ns
-1.989 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 ns
tsu
th
GCLK
2.223 2.248 2.393 2.331 2.783 2.185 2.457 2.331 2.783
1.758 1.874 2.092 1.974 1.990 1.986 2.088 1.974 1.990
ns
ns
SSTL-18
CLASS II
tsu
th
GCLK
PLL
-1.280 -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–288
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–134. EP3SE260 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
tsu
th
-1.173
1.311
1.078
-0.798
-1.187
1.325
1.064
-0.784
-1.187
1.325
1.064
-0.784
-1.173
1.311
1.078
-0.798
-1.173
1.311
1.078
-0.798
-1.164
1.302
1.087
-0.807
-1.164
1.302
1.087
-0.807
-1.225
1.361
0.977
-0.698
-1.225
1.361
0.977
-0.698
-1.324
1.475
1.007
-0.710
-1.336
1.487
0.995
-0.698
-1.336
1.487
0.995
-0.698
-1.324
1.475
1.007
-0.710
-1.324
1.475
1.007
-0.710
-1.312
1.463
1.019
-0.722
-1.312
1.463
1.019
-0.722
-1.385
1.535
0.972
-0.674
-1.385
1.535
0.972
-0.674
-1.974 -1.997 -2.110 -2.063 -2.516 -1.921 -2.165 -2.063 -2.516 ns
GCLK
2.209 2.238 2.375 2.313 2.765 2.174 2.440 2.313 2.765
1.773 1.884 2.110 1.992 2.008 1.997 2.105 1.992 2.008
ns
ns
SSTL-15
CLASS I
tsu
th
GCLK
PLL
-1.294 -1.388 -1.559 -1.473 -1.476 -1.488 -1.543 -1.473 -1.476 ns
-1.989 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 ns
tsu
th
GCLK
2.223 2.248 2.393 2.331 2.783 2.185 2.457 2.331 2.783
1.758 1.874 2.092 1.974 1.990 1.986 2.088 1.974 1.990
ns
ns
1.8-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.280 -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 ns
-1.989 -2.007 -2.128 -2.081 -2.534 -1.932 -2.182 -2.081 -2.534 ns
tsu
th
GCLK
2.223 2.248 2.393 2.331 2.783 2.185 2.457 2.331 2.783
1.758 1.874 2.092 1.974 1.990 1.986 2.088 1.974 1.990
ns
ns
1.8-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.280 -1.378 -1.541 -1.455 -1.458 -1.477 -1.526 -1.455 -1.458 ns
-1.974 -1.997 -2.110 -2.063 -2.516 -1.921 -2.165 -2.063 -2.516 ns
tsu
th
GCLK
2.209 2.238 2.375 2.313 2.765 2.174 2.440 2.313 2.765
1.773 1.884 2.110 1.992 2.008 1.997 2.105 1.992 2.008
ns
ns
1.5-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.294 -1.388 -1.559 -1.473 -1.476 -1.488 -1.543 -1.473 -1.476 ns
-1.974 -1.997 -2.110 -2.063 -2.516 -1.921 -2.165 -2.063 -2.516 ns
tsu
th
GCLK
2.209 2.238 2.375 2.313 2.765 2.174 2.440 2.313 2.765
1.773 1.884 2.110 1.992 2.008 1.997 2.105 1.992 2.008
ns
ns
1.5-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.294 -1.388 -1.559 -1.473 -1.476 -1.488 -1.543 -1.473 -1.476 ns
-1.965 -1.987 -2.094 -2.047 -2.500 -1.912 -2.149 -2.047 -2.500 ns
tsu
th
GCLK
2.200 2.228 2.359 2.297 2.749 2.165 2.424 2.297 2.749
1.782 1.894 2.126 2.008 2.024 2.006 2.121 2.008 2.024
ns
ns
1.2-V HSTL
CLASS I
tsu
th
GCLK
PLL
-1.303 -1.398 -1.575 -1.489 -1.492 -1.497 -1.559 -1.489 -1.492 ns
-1.965 -1.987 -2.094 -2.047 -2.500 -1.912 -2.149 -2.047 -2.500 ns
tsu
th
GCLK
2.200 2.228 2.359 2.297 2.749 2.165 2.424 2.297 2.749
1.782 1.894 2.126 2.008 2.024 2.006 2.121 2.008 2.024
ns
ns
1.2-V HSTL
CLASS II
tsu
th
GCLK
PLL
-1.303 -1.398 -1.575 -1.489 -1.492 -1.497 -1.559 -1.489 -1.492 ns
-2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646 ns
tsu
th
GCLK
2.290 2.234 2.556 2.434 2.905 2.259 2.664 2.434 2.905
1.752 1.863 1.859 1.764 1.881 1.865 1.878 1.764 1.881
ns
ns
3.0-V PCI
tsu
th
GCLK
PLL
-1.271 -1.362 -1.306 -1.244 -1.340 -1.353 -1.313 -1.244 -1.340 ns
-2.056 -1.989 -2.286 -2.180 -2.646 -2.002 -2.387 -2.180 -2.646 ns
tsu
th
GCLK
2.290 2.234 2.556 2.434 2.905 2.259 2.664 2.434 2.905
1.752 1.863 1.859 1.764 1.881 1.865 1.878 1.764 1.881
ns
ns
3.0-V
PCI-X
tsu
th
GCLK
PLL
-1.271 -1.362 -1.306 -1.244 -1.340 -1.353 -1.313 -1.244 -1.340 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–289
I/O Timing
Table 1–135 specifies EP3SE260 Column Pins Output Timing parameters for single-
ended I/O standards.
Table 1–135. EP3SE260 Column Pins output Timing Parameters (Part 1 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.472
1.719
3.393
1.614
3.364
1.554
3.350
1.533
3.410
1.661
3.339
1.529
3.314
1.487
3.307
1.474
3.470
1.724
3.403
1.620
3.365
1.568
3.343
1.532
3.750
1.820
3.661
1.731
3.629
1.699
3.615
1.685
3.683
1.753
3.606
1.676
3.578
1.648
3.571
1.641
3.759
1.829
3.674
1.744
3.637
1.707
3.610
1.680
5.438 5.642 6.327 6.171 6.415 5.777 6.468 6.317 6.508
2.330 2.414 2.798 2.798 2.620 2.685 2.916 2.918 2.742
5.335 5.530 6.159 6.003 6.298 5.661 6.295 6.144 6.388
2.226 2.302 2.630 2.630 2.503 2.516 2.743 2.745 2.569
5.268 5.460 6.059 5.903 6.228 5.591 6.190 6.039 6.321
2.159 2.232 2.530 2.530 2.433 2.418 2.638 2.640 2.464
5.247 5.437 6.016 5.860 6.200 5.565 6.149 5.998 6.287
2.138 2.209 2.487 2.487 2.405 2.372 2.597 2.599 2.423
5.365 5.559 6.205 6.049 6.327 5.691 6.343 6.192 6.420
2.257 2.331 2.676 2.676 2.532 2.564 2.791 2.793 2.617
5.243 5.433 6.007 5.851 6.196 5.561 6.142 5.991 6.283
2.135 2.205 2.478 2.478 2.401 2.363 2.590 2.592 2.416
5.214 5.406 5.948 5.792 6.171 5.534 6.079 5.928 6.258
2.106 2.178 2.419 2.419 2.376 2.309 2.527 2.529 2.357
5.206 5.397 5.927 5.771 6.162 5.525 6.055 5.904 6.248
2.098 2.169 2.398 2.398 2.367 2.286 2.503 2.505 2.348
5.472 5.678 6.387 6.231 6.454 5.816 6.517 6.366 6.550
2.364 2.450 2.858 2.858 2.659 2.728 2.965 2.967 2.791
5.368 5.567 6.234 6.078 6.338 5.701 6.344 6.193 6.431
2.260 2.338 2.705 2.705 2.543 2.561 2.792 2.794 2.618
5.300 5.495 6.132 5.976 6.264 5.627 6.231 6.080 6.355
2.192 2.267 2.603 2.603 2.469 2.455 2.679 2.681 2.505
5.265 5.456 6.082 5.926 6.222 5.587 6.161 6.010 6.312
2.157 2.228 2.553 2.553 2.427 2.385 2.609 2.611 2.435
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVTTL
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.3-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVTTL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–290
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–135. EP3SE260 Column Pins output Timing Parameters (Part 2 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.424
1.672
3.352
1.546
3.328
1.496
3.328
1.491
3.528
1.791
3.445
1.684
3.390
1.600
3.356
1.572
3.699
1.769
3.620
1.690
3.591
1.661
3.591
1.661
3.814
1.884
3.721
1.791
3.677
1.747
3.631
1.701
5.402 5.600 6.288 6.132 6.373 5.735 6.397 6.246 6.468
2.294 2.372 2.759 2.759 2.578 2.612 2.845 2.847 2.671
5.279 5.471 6.106 5.950 6.238 5.602 6.186 6.035 6.328
2.170 2.243 2.577 2.577 2.443 2.410 2.634 2.636 2.460
5.239 5.432 6.035 5.879 6.197 5.562 6.121 5.970 6.287
2.131 2.203 2.506 2.506 2.402 2.349 2.569 2.571 2.395
5.231 5.422 6.036 5.880 6.187 5.551 6.090 5.939 6.275
2.123 2.194 2.507 2.507 2.392 2.318 2.538 2.540 2.374
5.609 5.827 6.570 6.414 6.620 5.968 6.722 6.571 6.723
2.501 2.599 3.041 3.041 2.825 2.903 3.170 3.172 2.996
5.490 5.701 6.373 6.217 6.488 5.840 6.512 6.361 6.587
2.382 2.473 2.844 2.844 2.693 2.711 2.960 2.962 2.786
5.398 5.605 6.233 6.077 6.388 5.742 6.362 6.211 6.485
2.290 2.377 2.704 2.704 2.593 2.571 2.810 2.812 2.636
5.364 5.568 6.183 6.027 6.347 5.703 6.298 6.147 6.441
2.256 2.340 2.654 2.654 2.552 2.505 2.746 2.748 2.572
4mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
3.0-V
LVCMOS
GCLK tco
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
2.5 V
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–291
I/O Timing
Table 1–135. EP3SE260 Column Pins output Timing Parameters (Part 3 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.642
1.968
3.544
1.823
3.462
1.721
3.437
1.638
3.366
1.584
3.361
1.578
3.583
1.886
3.451
1.687
3.407
1.612
3.395
1.606
3.360
1.565
3.356
1.528
3.942
2.012
3.831
1.901
3.744
1.814
3.711
1.781
3.647
1.717
3.637
1.707
3.909
1.979
3.728
1.798
3.691
1.761
3.685
1.755
3.634
1.704
3.627
1.697
5.804 6.036 6.897 6.741 6.838 6.186 7.057 6.906 6.949
2.695 2.808 3.368 3.368 3.043 3.235 3.505 3.507 3.331
5.652 5.878 6.647 6.491 6.677 6.027 6.800 6.649 6.783
2.543 2.650 3.118 3.118 2.882 2.982 3.248 3.250 3.074
5.525 5.740 6.443 6.287 6.533 5.883 6.581 6.430 6.635
2.416 2.512 2.914 2.914 2.738 2.775 3.029 3.031 2.855
5.464 5.674 6.333 6.177 6.458 5.812 6.466 6.315 6.555
2.356 2.446 2.804 2.804 2.663 2.671 2.914 2.916 2.740
5.376 5.580 6.203 6.047 6.359 5.715 6.322 6.171 6.454
2.268 2.352 2.674 2.674 2.564 2.532 2.770 2.772 2.596
5.370 5.574 6.198 6.042 6.352 5.708 6.310 6.159 6.447
2.262 2.346 2.669 2.669 2.557 2.519 2.758 2.760 2.584
5.742 5.963 6.785 6.629 6.766 6.116 6.944 6.793 6.882
2.634 2.735 3.256 3.256 2.971 3.124 3.392 3.394 3.218
5.499 5.709 6.382 6.226 6.495 5.848 6.519 6.368 6.595
2.390 2.481 2.853 2.853 2.700 2.720 2.967 2.969 2.793
5.418 5.629 6.275 6.119 6.415 5.768 6.392 6.241 6.512
2.310 2.401 2.746 2.746 2.620 2.597 2.840 2.842 2.666
5.412 5.622 6.260 6.104 6.406 5.761 6.379 6.228 6.505
2.304 2.393 2.731 2.731 2.611 2.587 2.827 2.829 2.653
5.364 5.568 6.190 6.034 6.345 5.702 6.295 6.144 6.440
2.256 2.340 2.661 2.661 2.550 2.503 2.743 2.745 2.569
5.344 5.547 6.166 6.010 6.325 5.681 6.252 6.101 6.418
2.235 2.319 2.637 2.637 2.530 2.465 2.700 2.702 2.526
2mA
4mA
6mA
8mA
10mA
12mA
2mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.8 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5 V
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–292
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–135. EP3SE260 Column Pins output Timing Parameters (Part 4 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.562
1.850
3.440
1.640
3.387
1.598
3.366
1.549
3.380
1.585
3.383
1.589
3.364
1.557
3.359
1.541
3.398
1.607
3.379
1.580
3.380
1.577
3.363
1.547
3.359
1.540
3.852
1.922
3.717
1.787
3.676
1.746
3.642
1.712
3.650
1.720
3.653
1.723
3.633
1.703
3.626
1.696
3.670
1.740
3.649
1.719
3.652
1.722
3.632
1.702
3.628
1.698
5.696 5.917 6.709 6.553 6.709 6.063 6.856 6.705 6.816
2.588 2.689 3.180 3.180 2.914 3.035 3.304 3.306 3.130
5.477 5.686 6.352 6.196 6.469 5.824 6.475 6.324 6.567
2.369 2.458 2.823 2.823 2.674 2.681 2.923 2.925 2.749
5.401 5.609 6.251 6.095 6.395 5.749 6.359 6.208 6.495
2.293 2.381 2.722 2.722 2.600 2.570 2.807 2.809 2.633
5.362 5.566 6.201 6.045 6.345 5.700 6.278 6.127 6.438
2.254 2.338 2.672 2.672 2.550 2.486 2.726 2.728 2.552
5.370 5.574 6.214 6.058 6.353 5.706 6.293 6.142 6.443
2.262 2.346 2.685 2.685 2.558 2.508 2.741 2.743 2.567
5.374 5.578 6.222 6.066 6.357 5.709 6.299 6.148 6.447
2.266 2.350 2.693 2.693 2.562 2.514 2.747 2.749 2.573
5.353 5.556 6.180 6.024 6.335 5.688 6.265 6.114 6.425
2.244 2.328 2.651 2.651 2.540 2.479 2.713 2.715 2.539
5.338 5.540 6.161 6.005 6.318 5.671 6.234 6.083 6.407
2.229 2.312 2.632 2.632 2.523 2.450 2.682 2.684 2.508
5.393 5.597 6.244 6.088 6.376 5.729 6.320 6.169 6.467
2.285 2.369 2.715 2.715 2.581 2.535 2.768 2.770 2.594
5.371 5.575 6.209 6.053 6.354 5.707 6.289 6.138 6.444
2.263 2.347 2.680 2.680 2.559 2.504 2.737 2.739 2.563
5.379 5.584 6.226 6.070 6.364 5.717 6.300 6.149 6.455
2.271 2.356 2.697 2.697 2.569 2.513 2.748 2.750 2.574
5.355 5.559 6.186 6.030 6.339 5.691 6.262 6.111 6.429
2.246 2.331 2.657 2.657 2.544 2.477 2.710 2.712 2.536
5.351 5.555 6.178 6.022 6.334 5.687 6.256 6.105 6.425
2.242 2.327 2.649 2.649 2.539 2.470 2.704 2.706 2.530
2mA
GCLK
tco
PLL
GCLK tco
4mA
GCLK
tco
PLL
1.2 V
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
8mA
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS I
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-2
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–293
I/O Timing
Table 1–135. EP3SE260 Column Pins output Timing Parameters (Part 5 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.360
1.539
3.359
1.526
3.389
1.593
3.374
1.564
3.361
1.540
3.362
1.533
3.357
1.526
3.375
1.570
3.374
1.563
3.627
1.697
3.627
1.697
3.661
1.731
3.645
1.715
3.630
1.700
3.631
1.701
3.626
1.696
3.643
1.713
3.643
1.713
5.338 5.541 6.160 6.004 6.318 5.672 6.230 6.079 6.408
2.230 2.312 2.631 2.631 2.523 2.447 2.678 2.680 2.507
5.346 5.551 6.156 6.000 6.330 5.682 6.231 6.080 6.421
2.238 2.322 2.627 2.627 2.535 2.445 2.679 2.681 2.520
5.386 5.590 6.225 6.069 6.368 5.722 6.304 6.153 6.459
2.278 2.362 2.696 2.696 2.573 2.520 2.752 2.754 2.578
5.372 5.577 6.209 6.053 6.356 5.709 6.284 6.133 6.448
2.264 2.349 2.680 2.680 2.561 2.499 2.732 2.734 2.558
5.352 5.556 6.181 6.025 6.336 5.689 6.254 6.103 6.427
2.244 2.328 2.652 2.652 2.541 2.469 2.702 2.704 2.528
5.353 5.558 6.186 6.030 6.339 5.691 6.249 6.098 6.430
2.245 2.330 2.657 2.657 2.544 2.463 2.697 2.699 2.529
5.346 5.551 6.175 6.019 6.331 5.683 6.238 6.087 6.422
2.238 2.323 2.646 2.646 2.536 2.452 2.686 2.688 2.521
5.354 5.556 6.183 6.027 6.333 5.687 6.256 6.105 6.423
2.246 2.328 2.654 2.654 2.538 2.473 2.704 2.706 2.530
5.358 5.561 6.198 6.042 6.339 5.692 6.262 6.111 6.429
2.250 2.333 2.669 2.669 2.544 2.478 2.710 2.712 2.536
8mA
GCLK
tco
PLL
SSTL-18
CLASS II
GCLK tco
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
SSTL-15
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
8mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
SSTL-15
CLASS II
GCLK tco
16mA
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–294
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–135. EP3SE260 Column Pins output Timing Parameters (Part 6 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.361
1.541
3.357
1.532
3.359
1.530
3.358
1.523
3.376
1.567
3.371
1.556
3.371
1.554
3.361
1.537
3.363
1.534
3.385
1.570
3.374
1.553
3.373
1.544
3.629
1.699
3.624
1.694
3.627
1.697
3.625
1.695
3.644
1.714
3.640
1.710
3.639
1.709
3.629
1.699
3.631
1.701
3.656
1.726
3.644
1.714
3.642
1.712
5.342 5.545 6.171 6.015 6.323 5.676 6.237 6.086 6.413
2.234 2.317 2.642 2.642 2.528 2.453 2.685 2.687 2.512
5.336 5.539 6.156 6.000 6.317 5.670 6.226 6.075 6.407
2.228 2.311 2.627 2.627 2.522 2.442 2.674 2.676 2.506
5.341 5.544 6.173 6.017 6.323 5.676 6.230 6.079 6.413
2.233 2.316 2.644 2.644 2.528 2.445 2.678 2.680 2.513
5.334 5.537 6.146 5.990 6.315 5.668 6.210 6.057 6.404
2.226 2.309 2.617 2.617 2.520 2.425 2.656 2.658 2.504
5.356 5.558 6.183 6.027 6.336 5.690 6.255 6.104 6.425
2.248 2.330 2.654 2.654 2.541 2.473 2.703 2.705 2.529
5.354 5.557 6.186 6.030 6.335 5.689 6.251 6.100 6.425
2.246 2.329 2.657 2.657 2.540 2.468 2.699 2.701 2.525
5.355 5.558 6.187 6.031 6.336 5.690 6.252 6.101 6.426
2.247 2.330 2.658 2.658 2.541 2.469 2.700 2.702 2.526
5.343 5.546 6.168 6.012 6.324 5.677 6.233 6.082 6.414
2.234 2.318 2.639 2.639 2.529 2.449 2.681 2.683 2.513
5.348 5.553 6.178 6.022 6.332 5.684 6.236 6.085 6.422
2.240 2.324 2.649 2.649 2.537 2.451 2.684 2.686 2.522
5.376 5.580 6.208 6.052 6.358 5.712 6.274 6.123 6.449
2.268 2.351 2.679 2.679 2.563 2.492 2.722 2.724 2.549
5.364 5.568 6.194 6.038 6.347 5.700 6.258 6.107 6.438
2.256 2.340 2.665 2.665 2.552 2.474 2.706 2.708 2.537
5.362 5.566 6.193 6.037 6.345 5.699 6.251 6.100 6.437
2.254 2.338 2.664 2.664 2.550 2.466 2.699 2.701 2.536
4mA
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
4mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
6mA
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS I
8mA
GCLK
tco
PLL
GCLK tco
10mA
12mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.5-V
HSTL
CLASS II
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–295
I/O Timing
Table 1–135. EP3SE260 Column Pins output Timing Parameters (Part 7 of 7)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.370
1.538
3.366
1.533
3.443
1.611
3.443
1.611
3.472
1.719
3.393
1.614
3.364
1.554
3.350
1.533
3.640
1.710
3.636
1.706
3.711
1.781
3.711
1.781
3.750
1.820
3.661
1.731
3.629
1.699
3.615
1.685
5.361 5.566 6.191 6.035 6.345 5.698 6.247 6.096 6.437
2.253 2.338 2.662 2.662 2.550 2.461 2.695 2.697 2.536
5.355 5.559 6.181 6.025 6.338 5.691 6.239 6.088 6.429
2.246 2.331 2.652 2.652 2.543 2.453 2.687 2.689 2.529
5.372 5.567 6.150 5.994 6.335 5.699 6.232 6.079 6.427
2.264 2.339 2.621 2.621 2.540 2.456 2.678 2.680 2.526
5.372 5.567 6.150 5.994 6.335 5.699 6.232 6.079 6.427
2.264 2.339 2.621 2.621 2.540 2.456 2.678 2.680 2.526
5.438 5.642 6.327 6.171 6.415 5.777 6.468 6.317 6.508
2.330 2.414 2.798 2.798 2.620 2.685 2.916 2.918 2.742
5.335 5.530 6.159 6.003 6.298 5.661 6.295 6.144 6.388
2.226 2.302 2.630 2.630 2.503 2.516 2.743 2.745 2.569
5.268 5.460 6.059 5.903 6.228 5.591 6.190 6.039 6.321
2.159 2.232 2.530 2.530 2.433 2.418 2.638 2.640 2.464
5.247 5.437 6.016 5.860 6.200 5.565 6.149 5.998 6.287
2.138 2.209 2.487 2.487 2.405 2.372 2.597 2.599 2.423
4mA
6mA
8mA
10mA
12mA
16mA
—
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.2-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
3.0-V PCI
GCLK
tco
PLL
GCLK tco
3.0-V
PCI-X
—
GCLK
tco
PLL
Table 1–136 specifies EP3SE260 Row Pins Output Timing parameters for single-ended
I/O standards.
Table 1–136. EP3SE260 Row Pins output Timing Parameters (Part 1 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
3.648
1.582
3.555
1.489
3.456
1.390
3.902
1.785
3.797
1.680
3.707
1.574
5.663 5.865 6.484 6.256 6.709 6.063 6.530 6.256 6.709
2.228 2.322 2.505 2.489 2.454 2.441 2.632 2.489 2.454
5.533 5.727 6.340 6.112 6.565 5.922 6.414 6.112 6.565
2.098 2.184 2.361 2.346 2.310 2.300 2.483 2.346 2.310
5.414 5.604 6.212 5.995 6.446 5.795 6.315 5.995 6.446
1.979 2.061 2.233 2.250 2.182 2.173 2.354 2.250 2.182
4mA
8mA
12mA
GCLK
PLL
3.3-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–296
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–136. EP3SE260 Row Pins output Timing Parameters (Part 2 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.658
1.592
3.460
1.394
3.602
1.536
3.477
1.411
3.438
1.372
3.516
1.450
3.416
1.350
3.628
1.562
3.518
1.452
3.472
1.406
3.886
1.787
3.661
1.562
3.596
1.497
3.536
1.437
3.906
1.789
3.711
1.580
3.848
1.731
3.721
1.604
3.678
1.553
3.767
1.650
3.662
1.531
3.884
1.767
3.785
1.668
3.718
1.592
4.170
2.014
3.968
1.812
3.866
1.710
3.792
1.649
5.671 5.870 6.489 6.261 6.714 6.069 6.542 6.261 6.714
2.236 2.327 2.510 2.494 2.459 2.447 2.637 2.494 2.459
5.420 5.616 6.218 6.005 6.456 5.801 6.324 6.005 6.456
1.985 2.067 2.239 2.260 2.188 2.179 2.363 2.260 2.188
5.615 5.818 6.441 6.213 6.666 6.020 6.496 6.213 6.666
2.180 2.275 2.462 2.446 2.411 2.398 2.590 2.446 2.411
5.463 5.659 6.277 6.049 6.502 5.858 6.351 6.049 6.502
2.028 2.116 2.298 2.282 2.247 2.236 2.426 2.282 2.247
5.381 5.576 6.189 5.961 6.414 5.772 6.277 5.961 6.414
1.946 2.033 2.210 2.211 2.159 2.150 2.333 2.211 2.159
5.510 5.711 6.330 6.102 6.555 5.912 6.387 6.102 6.555
2.075 2.168 2.351 2.335 2.300 2.290 2.479 2.335 2.300
5.351 5.545 6.150 5.928 6.379 5.732 6.249 5.928 6.379
1.911 1.994 2.171 2.183 2.120 2.110 2.293 2.183 2.120
5.748 5.972 6.613 6.385 6.838 6.180 6.648 6.385 6.838
2.313 2.429 2.634 2.618 2.583 2.558 2.769 2.618 2.583
5.593 5.809 6.443 6.215 6.668 6.013 6.504 6.215 6.668
2.158 2.266 2.464 2.448 2.413 2.391 2.595 2.448 2.413
5.482 5.690 6.317 6.089 6.542 5.890 6.409 6.089 6.542
2.047 2.147 2.338 2.338 2.287 2.268 2.465 2.338 2.287
6.174 6.450 7.088 6.750 7.260 6.640 7.070 6.750 7.260
2.698 2.822 3.109 3.100 3.058 2.988 3.253 3.100 3.058
5.848 6.082 6.683 6.390 6.855 6.275 6.709 6.390 6.855
2.372 2.454 2.704 2.695 2.653 2.623 2.847 2.695 2.653
5.694 5.932 6.524 6.289 6.709 6.107 6.603 6.289 6.709
2.218 2.304 2.545 2.536 2.494 2.455 2.674 2.536 2.494
5.617 5.839 6.428 6.224 6.644 6.012 6.531 6.224 6.644
2.141 2.227 2.449 2.440 2.398 2.360 2.580 2.440 2.398
4mA
8mA
4mA
8mA
12mA
4mA
8mA
4mA
8mA
12mA
2mA
4mA
6mA
8mA
GCLK
PLL
3.3-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVTTL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
3.0-V
LVCMOS
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
2.5 V
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
1.8 V
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–297
I4L
Table 1–136. EP3SE260 Row Pins output Timing Parameters (Part 3 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
0.9V
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.797
1.698
3.555
1.456
3.528
1.429
3.519
1.420
3.740
1.641
3.560
1.461
3.457
1.391
3.445
1.379
3.429
1.363
3.497
1.398
3.482
1.383
3.471
1.372
3.447
1.348
3.447
1.348
4.088
1.932
3.831
1.675
3.783
1.640
3.774
1.629
4.013
1.857
3.824
1.670
3.706
1.578
3.702
1.566
3.691
1.548
3.748
1.593
3.734
1.588
3.722
1.577
3.699
1.566
3.698
1.565
6.084 6.364 7.016 6.687 7.188 6.547 7.005 6.687 7.188
2.608 2.736 3.037 3.028 2.986 2.895 3.177 3.028 2.986
5.679 5.927 6.525 6.293 6.713 6.101 6.604 6.293 6.713
2.203 2.299 2.546 2.537 2.495 2.449 2.673 2.537 2.495
5.606 5.831 6.419 6.224 6.644 6.003 6.531 6.224 6.644
2.130 2.219 2.440 2.431 2.389 2.351 2.568 2.431 2.389
5.584 5.813 6.400 6.205 6.625 5.985 6.512 6.205 6.625
2.108 2.195 2.421 2.412 2.370 2.333 2.549 2.412 2.370
5.994 6.278 6.941 6.626 7.113 6.459 6.936 6.626 7.113
2.518 2.650 2.962 2.953 2.911 2.807 3.093 2.953 2.911
5.701 5.955 6.566 6.341 6.761 6.126 6.648 6.341 6.761
2.225 2.327 2.587 2.578 2.536 2.474 2.715 2.578 2.536
5.468 5.677 6.285 6.073 6.524 5.857 6.395 6.073 6.524
2.024 2.119 2.306 2.328 2.255 2.235 2.434 2.328 2.255
5.465 5.675 6.277 6.071 6.522 5.849 6.394 6.071 6.522
2.016 2.111 2.301 2.326 2.247 2.227 2.433 2.326 2.247
5.450 5.659 6.250 6.054 6.505 5.823 6.376 6.054 6.505
1.991 2.086 2.284 2.309 2.220 2.201 2.415 2.309 2.220
5.512 5.726 6.301 6.119 6.539 5.893 6.422 6.119 6.539
2.041 2.131 2.324 2.313 2.271 2.241 2.459 2.313 2.271
5.509 5.724 6.299 6.118 6.538 5.891 6.420 6.118 6.538
2.039 2.130 2.323 2.311 2.269 2.239 2.457 2.311 2.269
5.492 5.707 6.282 6.108 6.528 5.874 6.411 6.108 6.528
2.029 2.120 2.313 2.294 2.252 2.222 2.448 2.294 2.252
5.476 5.691 6.267 6.095 6.515 5.859 6.399 6.095 6.515
2.016 2.107 2.300 2.279 2.237 2.207 2.436 2.279 2.237
5.475 5.690 6.266 6.095 6.515 5.858 6.399 6.095 6.515
2.016 2.107 2.300 2.278 2.236 2.206 2.436 2.278 2.236
2mA
4mA
6mA
8mA
2mA
4mA
8mA
12mA
16mA
4mA
6mA
8mA
10mA
12mA
GCLK
PLL
GCLK
GCLK
PLL
1.5 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.2 V
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-2
CLASS I
GCLK
GCLK
PLL
GCLK
SSTL-2
CLASS II
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
SSTL-18
CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–298
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–136. EP3SE260 Row Pins output Timing Parameters (Part 4 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.457
1.358
3.451
1.352
3.493
1.394
3.470
1.371
3.453
1.354
3.472
1.373
3.460
1.361
3.447
1.348
3.449
1.350
3.442
1.343
3.448
1.349
3.479
1.380
3.467
1.368
3.463
1.364
3.707
1.572
3.702
1.575
3.744
1.596
3.722
1.582
3.705
1.570
3.720
1.578
3.708
1.572
3.696
1.564
3.698
1.566
3.693
1.563
3.697
1.571
3.727
1.584
3.717
1.579
3.712
1.575
5.473 5.686 6.260 6.090 6.510 5.853 6.393 6.090 6.510
2.015 2.104 2.295 2.272 2.230 2.201 2.430 2.272 2.230
5.472 5.687 6.262 6.100 6.520 5.855 6.404 6.100 6.520
2.021 2.112 2.305 2.274 2.233 2.203 2.441 2.274 2.233
5.523 5.740 6.318 6.132 6.552 5.906 6.434 6.132 6.552
2.050 2.142 2.339 2.330 2.288 2.254 2.471 2.330 2.288
5.505 5.723 6.301 6.122 6.542 5.890 6.425 6.122 6.542
2.039 2.132 2.327 2.313 2.271 2.238 2.462 2.313 2.271
5.488 5.705 6.283 6.109 6.529 5.872 6.412 6.109 6.529
2.026 2.119 2.314 2.295 2.253 2.220 2.449 2.295 2.253
5.479 5.691 6.263 6.088 6.508 5.857 6.390 6.088 6.508
2.014 2.102 2.293 2.275 2.233 2.205 2.427 2.275 2.233
5.470 5.683 6.255 6.087 6.507 5.849 6.390 6.087 6.507
2.012 2.101 2.292 2.267 2.225 2.197 2.427 2.267 2.225
5.462 5.674 6.247 6.080 6.500 5.841 6.383 6.080 6.500
2.005 2.094 2.285 2.259 2.217 2.189 2.420 2.259 2.217
5.464 5.677 6.250 6.084 6.504 5.844 6.386 6.084 6.504
2.008 2.097 2.289 2.262 2.220 2.192 2.423 2.262 2.220
5.462 5.676 6.250 6.087 6.507 5.844 6.391 6.087 6.507
2.010 2.100 2.292 2.262 2.220 2.192 2.428 2.262 2.220
5.457 5.668 6.241 6.083 6.503 5.835 6.385 6.083 6.503
2.008 2.097 2.288 2.253 2.216 2.183 2.422 2.253 2.216
5.490 5.704 6.278 6.099 6.519 5.869 6.401 6.099 6.519
2.023 2.112 2.304 2.290 2.248 2.217 2.438 2.290 2.248
5.486 5.700 6.274 6.101 6.521 5.866 6.404 6.101 6.521
2.024 2.114 2.306 2.286 2.244 2.214 2.441 2.286 2.244
5.480 5.694 6.268 6.096 6.516 5.860 6.398 6.096 6.516
2.019 2.109 2.301 2.280 2.238 2.208 2.435 2.280 2.238
8mA
16mA
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
16mA
4mA
6mA
8mA
GCLK
PLL
SSTL-18
CLASS II
GCLK
GCLK
PLL
GCLK
GCLK
PLL
SSTL-15
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
1.8-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
1.8-V
HSTL
CLASS II
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
1.5-V
HSTL
CLASS I
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
1–299
I4L
Table 1–136. EP3SE260 Row Pins output Timing Parameters (Part 5 of 5)
Fast Model
C2
C3
C4
C4L
I3
I4
I/O
Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
0.9V
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.478
1.379
3.466
1.367
3.463
1.364
3.542
1.476
3.542
1.476
3.726
1.586
3.714
1.578
3.712
1.578
3.812
1.661
3.812
1.661
5.501 5.718 6.296 6.118 6.538 5.883 6.420 6.118 6.538
2.036 2.128 2.323 2.308 2.266 2.231 2.457 2.308 2.266
5.490 5.706 6.284 6.109 6.529 5.872 6.411 6.109 6.529
2.027 2.119 2.314 2.296 2.254 2.220 2.448 2.296 2.254
5.494 5.711 6.290 6.118 6.538 5.878 6.421 6.118 6.538
2.034 2.127 2.323 2.302 2.260 2.226 2.458 2.302 2.260
5.520 5.723 6.294 6.113 6.564 5.875 6.437 6.113 6.564
2.049 2.137 2.343 2.368 2.264 2.253 2.476 2.368 2.264
5.520 5.723 6.294 6.113 6.564 5.875 6.437 6.113 6.564
2.049 2.137 2.343 2.368 2.264 2.253 2.476 2.368 2.264
4mA
6mA
8mA
—
GCLK
PLL
1.2-V
HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
3.0-V PCI
GCLK
PLL
GCLK
3.0-V
PCI-X
—
GCLK
PLL
Table 1–137 through Table 1–140 show the maximum I/O timing parameters for
EP3SE260 devices for differential I/O standards.
Table 1–137 specifies EP3SE260 column pins input timing parameters for differential
I/O standards.
Table 1–137. EP3SE260 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.153
1.289
1.103
-0.824
-1.153
1.289
1.103
-0.824
-1.161
1.297
1.095
-0.816
-1.161
1.297
1.095
-0.816
-1.221
1.376
1.122
-0.821
-1.221
1.376
1.122
-0.821
-1.233
1.388
1.110
-0.809
-1.233
1.388
1.110
-0.809
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
GCLK
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096
ns
ns
LVDS
tsu
th
GCLK
PLL
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
tsu
th
GCLK
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096
ns
ns
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS I
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–300
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–137. EP3SE260 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.173
1.309
1.083
-0.804
-1.173
1.309
1.083
-0.804
-1.161
1.297
1.095
-0.816
-1.161
1.297
1.095
-0.816
-1.173
1.309
1.083
-0.804
-1.173
1.309
1.083
-0.804
-1.180
1.316
1.076
-0.797
-1.180
1.316
1.076
-0.797
-1.153
1.289
1.103
-0.824
-1.244
1.399
1.099
-0.798
-1.244
1.399
1.099
-0.798
-1.233
1.388
1.110
-0.809
-1.233
1.388
1.110
-0.809
-1.244
1.399
1.099
-0.798
-1.244
1.399
1.099
-0.798
-1.250
1.405
1.093
-0.792
-1.250
1.405
1.093
-0.792
-1.221
1.376
1.122
-0.821
-1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 ns
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
2.133 2.172 2.365 2.272 2.746 2.199 2.388 2.272 2.746
1.863 1.964 2.172 2.064 2.061 1.976 2.184 2.064 2.061
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 ns
-1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS I
2.133 2.172 2.365 2.272 2.746 2.199 2.388 2.272 2.746
1.863 1.964 2.172 2.064 2.061 1.976 2.184 2.064 2.061
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS I
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
-1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
2.133 2.172 2.365 2.272 2.746 2.199 2.388 2.272 2.746
1.863 1.964 2.172 2.064 2.061 1.976 2.184 2.064 2.061
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 ns
-1.898 -1.933 -2.102 -2.022 -2.494 -1.950 -2.117 -2.022 -2.494 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS I
2.133 2.172 2.365 2.272 2.746 2.199 2.388 2.272 2.746
1.863 1.964 2.172 2.064 2.061 1.976 2.184 2.064 2.061
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.471 -1.624 -1.545 -1.527 -1.471 -1.626 -1.545 -1.527 ns
-1.910 -1.938 -2.102 -2.024 -2.493 -1.954 -2.112 -2.024 -2.493 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V SSTL
CLASS II
2.146 2.180 2.368 2.275 2.750 2.206 2.388 2.275 2.750
1.851 1.959 2.172 2.062 2.062 1.972 2.189 2.062 2.062
ns
ns
tsu
th
GCLK
PLL
-1.371 -1.463 -1.621 -1.542 -1.523 -1.464 -1.626 -1.542 -1.523 ns
-1.910 -1.938 -2.102 -2.024 -2.493 -1.954 -2.112 -2.024 -2.493 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS I
2.146 2.180 2.368 2.275 2.750 2.206 2.388 2.275 2.750
1.851 1.959 2.172 2.062 2.062 1.972 2.189 2.062 2.062
ns
ns
tsu
th
GCLK
PLL
-1.371 -1.463 -1.621 -1.542 -1.523 -1.464 -1.626 -1.542 -1.523 ns
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V SSTL
CLASS II
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096
ns
ns
tsu
th
GCLK
PLL
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–301
I/O Timing
Table 1–137. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.153
1.289
1.103
-0.824
-1.161
1.297
1.095
-0.816
-1.221
1.376
1.122
-0.821
-1.233
1.388
1.110
-0.809
-1.879 -1.911 -2.067 -1.987 -2.459 -1.928 -2.084 -1.987 -2.459 ns
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS I
2.114 2.150 2.330 2.237 2.711 2.177 2.355 2.237 2.711
1.882 1.986 2.207 2.099 2.096 1.998 2.217 2.099 2.096
ns
ns
tsu
th
GCLK
PLL
-1.403 -1.493 -1.659 -1.580 -1.562 -1.493 -1.659 -1.580 -1.562 ns
-1.889 -1.922 -2.083 -2.003 -2.475 -1.939 -2.099 -2.003 -2.475 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
2.124 2.161 2.346 2.253 2.727 2.188 2.370 2.253 2.727
1.872 1.975 2.191 2.083 2.080 1.987 2.202 2.083 2.080
ns
ns
tsu
th
GCLK
PLL
-1.393 -1.482 -1.643 -1.564 -1.546 -1.482 -1.644 -1.564 -1.546 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–302
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–138 specifies EP3SE260 row pins input timing parameters for differential I/O
standards.
Table 1–138. EP3SE260 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tsu
th
-1.332
1.476
0.869
-0.581
-1.332
1.476
0.869
-0.581
-1.332
1.476
0.869
-0.581
-1.137
1.274
1.064
-0.783
-1.137
1.274
1.064
-0.783
-1.146
1.283
1.055
-0.774
-1.146
1.283
1.055
-0.774
-1.160
1.297
1.041
-0.760
-1.401
1.563
0.886
-0.578
-1.401
1.563
0.886
-0.578
-1.401
1.563
0.886
-0.578
-1.216
1.369
1.071
-0.772
-1.216
1.369
1.071
-0.772
-1.228
1.381
1.059
-0.760
-1.228
1.381
1.059
-0.760
-1.240
1.393
1.047
-0.748
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
GCLK
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297
ns
ns
LVDS
tsu
th
GCLK
PLL
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
tsu
th
GCLK
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297
ns
ns
MINI-LVDS
RSDS
tsu
th
GCLK
PLL
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.719 -1.648 -1.841 -1.769 -2.221 -1.630 -1.815 -1.769 -2.221 ns
tsu
th
GCLK
1.994 1.939 2.157 2.071 2.526 1.934 2.145 2.071 2.526
1.991 2.205 2.405 2.282 2.297 2.252 2.458 2.282 2.297
ns
ns
tsu
th
GCLK
PLL
-1.475 -1.662 -1.803 -1.711 -1.711 -1.692 -1.839 -1.711 -1.711 ns
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS I
2.088 2.122 2.297 2.206 2.656 2.156 2.330 2.206 2.656
1.866 1.981 2.216 2.098 2.118 1.985 2.221 2.098 2.118
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 ns
-1.849 -1.877 -2.030 -1.953 -2.400 -1.901 -2.052 -1.953 -2.400 ns
tsu
th
GCLK
DIFFERENTIAL
1.2-V
HSTL CLASS II
2.088 2.122 2.297 2.206 2.656 2.156 2.330 2.206 2.656
1.866 1.981 2.216 2.098 2.118 1.985 2.221 2.098 2.118
ns
ns
tsu
th
GCLK
PLL
-1.384 -1.483 -1.663 -1.576 -1.581 -1.474 -1.654 -1.576 -1.581 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS I
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
HSTL CLASS II
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
HSTL CLASS I
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084
ns
ns
tsu
th
GCLK
PLL
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–303
I/O Timing
Table 1–138. EP3SE260 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
GCLK
tsu
th
-1.160
1.297
-1.240
1.393
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690
ns
DIFFERENTIAL
1.8-V
HSTL CLASS II
GCLK
PLL
tsu
1.041
1.047
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084
ns
th
tsu
th
-0.760
-1.146
1.283
1.055
-0.774
-1.146
1.283
1.055
-0.774
-1.160
1.297
1.041
-0.760
-1.160
1.297
1.041
-0.760
-1.169
1.306
1.032
-0.751
-1.169
1.306
1.032
-0.751
-0.748
-1.228
1.381
1.059
-0.760
-1.228
1.381
1.059
-0.760
-1.240
1.393
1.047
-0.748
-1.240
1.393
1.047
-0.748
-1.249
1.402
1.038
-0.739
-1.249
1.402
1.038
-0.739
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS I
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.858 -1.887 -2.046 -1.969 -2.416 -1.910 -2.068 -1.969 -2.416 ns
tsu
th
GCLK
DIFFERENTIAL
1.5-V
SSTL CLASS II
2.097 2.132 2.313 2.222 2.672 2.165 2.346 2.222 2.672
1.857 1.971 2.200 2.082 2.102 1.976 2.205 2.082 2.102
ns
ns
tsu
th
GCLK
PLL
-1.375 -1.473 -1.647 -1.560 -1.565 -1.465 -1.638 -1.560 -1.565 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS I
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084
ns
ns
tsu
th
GCLK
PLL
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.867 -1.897 -2.064 -1.987 -2.434 -1.921 -2.085 -1.987 -2.434 ns
tsu
th
GCLK
DIFFERENTIAL
1.8-V
SSTL CLASS II
2.106 2.142 2.331 2.240 2.690 2.176 2.363 2.240 2.690
1.844 1.961 2.182 2.064 2.084 1.965 2.188 2.064 2.084
ns
ns
tsu
th
GCLK
PLL
-1.363 -1.463 -1.629 -1.542 -1.547 -1.454 -1.621 -1.542 -1.547 ns
-1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS I
2.121 2.156 2.341 2.250 2.701 2.186 2.369 2.250 2.701
1.829 1.945 2.171 2.052 2.073 1.954 2.182 2.052 2.073
ns
ns
tsu
th
GCLK
PLL
-1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 ns
-1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 ns
tsu
th
GCLK
DIFFERENTIAL
2.5-V
SSTL CLASS II
2.121 2.156 2.341 2.250 2.701 2.186 2.369 2.250 2.701
1.829 1.945 2.171 2.052 2.073 1.954 2.182 2.052 2.073
ns
ns
tsu
th
GCLK
PLL
-1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 ns
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–304
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–139 specifies EP3SE260 Column Pins Output Timing parameters for
differential I/O standards.
Table 1–139. EP3SE260 Column Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
VCCL
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.460
1.374
3.456
1.370
3.460
1.374
3.456
1.370
3.460
1.374
3.456
1.370
3.487
1.401
3.477
1.391
3.477
1.391
3.470
1.384
3.469
1.383
3.491
1.405
3.730
1.562
3.733
1.565
3.730
1.562
3.733
1.565
3.730
1.562
3.733
1.565
3.763
1.595
3.753
1.585
3.753
1.585
3.747
1.579
3.745
1.577
3.767
1.599
5.480 5.686 6.242 6.079 6.486 5.828 6.383 6.079 6.486
1.992 2.073 2.282 2.291 2.242 2.188 2.399 2.291 2.242
5.527 5.741 6.304 6.141 6.548 5.887 6.449 6.141 6.548
2.039 2.128 2.344 2.353 2.304 2.247 2.465 2.353 2.304
5.480 5.686 6.242 6.079 6.486 5.828 6.383 6.079 6.486
1.992 2.073 2.282 2.291 2.242 2.188 2.399 2.291 2.242
5.527 5.741 6.304 6.141 6.548 5.887 6.449 6.141 6.548
2.039 2.128 2.344 2.353 2.304 2.247 2.465 2.353 2.304
5.480 5.686 6.242 6.079 6.486 5.828 6.383 6.079 6.486
1.992 2.073 2.282 2.291 2.242 2.188 2.399 2.291 2.242
5.527 5.741 6.304 6.141 6.548 5.887 6.449 6.141 6.548
2.039 2.128 2.344 2.353 2.304 2.247 2.465 2.353 2.304
5.551 5.764 6.326 6.163 6.570 5.908 6.469 6.163 6.570
2.063 2.151 2.366 2.375 2.326 2.268 2.485 2.375 2.326
5.541 5.753 6.316 6.153 6.560 5.897 6.459 6.153 6.560
2.053 2.140 2.356 2.365 2.316 2.257 2.475 2.365 2.316
5.544 5.757 6.320 6.157 6.564 5.902 6.464 6.157 6.564
2.056 2.144 2.360 2.369 2.320 2.262 2.480 2.369 2.320
5.537 5.751 6.314 6.151 6.558 5.895 6.458 6.151 6.558
2.049 2.138 2.354 2.363 2.314 2.255 2.474 2.363 2.314
5.534 5.748 6.311 6.148 6.555 5.892 6.454 6.148 6.555
2.046 2.135 2.351 2.360 2.311 2.252 2.470 2.360 2.311
5.555 5.768 6.330 6.167 6.574 5.912 6.474 6.167 6.574
2.067 2.155 2.370 2.379 2.330 2.272 2.490 2.379 2.330
—
—
LVDS_E_1R
LVDS_E_3R
GCLK
PLL
GCLK
GCLK
PLL
GCLK
MINI-
LVDS_E_1R
—
GCLK
PLL
GCLK
MINI-
LVDS_E_3R
—
GCLK
PLL
GCLK
—
RSDS_E_1R
RSDS_E_3R
GCLK
PLL
GCLK
—
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.2-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.2-V HSTL
CLASS II
16m
A
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–305
I/O Timing
Table 1–139. EP3SE260 Column Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
VCCL
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.481
1.395
3.476
1.390
3.474
1.388
3.466
1.380
3.467
1.381
3.466
1.380
3.478
1.392
3.474
1.388
3.464
1.378
3.462
1.376
3.462
1.376
3.466
1.380
3.756
1.588
3.752
1.584
3.750
1.582
3.741
1.573
3.743
1.575
3.740
1.572
3.753
1.585
3.750
1.582
3.739
1.571
3.737
1.569
3.738
1.570
3.741
1.573
5.534 5.745 6.305 6.142 6.549 5.888 6.447 6.142 6.549
2.046 2.132 2.345 2.354 2.305 2.248 2.463 2.354 2.305
5.534 5.745 6.306 6.143 6.550 5.889 6.449 6.143 6.550
2.046 2.132 2.346 2.355 2.306 2.249 2.465 2.355 2.306
5.533 5.744 6.304 6.141 6.548 5.888 6.448 6.141 6.548
2.045 2.131 2.344 2.353 2.304 2.248 2.464 2.353 2.304
5.523 5.734 6.295 6.132 6.539 5.878 6.438 6.132 6.539
2.035 2.121 2.335 2.344 2.295 2.238 2.454 2.344 2.295
5.529 5.741 6.303 6.140 6.547 5.886 6.447 6.140 6.547
2.041 2.128 2.343 2.352 2.303 2.246 2.463 2.352 2.303
5.512 5.722 6.281 6.118 6.525 5.865 6.423 6.118 6.525
2.024 2.109 2.321 2.330 2.281 2.225 2.439 2.330 2.281
5.530 5.740 6.299 6.136 6.543 5.884 6.442 6.136 6.543
2.042 2.127 2.339 2.348 2.299 2.244 2.458 2.348 2.299
5.531 5.742 6.303 6.140 6.547 5.886 6.446 6.140 6.547
2.043 2.129 2.343 2.352 2.303 2.246 2.462 2.352 2.303
5.520 5.731 6.291 6.128 6.535 5.875 6.434 6.128 6.535
2.032 2.118 2.331 2.340 2.291 2.235 2.450 2.340 2.291
5.518 5.728 6.289 6.126 6.533 5.873 6.432 6.126 6.533
2.030 2.115 2.329 2.338 2.289 2.233 2.448 2.338 2.289
5.521 5.733 6.294 6.131 6.538 5.877 6.438 6.131 6.538
2.033 2.120 2.334 2.343 2.294 2.237 2.454 2.343 2.294
5.518 5.728 6.288 6.125 6.532 5.872 6.431 6.125 6.532
2.030 2.115 2.328 2.337 2.288 2.232 2.447 2.337 2.288
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.5-V HSTL
CLASS II
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V HSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
1.8-V HSTL
CLASS II
16m
A
GCLK
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–306
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–139. EP3SE260 Column Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
VCCL
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
tco
3.492
1.406
3.478
1.392
3.466
1.380
3.466
1.380
3.462
1.376
3.466
1.380
3.467
1.381
3.495
1.409
3.484
1.398
3.479
1.393
3.465
1.379
3.463
1.377
3.467
1.381
3.467
1.381
3.770
1.602
3.756
1.588
3.743
1.575
3.743
1.575
3.739
1.571
3.741
1.573
3.743
1.575
3.773
1.605
3.761
1.593
3.757
1.589
3.742
1.574
3.740
1.572
3.742
1.574
3.743
1.575
5.563 5.776 6.338 6.175 6.582 5.920 6.481 6.175 6.582
2.075 2.163 2.378 2.387 2.338 2.280 2.497 2.387 2.338
5.551 5.765 6.328 6.165 6.572 5.910 6.472 6.165 6.572
2.063 2.152 2.368 2.377 2.328 2.270 2.488 2.377 2.328
5.534 5.747 6.310 6.147 6.554 5.892 6.454 6.147 6.554
2.046 2.134 2.350 2.359 2.310 2.252 2.470 2.359 2.310
5.537 5.751 6.314 6.151 6.558 5.896 6.459 6.151 6.558
2.049 2.138 2.354 2.363 2.314 2.256 2.475 2.363 2.314
5.530 5.743 6.307 6.144 6.551 5.889 6.451 6.144 6.551
2.042 2.130 2.347 2.356 2.307 2.249 2.467 2.356 2.307
5.523 5.734 6.295 6.132 6.539 5.878 6.438 6.132 6.539
2.035 2.121 2.335 2.344 2.295 2.238 2.454 2.344 2.295
5.531 5.744 6.306 6.143 6.550 5.888 6.450 6.143 6.550
2.043 2.131 2.346 2.355 2.306 2.248 2.466 2.355 2.306
5.562 5.774 6.336 6.173 6.580 5.919 6.479 6.173 6.580
2.074 2.161 2.376 2.385 2.336 2.279 2.495 2.385 2.336
5.550 5.762 6.324 6.161 6.568 5.907 6.467 6.161 6.568
2.062 2.149 2.364 2.373 2.324 2.267 2.483 2.373 2.324
5.550 5.763 6.325 6.162 6.569 5.908 6.469 6.162 6.569
2.062 2.150 2.365 2.374 2.325 2.268 2.485 2.374 2.325
5.532 5.744 6.306 6.143 6.550 5.889 6.451 6.143 6.550
2.044 2.131 2.346 2.355 2.306 2.249 2.467 2.355 2.306
5.530 5.742 6.304 6.141 6.548 5.887 6.448 6.141 6.548
2.042 2.129 2.344 2.353 2.304 2.247 2.464 2.353 2.304
5.522 5.732 6.292 6.129 6.536 5.876 6.435 6.129 6.536
2.034 2.119 2.332 2.341 2.292 2.236 2.451 2.341 2.292
5.530 5.742 6.304 6.141 6.548 5.887 6.448 6.141 6.548
2.042 2.129 2.344 2.353 2.304 2.247 2.464 2.353 2.304
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.5-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
8mA
DIFFERENTIAL
1.5-V SSTL
CLASS II
GCLK
PLL
GCLK
16m
A
GCLK
PLL
GCLK
4mA
6mA
8mA
GCLK
PLL
GCLK
GCLK
PLL
DIFFERENTIAL
1.8-V SSTL
CLASS I
GCLK
GCLK
PLL
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
8mA
DIFFERENTIAL
1.8-V SSTL
CLASS II
GCLK
PLL
GCLK
16m
A
GCLK
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–307
I/O Timing
Table 1–139. EP3SE260 Column Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
VCCL
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
=
VCCL
1.1V
=
VCCL
1.1V
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
0.9V
GCLK
ns
ns
ns
ns
ns
ns
ns
ns
tco
tco
tco
tco
tco
tco
tco
tco
3.483
1.397
3.483
1.397
3.473
1.387
3.466
1.380
3.760
1.592
3.760
1.592
3.750
1.582
3.742
1.574
5.546 5.757 6.318 6.155 6.562 5.902 6.461 6.155 6.562
2.058 2.144 2.358 2.367 2.318 2.262 2.477 2.367 2.318
5.546 5.757 6.318 6.155 6.562 5.902 6.461 6.155 6.562
2.058 2.144 2.358 2.367 2.318 2.262 2.477 2.367 2.318
5.536 5.747 6.308 6.145 6.552 5.892 6.452 6.145 6.552
2.048 2.134 2.348 2.357 2.308 2.252 2.468 2.357 2.308
5.522 5.732 6.292 6.129 6.536 5.876 6.435 6.129 6.536
2.034 2.119 2.332 2.341 2.292 2.236 2.451 2.341 2.292
8mA
GCLK
PLL
DIFFERENTIAL
2.5-V SSTL
CLASS I
GCLK
10m
A
GCLK
PLL
GCLK
12m
A
GCLK
PLL
GCLK
DIFFERENTIAL
2.5-V SSTL
CLASS II
16m
A
GCLK
PLL
Table 1–140 specifies EP3SE260 Row Pins Output Timing parameters for differential
I/O standards.
Table 1–140. EP3SE260 Row Pins output Timing Parameters (Part 1 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
LVDS
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.149
1.067
3.527
1.445
3.509
1.427
3.149
1.067
3.527
1.445
3.509
1.427
3.149
1.067
3.372
1.206
3.802
1.636
3.792
1.626
3.372
1.206
3.802
1.636
3.792
1.626
3.372
1.206
4.930 5.111 5.636 5.477 5.864 5.235 5.760 5.477 5.864
1.444 1.503 1.675 1.692 1.626 1.599 1.774 1.692 1.626
5.588 5.798 6.363 6.197 6.576 5.946 6.513 6.197 6.576
2.102 2.190 2.402 2.412 2.338 2.310 2.527 2.412 2.338
5.626 5.844 6.417 6.251 6.630 5.997 6.574 6.251 6.630
2.140 2.236 2.456 2.466 2.392 2.361 2.588 2.466 2.392
4.930 5.111 5.636 5.477 5.864 5.235 5.760 5.477 5.864
1.444 1.503 1.675 1.692 1.626 1.599 1.774 1.692 1.626
5.588 5.798 6.363 6.197 6.576 5.946 6.513 6.197 6.576
2.102 2.190 2.402 2.412 2.338 2.310 2.527 2.412 2.338
5.626 5.844 6.417 6.251 6.630 5.997 6.574 6.251 6.630
2.140 2.236 2.456 2.466 2.392 2.361 2.588 2.466 2.392
4.930 5.111 5.636 5.477 5.864 5.235 5.760 5.477 5.864
1.444 1.503 1.675 1.692 1.626 1.599 1.774 1.692 1.626
—
—
—
—
—
—
—
GCLK
tco
PLL
GCLK tco
LVDS_E_1R
LVDS_E_3R
MINI-LVDS
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_1R
GCLK
tco
PLL
GCLK tco
MINI-
LVDS_E_3R
GCLK
tco
PLL
GCLK tco
RSDS
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–308
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–140. EP3SE260 Row Pins output Timing Parameters (Part 2 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
RSDS_E_1R
RSDS_E_3R
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.527
1.445
3.509
1.427
3.553
1.481
3.539
1.467
3.535
1.463
3.551
1.479
3.540
1.468
3.537
1.465
3.548
1.476
3.538
1.466
3.524
1.452
3.521
1.449
3.518
1.446
3.802
1.636
3.792
1.626
3.835
1.679
3.821
1.665
3.817
1.661
3.832
1.676
3.822
1.666
3.819
1.663
3.829
1.673
3.820
1.664
3.806
1.650
3.802
1.646
3.800
1.644
5.588 5.798 6.363 6.197 6.576 5.946 6.513 6.197 6.576
2.102 2.190 2.402 2.412 2.338 2.310 2.527 2.412 2.338
5.626 5.844 6.417 6.251 6.630 5.997 6.574 6.251 6.630
2.140 2.236 2.456 2.466 2.392 2.361 2.588 2.466 2.392
5.662 5.878 6.450 6.284 6.663 6.030 6.603 6.284 6.663
2.186 2.280 2.499 2.509 2.435 2.404 2.627 2.509 2.435
5.649 5.865 6.437 6.271 6.650 6.016 6.590 6.271 6.650
2.173 2.267 2.486 2.496 2.422 2.390 2.614 2.496 2.422
5.647 5.865 6.438 6.272 6.651 6.016 6.592 6.272 6.651
2.171 2.267 2.487 2.497 2.423 2.390 2.616 2.497 2.423
5.648 5.862 6.432 6.266 6.645 6.013 6.585 6.266 6.645
2.172 2.264 2.481 2.491 2.417 2.387 2.609 2.491 2.417
5.644 5.858 6.429 6.263 6.642 6.010 6.582 6.263 6.642
2.168 2.260 2.478 2.488 2.414 2.384 2.606 2.488 2.414
5.642 5.856 6.427 6.261 6.640 6.008 6.581 6.261 6.640
2.166 2.258 2.476 2.486 2.412 2.382 2.605 2.486 2.412
5.643 5.857 6.426 6.260 6.639 6.007 6.579 6.260 6.639
2.167 2.259 2.475 2.485 2.411 2.381 2.603 2.485 2.411
5.641 5.855 6.425 6.259 6.638 6.007 6.579 6.259 6.638
2.165 2.257 2.474 2.484 2.410 2.381 2.603 2.484 2.410
5.626 5.840 6.411 6.245 6.624 5.992 6.564 6.245 6.624
2.150 2.242 2.460 2.470 2.396 2.366 2.588 2.470 2.396
5.622 5.836 6.407 6.241 6.620 5.988 6.560 6.241 6.620
2.146 2.238 2.456 2.466 2.392 2.362 2.584 2.466 2.392
5.623 5.839 6.410 6.244 6.623 5.991 6.564 6.244 6.623
2.147 2.241 2.459 2.469 2.395 2.365 2.588 2.469 2.395
—
GCLK
tco
PLL
GCLK tco
—
GCLK
tco
PLL
GCLK tco
4mA
6mA
8mA
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.2-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
HSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–309
I/O Timing
Table 1–140. EP3SE260 Row Pins output Timing Parameters (Part 3 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
GCLK tco
3.519
1.447
3.568
1.496
3.544
1.472
3.526
1.454
3.572
1.500
3.557
1.485
3.546
1.474
3.526
1.454
3.523
1.451
3.528
1.456
3.521
1.449
3.800
1.644
3.853
1.697
3.829
1.673
3.810
1.654
3.856
1.700
3.841
1.685
3.830
1.674
3.810
1.654
3.806
1.650
3.810
1.654
3.803
1.647
5.613 5.827 6.397 6.231 6.610 5.978 6.550 6.231 6.610
2.137 2.229 2.446 2.456 2.382 2.352 2.574 2.456 2.382
5.684 5.900 6.473 6.307 6.686 6.052 6.626 6.307 6.686
2.208 2.302 2.522 2.532 2.458 2.426 2.650 2.532 2.458
5.666 5.883 6.456 6.290 6.669 6.035 6.611 6.290 6.669
2.190 2.285 2.505 2.515 2.441 2.409 2.635 2.515 2.441
5.644 5.861 6.434 6.268 6.647 6.013 6.589 6.268 6.647
2.168 2.263 2.483 2.493 2.419 2.387 2.613 2.493 2.419
5.684 5.900 6.472 6.306 6.685 6.052 6.626 6.306 6.685
2.208 2.302 2.521 2.531 2.457 2.426 2.650 2.531 2.457
5.670 5.885 6.457 6.291 6.670 6.037 6.611 6.291 6.670
2.194 2.287 2.506 2.516 2.442 2.411 2.635 2.516 2.442
5.665 5.882 6.454 6.288 6.667 6.034 6.609 6.288 6.667
2.189 2.284 2.503 2.513 2.439 2.408 2.633 2.513 2.439
5.642 5.858 6.431 6.265 6.644 6.011 6.585 6.265 6.644
2.166 2.260 2.480 2.490 2.416 2.385 2.609 2.490 2.416
5.638 5.855 6.427 6.261 6.640 6.007 6.582 6.261 6.640
2.162 2.257 2.476 2.486 2.412 2.381 2.606 2.486 2.412
5.629 5.843 6.413 6.247 6.626 5.994 6.566 6.247 6.626
2.153 2.245 2.462 2.472 2.398 2.368 2.590 2.472 2.398
5.628 5.844 6.416 6.250 6.629 5.997 6.571 6.250 6.629
2.152 2.246 2.465 2.475 2.401 2.371 2.595 2.475 2.401
DIFFERENTIAL
1.8-V HSTL
CLASS II
16mA
4mA
6mA
8mA
4mA
6mA
8mA
10mA
12mA
8mA
16mA
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.5-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
1.8-V
SSTL CLASS I
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
PLL
GCLK tco
GCLK
tco
DIFFERENTIAL
1.8-V
SSTL CLASS II
PLL
GCLK tco
GCLK
tco
PLL
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–310
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–140. EP3SE260 Row Pins output Timing Parameters (Part 4 of 4)
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
I/O Standard
Clock
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
ns
ns
ns
ns
ns
ns
GCLK tco
3.559
1.477
3.541
1.459
3.527
1.445
3.842
1.676
3.825
1.659
3.809
1.643
5.666 5.881 6.452 6.286 6.665 6.033 6.606 6.286 6.665
2.180 2.273 2.491 2.501 2.427 2.397 2.620 2.501 2.427
5.651 5.866 6.437 6.271 6.650 6.018 6.591 6.271 6.650
2.165 2.258 2.476 2.486 2.412 2.382 2.605 2.486 2.412
5.628 5.842 6.412 6.246 6.625 5.994 6.566 6.246 6.625
2.142 2.234 2.451 2.461 2.387 2.358 2.580 2.461 2.387
8mA
GCLK
tco
DIFFERENTIAL
2.5-V
SSTL CLASS I
PLL
GCLK tco
12mA
16mA
GCLK
tco
PLL
GCLK tco
DIFFERENTIAL
2.5-V
SSTL CLASS II
GCLK
tco
PLL
Table 1–141 and Table 1–142 show EP3SE260 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when I/O pin is driven using regional clock. This applies for all I/O standards
supported by Stratix III devices.
Table 1–141 specifies EP3SE260 Column Pin delay adders when using the regional
clock.
Table 1–141. EP3SE260 Column Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.233
-0.036
-0.204
1.899
0.311
0.028
-0.237
1.965
0.488 0.489 0.45 0.439 0.515 0.416 0.458 0.439 0.515
0.059 0.06 0.113 0.11 -0.005 -0.038 0.121
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
0.11 -0.005 ns
-0.334 -0.331 -0.413 -0.405 -0.44 -0.32 -0.371 -0.405 -0.44
3.193 3.323 3.677 3.512 3.802 3.346 3.705 3.512 3.802
ns
ns
Table 1–142 specifies EP3SE260 Row Pin delay adders when using the regional clock
in Stratix III devices.
Table 1–142. EP3SE260 Row Pin Delay Adders for Regional Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
RCLK input adder
0.244
0.124
-0.256
-0.134
0.293
0.134
-0.289
-0.147
0.438 0.412 0.471 0.427 0.577 0.421 0.452 0.427 0.577
0.21 0.215 0.234 0.228 0.297 0.217 0.239 0.228 0.297
ns
ns
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
-0.418 -0.424 -0.484 -0.438 -0.591 -0.443 -0.464 -0.438 -0.591 ns
-0.228 -0.233 -0.254 -0.261 -0.322 -0.236 -0.262 -0.261 -0.322 ns
Dedicated Clock Pin Timing
Table 1–143 to Table 1–203 show clock pin timing for Stratix III devices when the clock
is driven by global clock, regional clock, periphery clock and a PLL.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–311
I/O Timing
Table 1–143 describes Stratix III clock timing parameters.
Table 1–143. Stratix III Clock Timing Parameters
Symbol
Parameter
tCIN
Delay from clock pad to I/O input register
tCOUT
Delay from clock pad to I/O output register
Delay from PLL inclkpad to I/O input register
Delay from PLL inclkpad to I/O output register
tPLLCIN
tPLLCOUT
EP3SL50 Clock Timing Parameters
Table 1–144 and Table 1–145 show the global clock timing parameters for EP3SL50
devices.
Table 1–144. EP3SL50 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.736
1.736
-0.018
-0.018
1.737
1.737
-0.026
-0.026
2.436 2.691 3.056 2.925 3.433 2.691 3.056 2.925 3.433
2.436 2.691 3.056 2.925 3.433 2.691 3.056 2.925 3.433
-0.261 -0.312 -0.251 -0.230 -0.011 -0.312 0.161 -0.230 -0.011
-0.261 -0.312 -0.251 -0.230 -0.011 -0.312 0.161 -0.230 -0.011
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–145. EP3SL50 Row Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.732
1.650
0.048
-0.034
1.843
1.752
0.116
0.025
2.527 2.758 3.099 2.997 3.227 2.811 3.146 3.055 3.260
2.385 2.595 2.918 2.826 3.068 2.641 2.957 2.876 3.101
-0.142 -0.216 -0.181 -0.136 -0.188 -0.173 0.265 -0.087 -0.230
-0.284 -0.379 -0.362 -0.307 -0.347 -0.343 0.076 -0.266 -0.389
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–146 and Table 1–147 show the regional clock timing parameters for EP3SL50
devices.
Table 1–146. EP3SL50 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.689
1.689
-0.019
-0.019
1.669
1.669
-0.025
-0.025
2.371 2.645 3.004 2.719 3.136 2.645 3.009 2.719 3.136
2.371 2.645 3.004 2.719 3.136 2.645 3.009 2.719 3.136
-0.264 -0.315 -0.256 -0.236 -0.017 -0.315 0.224 -0.236 -0.017
-0.264 -0.315 -0.256 -0.236 -0.017 -0.315 0.224 -0.236 -0.017
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–312
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–147. EP3SL50 Row Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.636
1.554
0.018
-0.064
1.729
1.638
0.084
-0.007
2.356 2.567 2.894 2.800 2.964 2.622 2.941 2.853 2.997
2.214 2.404 2.713 2.629 2.805 2.452 2.752 2.674 2.838
-0.178 -0.255 -0.222 -0.169 -0.226 -0.203 0.298 -0.123 -0.272
-0.320 -0.418 -0.403 -0.340 -0.385 -0.373 0.109 -0.302 -0.431
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–148 and Table 1–149 show the periphery clock timing parameters for EP3SL50
devices.
Table 1–148. EP3SL50 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.468
1.468
-0.081
-0.081
1.469
1.469
-0.081
-0.081
2.143 2.418 2.797 2.668 3.219 2.418 2.801 2.668 3.219
2.143 2.418 2.797 2.668 3.219 2.418 2.801 2.668 3.219
-0.327 -0.383 -0.334 -0.310 -0.105 -0.383 0.273 -0.310 -0.105
-0.327 -0.383 -0.334 -0.310 -0.105 -0.383 0.273 -0.310 -0.105
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–149. EP3SL50 Row Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.482
1.400
-0.014
-0.096
1.556
1.465
0.042
-0.049
2.223 2.488 2.859 2.740 3.034 2.539 2.897 2.785 3.056
2.078 2.325 2.678 2.569 2.875 2.369 2.708 2.606 2.897
-0.222 -0.299 -0.278 -0.224 -0.295 -0.256 0.368 -0.177 -0.257
-0.364 -0.462 -0.459 -0.395 -0.454 -0.426 0.179 -0.356 -0.416
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SL70 Clock Timing Parameters
Table 1–150 and Table 1–151 show the global clock timing specifications for EP3SL70
devices.
.
Table 1–150. EP3SL70 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.749
1.749
-0.012
-0.012
1.735
1.735
-0.021
-0.021
2.434 2.702 3.056 2.950 3.403 2.702 3.056 2.950 3.403
2.434 2.702 3.056 2.950 3.403 2.702 3.056 2.950 3.403
-0.255 -0.306 -0.251 -0.203 -0.044 -0.306 0.161 -0.203 -0.044
-0.255 -0.306 -0.251 -0.203 -0.044 -0.306 0.161 -0.203 -0.044
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–313
I/O Timing
Table 1–151. EP3SL70 Row Pin Global Clock Timing Specifications
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.732
1.650
0.051
-0.031
1.840
1.749
0.115
0.024
2.524 2.758 3.083 2.986 3.227 2.811 3.157 3.042 3.260
2.382 2.595 2.902 2.815 3.068 2.641 2.968 2.863 3.101
-0.144 -0.219 -0.193 -0.144 -0.188 -0.170 0.275 -0.097 -0.234
-0.286 -0.382 -0.374 -0.315 -0.347 -0.340 0.086 -0.276 -0.393
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–152 and Table 1–153 show the regional clock timing parameters for EP3SL70
devices.
Table 1–152. EP3SL70 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.689
1.689
-0.011
-0.011
1.689
1.689
-0.022
-0.022
2.388 2.649 3.004 2.723 3.132 2.649 3.014 2.723 3.132
2.388 2.649 3.004 2.723 3.132 2.649 3.014 2.723 3.132
-0.261 -0.308 -0.256 -0.207 -0.054 -0.308 0.224 -0.207 -0.054
-0.261 -0.308 -0.256 -0.207 -0.054 -0.308 0.224 -0.207 -0.054
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–153. EP3SL70 Row Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.637
1.555
0.018
-0.064
1.726
1.635
0.085
-0.006
2.353 2.566 2.885 2.786 2.964 2.625 2.948 2.839 3.001
2.211 2.403 2.704 2.615 2.805 2.455 2.759 2.660 2.842
-0.176 -0.252 -0.230 -0.180 -0.226 -0.203 0.307 -0.139 -0.272
-0.318 -0.415 -0.411 -0.351 -0.385 -0.373 0.118 -0.318 -0.431
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–154 and Table 1–155 show the periphery clock timing parameters for EP3SL70
devices.
Table 1–154. EP3SL70 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.465
1.465
-0.068
-0.068
1.468
1.468
-0.083
-0.083
2.142 2.410 2.792 2.673 3.220 2.410 2.802 2.673 3.220
2.142 2.410 2.792 2.673 3.220 2.410 2.802 2.673 3.220
-0.330 -0.370 -0.334 -0.288 -0.133 -0.370 0.273 -0.288 -0.133
-0.330 -0.370 -0.334 -0.288 -0.133 -0.370 0.273 -0.288 -0.133
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–314
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–155. EP3SL70 Row Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.482
1.400
-0.019
-0.101
1.558
1.467
0.039
-0.052
2.227 2.488 2.851 2.727 3.031 2.539 2.905 2.777 3.056
2.082 2.325 2.670 2.556 2.872 2.369 2.716 2.598 2.897
-0.225 -0.302 -0.291 -0.235 -0.295 -0.261 0.376 -0.188 -0.257
-0.367 -0.465 -0.472 -0.406 -0.454 -0.431 0.187 -0.367 -0.416
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SL110 Clock Timing Parameters
Table 1–156 and Table 1–157 show the global clock timing parameters for EP3SL110
devices.
.
Table 1–156. EP3SL110 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.909
1.909
-0.048
-0.048
1.907
1.907
-0.050
-0.050
2.674 2.936 3.285 3.182 3.700 2.936 3.285 3.182 3.700
2.674 2.936 3.285 3.182 3.700 2.936 3.285 3.182 3.700
-0.274 -0.330 -0.290 -0.251 -0.032 -0.330 -0.290 -0.251 -0.032
-0.274 -0.330 -0.290 -0.251 -0.032 -0.330 -0.290 -0.251 -0.032
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–157. EP3SL110 Row Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Unit
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.882
1.800
-0.002
-0.084
2.014
1.923
0.059
-0.032
2.754 2.975 3.344 3.221 3.511 3.062 3.413 3.287 3.551
2.612 2.812 3.163 3.050 3.352 2.892 3.224 3.108 3.392
-0.202 -0.271 -0.231 -0.184 -0.212 -0.219 -0.184 -0.138 -0.260
-0.347 -0.434 -0.412 -0.355 -0.371 -0.389 -0.373 -0.317 -0.419
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–158 and Table 1–159 show the regional clock timing parameters for EP3SL110
devices.
Table 1–158. EP3SL110 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.689
1.689
-0.036
-0.036
1.687
1.687
-0.038
-0.038
2.360 2.600 2.924 2.836 3.241 2.600 2.924 2.836 3.241
2.360 2.600 2.924 2.836 3.241 2.600 2.924 2.836 3.241
-0.262 -0.317 -0.278 -0.239 -0.020 -0.317 -0.278 -0.239 -0.020
-0.262 -0.317 -0.278 -0.239 -0.020 -0.317 -0.278 -0.239 -0.020
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–315
I/O Timing
Table 1–159. EP3SL110 Row Pin Regional Clock Timing Specifications
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.684
1.602
0.008
-0.074
1.792
1.701
0.071
-0.020
2.440 2.644 2.985 2.879 3.044 2.720 3.044 2.938 3.083
2.298 2.481 2.804 2.708 2.885 2.550 2.855 2.759 2.924
-0.189 -0.276 -0.218 -0.188 -0.214 -0.209 -0.174 -0.141 -0.263
-0.334 -0.439 -0.399 -0.359 -0.373 -0.379 -0.363 -0.320 -0.422
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–160 and Table 1–161 show the periphery clock timing parameters for
EP3SL110 devices.
.
Table 1–160. EP3SL110 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.541
1.541
-0.029
-0.029
1.538
1.538
-0.031
-0.031
2.257 2.539 2.931 2.810 3.345 2.539 2.931 2.810 3.345
2.257 2.539 2.931 2.810 3.345 2.539 2.931 2.810 3.345
-0.253 -0.310 -0.276 -0.222 -0.020 -0.310 -0.276 -0.222 -0.020
-0.253 -0.310 -0.276 -0.222 -0.020 -0.310 -0.276 -0.222 -0.020
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–161. EP3SL110 Row Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.430
1.348
0.015
-0.067
1.503
1.412
0.072
-0.019
2.156 2.416 2.783 2.665 2.926 2.465 2.828 2.711 2.951
2.011 2.253 2.602 2.494 2.767 2.295 2.639 2.532 2.792
-0.188 -0.267 -0.219 -0.180 -0.214 -0.206 -0.170 -0.133 -0.263
-0.333 -0.430 -0.400 -0.351 -0.373 -0.376 -0.359 -0.312 -0.422
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SL150 Clock Timing Parameters
Table 1–162 and Table 1–163 show the global clock timing parameters for EP3SL150
devices.
Table 1–162. EP3SL150 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Unit
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.898
1.898
-0.054
-0.054
1.926
1.926
-0.028
-0.028
2.692 2.920 3.294 3.170 3.719 2.920 3.294 3.170 3.719
2.692 2.920 3.294 3.170 3.719 2.920 3.294 3.170 3.719
-0.252 -0.342 -0.296 -0.239 -0.018 -0.342 -0.296 -0.239 -0.018
-0.252 -0.342 -0.296 -0.239 -0.018 -0.342 -0.296 -0.239 -0.018
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–316
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–163. EP3SL150 Row Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.868
1.786
0.007
-0.075
2.010
1.919
0.059
-0.032
2.750 2.982 3.347 3.224 3.506 3.048 3.400 3.293 3.549
2.608 2.819 3.166 3.053 3.347 2.878 3.211 3.114 3.390
-0.202 -0.255 -0.231 -0.184 -0.214 -0.210 -0.173 -0.122 -0.249
-0.347 -0.418 -0.412 -0.355 -0.373 -0.380 -0.362 -0.301 -0.408
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–164 and Table 1–165 show the regional clock timing parameters for EP3SL150
devices.
Table 1–164. EP3SL150 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.683
1.683
-0.043
-0.043
1.701
1.701
-0.016
-0.016
2.375 2.595 2.936 2.833 3.255 2.595 2.936 2.833 3.255
2.375 2.595 2.936 2.833 3.255 2.595 2.936 2.833 3.255
-0.240 -0.329 -0.284 -0.227 -0.005 -0.329 -0.284 -0.227 -0.005
-0.240 -0.329 -0.284 -0.227 -0.005 -0.329 -0.284 -0.227 -0.005
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–165. EP3SL150 Row Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.683
1.601
-0.007
-0.089
1.793
1.702
0.068
-0.023
2.441 2.659 2.987 2.875 3.042 2.719 3.047 2.951 3.096
2.299 2.496 2.806 2.704 2.883 2.549 2.858 2.772 2.937
-0.192 -0.269 -0.221 -0.188 -0.211 -0.226 -0.186 -0.135 -0.260
-0.337 -0.432 -0.402 -0.359 -0.370 -0.396 -0.375 -0.314 -0.419
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–166 and Table 1–167 show the periphery clock timing parameters for
EP3SL150 devices.
Table 1–166. EP3SL150 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.537
1.537
-0.040
-0.040
1.550
1.550
-0.012
-0.012
2.268 2.535 2.929 2.812 3.354 2.535 2.929 2.812 3.354
2.268 2.535 2.929 2.812 3.354 2.535 2.929 2.812 3.354
-0.235 -0.326 -0.267 -0.234 0.002 -0.326 -0.267 -0.234 0.002
-0.235 -0.326 -0.267 -0.234 0.002 -0.326 -0.267 -0.234 0.002
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–317
I/O Timing
Table 1–167. EP3SL150 Row Pin Periphery Clock Timing Specifications
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.438
1.356
0.002
-0.080
1.505
1.414
0.076
-0.015
2.159 2.429 2.783 2.657 2.934 2.475 2.838 2.725 2.972
2.014 2.266 2.602 2.486 2.775 2.305 2.649 2.546 2.813
-0.183 -0.266 -0.217 -0.185 -0.206 -0.220 -0.182 -0.132 -0.260
-0.328 -0.429 -0.398 -0.356 -0.365 -0.390 -0.371 -0.311 -0.419
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SL200 Clock Timing Parameters
Table 1–168 and Table 1–169 show the global clock timing parameters for EP3SL200
devices.
Table 1–168. EP3SL200 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Unit
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.237
2.237
0.032
0.032
2.264
2.264
0.060
0.060
3.331 3.416 3.842 3.686 4.345 3.416 3.834 3.686 4.345
3.331 3.416 3.842 3.686 4.345 3.416 3.834 3.686 4.345
-0.177 -0.219 -0.137 -0.122 0.088 -0.219 0.287 -0.122 0.088
-0.177 -0.219 -0.137 -0.122 0.088 -0.219 0.287 -0.122 0.088
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–169. EP3SL200 Row Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.208
2.126
0.102
0.020
2.371
2.280
0.174
0.083
3.453 3.526 3.900 3.747 4.190 3.601 3.977 3.747 4.190
3.301 3.366 3.719 3.576 4.031 3.433 3.788 3.576 4.031
-0.085 -0.115 -0.076 -0.043 -0.063 -0.067 0.409 -0.043 -0.063
-0.237 -0.278 -0.257 -0.214 -0.222 -0.237 0.220 -0.214 -0.222
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–170 and Table 1–171 show the regional clock timing parameters for EP3SL200.
Table 1–170. EP3SL200 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.006
2.006
0.059
0.059
2.035
2.035
0.086
0.086
3.020 3.113 3.494 3.213 3.743 3.113 3.531 3.213 3.743
3.020 3.113 3.494 3.213 3.743 3.113 3.531 3.213 3.743
-0.150 -0.191 -0.109 -0.094 0.116 -0.191 0.291 -0.094 0.116
-0.150 -0.191 -0.109 -0.094 0.116 -0.191 0.291 -0.094 0.116
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–318
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–171. EP3SL200 Row Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.937
1.855
0.126
0.044
2.065
1.974
0.197
0.106
3.000 3.070 3.414 3.275 3.597 3.139 3.479 3.275 3.597
2.848 2.910 3.233 3.104 3.438 2.971 3.290 3.104 3.438
-0.059 -0.091 -0.051 -0.036 -0.041 -0.043 0.410 -0.036 -0.041
-0.211 -0.254 -0.232 -0.207 -0.200 -0.213 0.221 -0.207 -0.200
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–172 and Table 1–173 show the periphery clock timing parameters for
EP3SL200 devices.
Table 1–172. EP3SL200 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.720
1.720
0.037
0.037
1.712
1.712
0.064
0.064
2.615 2.776 3.177 3.044 3.660 2.776 3.177 3.044 3.660
2.615 2.776 3.177 3.044 3.660 2.776 3.177 3.044 3.660
-0.173 -0.213 -0.135 -0.118 0.090 -0.213 0.292 -0.118 0.090
-0.173 -0.213 -0.135 -0.118 0.090 -0.213 0.292 -0.118 0.090
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–173. EP3SL200 Row Pin Periphery Clock Timing Specifications -
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.501
1.419
0.105
0.023
1.575
1.484
0.174
0.083
2.380 2.518 2.892 2.761 3.077 2.567 2.938 2.761 3.077
2.225 2.355 2.711 2.590 2.918 2.397 2.749 2.590 2.918
-0.081 -0.118 -0.077 -0.061 -0.063 -0.067 0.411 -0.061 -0.063
-0.233 -0.281 -0.258 -0.232 -0.222 -0.237 0.222 -0.232 -0.222
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SL340 Clock Timing Parameters
Table 1–174 and Table 1–175 show the global clock timing parameters for EP3S340
devices.
Table 1–174. EP3SL340 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.357
2.357
0.091
0.091
2.331
2.331
0.058
0.058
3.440 3.566 3.938 3.807 4.482 3.566 3.938 3.807 4.482
3.440 3.566 3.938 3.807 4.482 3.566 3.938 3.807 4.482
-0.165 -0.152 -0.140 -0.096 0.111 -0.152 -0.140 -0.096 0.111
-0.165 -0.152 -0.140 -0.096 0.111 -0.152 -0.140 -0.096 0.111
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–319
I/O Timing
Table 1–175. EP3SL340 Row Pin Global Clock Timing Specifications
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.293
2.211
0.121
0.039
2.479
2.388
0.210
0.119
3.608 3.630 4.020 3.880 4.324 3.746 4.099 3.977 4.369
3.456 3.470 3.839 3.709 4.165 3.578 3.910 3.798 4.210
-0.034 -0.098 -0.045 -0.001 -0.042 -0.031 0.005 0.051 -0.083
-0.186 -0.261 -0.226 -0.172 -0.201 -0.201 -0.184 -0.128 -0.242
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–176 and Table 1–177 show the regional clock timing parameters for EP3S340
devices.
Table 1–176. EP3SL340 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.031
2.031
0.127
0.127
2.013
2.013
0.094
0.094
2.958 3.073 3.435 3.308 3.803 3.073 3.435 3.308 3.803
2.958 3.073 3.435 3.308 3.803 3.073 3.435 3.308 3.803
-0.128 -0.116 -0.104 -0.061 0.148 -0.116 -0.104 -0.061 0.148
-0.128 -0.116 -0.104 -0.061 0.148 -0.116 -0.104 -0.061 0.148
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–177. EP3SL340 Row Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.998
1.916
0.157
0.075
2.161
2.070
0.248
0.157
3.129 3.149 3.501 3.376 3.648 3.242 3.570 3.463 3.707
2.977 2.989 3.320 3.205 3.492 3.074 3.381 3.284 3.551
0.006 -0.069 -0.009 0.017 -0.011 0.003 0.039 0.093 -0.057
-0.146 -0.232 -0.190 -0.154 -0.170 -0.167 -0.150 -0.086 -0.216
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–178 and Table 1–179 show the periphery clock timing parameters for
EP3SL340 devices.
Table 1–178. EP3SL340 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.778
1.778
0.086
0.086
1.760
1.760
0.061
0.061
2.687 2.847 3.240 3.099 3.718 2.847 3.240 3.099 3.718
2.687 2.847 3.240 3.099 3.718 2.847 3.240 3.099 3.718
-0.164 -0.161 -0.140 -0.097 0.101 -0.161 -0.140 -0.097 0.101
-0.164 -0.161 -0.140 -0.097 0.101 -0.161 -0.140 -0.097 0.101
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–320
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–179. EP3SL340 Row Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.524
1.442
0.116
0.034
1.616
1.525
0.211
0.120
2.435 2.567 2.958 2.823 3.141 2.605 3.002 2.861 3.165
2.280 2.404 2.777 2.652 2.982 2.435 2.813 2.682 3.006
-0.039 -0.116 -0.055 -0.030 -0.051 -0.040 -0.006 0.050 -0.098
-0.191 -0.279 -0.236 -0.201 -0.210 -0.210 -0.195 -0.129 -0.257
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SE50 Clock Timing Parameters
Table 1–180 and Table 1–181 show the global clock timing parameters for EP3SE50
devices.
Table 1–180. EP3SE50 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.786
1.786
0.023
0.083
1.789
1.789
0.027
0.103
2.495 2.748 3.111 2.993 3.489 2.748 3.105 2.993 3.489
2.495 2.748 3.111 2.993 3.489 2.748 3.105 2.993 3.489
-0.204 -0.268 -0.226 -0.180 0.025 -0.268 0.249 -0.180 0.025
-0.068 -0.131 -0.226 -0.010 0.025 -0.131 0.249 -0.010 0.025
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–181. EP3SE50 Row Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.739
1.657
0.044
-0.038
1.849
1.758
0.117
0.026
2.536 2.769 3.112 3.010 3.250 2.830 3.171 3.069 3.276
2.394 2.606 2.931 2.839 3.091 2.660 2.982 2.890 3.117
-0.143 -0.220 -0.183 -0.135 -0.189 -0.171 0.345 -0.088 -0.242
-0.285 -0.383 -0.364 -0.306 -0.348 -0.341 0.156 -0.267 -0.401
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–182 and Table 1–183 show the regional clock timing parameters for EP3SE50
devices.
Table 1–182. EP3SE50 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.711
1.711
0.034
0.106
1.721
1.721
0.038
0.102
2.429 2.679 3.053 2.767 3.191 2.679 3.053 2.767 3.191
2.429 2.679 3.053 2.767 3.191 2.679 3.053 2.767 3.191
-0.193 -0.255 -0.212 -0.168 0.040 -0.255 0.263 -0.168 0.040
-0.074 -0.101 -0.212 -0.168 0.040 -0.101 0.263 -0.168 0.040
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–321
I/O Timing
Table 1–183. EP3SE50 Row Pin Regional Clock Timing Specifications
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.640
1.558
0.020
-0.062
1.732
1.641
0.091
0.000
2.361 2.580 2.905 2.810 2.977 2.636 2.960 2.868 3.003
2.219 2.417 2.724 2.639 2.818 2.466 2.771 2.689 2.844
-0.168 -0.241 -0.208 -0.155 -0.210 -0.191 0.321 -0.108 -0.264
-0.310 -0.404 -0.389 -0.326 -0.369 -0.361 0.132 -0.287 -0.423
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–184 and Table 1–185 show the periphery clock timing parameters for EP3SE50
devices.
Table 1–184. EP3SE50 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.472
1.472
-0.047
-0.047
1.481
1.481
-0.044
-0.044
2.155 2.417 2.825 2.681 3.247 2.417 2.819 2.681 3.247
2.155 2.417 2.825 2.681 3.247 2.417 2.819 2.681 3.247
-0.288 -0.347 -0.302 -0.266 -0.079 -0.347 0.300 -0.266 -0.079
-0.288 -0.347 -0.302 -0.266 -0.079 -0.347 0.300 -0.266 -0.079
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–185. EP3SE50 Row Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.467
1.385
-0.021
-0.103
1.543
1.452
0.036
-0.055
2.208 2.472 2.843 2.729 3.012 2.521 2.891 2.771 3.028
2.063 2.309 2.662 2.558 2.853 2.351 2.702 2.592 2.869
-0.231 -0.307 -0.282 -0.230 -0.301 -0.262 0.372 -0.184 -0.361
-0.373 -0.470 -0.463 -0.401 -0.460 -0.432 0.183 -0.363 -0.520
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SE80 Clock Timing Parameters
Table 1–186 and Table 1–187 show the global clock timing parameters for EP3SE80
devices.
Table 1–186. EP3SE80 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.037
2.037
-0.024
-0.024
2.059
2.059
-0.007
-0.007
2.879 3.127 3.524 3.430 3.989 3.127 3.524 3.430 3.989
2.879 3.127 3.524 3.430 3.989 3.127 3.524 3.430 3.989
-0.235 -0.315 -0.292 -0.199 -0.042 -0.315 -0.292 -0.199 -0.042
-0.235 -0.315 -0.292 -0.199 -0.042 -0.315 -0.292 -0.199 -0.042
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–322
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–187. EP3SE80 Row Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.994
1.912
0.020
-0.062
2.143
2.052
0.086
-0.005
2.942 3.188 3.552 3.446 3.769 3.258 3.633 3.515 3.813
2.800 3.025 3.371 3.275 3.610 3.089 3.444 3.336 3.654
-0.177 -0.249 -0.221 -0.171 -0.221 -0.199 -0.173 -0.121 -0.266
-0.319 -0.412 -0.402 -0.342 -0.380 -0.369 -0.362 -0.300 -0.425
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–188 and Table 1–189 show the regional clock timing parameters for EP3SE80
devices.
Table 1–188. EP3SE80 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.828
1.828
-0.013
-0.013
1.849
1.849
0.004
0.004
2.578 2.811 3.171 3.087 3.547 2.811 3.171 3.087 3.547
2.578 2.811 3.171 3.087 3.547 2.811 3.171 3.087 3.547
-0.224 -0.303 -0.280 -0.187 -0.030 -0.303 -0.280 -0.187 -0.030
-0.224 -0.303 -0.280 -0.187 -0.030 -0.303 -0.280 -0.187 -0.030
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–189. EP3SE80 Row Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.812
1.730
0.010
-0.072
1.928
1.837
0.087
-0.004
2.638 2.874 3.205 3.107 3.332 2.938 3.277 3.169 3.373
2.496 2.711 3.024 2.936 3.173 2.768 3.088 2.990 3.214
-0.176 -0.259 -0.231 -0.167 -0.229 -0.210 -0.169 -0.118 -0.275
-0.318 -0.422 -0.412 -0.338 -0.388 -0.380 -0.358 -0.297 -0.434
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–190 and Table 1–191 show the periphery clock timing parameters for EP3SE80
devices.
Table 1–190. EP3SE80 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.564
1.564
-0.028
-0.028
1.585
1.584
-0.006
-0.006
2.309 2.566 2.962 2.838 3.377 2.566 2.962 2.838 3.377
2.308 2.566 2.962 2.844 3.377 2.566 2.962 2.844 3.377
-0.234 -0.327 -0.270 -0.193 -0.018 -0.327 -0.270 -0.193 -0.018
-0.234 -0.327 -0.270 -0.193 -0.018 -0.327 -0.270 -0.193 -0.018
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–323
I/O Timing
Table 1–191. EP3SE80 Row Pin Periphery Clock Timing Specifications
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.441
1.359
0.004
-0.078
1.503
1.412
0.077
-0.014
2.156 2.429 2.776 2.665 2.934 2.477 2.828 2.711 2.959
2.011 2.266 2.595 2.494 2.775 2.307 2.639 2.532 2.800
-0.186 -0.268 -0.243 -0.177 -0.238 -0.219 -0.177 -0.128 -0.287
-0.328 -0.431 -0.424 -0.348 -0.397 -0.389 -0.366 -0.307 -0.446
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SE110 Clock Timing Parameters
Table 1–192 and Table 1–193 show the global clock timing parameters for EP3SE110
devices.
Table 1–192. EP3SE110 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.046
2.046
-0.020
-0.020
2.046
2.046
-0.034
-0.034
2.868 3.144 3.524 3.429 3.989 3.144 3.524 3.429 3.989
2.868 3.144 3.524 3.429 3.989 3.144 3.524 3.429 3.989
-0.265 -0.311 -0.267 -0.198 -0.034 -0.311 -0.267 -0.198 -0.034
-0.265 -0.311 -0.267 -0.198 -0.034 -0.311 -0.267 -0.198 -0.034
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–193. EP3SE110 Row Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.985
1.903
0.012
-0.070
2.130
2.039
0.084
-0.007
2.928 3.183 3.546 3.437 3.772 3.250 3.615 3.507 3.815
2.786 3.020 3.365 3.266 3.613 3.082 3.426 3.328 3.656
-0.180 -0.253 -0.223 -0.173 -0.223 -0.207 -0.173 -0.123 -0.267
-0.322 -0.416 -0.404 -0.344 -0.382 -0.377 -0.362 -0.302 -0.426
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–194 and Table 1–195 show the regional clock timing parameters for EP3SE110
devices.
Table 1–194. EP3SE110 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.828
1.828
-0.008
-0.008
1.849
1.849
-0.022
-0.022
2.578 2.811 3.155 3.082 3.560 2.811 3.155 3.082 3.560
2.578 2.811 3.155 3.082 3.560 2.811 3.155 3.082 3.560
-0.254 -0.299 -0.255 -0.186 -0.021 -0.299 -0.255 -0.186 -0.021
-0.254 -0.299 -0.255 -0.186 -0.021 -0.299 -0.255 -0.186 -0.021
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–324
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table 1–195. EP3SE110 Row Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.798
1.716
0.001
-0.081
1.924
1.833
0.076
-0.015
2.631 2.860 3.204 3.101 3.332 2.920 3.268 3.163 3.373
2.489 2.697 3.023 2.930 3.173 2.750 3.079 2.984 3.214
-0.188 -0.262 -0.231 -0.184 -0.229 -0.218 -0.180 -0.134 -0.277
-0.330 -0.425 -0.412 -0.355 -0.388 -0.388 -0.369 -0.313 -0.436
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–196 and Table 1–197 show the periphery clock timing parameters for
EP3SE110 devices.
Table 1–196. EP3SE110 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.564
1.564
-0.019
-0.019
1.585
1.584
-0.019
-0.019
2.309 2.566 2.951 2.843 3.398 2.566 2.951 2.843 3.398
2.308 2.566 2.951 2.843 3.398 2.566 2.951 2.843 3.398
-0.245 -0.310 -0.267 -0.194 -0.018 -0.310 -0.267 -0.194 -0.018
-0.245 -0.310 -0.267 -0.194 -0.018 -0.310 -0.267 -0.194 -0.018
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–197. EP3SE110 Row Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.423
1.341
0.001
-0.081
1.502
1.411
0.069
-0.022
2.156 2.411 2.781 2.659 2.934 2.455 2.826 2.704 2.949
2.011 2.248 2.600 2.488 2.775 2.285 2.637 2.525 2.790
-0.195 -0.271 -0.241 -0.188 -0.238 -0.222 -0.190 -0.139 -0.288
-0.337 -0.434 -0.422 -0.359 -0.397 -0.392 -0.379 -0.318 -0.447
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
EP3SE260 Clock Timing Parameters
Table 1–198 and Table 1–199 show the global clock timing parameters for EP3SE260
devices.
Table 1–198. EP3SE260 Column Pin Global Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.237
2.237
0.040
0.040
2.237
2.237
0.040
0.040
3.302 3.416 3.837 3.683 4.331 3.416 3.837 3.683 4.331
3.302 3.416 3.837 3.683 4.331 3.416 3.837 3.683 4.331
-0.199 -0.211 -0.135 -0.127 0.074 -0.211 0.296 -0.127 0.074
-0.199 -0.211 -0.135 -0.127 0.074 -0.211 0.296 -0.127 0.074
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–325
I/O Timing
Table 1–199. EP3SE260 Row Pin Global Clock Timing Specifications
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
2.171
2.089
0.091
0.009
2.374
2.283
0.172
0.081
3.458 3.526 3.868 3.768 4.184 3.564 3.943 3.768 4.184
3.306 3.366 3.687 3.597 4.025 3.396 3.754 3.597 4.025
-0.087 -0.116 -0.085 -0.031 -0.071 -0.077 0.399 -0.031 -0.071
-0.239 -0.279 -0.266 -0.202 -0.230 -0.247 0.210 -0.202 -0.230
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–200 and Table 1–201 show the regional clock timing parameters for EP3SE260
devices.
Table 1–200. EP3SE260 Column Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.930
1.930
0.061
0.061
2.003
2.003
0.066
0.066
2.983 2.955 3.531 3.209 3.736 2.955 3.531 3.209 3.736
2.983 2.955 3.531 3.209 3.736 2.955 3.531 3.209 3.736
-0.172 -0.191 -0.109 -0.091 0.102 -0.191 0.302 -0.091 0.102
-0.172 -0.191 -0.109 -0.091 0.102 -0.191 0.302 -0.091 0.102
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–201. EP3SE260 Row Pin Regional Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.903
1.821
0.088
0.006
2.065
1.974
0.199
0.108
3.000 3.070 3.388 3.294 3.593 3.103 3.457 3.294 3.593
2.848 2.910 3.207 3.123 3.434 2.935 3.268 3.123 3.434
-0.056 -0.091 -0.081 -0.009 -0.049 -0.078 0.379 -0.009 -0.049
-0.208 -0.254 -0.262 -0.180 -0.208 -0.248 0.190 -0.180 -0.208
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Table 1–202 and Table 1–203 show the periphery clock timing parameters for
EP3SE260 devices
Table 1–202. EP3SE260 Column Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.709
1.709
0.037
0.037
1.716
1.716
0.037
0.037
2.620 2.765 3.177 3.039 3.668 2.765 3.177 3.039 3.668
2.620 2.765 3.177 3.039 3.668 2.765 3.177 3.039 3.668
-0.202 -0.213 -0.140 -0.119 0.075 -0.213 0.293 -0.119 0.075
-0.202 -0.213 -0.140 -0.119 0.075 -0.213 0.293 -0.119 0.075
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–326
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Glossary
Table 1–203. EP3SE260 Row Pin Periphery Clock Timing Specifications
Fast Model C2 C3 C4
C4L
I3
I4
I4L
Parameter
Units
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
VCCL
=
Industrial
Commercial
1.1V
1.1V
1.1V
1.1V
0.9V
1.1V
1.1V
1.1V
0.9V
tCIN
1.495
1.413
0.065
-0.017
1.574
1.483
0.172
0.081
2.378 2.518 2.878 2.776 3.072 2.555 2.926 2.776 3.072
2.223 2.355 2.697 2.605 2.913 2.385 2.737 2.605 2.913
-0.084 -0.118 -0.103 -0.033 -0.071 -0.103 0.384 -0.033 -0.071
-0.236 -0.281 -0.284 -0.204 -0.230 -0.273 0.195 -0.204 -0.230
ns
ns
ns
ns
tCOUT
tPLLCIN
tPLLCOUT
Glossary
The following table shows the glossary for this chapter.
Table 1.
Glossary Table (Part 1 of 4)
Letter
Subject
—
Definitions
A
B
C
D
—
—
—
—
—
Receiver Input Waveforms
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
Ground
IL
V
CM
Differential Waveform
V
ID
p − n = 0 V
V
ID
Differential I/O
Standards
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
Ground
OL
V
CM
Differential Waveform
V
OD
p − n = 0 V
V
OD
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–327
Glossary
Table 1.
Glossary Table (Part 2 of 4)
Letter
Subject
—
Definitions
E
F
—
fHS CLK
HIGH-SPEED I/O Block: High-speed receiver/transmitter input and output clock frequency.
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate
(fHS DR = 1/TUI), non-DPA.
fH SD R
HIGH-SPEED I/O Block: Maximum/minimum LVDS data transfer rate
(fHS DR DPA = 1/TUI), DPA.
fH SD RD PA
G
H
I
—
—
—
J
—
—
—
J
HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications are in the following figure:
TMS
TDI
JTAG Timing
Specifications
tJCP
tJCH
tJCL
tJPH
tJPSU
TCK
TDO
tJPZX
tJPXZ
tJPCO
K
L
—
—
—
—
—
—
—
—
—
—
M
N
O
P
The block diagram shown in the following figure highlights the PLL Specification parameters:
Diagram of PLL Specifications (1)
CLKOUT Pins
Switchover
fOUT_EXT
CLK
fIN
fINPFD
N
GCLK
RCLK
fVCO
fOUT
Counters
C0..C9
VCO
PFD
CP
LF
Core Clock
PLL
Specifications
M
Key
External Feedback
Reconfigurable in User Mode
Note:
(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.
—
Q
—
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–328
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Glossary
Table 1.
Glossary Table (Part 3 of 4)
Letter
Subject
Definitions
R
S
RL
Receiver differential input discrete resistor (external to Stratix III device).
The period of time during which the data must be valid in order to capture it correctly. The
setup and hold times determine the ideal strobe position within the sampling window (the
following figure):
Timing Diagram
SW (sampling
window)
Bit Time
Sampling Window
(SW)
RSKM
RSKM
0.5 x TCCS
0.5 x TCCS
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input
signal values. The AC values indicate the voltage levels at which the receiver must meet its
timing specifications. The DC values indicate the voltage levels at which the final logic state of
the receiver is unambiguously defined. Once the receiver input has crossed the AC value, the
receiver will change to the new logic state.
The new logic state will be maintained as long as the input stays beyond the DC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing (The following figure):
Single-Ended Voltage Referenced I/O Standard
Single-ended
Voltage
VCCIO
Referenced I/O
Standard
VOH
VIH AC
(
)
VIH(DC)
VREF
VIL(DC)
VIL(AC
)
VOL
VSS
T
tC
High-speed receiver/transmitter input and output clock period.
The timing difference between the fastest and the slowest output edges, including tco
variation and clock skew, across channels driven by the same PLL. The clock is included in
the TCCS measurement (refer to the Timing Diagram figure under S in this table)
TCCS (channel-
to-channel-skew)
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUT Y
The timing budget allowed for skew, propagation delays, and data sampling window. (TUI =
1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w)
tFALL
tIN CCJ
Signal High-to-low transition time (80-20%)
Cycle-to-cycle jitter tolerance on PLL clock input
Period jitter on general purpose I/O driven by a PLL
Period jitter on dedicated clock output driven by a PLL
Signal Low-to-high transition time (20-80%)
—
tO UT PJ_I O
tO UTP J_ DC
tRISE
U
—
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–329
Glossary
Table 1.
Glossary Table (Part 4 of 4)
Letter
Subject
VCM(DC)
VICM
Definitions
V
DC Common Mode Input Voltage.
Input Common Mode Voltage: The common mode of the differential signal at the receiver.
Input differential Voltage Swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VID
VDIF(A C)
VDIF(D C)
AC differential Input Voltage: Minimum AC input differential voltage required for switching.
DC differential Input Voltage: Minimum DC input differential voltage required for switching.
Voltage Input High: The minimum positive voltage applied to the input that will be accepted
by the device as a logic high.
VIH
VI H( AC )
VI H( DC )
High-level AC input voltage
High-level DC input voltage
Voltage Input Low: The maximum positive voltage applied to the input that will be accepted
by the device as a logic low.
VIL
VIL(AC)
VIL(DC)
Low-level AC input voltage
Low-level DC input voltage
Output Common Mode Voltage: The common mode of the differential signal at the
transmitter.
VOC M
VOD
Output differential Voltage Swing: The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
Voltage Output High: The maximum positive voltage from an output which the device
considers will be accepted as the minimum positive high level.
VOH
Voltage Output Low: The maximum positive voltage from an output which the device
considers will be accepted as the maximum positive low level.
VOL
AC differential Input cross point Voltage: The voltage at which the differential input signals
must cross.
VX (A C)
VSWING (AC )
VSWING (DC )
VIN
AC differential Input Voltage: AC Input differential voltage required for switching.
DC differential Input Voltage: DC Input differential voltage required for switching.
DC input voltage.
AC differential Output cross point Voltage: The voltage at which the differential output signals
must cross.
VO X ( AC )
VR EF
VTT
W
Reference voltage for SSTL and HSTL I/O Standards.
Termination voltage for SSTL and HSTL I/O Standards.
W
X
Y
Z
HIGH-SPEED I/O BLOCK: Clock Boost Factor
—
—
—
—
—
—
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
1–330
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
Chapter Revision History
Chapter Revision History
Table 1–204 shows the revision history for this document.
Table 1–204. Chapter Revision History (Part 1 of 2)
Date and Revision
Changes Made
■ Updated Table 1–43, Table 1–44, Table 1–45, Table 1–49,
Summary of Changes
Table 1–50, Table 1–53, Table 1–54, Table 1–55, Table 1–59,
Table 1–60, Table 1–63, Table 1–65, Table 1–73, Table 1–75,
Table 1–83, Table 1–84, Table 1–85, Table 1–89, Table 1–90,
Table 1–93, Table 1–95, Table 1–103, Table 1–104, Table 1–105,
Table 1–109, Table 1–110, Table 1–113, Table 1–115, Table 1–123,
Table 1–125, Table 1–133, Table 1–134, Table 1–135, Table 1–139,
and Table 1–140.
July 2009,
version 2.1
—
■ Updated “Glossary” section.
■ Updated Table 1–1, Table 1–7, Table 1–9, Table 1–18, Table 1–21,
Table 1–22, Table 1–23, Table 1–25, Table 1–26, Table 1–30,
Table 1–31, Table 1–32, Table 1–35, Table 1–37, Table 1–43,
Table 1–45, Table 1–53, Table 1–55, Table 1–63, Table 1–65,
Table 1–73, Table 1–75, Table 1–83, Table 1–85, Table 1–93,
Table 1–95, Table 1–103, Table 1–105, Table 1–113, Table 1–115,
Table 1–123, Table 1–125, Table 1–133, and Table 1–135.
May 2009,
version 2.0
—
—
■ Updated Equation 1–1.
■ Updated “Programmable IOE Delay”, “PLL Specifications”, “DSP
Block Specifications”, “TriMatrix Memory Block Specifications”,
“External Memory Interface Specifications”, and “High-Speed I/O
Specifications” sections.
February 2009,
version 1.9
■ Updated all Timing Information Tables in “User I/O Pin Timing” and
“Dedicated Clock Pin Timing” sections.
■ Removed “Referenced Documents” and “Maximum Input and
Output Toggle Rate” sections.
■ Updated “Operating Conditions”.
■ Added “Bus Hold Specifications”.
■ Updated Table 1–3, Table 1–6, Table 1–7, Table 1–11, and
Table 1–14.
■ Updated Table 1–17 to Table 1–25.
■ Updated Table 1–39 to Table 1–47.
■ Updated Table 1–50 to Table 1–210.
■ Added (Note 3) to Table 1–11.
■ Added (Note 1) to Table 1–14.
■ Added (Note 6) to Table 1–17.
■ Added (Note 1) to Table 1–47.
■ Added Table 1–26.
October 2008,
version 1.8
—
■ Added Figure 1–2.
Stratix III Device Handbook, Volume 2
© July 2009 Altera Corporation
Chapter 1: Stratix III Device Data Sheet: DC and Switching Characteristics
1–331
Chapter Revision History
Table 1–204. Chapter Revision History (Part 2 of 2)
Date and Revision
Changes Made
Summary of Changes
■ Updated “Operating Conditions” introduction section.
■ Updated Table 1–3, Table 1–7, Table 1–8, Table 1–19, Table 1–21,
Table 1–22, Table 1–25, Table 1–26,Table 1–28, Table 1–29,
Table 1–30, Table 1–31, Table 1–32, Table 1–33, Table 1–35, and
Table 1–48.
July 2008,
version 1.7
—
■ Updated “PLL Specifications” introduction section.
■ Updated “I/O Timing Measurement Methodology” section.
■ Updated Figure 1–5, Figure 1–6, and Figure 1–7.
■ Updated all tables for timing section.
■ Added “Internal Weak Pull-Up Resistor” section.
May 2008,
version 1.6
■ Removed “Stratix III Temperature Sensing Diode Specifications”
Text, Table, and Figure
updates.
section.
■ Added Figure 1–6 and Figure 1–7.
■ Added derating factors Table 1–45 and Table 1–46.
■ Updated Table 1–90 to Table 1–109.
■ Updated Table 1–140 to Table 1–149.
■ Updated Table 1–175 to Table 1–180.
■ Updated Table 1–181 to Table 1–186.
■ Updated Table 1–205 to Table 1–210.
■ Updated I/O Timing
November 2007,
version1.5
—
—
October 2007,
version 1.4
■ Added new device packages for EP3SL50, EP3SL110, EP3SE80.
May 2007,
version 1.3
Added new contact information table to the About this Handbook
section.
—
—
May 2007,
version 1.2
Updated Table 1–44 through Table 1–205.
March 2007,
version 1.1
Added I/O Timing section
Initial Release
—
—
November 2006,
version 1.0
© July 2009 Altera Corporation
Stratix III Device Handbook, Volume 2
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