EPM7128BFC100_技术文档

MAX 7000B

Programmable Logic

Device Family

®

February 2000, ver. 2.0

Data Sheet

■

High-performance 2.5-V CMOS EEPROM-based programmable

logic devices (PLDs) built on second-generation Multiple Array

MatriX (MAX^®) architecture (see Table 1)

Features...

–

Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V

MAX 7000A device families

–

High-density PLDs ranging from 600 to 10,000 usable gates

3.5-ns pin-to-pin logic delays with counter frequencies in excess

of 285.7 MHz

Preliminary

Information

■

Advanced 2.5-V in-system programmability (ISP)

–

Programs through the built-in IEEE Std. 1149.1 Joint Test Action

Group (JTAG) interface with advanced pin-locking capability

Enhanced ISP algorithm for faster programming

ISP_Done bit to ensure complete programming

Pull-up resistor on I/O pins during in-system programming

–

For information on in-system programmable 5.0-V MAX 7000S or 3.3-V

MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family

Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet.

f

Table 1. MAX 7000B Device Features

Note (1)

Feature

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

Usable gates

Macrocells

600

32

2

1,250

64

2,500

128

8

5,000

256

16

10,000

512

Logic array blocks

4

32

Maximum user I/O

pins

36

68

100

164

212

t

f

(ns)

3.5

2.8

3.5

2.7

4.5

3.5

5.0

3.8

6.0

4.3

PD

SU

(ns)

1.0

2.0

FSU

CO1

CNT

(ns)

1.9

2.0

2.5

2.9

3.9

(MHz)

285.7

277.8

212.8

188.7

147.1

Note:

(1) Contact Altera for up-to-date information on timing information.

Altera Corporation

1

A-DS-MAX7000B-01.1

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

■

System-level features

–

...and More

Features

MultiVolt^TMI/ O interface enabling device core to run at 2.5 V,

while I/ O pins are compatible with 3.3-V, 2.5-V, and 1.8-V logic

levels

–

Programmable power-saving mode for 50% or greater power

reduction in each macrocell

Fast input setup times provided by a dedicated path from I/ O

pin to macrocell registers

Support for advanced I/ O standards, including stub-series

terminated logic (SSTL-2 and SSTL-3) and Gunning transceiver

logic (GTL+)

–

Bus-hold option on I/ O pins

Peripheral component interconnect (PCI) compatible

Bus friendly architecture including programmable slew-rate

control

–

Open-drain output option

Programmable security bit for protection of proprietary designs

Built-in boundary-scan test circuitry compliant with

IEEE Std. 1149.1

–

Supports hot-socketing operation

Programmable ground pins

■

Advanced architecture features

–

Programmable interconnect array (PIA) continuous routing

structure for fast, predictable performance

Configurable expander product-term distribution, allowing up

to 32 product terms per macrocell

Programmable macrocell registers with individual clear, preset,

clock, and clock enable controls

–

Two global clock signals with optional inversion

Programmable power-up states for macrocell registers

6 to 10 pin- or logic-driven output enable signals

■

Advanced package options

–

Pin counts ranging from 44 to 256 in a variety of thin quad flat

pack (TQFP), plastic quad flat pack (PQFP), ball-grid array

(BGA), space-saving FineLine BGA^TM, 0.8-mm Ultra

FineLine BGA, and plastic J-lead chip carrier (PLCC) packages

Pin-compatibility with other MAX 7000B devices in the same

package

–

Advanced software support

–

Software design support and automatic place-and-route

provided by Altera’s Quartus^TMdevelopment system for

Windows-based PCs and Sun SPARCstation and HP 9000 Series

700/ 800 workstations, and the MAX+PLUS^®II development

system for Windows-based PCs and Sun SPARCstation, HP 9000

Series 700/ 800, and IBM RISC System/ 6000 workstations

2

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

–

Additional design entry and simulation support provided by

EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized

modules (LPMs), Verilog HDL, VHDL, and other interfaces to

popular EDA tools from manufacturers such as Cadence,

Exemplar Logic, Mentor Graphics, OrCAD, Synopsys,

Synplicity, and VeriBest

Programming support with Altera’s Master Programming Unit

(MPU), MasterBlaster^TMserial/ universal serial bus (USB)

communications cable, and ByteBlasterMV^TMparallel port

download cable, as well as programming hardware from third-

party manufacturers and any Jam^TMSTAPL File (.jam), Jam Byte-

Code File (.jbc), or Serial Vector Format File (.svf)-capable in-

circuit tester

MAX 7000B devices are high-density, high-performance devices based on

Altera’s second-generation MAX architecture. Fabricated with advanced

CMOS technology, the EEPROM-based MAX 7000B devices operate with

a 2.5-V supply voltage and provide 600 to 10,000 usable gates, ISP,

pin-to-pin delays as fast as 3.5 ns, and counter speeds up to 285.7 MHz.

All MAX 7000B device speed grades are compatible with the timing

requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus

Specification, Revision 2.2. See Table 2.

General

Description

Table 2. MAX 7000B Speed Grades

Device

Notes (1), (2)

Speed Grade

-3

-4

-5

-6

-7

-10

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

v

Notes:

(1) Contact Altera Marketing for up-to-date information on available device speed

grades.

(2) Timing parameters are preliminary.

Altera Corporation

3

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

The MAX 7000B architecture supports 100% TTL emulation and high-

density integration of SSI, MSI, and LSI logic functions. It easily integrates

multiple devices ranging from PALs, GALs, and 22V10s to MACH and

pLSI devices. MAX 7000B devices are available in a wide range of

packages, including PLCC, BGA, FineLine BGA, 0.8-mm Ultra FineLine

BGA, PQFP, TQFP, and VTQFP packages. See Table 3.

Table 3. MAX 7000B Maximum User I/O Pins

Notes (1), (2)

Device

44-Pin 44-Pin 48-Pin 49-Pin

PLCC TQFP VTQFP 0.8-mm

100-

TQFP

100-Pin

FineLine

BGA (4)

144- 169-Pin 208-

256- 256-Pin

Pin FineLine

BGA BGA (4)

0.8-mm

Ultra

TQFP

PQFP

FineLine

BGA (3)

FineLine

BGA (3)

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

36

40

68

84

68

84

68

V(1)

100

120

100

164

176

212

Notes:

(1) Contact Altera for up-to-date information on available device package options.

(2) When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or boundary-scan testing, four I/ O

pins become JTAG pins.

(3) All 0.8-mm BGA packages are footprint-compatible via the SameFrame^TMpin-out feature. Therefore, designers can

design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.

Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 14 for more

details.

(4) All FineLine BGA packages are footprint-compatible via the SameFrame pin-out feature. Therefore, designers can

design a board to support a variety of devices, providing a flexible migration path across densities and pin counts.

Device migration is fully supported by Altera development tools. See “SameFrame Pin-Outs” on page 14 for more

details.

MAX 7000B devices use CMOS EEPROM cells to implement logic

functions. The user-configurable MAX 7000B architecture accommodates

a variety of independent combinatorial and sequential logic functions.

The devices can be reprogrammed for quick and efficient iterations

during design development and debug cycles, and can be programmed

and erased up to 100 times.

MAX 7000B devices contain 32 to 512 macrocells that are combined into

groups of 16 macrocells, called logic array blocks (LABs). Each macrocell

has a programmable-AND/ fixed-ORarray and a configurable register with

independently programmable clock, clock enable, clear, and preset

functions. To build complex logic functions, each macrocell can be

supplemented with both shareable expander product terms and high-

speed parallel expander product terms to provide up to 32 product terms

per macrocell.

4

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

MAX 7000B devices provide programmable speed/ power optimization.

Speed-critical portions of a design can run at high speed/ full power,

while the remaining portions run at reduced speed/ low power. This

speed/ power optimization feature enables the designer to configure one

or more macrocells to operate at 50% or lower power while adding only a

nominal timing delay. MAX 7000B devices also provide an option that

reduces the slew rate of the output buffers, minimizing noise transients

when non-speed-critical signals are switching. The output drivers of all

MAX 7000B devices can be set for 3.3 V, 2.5 V, or 1.8 V and all input pins

are 3.3-V, 2.5-V, and 1.8-V tolerant, allowing MAX 7000B devices to be

used in mixed-voltage systems.

MAX 7000B devices are supported by the Quartus and MAX+PLUS II

development systems, which are integrated packages that offer

schematic, text—including VHDL, Verilog HDL, and the Altera

Hardware Description Language (AHDL)—and waveform design entry,

compilation and logic synthesis, simulation and timing analysis, and

device programming. The Quartus and MAX+PLUS II software provides

EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for

additional design entry and simulation support from other industry-

standard PC- and UNIX-workstation-based EDA tools. The Quartus

software runs on Windows-based PCs, as well as Sun SPARCstation and

HP 9000 Series 700/ 800 workstations. The MAX+PLUS II software runs

on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series

700/ 800, and IBM RISC System/ 6000 workstations.

For more information on development tools, see the Quartus Programmable

Logic Development System & Software Data Sheet and the MAX+PLUS II

Programmable Logic Development System & Software Data Sheet.

f

The MAX 7000B architecture includes the following elements:

Functional

Description

■

LABs

Macrocells

Expander product terms (shareable and parallel)

PIA

I/ O control blocks

The MAX 7000B architecture includes four dedicated inputs that can be

used as general-purpose inputs or as high-speed, global control signals

(clock, clear, and two output enable signals) for each macrocell and I/ O

pin. Figure 1 shows the architecture of MAX 7000B devices.

Altera Corporation

5

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 1. MAX 7000B Device Block Diagram

INPUT/GCLK1

INPUT/OE2/GCLK2

INPUT/OE1

INPUT/GCLRn

6 or 10 Output Enables (1)

LAB A

LAB B

3 to 16

36

Macrocells

1 to 16

Macrocells

17 to 32

I/O

3 to 16 I/O

Control

Block

Control

Block

3 to 16 I/O

16

6 or 10

3 to 16

6 or 10

LAB C

LAB D

3 to 16

PIA

3 to 16

36

Macrocells

33 to 48

Macrocells

49 to 64

I/O

Control

Block

I/O

Control

Block

3 to 16 I/O

16

6 or 10

3 to 16

Note:

(1) EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enables. EPM7512B devices have ten

output enables.

Logic Array Blocks

The MAX 7000B device architecture is based on the linking of

high-performance LABs. LABs consist of 16 macrocell arrays, as shown in

Figure 1. Multiple LABs are linked together via the PIA, a global bus that

is fed by all dedicated input pins, I/ O pins, and macrocells.

Each LAB is fed by the following signals:

■

36 signals from the PIA that are used for general logic inputs

Global controls that are used for secondary register functions

Direct input paths from I/ O pins to the registers that are used for fast

setup times

6

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Macrocells

The MAX 7000B macrocell can be individually configured for either

sequential or combinatorial logic operation. The macrocell consists of

three functional blocks: the logic array, the product-term select matrix,

and the programmable register. Figure 2 shows the MAX 7000B

macrocell.

Figure 2. MAX 7000B Macrocell

Global Global

LAB Local Array

Clear

Clocks

From

2

I/O pin

Parallel Logic

Expanders

(from other

macrocells)

Fast Input

Select

Programmable

Register

Bypass

To I/O

Control

Block

PRN

D/T

Q

Clock/

Enable

Select

Product-

Term

Select

Matrix

ENA

CLRN

VCC

Clear

Select

To PIA

Shared Logic

Expanders

36 Signals

from PIA

16 Expander

Product Terms

Combinatorial logic is implemented in the logic array, which provides

five product terms per macrocell. The product-term select matrix allocates

these product terms for use as either primary logic inputs (to the ORand

XORgates) to implement combinatorial functions, or as secondary inputs

to the macrocell’s register preset, clock, and clock enable control

functions.

Two kinds of expander product terms (“expanders”) are available to

supplement macrocell logic resources:

■

Shareable expanders, which are inverted product terms that are fed

back into the logic array

Parallel expanders, which are product terms borrowed from adjacent

macrocells

Altera Corporation

7

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

The MAX+PLUS II development system automatically optimizes

product-term allocation according to the logic requirements of the design.

For registered functions, each macrocell flipflop can be individually

programmed to implement D, T, JK, or SR operation with programmable

clock control. The flipflop can be bypassed for combinatorial operation.

During design entry, the designer specifies the desired flipflop type; the

MAX+PLUS II software then selects the most efficient flipflop operation

for each registered function to optimize resource utilization.

Each programmable register can be clocked in three different modes:

■

Global clock signal. This mode achieves the fastest clock-to-output

performance.

Global clock signal enabled by an active-high clock enable. A clock

enable is generated by a product term. This mode provides an enable

on each flipflop while still achieving the fast clock-to-output

performance of the global clock.

■

Array clock implemented with a product term. In this mode, the

flipflop can be clocked by signals from buried macrocells or I/ O pins.

Two global clock signals are available in MAX 7000B devices. As shown

in Figure 1, these global clock signals can be the true or the complement

of either of the global clock pins, GCLK1or GCLK2.

Each register also supports asynchronous preset and clear functions. As

shown in Figure 2, the product-term select matrix allocates product terms

to control these operations. Although the product-term-driven preset and

clear from the register are active high, active-low control can be obtained

by inverting the signal within the logic array. In addition, each register

clear function can be individually driven by the active-low dedicated

global clear pin (GCLRn). Upon power-up, each register in a MAX 7000B

device may be set to either a high or low state. This power-up state is

specified at design entry.

All MAX 7000B I/ O pins have a fast input path to a macrocell register.

This dedicated path allows a signal to bypass the PIA and combinatorial

logic and be clocked to an input D flipflop with an extremely fast input

setup time. The input path from the I/ O pin to the register has a

programmable delay element that can be selected to either guarantee zero

hold time or to get the fastest possible set-up time (as fast as 1.0 ns).

8

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Expander Product Terms

Although most logic functions can be implemented with the five product

terms available in each macrocell, more complex logic functions require

additional product terms. Another macrocell can be used to supply the

required logic resources. However, the MAX 7000B architecture also

offers both shareable and parallel expander product terms (“expanders”)

that provide additional product terms directly to any macrocell in the

same LAB. These expanders help ensure that logic is synthesized with the

fewest possible logic resources to obtain the fastest possible speed.

Shareable Expanders

Each LAB has 16 shareable expanders that can be viewed as a pool of

uncommitted single product terms (one from each macrocell) with

inverted outputs that feed back into the logic array. Each shareable

expander can be used and shared by any or all macrocells in the LAB to

build complex logic functions. A small delay (t

) is incurred when

SEXP

shareable expanders are used. Figure 3 shows how shareable expanders

can feed multiple macrocells.

Figure 3. MAX 7000B Shareable Expanders

Shareable expanders can be shared by any or all macrocells in an LAB.

Macrocell

Product-Term

Logic

Product-Term Select Matrix

Macrocell

Product-Term

Logic

36 Signals

from PIA

16 Shared

Expanders

Altera Corporation

9

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Parallel Expanders

Parallel expanders are unused product terms that can be allocated to a

neighboring macrocell to implement fast, complex logic functions.

Parallel expanders allow up to 20 product terms to directly feed the

macrocell ORlogic, with five product terms provided by the macrocell and

15 parallel expanders provided by neighboring macrocells in the LAB.

The MAX+PLUS II Compiler can automatically allocate up to three sets of

up to five parallel expanders to the macrocells that require additional

product terms. Each set of five parallel expanders incurs a small,

incremental timing delay (t

). For example, if a macrocell requires 14

PEXP

product terms, the Compiler uses the five dedicated product terms within

the macrocell and allocates two sets of parallel expanders; the first set

includes five product terms and the second set includes four product

terms, increasing the total delay by 2 × t

.

PEXP

Two groups of eight macrocells within each LAB (e.g., macrocells 1

through 8, and 9 through 16) form two chains to lend or borrow parallel

expanders. A macrocell borrows parallel expanders from lower-

numbered macrocells. For example, macrocell 8 can borrow parallel

expanders from macrocell 7, from macrocells 7 and 6, or from macrocells

7, 6, and 5. Within each group of eight, the lowest-numbered macrocell

can only lend parallel expanders and the highest-numbered macrocell can

only borrow them. Figure 4 shows how parallel expanders can be

borrowed from a neighboring macrocell.

10

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Figure 4. MAX 7000B Parallel Expanders

Unused product terms in a macrocell can be allocated to a neighboring macrocell.

From

Preset

Product-

Term

Select

Matrix

Macrocell

Product-

Term Logic

Clock

Clear

Preset

Product-

Term

Select

Matrix

Macrocell

Product-

Term Logic

Clock

Clear

To Next

Macrocell

36 Signals 16 Shared

from PIA

Expanders

Programmable Interconnect Array

Logic is routed between LABs on the PIA. This global bus is a

programmable path that connects any signal source to any destination on

the device. All MAX 7000B dedicated inputs, I/ O pins, and macrocell

outputs feed the PIA, which makes the signals available throughout the

entire device. Only the signals required by each LAB are actually routed

from the PIA into the LAB. Figure 5 shows how the PIA signals are routed

into the LAB. An EEPROM cell controls one input to a two-input ANDgate,

which selects a PIA signal to drive into the LAB.

Altera Corporation

11

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 5. MAX 7000B PIA Routing

To LAB

PIA Signals

While the routing delays of channel-based routing schemes in masked or

field-programmable gate arrays (FPGAs) are cumulative, variable, and

path-dependent, the MAX 7000B PIA has a predictable delay. The PIA

makes a design’s timing performance easy to predict.

I/O Control Blocks

The I/ O control block allows each I/ O pin to be individually configured

for input, output, or bidirectional operation. All I/ O pins have a tri-state

buffer that is individually controlled by one of the global output enable

signals or directly connected to ground or V . Figure 6 shows the I/ O

CC

control block for MAX 7000B devices. The I/ O control block has

six or ten global output enable signals that are driven by the true or

complement of two output enable signals, a subset of the I/ O pins, or a

subset of the I/ O macrocells.

12

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Figure 6. I/O Control Block of MAX 7000B Devices

6 or 10 Global

Output Enable Signals (1)

PIA

OE Select Multiplexer

VCC

Programmable

Pull-up

to Other I/O Pins

GND

from

Macrocell

Open-Drain Output

Slew-Rate Control

I/O Standards

Bus Hold

Programmable

Ground

Fast Input to

Macrocell

Register

Programmable Delay

to PIA

Note:

(1) EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enable signals. EPM7512B devices

have ten output enable signals.

When the tri-state buffer control is connected to ground, the output is

tri-stated (high impedance) and the I/ O pin can be used as a dedicated

input. When the tri-state buffer control is connected to V , the output is

CC

enabled.

The MAX 7000B architecture provides dual I/ O feedback, in which

macrocell and pin feedbacks are independent. When an I/ O pin is

configured as an input, the associated macrocell can be used for buried

logic.

Altera Corporation

13

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

MAX 7000B devices support the SameFrame pin-out feature for

FineLine BGA and 0.8-mm Ultra FineLine BGA packages. The

SameFrame

Pin-Outs

SameFrame pin-out feature is the arrangement of balls on FineLine BGA

and 0.8-mm Ultra FineLine BGA packages such that the lower-ball-count

packages form a subset of the higher-ball-count packages. SameFrame

pin-outs provide the flexibility to migrate not only from device to device

within the same package, but also from one package to another. FineLine

BGA packages are compatible with other FineLine BGA packages, and

0.8-mm Ultra FineLine BGA packages are compatible with other 0.8-mm

Ultra FineLine BGA packages. A given printed circuit board (PCB) layout

can support multiple device density/ package combinations. For example,

a single board layout can support a range of devices from an EPM7064B

device in a 100-pin FineLine BGA package to an EPM7512B device in a

256-pin FineLine BGA package.

The Quartus and MAX+PLUS II software provides support to design

PCBs with SameFrame pin-out devices. Devices can be defined for present

and future use. The Quartus and MAX+PLUS II software generates pin-

outs describing how to layout a board to take advantage of this migration

(see Figure 7).

Figure 7. SameFrame Pin-Out Example

Printed Circuit Board

Designed for 256-Pin FineLine BGA Package

100-Pin

FineLine

BGA

256-Pin

FineLine

BGA

100-Pin FineLine BGA Package

(Reduced I/O Count or

256-Pin FineLine BGA Package

(Increased I/O Count or

Logic Requirements)

14

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

MAX 7000B devices can be programmed in-system via an industry-

standard 4-pin IEEE Std. 1149.1 (JTAG) interface. ISP offers quick, efficient

iterations during design development and debugging cycles. The

MAX 7000B architecture internally generates the high programming

voltages required to program EEPROM cells, allowing in-system

programming with only a single 2.5-V power supply. During in-system

programming, the I/ O pins are tri-stated and weakly pulled-up to

eliminate board conflicts. The pull-up value is nominally 50 kΩ.

In-System

Programma-

bility (ISP)

MAX 7000B devices have an enhanced ISP algorithm for faster

programming. These devices also offer an ISP_Done bit that provides safe

operation when in-system programming is interrupted. This ISP_Done

bit, which is the last bit programmed, prevents all I/ O pins from driving

until the bit is programmed.

ISP simplifies the manufacturing flow by allowing devices to be mounted

on a PCB with standard pick-and-place equipment before they are

programmed. MAX 7000B devices can be programmed by downloading

the information via in-circuit testers, embedded processors, the Altera

MasterBlaster communications cable, and the ByteBlasterMV parallel port

download cable. Programming the devices after they are placed on the

board eliminates lead damage on high-pin-count packages (e.g., QFP

packages) due to device handling. MAX 7000B devices can be

reprogrammed after a system has already shipped to the field. For

example, product upgrades can be performed in the field via software or

modem.

In-system programming can be accomplished with either an adaptive or

constant algorithm. An adaptive algorithm reads information from the

unit and adapts subsequent programming steps to achieve the fastest

possible programming time for that unit. A constant algorithm uses a

pre-defined (non-adaptive) programming sequence that does not take

advantage of adaptive algorithm programming time improvements.

Some in-circuit testers cannot program using an adaptive algorithm.

Therefore, a constant algorithm must be used. MAX 7000B devices can be

programmed with either an adaptive or constant (non-adaptive)

algorithm.

The Jam Standard Test and Programming Language (STAPL), JEDEC

standard JESD-71, can be used to program MAX 7000B devices with

in-circuit testers, PCs, or embedded processors.

For more information on using the Jam language, see Application Note 88

(Using the Jam Language for ISP & ICR via an Embedded Processor) and

Application Note 122 (Using STAPL for ISP & ICR via an Embedded Processor).

f

Altera Corporation

15

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

MAX 7000B devices can be programmed on Windows-based PCs with an

Altera Logic Programmer card, the Master Programming Unit (MPU),

and the appropriate device adapter. The MPU performs continuity

checking to ensure adequate electrical contact between the adapter and

the device.

Programming

with External

Hardware

For more information, see the Altera Programming Hardware Data Sheet.

f

The MAX+PLUS II software can use text- or waveform-format test vectors

created with the MAX+PLUS II Text Editor or Waveform Editor to test the

programmed device. For added design verification, designers can

perform functional testing to compare the functional device behavior with

the results of simulation.

Data I/ O, BP Microsystems, and other programming hardware

manufacturers provide programming support for Altera devices. For

more information, see Programming Hardware Manufacturers.

MAX 7000B devices include the JTAG boundary-scan test circuitry

defined by IEEE Std. 1149.1. Table 4 describes the JTAG instructions

supported by MAX 7000B devices. The pin-out tables starting on page 54

of this data sheet show the location of the JTAG control pins for each

device. If the JTAG interface is not required, the JTAG pins are available

as user I/ O pins.

IEEE Std.

1149.1 (JTAG)

Boundary-Scan

Support

Table 4. MAX 7000B JTAG Instructions

JTAG Instruction

Description

SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during

normal device operation, and permits an initial data pattern output at the device pins.

EXTEST

Allows the external circuitry and board-level interconnections to be tested by forcing a

test pattern at the output pins and capturing test results at the input pins.

BYPASS

Places the 1-bit bypass register between the TDIand TDOpins, which allows the

boundary-scan test data to pass synchronously through a selected device to adjacent

devices during normal operation.

CLAMP

Allows the values in the boundary-scan register to determine pin states while placing the

1-bit bypass register between the TDIand TDOpins.

IDCODE

Selects the IDCODE register and places it between the TDIand TDOpins, allowing the

IDCODE to be serially shifted out of TDO.

USERCODE

ISP Instructions

Selects the 32-bit USERCODE register and places it between the TDIand TDOpins,

allowing the USERCODE value to be shifted out of TDO.

These instructions are used when programming MAX 7000B devices via the JTAG ports

with the MasterBlaster, ByteBlaster, or ByteBlasterMV download cable, or using a Jam

File (.jam), Jam Byte-Code File (.jbc), or Serial Vector Format File (.svf) via an

embedded processor or test equipment.

16

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

The instruction register length of MAX 7000B devices is ten bits. The

MAX 7000B USERCODE register length is 32 bits. Tables 5 and 6 show the

boundary-scan register length and device IDCODE information for

MAX 7000B devices.

Table 5. MAX 7000B Boundary-Scan Register Length

Device

Boundary-Scan Register Length

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

96

192

288

480

624

Table 6. 32-Bit MAX 7000B Device IDCODE Note (1)

Device

IDCODE (32 Bits)

Version

(4 Bits)

Part Number (16 Bits) Manufacturer’s 1 (1 Bit)

Identity (11 Bits)

(2)

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

0010

0111 0000 0011 0010 00001101110

0111 0000 0110 0100 00001101110

0111 0001 0010 1000 00001101110

0111 0010 0101 0110 00001101110

0111 0101 0001 0010 00001101110

1

Notes:

(1) The most significant bit (MSB) is on the left.

(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.

See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera

Devices) for more information on JTAG boundary-scan testing.

f

Altera Corporation

17

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 8 shows the timing information for the JTAG signals.

Figure 8. MAX 7000B JTAG Waveforms

TMS

TDI

t_JCP

t_JCH

t _JCL

t_JPH

t_JPSU

TCK

TDO

t_JPXZ

t_JPZX

t_JPCO

t_JSSU

t_JSH

Signal

to Be

Captured

t_JSCO

t_JSZX

t_JSXZ

Signal

to Be

Driven

Table 7 shows the JTAG timing parameters and values for MAX 7000B

devices.

Table 7. JTAG Timing Parameters & Values for MAX 7000B Devices

Note (1)

Symbol

Parameter

Min Max Unit

t_JCP

TCKclock period

100

50

20

45

ns

t_JCH

TCKclock high time

TCKclock low time

JTAG port setup time

JTAG port hold time

t_JCL

t_JPSU

t_JPH

t_JPCO

t_JPZX

t_JPXZ

t_JSSU

t_JSH

JTAG port clock to output

25

JTAG port high impedance to valid output

JTAG port valid output to high impedance

Capture register setup time

20

45

Capture register hold time

t_JSCO

t_JSZX

t_JSXZ

Update register clock to output

25

Update register high impedance to valid output

Update register valid output to high impedance

18

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Note:

(1) Timing parameters in this table apply to all VCCIO levels.

MAX 7000B devices offer a power-saving mode that supports low-power

operation across user-defined signal paths or the entire device. This

feature allows total power dissipation to be reduced by 50% or more,

because most logic applications require only a small fraction of all gates to

operate at maximum frequency.

Programmable

Speed/Power

Control

The designer can program each individual macrocell in a MAX 7000B

device for either high-speed or low-power operation. As a result, speed-

critical paths in the design can run at high speed, while the remaining

paths can operate at reduced power. Macrocells that run at low power

incur a nominal timing delay adder (t

) for the t

, t

, t , t

,

LPA

LAD LAC IC ACL

t

, t , and t

parameters.

CPPW EN

SEXP

MAX 7000B device outputs can be programmed to meet a variety of

system-level requirements.

Output

Conﬁguration

MultiVolt I/O Interface

The MAX 7000B device architecture supports the MultiVolt I/ O interface

feature, which allows MAX 7000B devices to connect to systems with

differing supply voltages. MAX 7000B devices in all packages can be set

for 3.3-V, 2.5-V, or 1.8-V pin operation. These devices have one set of V

CC

pins for internal operation and input buffers (VCCINT), and another set for

I/ O output drivers (VCCIO).

The VCCIOpins can be connected to either a 3.3-V, 2.5-V, or 1.8-V power

supply, depending on the output requirements. When the VCCIOpins are

connected to a 1.8-V power supply, the output levels are compatible with

1.8-V systems. When the VCCIOpins are connected to a 2.5-V power

supply, the output levels are compatible with 2.5-V systems. When the

VCCIOpins are connected to a 3.3-V power supply, the output high is at

3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices

operating with V

adder.

levels of 2.5 V or 1.8 V incur a nominal timing delay

CCIO

Table 8 describes the MAX 7000B MultiVolt I/ O support.

Altera Corporation

19

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 8. MAX 7000B MultiVolt I/O Support

V

(V)

Input Signal (V)

Output Signal (V)

CCIO

1.8

2.5

3.3

5.0

1.8

2.5

3.3

5.0

1.8

2.5

3.3

v

Open-Drain Output Option

MAX 7000B devices provide an optional open-drain (equivalent to

open-collector) output for each I/ O pin. This open-drain output enables

the device to provide system-level control signals (e.g., interrupt and

write enable signals) that can be asserted by any of several devices. It can

also provide an additional wired-ORplane.

Programmable Ground Pins

Each unused I/ O pin on MAX 7000B devices may be used as an additional

ground pin. This programmable ground feature does not require the use

of the associated macrocell; therefore, the buried macrocell is still

available for user logic.

Slew-Rate Control

The output buffer for each MAX 7000B I/ O pin has an adjustable output

slew rate that can be configured for low-noise or high-speed performance.

A faster slew rate provides high-speed transitions for high-performance

systems. However, these fast transitions may introduce noise transients

into the system. A slow slew rate reduces system noise, but adds a

nominal delay of 4 to 5 ns. When the configuration cell is turned off, the

slew rate is set for low-noise performance. Each I/ O pin has an individual

EEPROM bit that controls the slew rate, allowing designers to specify the

slew rate on a pin-by-pin basis. The slew rate control affects both the

rising and falling edges of the output signal.

Advanced I/O Standard Support

The MAX 7000B I/ O pins support the following I/ O standards: LVTTL,

LVCMOS, 1.8-V I/ O, 2.5-V I/ O, GTL+, SSTL-3 Class I and II, and SSTL-2

Class I and II.

20

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

MAX 7000B devices contain two I/ O banks. Both banks support all

standards. Each I/ O bank has its own VCCIOpins. A single device can

support 1.8-V, 2.5-V, and 3.3-V interfaces; each bank can support a

different standard independently. Within a bank, any one of the

terminated standards can be supported.

Figure 9 shows the arrangement of the MAX 7000B I/ O banks.

Figure 9. MAX 7000B I/O Banks for Various Advanced I/O Standards

Programmable I/O Banks

Individual

Power Bus

Table 9 shows which macrocells have pins in each I/ O bank.

Table 9. Macrocells Contained in Each I/O Bank

Device

Bank 1

Bank 2

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

1-16

1-32

17-32

33-64

1-64

65-128

1-128, 177-181

1-265

129-176, 182-256

266-512

Each MAX 7000B device has two VREFpins. Each can be set to a separate

VREF level. Any I/ O pin that uses one of the voltage-referenced

standards (GTL+, SSTL2, or SSTL3) may use either of the two VREFpins.

If these pins are not required as VREFpins, they may be individually

programmed to function as user I/ O pins.

Altera Corporation

21

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Programmable Pull-Up Resistor

Each MAX 7000B device I/ O pin provides an optional programmable

pull-up resistor during user mode. When this feature is enabled for an I/ O

pin, the pull-up resistor (typically 50 kΩ) weakly holds the output to

V

level.

CCIO

Bus Hold

Each MAX 7000B device I/ O pin provides an optional bus-hold feature.

When this feature is enabled for an I/ O pin, the bus-hold circuitry weakly

holds the signal at its last driven state. By holding the last driven state of

the pin until the next input signals is present, the bus-hold feature can

eliminate the need to add external pull-up or pull-down resistors to hold

a signal level when the bus is tri-stated. The bus-hold circuitry also pulls

undriven pins away from the input threshold voltage where noise can

cause unintended high-frequency switching. This feature can be selected

individually for each I/ O pin. The bus-hold output will drive no higher

than V

to prevent overdriving signals.

CCIO

The bus-hold circuitry weakly pulls the signal level to the last driven state

through a resistor with a nominal resistance (RBH) of approximately

8.5 kΩ. Table 10 gives specific sustaining current that will be driven

through this resistor and overdrive current that will identify the next

driven input level. This information is provided for each VCCIO voltage

level.

Table 10. Bus Hold Parameters

Parameter

Conditions

VCCIO Level

2.5 V

Units

1.8 V

3.3 V

Min Max Min Max Min Max

Low sustaining current

High sustaining current

Low overdrive current

High overdrive current

V

> V (max)

30

50

70

µA

IN

IL

< V (min)

–30

–50

–70

IH

0 V < V < V

200

300

500

IN

CCIO

0 V < V < V

–295

–435

–680

IN

The bus-hold circuitry is active only during user operation. At power-up,

the bus-hold circuit initializes its initial hold value as V approaches the

CC

recommended operation conditions. When transitioning from ISP to User

Mode with bus hold enabled, the bus-hold circuit captures the value

present on the pin at the end of programming.

22

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Two inverters implement the bus-hold circuitry in a loop that weakly

drives back to the I/ O pin at the end of programming.

Figure 10 shows a block diagram of the bus-hold circuit.

Figure 10. Bus-Hold Circuit

Bus Hold Circuit

Drive to

VCCIO level

RBH

I/O

Because MAX 7000B devices can be used in a mixed-voltage environment,

they have been designed specifically to tolerate any possible power-up

Power

Sequencing &

Hot-Socketing

sequence. The V

order.

and V

power planes can be powered in any

CCIO

CCINT

Signals can be driven into MAX 7000B devices before and during power

up without damaging the device. Additionally, MAX 7000B devices do

not drive out during power up. Once operating conditions are reached,

MAX 7000B devices operate as specified by the user.

All MAX 7000B devices contain a programmable security bit that controls

access to the data programmed into the device. When this bit is

programmed, a design implemented in the device cannot be copied or

retrieved. This feature provides a high level of design security, because

programmed data within EEPROM cells is invisible. The security bit that

controls this function, as well as all other programmed data, is reset only

when the device is reprogrammed.

Design Security

Generic Testing

MAX 7000B devices are fully functionally tested. Complete testing of each

programmable EEPROM bit and all internal logic elements ensures 100%

programming yield. AC test measurements are taken under conditions

equivalent to those shown in Figure 11. Test patterns can be used and then

erased during early stages of the production flow.

Altera Corporation

23

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 11. MAX 7000B AC Test Conditions

Power supply transients can affect AC

measurements. Simultaneous transitions

of multiple outputs should be avoided for

accurate measurement. Threshold tests

must not be performed under AC

conditions. Large-amplitude, fast-ground-

current transients normally occur as the

device outputs discharge the load

VCC

703 Ω

[521 Ω]

Device

Output

To Test

System

capacitances. When these transients ﬂow

through the parasitic inductance between

the device ground pin and the test system

ground, signiﬁcant reductions in

observable noise immunity can result.

Numbers in brackets are for 2.5-V

outputs. Numbers without brackets are for

3.3-V outputs.

8,060 Ω

[481 Ω]

C1 (includes JIG

capacitance)

Device input

rise and fall

times < 2 ns

Tables 11 through 14 provide information on absolute maximum ratings,

recommended operating conditions, operating conditions, and

capacitance for MAX 7000B devices.

Operating

Conditions

Table 11. MAX 7000B Device Absolute Maximum Ratings

Note (1)

Symbol

Parameter

Conditions

Min

Max

Unit

V_CCINT

V_CCIO

V_I

Supply voltage

–0.5

–2.0

–25

–65

3.6

4.6

25

V

Supply voltage

DC input voltage

(2)

V

I_OUT

T_STG

T_A

DC output current, per pin

Storage temperature

Ambient temperature

Junction temperature

mA

° C

No bias

150

135

Under bias

T_J

24

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 12. MAX 7000B Device Recommended Operating Conditions

Symbol

Parameter

Conditions

Min

Max

Unit

V_CCINT

Supply voltage for internal logic and

input buffers

2.375

2.625

V

V_CCIO

Supply voltage for output drivers,

3.3-V operation

3.0

3.6

2.625

1.89

2.625

3.9

V

Supply voltage for output drivers,

2.5-V operation

2.375

1.71

Supply voltage for output drivers,

1.8-V operation

V_CCISP

Supply voltage during in-system

programming

2.375

V_I

Input voltage

(3)

–0.5

0

V

V_O

T_J

Output voltage

V

CCIO

Junction temperature

For commercial use

For industrial use

0

90

° C

ns

–40

105

40

t_R

t_F

Input rise time

Input fall time

40

Altera Corporation

25

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 13. MAX 7000B Device DC Operating Conditions

Note (4)

Conditions

Symbol

Parameter

Min

Max

Unit

V_IH

High-level input voltage for 3.3 V

TTL/CMOS and 2.5 V TTL/CMOS

1.7

3.9

V

High-level input voltage for 1.8 V

TTL/CMOS

0.65

VCCIO

2.25

0.8

V

V_IL

Low-level input voltage for 3.3 V

TTL/CMOS, 2.5 V TTL/CMOS, and

PCI compliance

–0.5

Low-level input voltage for 1.8 V

TTL/CMOS

–0.5

2.4

0.35

VCCIO

V_OH

3.3-V high-level TTL output voltage I_OH= –8 mA DC, V_CCIO= 3.00 V (5)

V

3.3-V high-level CMOS output

voltage

I_OH= –0.1 mA DC, V_CCIO= 3.00 V (5)

V

–

CCIO

0.2

2.5-V high-level output voltage

I_OH= –100 µA DC, V_CCIO= 2.30 V (5)

I_OH= –1 mA DC, V_CCIO= 2.30 V (5)

I_OH= –2 mA DC, V_CCIO= 2.30 V (5)

I_OH= –2 mA DC, V_CCIO=1.65 V (5)

2.1

2.0

1.7

1.2

V

1.8-V high-level output voltage

V_OL

3.3-V low-level TTL output voltage I_OL= 8 mA DC, V_CCIO= 3.00 V (6)

0.4

0.2

3.3-V low-level CMOS output

voltage

I_OL= 0.1 mA DC, V_CCIO= 3.00 V (6)

2.5-V low-level output voltage

I_OL= 100 µA DC, V_CCIO= 2.30 V (6)

0.2

V

I_OL= 1 mA DC, V_CCIO= 2.30 V (6)

I_OL= 2 mA DC, V_CCIO= 2.30 V (6)

I_OL= 2 mA DC, V_CCIO= 1.7 V (6)

V_I= V_CCINTor ground

0.4

0.7

0.4

5

V

1.8-V low-level output voltage

Input leakage current

V

I_I

–5

20

µA

kΩ

I_OZ

R_ISP

Tri-state output off-state current

V_O= V_CCINTor ground

5

Value of I/O pin pull-up resistor

during in-system programming or

during power-up

V

= 1.7 to 3.6 V (7)

74

CCIO

Table 14. MAX 7000B Device Capacitance

Note (8)

Symbol

Parameter

Conditions

Min

Max

Unit

C_IN

Input pin capacitance

V_IN= 0 V, f = 1.0 MHz

V_OUT= 0 V, f = 1.0 MHz

8

pF

C_I/O

I/O pin capacitance

26

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See the Operating Requirements for Altera Devices Data Sheet.

(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 4.6 V

for input currents less than 100 mA and periods shorter than 20 ns.

(3) All pins, including dedicated inputs, I/ O pins, and JTAG pins, may be driven before V_CCINTand V_CCIOare

powered.

(4) These values are specified under the Recommended Operating Conditions in Table 12 on page 25.

(5) The parameter is measured with 50% of the outputs each sourcing the specified current. The I_OHparameter refers

to high-level TTL or CMOS output current.

(6) The parameter is measured with 50% of the outputs each sinking the specified current. The I_OLparameter refers to

low-level TTL or CMOS output current.

(7) This pull-up exists while devices are being programmed in-system and in unprogrammed devices during

power-up. The pull-up resistor is from the pins to V_CCIO

.

(8) Capacitance is measured at 25° C and is sample-tested only. Two of the dedicated input pins (OE1and GCLRN) have

a maximum capacitance of 15 pF.

Figure 12 shows the typical output drive characteristics of MAX 7000B

devices.

Altera Corporation

27

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 12. Output Drive Characteristics of MAX 7000B Devices

3.3-V VCCIO

2.5-V VCCIO

150

120

150

I_OL

120

V_CCINT= 2.5 V

_CCIO= 3.0 V

Typical I_O

Output

Current (mA)

Typical I_O

Output

90

60

90

60

V_CCINT= 2.5 V

V

V_CCIO= 2.5 V

Room Temperature Current (mA)

Room Temperature

30

I_OH

1

2

3

4

1

2

3

4

V_OOutput Voltage (V)

1.8-V VCCIO

150

I_OL

120

Typical I_O

Output

Current (mA)

90

60

V_CCINT= 2.5 V

_CCIO= 1.8 V

Room Temperature

V

30

I_OH

1

2

3

4

V_OOutput Voltage (V)

28

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

MAX 7000B device timing can be analyzed with the Quartus and

MAX+PLUS II software, with a variety of popular industry-standard

EDA simulators and timing analyzers, or with the timing model shown in

Figure 13. MAX 7000B devices have predictable internal delays that

enable the designer to determine the worst-case timing of any design. The

MAX+PLUS II software provides timing simulation, point-to-point delay

prediction, and detailed timing analysis for device-wide performance

evaluation.

Timing Model

Figure 13. MAX 7000B Timing Model

Internal Output

Enable Delay

t_IOE

Global Control

Delay

Input

Delay

t _{I N}

Output

Delay

t_GLOB

Register

Delay

t_SU

Parallel

Expander Delay

t_PEXP

Logic Array

Delay

t _LAD

t_OD1

t_OD2

t_OD3

t_XZ

t_ZX1

t_ZX2

t_ZX3

PIA

Delay

t_PIA

t_H

t_PRE

t_CLR

t_RD

t_COMB

t_FSU

t_FH

Register

Control Delay

t_LAC

t_IC

t_EN

I/O

Delay

t_IO

Shared

Expander Delay

t_SEXP

Fast

Input Delay

t_FIN

+

t_FINt_FIND

The timing characteristics of any signal path can be derived from the

timing model and parameters of a particular device. External timing

parameters, which represent pin-to-pin timing delays, can be calculated

as the sum of internal parameters. Figure 14 shows the timing relationship

between internal and external delay parameters.

See Application Note 94 (Understanding MAX 7000 Timing) for more

information.

f

Altera Corporation

29

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 14. MAX 7000B Switching Waveforms

t & t < 2 ns. Inputs are

Combinatorial Mode

R

F

driven at 3.0 V for a logic

high and 0 V for a logic

low. All timing

characteristics are

measured at 1.5 V.

t_IN

Input Pin

I/O Pin

t_IO

t_PIA

PIA Delay

t_SEXP

Shared Expander

Delay

t_LAC, t_LAD

Logic Array

Input

t_PEXP

Parallel Expander

Delay

t_COMB

Logic Array

Output

t_OD

Output Pin

Global Clock Mode

t_R

t_CH

t_CL

t_F

Global

Clock Pin

t_IN

t_GLOB

Global Clock

at Register

t_SU

t_H

Data or Enable

(Logic Array Output)

Array Clock Mode

t_R

t_ACH

t_ACL

t_F

Input or I/O Pin

Clock into PIA

t_IN

t_IO

t_PIA

Clock into

Logic Array

t_IC

t_SU

Clock at

Register

t_H

Data from

Logic Array

t_RD

t_PIA

t_CLR, t_PRE

Register to PIA

to Logic Array

t_OD

Register Output

to Pin

30

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Tables 15 and 16 show EPM7032B AC operating conditions.

Table 15. EPM7032B External Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-5

Unit

-3

-7

Min

Max

Min

Max

Min

Max

t_PD1

t_PD2

Input to non-registered

output

C1 = 35 pF (3)

3.5

5.0

7.5

ns

I/O input to non-registered C1 = 35 pF (3)

output

3.5

5.0

7.5

t_SU

t_H

Global clock setup time

Global clock hold time

(3)

2.8

0.0

1.0

4.0

0.0

1.0

5.7

0.0

1.5

ns

t_FSU

Global clock setup time of

fast input

t_FH

Global clock hold time of

fast input

1.0

2.5

1.0

2.5

1.0

3.0

ns

t_FZHSU

Global clock setup time of

fast input with zero hold

time

t_FZHH

Global clock hold time of

fast input with zero hold

time

0.0

1.0

0.0

1.0

0.0

1.0

ns

t_CO1

Global clock to output

delay

C1 = 35 pF

1.9

3.0

2.7

4.2

4.0

6.2

t_CH

Global clock high time

Global clock low time

Array clock setup time

Array clock hold time

1.5

1.7

0.0

1.0

1.5

2.0

2.5

0.0

1.0

2.0

3.0

3.5

0.0

1.0

3.0

ns

t_CL

t_ASU

t_AH

(3)

t_ACO1

t_ACH

t_ACL

t_CPPW

Array clock to output delay C1 = 35 pF (3)

Array clock high time

Array clock low time

Minimum pulse width for

clear and preset

t_CNT

Minimum global clock

period

(3)

3.5

5.0

7.2

ns

MHz

ns

f_CNT

Maximum internal global

clock frequency

(3), (4)

(3)

285.7

200.0

138.9

t_ACNT

f_ACNT

Minimum array clock

period

Maximum internal array

clock frequency

(3), (4)

MHz

Altera Corporation

31

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 16. EPM7032B Internal Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-5

Min Max Min Max Min Max

Unit

-3

-7

Input pad and buffer delay

I/O input pad and buffer delay

Fast input delay

t

0.6

0.1

1.5

0.8

0.2

1.5

1.2

0.3

1.5

ns

IN

IO

FIN

FIND

Programmable delay adder for

fast input

Shared expander delay

Parallel expander delay

Logic array delay

t

1.5

0.4

1.2

0.5

0.0

0.6

2.1

0.5

1.7

0.7

0.0

0.9

3.1

0.8

2.5

1.0

0.0

1.3

ns

SEXP

PEXP

LAD

Logic control array delay

Internal output enable delay

LAC

IOE

Output buffer and pad delay

slow slew rate = off

V_CCIO= 3.3 V

C1 = 35 pF

C1 = 5 pF

OD1

Output buffer and pad delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

t

5.6

4.0

9.0

4.0

5.9

4.0

9.0

4.0

6.3

4.0

9.0

4.0

ns

OD3

ZX1

ZX3

Output buffer enable delay

slow slew rate = off

V_CCIO= 3.3 V

Output buffer enable delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

Output buffer disable delay

Register setup time

Register hold time

t

ns

XZ

1.0

0.5

1.0

1.5

0.6

1.0

1.5

2.0

1.0

1.5

SU

H

Register setup time of fast input

Register hold time of fast input

Register delay

FSU

FH

0.6

0.4

0.5

0.1

0.8

0.6

0.7

2.5

0.8

0.6

0.7

0.2

1.2

0.9

1.0

4.0

1.2

1.0

0.3

1.7

1.3

1.5

4.0

RD

Combinatorial delay

Array clock delay

COMB

IC

Register enable time

Global control delay

Register preset time

Register clear time

PIA delay

EN

GLOB

PRE

CLR

PIA

LPA

(3)

(7)

Low-power adder

32

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 17. Selectable I/O Standard Input Adder Delays (Excluding Path to Fast Input Register)

I/O Standard

Speed Grade

-5

Unit

-3

-7

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.4

0.0

1.0

0.7

0.0

0.3

0.5

0.0

1.4

1.0

0.0

0.4

0.8

0.0

2.1

1.5

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Table 18. Selectable I/O Standard Input Adder Delays (Path to Fast Input Register)

I/O Standard

Speed Grade

-5

Unit

-3

-7

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.4

0.0

0.6

0.4

0.0

0.3

0.5

0.0

0.9

0.5

0.0

0.4

0.8

0.0

1.3

0.8

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Altera Corporation

33

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 19. Selectable I/O Standard Output Adder Delays

I/O Standard

Speed Grade

Unit

-3

-5

-7

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.0

0.3

0.0

0.4

ns

1.2

1.7

2.5

0.0

GTL+

-0.2

-0.1

-0.3

-0.1

-0.4

-0.2

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Notes to tables:

(1) These values are specified under the Recommended Operating Conditions in Table 12 on page 25.

(2) MAX 7000B timing values are preliminary.

(3) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing value.

(4) Measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.

(5) The f_MAXvalues represent the highest frequency for pipelined data.

(6) Operating conditions: V_CCIO= 2.5 ± 5% for commercial and industrial use.

(7) The t_LPAparameter must be added to the t_LAD, t_LAC, t_IC, t_ACL, t_CPPW, t_EN, and t_SEXPparameters for macrocells

running in low-power mode.

34

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Tables 20 and 21 show EPM7064B AC operating conditions.

Table 20. EPM7064B External Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-5

Unit

-3

-7

Min

Max

Min

Max

Min

Max

t_PD1

t_PD2

Input to non-registered

output

C1 = 35 pF (3)

3.5

5.0

7.5

ns

I/O input to non-registered C1 = 35 pF (3)

output

3.5

5.0

7.5

t_SU

t_H

Global clock setup time

Global clock hold time

(3)

2.7

0.0

1.0

3.8

0.0

1.0

5.6

0.0

1.5

ns

t_FSU

Global clock setup time of

fast input

t_FH

Global clock hold time of

fast input

1.0

2.5

1.0

2.5

1.0

3.0

ns

t_FZHSU

Global clock setup time of

fast input with zero hold

time

t_FZHH

Global clock hold time of

fast input with zero hold

time

0.0

1.0

0.0

1.0

0.0

1.0

ns

t_CO1

Global clock to output

delay

C1 = 35 pF

2.0

3.0

2.9

4.2

6.3

t_CH

Global clock high time

Global clock low time

Array clock setup time

Array clock hold time

1.5

1.7

0.0

1.0

1.5

2.0

2.5

0.0

1.0

2.0

5.1

3.0

3.5

0.0

1.0

3.0

7.4

ns

t_CL

t_ASU

t_AH

(3)

t_ACO1

t_ACH

t_ACL

t_CPPW

Array clock to output delay C1 = 35 pF (3)

Array clock high time

Array clock low time

Minimum pulse width for

clear and preset

t_CNT

Minimum global clock

period

(3)

3.6

5.1

7.4

ns

MHz

ns

f_CNT

Maximum internal global

clock frequency

(3), (4)

(3)

277.8

196.1

5.1

135.1

7.4

t_ACNT

f_ACNT

Minimum array clock

period

Maximum internal array

clock frequency

(3), (4)

196.1

135.1

MHz

Altera Corporation

35

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 21. EPM7064B Internal Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-5

Min Max Min Max Min Max

Unit

-3

-7

Input pad and buffer delay

I/O input pad and buffer delay

Fast input delay

t

0.5

0.3

1.5

0.7

0.5

1.5

1.1

0.6

1.5

ns

IN

IO

FIN

FIND

Programmable delay adder for

fast input

Shared expander delay

Parallel expander delay

Logic array delay

t

1.5

0.3

1.2

0.5

0.0

0.6

2.0

0.4

1.7

0.7

0.0

0.9

3.0

0.7

2.5

1.0

0.0

1.3

ns

SEXP

PEXP

LAD

Logic control array delay

Internal output enable delay

LAC

IOE

Output buffer and pad delay

slow slew rate = off

V_CCIO= 3.3 V

C1 = 35 pF

C1 = 5 pF

OD1

Output buffer and pad delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

t

5.6

4.0

9.0

4.0

5.9

4.0

9.0

4.0

6.3

4.0

9.0

4.0

ns

OD3

ZX1

ZX3

Output buffer enable delay

slow slew rate = off

V_CCIO= 3.3 V

Output buffer enable delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

Output buffer disable delay

Register setup time

Register hold time

t

ns

XZ

1.0

0.5

1.0

1.5

0.6

1.0

1.5

2.0

1.0

1.5

SU

H

Register setup time of fast input

Register hold time of fast input

Register delay

FSU

FH

0.6

0.4

0.5

0.3

1.0

0.6

0.8

3.5

0.8

0.6

0.7

0.5

1.3

0.9

1.1

4.0

1.2

0.9

1.0

0.6

2.0

1.3

1.7

4.0

RD

Combinatorial delay

Array clock delay

COMB

IC

Register enable time

Global control delay

Register preset time

Register clear time

PIA delay

EN

GLOB

PRE

CLR

PIA

LPA

(3)

(7)

Low-power adder

36

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 22. Selectable I/O Standard Input Adder Delays (Excluding Path to Fast Input Register)

I/O Standard

Speed Grade

-5

Unit

-3

-7

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.3

0.0

0.8

0.6

0.0

0.3

0.5

0.0

1.4

1.0

0.0

0.4

0.8

0.0

2.1

1.5

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Table 23. Selectable I/O Standard Input Adder Delays (Path to Fast Input Register)

I/O Standard

Speed Grade

-5

Unit

-3

-7

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.3

0.0

0.5

0.3

0.0

0.3

0.5

0.0

0.9

0.5

0.0

0.4

0.8

0.0

1.3

0.8

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Altera Corporation

37

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 24. Selectable I/O Standard Output Adder Delays

I/O Standard

Speed Grade

Unit

-3

-5

-7

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.0

0.3

0.0

0.4

ns

1.0

1.7

2.5

0.0

GTL+

–0.2

–0.1

–0.3

–0.1

–0.4

–0.2

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Notes to tables:

(1) These values are specified under the Recommended Operating Conditions in Table 12 on page 25.

(2) MAX 7000B timing values are preliminary.

(3) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing value.

(4) Measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.

(5) The f_MAXvalues represent the highest frequency for pipelined data.

(6) Operating conditions: V_CCIO= 2.5 ± 5% for commercial and industrial use.

(7) The t_LPAparameter must be added to the t_LAD, t_LAC, t_IC, t_ACL, t_CPPW, t_EN, and t_SEXPparameters for macrocells

running in low-power mode.

38

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Tables 25 and 26 show EPM7128B AC operating conditions.

Table 25. EPM7128B External Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-7

Unit

-4

-10

Min

Max

Min

Max

Min

Max

t_PD1

t_PD2

Input to non-registered

output

C1 = 35 pF (3)

4.5

7.5

10.0

ns

I/O input to non-registered C1 = 35 pF (3)

output

4.5

7.5

10.0

t_SU

t_H

Global clock setup time

Global clock hold time

(3)

3.5

0.0

1.0

5.6

0.0

1.5

7.5

0.0

1.5

ns

t_FSU

Global clock setup time of

fast input

t_FH

Global clock hold time of

fast input

1.0

2.5

1.0

3.0

1.0

3.0

ns

t_FZHSU

Global clock setup time of

fast input with zero hold

time

t_FZHH

Global clock hold time of

fast input with zero hold

time

0.0

1.0

0.0

1.0

0.0

1.0

ns

t_CO1

Global clock to output

delay

C1 = 35 pF

2.5

3.9

4.3

6.4

5.6

8.5

t_CH

Global clock high time

Global clock low time

Array clock setup time

Array clock hold time

2.0

2.1

0.0

1.0

2.0

3.0

3.5

0.0

1.0

3.0

4.0

4.6

0.0

1.0

4.0

ns

t_CL

t_ASU

t_AH

(3)

t_ACO1

t_ACH

t_ACL

t_CPPW

Array clock to output delay C1 = 35 pF (3)

Array clock high time

Array clock low time

Minimum pulse width for

clear and preset

t_CNT

Minimum global clock

period

(3)

4.7

7.8

10.2

ns

MHz

ns

f_CNT

Maximum internal global

clock frequency

(3), (4)

(3)

212.8

128.2

98.0

t_ACNT

f_ACNT

Minimum array clock

period

Maximum internal array

clock frequency

(3), (4)

MHz

Altera Corporation

39

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 26. EPM7128B Internal Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-7

Min Max Min Max Min Max

Unit

-4

-10

Input pad and buffer delay

I/O input pad and buffer delay

Fast input delay

t

0.6

0.5

1.5

0.9

1.0

1.5

1.3

1.1

1.5

ns

IN

IO

FIN

FIND

Programmable delay adder for

fast input

Shared expander delay

Parallel expander delay

Logic array delay

t

1.8

0.4

1.5

0.7

0.0

0.7

3.0

0.7

2.5

1.1

0.0

1.2

3.8

0.9

3.2

1.4

0.0

1.6

ns

SEXP

PEXP

LAD

Logic control array delay

Internal output enable delay

LAC

IOE

Output buffer and pad delay

slow slew rate = off

V_CCIO= 3.3 V

C1 = 35 pF

C1 = 5 pF

OD1

Output buffer and pad delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

t

5.7

3.0

8.0

3.0

6.2

4.0

9.0

4.0

6.6

5.0

ns

OD3

ZX1

ZX3

Output buffer enable delay

slow slew rate = off

V_CCIO= 3.3 V

Output buffer enable delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

10.0

5.0

Output buffer disable delay

Register setup time

Register hold time

t

ns

XZ

1.3

0.6

1.0

1.5

2.1

1.0

1.5

2.8

1.2

1.5

SU

H

Register setup time of fast input

Register hold time of fast input

Register delay

FSU

FH

0.7

0.5

0.7

0.5

1.5

0.7

1.2

3.5

1.2

0.9

1.1

1.0

2.6

1.2

2.0

4.0

1.6

1.3

1.4

1.1

3.3

1.6

2.6

5.0

RD

Combinatorial delay

Array clock delay

COMB

IC

Register enable time

Global control delay

Register preset time

Register clear time

PIA delay

EN

GLOB

PRE

CLR

PIA

LPA

(3)

(7)

Low-power adder

40

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 27. Selectable I/O Standard Input Adder Delays (Excluding Path to Fast Input Register)

I/O Standard

Speed Grade

-7

Unit

-4

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.4

0.0

1.1

0.8

0.0

0.3

0.7

0.0

1.8

1.3

0.0

0.4

0.9

0.0

2.4

1.8

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Table 28. Selectable I/O Standard Input Adder Delays (Path to Fast Input Register)

I/O Standard

Speed Grade

-7

Unit

-4

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.4

0.0

0.7

0.4

0.0

0.3

0.7

0.0

1.2

0.7

0.0

0.4

0.9

0.0

1.6

0.9

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Altera Corporation

41

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 29. Selectable I/O Standard Output Adder Delays

I/O Standard

Speed Grade

Unit

-4

-7

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.0

0.3

0.0

0.4

ns

1.3

2.2

2.9

0.0

GTL+

-0.2

-0.1

-0.3

-0.2

-0.4

-0.2

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Notes to tables:

(1) These values are specified under the Recommended Operating Conditions in Table 12 on page 25.

(2) MAX 7000B timing values are preliminary.

(3) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing value.

(4) Measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.

(5) The f_MAXvalues represent the highest frequency for pipelined data.

(6) Operating conditions: V_CCIO= 2.5 ± 5% for commercial and industrial use.

(7) The t_LPAparameter must be added to the t_LAD, t_LAC, t_IC, t_ACL, t_CPPW, t_EN, and t_SEXPparameters for macrocells

running in low-power mode.

42

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Tables 30 and 31 show EPM7256B AC operating conditions.

Table 30. EPM7256B External Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-7

Unit

-5

-10

Min

Max

Min

Max

Min

Max

t_PD1

t_PD2

Input to non-registered

output

C1 = 35 pF (3)

5.0

7.5

10.0

ns

I/O input to non-registered C1 = 35 pF (3)

output

5.0

7.5

10.0

t_SU

t_H

Global clock setup time

Global clock hold time

(3)

3.8

0.0

1.0

5.6

0.0

1.5

7.5

0.0

1.5

ns

t_FSU

Global clock setup time of

fast input

t_FH

Global clock hold time for

fast input

1.0

2.5

1.0

3.0

1.0

3.0

ns

t_FZHSU

Global clock setup time of

fast input with zero hold

time

t_FZHH

Global clock hold time of

fast input with zero hold

time

0.0

1.0

0.0

1.0

0.0

1.0

ns

t_CO1

Global clock to output

delay

C1 = 35 pF

2.9

4.5

4.4

6.7

5.8

8.9

t_CH

Global clock high time

Global clock low time

Array clock setup time

Array clock hold time

2.0

2.2

0.0

1.0

2.0

3.0

3.3

0.0

1.0

3.0

4.0

4.4

0.0

1.0

4.0

ns

t_CL

t_ASU

t_AH

(3)

t_ACO1

t_ACH

t_ACL

t_CPPW

Array clock to output delay C1 = 35 pF (3)

Array clock high time

Array clock low time

Minimum pulse width for

clear and preset

t_CNT

Minimum global clock

period

(3)

5.3

7.9

10.5

ns

MHz

ns

f_CNT

Maximum internal global

clock frequency

(3), (4)

(3)

188.7

126.6

95.2

t_ACNT

f_ACNT

Minimum array clock

period

Maximum internal array

clock frequency

(3), (4)

MHz

Altera Corporation

43

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 31. EPM7256B Internal Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-7

Min Max Min Max Min Max

Unit

-5

-10

Input pad and buffer delay

I/O input pad and buffer delay

Fast input delay

t

0.6

0.7

1.5

0.9

1.1

1.5

1.2

1.4

1.5

ns

IN

IO

FIN

FIND

Programmable delay adder for

fast input

Shared expander delay

Parallel expander delay

Logic array delay

t

1.9

0.3

1.5

0.7

0.0

0.8

2.8

0.5

2.2

1.0

0.0

1.2

3.7

0.6

2.8

1.3

0.0

1.6

ns

SEXP

PEXP

LAD

Logic control array delay

Internal output enable delay

LAC

IOE

Output buffer and pad delay

slow slew rate = off

V_CCIO= 3.3 V

C1 = 35 pF

C1 = 5 pF

OD1

Output buffer and pad delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

t

5.8

4.0

9.0

4.0

6.2

4.0

9.0

4.0

6.6

5.0

ns

OD3

ZX1

ZX3

Output buffer enable delay

slow slew rate = off

V_CCIO= 3.3 V

Output buffer enable delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

10.0

5.0

Output buffer disable delay

Register setup time

Register hold time

t

ns

XZ

1.4

0.6

1.0

1.5

2.1

0.9

1.5

2.9

1.2

1.5

SU

H

Register setup time of fast input

Register hold time of fast input

Register delay

FSU

FH

0.8

0.5

0.7

1.9

0.8

1.6

4.0

1.2

0.8

1.0

1.1

2.9

1.2

2.4

4.0

1.6

1.2

1.3

1.4

3.8

1.6

3.2

5.0

RD

Combinatorial delay

Array clock delay

COMB

IC

Register enable time

Global control delay

Register preset time

Register clear time

PIA delay

EN

GLOB

PRE

CLR

PIA

LPA

(3)

(7)

Low-power adder

44

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 32. Selectable I/O Standard Input Adder Delays (Excluding Path to Fast Input Register)

I/O Standard

Speed Grade

-7

Unit

-5

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.4

0.0

1.1

0.8

0.0

0.3

0.7

0.0

1.8

1.3

0.0

0.4

0.9

0.0

2.4

1.8

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Table 33. Selectable I/O Standard Input Adder Delays (Path to Fast Input Register)

I/O Standard

Speed Grade

-7

Unit

-5

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.4

0.0

1.1

0.8

0.0

0.3

0.7

0.0

1.8

1.3

0.0

0.4

0.9

0.0

2.4

1.8

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Altera Corporation

45

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 34. Standard Output Adder Delays

I/O Standard

Speed Grade

Unit

-5

-7

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.0

0.3

0.0

0.4

ns

1.3

2.2

2.9

0.0

GTL+

–0.2

–0.1

–0.3

–0.2

–0.4

–0.2

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Notes to tables:

(1) These values are specified under the Recommended Operating Conditions in Table 12 on page 25.

(2) MAX 7000B timing values are preliminary.

(3) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing value.

(4) Measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.

(5) The f_MAXvalues represent the highest frequency for pipelined data.

(6) Operating conditions: V_CCIO= 2.5 ± 5% for commercial and industrial use.

(7) The t_LPAparameter must be added to the t_LAD, t_LAC, t_IC, t_ACL, t_CPPW, t_EN, and t_SEXPparameters for macrocells

running in low-power mode.

46

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Tables 35 and 36 show EPM7512B AC operating conditions.

Table 35. EPM7512B External Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-7

Unit

-6

-10

Min

Max

Min

Max

Min

Max

t_PD1

t_PD2

Input to non-registered

output

C1 = 35 pF (3)

6.0

7.5

10.0

ns

I/O input to non-registered C1 = 35 pF (3)

output

6.0

7.5

10.0

t_SU

t_H

Global clock setup time

Global clock hold time

(3)

4.3

0.0

1.0

5.4

0.0

1.5

7.2

0.0

1.5

ns

t_FSU

Global clock setup time of

fast input

t_FH

Global clock hold time of

fast input

1.0

2.5

1.0

3.0

1.0

3.0

ns

t_FZHSU

Global clock setup time of

fast input with zero hold

time

t_FZHH

Global clock hold time of

fast input with zero hold

time

0.0

1.0

0.0

1.0

0.0

1.0

ns

t_CO1

Global clock to output

delay

C1 = 35 pF

3.9

6.0

4.9

7.5

6.7

t_CH

Global clock high time

Global clock low time

Array clock setup time

Array clock hold time

3.0

2.2

0.0

1.0

3.0

2.8

0.0

1.0

3.0

4.0

3.8

0.0

1.0

4.0

ns

t_CL

t_ASU

t_AH

(3)

t_ACO1

t_ACH

t_ACL

t_CPPW

Array clock to output delay C1 = 35 pF (3)

Array clock high time

10.1

Array clock low time

Minimum pulse width for

clear and preset

t_CNT

Minimum global clock

period

(3)

6.8

8.6

11.5

ns

MHz

ns

f_CNT

Maximum internal global

clock frequency

(3), (4)

(3)

147.1

116.3

87.0

t_ACNT

f_ACNT

Minimum array clock

period

Maximum internal array

clock frequency

(3), (4)

MHz

Altera Corporation

47

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 36. EPM7512B Internal Timing Parameters

Notes (1), (2)

Symbol

Parameter

Conditions

Speed Grade

-7

Min Max Min Max Min Max

Unit

-6

-10

Input pad and buffer delay

I/O input pad and buffer delay

Fast input delay

t

0.6

1.5

0.7

1.9

1.5

0.9

2.6

1.5

ns

IN

IO

FIN

FIND

Programmable delay adder for

fast input

Shared expander delay

Parallel expander delay

Logic array delay

t

2.1

0.3

1.7

0.8

0.0

0.8

2.7

0.4

2.2

1.0

0.0

1.0

3.5

0.5

2.8

1.3

0.0

1.5

ns

SEXP

PEXP

LAD

Logic control array delay

Internal output enable delay

LAC

IOE

Output buffer and pad delay

slow slew rate = off

V_CCIO= 3.3 V

C1 = 35 pF

C1 = 5 pF

OD1

Output buffer and pad delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

t

5.8

4.0

9.0

4.0

6.0

4.0

9.0

4.0

6.5

5.0

ns

OD3

ZX1

ZX3

Output buffer enable delay

slow slew rate = off

V_CCIO= 3.3 V

Output buffer enable delay

slow slew rate = on

V_CCIO= 2.5 V or 3.3 V

10.0

5.0

Output buffer disable delay

Register setup time

Register hold time

t

ns

XZ

1.7

0.5

1.0

1.5

2.1

0.6

1.5

3.0

0.8

1.5

SU

H

Register setup time of fast input

Register hold time of fast input

Register delay

FSU

FH

1.0

0.5

1.2

0.8

1.5

2.5

0.8

2.4

4.0

1.3

0.6

1.5

1.0

1.9

3.1

1.0

3.0

4.0

1.7

0.8

2.0

1.3

2.6

4.1

1.4

4.0

5.0

RD

Combinatorial delay

Array clock delay

COMB

IC

Register enable time

Global control delay

Register preset time

Register clear time

PIA delay

EN

GLOB

PRE

CLR

PIA

LPA

(3)

(7)

Low-power adder

48

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 37. Selectable I/O Standard Input Adder Delays (Excluding Path to Fast Input Register)

I/O Standard

Speed Grade

-7

Unit

-6

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.4

0.0

1.1

0.8

0.0

0.3

0.7

0.0

1.8

1.3

0.0

0.4

0.9

0.0

2.4

1.8

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Table 38. Selectable I/O Standard Input Adder Delays (Path to Fast Input Register)

I/O Standard

Speed Grade

-7

Unit

-6

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.4

0.0

0.7

0.4

0.0

0.3

0.7

0.0

1.2

0.7

0.0

0.4

0.9

0.0

1.6

0.9

ns

GTL+

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Altera Corporation

49

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 39. Selectable I/O Standard Output Adder Delays

I/O Standard

Speed Grade

Unit

-6

-7

-10

Min

Max Min Max

Min

Max

3.3 V TTL/CMOS

2.5 V TTL/CMOS

1.8 V TTL/CMOS

PCI

0.0

0.2

0.0

0.3

0.0

0.4

ns

1.3

2.2

2.9

0.0

GTL+

-0.2

-0.1

-0.3

-0.2

-0.4

-0.2

SSTL-3 Class I

SSTL-3 Class II

SSTL-3 Class I

SSTL-3 Class II

Notes to tables:

(1) These values are specified under the Recommended Operating Conditions in Table 12 on page 25.

(2) MAX 7000B timing values are preliminary.

(3) These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing value.

(4) Measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.

(5) The f_MAXvalues represent the highest frequency for pipelined data.

(6) Operating conditions: V_CCIO= 2.5 ± 5% for commercial and industrial use.

(7) The t_LPAparameter must be added to the t_LAD, t_LAC, t_IC, t_ACL, t_CPPW, t_EN, and t_SEXPparameters for macrocells

running in low-power mode.

Supply power (P) versus frequency (f

devices is calculated with the following equation:

, in MHz) for MAX 7000B

MAX

Power

Consumption

P = P + P = I × V + P

INT

IO

CCINT

CC

IO

The P value, which depends on the device output load characteristics

IO

and switching frequency, can be calculated using the guidelines given in

Application Note 74 (Evaluating Power for Altera Devices).

The I

value depends on the switching frequency and the application

CCINT

logic. The I

value is calculated with the following equation:

CCINT

I

=

CCINT

(A × MC

) + [B × (MC

– MC

)] + (C × MC

× f

× tog

)

LC

TON

DEV

TON

USED

MAX

The parameters in this equation are:

50

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

MC

=

Number of macrocells with the Turbo Bit^TMoption turned

on, as reported in the MAX+PLUS II Report File (.rpt)

Number of macrocells in the device

Total number of macrocells in the design, as reported in

the Report File

TON

MC

=

DEV

USED

f

tog

=

Highest clock frequency to the device

Average percentage of logic cells toggling at each clock

(typically 12.5%)

MAX

LC

A, B, C

=

Constants, shown in Table 40

Table 40. MAX 7000B I Equation Constants

CC

Device

A

B

C

EPM7032B

EPM7064B

EPM7128B

EPM7256B

EPM7512B

0.53

0.22

0.010

This calculation provides an I estimate based on typical conditions

CC

using a pattern of a 16-bit, loadable, enabled, up/ down counter in each

LAB with no output load. Actual I should be verified during operation

CC

because this measurement is sensitive to the actual pattern in the device

and the environmental operating conditions.

Figure 15. I vs. Frequency for EPM7032B Devices

CC

EPM7032B

30

285.7 MHz

VCC = 2.5 V

25

20

15

10

Room Temperature

High Speed

Typical I^CC

Active (mA)

166.7 MHz

Low Power

5

0

50

100

150

200

250

300

Frequency (MHz)

Altera Corporation

51

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 16. I vs. Frequency for EPM7064B Devices

CC

70

60

EPM7064B

VCC = 2.5 V

Room Temperature

277.8 MHz

Typical I^CC50

Active (mA)

40

30

20

High Speed

140.9 MHz

Low Power

10

0

50

100

150

200

250

300

Frequency (MHz)

Figure 17. I vs. Frequency for EPM7128B Devices

CC

EPM7128B

120

238.1 MHz

VCC = 2.5 V

Room Temperature

100

80

High Speed

Typical I^CC

Active (mA)

60

129.9 MHz

40

Low Power

20

0

50

100

150

200

250

Frequency (MHz)

52

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Figure 18. I vs. Frequency for EPM7256B Devices

CC

EPM7256B

250

VCC = 2.5 V

Room Temperature

188.7 MHz

200

150

High Speed

Typical I^CC

Active (mA)

100

107.5 MHz

50

0

Low Power

50

100

150

200

Frequency (MHz)

Figure 19. I vs. Frequency for EPM7512B Devices

CC

EPM7512B

450

VCC = 2.5 V

Room Temperature

400

147.1 MHz

350

300

High Speed

Typical I^CC

250

Active (mA)

200

88.5 MHz

150

100

Low Power

50

0

20

40

60

80

100

120

140

160

Frequency (MHz)

Altera Corporation

53

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Tables 41 through 52 show the pin names and numbers for MAX 7000B

device packages.

Device

Pin-Outs

Table 41. EPM7032B Dedicated Pin-Outs

Dedicated Pin

44-Pin PLCC 44-Pin TQFP 48-Pin VTQFP

INPUT/GCLK1

43

37

39

38

40

1

41

INPUT/GCLRn

INPUT/OE1

INPUT/OE2/GCLK2

TDI(1)

1

43

44

42

2

44

7

2

TMS(1)

13

7

8

TCK(1)

32

26

32

5

29

TDO(1)

38

35

VREFA(2)

VREFB(2)

GNDINT

11

6

31

25

16, 36

4, 24

17, 41

9

28

22, 42

10, 30

3, 23

18, 40

5, 27

19, 45

10

GNDIO

VCCINT(2.5 V)

VCCIO1(1.8 V, 2.5 V, or 3.3 V) 15

VCCIO2(1.8 V, 2.5 V, or 3.3 V) 35

29

–

32

No Connect (N.C.)

–

1, 13, 24, 37

36

Total User I/O Pins (3)

36

54

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 42. EPM7032B I/O Pin–Outs & I/O Standards

LAB

MC

44-Pin

PLCC

44-Pin

TQFP

48-Pin

VTQFP

IOGND

Groups

IOVCC

Groups

I/O Bank

(200 mA)

(100 mA)

A

1

4

5

6

42

43

44

46

47

48

A

B

A

B

A

B

D

C

1

2

3

4

7 (1)

8

1 (1)

2

2 (1)

3

5

6

9

3

4

7

11 (2)

12

5 (2)

6

6 (2)

7

8

9

13 (1)

14

7 (1)

8

8 (1)

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

16

10

11

17

11

12

18

12

14

19

13

15

20

14

16

21

15

17

B

41

35

39

40

34

38

39

33

36

38 (1)

37

32 (1)

31

35 (1)

34

36

30

33

34

28

31

33

27

30

32 (1)

31 (2)

29

26 (1)

25 (2)

23

29 (1)

28 (2)

26

28

22

25

27

21

23

26

20

22

25

19

21

24

18

20

Altera Corporation

55

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Notes to tables:

(1) This pin may function as either a JTAG port or a user I/ O pin. If the device is configured to use the JTAG ports for

in-system programming, this pin is not available as a user I/ O pin.

(2) This pin may function as either a VREFpin or a user I/ O pin. If this pin is programmed to be a VREFpin for using

the advanced I/ O standards, this pin is not available as a user I/ O pin.

(3) The user I/ O pin count includes dedicated input pins and all I/ O pins.

Table 43. EPM7064B Dedicated Pin-Outs

Dedicated Pin

44-Pin

PLCC

44-Pin

TQFP

48-Pin

VTQFP

100-Pin

TQFP

100-Pin

FineLine BGA

INPUT/GCLK1

43

1

37

39

38

40

1

41

43

42

44

2

87

89

88

90

4

A6

INPUT/GCLRN

INPUT/OE1

INPUT/OE2/GLCK2

TDI(1)

B5

44

2

B6

A5

7

A1

TMS(1)

13

32

38

11

31

7

8

15

62

73

12

60

F3

TCK(1)

26

32

5

29

35

6

F8

TDO(1)

A10

F1

VREFA(2)

VREFB(2)

GNDINT

25

28

E8

22, 42

10, 30

16, 36

4, 24

18, 40

5, 27

38, 86

D6, G5

GNDIO

11, 26, 43, 59, C3, D7, E5, F6,

74, 95

G4, H8

VCCINT(2.5 V)

3, 23

15

17, 41

9

19, 45

10

39, 91

D5, G6

VCCIO1(1.8 V, 2.5V,

3, 18, 34

D4, F5, H3

3.3V)

VCCIO2(1.8 V, 2.5V,

3.3V)

35

–

29

–

32

–

51, 66, 82

C8, E6, G7

No Connect

1, 2, 5, 7, 22,

B1, B10, C1,

24, 27, 28, 49, C9, C10, D8,

50, 53, 55, 70, E3, E4, H1, H9,

72, 77, 78

H10, J1, J2,

J10, K1, K9

Total User I/O Pins (3)

36

40

68

56

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 44. EPM7064B I/O Pins & I/O Standards (Part 1 of 2)

LAB

MC

44-Pin

PLCC

44-Pin

TQFP

48-Pin

VTQFP

IOGND

Group

IOVCC

Group

I/O Bank

(200 mA)

(100 mA)

A

1

12

–

6

–

7

–

B

–

A

1

2

–

3

11 (2)

5 (2)

3

6 (2)

4

B

A

–

A

–

4

9

5

8

2

3

6

–

7

–

8

7 (1)

–

1 (1)

–

2 (1)

1

A

–

A

–

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

–

6

44

–

48

–

A

–

A

–

5

43

–

47

–

A

–

A

–

4

42

15

–

46

17

–

A

B

–

A

B

–

B

21

–

20

19

18

–

14

13

12

–

16

15

14

13

–

B

–

B

–

17

16

–

11

10

–

12

11

–

B

–

B

–

14

–

8

9

B

–

A

–

13 (1)

7 (1)

8 (1)

B

A

Altera Corporation

57

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 44. EPM7064B I/O Pins & I/O Standards (Part 2 of 2)

LAB

MC

44-Pin

PLCC

44-Pin

TQFP

48-Pin

VTQFP

IOGND

Group

IOVCC

Group

I/O Bank

(200 mA)

(100 mA)

C

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

24

–

18

–

20

–

B

–

C

2

–

25

26

27

–

19

20

21

–

21

22

23

–

B

–

C

–

24

25

26

–

B

–

C

–

28

29

–

22

23

–

31 (2)

25 (2)

28 (2)

–

A

–

C

–

32 (1)

33

–

26 (1)

27

–

29 (1)

30

–

A

–

C

–

D

34

36

37

–

28

30

31

–

31

33

34

–

A

–

C

D

–

38 (1)

39

–

32 (1)

33

–

35 (1)

36

–

A

–

D

–

37

–

A

–

D

–

40

–

34

–

38

–

A

–

D

–

41

35

39

A

D

58

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This pin may function as either a JTAG port or a user I/ O pin. If the device is configured to use the JTAG ports for

in-system programming, this pin is not available as a user I/ O pin.

(2) This pin may function as either a VREFpin or a user I/ O pin. If this pin is programmed to be a VREFpin for using

the advanced I/ O standards, this pin is not available as a user I/ O pin.

(3) The user I/ O pin count includes dedicated input pins and all I/ O pins.

Table 45. EPM7064B I/O Pins & I/O Standards (Part 1 of 3)

LAB

MC

100-Pin

TQFP

100-Pin

FineLine

BGA

IOGND Group IOVCC Group

(200 mA)

I/O Bank

A

1

14

13

F4

E2

E1

D2

D1

D3

C2

C

B (200 mA)

A (100 mA)

1

2

C

B

A

3

12 (2)

10

9

4

5

6

8

7

6

8

4 (1)

100

99

98

97

96

94

93

92

A1 (1)

B2

9

10

11

12

13

14

15

16

A2

A3

B3

A4

B4

C4

C5

Altera Corporation

59

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 45. EPM7064B I/O Pins & I/O Standards (Part 2 of 3)

LAB

MC

100-Pin

TQFP

100-Pin

FineLine

BGA

IOGND Group IOVCC Group

(200 mA)

I/O Bank

B

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

37

36

35

33

32

31

30

29

25

23

21

20

19

17

16

K5

J5

D

C

D

E

F

D (100 mA)

C (200 mA)

B (200 mA)

E (100 mA)

F (200 mA)

1

2

H5

K4

J4

H4

J3

K3

K2

H2

G2

G1

G3

F2

F1 (2)

F3 (1)

K6

15 (1)

40

C

41

J6

42

H6

44

K7

45

J7

46

H7

47

J8

48

K8

52

K10

J9

54

56

G9

57

G10

G8

58

60 (2)

61

F9

F10

F8 (1)

F

62 (1)

F

60

Altera Corporation

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 45. EPM7064B I/O Pins & I/O Standards (Part 2 of 3)

LAB

MC

100-Pin

TQFP

100-Pin

FineLine

BGA

IOGND Group IOVCC Group

(200 mA)

I/O Bank

B

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

37

36

35

33

32

31

30

29

25

23

21

20

19

17

16

K5

J5

D

C

D

E

F

D (100 mA)

C (200 mA)

B (200 mA)

E (100 mA)

F (200 mA)

1

2

H5

K4

J4

H4

J3

K3

K2

H2

G2

G1

G3

F2

F1 (2)

F3 (1)

K6

15 (1)

40

C

41

J6

42

H6

44

K7

45

J7

46

H7

47

J8

48

K8

52

K10

J9

54

56

G9

57

G10

G8

58

60 (2)

61

F9

F10

F8 (1)

F

62 (1)

F

60

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 45. EPM7064B I/O Pins & I/O Standards (Part 3 of 3)

LAB

MC

100-Pin

TQFP

100-Pin

FineLine

BGA

IOGND Group IOVCC Group

(200 mA)

I/O Bank

D

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

63

64

65

67

68

69

71

F7

E9

F

F (200 mA)

G (200 mA)

H (100 mA)

2

F

A

E10

E8 (2)

E7

D9

D10

A10 (1)

B9

73 (1)

75

76

A9

79

A8

80

B8

81

A7

83

B7

84

C7

85

C6

Notes to tables:

(1) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for

in-system programming, this pin is not available as a user I/O pin.

(2) This pin may function as either a VREFpin or a user I/O pin. If this pin is programmed to be a VREFpin for using

the advanced I/O standards, then this pin is not available as a user I/O pin.

(3) The user I/O pin count includes dedicated input pins and all I/O pins.

Altera Corporation

61

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 46. EPM7128B Dedicated Pin-Outs

Dedicated Pin

48-Pin

VTQFP

100-Pin

TQFP

100-Pin

FineLine

BGA

144-Pin

TQFP

256-Pin

FineLine BGA

INPUT/GCLK1

41

87

A6

125

D9

E8

INPUT/GCLRn

INPUT/OE1

INPUT/OE2/GCLK2

TDI(1)

43

42

44

2

89

88

90

4

B5

127

126

128

4

B6

E9

A5

D8

D4

J6

A1

TMS(1)

8

15

62

73

12

60

38, 86

F3

20

TCK(1)

29

35

6

F8

89

J11

D13

J4

TDO(1)

A10

F1

104

14

VREFA(2)

VREFB(2)

GNDINT

28

18, 40

E8

87

H11

D6, G5

52, 57, 124, A8, C9, G9, K8, P9

129

GNDIO

5, 27

11, 26, 43, C3, D7,

59, 74, 95 E5, F6,

G4, H8

3, 13, 17,

A3, B10, C2, D14, F6, G10, H8, J9,

33, 59, 64, K7, L11, M3, P6, P10, R2, R3, T1,

85, 105, 135 T15

VCCINT(2.5 V Only)

19, 45

39, 91

D5, G6

51, 58, 123, B9, C8, G8, K9, P8

130

VCCIO1(1.8 V, 2.5 V, 10

3, 18, 34

D4, F5, H3 24, 50, 144 B3, B5, G3, G7, J8, L3, L6, T2, T3

or 3.3 V)

VCCIO2(1.8 V, 2.5 V, 32

or 3.3 V)

51, 66, 82 C8, E6, G7 73, 76, 95, C14, E15, F11, G15, H9, K10, M15,

115 P14

No Connect (N.C.)

–

1, 2, 12, 19, A1, A2, A4, A5, A6, A7, A9, A10,

34, 35, 36, A11, A12, A13, A14, A15, A16, B1,

43, 46, 47, B2, B4, B6, B7, B8, B11, B12, B13,

48, 49, 66, B14, B 15, B16, C1, C3, C4, C6,

75, 90, 103, C11, C13, C15, C16, D1, D2, D3,

108, 120,

121, 122

D15, D16, E1, E2, E3, E14, E16,

F1, F2, F15, F16, G1, G2, G14,

G16, H1, H2, H15, H16, J1, J2,

J15, J16, K1, K2, K3, K14, K15,

K16, L1, L2, L15, L16, M1, M14,

M16, N1, N2, N3, N14, N15, N16,

P1, P2, P3, P4, P12, P13, P15,

P16, R1, R4, R5, R6, R7, R8, R9,

R11, R12, R13, R14, R15, R16, T4,

T5, T6, T7, T8, T9, T10, T11, T12,

T13, T14, T16

Total User I/O Pins (2) 40

84

100

62

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 47. EPM7128B I/O Pins & I/O Standard Groups (Part 1 of 4)

LAB MC 48-Pin IOGND

IOVCC 100-Pin 100-Pin 144-Pin 256-Pin IOGND

IOVCC

Group for Bank

Other

I/O

VTQFP Group for Group for TQFP FineLine TQFP FineLine Group

48-Pin

VTQFP

(200 mA) (100 mA)

48-Pin

VTQFP

BGA

for Other

Packages Packages

(200 mA)

A

1

2

3

4

5

6

7

8

9

10

1

–

48

–

A

–

A

–

A

–

A

–

B

–

B

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

2

C1

143

–

F4

B

–

A (100 mA) 1

–

1

B1

–

142

141

140

139

–

E4

C5

E5

D5

–

B

–

A (100 mA) 1

–

100

99

–

B2

A2

–

1

98

97

–

A3

B3

–

138

137

–

D6

E6

–

B

–

A (100 mA) 1

–

1

11 47

12

13 46

96

–

A4

–

136

134

133

132

–

D7

C7

E7

F7

–

B

A

–

A (100 mA) 1

–

94

93

–

B4

C4

–

14

15

16

17

18

19

20

–

7

–

1

92

14

–

C5

F4

–

131

18

–

F8

J7

–

A

C

–

A (100 mA) 1

B (200 mA) 1

B

–

1

13

–

E2

–

16

15

14 (2)

11

–

H5

H3

H4

H6

–

C

B

–

B (200 mA) 1

21 6 (2)

12 (2)

10

–

E1

E3

–

22

23

24

25

26

27

28

29

30

31

–

4

–

3

–

1

9

E4

D2

–

10

9

H7

G5

–

B

–

B (200 mA) 1

8

–

1

7

D1

–

8

G4

F3

G6

F5

–

B

–

B (200 mA) 1

–

7

6

D3

C2

–

6

5

–

1

32 2 (1)

4 (1)

A1 (1)

4 (1)

D4 (1)

B

B (200 mA) 1

Altera Corporation

63

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 47. EPM7128B I/O Pins & I/O Standard Groups (Part 2 of 4)

LAB MC 48-Pin IOGND

IOVCC 100-Pin 100-Pin 144-Pin 256-Pin IOGND

IOVCC

Group for Bank

Other

I/O

VTQFP Group for Group for TQFP FineLine TQFP FineLine Group

48-Pin

VTQFP

(200 mA) (100 mA)

48-Pin

VTQFP

BGA

for Other

Packages Packages

(200 mA)

C

33 13

34

35 12

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

A

–

A

–

B

–

B

–

B

–

B

25

–

K1

32

–

N4

C

–

C (200 mA) 1

–

1

24

–

J1

–

31

30

29

28

–

M4

M2

L4

L5

–

C

–

C (200 mA) 1

36

37

38

39

40

41

42

–

23

22

–

H1

H2

–

1

21

20

–

G2

G1

–

27

26

–

K5

K4

–

C

–

C (200 mA) 1

–

1

43 11

19

–

G3

–

25

23

22

21

–

K6

J3

J5

J4 (2)

–

C

–

C (200 mA) 1

B (200 mA) 1

44

45

46

47

–

9

–

17

16

–

F2

F1 (2)

–

1

48 8 (1)

15 (1)

37

–

F3 (1)

K5

–

20 (1)

56

–

J6 (1)

N8

–

C

D

–

B (200 mA) 1

D (100 mA) 1

D

49

50

–

1

51 17

36

–

J5

–

55

54

53

45

–

M8

P7

L8

N7

–

D

–

D (100 mA) 1

C (200 mA) 1

52

53

54

55

–

35

33

–

H5

K4

–

1

56 16

32

31

–

J4

H4

–

44

42

–

M7

L7

–

D

–

C (200 mA) 1

57

58

–

1

59 15

30

–

J3

–

41

40

39

38

–

M6

P5

N6

M5

–

D

–

C (200 mA) 1

60

61

62

63

–

29

28

–

K3

J2

–

1

64 14

27

K2

37

N5

D

C (200 mA) 1

64

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 47. EPM7128B I/O Pins & I/O Standard Groups (Part 3 of 4)

LAB MC 48-Pin IOGND

IOVCC 100-Pin 100-Pin 144-Pin 256-Pin IOGND

IOVCC

Group for Bank

Other

I/O

VTQFP Group for Group for TQFP FineLine TQFP FineLine Group

48-Pin

VTQFP

(200 mA) (100 mA)

48-Pin

VTQFP

BGA

for Other

Packages Packages

(200 mA)

E

65

66

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

A

–

A

–

C

–

C

–

C

–

C

–

C

–

C

–

C

–

C

–

C

40

–

K6

60

–

N9

D

–

E (100 mA) 2

–

2

67 20

68

69 21

41

–

J6

–

61

62

63

65

–

M9

R10

L9

D

E

–

E (100 mA) 2

–

42

44

–

H6

K7

–

70

71

–

N10

–

2

72 22

45

46

–

J7

H7

–

67

68

–

M10

L10

–

E

–

E (100 mA) 2

73

74

–

2

75 23

76

77 24

47

–

J8

–

69

70

71

72

–

M11

P11

N11

N12

–

E

–

E (100 mA) 2

–

48

49

–

K8

K9

–

78

79

80

81

82

–

2

50

52

–

K10

J10

–

74

77

–

N13

M13

–

E

–

E (100 mA) 2

F (200 mA) 2

F

–

2

83 25

53

–

H10

–

78

79

80

81

–

L13

L14

L12

M12

–

E

–

F (200 mA) 2

84

85

86

87

88

89

90

–

54

55

–

H9

J9

–

2

56

57

–

G9

G10

–

82

83

–

K12

K13

–

E

–

F (200 mA) 2

–

2

91 26

92

93 28 (2)

58

–

G8

–

84

86

87 (2)

88

–

K11

J14

J12

J13

–

E

F

–

F (200 mA) 2

–

60 (2)

61

–

F9

F10

–

94

95

–

2

96 29 (1)

62 (1)

F8 (1)

89 (1)

J11 (1)

F

F (200 mA) 2

Altera Corporation

65

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 47. EPM7128B I/O Pins & I/O Standard Groups (Part 4 of 4)

LAB MC 48-Pin IOGND

IOVCC 100-Pin 100-Pin 144-Pin 256-Pin IOGND

IOVCC

Group for Bank

Other

I/O

VTQFP Group for Group for TQFP FineLine TQFP FineLine Group

48-Pin

VTQFP

(200 mA) (100 mA)

48-Pin

VTQFP

BGA

for Other

Packages Packages

(200 mA)

G

97

98

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

C

–

C

–

D

–

D

–

D

–

D

–

D

–

D

–

D

–

63

–

F7

91

–

J10

F

–

F (200 mA) 2

–

2

99 30

100 –

101 31

102 –

103 –

104 –

105 –

106 –

107 33

108 –

109 34

110 –

111 –

112 35 (1)

113 –

114 –

115 36

116 –

117 37

118 –

119 –

120 –

121 –

122 –

123 38

124 –

125 39

126 –

127 –

128 –

64

–

E9

–

92

93

94

96

–

H12

H14

H13

H11 (2)

–

F

–

F (200 mA) 2

G (200 mA) 2

65

67

–

E10

E8 (2)

–

2

68

69

–

E7

D9

–

97

98

–

H10

G12

–

F

–

G (200 mA) 2

–

2

70

–

D10

–

99

100

101

102

–

G13

F14

G11

F12

–

F

–

G (200 mA) 2

71

72

–

D8

C9

–

2

73 (1)

75

–

A10 (1) 104 (1) D13 (1)

F

A

–

G (200 mA) 2

H

C10

–

106

–

F13

–

2

76

–

B10

–

107

109

110

111

–

E13

C12

E12

D12

–

A

–

G (200 mA) 2

77

78

–

B9

A9

–

2

79

80

–

A8

B8

–

112

113

–

D11

E11

–

A

–

G (200 mA) 2

–

2

81

–

A7

–

114

116

117

118

–

D10

C10

E10

F10

–

A

–

G (200 mA) 2

H (100 mA) 2

83

84

–

B7

C7

–

2

85

C6

119

F9

A

H (100 mA) 2

66

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for

in-system programming, this pin is not available as a user I/O pin.

(2) This pin may function as either a VREFpin or a user I/O pin. If this pin is programmed to be a VREFpin for using

the advanced I/O standards, then this pin is not available as a user I/O pin.

(3) The user I/O pin count includes dedicated input pins and all I/O pins.

Table 48. EPM7256B Dedicated Pin-Outs

Dedicated Pin

100-Pin TQFP 144-Pin TQFP

208-Pin PQFP

256-Pin

FineLine BGA

INPUT/GCLK1

87

125

127

126

128

4

184

D9

E8

INPUT/GCLRn

INPUT/OE1

INPUT/OE2/GCLK2

TDI(1)

89

88

182

183

181

176

127

30

E9

90

D8

D4

J6

4

TMS(1)

15

20

TCK(1)

62

89

J11

D13

J4

TDO(1)

73

104

14

189

128

22

VREFA (2)

VREFB (2)

GNDINT

12

60

87

H11

38, 86

52, 57, 124, 129 75, 82, 180, 185 A8, C9, G9, K8, P9

GNDIO(2)

11, 26, 43, 59, 3, 13, 17, 33,

14, 32, 50, 72,

59, 64, 85, 105, 94, 116, 134,

135 152, 174, 200

A3, B10, C2, D14, F6, G10, H8,

J9, K7, L11, M3, P6, P10, R2,

R3, T1, T15

74, 95

VCCINT(2.5 V Only)

39, 91

51, 58, 123, 130 74, 83, 179, 186 B9, C8, G8, K9, P8

VCCIO1(1.8 V, 2.5 V, 3, 18, 34

or 3.3 V)

24, 50, 144

85, 107, 125,

143, 165

B3, B5, G3, G7, J8, L3, L6, T2,

T3

VCCIO2(1.8 V, 2.5 V, 51, 66, 82

or 3.3 V)

73, 76, 95, 115 5, 23, 41, 63, 191 C14, E15, F11, G15, H9, K10,

M15, P14

No Connect (N.C.)

–

1, 2, 51, 52, 53, A1, A2, A6, A12, A13, A14, A15,

54, 103, 104,

105, 106, 155,

156, 157, 158,

207, 208

A16, B1, B2, B15, B16, C1, C15,

C16, D1, D3, D15, D16, G1,

G16, H15, H16, J1, K1, L1, L2,

M1, M16, N1, N2, N14, N15,

N16, P1, P2, P15, P16, R1, R14,

R15, R16, T7, T8, T10, T11, T14,

T16

Total User I/O Pins

84

120

164

Altera Corporation

67

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 49. EPM7256B I/O Pin-Outs & I/O Standards (Part 1 of 8)

Lab

MC

100-Pin

TQFP

IOGND

Group for

100-Pin

TQFP

IOVCC

Group for

100-Pin

TQFP

144-Pin

TQFP

IOGND

Group for

144-Pin

TQFP

IOVCC

Group for

144-Pin

TQFP

I/O Bank

(200 mA)

A

1

2

3

4

5

6

7

8

9

–

2

1

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

2

–

1

–

1

B

–

B (200 mA)

–

B

–

B (200 mA)

143

–

A (100 mA)

–

A (100 mA)

–

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

–

100

–

A (100 mA) 142

B

–

A (100 mA)

–

141

B

–

A (100 mA)

99

–

A (100 mA) 140

A (100 mA)

–

98

–

A (100 mA) 139

B

–

A (100 mA)

B

–

10

–

9

–

8

7

–

6

–

5

–

C

–

B (200 mA)

–

C

–

B (200 mA)

–

8

B (200 mA)

C

–

B (200 mA)

7

B (200 mA)

–

6

B (200 mA)

C

–

B (200 mA)

–

5

B (200 mA)

C

–

B (200 mA)

–

4 (1)

B (200 mA) 4 (1)

C

B (200 mA)

68

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 49. EPM7256B I/O Pin-Outs & I/O Standards (Part 2 of 8)

Lab

MC

100-Pin

TQFP

IOGND

Group for

100-Pin

TQFP

IOVCC

Group for

100-Pin

TQFP

144-Pin

TQFP

IOGND

Group for

144-Pin

TQFP

IOVCC

Group for

144-Pin

TQFP

I/O Bank

(200 mA)

C

33

–

C

–

C

–

C

–

C

D

–

D

–

D

–

D

–

36

D

–

C (200 mA)

1

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

–

35

–

D

–

C (200 mA)

–

34

–

D

–

C (200 mA)

–

25

24

–

C (200 mA) 32

C (200 mA) 31

C

–

C (200 mA)

–

23

–

C (200 mA) 30

C

–

C (200 mA)

–

22

–

C (200 mA) 29

C

–

C (200 mA)

–

21

31

–

C (200 mA) 28

C (200 mA) 44

C

D

–

C (200 mA)

D

C (200 mA)

–

30

–

C (200 mA) 43

D

–

C (200 mA)

–

29

28

–

C (200 mA) 42

C (200 mA) 41

D

–

C (200 mA)

–

40

–

D

–

C (200 mA)

–

39

–

D

–

C (200 mA)

–

38

–

D

–

C (200 mA)

–

27

C (200 mA) 37

D

C (200 mA)

Altera Corporation

69

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 49. EPM7256B I/O Pin-Outs & I/O Standards (Part 3 of 8)

Lab

MC

100-Pin

TQFP

IOGND

Group for

100-Pin

TQFP

IOVCC

Group for

100-Pin

TQFP

144-Pin

TQFP

IOGND

Group for

144-Pin

TQFP

IOVCC

Group for

144-Pin

TQFP

I/O Bank

(200 mA)

E

65

–

B

–

A

–

A

–

A

–

C

–

C

–

B

–

B

–

1

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

–

138

–

B

–

A (100 mA)

–

97

96

–

A (100 mA) 137

A (100 mA) 136

B

–

A (100 mA)

–

94

–

A (100 mA) 134

A

–

A (100 mA)

–

93

–

A (100 mA) 133

A

–

A (100 mA)

–

132

–

A (100 mA)

–

92

–

A (100 mA) 131

A

–

A (100 mA)

F

–

19

–

C

–

B (200 mA)

–

18

–

C

–

B (200 mA)

–

14

13

–

B (200 mA) 16

B (200 mA) 15

C

–

B (200 mA)

–

12 (2)

–

B (200 mA) 14 (2)

C

–

B (200 mA)

–

10

–

B (200 mA) 12

C

–

B (200 mA)

–

9

B (200 mA) 11

C

B (200 mA)

70

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 49. EPM7256B I/O Pin-Outs & I/O Standards (Part 4 of 8)

Lab

MC

100-Pin

TQFP

IOGND

Group for

100-Pin

TQFP

IOVCC

Group for

100-Pin

TQFP

144-Pin

TQFP

IOGND

Group for

144-Pin

TQFP

IOVCC

Group for

144-Pin

TQFP

I/O Bank

(200 mA)

G

97

–

C

–

C

–

C

–

C

D

–

D

–

D

–

D

–

D

–

1

98

–

99

27

–

C

–

C (200 mA)

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

–

26

–

C

–

C (200 mA)

–

20

19

–

C (200 mA) 25

C (200 mA) 23

C

–

C (200 mA)

B (200 mA)

–

17

–

B (200 mA) 22

C

–

B (200 mA)

–

16

–

B (200 mA) 21

C

–

B (200 mA)

–

15 (1)

37

–

B (200 mA) 20 (1)

C

–

B (200 mA)

H

D (58 mA)

–

36

–

D (58 mA)

54

–

D

–

D (58 mA)

–

53

–

D

–

D (58 mA)

35

–

D (58 mA)

–

49

48

–

D

–

C (200 mA)

–

C (200 mA)

–

47

–

D

–

C (200 mA)

–

33

–

C (200 mA) 46

D

–

C (200 mA)

–

32

C (200 mA) 45

D

C (200 mA)

Altera Corporation

71

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 49. EPM7256B I/O Pin-Outs & I/O Standards (Part 5 of 8)

Lab

MC

100-Pin

TQFP

IOGND

Group for

100-Pin

TQFP

IOVCC

Group for

100-Pin

TQFP

144-Pin

TQFP

IOGND

Group for

144-Pin

TQFP

IOVCC

Group for

144-Pin

TQFP

I/O Bank

(200 mA)

I

129

80

A

–

A

–

A

–

A

–

A

F

–

F

–

F

–

F

–

F

G (200 mA) 114

A

–

H (200 mA)

2

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

–

81

–

G (200 mA) 116

A

–

I (100 mA)

–

117

–

A

–

I (100 mA)

–

118

119

–

A

–

I (100 mA)

–

I (100 mA)

–

83

–

H (100 mA) 120

A

–

I (100 mA)

–

84

–

H (100 mA) 121

A

–

I (100 mA)

–

85

63

–

H (100 mA) 122

A

–

I (100 mA)

J

F (200 mA)

–

64

–

F (200 mA) 90

G

–

G (200 mA)

–

65

–

F (200 mA) 91

G

–

G (200 mA)

–

92

93

–

G

–

G (200 mA)

–

G (200 mA)

–

67

–

G (200 mA) 94

G

–

G (200 mA)

–

96

–

G

–

H (200 mA)

–

68

G (200 mA) 97

G

H (200 mA)

72

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 49. EPM7256B I/O Pin-Outs & I/O Standards (Part 6 of 8)

Lab

MC

100-Pin

TQFP

IOGND

Group for

100-Pin

TQFP

IOVCC

Group for

100-Pin

TQFP

144-Pin

TQFP

IOGND

Group for

144-Pin

TQFP

IOVCC

Group for

144-Pin

TQFP

I/O Bank

(200 mA)

K

161

–

E

–

E

–

F

–

F

–

F

–

D

–

D

–

E

–

E

–

2

1

2

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

–

57

–

F (200 mA) 82

F

–

G (200 mA)

–

83

–

F

–

G (200 mA)

–

58

–

F (200 mA) 84

F

G

–

G (200 mA)

–

86

–

G (200 mA)

–

60 (2)

–

F (200 mA) 87 (2)

G

–

G (200 mA)

–

61

–

F (200 mA) 88

G

–

G (200 mA)

–

62 (1)

–

F (200 mA) 89 (1)

G

–

G (100 mA)

L

–

55

–

D

–

D (58 mA)

–

56

–

D

–

D (58 mA)

–

40

41

–

E (100 mA) 60

E (100 mA) 61

E

–

E (100 mA)

–

42

–

E (100 mA) 62

E

–

E (100 mA)

–

44

–

E (100 mA) 63

E

–

E (100 mA)

–

45

E (100 mA) 65

F

E (100 mA)

Altera Corporation

73

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 49. EPM7256B I/O Pin-Outs & I/O Standards (Part 7 of 8)

Lab

MC

100-Pin

TQFP

IOGND

Group for

100-Pin

TQFP

IOVCC

Group for

100-Pin

TQFP

144-Pin

TQFP

IOGND

Group for

144-Pin

TQFP

IOVCC

Group for

144-Pin

TQFP

I/O Bank

(200 mA)

M

193

–

A

–

A

–

A

–

A

–

A

–

F

–

F

–

F

–

F

–

F

–

106

A

–

H (200 mA)

2

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

–

75

–

G (200 mA) 107

A

–

H (200 mA)

–

108

–

A

–

H (200 mA)

–

109

A

–

H (200 mA)

76

–

G (200 mA) 110

H (200 mA)

–

77

–

G (200 mA) 111

A

–

H (200 mA)

–

78

–

G (200 mA) 112

A

–

H (200 mA)

–

79

–

G (200 mA) 113

A

–

H (200 mA)

N

–

69

–

G (200 mA) 98

G

–

H (200 mA)

–

99

–

G

–

H (200 mA)

–

70

–

G (200 mA) 100

G

–

H (200 mA)

–

101

–

H (200 mA)

–

71

–

G (200 mA) 102

G

–

H (200 mA)

–

72

–

G (200 mA) 103

G

–

H (200 mA)

–

73 (1)

G (200 mA) 104 (1)

G

H (200 mA)

74

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 49. EPM7256B I/O Pin-Outs & I/O Standards (Part 8 of 8)

Lab

MC

100-Pin

TQFP

IOGND

Group for

100-Pin

TQFP

IOVCC

Group for

100-Pin

TQFP

144-Pin

TQFP

IOGND

Group for

144-Pin

TQFP

IOVCC

Group for

144-Pin

TQFP

I/O Bank

(200 mA)

P

225

–

E

–

E

–

E

–

E

–

E

–

E

–

E

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

2

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

74

–

F (200 mA)

–

75

–

F (200 mA)

–

52

53

–

F (200 mA) 77

F (200 mA) 78

G (200 mA)

–

54

–

F (200 mA) 79

G (200 mA)

–

55

–

F (200 mA) 80

G (200 mA)

–

56

46

–

F (200 mA) 81

E (100 mA) 66

G (200 mA)

Q

E (100 mA)

–

47

–

E (100 mA) 67

E (100 mA)

–

48

49

–

E (100 mA) 68

E (100 mA) 69

E (100 mA)

–

70

–

E (100 mA)

–

71

–

E (100 mA)

–

50

E (100 mA) 72

E (100 mA)

Altera Corporation

75

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Notes to tables:

(1) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for

in-system programming, this pin is not available as a user I/O pin.

(2) This pin may function as either a VREFpin or a user I/O pin. If this pin is programmed to be a VREFpin for using

the advanced I/O standards, then this pin is not available as a user I/O pin.

(3) The user I/O pin count includes dedicated input pins and all I/O pins.

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 1 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

A

1

153

B

–

C3

B

–

B (200 mA)

–

1

2

–

3

154

–

B

–

C4

–

B

–

B (200 mA)

–

4

5

159

160

–

B

–

E5

D5

–

B

–

B (200 mA)

–

6

7

8

161

162

–

B

–

C5

B4

–

B

–

B (200 mA)

–

9

10

11

12

13

14

15

16

163

–

B

–

A4

–

B

–

B (200 mA)

–

164

166

–

B

–

A5

D6

–

B

–

B (200 mA)

A (100 mA)

–

167

B

C6

B

A (100 mA)

76

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 2 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

B

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

141

C

–

F5

C

–

C (200 mA)

–

1

–

142

–

C

–

F2

–

C

–

C (200 mA)

–

144

145

–

C

–

E1

F4

–

C

–

B (200 mA)

–

146

147

–

C

–

F3

E2

–

C

–

B (200 mA)

–

148

–

C

–

D2

–

C

–

B (200 mA)

–

149

150

–

C

–

E3

E4

–

C

–

B (200 mA)

–

151

108

–

C

E

–

D4 (1)

N4

–

C

E

–

B (200 mA)

D (200 mA)

–

C

109

–

E

–

P3

–

E

–

D (200 mA)

–

110

111

–

E

–

N3

M4

–

E

–

D (200 mA)

–

112

113

–

E

–

M2

L4

–

E

–

D (200 mA)

–

114

–

E

–

L5

–

E

–

D (200 mA)

–

115

117

–

E

D

–

K6

K5

–

E

D

–

D (200 mA)

–

118

D

K4

D

D (200 mA)

Altera Corporation

77

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 3 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

D

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

92

–

F

–

N6

F

–

E (200 mA)

–

1

–

93

–

F

–

T5

–

F

–

E (200 mA)

–

95

96

–

E

–

M6

R5

–

E

–

E (200 mA)

–

97

98

–

E

–

M5

P5

–

E

–

E (200 mA)

–

99

–

E

–

N5

–

E

–

E (200 mA)

–

100

101

–

E

–

T4

R4

–

E

–

E (200 mA)

–

102

168

–

E

B

–

P4

B6

–

E

B

–

E (200 mA)

A (100 mA)

–

E

169

–

B

–

E6

–

B

–

A (100 mA)

–

170

171

–

B

–

F7

E7

–

B

–

A (100 mA)

–

172

173

–

B

–

D7

C7

–

B

–

A (100 mA)

–

175

–

A

–

B7

–

A

–

A (100 mA)

–

176 (1)

177

–

A

–

A7

F8

–

A

–

A (100 mA)

–

178

A

B8

A

A (100 mA)

78

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 4 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

F

81

130

D

–

H5

D

–

C (200 mA)

–

1

82

–

83

131

–

D

–

H1

–

D

–

C (200 mA)

–

84

85

132

133

–

D

–

H2

H3

–

D

–

C (200 mA)

–

86

87

88

135

136

–

C

–

H4

G6

–

C

–

C (200 mA)

–

89

90

91

137

–

C

–

G5

–

C

–

C (200 mA)

–

92

93

138

139

–

C

–

G2

G4

–

C

–

C (200 mA)

–

94

95

96

140

119

–

C

D

–

F1

K3

–

C

D

–

C (200 mA)

D (200 mA)

–

G

97

98

99

120

–

D

–

K2

–

D

–

D (200 mA)

–

100

101

102

103

104

105

106

107

108

109

110

111

112

121

122

–

D

–

J7

H7

–

D

–

D (200 mA)

–

123

124

–

D

–

J5

J2

–

D

–

D (200 mA)

–

126

–

D

–

J3

–

D

–

C (200 mA)

–

127 (1)

128 (2)

–

D

–

J4 (2)

H6

–

D

–

C (200 mA)

–

129

D

J6 (1)

D

C (200 mA)

Altera Corporation

79

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 5 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

H

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

79

–

F

–

F

–

F

–

F

–

F

–

F

–

F

A

–

A

–

A

–

A

–

A

–

A

–

A

M8

F

–

F

–

F

–

F

–

F

–

F

–

F

A

–

A

–

A

–

A

–

A

–

A

–

A

F (100 mA)

–

1

2

–

80

–

N8

–

F (100 mA)

–

81

84

–

L8

R7

–

F (100 mA)

–

86

87

–

P7

N7

–

E (200 mA)

–

88

–

M7

–

E (200 mA)

–

89

90

–

L7

T6

–

E (200 mA)

–

91

R6

C11

–

E (200 mA)

K (200 mA)

–

I

197

–

196

–

B11

–

K (200 mA)

–

195

194

–

A11

F10

–

K (200 mA)

–

193

192

–

E10

A10

–

K (200 mA)

–

190

–

C10

–

L (100 mA)

–

189 (1)

188

–

D10

F9

–

L (100 mA)

–

187

A9

L (100 mA)

80

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 6 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

J

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

27

–

I

J15

I

I (200 mA)

–

2

–

I

–

I

26

–

J16

–

I (200 mA)

–

I

–

I

25

24

–

J10

H14

–

I (200 mA)

–

I

–

I

–

I

22 (2)

21

–

H13

H12

–

J (200 mA)

–

I

–

I

–

I

20

–

H11 (2)

–

J (200 mA)

–

I

–

I

19

18

–

H10

G11

–

J (200 mA)

–

I

–

I

–

I

17

38

–

G14

K11

–

J (200 mA)

I (200 mA)

–

K

H

–

H

–

H

–

H

–

I

H

–

H

–

H

–

H

–

I

37

–

K12

–

I (200 mA)

–

36

35

–

K14

K13

–

I (200 mA)

–

34

33

–

K15

K16

–

I (200 mA)

–

31

–

J13

–

I (200 mA)

–

I

–

I

30 (1)

29

–

J14

J12

–

I (200 mA)

–

I

–

I

–

I

28

J11 (1)

I (200 mA)

Altera Corporation

81

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 7 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

L

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

78

–

F

–

F

–

F

–

G

–

G

–

G

–

G

J

R8

F

–

F

–

F

–

G

–

G

–

G

–

G

J

F (100 mA)

–

2

–

77

–

T9

–

F (100 mA)

–

76

73

–

R9

N9

–

F (100 mA)

G (100 mA)

–

71

70

–

M9

L9

G (100 mA)

–

69

–

R10

–

G (100 mA)

–

68

67

–

N10

M10

–

G (100 mA)

–

66

4

L10

B14

–

G (100 mA)

K (200 mA)

–

M

–

J

–

J

3

C13

–

K (200 mA)

–

J

–

J

206

205

–

B13

F12

–

K (200 mA)

–

J

–

J

–

J

204

203

–

E12

D12

–

K (200 mA)

–

J

–

J

–

J

202

–

C12

–

K (200 mA)

–

J

–

J

201

199

–

B12

E11

–

K (200 mA)

–

A

–

A

–

A

198

D11

K (200 mA)

82

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 8 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

N

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

16

–

I

G13

I

J (200 mA)

–

2

–

I

–

I

15

–

G12

–

J (200 mA)

–

J

–

J

13

12

–

F16

F15

–

J (200 mA)

–

J

–

J

–

J

11

10

–

F13

F14

–

J (200 mA)

–

J

–

J

–

J

9

E16

–

J (200 mA)

–

J

–

J

8

E14

E13

–

J (200 mA)

–

7

J

–

J

–

J

6

D13 (1)

R13

–

J (200 mA)

H (200 mA)

–

O

49

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

48

–

P13

–

H (200 mA)

–

47

46

–

N13

M14

–

H (200 mA)

–

45

44

–

M13

L13

–

H (200 mA)

–

43

–

L14

–

H (200 mA)

–

42

40

–

L12

L15

–

H (200 mA)

I (200 mA)

–

39

L16

I (200 mA)

Altera Corporation

83

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 9 of 9)

LAB

MC

208-Pin

PQFP

(4)

IOGND

group for

208-Pin PQFP

(200 mA)

256-Pin

FineLine

BGA

IOGND

group for

256-Pin

FineLineBGA

(200 mA)

IOVCC

group for

208 &

256-Pin

Packages

I/O

Bank

P

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

65

–

G

–

R11

G

–

G (100 mA)

–

2

–

64

–

G

–

P11

–

G

–

G (100 mA)

–

62

61

–

G

–

N11

M11

–

G

–

H (200 mA)

–

60

59

–

G

–

T12

R12

–

G

–

H (200 mA)

–

58

–

G

–

M12

–

G

–

H (200 mA)

–

57

56

–

G

–

P12

N12

–

G

–

H (200 mA)

–

55

G

T13

G

H (200 mA)

Notes to tables:

(1) This pin can function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for

in-system programming, this pin is not available as a user I/O pin.

(2) This pin may function as either a VREFpin or a user I/O pin. If this pin is programmed to be a VREFpin for using

the advanced I/O standards, this pin is not available as a user I/O pin.

(3) The user I/O pin count includes dedicated input pins and all I/O pins.

(4) EPM7512B devices in the 208-pin PQFP package support vertical migration from EPM7256E, EPM7256S, and

EPM7256B devices. EPM7512B devices contain additional I/O pins which are no connects on the EPM7256E,

EPM7256S, and EPM7256B devices. To support these additional I/O pins, EPM7512B devices have two additional

VCCIO1(pin 105), VCCIO2(pin 207) and GNDIO(pins 51 and 158) pins that are no-connect pins on the EPM7256E,

EPM7256S, and EPM7256B devices. To achieve vertical migration between the EPM7256B and EPM7512B devices,

the no-connect pin 105 may be tied to VCCIO1, pin 207 may be tied to VCCIO2, and pins 51 and 158 may be tied to

GNDIOon EPM7256B devices.

84

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 51. EPM7512B Dedicated Pin-Outs

Dedicated Pin

100-Pin

TQFP

144-Pin

TQFP

208-Pin

PQFP (1)

256-Pin

BGA

256-Pin

FineLine BGA

INPUT/GCLK1

87

89

88

90

4

125

127

126

128

4

184

L1

D9

INPUT/GCLRn

INPUT/OE1

INPUT/OE2/GCLK2

TDI(2)

182

183

181

176

127

30

K2

E8

K1

E9

K3

D8

D4

J6

A2

TMS(2)

15

62

73

12

60

20

B12

V12

Y2

TCK(2)

89

J11

D13

J4

TDO(2)

104

14

189

128

22

VREFA(2)

VREFB(2)

GNDINT

C12

V10

87

H11

38, 86

52, 57, 124,

129

75, 82, 180,

185

J20, K4, K18,

L2, L17

A8, C9, G9, K8,

P9

GNDIO

11, 26, 43, 59, 3, 13, 17, 33,

14, 32, 50, 51, A1, B2, B19,

A3, B10, C2,

74, 95

59, 64, 85, 105, 72, 94, 116,

B20, C3, C18, D14, F6, G10,

135

134, 152, 158, D4, D17, U4,

H8, J9, K7, L11,

U17, V3, V18, M3, P6, P10,

V19, W2, W19, R2, R3, T1, T15

Y1, Y20

174, 200

VCCINT (2.5 V)

39, 91

51, 58, 123,

130

74, 83, 179,

186

J1, J19, L4,

M19, M20

B9, C8, G8, K9,

P8

VCCIO1(1.8 V, 2.5 V,

3.3 V)

3, 18, 34

24, 50, 144

85, 105, 107,

125, 143, 165

C4, C17, D3,

B3, B5, G3, G7,

D5, D16, D18, J8, L3, L6, T2,

E4, E17

T3

VCCIO2(1.8 V, 2.5 V,

3.3 V)

51, 66, 82

73, 76, 95, 115 5, 23, 41, 63,

191, 207

T4, T17, U3,

C14, E15,

U5, U16, U18, F11,G15, H9,

V2, V4, V17

K10, M15, P14

No Connect (N.C.)

–

Total User I/O Pins (3) 84

120

176

212

Altera Corporation

85

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 1 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

A

1

2

3

4

5

6

7

8

9

94

–

134

A

–

A

–

A

–

B

–

B

–

A

–

A

–

A

–

A

–

B

–

B

–

B

–

A (100 mA) A (100 mA) 1

–

1

–

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

–

93

–

133

–

A (100 mA) A (100 mA)

–

92

–

132

–

A (100 mA) A (100 mA)

–

131

–

A (100 mA) A (100 mA)

B

–

138

–

A (100 mA) A (100 mA)

–

97

–

137

–

A (100 mA) A (100 mA)

–

96

–

136

–

A (100 mA) A (100 mA)

–

86

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 2 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

C

33

–

142

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

A (100 mA) A (100 mA) 1

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

–

1

–

100

–

141

–

A (100 mA) A (100 mA)

–

99

–

140

–

A (100 mA) A (100 mA)

–

98

–

139

–

A (100 mA) A (100 mA)

–

D

–

2

B (200 mA) B (200 mA)

–

1

B (200 mA) B (200 mA)

–

2

–

A (100 mA) A (100 mA)

–

1

143

A (100 mA) A (100 mA)

Altera Corporation

87

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 3 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

E

65

–

6

–

5

–

7

–

6

–

5

–

B

–

B

–

B

–

B

–

B

–

B

–

C

–

C

–

C

–

C

–

C

–

C

–

C

–

C

–

1

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

1

B (200 mA) B (200 mA)

–

B (200 mA) B (200 mA)

–

B (200 mA) B (200 mA)

–

4 (1)

–

4 (1)

–

B (200 mA) B (200 mA)

F

–

9

11

–

B (200 mA) B (200 mA)

–

8

10

–

B (200 mA) B (200 mA)

–

7

9

B (200 mA) B (200 mA)

–

8

B (200 mA) B (200 mA)

88

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 4 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

G

97

–

C

–

B

–

C

–

C

–

D

–

D

–

C

–

E

–

E

–

D

–

1

98

1

99

15

–

B (200 mA) B (200 mA)

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

–

12 (2)

–

14 (2)

–

B (200 mA) B (200 mA)

–

10

–

12

–

B (200 mA) B (200 mA)

–

H

14

–

19

–

B (200 mA) B (200 mA)

–

13

–

18

–

B (200 mA) B (200 mA)

–

16

B (200 mA) B (200 mA)

Altera Corporation

89

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 5 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

I

129

–

C

–

C

–

C

–

C

–

C

–

E

–

E

–

E

–

E

–

E

–

E

–

1

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

1

15 (1)

–

20 (1)

–

B (200 mA) B (200 mA)

–

J

–

20

–

26

–

C (200 mA) C (200 mA)

–

19

–

25

–

C (200 mA) C (200 mA)

–

23

–

B (200 mA) B (200 mA)

–

17

–

22

–

B (200 mA) B (200 mA)

–

16

21

B (200 mA) B (200 mA)

90

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 6 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

K

161

22

–

29

C

–

C

–

C

–

C

–

C

E

–

E

–

E

F

–

E

–

E

–

E

C (200 mA) C (200 mA) 1

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

–

1

–

21

–

28

–

C (200 mA) C (200 mA)

–

27

34

–

C (200 mA) C (200 mA)

L

–

25

–

32

–

C (200 mA) C (200 mA)

–

24

–

31

–

C (200 mA) C (200 mA)

–

23

30

C (200 mA) C (200 mA)

Altera Corporation

91

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 7 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

M

193

–

D

–

D

–

D

–

D

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

1

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

–

1

–

37

–

C (200 mA) C (200 mA)

–

27

–

36

–

C (200 mA) C (200 mA)

–

35

42

–

C (200 mA) C (200 mA)

N

30

–

29

–

41

–

C (200 mA) C (200 mA)

–

28

–

40

–

C (200 mA) C (200 mA)

–

39

–

C (200 mA) C (200 mA)

–

38

C (200 mA) C (200 mA)

92

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 8 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

O

225

–

47

–

D

–

D

–

D

–

D

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

F

C (200 mA) C (200 mA) 1

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

–

1

33

–

46

–

C (200 mA) C (200 mA)

–

45

–

C (200 mA) C (200 mA)

–

32

–

44

–

C (200 mA) C (200 mA)

–

31

36

–

43

54

–

C (200 mA) C (200 mA)

D (58 mA) D (58 mA)

P

–

35

–

53

–

D (58 mA) D (58 mA)

–

49

–

C (200 mA) C (200 mA)

–

48

C (200 mA) C (200 mA)

Altera Corporation

93

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 9 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

Q

257

–

55

–

D

–

D

–

D

–

D

–

E

–

F

–

F

–

G

–

G

–

G

–

H

–

D (100 mA) D (100 mA) 1

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

–

1

2

–

37

–

56

–

D (100 mA) D (100 mA)

–

40

–

60

–

E (100 mA) E (100 mA)

–

61

62

–

E (100 mA) E (100 mA)

R

41

–

42

–

63

–

E (100 mA) E (100 mA)

–

44

–

65

–

E (100 mA) E (100 mA)

–

94

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 10 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

S

289

–

66

–

E

–

E

–

E

–

E

–

E

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

E (100 mA) E (100 mA) 2

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

–

2

–

45

–

67

–

E (100 mA) E (100 mA)

–

68

–

E (100 mA) E (100 mA)

–

46

–

69

–

E (100 mA) E (100 mA)

–

70

–

E (100 mA) E (100 mA)

T

–

47

–

71

–

E (100 mA) E (100 mA)

–

48

–

72

–

E (100 mA) E (100 mA)

–

49

74

E (200 mA) F (200 mA)

Altera Corporation

95

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 11 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

U

321

50

–

75

E

–

E

–

E

–

E

–

E

–

H

–

H

–

H

–

H

–

H

–

E (200 mA) F (200 mA) 2

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

–

2

–

52

–

77

–

F (200 mA) G (200 mA) 2

–

2

53

54

–

78

79

–

F (200 mA) G (200 mA) 2

V

–

2

55

–

80

–

F (200 mA) G (200 mA) 2

–

2

–

56

–

81

–

F (200 mA) G (200 mA) 2

–

2

–

96

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 12 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

W

353

57

–

82

E

–

E

–

F

–

F

–

F

H

–

H

–

H

–

I

F (200 mA) G (200 mA) 2

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

–

2

–

83

F (200 mA) G (200 mA) 2

–

2

–

58

–

84

F (200 mA) G (200 mA) 2

–

2

–

86

F (200 mA) G (200 mA) 2

–

I

–

2

–

60 (2)

87 (2)

F (200 mA) G (200 mA) 2

–

I

–

2

61

88

F (200 mA) G (200 mA) 2

X

62 (1)

89 (1)

I

–

63

–

90

–

I

–

2

F (200 mA) G (200 mA) 2

Altera Corporation

97

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 13 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

Y

385

–

91

–

F

–

F

–

F

–

F

–

I

F (200 mA) G (200 mA) 2

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

–

I

–

2

–

64

–

92

–

F (200 mA) G (200 mA) 2

–

I

–

2

–

65

–

93

–

F (200 mA) G (200 mA) 2

Z

–

I

–

2

–

94

–

F (200 mA) G (200 mA) 2

–

I

–

2

–

67

–

96

–

G (200 mA) H (200 mA)

–

I

–

68

–

97

–

G (200 mA) H (200 mA)

–

98

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 14 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

AA

417

–

F

–

F

–

F

–

F

–

F

–

A

–

I

–

2

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

–

2

–

69

–

98

G (200 mA) H (200 mA)

–

I

–

70

–

99

G (200 mA) H (200 mA)

–

I

–

71

–

100

G (200 mA) H (200 mA)

–

I

–

101

G (200 mA) H (200 mA)

BB

–

I

–

72

–

102

G (200 mA) H (200 mA)

–

I

–

103

G (200 mA) H (200 mA)

–

I

–

73 (1)

–

104 (1)

–

G (200 mA) H (200 mA)

–

A

–

75

106

G (200 mA) H (200 mA)

Altera Corporation

99

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 15 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

CC

449

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

2

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

–

2

–

76

–

107

–

G (200 mA) H (200 mA)

–

77

–

108

–

G (200 mA) H (200 mA)

–

78

–

109

–

G (200 mA) H (200 mA)

DD

–

79

–

110

–

G (200 mA) H (200 mA)

–

80

–

111

–

G (200 mA) H (200 mA)

–

112

–

G (200 mA) H (200 mA)

–

100

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 52. EPM7512B I/O Pin-Outs & I/O Standards (Part 16 of 16)

LAB

MC

100-Pin

TQFP

144-Pin

TQFP

IOGND Group for

TQFP (200 mA)

IOVCC Group for

TQFP

I/O

Bank

100 Pin

144 Pin

100 Pin

144 Pin

EE

481

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

2

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

512

–

2

–

113

–

G (200 mA) H (200 mA)

–

81

–

114

–

G (200 mA) H (200 mA)

–

83

–

116

–

H (100 mA) I (100 mA)

–

117

–

H (100 mA) I (100 mA)

–

FF

–

118

–

H (100 mA) I (100 mA)

–

84

–

119

–

H (100 mA) I (100 mA)

–

120

–

H (100 mA) I (100 mA)

–

121

–

H (100 mA) I (100 mA)

–

85

122

H (100 mA) I (100 mA)

Altera Corporation

101

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 1 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

A

1

173

B

A (100 mA) H3

D7

B

–

B

–

A

–

A

–

A

–

A

C

–

C

–

C

–

C

–

B

–

B

–

B

–

A

–

A

–

A

–

A

C

–

C

–

C

–

C

–

B

–

B

B (200 mA) 1

2

–

A

–

A

–

A

–

A

B

–

B

–

B

–

B

–

1

3

–

4

–

5

–

H2

–

C7

–

B (200 mA) 1

6

–

1

7

–

8

–

9

175

A (100 mA) H1

B7

–

A (100 mA) 1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

–

1

176 (1)

A (100 mA) J4

A7

–

A (100 mA) 1

–

1

–

177

–

A (100 mA) J3

F8

–

A (100 mA) 1

–

1

178

169

–

A (100 mA) J2

A (100 mA) G4

B8

D6

–

A (100 mA) 1

B (200 mA) 1

B

–

1

–

170

–

A (100 mA) F1

C6

–

B (200 mA) 1

–

1

–

171

–

A (100 mA) G3

B6

–

B (200 mA) 1

–

1

172

–

A (100 mA) G2

A6

–

B (200 mA) 1

–

1

–

G1

–

F7

–

B (200 mA) 1

–

1

–

H4

E7

B (200 mA) 1

102

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 2 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

C

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

163

B

B (200 mA) F4

E4

C

–

C

–

C (200 mA) 1

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

B

–

1

–

164

–

B (200 mA) E3

C5

–

C

–

C

–

C (200 mA) 1

–

1

–

166

–

A (100 mA) E2

A5

–

C

–

C

–

B (200 mA) 1

–

1

167

–

A (100 mA) F3

D5

–

C

–

C

–

B (200 mA) 1

–

1

–

168

–

A (100 mA) E1

E5

–

C

–

C

–

B (200 mA) 1

–

1

–

F2

B3

–

E6

B2

–

C

D

–

C

D

–

B (200 mA) 1

D (200 mA) 1

D

–

1

–

C2

–

A2

–

D

–

D

–

D (200 mA) 1

–

1

–

159

–

B (200 mA) B1

B4

–

C

–

C

–

C (200 mA) 1

–

1

160

–

B (200 mA) C1

A4

–

C

–

C

–

C (200 mA) 1

–

1

–

161

–

B (200 mA) D2

C4

–

C

–

C

–

C (200 mA) 1

–

1

162

B (200 mA) D1

C3

C

C (200 mA) 1

Altera Corporation

103

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 3 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

E

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

–

B5

–

E3

E

–

E

–

E

–

E

–

E

–

E

–

E

F

–

F

–

F

–

F

–

F

–

F

–

E

–

E

–

E

–

E

–

E

–

E

–

E

F

–

F

–

F

–

F

–

F

–

F

–

E

D (200 mA) 1

–

C

–

C

–

C

–

C

–

C

D

–

D

–

D

–

D

–

D

–

1

153

–

B (200 mA) C5

C1

–

D (200 mA) 1

–

1

–

D6

–

B1

–

D (200 mA) 1

–

1

–

154

–

B (200 mA) A4

A1

–

D (200 mA) 1

–

1

155

–

B (200 mA) B4

D2

–

D (200 mA) 1

–

1

–

156

–

B (200 mA) A3

D3

–

D (200 mA) 1

–

1

157

147

–

B (200 mA) A2 (1)

D4 (1)

F2

–

D (200 mA) 1

F

B (200 mA) B7

–

1

148

–

B (200 mA) C7

F3

–

D (200 mA) 1

–

1

149

–

B (200 mA) A6

F1

–

D (200 mA) 1

–

1

–

D7

–

F4

–

D (200 mA) 1

–

1

150

–

B (200 mA) B6

E1

–

D (200 mA) 1

–

1

–

151

–

B (200 mA) A5

D1

–

D (200 mA) 1

–

1

–

C6

E2

D (200 mA) 1

104

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 4 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

G

97

–

C9

–

H6

G

–

G

–

E (200 mA) 1

98

–

1

99

141

–

D

–

C (200 mA) D9

G5

–

G

–

G

–

E (200 mA) 1

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

–

1

142

–

D

–

C (200 mA) A8

G4

–

G

–

G

–

E (200 mA) 1

–

1

–

144

–

D

–

B (200 mA) B8

G2

–

F

–

F

–

D (200 mA) 1

–

1

145

–

D

–

B (200 mA) C8

G1

–

F

–

F

–

D (200 mA) 1

–

1

–

146

–

D

–

B (200 mA) D8

G6

–

F

–

F

–

D (200 mA) 1

–

1

–

A7

F5

J1

–

F

H

–

F

H

–

D (200 mA) 1

E (200 mA) 1

H

135

–

D

–

C (200 mA) A11

–

1

136

–

D

–

C (200 mA) A10

H7

–

H

–

H

–

E (200 mA) 1

–

1

137

–

D

–

C (200 mA) B10

H5

–

H

–

H

–

E (200 mA) 1

–

1

–

D10

–

H2

–

H

–

H

–

E (200 mA) 1

–

1

138

–

D

–

C (200 mA) C10

H3

–

G

–

G

–

E (200 mA) 1

–

1

–

139

–

D

–

C (200 mA) A9

H1

–

G

–

G

–

E (200 mA) 1

–

1

140

D

C (200 mA) B9

H4

G

E (200 mA) 1

Altera Corporation

105

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 5 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

I

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

–

D12

–

K1

I

E (200 mA) 1

–

E

–

E

–

E

–

E

–

E

–

E

–

E

–

E

–

E

–

E

–

I

–

I

–

1

129

C (200 mA) C12 (2) J7

E (200 mA) 1

–

I

–

I

–

1

130 (1)

C (200 mA) B12 (1) J6 (1)

E (200 mA) 1

–

I

–

I

–

1

–

131

C (200 mA) A12

J5

–

E (200 mA) 1

–

I

–

I

–

1

–

D11

–

J4 (2)

–

E (200 mA) 1

–

I

–

I

–

1

–

132

C (200 mA) C11

J3

–

E (200 mA) 1

–

I

–

I

–

1

133

C (200 mA) B11

D (200 mA) C14

J2

L2

–

E (200 mA) 1

J

122

I

F (200 mA)

1

–

I

–

I

–

B14

–

L1

–

F (200 mA)

–

I

–

I

–

123

D (200 mA) A14

K6

–

F (200 mA)

–

I

–

I

–

124

D (200 mA) D13

K5

–

F (200 mA)

–

I

–

I

126

C (200 mA) C13

K4

–

E (200 mA) 1

–

I

–

I

–

1

–

127 (1)

–

C (200 mA) B13

K3

–

E (200 mA) 1

–

I

–

I

–

1

128 (2)

C (200 mA) A13

K2

E (200 mA) 1

106

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 6 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

K

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

115

F

D (200 mA) B16

N4

J

–

I

J

–

I

F (200 mA)

1

–

E

–

E

–

E

–

E

–

E

F

–

F

–

F

–

F

–

F

–

F

–

117

–

D (200 mA) C15

M2

–

F (200 mA)

–

I

–

I

–

118

–

D (200 mA) A17

M1

–

F (200 mA)

–

I

–

I

–

119

–

D (200 mA) B15

M4

–

F (200 mA)

–

I

–

I

–

D14

–

M5

–

F (200 mA)

–

I

–

I

–

120

–

D (200 mA) A16

L5

–

F (200 mA)

–

I

–

I

–

121

109

–

D (200 mA) A15

D (200 mA) A20

L4

R1

–

F (200 mA)

L

J

–

J

–

J

–

J

–

J

–

J

K

–

J

–

J

–

J

–

J

–

J

F (200 mA)

–

110

–

D (200 mA) A19

P2

–

F (200 mA)

–

111

–

D (200 mA) B17

N3

–

F (200 mA)

–

112

–

D (200 mA) A18

N2

–

F (200 mA)

–

113

–

D (200 mA) D15

P1

–

F (200 mA)

–

114

D (200 mA) C16

N1

F (200 mA)

Altera Corporation

107

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 7 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

M

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

101

F

F (200 mA) E18

P5

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

J

–

J

–

J

–

J

–

J

–

J

–

J

–

J

–

J

–

J

–

J

H (200 mA) 1

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

F

–

1

–

102

–

F (200 mA) D20

N5

–

H (200 mA) 1

–

1

–

103

–

F (200 mA) D19

T4

–

H (200 mA) 1

–

1

104

–

F (200 mA) C20

R4

–

H (200 mA) 1

–

1

–

106

–

E (200 mA) C19

P4

–

G (200 mA) 1

–

1

108

95

–

D (200 mA) B18

F (200 mA) G17

P3

R6

–

F (200 mA)

N

I (200 mA)

–

96

–

F (200 mA) F19

T6

–

I (200 mA)

–

97

–

F (200 mA) E20

N6

–

I (200 mA)

–

98

–

F (200 mA) F18

M6

–

I (200 mA)

–

99

–

F (200 mA) E19

R5

–

I (200 mA)

–

100

F (200 mA) F17

T5

H (200 mA) 1

108

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 8 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

O

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

252

253

254

255

256

88

–

G

F (200 mA) H19

R7

L

–

L

–

L

–

L

–

L

–

L

–

L

–

L

–

L

–

L

–

L

–

L

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

I (200 mA)

1

–

89

–

G

–

F (200 mA) H18

P7

–

I (200 mA)

–

90

–

G

–

F (200 mA) H17

T7

–

I (200 mA)

–

91

–

G

–

F (200 mA) G20

L8

–

I (200 mA)

–

92

–

G

–

F (200 mA) G19

N7

–

I (200 mA)

–

G18

–

M7

–

I (200 mA)

–

93

79

–

G

–

F (200 mA) F20

G (200 mA) K20

L7

M9

–

I (200 mA)

P

J (200 mA)

–

80

–

G

–

G (200 mA) K19

L9

–

J (200 mA)

–

81

–

G

–

G (200 mA) K17

R8

–

J (200 mA)

–

84

–

G

–

G (200 mA) J18

T8

–

J (200 mA)

–

86

–

G

–

F (200 mA) J17

N8

–

I (200 mA)

–

87

G

F (200 mA) H20

M8

I (200 mA)

Altera Corporation

109

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 9 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

Q

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

275

276

277

278

279

280

281

282

283

284

285

286

287

288

78

–

G

G (100 mA) L20

N9

L

K

–

J (100 mA)

1

–

77

–

G

–

G (100 mA) L19

T9

–

L

K

–

J (100 mA)

–

76

–

G

–

G (100 mA) L18

R9

–

L

K

–

J (100 mA)

–

73

–

G

–

H (100 mA) M18

L10

–

L

K

–

K (100 mA) 2

–

2

–

71

–

H

–

H (100 mA) M17

M10

–

M

–

L

K (100 mA) 2

–

2

70

69

–

H

–

H (100 mA) N20

H (100 mA) N19

N10

R10

–

M

–

L

K (100 mA) 2

R

L

–

2

68

–

H

–

H (100 mA) N18

T10

–

M

–

L

K (100 mA) 2

–

2

67

–

H

–

H (100 mA) N17

M11

–

N

–

M

–

K (100 mA) 2

–

2

–

66

–

H

–

H (100 mA) P20

N11

–

N

–

M

–

K (100 mA) 2

–

2

65

–

H

–

H (100 mA) P19

P11

–

N

–

M

–

K (100 mA) 2

–

2

–

P18

–

R11

–

N

–

M

–

K (100 mA) 2

–

2

64

H

H (100 mA) R20

T11

N

M

K (100 mA) 2

110

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 10 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

S

289

290

291

292

293

294

295

296

297

298

299

300

301

302

303

304

305

306

307

308

309

310

311

312

313

314

315

316

317

318

319

320

62

–

H

I (200 mA) P17

K11

N

–

M

–

L (200 mA)

2

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

H

–

I

–

61

–

I (200 mA) R19

M12

–

N

–

M

–

L (200 mA)

–

60

–

I (200 mA) T20

N12

–

N

–

M

–

L (200 mA)

–

59

–

I (200 mA) R18

T12

–

N

–

M

–

L (200 mA)

–

58

–

I (200 mA) T19

R12

–

N

–

M

–

L (200 mA)

–

57

56

–

I (200 mA) T18

I (200 mA) R17

T13

P12

–

N

–

M

–

L (200 mA)

T

L (200 mA)

–

55

–

I (200 mA) U20

T14

–

N

–

M

–

L (200 mA)

–

54

–

I (200 mA) U19

P13

–

N

–

M

–

L (200 mA)

–

53

–

I (200 mA) V20

R13

–

N

–

M

–

L (200 mA)

–

52

–

I (200 mA) W20

R14

–

N

–

M

–

M (200 mA) 2

–

2

49

I (200 mA) W18

R15

O

N

M (200 mA) 2

Altera Corporation

111

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 11 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

U

321

322

323

324

325

326

327

328

329

330

331

332

333

334

335

336

337

338

339

340

341

342

343

344

345

346

347

348

349

350

351

352

48

–

I

I (200 mA) Y19

P15

O

–

N

–

M (200 mA) 2

–

I

–

2

–

47

–

I (200 mA) Y18

N15

–

O

–

N

–

N (200 mA) 2

–

I

–

2

–

46

–

I (200 mA) W17

T16

–

O

–

N

–

N (200 mA) 2

–

I

–

2

45

–

I (200 mA) Y17

R16

–

O

–

N

–

N (200 mA) 2

–

I

–

2

–

44

–

I (200 mA) U15

P16

–

O

–

N

–

N (200 mA) 2

–

I

–

2

43

42

–

I (200 mA) V16

I (200 mA) W16

N14

N16

–

O

–

N

–

N (200 mA) 2

V

I

–

I

–

2

40

–

J (200 mA) V15

M14

–

O

–

N

–

O (200 mA) 2

–

I

–

2

39

–

J (200 mA) Y16

N13

–

O

–

N

–

O (200 mA) 2

–

I

–

2

–

38

–

J (200 mA) W15

M16

–

O

–

N

–

O (200 mA) 2

–

I

–

2

–

U14

–

M13

–

O

–

N

–

O (200 mA) 2

–

2

–

37

–

J (200 mA) Y15

L14

–

O

–

N

–

O (200 mA) 2

–

I

–

2

36

J (200 mA) V14

L15

O

N

O (200 mA) 2

112

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 12 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

W

353

354

355

356

357

358

359

360

361

362

363

364

365

366

367

368

369

370

371

372

373

374

375

376

377

378

379

380

381

382

383

384

35

–

I

J (200 mA) W14

L16

O

–

N

–

O (200 mA) 2

–

I

–

2

–

Y14

–

L13

–

O

–

N

–

O (200 mA) 2

–

2

34

–

J (200 mA) U13

L12

–

O

–

N

–

O (200 mA) 2

–

I

–

2

–

33

–

J (200 mA) V13

K12

–

O

–

N

–

O (200 mA) 2

–

J

–

J

–

J

–

J

–

J

–

J

–

J

–

J

–

2

31

–

J (200 mA) W13

K14

–

P

–

O

–

O (200 mA) 2

–

2

–

30 (1)

–

J (200 mA) Y13

K15

–

P

–

O

–

O (200 mA) 2

–

2

29

–

J (200 mA) U12

K16

P

–

O

–

O (200 mA) 2

X

–

V12 (1) J11 (1)

–

2

28

–

J (200 mA) W12

J12

–

P

–

O

–

O (200 mA) 2

–

2

27

–

J (200 mA) Y12

J13

–

P

–

O

–

O (200 mA) 2

–

2

–

26

–

J (200 mA) V11

J14

–

P

–

O

–

O (200 mA) 2

–

2

–

U11

–

J15

–

P

–

O

–

O (200 mA) 2

–

2

–

25

–

J (200 mA) W11

K13

–

P

–

O

–

O (200 mA) 2

–

2

24

J (200 mA) Y11

J16

P

O

O (200 mA) 2

Altera Corporation

113

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 13 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

Y

385

386

387

388

389

390

391

392

393

394

395

396

397

398

399

400

401

402

403

404

405

406

407

408

409

410

411

412

413

414

415

416

22 (2)

–

J

K (200 mA) Y10

H10

P

–

O

–

P (200 mA) 2

–

J

–

2

21

–

K (200 mA) W10

H11 (2)

P

–

O

–

P (200 mA) 2

–

J

–

2

20

–

K (200 mA) V10 (2) H12

P

–

O

–

P (200 mA) 2

–

J

–

2

–

U10

–

H15

–

P

–

O

–

P (200 mA) 2

–

2

19

–

K (200 mA) Y9

H16

–

P

–

O

–

P (200 mA) 2

–

J

–

2

–

18

–

K (200 mA) W9

H14

–

P

–

O

–

P (200 mA) 2

–

J

–

2

17

–

K (200 mA) V9

H13

G12

–

P

–

O

–

P (200 mA) 2

Z

–

J

–

U9

–

2

16

–

K (200 mA) Y8

G13

–

P

–

O

–

P (200 mA) 2

–

J

–

2

15

–

K (200 mA) W8

G14

–

P

–

O

–

P (200 mA) 2

–

K

–

K

–

K

–

2

–

13

–

K (200 mA) V8

G16

–

Q

–

P

–

Q (200 mA) 2

–

2

12

–

K (200 mA) U8

G11

–

Q

–

P

–

Q (200 mA) 2

–

2

–

11

–

K (200 mA) Y7

F12

–

Q

–

P

–

Q (200 mA) 2

–

2

–

W7

F13

Q

P

Q (200 mA) 2

114

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 14 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

AA 417

418

419

420

421

422

423

424

425

426

427

428

429

430

431

432

BB 433

434

435

436

437

438

439

440

441

442

443

444

445

446

447

448

10

–

9

–

8

–

7

–

6

–

4

–

3

–

2

–

1

–

K

K (200 mA) V7

F14

Q

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

P

–

Q

Q (200 mA) 2

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

K

–

2

K (200 mA) Y6

F15

–

Q

–

Q (200 mA) 2

–

2

K (200 mA) U7

F16

–

Q

–

Q (200 mA) 2

–

2

–

W6

–

E12

–

Q

–

Q (200 mA) 2

–

2

K (200 mA) Y5

E13

–

Q

–

Q (200 mA) 2

–

2

–

K (200 mA) V6

E14

–

Q

–

Q (200 mA) 2

–

2

W5

V5

–

E16

D16

–

Q

–

R (200 mA) 2

–

2

L (200 mA) U6

C16

–

Q

–

R (200 mA) 2

–

2

Y4

–

B16

–

Q

–

R (200 mA) 2

–

2

–

L (200 mA) W4

A16

–

Q

–

R (200 mA) 2

–

2

L (200 mA) Y3

D15

–

Q

–

R (200 mA) 2

–

2

–

L (200 mA) Y2 (1)

D13 (1)

–

Q

–

R (200 mA) 2

–

2

208

L (200 mA) W3

C15

R

R (200 mA) 2

Altera Corporation

115

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 15 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

CC 449

450

451

452

453

454

455

456

457

458

459

460

461

462

463

464

DD 465

466

467

468

469

470

471

472

473

474

475

476

477

478

479

480

–

W1

–

B15

R

–

R

–

R

–

R

–

R

–

R

–

R

–

S

–

S

–

S

–

S

Q

–

S (200 mA) 2

–

K

–

K

–

K

–

K

–

K

–

A

–

A

–

A

–

2

–

V1

–

A15

–

Q

–

S (200 mA) 2

–

2

–

206

–

M (200 mA) U2

B14

–

Q

–

S (200 mA) 2

–

2

205

–

M (200 mA) U1

A14

–

Q

–

S (200 mA) 2

–

2

–

204

–

M (200 mA) T3

B13

–

Q

–

S (200 mA) 2

–

2

203

202

–

M (200 mA) R4

M (200 mA) T2

A13

C13

–

Q

–

S (200 mA) 2

–

2

–

201

–

M (200 mA) R3

D12

–

Q

–

S (200 mA) 2

–

2

–

199

–

M (200 mA) T1

C12

–

R

–

S (200 mA) 2

–

2

198

–

M (200 mA) R2

B12

–

R

–

S (200 mA) 2

–

2

–

197

–

M (200 mA) P4

A12

–

R

–

S (200 mA) 2

–

2

–

R1

E11

R

S (200 mA) 2

116

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Table 53. EPM7512B I/O Pin-Outs & I/O Standards (Part 16 of 16)

LAB MC 208-Pin

IOGND

IOVCC

256-Pin 256-Pin IOGND Group for

BGA FineLine 256-Pin Packages Group for Bank

IOVCC

I/O

PQFP Group for Group for

(4)

208-Pin

PQFP

(200 mA)

208-Pin

PQFP

BGA

(200 mA)

BGA FBGA

256-Pin

Packages

EE 481

482

483

484

485

486

487

488

489

490

491

492

493

494

495

496

FF 497

498

499

500

501

502

503

504

505

506

507

508

509

510

511

512

196

A

M (200 mA) P3

D11

S

–

S

–

S

–

S

–

S

–

S

–

S

–

A

–

A

–

A

–

A

R

–

R

–

R

–

R

–

R

–

R

–

R

–

A

–

A

–

A

–

A

S (200 mA) 2

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

A

–

2

–

195

M (200 mA) P2

C11

–

S (200 mA) 2

–

2

–

194

M (200 mA) P1

A11

–

S (200 mA) 2

–

2

193

M (200 mA) N4

B11

–

T (200 mA)

–

N3

–

F10

–

T (200 mA)

–

N2

E10

D10

–

T (200 mA)

192

M (200 mA) N1

T (200 mA)

–

M4

–

C10

–

T (200 mA)

–

190

N (100 mA) M3

A10

–

U (100 mA) 2

–

2

189 (1)

N (100 mA) M2

J10

–

U (100 mA) 2

–

2

–

188

–

N (100 mA) M1

F9

–

U (100 mA) 2

–

2

187

N (100 mA) L3

A9

U (100 mA) 2

Altera Corporation

117

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Notes to tables:

(1) The EPM7512B device in the 208-pin PQFP package supports vertical migration from the EPM7256E, EPM7256S,

and EPM7256B devices. The EPM7512B device contains additional I/O pins which are no connects on the

EPM7256E, EPM7256S, and EPM7256B devices. To support these additional I/O pins, the EPM7512B device has two

additional VCCIO(pins 105 and 207) and GNDIO(pins 51 and 158) pins that are no-connect pins on the EPM7256E,

EPM7256S, and EPM7256B devices. To achieve vertical migration between the EPM7256B and EPM7512B devices,

the no-connect pins 105 and 207 may be tied to VCCIO, and pins 51 and 158 may be tied to GNDIOon the EPM7256B

devices. On the EPM7256E and EPM7256S devices, these no-connect pins must not be tied to VCCIOor GNDIO.

EPM7512B devices have identical pin-outs.

(2) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for

in-system programming, this pin is not available as a user I/O pin.

(3) The user I/O pin count includes dedicated input pins and all I/O pins.

Figures 20 through 27 show the package pin-out diagrams for

MAX 7000B devices.

Figure 20. 44-Pin PLCC/TQFP Package Pin-Out Diagram

Package outlines not drawn to scale.

Pin 34

Pin 1

6

5

4

3

2

1 44 43 42 41 40

7

39

38

37

36

35

34

33

32

31

30

29

I/O

I/O/TDI

I/O

I/O/TDI

I/O

8

I/O/TDO

I/O

I/O/TDO

9

I/O

10

11

12

13

14

15

16

17

I/O

GND

I/O

GND

I/O

VCC

I/O

VCC

I/O

EPM7032B

EPM7064B

EPM7032B

EPM7064B

I/O

I/O/TMS

I/O

I/O/TMS

I/O

I/O/TCK

I/O

I/O/TCK

I/O

VCC

I/O

GND

I/O

VCC

I/O

GND

I/O

18 19 20 21 22 23 24 25 26 27 28

Pin 12

Pin 23

44-Pin PLCC

44-Pin TQFP

118

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Figure 21. 48-Pin VTQFP Package Pin-Out Diagram

Package outlines not drawn to scale.

48 47 46 45 44 43 42 41 40 39 38 37

36

I/O

1

N/C

I/O/TDI

I/O

35

34

33

32

31

30

29

28

27

26

25

I/O/TDO

I/O

2

3

I/O

4

VCCIO2

I/O

GNDIO

I/O / VREFA

I/O

5

6

EPM7032B

EPM7064B

I/O

7

I/O/TCK

I/O / VREFB

GNDIO

I/O

I/O/TMS

I/O

8

9

VCCIO1

I/O

10

11

12

I/O

13 14 15 16 17 18 19 20 21 22 23 24

48-Pin VTQFP

Figure 22. 100-Pin TQFP Package Pin-Out Diagram

Package outline not drawn to scale.

Pin 1

Pin 76

EPM7064B

EPM7128B

EPM7256B

Pin 26

Pin 51

Altera Corporation

119

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 23. 100-Pin FineLine BGA Package Pin-Out Diagram

Package outline not drawn to scale.

A1 Ball

Pad Corner

Indicates

location of

Ball A1

A

B

C

D

E

F

G

H

EPM7064B

EPM7128B

EPM7256B

J

K

10

9

8

7

6

5

4

3

2

1

Figure 24. 144-Pin TQFP Package Pin-Out Diagram

Package outline not drawn to scale.

Indicates location

of Pin 1

Pin 1

Pin 109

EPM7128B

EPM7256B

EPM7512B

Pin 37

Pin 73

120

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Figure 25. 208-Pin PQFP Package Pin-Out Diagram

Package outline not drawn to scale.

Pin 1

Pin 157

EPM7256B

EPM7512B

Pin 53

Pin 105

Altera Corporation

121

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

Figure 26. 256-Pin BGA Package Pin-Out Diagram

Package outline not drawn to scale.

A1 Ball

Pad Corner

Indicates

Location of

Ball A1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

EPM7512B

U

V

W

X

Y

20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

122

Altera Corporation

Preliminary Information

MAX 7000B Programmable Logic Device Family Data Sheet

Figure 27. 256-Pin FineLine BGA Package Pin-Out Diagram

Package outline not drawn to scale.

A1 Ball

Pad Corner

A

Indicates

Location of

Ball A1

B

C

D

E

F

G

H

J

K

EPM7128B

EPM7256B

EPM7512B

L

M

N

P

R

T

16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Altera Corporation

123

MAX 7000B Programmable Logic Device Family Data Sheet

Preliminary Information

®

Altera, BitBlaster, ByteBlaster, ByteBlasterMV, EPM7032B, EPM7064B, EPM7128B, EPM7256B, EPM7512B,

FineLine BGA, Jam, MasterBlaster, MAX, MAX 7000, MAX 7000A, MAX 7000B, MAX 7000S, MAX+PLUS,

MAX+PLUS II, MultiVolt, Quartus, SameFrame, and Turbo Bit are trademarks and/or service marks of Altera

Corporation in the United States or other countries. Altera acknowledges the trademarks of other

organizations for their respective products or services mentioned in this document, specifically: Verilog is a

registered trademark of Cadence Design Systems, Inc. Altera products are protected under numerous U.S. and

foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of

its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no

responsibility or liability arising out of the application or use of any information, product,

101 Innovation Drive

San Jose, CA 95134

(408) 544-7000

http://www.altera.com

Applications Hotline:

(800) 800-EPLD

Customer Marketing:

(408) 894-7104

Literature Services:

(888) 3-ALTERA

or service described herein except as expressly agreed to in writing by Altera Corporation.

Altera customers are advised to obtain the latest version of device specifications before

relying on any published information and before placing orders for products or services.

lit_req@altera.com

124

Altera Corporation

Printed on Recycled Paper.


型号：	EPM7128BFC100
厂家：	ALTERA CORPORATION
描述：	EE PLD, 4ns, CMOS, PBGA100, FINE LINE, BGA-100
文件：	总125页 (文件大小：1051K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EPM7128BFC100 [ALTERA]

相关型号：

EPM7128BFC100-10

EPM7128BFC100-10N

EPM7128BFC100-4

EPM7128BFC100-7

EPM7128BFC256-10

EPM7128BFC256-10N

EPM7128BFC256-4

EPM7128BFC256-4N

EPM7128BFC256-7

EPM7128BFI100-4

EPM7128BFI100-4N

EPM7128BFI100-7