CS4804 [AMCC]
OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER; OC- 48 /的4xOC - 12 / 16xOC - 3 SONET / SDH成帧器和POS / ATM MAPPER
| 型号： | CS4804 |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER |
| 文件： | 总2页 (文件大小：42K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Part Number - S4804CBI41
Product Brief Version 2.0 - January 2002
PRODUCT BRIEF
RHINE
OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER
Features
• Provides a SONET/SDH STS-48/STM-16, 4 STS-12/STM-
4, or 16 STS-3/STM-1 line interfaces.
The S4804 is a highly-integrated VLSI device that provides
full-duplex mapping of packets or ATM cells to SONET/SDH
payloads. It provides support for both uni-directional and
bi-directional rings.
• STS-48/STM-16 data stream supports a single STS-48c/
AU-4-16c, or any valid combination of STS-12c/AU-4-4c
and/or STS-3c/AU-4 SONET/SDH payloads.
The S4804 provides full section, line, and path overhead
processing, and supports framing, scrambling/descrambling,
alarm signal insertion/detection, and bit-interleaved parity
(B1/B2/B3) processing.
• Each STS-12/STM-4 data stream supports a single STS-
12c/AU-4-4c or 4 STS-3c/AU-4 SONET/SDH payloads.
• Each STS-3/STM-1 data stream supports a single
STS-3c/AU-4 SONET/SDH payload.
The S4804 is SONET/SDH standards compliant with Bellcore
GR-253, ITU G.707, ITU-T 432.1, ANSI T1.105 -1995, and
IETF RFCs 1619/1661/1662/2615.
• Supports mixed STS-3 / STS-12 line rates
• Provides full-duplex mapping of ATM cells or packets in
each payload tributary.
A general purpose 8-bit or 16-bit microprocessor interface is
provided for control and monitoring. The interface supports
both IntelTM and MotorolaTM type microprocessors, and is
capable of operating in either an interrupt-driven or
polled-mode configuration. In addition, a standard 5 signal
IEEE 1149.1 JTAG Test Port is provided for Boundary Scan
test purposes.
• Supports termination of mixed ATM and POS tributaries.
• Terminates/generates SONET/SDH section, line, and path
layers with transport/section E1, E2, F1, and DCC over-
head interfaces in both transmit and receive directions.
• APS port to support protection-switching configurations
between two RHINE devices.
Applications
•
•
•
ATM switches
• 16-bit, bus interface at 155 MHz for STS-48/STM-16 mode,
or serial interfaces operating at 622/155 MHz for STS-12/3
(STM-4/1) modes on the line side.
Packet over SONET Routers and Switches
SONET/SDH Add Drop Multiplexers, Terminal
Multiplexers, and Digital Cross Connects
• 32-bit, parallel interface (FlexBus-3TM) operating at 100
MHz on the system side.
•
Test equipment
• .25 micron, 2.5V core, and 3.3V tolerant I/O.
• Packaged in a 624 Pin CBGA.
S4804CBI Block Diagram
TX_ERR[1:4]
TX_EOP[1:4]
TX_LBYTE[1:0]
TX_SYS_DAT[31:0]
TX
FIFO
x16
TX_ADR[4:0]
TX_SONETCLK_OUT_155_622
MICROPROCESSOR I/F
TOH INSERT
SPE/VC
TX
TX_CLK[1:4]
TX_SONETCLK_OUT_155
TX_PRTY[1:4]
TX_ENB[1:4]
FRAMER
TX ATM/HDLC x16
TX_DATA[15:0]
TX_SONETCLK_IN
TX_FRAME_IN
x16
PROC w/
GEN.
43
(X + 1)
SCRMBL
x16
TX_SOC/P[1:4]
TX_CLAV_PDA[1:4]
TX_CLK_OUT[1:4]
RX_SYS_DAT[31:0]
RX_ADR[4:0]
RX ATM/HDLC
PROC w/
POH
x16
MON.
43
TOH
MON.
RX
RX_DATA[15:0]
x16
(X + 1)
DeSCRMBL
x16
FRAMER
RX ATM/
HDLC
RX_SONETCLK[1:16]
RX_CLK[1:4]
RX_PRTY[1:4]
RX_ENB[1:4]
RX_SOC/P[1:4]
RX_CLAV_PDA[1:4]
RX_DV[1:4]
x16
Ptr
Intrp
Ptr
Proc
CNTRS
x16
RX_LOSEXT[1:16]
RX_REF_CLK_OUT
x16
x16
TOH EXTRACT
JTAG PORT
GPIO/LED REG
RX
FIFO
x16
RX_LBYTE[1:0]
RX_EOP[1:4]
RX_ERR[1:4]
RX_CLK_OUT[1:4}
Production Release Information - The information con-
tained in this document is about a product in its fully tested
and characterized phase. All features described herein are
supported. Contact AMCC for updates to this document and
the latest product status.
AMCC
S4804CBI41: RHINE
Product Brief Version 2.0 - January 2002
STS-48 POS/ATM SONET MAPPER
PRODUCT BRIEF
HDLC Processing
Overview and Applications
Sonet/SDH Processing
When configured for POS mode, the S4804’s HDLC proces-
sor(s) provides HDLC packet processing as defined by IETF
RFCs 1619, 1662 and 2615. In addition, the S4804 optionally
performs scrambling (X43+1).
The S4804 implements SONET/SDH processing and full-
duplex ATM/packet-mapping functions for STS-48/STM-16,
STS-12/STM-4, or STS-3/STM-1 data streams. It can support
either a single STS-48c/AU-4-16c or any valid combination of
STS-12c/AU-4-4c or STS-3c/AU-4 signals within an STS-48/
STM-16. The S4804 also supports 4 STS-12/STM-4 signals
(each containing a single STS-12c/AU-4-4c or 4 STS-3c/AU-
4), or 16 STS-3c/STM-1 signals each containing an STS-3c/
AU-4.
Direct Map Mode
Direct Map Mode allows to map any protocol directly into the
Sonet/SDH Synchronous Payload Envelope, by-passing the
ATM and HDLC processing circuitry.
Automatic Protection Switching
The S4804 provides APS input and output interfaces to
convey signals between two S4804 devices configured for
APS operation. This configuration supports both 1+1 and 1:1
configurations.
A TOH/SOH interface provides direct add/drop capability for
E1, E2, F1, and both Section and Line DCC channels. The
S4804 also includes a clear channel mode that enables the
direct transmission of system payload from the system inter-
face to the line-side interface.
Line-side Interface
On the transmit side, the S4804 generates section, line, and
path overhead. It performs framing pattern insertion (A1, A2),
scrambling, alarm-signal insertion, and generates section,
line, and path Bit Interleaved Parity (B1/B2/B3) for far-end
performance monitoring.
On the line side, the S4804 supports a 16-bit parallel
interface, operating at 155MHz for a single OC-48 optical
interface. It provides serial interfaces at either 622 MHz or
155 MHz for OC-12 and/or OC-3 optical interfaces. Mixed
OC-3 / OC-12 line rates are supported.
On the receive side, the S4804 processes section, line, and
path overhead. It performs framing (A1, A2), descrambling,
alarm detection, pointer processing, Bit Interleaved Parity
monitoring (B1/B2/B3), and error-count accumulation for
performance monitoring.
System Interface
The S4804 supports a 32-bit, 100-MHz system interface. For
ATM cell transfers, the S4804 supports Utopia Level 3
interface. For packet transfers, the S4804 supports
FlexBusTM interface. The S4804 also provides support for a
quad, 8-bit extension of the Utopia 3.
ATM Processing
When configured for ATM cell processing, the S4804’s trans-
mit ATM processor(s) will perform all necessary cell process-
ing as defined by ATM UNI3.1, ITU-T I.432.1, and I.432.2.
TYPICAL APPLICATIONS: S4804CBI - RHINE in ATM or POS System
Microprocessor
Single STS-48 / Quad STS-12/ 16xSTS-3
POS or ATM over SONET Application
Control
14
16
Addr
Control
Data
Reference
Clock
IP Router or ATM Switch
TX_SONETCLK_IN
SerTxD±
TX_CLK
Switching/
Routing
Logic
SONET
Line Side
Interface
P/S & S/P
TX_DATA[15:0]
Multi
Fiber Optic
TX_SYS_DAT[31:0]
RX_SYS_DAT[31:0]
AMCC
RHINE
S4804CBI
Channel
Link Layer
Device
SONET XCVR
with
Clk Recovery
Transceiver SerRxD±
RX_LOSEXT[1]
RX_SONETCLK[2]
RX_DATA[15:0]
RX_CLK
HP / Lucent
Either
Single OC-48
or
For OC-48 Mode:
AMCC 3055
Four OC-12
or
Sixteen OC-3
TOH Insertion
and Extraction
AMCC
200 Minuteman Road, Andover, MA 01810 Ph: (978) 623-0009 Fax: (978) 623-0024
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