PPC440EP-3UC400CZ_技术文档

Part Number 440EP

Revision 1.25 – December 18, 2006

Data Sheet

440EP

Power PC 440EP Embedded Processor

Features

®

• Up to four serial ports (16750 compatible UART).

• PowerPC 440 processor core operating up to

667MHz with 32KB I-cache and D-cache with

parity checking.

• Two USB ports. One USB 1.1 Host interface with

on-chip PHY. One USB 2.0 Device interface, with

dedicated DMA, configured as a 1.1 on-chip PHY

or a 2.0 UTMI.

• Selectable processor:bus clock ratios of N:1, N:2.

• Floating Point Unit with single- and double-

precision and single-cycle throughput.

• External peripheral bus (16-bit data) for up to six

devices with external mastering.

• Dual bridged Processor Local Buses (PLBs) with

64- and 128-bit widths.

• Two IIC interfaces (one with boot parameter read

capability).

• Double Data Rate (DDR) Synchronous DRAM

(SDRAM) interface operating up to 133MHz with

ECC.

• NAND Flash interface.

• SPI interface.

• DMA support for external peripherals, internal

UART and memory.

• General Purpose I/O (GPIO) interface.

• JTAG interface for board level testing.

• PCI V2.2 interface (3.3V only). Thirty-two bits at

up to 66MHz.

• Boot from PCI memory, NOR Flash on the

external peripheral bus, or NAND Flash on the

NAND Flash interface.

• Programmable interrupt controller supports

interrupts from a variety of sources.

• Available in RoHS compliant lead-free package.

• Available in thermally enhanced package.

• Programmable General Purpose Timers (GPT).

• Two Ethernet 10/100Mbps half- or full-duplex

interfaces. Operational modes supported are MII,

RMII, and SMII with packet reject.

Description

Designed specifically to address high-end embedded

applications, the PowerPC 440EP (PPC440EP)

provides a high-performance, low- power solution that

interfaces to a wide range of peripherals and

Technology: CMOS Cu-11, 0.13μm.

Package: 35mm, 456-ball standard and thermally

enhanced plastic ball grid array (E-PBGA and

TE-PBGA), with and without lead (RoHS compliant).

incorporates on-chip power management features.

Typical power (measured): Less than 3W at 533MHz,

2.5W at 400MHz.

This chip contains a high-performance RISC

processor, a floating point unit, DDR SDRAM

controller, PCI bus interface, control for external ROM

and peripherals, DMA with scatter-gather support,

Ethernet ports, serial ports, IIC interfaces, SPI

interface, USB ports, NAND Flash interface, and

general purpose I/O.

Supply voltages required: 3.3V, 2.5V, 1.5V.

AMCC Proprietary

1

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Contents

Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DDR SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DMA to PLB 64 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DMA to PLB 128 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Ports (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Peripheral Interface (SPI/SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

DDR1 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

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AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Figures

Data Sheet

Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. PPC440EP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. 35mm, 456-Ball E-PBGA and TE-PBGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 4. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 6. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 7. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 9. DDR SDRAM MemClkOut0 and Read Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Figure 10. DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 11. DDR SDRAM Read Cycle Timing—Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 12. DDR SDRAM Read Cycle Timing—Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 13. DDR SDRAM Read Cycle Timing—Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Tables

Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. DCR Address Map (4KB of Device Configuration Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 8. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 9. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 10. Typical DC Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 11. V Supply Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

DD

Table 12. DC Power Supply Current Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 13. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 14. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 15. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 16. I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 17. I/O Specifications—333MHz to 533MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 18. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 19. I/O Timing—DDR SDRAM T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

DS

Table 20. I/O Timing—DDR SDRAM T , T , and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

HA

SK SA

Table 21. I/O Timing—DDR SDRAM T and T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

SD

HD

Table 22. I/O Timing—DDR SDRAM T

and T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

DIN

SIN

Table 23. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

AMCC Proprietary

3

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Ordering and PVR Information

For information on the availability of the following parts, contact your local AMCC sales office.

Order Part Number

Revision

Level

Product Name

Package

PVR Value

JTAG ID

(see Notes:)

PPC440EP

Notes:

PPC440EP-3pbfffCx

35mm, 456 ball, PBGA

B

C

0x422218D3

0x422218D4

0x2A950049

1. p = Module Package type

B = standard (E-PBGA) and contains lead.

J = standard (E-PBGA) and is lead-free (RoHS compliant)

T = thermally enhanced (TE-PBGA) and contains lead

U = thermally enhanced (TE-PBGA) and is lead-free (RoHS compliant)

2. b = Chip revision level

B = Revision level B (2.0)

C = Revision level C (2.1)

3. fff = Processor frequency

333 = 333MHz

400 = 400MHz

533 = 533MHz

667 = 667MHz

4. C = Case temperature range:

-40°C to +100°C for 333MHz, 400MHz, and 533MHz parts in any package

-40°C to +85°C for 667MHz parts in the E-PBGA package

-40°C to +95°C for 667MHz parts in the TE-PBGA package.

5. x = Shipping package type

Z = tape-and-reel

Blank = tray

Each part number contains a revision code. This is the die mask revision number and is included in the part

number for identification purposes only.

The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain

information that uniquely identifies the part. Refer to the PPC440EP User’s Manual for details on accessing these

registers.

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AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Figure 1. Order Part Number Key

PPC440EP-3JC667CZ

Shipping Package

AMCC Part Number

Grade 3 Reliability

Package

Case Temperature Range

Processor Frequency

Revision Level

Note: The example P/N above is a standard, revision C, lead-free package, capable of running at

667MHz, and is shipped in tape-and-reel packaging.

AMCC Proprietary

5

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Block Diagram

Figure 2. PPC440EP Functional Block Diagram

10

Clock

Control

Reset

External

Power

Mgmt

Interrupts

66MHz max

- 32 bits

- 6 devices

66MHz max

- 30-bit addr

- 16-bit data

DCRs

Timers

MMU

UIC

PPC440

Processor Core

DCR Bus

FPU

External

NAND

Flash

Controller

PCI

Bridge

Trace

JTAG

Peripheral

Controller

32KB

I-Cache

32KB

D-Cache

Performance

Monitor

PLB

Bridge

PLB (PLB4—128 bits)

PLB (PLB3—64 bits)

GPT

OPB

DMA

Controller

DMA

OPB

Bridge

Controller

DDR SDRAM

Controller

On-chip Peripheral Bus (OPB 0)

OPB 1

USB 2.0

Device

USB 1.1

Host

Ethernet

10/100

x2

IIC

x2

UART

x4

SPI

GPIO

BSC

266MHz max

- 13-bit addr

- 32-bit data

MAL

1 MII

1.1PHY 1.1PHY

UTMI

ZMII

or

2 RMII

or

2 SMII

D+/D−

™

The PPC440EP is a system on a chip (SOC) using IBM CoreConnect Bus Architecture.

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AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Address Maps

Data Sheet

The PPC440EP incorporates two address maps. The first is a fixed processor System Memory Address Map. This

address map defines the possible contents of various address regions which the processor can access. The

second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software

running on the PPC440EP processor through the use of mtdcr and mfdcr instructions.

Table 1. System Memory Address Map (Sheet 1 of 2)

Function

Local Memory¹

Sub Function

Start Address

0 0000 0000

0 4000 0000

0 5000 0000

0 5000 0040

0 5000 0100

0 5000 0180

0 8000 0000

0 A000 0000

0 E000 0000

0 E800 0000

0 E801 0000

0 E880 0000

0 EC00 0000

0 EEC0 0000

0 EEC0 0008

0 EED0 0000

0 EED0 0004

0 EF40 0000

0 EF40 0040

End Address

0 3FFF FFFF

0 4FFF FFFF

0 5000 003F

0 5000 00FF

0 5000 017F

0 7FFF FFFF

0 9FFF FFFF

0 DFFF FFFF

0 E7FF FFFF

0 E800 FFFF

0 E87F FFFF

0 EBFF FFFF

0 EEBF FFFF

0 EEC0 0007

0 EECF FFFF

0 EED0 0003

0 EF3F FFFF

0 EF40 003F

0 EF4F FFFF

Size

DDR SDRAM

Reserved

1GB

OPB Arbiter for USB (OPB 1)

Reserved

64B

USB 2.0 Device Bus

USB 2.0 Device

Reserved

128B

EBC

512MB

1GB

PCI Memory

Reserved

PCI I/O

64KB

56MB

8B

Reserved

PCI I/O

Reserved

PCI

Configuration Registers

Reserved

PCI Interrupt Ack / Special Cycle

Reserved

4B

Local Configuration Registers

Reserved

64B

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 1. System Memory Address Map (Sheet 2 of 2)

Function

Sub Function

Start Address

0 EF50 0000

0 EF60 0000

0 EF60 0100

0 EF60 0300

0 EF60 0308

0 EF60 0400

0 EF60 0408

0 EF60 0500

0 EF60 0508

0 EF60 0600

0 EF60 0608

0 EF60 0700

0 EF60 0720

0 EF60 0800

0 EF60 0820

0 EF60 0900

0 EF60 0907

0 EF60 0A00

0 EF60 0A40

0 EF60 0B00

0 EF60 0B80

0 EF60 0C00

0 EF60 0C80

0 EF60 0D00

0 EF60 0D10

0 EF60 0E00

0 EF60 0F00

0 EF60 1000

0 EF60 1080

0 F000 0000

0 FFE0 0000

End Address

0 EF5F FFFF

0 EF60 00FF

0 EF60 02FF

0 EF60 0307

0 EF60 03FF

0 EF60 0407

0 EF60 04FF

0 EF60 0507

0 EF60 05FF

0 EF60 0607

0 EF60 06FF

0 EF60 071F

0 EF60 07FF

0 EF60 081F

0 EF60 08FF

0 EF60 0906

0 EF60 09FF

0 EF60 0A3F

0 EF60 0AFF

0 EF60 0B7F

0 EF60 0BFF

0 EF60 0C7F

0 EF60 0CFF

0 EF60 0D0F

0 EF60 0DFF

0 EF60 0EFF

0 EF60 0FFF

0 EF60 107F

0 EFFF FFFF

0 FFDF FFFF

0 FFFF FFFF

Size

256B

8B

Reserved

General Purpose Timer

Reserved

UART0

Reserved

UART1

8B

Reserved

UART2

8B

Reserved

UART3

8B

Reserved

IIC0

32B

6B

Reserved

IIC1

Internal Peripherals

Reserved

SPI

Reserved

OPB Arbiter (OPB 0)

Reserved

64B

128B

16B

GPIO0 Controller

Reserved

GPIO1 Controller

Reserved

Ethernet PHY ZMII

Reserved

Ethernet 0 Controller

Ethernet 1 Controller

USB 1.1 Host

Reserved

256B

128B

EBC

254MB

2MB

Boot space (EBC Bank 0 and PCI)

Notes:

1. DDR SDRAM can be located anywhere in the Local Memory area of the memory map.

2. EBC and PCI are relocatable, but this map reflects the suggested configuration.

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AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 2. DCR Address Map (4KB of Device Configuration Registers)

Function

Total DCR Address Space¹

Start Address

End Address

Size

1KW (4KB)¹

000

3FF

By function:

Reserved

000

00C

00E

010

012

014

016

018

020

030

040

070

080

090

0A0

0A8

0B0

0B8

0C0

0D0

0E0

100

140

180

200

210

300

340

00B

00D

00F

011

013

015

017

01F

02F

03F

06F

07F

08F

09F

0A7

0AF

0B7

0BF

0CF

0DF

0FF

13F

17F

1FF

20F

2FF

33F

3FF

12W

2W

Clocking Power On Reset (CPR)

System DCRs (SDR)

Memory Controller (SDRAM)

External Bus Controller (EBC)

Reserved

2W

PLB 128 Performance Monitor (PPM)

Reserved

2W

8W

PLB 128 to PLB 64 Bridge Out

PLB 64 to PLB 128 Bridge In

Reserved

16W

64W

16W

8W

PLB 64 Arbiter

PLB 128 Arbiter

PLB 64 to OPB Bridge Out

Reserved

OPB to PLB 64 Bridge In

Power Management

Reserved

8W

Interrupt Controller 0

Interrupt Controller 1

Reserved

16W

32W

64W

128W

16W

512W

64W

512W

DMA to PLB 64 Controller

Reserved

Ethernet MAL

PLB 128 to OPB Bridge

Reserved

DMA to PLB 128 Controller

Reserved

Notes:

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit

(word) register. One kiloword (1024W) equals 4KB (4096 B).

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440EP – PPC440EP Embedded Processor

Data Sheet

PowerPC 440 Processor Core

The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, iSCSI, routers,

switches, printers, set-top boxes, etc. It is the first processor core to implement the new Book E PowerPC

embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.

Features include:

• Up to 667MHz operation

• PowerPC Book E architecture

• 32KB I-cache, 32KB D-cache

– UTLB Word Wide parity on data and tag address parity with exception force

• Three logical regions in D-cache: locked, transient, normal

• D-cache full line flush capability

• 41-bit virtual address, 36-bit (64GB) physical address

• Superscalar, out-of-order execution

• 7-stage pipeline

• 3 execution pipelines

• Dynamic branch prediction

• Memory management unit

– 64-entry, full associative, unified TLB with optional parity

– Separate instruction and data micro-TLBs

– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian

• Debug facilities

– Multiple instruction and data range breakpoints

– Data value compare

– Single step, branch, and trap events

– Non-invasive real-time trace interface

• 24 DSP instructions

– Single cycle multiply and multiply-accumulate

– 32 x 32 integer multiply

– 16 x 16 -> 32-bit MAC

Floating Point Unit (FPU)

Features include:

• Five stages with 2 MFlops/MHz

• Hardware support for IEEE 754

• Single- and double-precision

• Single-cycle throughput on most instructions

• Thirty-two 64-bit floating point registers

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Internal Buses

Data Sheet

The PowerPC 440EP features five standard on-chip buses: two Processor Local Buses (PLBs), two On-Chip

Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth

cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI bridge connect

to the PLBs. The primary OPB hosts lower data rate peripherals. The secondary OPB is dedicated to USB 2.0 and

DMA. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between

the processor core and the other on-chip cores.

Features include:

• PLB 128 (PLB4)

– 128-bit implementation of the PLB architecture

– Separate and simultaneous read and write data paths

– 36-bit address

– Simultaneous control, address, and data phases

– Four levels of pipelining

– Byte-enable capability supporting unaligned transfers

– 32- and 64-byte burst transfers

– 133MHz, maximum 4.25GB/s (simultaneous read and write)

– Processor:bus clock ratios of N:1 and N:2

• PLB 64 (PLB3)

– 64-bit implementation of the PLB architecture

– 32-bit address

– 133MHz (1:1 ratio with PLB 128), maximum 1.1GB/s (no simultaneous read and write)

• OPB (2)

– 32-bit data path

– 32-bit address

– 66.66MHz

• DCR

– 32-bit data path

– 10-bit address

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440EP – PPC440EP Embedded Processor

Data Sheet

PCI Interface

The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is

designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices.

Reference Specifications:

• PowerPC CoreConnect Bus (PLB) Specification Version 3.1

• PCI Specification Version 2.2

• PCI Bus Power Management Interface Specification Version 1.1

Features include:

• PCI 2.2

– Frequency to 66MHz

– 32-bit bus

• PCI Host Bus Bridge or an Adapter Device's PCI interface

• Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an

external arbiter

• Support for Message Signaled Interrupts

• Simple message passing capability

• Asynchronous to the PLB

• PCI Power Management 1.1

• PCI register set addressable both from on-chip processor and PCI device sides

• Ability to boot from PCI bus memory

• Error tracking/status

• Supports initiation of transfer to the following address spaces:

– Single beat I/O reads and writes

– Single beat and burst memory reads and writes

– Single beat configuration reads and writes (type 0 and type 1)

– Single beat special cycles

DDR SDRAM Memory Controller

The Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. Up to four

256MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and

memory addressing modes are programmable.

Features include:

• Registered and non-registered industry standard discrete devices

• 32-bit memory interface with optional 8-bit ECC (SEC/DED)

• Sustainable 1.1GB/s peak bandwidth at 133MHz

• SSTL_2 logic

• 1 to 4 chip selects

• CAS latencies of 2, 2.5 and 3 supported

• DDR200/266 support

• Page mode accesses (up to eight open pages) with configurable paging policy

• Programmable address mapping and timing

• Hardware and software initiated self-refresh

• Power management (self-refresh, suspend, sleep)

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440EP – PPC440EP Embedded Processor

Data Sheet

External Peripheral Bus Controller (EBC)

Features include:

• Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported

• Up to 66.66MHz operation

• Burst and non-burst devices

• 16-bit byte-addressable data bus

• 30-bit address

• Peripheral Device pacing with external “Ready”

• Latch data on Ready, synchronous or asynchronous

• Programmable access timing per device

– 256 Wait States for non-burst

– 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses

– Programmable CSon, CSoff relative to address

– Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS

• Programmable address mapping

• External DMA Slave Support

• External master interface

– Write posting from external master

– Read prefetching on PLB for external master reads

– Bursting capable from external master

– Allows external master access to all non-EBC PLB slaves

– External master can control EBC slaves for own access and control

Ethernet Controller Interface

Ethernet support provided by the PPC440EP interfaces to the physical layer but the PHY is not included on the

chip:

• One to two 10/100 interfaces running in full- and half-duplex modes

– One full Media Independent Interface (MII) with 4-bit parallel data transfer

– Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer

– Two Serial Media Independent Interfaces (SMII)

– Packet reject support

DMA to PLB 64 Controller

This DMA controller provides a DMA interface between the OPB and the 64-bit PLB.

Features include:

• Supports the following transfers:

– Memory-to-memory transfers

– Buffered peripheral to memory transfers

– Buffered memory to peripheral transfers

• Four channels

• Scatter/Gather capability for programming multiple DMA operations

• 32-byte buffer

• 8-, 16-, 32-bit peripheral support (OPB and external)

• 32-bit addressing

• Address increment or decrement

• Supports internal and external peripherals

• Support for memory mapped peripherals

• Support for peripherals running on slower frequency buses

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440EP – PPC440EP Embedded Processor

Data Sheet

DMA to PLB 128 Controller

This DMA controller provides a DMA interface dedicated to the USB 2.0 device ports and the 128-bit PLB.

Features include:

• 4 independent channels supporting internal USB 2.0 Device endpoints 1 and 2

• Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers

• Scatter/gather capability

• 128-byte buffer with programmable thresholds

Serial Ports (UART)

Features include:

• Up to four ports in the following combinations:

– One 8-pin

– Two 4-pin

– One 4-pin and two 2-pin

– Four 2-pin

• Selectable internal or external serial clock to allow wide range of baud rates

• Register compatibility with NS16750 register set

• Complete status reporting capability

• Fully programmable serial-interface characteristics

• Supports DMA using internal DMA function on PLB 64

IIC Bus Interface

Features include:

• Two IIC interfaces provided

2

• Support for Philips® Semiconductors I C Specification, dated 1995

• Operation at 100kHz or 400kHz

• 8-bit data

• 10- or 7-bit address

• Slave transmitter and receiver

• Master transmitter and receiver

• Multiple bus masters

• Supports fixed V IIC interface

DD

• Two independent 4 x 1 byte data buffers

• Twelve memory-mapped, fully programmable configuration registers

• One programmable interrupt request signal

• Provides full management of all IIC bus protocols

• Programmable error recovery

• Includes an integrated boot-strap controller that is multiplexed with the second IIC interface

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440EP – PPC440EP Embedded Processor

Serial Peripheral Interface (SPI/SCP)

Data Sheet

The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous,

character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on

the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB.

Features include:

• Three-wire serial port interface

• Full-duplex synchronous operation

• SCP bus master

• OPB bus slave

• Programmable clock rate divider

• Clock inversion

• Reverse data

• Local data loop back for test

Universal Serial Bus (USB)

The USB interfaces provide both device and host support for version 1.1 and device support for version 2.0.

Support for the USB 2.0 Transceiver Macrocell Interface (UTMI) specification is included.

Features include:

• USB 1.1 Host port with internal PHY

• USB 2.0 Device UTMI or USB 1.1 Device PHY

• Device support provides 6 end points (3 in, 3 out)

• 1024B FIFO (double buffering of 512B packets)

• FIFOs are not shared between in and out endpoints

• Endpoints do not support high-bandwidth isochronous transfers

• Two USB 2.0 device end points have DMA dedicated channels (DMA to PLB 128)

NAND Flash Controller

The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND

Flash devices. It provides both direct command, address, and data access to the external device as well as a

memory-mapped linear region that generates data accesses. NAND Flash device data appears on the peripheral

data bus.

Features include:

• 1 to 4 banks supported on EBC

• Direct Interfacing to:

– Discrete NAND Flash devices (up to 4 devices)

– SmartMedia Card socket (22-pins)

• Device sizes 4MB-256MB supported

• (512 + 16)-B or (2K + 64)-B device page sizes supported

• Boot-from-NAND: Execute a linear sequence of boot code out of single page of first block (512B)

• Support DMA to allow direct, no-processor-intervention block copy from NAND Flash to SDRAM

• ECC provides single-bit error correction and double-bit error detection in each 256B of stored data

• Chip selects shared with EBC

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440EP – PPC440EP Embedded Processor

Data Sheet

General Purpose Timers (GPT)

Provides a separate time base counter and additional system timers in addition to those defined in the processor

core.

Features include:

• 32-bit Time Base Counter driven by the OPB bus clock

• Seven 32-bit compare timers

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master

accesses.

• 64 GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO

capabilities acts as a GPIO or is used for another purpose.

• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,

tri-stated if output bit is 1).

Universal Interrupt Controller (UIC)

Two Universal Interrupt Controllers (UIC) are employed. They provide control, status, and communications

necessary between the external and internal sources of interrupts and the on-chip PowerPC processor.

Note: Processor specific interrupts (for example, page faults) do not use UIC resources.

Features include:

• 10 external interrupts

• Edge triggered or level-sensitive

• Positive or negative active

• Non-critical or critical interrupt to the on-chip processor core

• Programmable interrupt priority ordering

• Programmable critical interrupt vector for faster vector processing

JTAG

Features include:

• IEEE 1149.1 Test Access Port

• IBM RISCWatch Debugger support

• JTAG Boundary Scan Description Language (BSDL)

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Package Diagram

Figure 3. 35mm, 456-Ball E-PBGA and TE-PBGA Packages

Top View

E-PBGA

TE-PBGA

®

PPC440EP

Part Number

30 TYP

PPC440EP

1YWWBZZZZZ

nprffft

1YWWBZZZZZ

Lot Number

PPC440EP-nprffft

Gold Gate Release

Corresponds to

A1 Ball Location

Lot Number (ZZZZZ)

Part Number

Heat slug

∅23.0 REF

Notes: 1. All dimensions are in mm.

2. Package is available in both lead-free and leaded versions.

3. The dimensions in this drawing are applicable to both the

standard E-PBGA and thermally enhanced TE-PBGA packages.

C

0.20

A

C

0.20

35.0

31.75

C

0.25

Bottom View

0.35

C

AF

AD

AB

Y

1.27 TYP

AE

AC

AA

W

U

Mold

Compound

V

Thermal Balls

T

R

P

35.0±0.2

N

PCB

Substrate

M

K

L

J

H

G

E

F

D

C

B

A

B

1

3

5

7

9 11 13 15 17 19 21 23 25

8 10

26

24

0.6±0.1

2.65 MAX

6

12 14

16 18

4

22

2

20

0.75 ± 0.15 SOLDERBALL x 456

s

B

∅ 0.30 C A

∅ 0.15

C

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440EP – PPC440EP Embedded Processor

Data Sheet

Signal Lists

The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the

signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate

signals in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each signal name

on the ball. The page number listed gives the page in “Signal Functional Description” on page 51 where the signals

in the indicated interface group begin. In cases where signals in the same interface group (for example, Ethernet)

have different names to distinguish variations in the mode of operation, the names are separated by a comma with

the primary mode name appearing first. These signals are listed only once, and appear alphabetically by the

primary mode name.

Table 3. Signals Listed Alphabetically (Sheet 1 of 24)

Signal Name

Ball

AE17

AD17

AF03

AF04

R04

Interface Group

Page

AGND

AV_DD

Power

59

BA0

DDR SDRAM

52

BA1

BankSel0

BankSel1

BankSel2

BankSel3

R02

DDR SDRAM

R01

N01

[BusReq][USB2TermSel]GPIO31

AA23

J02

External Master Peripheral

DDR SDRAM

55

52

CAS

ClkEn

AF05

AE05

AD07

J01

DDR SDRAM

DM0

DM1

DM2

DDR SDRAM

52

DM3

L03

DM8

AF07

D18

[DMAAck0][IRQ8]GPIO47

[DMAAck1][IRQ4]GPIO44

[DMAAck2][PerAddr06]GPIO01

[DMAAck3][PerAddr03]GPIO04

[DMAReq0][IRQ7]GPIO46

DMAReq1[IRQ5][ModeCtrl]

[DMAReq2][PerAddr07]GPIO00

[DMAReq3][PerAddr04]GPIO03

DQS0

G25

External Slave Peripheral

54

B06

C07

B24

AC12

C08

D08

AD09

AC08

K03

DQS1

DQS2

DDR SDRAM

System

52

DQS3

M04

AC06

Y25

DQS8

[DrvrInh1]USB2LS0[RejectPkt]

[DrvrInh2]Halt

58

C25

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440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 2 of 24)

Signal Name

Ball

P02

N02

Interface Group

Page

ECC0

ECC1

ECC2

M01

ECC3

M02

DDR SDRAM

52

ECC4

N03

ECC5

N04

ECC6

L02

ECC7

M03

[EMCCD, EMC1RxErr]GPIO25[NFRdyBusy]

[EMCCrS, EMC0CrsDV]GPIO22

[EMCDV, EMC1CrsDV]GPIO21[NFREn]

EMCMDClk

AC16

AD15

AF17

AE16

AC18

AF19

AD19

AE20

AD18

AC17

AD16

AC15

AD14

AF13

AF14

AC14

AF20

AF18

A19

EMCMDIO

EMCRxClk

[EMCRxD0, EMC0RxD0, EMC0RxD]GPIO12

[EMCRxD1, EMC0RxD1, EMC1RxD]GPIO13

[EMCRxD2, EMC1RxD0]GPIO14

[EMCRxD3, EMC1RxD1]GPIO15

[EMCRxErr, EMC0RxErr]GPIO20

EMCTxClk, EMCRefClk

[EMCTxD0, EMC0TxD0, EMC0TxD]GPIO16

[EMCTxD1, EMC0TxD1, EMC1TxD]GPIO17

[EMCTxD2, EMC1TxD0]GPIO18[NFCLE]

[EMCTxD3, EMC1TxD1]GPIO19[NFALE]

[EMCTxEn, EMC0TxEn, EMCSync]GPIO24

[EMCTxErr, EMC1TxEn]GPIO23[NFWEn]

[EOT0/TC0][IRQ9]GPIO48

[EOT1/TC1][IRQ6]GPIO45

[EOT2/TC2][PerAddr05]GPIO02

[EOT3/TC3][PerAddr02]GPIO05

[ExtAck][USB2XcvrSel]GPIO30

[ExtReq][USB2RxErr]GPIO27

ExtReset

Ethernet

53

H23

External Slave Peripheral

54

A05

B04

AA25

AD26

B23

External Master Peripheral

55

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440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 3 of 24)

Signal Name

Ball

A01

A02

Interface Group

Page

GND

A06

A09

A11

A16

A21

A26

B02

B25

B26

C03

C24

D04

D21

D23

E09

E14

E18

F01

F26

J05

J22

J26

L01

L04

L11

L13

L14

L16

L26

M12

M13

Power

59

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440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 4 of 24)

Signal Name

Ball

M15

M25

Interface Group

Page

GND

N05

N11

N13

N14

N15

N16

P11

P12

P13

P14

P16

P22

R12

R14

R15

T01

Power

59

T11

T13

T14

T16

T26

V05

V01

V22

AA01

AA26

AB09

AB13

AB18

AC01

AC04

AC07

AC23

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Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 5 of 24)

Signal Name

Ball

AD03

AD24

Interface Group

Page

GND

AE01

AE02

AE25

AF01

AF06

AF11

AF16

AF21

AF25

AF26

Power

59

22

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440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 6 of 24)

Signal Name

Ball

C08

B06

Interface Group

Page

GPIO00[PerAddr07][DMAReq2]

GPIO01[PerAddr06][DMAAck2]

GPIO02[PerAddr05][EOT2/TC2]

GPIO03[PerAddr04][DMAReq3]

GPIO04[PerAddr03][DMAAck3]

GPIO05[PerAddr02][EOT3/TC3]

GPIO06[PerCS1][NFCE1]

A05

D08

C07

B04

C06

GPIO07[PerCS2][NFCE2]

A04

GPIO08[PerCS3][NFCE3]

B07

GPIO09[PerCS4]

B10

GPIO10[PerCS5]

A10

GPIO11[PerErr]

E04

GPIO12[EMCRxD0, EMC0RxD0, EMC0RxD]

GPIO13[EMCRxD1, EMC0RxD1, EMC1RxD]

GPIO14[EMCRxD2, EMC1RxD0]

GPIO15[EMCRxD3, EMC1RxD1]

GPIO16[EMCTxD0, EMC0TxD0, EMC0TxD]

GPIO17[EMCTxD1, EMC0TxD1, EMC1TxD]

GPIO18[EMCTxD2, EMC1TxD0][NFCLE]

GPIO19[EMCTxD3, EMC1TxD1][NFALE]

GPIO20[EMCRxErr, EMC0RxErr]

GPIO21[EMCDV, EMC1CrsDV][NFREn]

GPIO22[EMCCrS, EMC0CrsDV]

GPIO23[EMCTxErr, EMC1TxEn][NFWEn]

GPIO24[EMCTxEn, EMC0TxEn, EMCSync]

GPIO25[EMCCD, EMC1RxErr][NFRdyBusy]

GPIO26[USB2RxDV]

AD19

AE20

AD18

AC17

AD14

AF13

AF14

AC14

AD16

AF17

AD15

AF18

AF20

AC16

AC26

AD26

Y24

System

58

GPIO27[USB2RxErr][ExtReq]

GPIO28[USB2TxVal]

GPIO29[USB2Susp][HoldAck]

GPIO30[USB2XcvrSel][ExtAck]

GPIO31[USB2TermSel][BusReq]

AB25

AA25

AA23

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Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 7 of 24)

Signal Name

Ball

Interface Group

Page

GPIO32[USB2OM0]

GPIO33[USB2OM1]

GPIO34[UART0_DCD/UART1_CTS/UART2_Tx]

GPIO35[UART0_DSR/UART1_RTS/UART2_Rx]

GPIO36[UART0_CTS/UART3_Rx]

GPIO37[UART0_RTS/UART3_Tx]

GPIO38[UART0_DTR/UART1_Tx]

GPIO39[UART0_RI/UART1_Rx]

GPIO40[IRQ0]

W24

AB26

R25

U26

V26

R26

N24

P24

D03

GPIO41[IRQ1]

G04

GPIO42[IRQ2]

F02

GPIO43[IRQ3]

G02

GPIO44[IRQ4][DMAAck1]

GPIO45[IRQ6][EOT1/TC1]

GPIO46[IRQ7][DMAReq0]

GPIO47[IRQ8][DMAAck0]

GPIO48[IRQ9][EOT0/TC0]

GPIO49[TrcBS0]

G25

H23

B24

D18

System

58

A19

AE21

AC25

AA24

Y03

GPIO50[TrcBS1]

GPIO51[TrcBS2]

GPIO52[TrcES0]

GPIO53[TrcES1]

AA04

AB03

AB04

AF22

AC22

AE24

AD04

AD06

AC09

AD12

AE15

C25

GPIO54[TrcES2]

GPIO55[TrcES3]

GPIO56[TrcES4]

GPIO57[TrcTS0]

GPIO58[TrcTS1]

GPIO59[TrcTS2]

GPIO60[TrcTS3]

GPIO61[TrcTS4]

GPIO62[TrcTS5]

GPIO63[TrcTS6]

Halt[DrvrInh2]

System

58

55

[HoldAck][USB2Susp]GPIO29

[HoldPri]USB2LS1[LeakTest]

[HoldReq]USB2RxAct[RcvrInh]

IIC0SClk

AB25

V24

External Master Peripheral

IIC0 Peripheral

Y23

U25

55

IIC0SData

T24

24

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440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 8 of 24)

Signal Name

Ball

U24

V25

Interface Group

Page

[IIC1SClk]SCPClkOut

[IIC1SData]SCPDI

[IRQ0]GPIO40

IIC1 Peripheral

55

D03

G04

F02

[IRQ1]GPIO41

[IRQ2]GPIO42

[IRQ3]GPIO43

G02

G25

AC12

H23

B24

[IRQ4]GPIO44[DMAAck1]

[IRQ5][ModeCtrl]DMAReq1

[IRQ6]GPIO45[EOT1/TC1]

[IRQ7]GPIO46[DMAReq0]

[IRQ8]GPIO47[DMAAck0]

[IRQ9]GPIO48[EOT0/TC0]

[LeakTest]USB2LS1[HoldPri]

MemAddr00

Interrupts

57

D18

A19

V24

System

58

P01

MemAddr01

P04

MemAddr02

T02

MemAddr03

T04

MemAddr04

U01

V02

MemAddr05

MemAddr06

U04

W03

Y02

DDR SDRAM

52

MemAddr07

MemAddr08

MemAddr09

AB02

R03

AD01

AD02

AF12

AE13

MemAddr10

MemAddr11

MemAddr12

MemClkOut0

DDR SDRAM

52

MemClkOut0

AMCC Proprietary

25

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 9 of 24)

Signal Name

Ball

Interface Group

Page

MemData00

AE12

MemData01

MemData02

MemData03

MemData04

MemData05

MemData06

MemData07

MemData08

MemData09

MemData10

MemData11

MemData12

MemData13

MemData14

MemData15

MemData16

MemData17

MemData18

MemData19

MemData20

MemData21

MemData22

MemData23

MemData24

MemData25

MemData26

MemData27

MemData28

MemData29

MemData30

MemData31

MemSelfRef

[ModeCtrl][IRQ5]DMAReq1

AD13

AC13

AE11

AF10

AE10

AC11

AF09

AE09

AD10

AF08

AE08

AC10

AE07

AD08

AD05

AE03

AC05

AF02

AC03

AC02

AA03

Y04

DDR SDRAM

52

AA02

V04

Y01

V03

W02

W01

U03

T03

U02

AE04

AC12

DDR SDRAM

System

52

58

26

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 10 of 24)

Signal Name

Ball

Interface Group

Page

[NFALE][EMCTxD3, EMC1TxD1]GPIO19

AC14

D06

C06

A04

B07

AF14

AC16

AF17

AF18

F06

F07

F08

F09

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

[NFCE0]PerCS0

[NFCE1][PerCS1]GPIO06

[NFCE2][PerCS2]GPIO07

[NFCE3][PerCS3]GPIO08

NAND Flash

57

[NFCLE][EMCTxD2, EMC1TxD0]GPIO18

[NFRdyBusy][EMCCD, EMC1RxErr]GPIO25

[NFREn][EMCDV, EMC1CrsDV]GPIO21

[NFWEn][EMCTxErr, EMC1TxEn]GPIO23

No ball

A physical ball does not exist at these ball

coordinates.

NA

AMCC Proprietary

27

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 11 of 24)

Signal Name

Ball

G16

G17

Interface Group

Page

No ball

G18

G19

G20

G21

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

J06

J07

J08

J09

J10

J11

J12

J13

J14

J15

J16

J17

J18

J19

A physical ball does not exist at these ball

coordinates.

NA

28

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 12 of 24)

Signal Name

Ball

Interface Group

Page

No ball

J20

J21

K06

K07

K08

K09

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

L06

L07

L08

L09

L10

L17

L18

L19

L20

L21

M06

M07

M08

M09

M10

M17

M18

A physical ball does not exist at these ball

coordinates.

NA

AMCC Proprietary

29

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 13 of 24)

Signal Name

Ball

Interface Group

Page

No ball

M19

M20

M21

N06

N07

N08

N09

N10

N17

N18

N19

N20

N21

P06

P07

P08

P09

P10

P17

P18

P19

P20

P21

R06

R07

R08

R09

R10

R17

R18

R19

R20

R21

T06

T07

T08

A physical ball does not exist at these ball

coordinates.

NA

30

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 14 of 24)

Signal Name

Ball

Interface Group

Page

No ball

T09

T10

T17

T18

T19

T20

T21

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

A physical ball does not exist at these ball

coordinates.

NA

AMCC Proprietary

31

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 15 of 24)

Signal Name

Ball

Interface Group

Page

No ball

V18

V19

V20

V21

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

A physical ball does not exist at these ball

coordinates.

NA

32

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 16 of 24)

Signal Name

Ball

Interface Group

Page

No ball

OV_DD

AA06

AA07

AA08

AA09

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

E06

A physical ball does not exist at these ball

coordinates.

NA

OV_DD

E07

E08

E13

E19

E20

E21

F05

F22

G05

G22

H05

H22

L12

L15

M11

M16

N22

Power

59

AMCC Proprietary

33

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 17 of 24)

Signal Name

Ball

Interface Group

Page

PCIAD00

PCIAD01

PCIAD02

PCIAD03

PCIAD04

PCIAD05

PCIAD06

PCIAD07

PCIAD08

PCIAD09

PCIAD10

PCIAD11

PCIAD12

PCIAD13

PCIAD14

PCIAD15

PCIAD16

PCIAD17

PCIAD18

PCIAD19

PCIAD20

PCIAD21

PCIAD22

PCIAD23

PCIAD24

PCIAD25

PCIAD26

PCIAD27

PCIAD28

PCIAD29

PCIAD30

PCIAD31

PCIC0/BE0

PCIC1/BE1

PCIC2/BE2

PCIC3/BE3

PCIClk

B16

C15

D15

A17

B17

A18

C16

D16

C18

A20

C20

B22

A23

A24

C22

D22

H24

F25

J24

PCI

51

K23

K24

J25

L23

K25

K26

M24

M23

L25

N23

N26

M26

P26

B18

F23

F24

E26

B21

D26

G24

PCI

51

PCI

51

PCIDevSel

PCIFrame

34

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 18 of 24)

Signal Name

Ball

Interface Group

Page

PCIGnt0/Req

PCIGnt1

PCIGnt2

PCIGnt3

PCIGnt4

PCIGnt5

PCIIDSel

PCIINT

D17

L24

A25

D25

H25

E24

G26

D20

E25

C23

D24

N25

B20

B19

C19

A22

H26

D19

J23

PCI

51

PCI

51

PCIIRDY

PCIPar

PCIPErr

PCIReq0/Gnt

PCIReq1

PCIReq2

PCIReq3

PCIReq4

PCIReq5

PCIReset

PCISErr

PCI

51

PCI

51

PCIStop

PCITRDY

E23

G23

AMCC Proprietary

35

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 19 of 24)

Signal Name

[PerAddr02]GPIO05[EOT3/TC3]

Ball

Interface Group

Page

B04

C07

D08

A05

B06

C08

D09

A07

C09

B08

D10

A08

B09

C10

C11

D12

C12

B11

B12

D13

A13

A12

A14

B13

C13

B14

A15

B15

C14

D14

D11

C02

D06

C06

A04

B07

B10

A10

[PerAddr03]GPIO04[DMAAck3]

[PerAddr04]GPIO03[DMAReq3]

[PerAddr05]GPIO02[EOT2/TC2]

[PerAddr06]GPIO01[DMAAck2]

[PerAddr07]GPIO00[DMAReq2]

PerAddr08

PerAddr09

PerAddr10

PerAddr11

PerAddr12

PerAddr13

PerAddr14

PerAddr15

PerAddr16

External Slave Peripheral

54

PerAddr17

PerAddr18

PerAddr19

PerAddr20

PerAddr21

PerAddr22

PerAddr23

PerAddr24

PerAddr25

PerAddr26

PerAddr27

PerAddr28

PerAddr29

PerAddr30

PerAddr31

PerBLast

External Slave Peripheral

External Master Peripheral

54

55

PerClk

PerCS0[NFCE0]

[PerCS1][NFCE1]GPIO06

[PerCS2][NFCE2]GPIO07

[PerCS3][NFCE3]GPIO08

[PerCS4]GPIO09

[PerCS5]GPIO10

External Slave Peripheral

54

36

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 20 of 24)

Signal Name

Ball

Interface Group

Page

PerData00

PerData01

PerData02

PerData03

PerData04

PerData05

PerData06

PerData07

PerData08

PerData09

PerData10

PerData11

PerData12

PerData13

PerData14

PerData15

[PerErr]GPIO11

PerOE

H01

K04

G01

J03

J04

H03

E01

G03

H04

E02

D01

F03

C01

F04

E03

B01

E04

B03

C05

D05

H02

C04

C26

K02

Y23

W23

Y25

AF15

AE14

U24

V25

T23

External Slave Peripheral

54

External Master Peripheral

External Slave Peripheral

54

PerReady

PerR/W

PerWBE0

PerWBE1

PSROOut

RAS

External Slave Peripheral

54

System

58

52

58

53

DDR SDRAM

System

[RcvrInh]USB2RxAct[HoldReq]

[RefEn]USB2TxRdy

[RejectPkt]USB2LS0[DrvrInh1]

SAGND

System

Ethernet

Power

59

SAV_DD

SCPClkOut[IIC1SClk]

SCPDI[IIC1SData]

SCPDO

Serial Peripheral (SPI)

57

AMCC Proprietary

37

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 21 of 24)

Signal Name

Ball

Interface Group

Page

SV_DD

SV_REF1

SV_REF2A

SV_REF2B

P05

R11

R16

T12

T15

W05

W22

Y05

Y22

Power

59

AA05

AA22

AB06

AB07

AB08

AB14

AB19

AB20

AB21

W04

P03

DDR SDRAM

52

AE06

AE19

AB01

AE18

B05

SysClk

System

JTAG

58

57

58

57

SysErr

SysReset

TCK

TDI

C17

JTAG

TDO

C21

JTAG

TestEn

A03

System

JTAG

TmrClk

AD11

D02

TMS

[TrcBS0]GPIO49

[TrcBS1]GPIO50

[TrcBS2]GPIO51

TrcClk

AE21

AC25

AA24

AC19

Trace

59

38

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 22 of 24)

Signal Name

Ball

Interface Group

Page

[TrcES0]GPIO52

[TrcES1]GPIO53

[TrcES2]GPIO54

[TrcES3]GPIO55

[TrcES4]GPIO56

[TrcTS0]GPIO57

[TrcTS1]GPIO58

[TrcTS2]GPIO59

[TrcTS3]GPIO60

[TrcTS4]GPIO61

[TrcTS5]GPIO62

[TrcTS6]GPIO63

TRST

Y03

AA04

AB03

AB04

AF22

AC22

AE24

AD04

AD06

AC09

AD12

AE15

D07

Trace

59

Trace

JTAG

59

57

[UART0_CTS/UART3_Rx]GPIO36

[UART0_RTS/UART3_Tx]GPIO37

UART0_Rx

V26

R26

T25

UART0_Tx

P25

[UART0_DCD/UART1_CTS/UART2_Tx]GPIO34

[UART0_DSR/UART1_RTS/UART2_Rx]GPIO35

[UART0_DTR/UART1_Tx]GPIO38

[UART0_RI/UART1_Rx]GPIO39

UARTSerClk

R25

UART Peripheral

55

U26

N24

P24

P23

AMCC Proprietary

39

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 23 of 24)

Signal Name

Ball

Interface Group

Page

USB1Clk

AD25

R23

USB1DevXcvr

USB1HostXcvr

USB2Clk

R24

W25

W26

AD22

AD21

AE23

AF24

AC21

AE26

AB23

AC24

AB24

AD20

AE22

AC20

AF23

AD23

V23

USB2DI0

USB2DI1

USB2DI2

USB2DI3

USB2DI4

USB2DI5

USB2DI6

USB2DI7

USB2DO0

USB2DO1

USB2DO2

USB2DO3

USB2DO4

USB2DO5

USB2DO6

USB2DO7

Universal Serial Bus

56

Y26

U23

USB2LS0[DrvrInh1][RejectPkt]

USB2LS1[LeakTest][HoldPri]

[USB2OM0]GPIO32

Y25

V24

W24

AB26

Y23

[USB2OM1]GPIO33

USB2RxAct[HoldReq][RcvrInh]

[USB2RxDV]GPIO26

AC26

AD26

AB25

AA23

W23

Y24

[USB2RxErr]GPIO27[ExtReq]

[USB2Susp]GPIO29[HoldAck]

[USB2TermSel]GPIO31[BusReq]

USB2TxRdy[RefEn]

[USB2TxVal]GPIO28

[USB2XcvrSel]GPIO30[ExtAck]

AA25

40

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 3. Signals Listed Alphabetically (Sheet 24 of 24)

Signal Name

Ball

Interface Group

Page

V_DD

WE

E05

E10

E11

E12

E15

E16

E17

E22

K05

K22

L05

L22

M05

M22

M14

N12

P15

R05

R13

R22

T05

Power

59

T22

U05

U22

AB05

AB10

AB11

AB12

AB15

AB16

AB17

AB22

K01

DDR SDRAM

52

AMCC Proprietary

41

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction

signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those pins, look

up the primary signal name in Table 3, Signals Listed Alphabetically.

Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)

Ball

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

Signal Name

Ball

B01

B02

B03

B04

B05

B06

B07

B08

B09

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

Signal Name

Ball

C01

C02

C03

C04

C05

C06

C07

C08

C09

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

Signal Name

PerData12

Ball

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

Signal Name

PerData10

GND

PerData15

GND

PerClk

TMS

TestEn

PerOE

GND

GPIO40*

GND

GPIO07*

GPIO02*

GND

GPIO05*

TCK

PerWBE1

PerReady

GPIO06*

GPIO04*

GPIO00*

PerAddr10

PerAddr15

PerAddr16

PerAddr18

PerAddr26*

PerAddr30

PCIAD01

PCIAD06

TDI

PerR/W

GPIO01*

GPIO08*

PerAddr11

PerAddr14

GPIO09*

PerAddr19

PerAddr20

PerAddr25*

PerAddr27*

PerAddr29*

PCIAD00

PCIAD04

PCIC0/BE0

PCIReq2

PCIReq1

PCIClk

PerCS0

PerAddr09

PerAddr13

GND

TRST

GPIO03*

PerAddr08

PerAddr12

PerBLast

PerAddr17

PerAddr21

PerAddr31

PCIAD02

PCIAD07

PCIGnt0/Req

GPIO47*

PCIReset

PCIINT

GPIO10*

GND

PerAddr23

PerAddr22

PerAddr24*

PerAddr28*

GND

PCIAD03

PCIAD05

GPIO48*

PCIAD09

GND

PCIAD08

PCIReq3

PCIAD10

TDO

GND

PCIReq4

PCIAD12

PCIAD13

PCIGnt2

GND

PCIAD11

ExtReset

GPIO46*

GND

PCIAD14

PCIPar

PCIAD15

GND

PCIPErr

PCIGnt3

PCIDevSel

Halt[DrvrInh2]

PSROOut

GND

42

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)

Ball

E01

E02

E03

E04

E05

Signal Name

Ball

F01

F02

F03

F04

F05

Signal Name

Ball

G01

G02

G03

G04

G05

Signal Name

PerData02

Ball

H01

H02

H03

H04

H05

Signal Name

PerData00

PerData06

GND

PerData09

PerData14

GPIO11*

V_DD

GPIO42*

PerData11

PerData13

OV_DD

GPIO43*

PerData07

GPIO41*

OV_DD

PerWBE0

PerData05

PerData08

OV_DD

E06

E07

E08

E09

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

F06

F07

F08

F09

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

No ball

OV_DD

G06

G07

G08

G09

G10

G11

G12

G13

G14

G15

G16

G17

G18

G19

G20

G21

No ball

OV_DD

H06

H07

H08

H09

H10

H11

H12

H13

H14

H15

H16

H17

H18

H19

H20

H21

No ball

OV_DD

GND

V_DD

OV_DD

GND

V_DD

GND

OV_DD

V_DD

E22

E23

E24

E25

E26

F22

F23

F24

F25

F26

G22

G23

G24

G25

G26

H22

H23

H24

H25

H26

PCIStop

PCIC1/BE1

PCIC2/BE2

PCIAD17

GND

PCITRDY

PCIFrame

GPIO44*

PCIIDSel

GPIO45*

PCIAD16

PCIGnt4

PCIReq5

PCIGnt5

PCIIRDY

PCIC3/BE3

AMCC Proprietary

43

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)

Ball

J01

J02

J03

J04

J05

J06

J07

J08

J09

J10

J11

Signal Name

Ball

K01

K02

K03

K04

K05

K06

K07

K08

K09

K10

K11

Signal Name

Ball

L01

L02

L03

L04

L05

L06

L07

L08

L09

L10

L11

Signal Name

GND

Ball

M01

M02

M03

M04

M05

M06

M07

M08

M09

M10

M11

Signal Name

ECC2

DM2

CAS

WE

RAS

ECC6

DM3

GND

V_DD

ECC3

ECC7

DQS3

V_DD

PerData03

PerData04

GND

DQS2

PerData01

V_DD

No ball

GND

No ball

OV_DD

J12

J13

J14

J15

No ball

K12

K13

K14

K15

No ball

L12

L13

L14

L15

M12

M13

M14

M15

GND

V_DD

GND

OV_DD

GND

OV_DD

J16

J17

J18

J19

J20

J21

J22

J23

J24

J25

J26

No ball

GND

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

No ball

V_DD

L16

L17

L18

L19

L20

L21

L22

L23

L24

L25

L26

GND

M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

No ball

V_DD

No ball

V_DD

PCISErr

PCIAD18

PCIAD21

GND

PCIAD19

PCIAD20

PCIAD23

PCIAD24

PCIAD22

PCIGnt1

PCIAD27

GND

PCIAD26

PCIAD25

GND

PCIAD30

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440EP – PPC440EP Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)

Ball

N01

N02

N03

N04

N05

N06

N07

N08

N09

N10

N11

Signal Name

Ball

P01

P02

P03

P04

P05

P06

P07

P08

P09

P10

P11

Signal Name

Ball

R01

R02

R03

R04

R05

R06

R07

R08

R09

R10

R11

Signal Name

BankSel2

Ball

T01

T02

T03

T04

T05

T06

T07

T08

T09

T10

T11

Signal Name

BankSel3

MemAddr00

GND

ECC1

ECC4

ECC5

GND

ECC0

BankSel1

MemAddr10

BankSel0

V_DD

MemAddr02

MemData30

MemAddr03

V_DD

SV_REF2A

MemAddr01

SV_DD

No ball

GND

No ball

GND

No ball

SV_DD

No ball

GND

V_DD

SV_DD

N12

N13

N14

N15

P12

P13

P14

P15

GND

R12

R13

R14

R15

GND

V_DD

T12

T13

T14

T15

GND

V_DD

GND

SV_DD

GND

SV_DD

N16

N17

N18

N19

N20

N21

N22

N23

N24

N25

N26

GND

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

GND

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

GND

No ball

OV_DD

No ball

V_DD

No ball

V_DD

No ball

GND

PCIAD28

GPIO38*

UARTSerClk

GPIO39*

UART0_Tx

PCIAD31

USB1DevXcvr

GPIO34*

SCPDO

IIC0SData

UART0_Rx

GND

PCIReq0/Gnt

PCIAD29

GPIO37*

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Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)

Ball

U01

U02

U03

U04

Signal Name

Ball

V01

V02

V03

V04

Signal Name

Ball

W01

W02

W03

W04

Signal Name

MemData28

Ball

Y01

Y02

Y03

Y04

Signal Name

MemData25

MemAddr04

GND

MemData31

MemData29

MemAddr06

V_DD

MemAddr05

MemData26

MemData24

MemData27

MemAddr07

SV_REF1

MemAddr08

GPIO52*

MemData22

SV_DD

U05

U06

U07

U08

U09

U10

U11

U12

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

V05

V06

V07

V08

V09

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

V23

V24

V25

V26

GND

W05

W06

W07

W08

W09

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

Y05

Y06

Y07

Y08

Y09

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

Y21

Y22

Y23

Y24

Y25

Y26

No ball

V_DD

No ball

GND

No ball

SV_DD

No ball

SV_DD

USB2DO7

SCPClkOut*

IIC0SClk

USB2DO5

USB2LS1*

SCPDI*

GPIO36*

USB2TxRdy*

GPIO32*

USB2RxAct*

GPIO28*

USB1HostXcvr

USB2LS0*

USB2DO6

GPIO35*

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

AA01 GND

AB01 SysErr

AC01 GND

AD01 MemAddr11

AD02 MemAddr12

AD03 GND

AA02 MemData23

AA03 MemData21

AA04 GPIO53*

AB02 MemAddr09

AB03 GPIO54*

AB04 GPIO55*

AC02 MemData20

AC03 MemData19

AC04 GND

AD04 GPIO59*

AD05 MemData15

SV_DD

V_DD

AA05

AB05

AB06

AB07

AB08

AC05 MemData17

SV_DD

AA06 No ball

AA07 No ball

AA08 No ball

AA09 No ball

AA10 No ball

AA11 No ball

AA12 No ball

AA13 No ball

AA14 No ball

AA15 No ball

AA16 No ball

AA17 No ball

AA18 No ball

AA19 No ball

AA20 No ball

AA21 No ball

AC06 DQS8

AD06 GPIO60*

AD07 DM1

AC07 GND

AC08 DQS1

AD08 MemData14

AD09 DQS0

AB09 GND

AC09 GPIO61*

AC10 MemData12

AC11 MemData06

AC12 IRQ5*

V_DD

AB10

AB11

AB12

AD10 MemData09

AD11 TmrClk

AD12 GPIO62*

AD13 MemData01

AD14 GPIO16*

AD15 GPIO22*

AD16 GPIO20*

AB13 GND

AC13 MemData02

AC14 GPIO19*

AC15 EMCTxClk*

AC16 GPIO25*

AC17 GPIO15*

AC18 EMCMDIO

AC19 TrcClk

SV_DD

V_DD

AB14

AB15

AB16

AB17

AV_DD

AD17

AB18 GND

AD18 GPIO14*

AD19 GPIO12*

AD20 USB2DO0

AD21 USB2DI0

SV_DD

V_DD

AB19

AB20

AB21

AB22

AC20 USB2DO2

AC21 USB2DI3

SV_DD

AA22

AC22 GPIO57*

AC23 GND

AD22 USB2Clk

AD23 USB2DO4

AD24 GND

AA23 GPIO31*

AA24 GPIO51*

AA25 GPIO30*

AA26 GND

AB23 USB2DI5

AB24 USB2DI7

AB25 GPIO29*

AB26 GPIO33*

AC24 USB2DI6

AC25 GPIO50*

AC26 GPIO26*

AD25 USB1Clk

AD26 GPIO27*

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Data Sheet

Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

Ball

Signal Name

AE01 GND

AE02 GND

AF01 GND

AF02 MemData18

AF03 BA0

AE03 MemData16

AE04 MemSelfRef

AE05 DM0

AF04 BA1

AF05 ClkEn

SV_REF2B

AE06

AF06 GND

AE07 MemData13

AE08 MemData11

AE09 MemData08

AE10 MemData05

AE11 MemData03

AE12 MemData00

AE13 MemClkOut0

AF07 DM8

AF08 MemData10

AF09 MemData07

AF10 MemData04

AF11 GND

AF12 MemClkOut0

AF13 GPIO17*

AF14 GPIO18*

AF15 SAGND

AF16 GND

SAV_DD

AE14

AE15 GPIO63*

AE16 EMCMDClk

AE17 AGND

AF17 GPIO21*

AF18 GPIO23*

AF19 EMCRxClk

AF20 GPIO24*

AF21 GND

AE18 SysReset

AE19 SysClk

AE20 GPIO13*

AE21 GPIO49*

AE22 USB2DO1

AE23 USB2DI1

AE24 GPIO58*

AE25 GND

AF22 GPIO56*

AF23 USB2DO3

AF24 USB2DI2

AF25 GND

AE26 USB2DI4

AF26 GND

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Signal Descriptions

Data Sheet

The PPC440EP embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA). The

following tables describe the package level pinout.

Table 5. Pin Summary

Group

Total Signal Pins

AV_DD

No. of Pins

304

1

SAV_DD

1

SAGnd

AGnd

OV_DD

1

18

SV_DD

V_DD

18

32

80

Gnd

Total Power Pins

Reserved

152

0

Total Pins

456

In the table “Signal Functional Description” on page 51, each I/O signal is listed along with a short description of its

function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed

Alphabetically” on page 18 for the pin (ball) number to which each signal is assigned.

Multiplexed Signals

Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,

the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same

pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in “Signals

Listed Alphabetically” on page 18. It is expected that in any single application a particular pin will always be

programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin

selection than would otherwise be possible. The circuit type for multiplexed signals is shown as “Multiplex.” The

actual circuit type is the same as the primary signal.

Multipurpose Signals

In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address

pins (PerAddr) are used as outputs by the PPC440EP to broadcast an address to external slave devices when the

PPC440EP has control of the external bus. When during the course of normal chip operation an external master

gains ownership of the external bus, these same pins are used as inputs which are driven by the external master

and received by the EBC in the PPC440EP. In this example, the pins are also bidirectional, serving both as inputs

and outputs.

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Multimode Signals

In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin

has multiple signal names assigned to distinguish different modes of operation, all of the names are shown.

Strapping Pins

One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only

during reset and are used for other functions during normal operation (see “Strapping” on page 82). Note that

these are not multiplexed pins since the function of the pins is not programmable.

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 6. Signal Functional Description (Sheet 1 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

PCI Interface

Description

I/O

Type

Notes

PCIAD00:31

PCIC0:3/BE0:3

PCIClk

Address/Data bus (bidirectional).

I/O

I

3.3V PCI

PCI Command/Byte Enables.

Provides timing to the PCI interface for PCI transactions.

Indicates the driving device has decoded its address as the

target of the current access.

PCIDevSel

PCIFrame

I/O

3.3V PCI

Driven by the current master to indicate beginning and

duration of an access.

Indicates that the specified agent is granted access to the bus.

When the internal arbiter is enabled, output is PCIGnt0. When

the internal arbiter is disabled, output is Req.

PCIGnt0/Req

PCIGnt1:5

O

3.3V PCI

Indicates that the specified agent is granted access to the bus.

Used only when internal PCI arbiter enabled.

Used as a chip select during configuration read and write

transactions.

PCIIDSel

PCIINT

I

3.3V PCI

Level sensitive PCI interrupt.

O

Indicates initiating agent’s ability to complete the current data

phase of the transaction.

PCIIRDY

PCIPar

I/O

Even parity.

Reports data parity errors during all PCI transactions except a

Special Cycle.

PCIPErr

Indicates to the PCI arbiter that the specified agent wishes to

use the bus. When the internal arbiter is enabled, input is

PCIReq0. When internal arbiter is disabled, input is Gnt.

PCIReq0/Gnt

I

3.3V PCI

An indication to the PCI arbiter that the specified agent wishes

to use the bus. Used only when internal PCI arbiter enabled.

PCIReq1:5

PCIReset

PCISErr

I

3.3V PCI

Brings PCI device registers and logic to a consistent state.

O

Reports address parity errors, data parity errors on the Special

Cycle command, or other catastrophic system errors.

I/O

Current target is requesting the master to stop the current

transaction.

PCIStop

I/O

3.3V PCI

Target agent’s ability to complete the current data phase of the

transaction.

PCITRDY

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440EP – PPC440EP Embedded Processor

Data Sheet

Table 6. Signal Functional Description (Sheet 2 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

DDR SDRAM Interface

BA0:1

Description

I/O

Type

Notes

Bank Address supporting up to four internal banks.

Selects up to four external DDR SDRAM banks.

Column Address Strobe.

O

2.5V SSTL_2

BankSel0:3

CAS

ClkEn

Clock Enable.

DM0:3

DM8

Memory write data byte lane masks. DM8 is the byte lane

mask for the ECC byte lane.

O

2.5V SSTL_2

DQS0:3

DQS8

Byte lane data strobe. DQS8 is the data strobe for the ECC

byte lane.

I/O

ECC0:7

ECC check bits 0:7.

Memory address bus.

I/O

O

2.5V SSTL_2

MemAddr00:12

MemClkOut0

2.5V SSTL_2

Diff driver

Subsystem clock.

Memory data bus.

Self refresh.

O

I/O

I

MemData00:31

MemSelfRef

2.5V SSTL_2

3.3V tolerant

2.5V CMOS

5

RAS

Row Address Strobe.

Write Enable.

O

I

2.5V SSTL_2

Volt ref receiver

WE

S_VREF1

SSTL reference voltage.

Volt ref pin

(supplemental)

S_VREF2A:B

Supplemental SSTL reference voltage.

I

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 6. Signal Functional Description (Sheet 3 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Ethernet Interface

Description

I/O

Type

Notes

MII: Collision detection.

RMII B: Receive error.

3.3V tolerant

2.5V CMOS

EMCCD, EMC1RxErr

EMCCrS, EMC0CrsDV

EMCDV, EMC1CrsDV

EMCMDClk

I/O

O

MII: Carrier sense.

RMII A: Carrier sense data valid.

3.3V tolerant

2.5V CMOS

MII: Data valid.

RMII B: Carrier sense data valid.

3.3V tolerant

2.5V CMOS

3.3V tolerant

2.5V CMOS

MII, RMII, and SMII: Management data clock.

MII, RMII, and SMII: Transfer command and status information

with PHY.

3.3V tolerant

2.5V CMOS

EMCMDIO

I/O

3.3V tolerant

2.5V CMOS

EMCRxClk

MII: Receive clock.

EMCRxD0:1,

EMC0RxD0:1

EMC0:1RxD

MII: Receive data.

RMII A: Receive data.

SMII A and B: Receive data.

3.3V tolerant

2.5V CMOS

I/O

EMCRxD2:3,

EMC1RxD0:1

MII: Receive data.

RMII B: Receive data.

3.3V tolerant

2.5V CMOS

I/O

I

EMCRxErr,

EMC0RxErr

MII: Receive error.

RMII A: Receive error.

3.3V tolerant

2.5V CMOS

EMCTxClk,

EMCRefClk

MII: Transmit clock.

RMII and SMII: Transmit clock (max 125MHz in SMII).

3.3V tolerant

2.5V CMOS

EMCTxD0:1,

EMC0TxD0:1

EMC0:1TxD

MII: Transmit data.

RMII A: Transmit data.

SMII A and B: Transmit data.

3.3V tolerant

2.5V CMOS

I/O

O

EMCTxD2:3,

EMC1TxD0:1

MII: Transmit data.

RMII B: Transmit data.

3.3V tolerant

2.5V CMOS

EMCTxEn,

EMC0TxEn,

EMCSync

MII: Transmit data enabled.

RMII A: Transmit data enabled.

SMII: Sync signal.

3.3V tolerant

2.5V CMOS

EMCTxErr,

EMC1TxEn

MII: Transmit error.

RMII B: Transmit data enabled.

3.3V tolerant

2.5V CMOS

I/O

I

3.3V tolerant

2.5V CMOS

RejectPkt

External request to reject a packet.

5

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 6. Signal Functional Description (Sheet 4 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

External Slave Peripheral Interface

Used by the PPC440EP to indicate that data transfers have

occurred.

DMAAck0:3

O

Multiplex

Used by slave peripherals to indicate they are prepared to

transfer data.

DMAReq0:3

I

Multiplex

1, 5

1, 3

1, 2

EOT0:3/TC0:3

PerAddr02:07

End Of Transfer/Terminal Count.

I/O

Peripheral address bus used by PPC440EP when not in

external master mode, otherwise used by external master.

3.3V LVTTL

Peripheral address bus used by PPC440EP when not in

external master mode, otherwise used by external master.

PerAddr08:31

I/O

3.3V LVTTL

Used by either the peripheral controller, DMA controller, or

external master to indicate the last transfer of a memory

access.

PerBLast

I/O

O

3.3V LVTTL

1, 4

2

PerCS0:5

External peripheral device select.

Peripheral data bus used by PPC440EP when not in external

master mode, otherwise used by external master.

PerData00:15

I/O

1

Note: PerData00 is the most significant bit (msb) on this bus.

Used by either peripheral controller or DMA controller

depending upon the type of transfer involved. When the

PPC440EP is the bus master, it enables the selected device to

drive the bus.

PerOE

O

I

3.3V LVTTL

2

Used by a peripheral slave to indicate it is ready to transfer

data.

PerReady

Used by the PPC440EP when not in external master mode, as

output by either the peripheral controller or DMA controller

depending upon the type of transfer involved. High indicates a

read from memory, low indicates a write to memory.

PerR/W

I/O

3.3V LVTTL

1, 2

Otherwise, it used by the external master as an input to

indicate the direction of transfer.

PerWBE0:1

PerErr

External peripheral data bus byte enables.

I/O

3.3V LVTTL

1, 2

1, 5

External Error. Used as an input to record external slave

peripheral errors.

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Table 6. Signal Functional Description (Sheet 5 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

External Master Peripheral Interface

Bus Request. Used when the PPC440EP needs to regain

control of peripheral interface from an external master.

BusReq

ExtAck

O

I

Multiplex

External Acknowledgement. Used by the PPC440EP to

indicate that a data transfer occurred.

External Request. Used by an external master to indicate it is

prepared to transfer data.

ExtReq

ExtReset

HoldAck

HoldReq

HoldPri

Multiplex

1, 4

Peripheral Reset. Used by an external master and by

synchronous peripheral slaves.

O

I

3.3V LVTTL

Multiplex

Hold Acknowledge. Used by the PPC440EP to transfer

ownership of peripheral bus to an external master.

Hold Request. Used by an external master to request

ownership of the peripheral bus.

Multiplex

1, 5

Hold Primary. Used by an external master to indicate the

priority of a given external master tenure.

I

Multiplex

Peripheral Clock. Used by an external master and by

synchronous peripheral slaves.

PerClk

O

3.3V LVTTL

UART Peripheral Interface

Serial clock input that provides an alternative to the internally

generated serial clock. Used in cases where the allowable

internally generated clock rates are not satisfactory.

UARTSerClk

I

3.3V LVTTL

1, 4

UARTn_Rx

UART Receive data.

I

O

I

3.3V LVTTL

1, 4

UARTn_Tx

UART Transmit data.

4

UARTn_DCD

UARTn_DSR

UARTn_CTS

UARTn_DTR

UARTn_RTS

UARTn_RI

UART Data Carrier Detect.

UART Data Set Ready.

UART Clear To Send.

UART Data Terminal Ready.

UART Request To Send.

UART Ring Indicator.

6

I

1, 4, 6

4

O

I

4

1, 4

IIC Peripheral Interface

IIC0SClk

IIC0 Serial Clock.

IIC0 Serial Data.

IIC1 Serial Clock.

IIC1 Serial Data.

I/O

3.3V LVTTL

Multiplex

1, 2

IIC0SData

IIC1SClk

IIC1SData

Multiplex

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440EP – PPC440EP Embedded Processor

Data Sheet

Table 6. Signal Functional Description (Sheet 6 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

USB/UTMI Peripheral Interface

3.3V tolerant

2.5V CMOS

USB2DI0:7

USB2DO0:7

USB2TxRdy

USB2RxAct

USB2RxDV

USB2RxErr

USB2LS0

Unidirectional data inputs.

I

O

I

5

3.3V tolerant

2.5V CMOS

Unidirectional data outputs.

Transmit data ready.

Receive active.

3.3V tolerant

2.5V CMOS

3.3V tolerant

2.5V CMOS

I

3.3V tolerant

2.5V CMOS

Receive data valid.

Receive error.

I

3.3V tolerant

2.5V CMOS

I

3.3V tolerant

2.5V CMOS

Line state 0.

I

2

3.3V tolerant

2.5V CMOS

USB2LS1

Line state 1.

I

3.3V tolerant

2.5V CMOS

USB2TxVal

USB2Susp

USB2XcvrSel

USB2TermSel

USB2OM0:1

Transmit valid.

O

I/O

3.3V tolerant

2.5V CMOS

Suspend.

3.3V tolerant

2.5V CMOS

Transceiver select.

Termination select.

Operational mode.

USB 1.1 Host differential transceiver.

3.3V tolerant

2.5V CMOS

3.3V tolerant

2.5V CMOS

5V tolerant

USB1HostXcvr

5

USB diff xcvr

5V tolerant

USB1DevXcvr

USB 1.1 Device differential transceiver.

I/O

I

USB diff xcvr

USB 2.0 Clock

3.3V tolerant

2.5V CMOS

USB2Clk

USB1Clk

Requires 60MHz signal for operation in 1.1 or 2.0 mode.

USB 1.1 Host Clock (48MHz)

3.3V tolerant

2.5V CMOS

I

Note: If not used for USB, must be connected to a clock signal

with a frequency between 32kHz and 48MHz.

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Data Sheet

Table 6. Signal Functional Description (Sheet 7 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

NAND Flash Interface

NFALE

Description

I/O

Type

Notes

Address Latch Enable.

O

Multiplex

NFCE0:3

Chip Enable (multiplexed with the PerCS0:3 signals).

Command Latch Enable.

NFCLE

Ready/Busy.

NFRdyBusy

I

Multiplex

Indicates status of device during program erase or page read.

This signal is wire-or connected from all NAND Flash devices.

NFREn

Read Enable strobe.

Write Enable strobe.

O

Multiplex

NFWEn

Serial Peripheral Interface

Clock output.

SCPClkOut, the serial port master clock out, is used to

synchronize all data movement both into and out of the device

through the serial data ports. Normally, data is shifted out on

the rising edge of the clock and shifted in on the negative

edge.

SCPClkOut

O

3.3V LVTTL

SCPClkOut is also used to shift data into and out of the slave

device. When the SPMODE register is reset, SCPClkOut is

forced to 0.

Data In.

SCPDI

I

3.3V LVTTL

Data is received from the connected slave device and is

captured synchronously with SysClk.

Data output.

SCPDO

O

Data is sent to the connected slave device synchronously with

SysClk.

Interrupts Interface

IRQ0:4

External interrupt requests 0 through 4.

External interrupt request 5.

I/O

I

3.3V LVTTL

1, 5

1

3.3V tolerant

2.5V CMOS

IRQ5

IRQ6:9

External interrupt requests 6 through 9.

I/O

3.3V LVTTL

1

JTAG Interface

3.3V LVTTL

w/pull-up

TCK

Test Clock.

I

1

4

3.3V LVTTL

w/pull-up

TDI

Test Data In.

I

O

I

TDO

TMS

Test Data Out.

Test Mode Select.

3.3V LVTTL

w/pull-up

1

5

3.3V LVTTL

w/pull-up

TRST

Test Reset.

I

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Data Sheet

Table 6. Signal Functional Description (Sheet 8 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

System Interface

Description

I/O

Type

Notes

3.3V tolerant

2.5V CMOS

SysClk

SysErr

Main system clock input.

Clock

O

3.3V tolerant

2.5V CMOS

Set to 1 when a machine check is generated.

Main system reset. External logic can drive this bidirectional

pin low (minimum of 16 cycles) to initiate a system reset. A

system reset can also be initiated by software. Implemented as

an open-drain output (two states; 0 or open circuit).

3.3V tolerant

2.5V CMOS

SysReset

I/O

1, 2

1, 4

Halt

Halt from external debugger.

I

3.3V LVTTL

3.3V tolerant

2.5V CMOS

TmrClk

Processor timer external input clock.

General purpose I/O 0 through 63. To access these functions,

software must set DCR register bits.

GPIO00:63

TestEn

I/O

Multiplex

3.3V LVTTL

Multiplex

Test Enable.

I

3

Receiver Inhibit. Active only when TestEn is active. Used for

manufacturing test only.

RcvrInh

Mode Control. Active only when TestEn is active. Used for

manufacturing test only.

ModeCtrl

LeakTest

RefEn

I

Multiplex

Leakage Test. Active only when TestEn is active. Used for

manufacturing test only.

Reference Enable. Active only when TestEn is active. Used for

manufacturing test only.

I

Driver Inhibit. Active only when TestEn is active. Used for

manufacturing test only.

3.3V tolerant

2.5V CMOS

DrvrInh1

DrvrInh2

PSROOut

I

Driver Inhibit. Active only when TestEn is active. Used for

manufacturing test only.

I

3.3V LVTTL

Module characterization and screening. Use for test purposes

only. Tie down as specified in Note 3 for normal operation.

Perf screen

ring osc

O

1, 3

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Data Sheet

Table 6. Signal Functional Description (Sheet 9 of 9)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3kΩ to 3.3V)

3. Must pull down (recommended value is 1kΩ)

4. If not used, must pull up (recommended value is 3kΩ to 3.3V)

5. If not used, must pull down (recommended value is 1kΩ)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Trace Interface

Description

I/O

Type

Notes

3.3V tolerant

2.5V CMOS

TrcBS0:2

TrcClk

Trace branch execution status.

I/O

O

Trace data capture clock, runs at 1/4 the frequency of the

processor.

3.3V tolerant

2.5V CMOSL

Trace Execution Status is presented every fourth processor

clock cycle.

3.3V tolerant

2.5V CMOS

TrcES0:4

TrcTS0:6

I/O

3.3V tolerant

2.5V CMOS

Additional information on trace execution and branch status.

Power

V_DD

1.5V supply—Logic voltage.

na

OV_DD

SV_DD

3.3V supply—I/O (except DDR SDRAM, Ethernet).

2.5V supply—SDRAM, Ethernet.

Ground.

GND

AV_DD

1.5V—Filtered voltage for system PLLs (analog).

PLL (analog) voltage ground.

AGND

SAV_DD

1.5V—Filtered voltage for memory PLL (analog).

PLL (analog) memory voltage ground.

SAGND

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Data Sheet

Device Characteristics

Table 7. Absolute Maximum Ratings

The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause

permanent damage to the device. None of the performance specification contained in this document are guaranteed when

operating at these maximum ratings.

Characteristic

Supply Voltage (Internal Logic)

Symbol

Value

Unit

V

Notes

V_DD

0 to +1.65

0 to +3.6

1

OV_DD

SV_DD

AV_DD

SAV_DD

V_IN

Supply Voltage (I/O, except SDRAM, Ethernet)

Supply Voltage (SDRAM, Ethernet)

PLL Supply Voltage

V

0 to +2.7

V

0 to +1.65

0 to +3.6

V

2

SDRAM PLL Supply Voltage

Input Voltage (3.3V LVTTL receivers)

Storage Temperature Range

Case temperature under bias

Notes:

V

T_STG

T_C

-55 to +150

-40 to +120

°C

3

1. If OV_DD≤ 0.4V, it is required that V_DD≤ 0.4V. Supply excursions not meeting this criteria must be limited to less than 25ms duration

during each power up or power down event.

2. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the

PPC440EP. A separate filter, as shown below, is recommended for each voltage:

AV_DD,SAV_DD

V_DD

L

L – SMT ferrite bead chip, Murata BLM21PG600SN1

C

C – 0.1μF ceramic

3. This value is not a specification of the operational temperature range, it is a stress rating only.

Table 8. Recommended DC Operating Conditions (Sheet 1 of 2)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Symbol

Minimum

+1.4

Typical

+1.5

Maximum

+1.6

Unit

V

Notes

V_DD

Logic Supply Voltage

I/O Supply Voltage

OV_DD

SV_DD

+3.0

+3.3

+3.6

V

SDRAM Supply Voltage

PLL Supply Voltages

+2.3

+2.5

+2.7

V

AV_DD

+1.4

+1.5

+1.6

V

3

2

SAV_DD

SV_REF

SDRAM PLL Voltage

+1.4

+1.5

+1.6

V

DDR SDRAM Reference Voltage

+1.15

+1.25

+1.35

V

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Data Sheet

Table 8. Recommended DC Operating Conditions (Sheet 2 of 2)

Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended

conditions can affect device reliability.

Parameter

Input Logic High (2.5V SSTL)

Symbol

Minimum

Typical

Maximum

Unit

V

Notes

SV_REF+0.18

SV_DD+0.3

Input Logic High (2.5V CMOS, 3.3V tolerant receiver)

Input Logic High (3.3V PCI)

1.7

V

V_IH

0.5OV_DD

OV_DD+0.5

V

1

Input Logic High (3.3V LVTTL)

+2.0

-0.3

+3.6

V

SV_REF-0.18

Input Logic Low (2.5V SSTL)

V

Input Logic Low (2.5V CMOS, 3.3V tolerant receiver)

Input Logic Low (3.3V PCI)

0.7

V

V_IL

V_OH

V_OL

0.35OV_DD

-0.5

0

V

1

Input Logic Low (3.3V LVTTL)

+0.8

V

SV_DD

Output Logic High (2.5V SSTL)

+1.95

2.0

V

SV_DD

OV_DD

Output Logic High (2.5V CMOS, 3.3V tolerant receiver)

Output Logic High (3.3V PCI)

V

0.9OV_DD

V

1

Output Logic High (3.3V LVTTL)

+2.4

0

V

Output Logic Low (2.5V SSTL)

0.55

0.4

Output Logic Low (2.5V CMOS, 3.3V tolerant receiver)

Output Logic Low (3.3V PCI)

0.1OV_DD

Output Logic Low (3.3V LVTTL)

0

+0.4

0

I_IL1

I_IL2

Input Leakage Current (No pull-up or pull-down)

μA

V

Input Leakage Current for Pull-Down

0 (LPDL)

-150 (LPDL)

200 (MPUL)

0 (MPUL)

+3.9

I_IL3

Input Leakage Current for Pull-Up

V_IMAO

V_IMAU

V_OMAO

V_OMAU3

Input Max Allowable Overshoot (3.3V LVTTL)

Input Max Allowable Undershoot (3.3V LVTTL)

Output Max Allowable Overshoot (3.3V LVTTL)

Output Max Allowable Undershoot (3.3V LVTTL)

-0.6

V

+3.9

V

Case Temperature:

333MHz, 400MHz, and 533MHz parts in any package

667MHz parts in the E-PBGA package

667MHz parts in the TE-PBGA package.

-40

+100

+85

+95

T_C

°C

Notes:

1. PCI drivers meet PCI specifications.

2. SV_REF= SV_DD/2

3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the

PPC440EP. See “Absolute Maximum Ratings” on page 60.

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Data Sheet

Power Sequencing

Startup sequencing of the power supply voltages is not required. However, a power-down cycle must complete

(OV and V are below +0.4V) before a new power-up cycle is started.

DD

Table 9. Input Capacitance

Parameter

Symbol

Maximum

2.5

Unit

pF

Notes

C_IN1

Group 1 (2.5V SSTL I/O)

Group 2 (3.3V LVTTL I/O)

Group 3 (PCI I/O)

C_IN2

C_IN3

C_IN4

C_IN5

C_IN6

2.1

2.5

Group 4 (Receivers)

0.9

Group 5 (3.3V tolerant CMOS I/O)

Group 6 (USB)

2.4

4.5

Table 10. Typical DC Power Supply Requirements

+1.5V Supply

(V_DD+AV_DD+SAV_DD

+2.5V Supply

+3.3V Supply

Frequency (MHz)

Total

Unit

Notes

)

(SV_DD

)

(OV_DD)

333

400

533

667

1.15

1.24

1.43

2.08

1.15

0.04

2.34

2.43

2.62

3.27

W

1

Notes:

1. Typical Power is based on nominal voltage of V_DD= +1.5V and T_C= max. specified in Table 8 on page 60, while running Linux and a test

application that exercises each core with representative traffic.

Table 11. V Supply Power Dissipation

DD

Frequency (MHz)

+1.4V

0.96

1.04

1.20

1.74

+1.5V

1.15

1.24

1.43

2.08

+1.6V

1.38

1.49

1.71

2.52

Unit

W

Notes

333

1

400

W

533

W

667

W

Notes:

1. Power is based on V_DDspecified in the table and T_C= max. specified in Table 8 on page 60, while running Linux and a test application

that exercises each core with representative traffic.

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Data Sheet

Table 12. DC Power Supply Current Loads

Parameter

Symbol

Typical

1380

10

Maximum

Unit

mA

Notes

V

_DD(1.5V) active operating current

I_DD

2200

100

600

5

OV_DD(3.3V) active operating current

SV_DD(2.5V) active operating current

AV_DD(1.5V) input current

I_ODD

I_SDD

460

I_ADD

3.2

1

SAV_DD(1.5V) active operating current

I_SADD

6.05

10

Notes:

1. See “Absolute Maximum Ratings” on page 60 for filter recommendations.

2. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors

including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature,

and the power supply voltages. Your specific application can produce significantly different results. V_DDcurrent and power are primarily

dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OV_DDcurrent and power

are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.

3. Typical current is estimated at 667MHz with V_DD= +1.5V, OV_DD= +3.3V, SV_DD= +2.5V, and T_C= +85°C, while running Linux and a test

application that exercises each core with representative traffic.

4. Maximum current is estimated at 667MHz with V_DD= +1.6V, OV_DD= +3.6V, SV_DD= +2.7V, T_C= +85°C, and a best-case process (which

drives worst-case power), while running Linux and a test application that exercises each core with representative traffic.

Table 13. Package Thermal Specifications

Thermal resistance values for the E-PBGA and TE-PBGA package are as follows:

Airflow

ft/min (m/sec)

Parameter

Symbol

Package

Unit

Notes

0 (0)

20.0

15.6

15.3

13.9

100 (0.51)

200 (1.02)

17.9

E-PBGA

TE-PBGA

E-PBGA

18.7

°C/W

Junction-to-ambient thermal resistance

without heat sink

θ_JA

13.6

12.8

11.9

10.5

Junction-to-ambient thermal resistance

with heat sink

TE-PBGA

10.4

9.0

Resistance Value

E-PBGA

TE-PBGA

E-PBGA

8.3

6.3

°C/W

Junction-to-case thermal resistance

θ_JC

θ_JB

14.3

9.3

Junction-to-board thermal resistance

TE-PBGA

Notes:

1. Case temperature, T_C, is measured at top center of case surface with device soldered to circuit board.

2. T_A= T_C- P×θ_CA, where T_Ais ambient temperature and P is power consumption.

3. T_CMax= T_JMax- P×θ_JC, where T_JMaxis maximum junction temperature (+125°C) and P is power consumption.

4. The preceding equations assume that the chip is mounted on a board with at least one signal and two power planes.

5. Values in the table were achieved with a JEDEC standard board: 114.5mm x 101.6mm x 1.6mm, 4 layers.

6. Values for an attached heat sink were achieved with a 35mm x 35mm x 15mm unit (see Thermal Management below), attached with a

0.1mm thickness of adhesive having a thermal conductivity of 1.3W/mK.

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440EP – PPC440EP Embedded Processor

Data Sheet

Thermal Management

The following heat sinks were used in the above thermal analysis:

ALPHA W35-15W (35mm x 35mm x15mm)

ALPHA LPD35-15B (35mm x 35mm x15mm)

The heat sinks are manufactured by:

Alpha Novatech, Inc. (www.alphanovatech.com)

473 Sapena Court, #12

Santa Clara, CA 95054

Phone: 408-567-8082

Test Conditions

Output

Clock timing and switching characteristics are specified in accordance with operating

conditions shown in the table “Recommended DC Operating Conditions.” AC

50pF

specifications are characterized with V = 1.5V, T = +125°C and a 50pF test load as

DD

J

shown in the figure to the right.

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Data Sheet

Table 14. Clocking Specifications

Symbol

SysClk Input

F_C

Parameter

Min

Max

Units

Frequency

Period

33.33

66.66

30

MHz

ns

T_C

15

T_CS

T_CH

T_CL

Edge stability (cycle-to-cycle jitter)

–

±0.15

ns

High time

Low time

40% of nominal period

60% of nominal period

ns

Note: Input slew rate ≥ 1V/ns

MemClkOut and PLB Clock

F_C

T_C

Frequency

Period

100

7.5

133.33

10

MHz

ns

T_CH

High time

45% of nominal period

55% of nominal period

ns

PLL VCO

F_C

Frequency

Period

600

1334

1.66

MHz

ns

T_C

0.7496

MAL Clock

F_C

Frequency

Period

45

12

83.33

22.2

MHz

ns

T_C

Figure 4. Timing Waveform

T

CL

CH

T

C

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Data Sheet

Spread Spectrum Clocking

Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440EP. This controller

uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to

as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the

SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the

PPC440EP the following conditions must be met:

• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the

PPC440EP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower

the frequency.

• The maximum frequency deviation cannot exceed −3%, and the modulation frequency cannot exceed 40kHz.

In some cases, on-board PPC440EP peripherals impose more stringent requirements.

• Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the

modulation.

• Use the DDR SDRAM MemClkOut since it also tracks the modulation.

Notes:

1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of

approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that

the connected device is running at precise baud rates.

2. Ethernet operation is unaffected.

3. IIC operation is unaffected.

Important: It is up to the system designer to ensure that any SSCG used with the PPC440EP meets the above

requirements and does not adversely affect other aspects of the system.

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I/O Specifications

Data Sheet

Table 15. Peripheral Interface Clock Timings

Parameter

PCIClk input frequency (asynchronous mode)

PCIClk period (asynchronous mode)

PCIClk input high time

Min

Max

Units

MHz

ns

Notes

–

66.66

15

–

40% of nominal period

60% of nominal period

ns

PCIClk input low time

40% of nominal period

60% of nominal period

ns

EMCMDClk output frequency

EMCMDClk period

–

2.5

MHz

ns

400

–

EMCMDClk output high time

EMCMDClk output low time

EMCTxClk input frequency MII(RMII)

EMCTxClk period MII(RMII)

EMCTxClk input high time

160

–

ns

–

ns

2.5(5)

25(50)

MHz

ns

40(20)

400(200)

35% of nominal period

2.5(5)

–

ns

EMCTxClk input low time

–

ns

EMCRxClk input frequency MII(RMII)

EMCRxClk period MII(RMII)

EMCRxClk input high time

25(50)

MHz

ns

40(20)

400(200)

35% of nominal period

–

ns

EMCRxClk input low time

ns

PerClk (and OPB clock) output frequency (for ext. master or

sync. slaves)

–

66.66

MHz

PerClk period

15

–

ns

PerClk output high time

PerClk output low time

50% of nominal period

33% of nominal period

66% of nominal period

50% of nominal period

1000/(2T_OPB¹+2ns)

UARTSerClk input frequency

UARTSerClk period

–

MHz

ns

1

2T_OPB+2

T_OPB+1

–

UARTSerClk input high time

ns

T

_OPB+1

UARTSerClk input low time

USB2Clk input frequency

USB1Clk input frequency

–

ns

60

48

60

48

MHz

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Data Sheet

Table 15. Peripheral Interface Clock Timings (Continued)

Parameter

TmrClk input frequency

TmrClk period

Min

–

Max

Units

MHz

ns

Notes

100

10

–

TmrClk input high time

TmrClk input low time

Notes:

40% of nominal period

60% of nominal period

ns

1. T_OPBis the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maxi-

mum OPB clock frequency is 66.66 MHz.

Figure 5. Input Setup and Hold Waveform

Clock

T

min

IS

T

min

IH

Inputs

Valid

Figure 6. Output Delay and Float Timing Waveform

Clock

max

min

max

min

T

OV

T

min

T

OH

Outputs

OH

High (Drive)

Float (High-Z)

Valid

Low (Drive)

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Data Sheet

Table 16. I/O Specifications—All Speeds (Sheet 1 of 3)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

Input (ns)

Output (ns)

Output Current (mA)

Signal

Clock

Notes

async

Setup Time Hold Time

Valid Delay

(T_OVmax)

Hold Time

(T_OHmin)

I/O H

(minimum)

I/O L

(minimum)

(T_ISmin)

(T_IHmin)

PCI Interface

PCIAD31:00

PCIC3:0/BE3:0

PCIClk

5

0

6

2

0.5

na

1.5

na

PCIClk

dc

5

dc

0

PCIDevSel

PCIFrame

PCIGnt0:5

PCIIDSel

6

2

0.5

na

1.5

na

PCIClk

5

0

n/a

5

n/a

0

6

2

n/a

6

n/a

2

PCIINT

n/a

5

n/a

0

0.5

na

1.5

na

PCIIRDY

6

2

PCIPar

5

0

6

2

PCIPErr

5

0

6

2

PCIReq0:5

PCIReset

PCISErr

5

0

n/a

6

n/a

2

n/a

5

n/a

0

na

0.5

1.5

PCIStop

5

0

6

2

PCITRDY

Ethernet MII Interface

EMCCD

5

0

6

2

10

n/a

5.1

na

6.8

na

1, async

EMCCrS

EMCDV

EMCMDClk

EMCMDIO

EMCRxClk

EMCRxD0:3

EMCRxErr

EMCTxClk

EMCTxD0:3

EMCTxEn

EMCTxErr

1, async

10

n/a

10

n/a

10

20

n/a

20

0

n/a

0

EMCMDClk

1

1, async

EMCRxClk

1

10

1

n/a

1, async

5.1

6.8

EMCTxClk

1

20

0

20

0

for MII,

RMII,

SMII

RejectPkt

0481

0.277

EMCRxClk

Ethernet RMII Interface

EMC0CRSDV

EMC0RxD0:1

EMC0RxErr

4

2

n/a

0

5.1

6.8

EMCRefClk

1

4

2

n/a

EMC0TxD0:1

EMC1CRSDV

EMC1RxD0:1

EMC1RxErr

n/a

4

n/a

2

12.5

n/a

0

4

2

n/a

5.1

6.8

EMCRefClk

1

4

2

n/a

1

EMC1TxD0:1

EMCRefClk

n/a

12.5

n/a

1, async

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Data Sheet

Table 16. I/O Specifications—All Speeds (Sheet 2 of 3)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

Input (ns)

Output (ns)

Output Current (mA)

Signal

Clock

Notes

Setup Time Hold Time

Valid Delay

(T_OVmax)

Hold Time

(T_OHmin)

I/O H

(minimum)

I/O L

(minimum)

(T_ISmin)

(T_IHmin)

Ethernet SMII Interface

EMC0RxD

1.5

n/a

1.5

n/a

1

n/a

3.5

n/a

3.5

n/a

0

5.1

6.8

EMCRefClk

1

EMC0TxD

n/a

1

EMC1RxD

n/a

0

1

EMC1TxD

n/a

EMCRefClk

n/a

1, async

Internal Peripheral Interface

IIC0SClk

n/a

5

0

15.3

n/a

10.2

n/a

IIC0SData

IIC1SClk

IIC1SData

SCPClkOut

SCPDI

7

2

6

n/a

6

0

n/a

0

7

2

SCPDO

n/a

7

n/a

0.05

n/a

0.02

n/a

0.05

n/a

0.1

n/a

UARTSerClk

UARTn_Rx

UARTn_Tx

n/a

3

n/a

0

n/a

10.3

n/a

7.1

UARTn_DCD

UARTn_DSR

UARTn_CTS

UARTn_DTR

UARTn_RI

n/a

na

10.3

n/a

7.1

n/a

UARTn_RTS

USB1Clk

10.3

n/a

7.1

n/a

USB1DevXcvr

USB1HostXcvr

USB2Clk

USB 1.1

n/a

USB 1.1

n/a

3

0

3

0

3

0

n/a

3

n/a

0

USB2DI0:7

n/a

USB2DO0:7

USB2LS0:1

USB2OM0:1

USB2RxAct

USB2RxDV

USB2RxErr

USB2Susp

n/a

5.2

n/a

7

5.1

6.8

n/a

3

n/a

0

n/a

7.1

9.6

n/a

3

n/a

0

n/a

6

7.1

9.6

3

0

7.1

9.6

3

0

7.1

9.6

USB2TermSel

USB2TxRdy

USB2TxVal

USB2XcvrSel

Interrupts Interface

IRQ0:9

3

0

7.1

9.6

n/a

3

n/a

0

n/a

7.1

9.6

3

0

7.1

9.6

n/a

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Data Sheet

Table 16. I/O Specifications—All Speeds (Sheet 3 of 3)

Notes:

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

Input (ns)

Output (ns)

Output Current (mA)

Signal

Clock

Notes

Setup Time Hold Time

Valid Delay

(T_OVmax)

Hold Time

(T_OHmin)

I/O H

(minimum)

I/O L

(minimum)

(T_ISmin)

(T_IHmin)

JTAG Interface

TCK

n/a

async

TDI

TDO

15.3

n/a

10.2

n/a

TMS

TRST

n/a

System Interface

SysClk

n/a

10.3

n/a

7.1

n/a

TmrClk

async

SysReset

Halt

SysErr

TestEn

DrvrInh1:2

RcvrInh

GPIO00:63

PSROOut

Trace Interface

TrcClk

10.3

7.1

n/a

10.3

7.1

TrcBS0:2

TrcES0:4

TrcTS0:6

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Data Sheet

Table 17. I/O Specifications—333MHz to 533MHz

Notes:

1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.

Input (ns)

Output (ns)

Output Current (mA)

Signal

Clock

Notes

Setup Time Hold Time

Valid Delay

(T_OVmax)

Hold Time

(T_OHmin)

I/O H

(minimum)

I/O L

(minimum)

(T_ISmin)

(T_IHmin)

External Slave Peripheral Interface

DMAAck0:1

DMAAck2:3

DMAReq0:3

EOT0:1/TC0:1

EOT2:3/TC2:3

PerAddr02:31

PerBLast

n/a

11.7

4

n/a

0.5

1

10

1

5.1

15.3

na

6.8

10.2

na

PerClk

1

n/a

10

n/a

1

5.1

6.8

10

1

15.3

10.3

15.3

10.2

7.1

7.2

6.5

7.2

6.5

n/a

6.5

1.5

n/a

1.5

4

1

PerCS0:5

n/a

4

n/a

1

PerData00:15

PerOE

10.2

n/a

6

n/a

1

PerReady

PerR/W

4

1

PerWBE0:1

4

1

External Master Peripheral Interface

BusReq

n/a

4

n/a

1

6.5

n/a

6.0

6.5

n/a

1.5

n/a

1.5

n/a

7.1

9.6

n/a

10.2

9.6

na

PerClk

ExtAck

ExtReq

n/a

ExtReset

HoldAck

HoldReq

HoldPri

n/a

4

n/a

1

15.3

7.1

na

4

1

na

PerClk

n/a

6

n/a

1

15.3

10.3

10.2

7.1

PLB Clk

PerClk

1

PerErr

NAND Flash Interface

NFALE

n/a

4

n/a

1

6.5

n/a

6.5

1.5

n/a

1.5

5.1

10.3

5.1

na

6.8

7.1

6.8

na

NFCE0:3

NFCLE

NFRdyBusy

NFREn

n/a

5.1

6.8

NFWEn

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DDR1 SDRAM I/O Specifications

Data Sheet

The DDR1 SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from

the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the

same frequency as the PLB clock signal and is in phase with the PLB clock signal.

Note: MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR

programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific

application and requires a thorough understanding of the memory system in general (refer to the DDR

SDRAM controller chapter in the PowerPC 440EP User’s Manual).

In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and

MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90°. Advancing MemClkOut0 by 90°

creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to

MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.

The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths.

Values are calculated over best case and worst case processes with speed, temperature, and voltage as follows:

Best Case = Fast process, -40°C, +1.6V

Worst Case = Slow process, +85°C, +1.4V

Note: In all the following DDR tables and timing diagrams, minimum values are measured under best case

conditions and maximum values are measured under worst case conditions.

The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.

Figure 7. DDR SDRAM Simulation Signal Termination Model

MemClkOut0

10pF

120Ω

10pF

MemClkOut0

V

= SV /2

DD

TT

PPC440EP

50

Ω

Addr/Ctrl/Data/DQS

30pF

Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.

It is not a recommended physical circuit design for this interface. An actual interface design will depend on many

factors, including the type of memory used and the board layout.

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Data Sheet

Table 18. DDR SDRAM Output Driver Specifications

Output Current (mA)

Signal Path

I/O H (maximum)

I/O L (minimum)

Write Data

MemData00:07

MemData08:15

MemData16:23

MemData24:31

ECC0:7

15.2

DM0:8

MemClkOut0

MemAddr00:12

BA0:1

RAS

CAS

WE

BankSel0:3

ClkEn0:3

DQS0:8

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440EP – PPC440EP Embedded Processor

DDR SDRAM Write Operation

Data Sheet

The following diagram illustrates the relationship among the signals involved with a DDR write operation.

Figure 8. DDR SDRAM Write Cycle Timing

PLB Clk

MemClkOut0

MemClkOut0(90)

T

SA

Addr/Cmd

T

DS

T

SK

DS

T

HA

DQS

T

SD

T

SD

MemData

T

HD

T

HD

T

= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)

= Setup time for address and command signals to MemClkOut0(90)

SK

T

SA

T

= Hold time for address and command signals from MemClkOut0(90)

HA

SD

HD

DS

= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)

= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)

= Delay from rising/falling edge of clock to the rising/falling edge of DQS

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Data Sheet

Note: The timing data in the following tables is based on simulation runs using Einstimer.

Table 19. I/O Timing—DDR SDRAM T

DS

Notes:

1. All of the DQS signals are referenced to MemClkOut0(0).

2. Clock speed is 133MHz.

3. The T_DSvalues in the table include 3/4 of a cycle at 133MHz (7.5ns x 0.75 = 5.625 ns).

4. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle

time for the lower clock frequency (T_DS- 5.625 + 0.75T_CYC).

T_DS(ns)

Signal Name

Minimum

5.76

Maximum

5.86

DQS0

DQS1

DQS2

DQS3

DQS8

5.78

5.91

5.82

5.90

5.79

5.89

5.75

5.88

Table 20. I/O Timing—DDR SDRAM T , T , and T

SK SA

HA

Notes:

1. Clock speed is 133MHz. T_SKis referenced to MemClkOut0(0). T_SAand T_HAare referenced to MemClkOut0(90).

2. To obtain adjusted T_SAvalues for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and subtract

T_SKmaximum (0.75T_CYC- T_SKmax).

3. To obtain adjusted T_HAvalues for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add

T_SKminimum (0.25T_CYC+ T_SKmin).

T_SK(ns)

T_SA(ns)

T_HA(ns)

Signal Name

Minimum

0.11

Maximum

0.32

Minimum

5.31

Minimum

1.99

MemAddr00:12

BA0:1

0.07

0.31

5.32

1.95

BankSel0:3

ClkEn0:3

CAS

0.05

0.25

5.38

1.93

0.07

0.28

5.35

1.95

0.05

0.31

5.32

1.93

RAS

0.05

0.28

5.35

1.93

WE

0.08

0.22

5.41

1.96

Table 21. I/O Timing—DDR SDRAM T and T

SD

HD

Notes:

1. T_SDand T_HDare measured under worst case conditions.

2. Clock speed for the values in the table is 133MHz.

3. The time values in the table include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).

4. To obtain adjusted T_SDand T_HDvalues for lower clock frequencies, subtract 1.875 ns from the values in the table and add

1/4 of the cycle time for the lower clock frequency (e.g., T_SD- 1.875 + 0.25T_CYC).

T_SD(ns)

T_HD(ns)

Signal Names

MemData00:07, DM0

MemData08:15, DM1

MemData16:23, DM2

MemData24:31, DM3

ECC0:7, DM8

Reference Signal

DQS0

1.795

1.775

1.745

1.765

1.685

1.866

1.865

1.862

1.864

1.857

DQS1

DQS2

DQS3

DQS8

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DDR SDRAM Read Operation

Data Sheet

The following examples of timing for DDR SDRAM read operations are based on the relationship between the

incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of

MemClkOut(0) relative to the PLB clock (T ) is provided.

MD

The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the

PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be

programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set

in RDCT. The delay of Read Clock relative to the PLB clock (T ) shown below assumes the programmable Read

RD

Clock delay is set to zero.

Figure 9. DDR SDRAM MemClkOut0 and Read Clock Delay

PLB Clk

MemClkOut0(0)

T

MD

T

min = 600ps

MD

T

max = 1100ps

MD

Read Clock

T

RD

Note:

T

min = 300ps

max = 740ps

RD

min values assume best case conditions.

RD

max values assume worst case conditions.

In operation, following the receipt of an address and read command from the PPC440EP, the SDRAM generates

data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440EP using a DQS

signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs

using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to

be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of

Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.

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Data Sheet

Figure 10. DDR SDRAM Read Data Path

Mux

RDSP

FF

Package pins

Q

D

PLB bus

ECC

Stage 3

Stage 1

Stage 2

Q

D

Q

D

Q

C

FF,

XL

FF

Data

DQS

C

Read Select

(SDRAM0_TR1)

1/4

Cycle

Delay

Programmed

Read Clock

Delay

PLB Clock

FF Timing:

T

= Input setup time = 0.2ns

= Input hold time = 0.1ns

= Propagation delay (D to Q or C to Q) = 0.4ns maximum

FF: Flip-Flop

XL: Transparent Latch

IS

IH

P

Table 22. I/O Timing—DDR SDRAM T

and T

DIN

SIN

Notes:

1. T_SIN= Delay from DQS at package pin to C on Stage 1 FF.

2. T_DIN= Delay from data at package pin to D on Stage 1 FF.

3. Clock speed for the values in the table is 133MHz.

4. The time values for T_SINinclude 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).

T_SIN(ns)

minimum

T_SIN(ns)

maximum

T_DIN(ns)

minimum

T_DIN(ns)

maximum

Signal Name

MemData00:07

DQS0

DQS1

DQS2

DQS3

DQS8

2.74

2.75

2.74

2.76

2.77

3.70

3.69

3.68

0.86

1.87

1.86

1.85

1.83

MemData08:15

MemData16:23

MemData24:31

ECC0:7

0.87

0.89

0.88

0.89

In the following examples, the data strobes (DQS) and the data are shown to be coincident. There is actually a

slight skew as specified by the SDRAM specifications, and there can be additional skew due to loading and signal

routing. It is recommended that the signal length for all of the eight DQS signals be matched.

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Data Sheet

Example 1:

If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage

1 data is sampled at (1). Except for small, low frequency memory systems with the memory located physically

close to the PPC440EP, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary

to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to

allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example, T is

T

system dependent and taken into account by controller initialization software.

Figure 11. DDR SDRAM Read Cycle Timing—Example 1

DQS at pin

Data at pin

D0

D1

D3

D2

T

SIN

DQS Stage 1 C

Data in Stage 1 D

D0

D1

D3

D2

T

DIN

T

P

T

P

High

Low

D0

D1

D2

D3

Data out Stage 1

D0

D2

High

Low

D0

D1

D2

D3

Data in at RDSP

with no ECC

D2

D0

T

PLB Clock

High

Low

D0

D1

D2

D3

Data out RDSP

(1)

T

= Delay from DQS at package pin to C on Stage 1 FF.

= Propagation delay through FFs

SIN

T

P

T

= Delay from data at package pin to D on Stage 1 FF.

DIN

T = Propagation delay, Stage 1 input to RDSP input w/o ECC

T

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Data Sheet

Example 2:

In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at (2). If ECC

is enabled, Stage 3 data must be sampled (see Example 3). In this example, T and T are system dependent

T

TE

and taken into account by controller initialization software.

Figure 12. DDR SDRAM Read Cycle Timing—Example 2

DQS at pin

Data at pin

D0

D1

D3

D2

T

SIN

DQS Stage 1 C

Data in Stage 1 D

D0

D1

D3

D2

T

DIN

T

P

High

Low

D0

D1

D2

D3

Data out Stage 1

D0

D2

PLB Clock

Read Clock Delayed

T

P

D0

D1

High

D2

D3

Data out Stage 2

Low

High

Low

D2

D3

D0

D1

Data in at RDSP

without ECC

T

TE

High

Low

D0

D1

D2

D3

Data in at RDSP

with ECC

High

Low

D0

D1

D2

D3

Data out at RDSP

without ECC

(2)

T = Propagation delay from Stage 2 input to RDSP input w/o ECC

T

= Propagation delay from Stage 2 input to RDSP input with ECC

TE

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Data Sheet

Example 3:

In this example, ECC is enabled. This requires that Stage 3 data be sampled at (3). If ECC is disabled, the system

will still work, but there will be more latency before the data is sampled into RDSP. In this example, T and T are

T

TE

system dependent and taken into account by controller initialization software.

Figure 13. DDR SDRAM Read Cycle Timing—Example 3

DQS at pin

Data at pin

D0

D1

D3

D2

T

SIN

DQS Stage 1 C

Data in Stage 1 D

D0

D1

D3

D2

T

DIN

T

P

High

Low

D0

D1

D2

D3

Data out Stage 1

D0

D2

PLB Clock

Read Clock Delayed

T

P

D0

D1

High

D2

D3

Data out Stage 2

Low

High

Low

D2

D3

D0

D1

Data out Stage 3

with ECC

T

TE

High

Low

D0

D1

D2

D3

Data in at RDSP

with ECC

High

Low

D0

D1

D2

D3

Data out RDSP

with ECC

(3)

T = Propagation delay from Stage 2 input to RDSP input w/o ECC

T

= Propagation delay from Stage 2 input to RDSP input with ECC

TE

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Data Sheet

Initialization

The PPC440EP provides the option for setting initial parameters based on default values or by reading them from

a slave PROM attached to the IIC0 bus (see “EEPROM” below). Some of the default values can be altered by

strapping on external pins (see “Strapping” below).

Strapping

While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default

initial conditions prior to PPC440EP start-up. The actual capture instant is the nearest reference clock edge before

the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0)

resistors to select the desired default conditions. These pins are used for strap functions only during reset.

Following reset they are used for normal functions. The signal names assigned to the pins for normal operation are

shown in parentheses following the pin number.

The following table lists the strapping pins along with their functions and strapping options:

Table 23. Strapping Pin Assignments

Ball Strapping

Function

Option

R25

U26

V26

(UART0_DCD)

(UART0_DSR)

(UART0_CTS)

Serial device is disabled. Each of the six options (A–

F) is a combination of boot source, boot-source

width, and clock frequency specifications. Refer to

the IIC Bootstrap Controller chapter in the

PPC440EP Embedded Processor User’s Manual for

details.

A

0

1

0

1

0

1

0

1

0

1

0

1

B

C

D

E

F

Serial device is enabled. The option being selected is

the IIC0 slave address that will respond with

configuration data.

G (0xA8)

Note: If reading of configuration data from the serial

device fails, the PPC440EP defaults to configuration

X.

H (0xA4)

1

EEPROM

During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device

connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440EP

sequentially reads 16 bytes from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,

SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly.

The initialization settings and their default values are covered in detail in the PowerPC 440EP User’s Manual.

82

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Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Revision Log

Data Sheet

Date

Version

Contents of Modification

08/21/2003

09/22/2003

10/07/2003

10/13/2003

10/31/2003

11/03/2003

11/25/2003

12/15/2003

12/19/2003

01/12/2004

Initial creation of document.

Misc. updates and corrections.

Add I/O timing.

Miscellaneous updates.

Correct initialization strapping pins and response IIC interface.

Correct OV_DDand SV_DDpin assignments.

Delete heat sink mounting information placeholders and remove Confidential status.

Restore Confidential status.

Update DDR SDRAM interface timing section.

Correct MemClkOut0 pin assignment.

Correct SDRAM PLL voltage.

03/15/2004

Add Note 6 to UARTn_CTS signal.

Correct SDRAM I/O worst case spec temperature.

Change 333MHz to 400MHz.

04/7/2004

09/2/2004

Correct label on Ethernet transmit signals.

Convert to AMCC format.

Modify headers to flip between left and right pages like the footers.

Change part numbers to AMCC part numbers.

Remove Confidential status, again

09/8/2004

Add USB clock frequency numbers.

Number table and figure captions.

09/28/2004

10/06/2004

Correct USB block diagram and description.

Update formatting and PDF book marking.

10/12/2004

10/28/2004

Add missing DDR SDRAM timing data.

Miscellaneous updates.

Add RejectPkt signal to pin Y25. Issue 31

Corrected numbering on PCIReq signal. Issue 30

Added notes to USB signals to correctly define required pull-ups and pull-downs. Issue 20

11/18/2004

Correct typo on voltage specification for SAV

in the DC Power Supply Loads table. Issue 9

DD

Misc. typo corrections. Issue 29

11/19/2004

11/22/2004

Change bootstrap option numbers to letters and add two options.

Correct bootstrap pin settings to match new letter designations.

Add Revision B part numbers for both leaded and lead-free packages and tape-and-reel

shipping.

12/17/2004

Add input capacitance values.

01/18/2005

01/31/2005

02/08/2005

Update and add missing voltage supply currents.

Update DDR SDRAM timing.

Change circuit type info for some system interface signals and move RejectPkt to the Ethernet

group.

AMCC Proprietary

83

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Date

Version

Contents of Modification

02/15/2005

03/10/2005

03/25/2005

04/27/2005

05/24/2005

Miscellaneous updates

Correct I/O timing specs for ExtReq signal.

USB 2.0 I/O and DDR SDRAM timing updates.

Add RoHS compliance statement.

Updates and additions to power and thermal specifications.

Add new 667MHz PNs and remove old 466MHz PNs.

06/14/2005

07/06/2005

08/08/2005

10/05/2005

Change maximum NAND Flash to 256MB.

Change solder ball size specification and add thermally enhanced package specification.

Miscellaneous updates

1.20

1.21

Remove metal-layer specification from technology description.

Change default configuration when bootstrap IIC read fails from option A to configuration X.

Add package nomenclature.

11/18/2005

Correct MemClkOut duty cycle.

Correct and move PerErr signal description from master to slave.

Change maximum VCO freqruency to 1334MHz.

02/16/2006

05/24/2006

07/19/2006

1.22

1.23

1.24

Add revision level 2.1 (C) part number and PVR number.

Update power dissipation and add additional temperature data.

Correct enable/disable specifications for PCI Gnt/Req signals.

Change analog voltage filter circuit inductor part number.

Change all multiplexed GPIO signal defaults to the GPIO signals.

Change AC12 default from IRQ5 to DMAReq1.

12/18/2006

1.25

Correct descriptions of LeakTest, RcvrInh, ModeCtrl, RefEn, and DrvrInh1:2 signals

Remove “Preliminary” status from header.

84

AMCC Proprietary

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Printed in the United States of America, December 18, 2006

The following are trademarks of AMCC Corporation in the United States, or other countries, or both:

AMCC

Other company, product, and service names may be trademarks or service marks of others.

December 18, 2006

This document contains information on a new product under development by AMCC.

AMCC reserves the right to change or discontinue this product without notice.

This document is a preliminary edition of the PowerPC 440EP data sheet. Make sure you are using the correct

edition for the level of the product.

While the information contained herein is believed to be accurate, such information is preliminary, and should not

be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness

are made.

The information contained in this document is subject to change or withdrawal at any time without notice

and is being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or

implied, including without limitation, the implied warranties of non-infringement, merchantability, or

fitness for a particular purpose. Any products, services, or programs discussed in this document are sold

or licensed under AMCC's standard terms and conditions, copies of which may be obtained from your

local AMCC representative. Nothing in this document shall operate as an expressed or implied license or

indemnity under the intellectual property rights of AMCC or third parties.

Without limiting the generality of the foregoing, any performance data contained in this document was

determined in a specific or controlled environment and not submitted to any formal AMCC test. Therefore,

the results obtained in other operating environments may vary significantly. Under no circumstances will

AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or

the information contained herein.

AMCC Proprietary

85

Revision 1.25 – December 18, 2006

440EP – PPC440EP Embedded Processor

Data Sheet

Applied Micro Circuits Corporation

215 Moffett Park Drive, Sunnyvale, CA 94089

Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885

http://www.amcc.com

AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and war-

rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data

sheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations.

AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest

version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia-

bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under

its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower

grade.

AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE

SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL

APPLICATIONS.

86

AMCC Proprietary


型号：	PPC440EP-3UC400CZ
厂家：	APPLIED MICRO CIRCUITS CORPORATION
描述：	RISC Microprocessor, 32-Bit, 400MHz, CMOS, PBGA456, 35 MM, ROHS COMPLIANT, THERMALLY ENHANCED, PLASTIC, BGA-456
文件：	总86页 (文件大小：1207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PPC440EP-3UC400CZ [AMCC]

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