S2021B [AMCC]
Telecom Circuit, 1-Func, BICMOS, PQFP208, THERMALLY ENHANCED, PLASTIC, PACKAGE-208;型号: | S2021B |
厂家: | APPLIED MICRO CIRCUITS CORPORATION |
描述: | Telecom Circuit, 1-Func, BICMOS, PQFP208, THERMALLY ENHANCED, PLASTIC, PACKAGE-208 电信 信息通信管理 电信集成电路 |
文件: | 总23页 (文件大小:239K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
®
DEVICE SPECIFICATION
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
S2020/S2021 HIPPI Chipset
FEATURES
• Functionally compliant with the ANSI HIPPI
standard
• 32-Bit data channel
• Equivalent single channel rate of 800 Mbits/sec
• Host-side interface single-ended TTL designed
for use with external FIFO
• Channel-side interface differential ECL 10K
• Four rank data and control signal
synchronization
• Byte parity checking
• Length/Longitudinal Redundancy Checkword
(LLRC) generation and checking
• Automatic division of data into HIPPI bursts
• 16-Bit READY counter for flow control
• Maximum latency through both ICs
Connection: 600ns, Data: 400ns
• Diagnostic modes for self test
• Standard +5V, 0V(gnd), and -5.2V power
requirements
GENERAL DESCRIPTION
The S2020 and the S2021 are Source and Destination
interface circuits, respectively, for the High-
Performance Parallel Interface (HIPPI) standard.
These circuits are designed to completely meet the
signalling protocol of the proposed ANSI HIPPI
specification: current document number X3.183–
1991 They include both LLRC generation and
checking as well as byte parity checking. The
S2021 also incorporates a sophisticated four rank
synchronization scheme to ensure that the incoming
data and control signals are coupled to the local
clock. Data flow control is provided by a 16-bit ready
counter in both the Source and the Destination
circuits. HIPPI data BURST partitioning is also
provided in the Source circuit.
• 225-pin ceramic PGA package
• 208-pin Thermally Enhanced Plastic (TEP)
Figure 1. Interface Signal Summary
Request
Connect
Architected and designed by Network Systems
Corporation, the S2020 and S2021 utilize AMCC’s
1.5-micron BiCMOS technology. AMCC’s BiCMOS
technology is especially optimized for high performance
mixed mode ECL/TTL applications such as the
HIPPI Source and Destination interfaces. AMCC
pioneered ECL/TTL mixed mode BiCMOS capability
and continues to be the leading U.S. supplier of
BiCMOS VLSI circuits.
32
4
Data Bus
Parity Bus
Source
Destination
Ready
Packet
Burst
Clock
Interconnect S ➔ D
Interconnect D ➔ S
Source: ANSI X3.183–1991
High-Performance Parallel Interface.
Mechanical, Electrical, and Signalling
Protocol Specification (HIPPI-PH).
1
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Once the connection is established, data transfer
can proceed according to the Physical Framing
HIPPI OVERVIEW
The individual HIPPI channel is a simplex interface,
meaning that data moves in one direction from the
HIPPI Source (S2020) to the HIPPI Destination
(S2021). Thus a fully bidirectional interface requires
the use of two HIPPI channels as indicated in the
System Block Diagram.
Hierarchy (see Figure 3). The basic data block is the
Burst consisting of from 1 to 256 words of 32 data
bits and 4 bits of odd byte parity. Each Burst is
delimited by the assertion and deassertion of the
BURST signal by the data Source. Every burst is
followed immediately by Length/Longitudinal Redun-
dancy Checkword (LLRC) which is the even parity
for each bit for the entire length of the Burst together
with the modulo 256 count of the number of words in
the Burst. The count is included in the parity
calculation for the least significant 8 bits of the LLRC
word. For the normal full burst of 256 words, the
count is all zeros (256 base 2 truncated to 8 bits).
Figure 2. System Block Diagram
S
2
0
2
0
S
2
0
2
1
HIPPI
HIPPI
FIFO
FIFO
FIFO
FIFO
HOST
MEMORY
SYSTEM
HOST
MEMORY
SYSTEM
S
2
0
2
1
S
2
0
2
0
Figure 3. Physical Framing Hierarchy
Disabled I-Field Connection
Packet
LLRC
Packet
Wait
Packet
The transfer of data from the Source to the
Destination depends on the physical connection of
the two endpoints and the exchange of requesting,
acknowledging, and data delimiting signals. The
Source and Destination circuits both observe the
state of the INTERCONNECT signals to verify a
physically intact channel. If both Source and
Destination are interconnected, the Source may
initiate a data transfer by asserting the REQUEST
signal. At the same time the Source places a 32 bit
word also known as the I-Field on the data lines
together with the appropriate Byte parity. The Upper
Level Protocols (ULPs) controlling the Source and
Destination may use this information for routing. The
Destination responds to the REQUEST by asserting
the CONNECT signal either for a short period while
leaving the READY signal inactive to actively reject
the REQUEST, or by asserting CONNECT and then
asserting the READY signal to accept the REQUEST
and indicate the availability of an input data buffer.
The Destination can also accept the REQUEST by
asserting CONNECT for a longer period without
sending a READY, thus indicating a temporary delay
in the availability of an input data buffer. The Source
may remove the I-Field data after detecting the
CONNECT signal.
Wait Burst
Wait Burst LLRC Wait Burst LLRC
256 words of 32 bits each
Source: ANSI X3.183–1991
High-Performance Parallel Interface.
Mechanical, Electrical, and Signalling
Protocol Specification (HIPPI-PH).
One or more Bursts are grouped as a Packet
delimited by the assertion and deassertion of the
PACKET signal by the Source. Wait periods are
placed between Bursts and between Packets to
allow synchronization adjustments between the
Source and Destination circuits. A connection may
contain one or more Packets. The details of the data
transfer handshake are shown in Figure 4.
S2020 AND S2021 DESCRIPTION
The S2020 Source and the S2021 Destination
circuits generate all of the required control and
handshaking signals described above in the correct
timing relationships, as well as providing Burst and
Packet control, READY to BURST coordination, and
LLRC generation and checking.
2
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 4. Typical HIPPI-PH Waveforms
The circuits provide diagnostic modes for testing the
devices themselves plus the circuitry that interfaces
to the device. In the self-test modes, the INTER-
CONNECT signal can be deasserted. This
effectively “unplugs” the device undergoing self-test
from the HIPPI channel making it unavailable for
connection and thus unable to generate spurious data
or control information while in the diagnostic mode.
REQUEST (S)
CONNECT(D)
READY (D)
PACKET (S)
BURST (S)
DATA BUS (S)
S2020 HIPPI SOURCE DEVICE
I-Field Data LLRC Data LLRC
Data LLRC
Burst
This device meets the signalling protocol requirements
for a HIPPI-Source; i.e., it controls the forward signals
and receives and acts on the reverse signals.
Burst
Burst
Source: ANSI X3.183–1991
High-Performance Parallel Interface.
Mechanical, Electrical, and Signalling
Protocol Specification (HIPPI-PH).
The Host-side consists of 45 single-ended TTL inputs
used for data, control and the 50 MHz clock as well
as 9 single-ended TTL outputs used for control of
the external FIFO and to obtain device status.
The Host systems are the actual originator and the
ultimate destination of the data sent over the HIPPI
channel. The purpose of the S2020 and S2021 is to
decouple the Host hardware and software from the
timing and formatting details of the interface. Each
circuit can be considered as having a “Host-side”
and a “HIPPI-side.” The Host-side of the Source
circuit accepts data from the Host FIFO and passes
it to the HIPPI-side. The HIPPI-side controls the
forward signals (REQUEST, PACKET, BURST and
CLOCK) and receives the reverse signals (CONNECT
and READY) of the HIPPI channel. The HIPPI-side of
the Destination circuit receives the forward signals
and controls the reverse signals of the HIPPI
channel. The Host-side of the Destination delivers
the received data to the Host FIFO.
The HIPPI-side consists of 40 differential ECL
outputs (forward signals), 2 differential ECL inputs
(reverse signals), 1 single-ended TTL output
(Source-to-Destination INTERCONNECT signal) and
1 single-ended ECL input (Destination-to-Source
INTERCONNECT signal).
ELECTRICAL REQUIREMENTS
The differential ECL outputs require eighty 330 Ohm
2% resistors, one per pin. The differential ECL inputs
require two 110 Ohm 2% resistors, one per input pair.
The two INTERCONNECT signals require external
transmit and receive networks to reliably implement the
signal swing required by the HIPPI Specification. For
the Source-to-Destination INTERCONNECT (output
signal), the required network is shown in Figure 10.
The Host-side of both circuits can be thought of as
consisting of four sections:
It should be noted that this network is only required if
switching control of the INTERCONNECT signal by
the Source device is desired. The network may be
omitted and a simple pull-down of the Source-to-
Destination INTERCONNECT via a 220 Ohm resistor
to Vee may be used as indicated in the ANSI standard.
For the Destination-to-Source INTER-CONNECT (input
signal), the required network is shown in Figure 11.
• Connect Control (for connecting/disconnecting
to/from the HIPPI channel)
• Data/FIFO Control (for moving data to/from the
Host logic)
• Data + Parity (for presenting data to/from the
Host logic
• Status/Control (for general control of the circuit
and to obtain status from the circuit)
The network is strongly recommended for use on the
received INTERCONNECT signal to avoid risk of
saturation when operated with a switchable INTER-
CONNECT Destination device such as the S2021. It
is also recommended for use in the non-switched
passive pull-down applications to avoid damage to the
ECL input due to transients caused by mechanical
connection/disconnection cycles of the allowed cabling
while Source and Destination are under power.
The purpose of these circuits is to reduce the
complexity of the circuitry required to mate a Host
memory system to the HIPPI channel. The Host-side
is primarily single-ended TTL while the HIPPI-side is
primarily differential ECL. Beside meeting the
signalling protocol requirements of the HIPPI
standard, the circuits provide a reduction of the
signal lines to the host interface.
3
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 5. HIPPI Source Block Diagram
Host-side
HIPPI-side
destination available
32 data + 4 parity
connect request
connect cut
accept/reject
Connect
Control
request
packet
short burst
packet available
burst available
data request
read clock
not read enable
data available
burst
Data/
FIFO
Control
HIPPI
SOURCE
SIGNAL
clock
connect
32 data + 4 parity
input parity error
Data
ready
mode select 0
mode select 1
mode select 2
50 MHz
Status/
Control
sequence error
interconnects
Source Not Dest.
54 TTI
85 ECL, 1 TTL
CONNECTION LATENCY
SOURCE CONNECT CONTROL
The Connection latency through the Source device
consists of two parts: 1) The delay from the rising
edge of the TTL input CONNECT_REQUEST to the
assertion of the REQUEST signal in parallel with the
placement of the I-Field data on the Host data bus
and its availability on the HIPPI channel data bus (4
clock cycles), and 2) the delay from the detection of
the CONNECT signal for the 17th clock cycle and
the assertion of the TTL outputs CONNECT_OUT
and ACCEPT/REJECT to the Host (3 to 4 clock
cycles). The total connection latency in the Source
device ranges from 7 to 8 clock cycles. This does
not include cable delay or Destination processing.
Connection control is provided by four control signals
and two error flags on the Host-side of the Source
device. Using the signals the Host can “request” a
connection to a Destination and monitor the results
(whether the Destination has accepted or rejected the
connection request). Timeout mechanisms, if required,
must be provided by the Host hardware or software.
DESTINATION_AVAILABLE (output) [DSTAV]*
A high level on this signal indicates an active
Destination-to-Source INTERCONNECT signal. Low
indicates inactive INTERCONNECT.
CONNECT_REQUEST (input) [CNREQ]
This signal when high directs the Source device to
read the I-Field from the Host System (see HIPPI
Data Control, page ). When a valid I-Field is read, it
is placed on the HIPPI channel and the HIPPI
REQUEST signal is asserted. The information in the
I-Field can be used by intermediate HIPPI nodes
(nodes that are not end-points) to control the routing
of the associated connection. The Host would then
monitor the CONNECT_OUT and ACCEPT/REJECT
signals to determine the state of the connection.
DATA LATENCY
The data latency through the Source device is
defined as the delay from the rising edge of the
BURST_AVAILABLE signal and the assertion of the
BURST signal on the HIPPI channel. The data
latency is 4 clock cycles. This does not include cable
delay or Destination processing.
*Bracketed signal name refers to pin matrix on pages 20–23 (all signals).
4
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
CONNECT_OUT (output) [CNOUT]
The Source device FLOW control circuit consists of a set
of 16-bit counters that automatically maintain the number
of READYs received from the HIPPI Destination and the
number of BURSTs sent to the HIPPI Destination. In
the Source device, these counters are reset when the
HIPPI channel is disconnected, and then enabled
when the HIPPI channel is reconnected. When the
BURST counter and the READY counter are equal,
data transfer will be disabled and both counters are
enabled. When the BURST counter and the READY
counter are not equal and their difference is not 65535
[(2exp16)-1], data transfer will be enabled and both
counters are enabled. When the difference between
the BURST counter and the READY counter is 65535,
data transfer is enabled and the READY counter is
disabled. Disabling the READY counter results in a limit
of 65535 pending READYs for the HIPPI connection.
This signal, along with the CONNECT_REQUEST
and ACCEPT/REJECT signals defines the current
state of the HIPPI connection. A high level indicates
active acceptance or rejection of a requested
connection.
ACCEPT/REJECT (output) [ACREJ]
This signal along with the CONNECT_REQUEST
and CONNECT_OUT signals defines the current
state of the HIPPI connection. A high level indicates
active acceptance of a requested connection.
SEQUENCE_ERROR (output) [SQERR]
This signal when high indicates the presence of
either a Source error state (PACKET_AVAILABLE
dropped before the first word of Burst transmitted or
CONNECT_REQUEST is reasserted before Destin-
ation has deasserted CONNECT) or Destination
error state (CONNECT is detected before REQUEST
has been asserted).
The Source FLOW control signals are:
BURST_AVAILABLE (input) [BSTAV]
This signal when held high enables the initiation of a
data transfer from the FIFO, through the Source
device, to the HIPPI channel. When held low this
signal prevents the initiation of a data transfer. A
transition from high to low after a data transfer has
been initiated has no effect on that transfer (i.e., the
current Burst will terminate normally).
SOURCE_NOT_DESTINATION (output) [SRNDS]
This signal is used to distinguish between a Source
error (logic 1 state) and a Destination error (logic 0
state).
DATA/FIFO CONTROL
This interface provides control to the Source Host
system, of the flow and organization of the data to be
transferred over the HIPPI channel. It is intended for
this interface to attach to an external synchronous
FIFO, which is in turn attached to the Source Host
memory system. Recommended FIFO’s capable of
buffering 4 or more Bursts are:
DATA_AVAILABLE (input) [DATAV]
This signal when high indicates the current presence of
at least one more word from the Source Host FIFO and
enables the synchronous load of the data bus into the
Source device. When low this signal disables the data
loading. It is intended that this signal be driven by the
Not Empty flag of the FIFO. In this configuration any
interruption of the data flow due to the FIFO not being
refilled by the host will result in a Short Burst with
normal LLRC and Burst termination. This signal must
be reasserted and the BURST_AVAILABLE signal
reasserted to start a subsequent Burst.
IDT P/N 72225LB20 1K x 18 bits
IDT P/N 72235LB20 2K x 18 bits
IDT P/N 72245LB20 4K x 18 bits
The signals of this interface can be divided into three
groups; Source FLOW control, Source FIFO control,
and HIPPI data control.
DATA_REQUEST (output) [DTREQ]
SOURCE FLOW CONTROL
This signal indicates the current ability of the HIPPI
Destination to accept data. When high the signal
indicates a current connection on the HIPPI channel
and the inequality of the BURST and READY
counters in the Source device FLOW control circuit.
When low, (and during a HIPPI channel connection)
the signal indicates the equality of the BURST and
READY counters in the Source device FLOW control
circuit, i.e., the Source has sent one BURST to the
HIPPI Destination for each READY received from
that Destination.
After a HIPPI connection is established, data
transfer from the Source Host to the Destination
Host is enabled by the presence of data from the
Source Host and the current ability of the Destination
Host to accept data. The presence of data from the
Source Host is indicated to the Source device on the
Source FLOW control lines. The ability of the
Destination Host to receive data is determined by
the Source device’s FLOW control circuit.
5
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
SOURCE FIFO CONTROL
HIPPI DATA CONTROL SIGNALS
SHORT_BURST PACKET_AVAILABLE
When a data transfer is enabled, the Source device
will initiate read operations of the Source Host FIFO
by activating the Source FIFO control lines.
(input) [SHBST]
(input) [PKTAV]
IDLE. No
PACKET or
BURST onto
HIPPI channel
0
0
The Source FIFO control signals are:
READ_CLOCK (output) [RDCLK]
Assert PACKET
onto the HIPPI
channel*
This signal is a continuous 25 MHz clock synchronous
with the internal clocks of the Source device and the
HIPPI channel differential ECL CLOCK signal. The
signal is intended to be used together with NREN to
control the read function of the FIFO and as a
reference for timing critical Host-side control signals
such as SHORT_BURST and PACKET_AVAILABLE.
This signal is intended to drive the ‘read clock’ input
of the Source Host FIFO system.
0
1
1
1
0
1
Associated data
is a HIPPI
I-Field
Associated data
is last word of
HIPPI Burst
When the Source Host initiates a HIPPI
CONNECT_REQUEST, the Source device performs
read operations until a HIPPI I-Field is read. The
Source device recognizes a HIPPI I-Field by
decoding the HIPPI data control lines. Once a HIPPI
I-Field is presented to the Source device, the
REQUEST line will be asserted on the HIPPI
channel and the I-Field will be put on the HIPPI
channel data bus. By identifying the HIPPI I-Field in
this way, the Source Host can effectively queue
several connections in the FIFO and also enter
primary and secondary I-Fields for single connections
to support alternate paths for connect reject retries.
NOT_READ_ENABLE (output) [NRDEN]
This signal when held low, is used to strobe data
from the FIFO to the Source device. This signal is
used as a gate of the 25 MHz TTL RDCLK for the
synchronous operation of the FIFO. This signal is
intended to drive the ‘read enable’ input of the
Source Host FIFO system.
HIPPI DATA CONTROL
PACKET_AVAILABLE (input) [PKTAV]
This signal when high causes the Source device to
start a Packet if Bursts are available. When brought
low, this signal will end the Packet.
When data transfers are enabled, as described
above, the HIPPI data control field specifies what
partitioning operations are to be performed by the
Source device on the associated data word. The
main partitioning operations are: begin HIPPI
Packet, maintain HIPPI Packet, terminate HIPPI
Packet, auto-burst termination, and explicit (short)
burst termination.
SHORT_BURST (input) [SHBST]
This signal when high while PACKET_AVAILABLE is low
indicates presence of I-Field data at the Source device
input data lines. During a Burst, a high level indicates that
the current data word is the last word of a Short Burst.
Each read operation performed by the Source device
reads a Data/Parity word, and an associated HIPPI
data control field consisting of the PACKET_AVAILABLE
and SHORT_BURST signals. Because the HIPPI
data control field is to be read in parallel with the
associated DATA and PARITY, these (two) bits can be
written by the Source Host into the Source Host FIFO
as the DATA and PARITY are transferred into it. As the
Source device reads each word from the Source Host
FIFO, the HIPPI data control field specifies what type
of HIPPI data operation is to be performed.
The three HIPPI Packet functions control the
organization of data into HIPPI Packets. The auto-
burst termination allows the Source device to
automatically delimit the unbounded data from the
Source Host FIFO into HIPPI Bursts of 256 (max)
words each. The Short Burst termination allows the
Source Host to specify BURST boundaries for HIPPI
data bursts. In addition to the explicit Short Burst
and auto-burst terminations, the Source device will
terminate a HIPPI Burst if the HIPPI Packet is
terminated at a non-256 word boundary or if the
Source Host supply of data expires on a non-256
word boundary.
The three basic types of HIPPI data operations are:
I-Field, HIPPI PACKET control, and HIPPI BURST
control. The HIPPI data control signals defining these
data types are shown on the HIPPI Data Control Table.
*The Source device will not assert Packet onto the HIPPI channel until the first
data Burst of the Packet is sent. This prevents the possible generation of a zero-
Burst Packet (illegal) onto the HIPPI channel.
6
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
The sequence of control signals and data presented to
the HIPPI channel by the Source device meet all the
requirements of the HIPPI specification. There is no
need for the Source Host to insert wait intervals
(dummy words) in the FIFO stream to provide the
required wait intervals between PACKET and BURST
(the FIFO can be 100% utilized for HIPPI
I-Field and data). The Source device will automatically
generate LLRC and append it to the end of each
terminated HIPPI Burst regardless of how the Burst
was terminated. It is the responsibility of the Source
Host to prevent multiple Short Bursts in one Packet.
input also latches the MODE_SELECT inputs on its
rising edge. The phase of the resulting 25 MHz clock
is controllable by the phase of the asserted RESET
mode described below.
SOURCE DEVICE OPERATING MODES
The Source device has several operating modes,
which require external selection by the Source Host.
Also provided is a ‘board test’ mode that may be used
by the Source Host as a part of a system diagnostic
routine. The Source Host selects the operating
mode with the two lines, MODE_SELECT_0 and
MODE_SELECT_1 [MSELx]. For numerical reference,
MODE_SELECT_1 is the most significant bit.
MODE_SELECT_2 should be held at a TTL logic zero
(ground) for in-board operation of the Source device.*
The Source device automatically formats the
transferred data into packets and bursts with LLRC.
The Source device counts the number of data words
received from the FIFO and uses this number as the
“seed” for the LLRC calculation.
Mode 0 (00 on mode select bus) is device reset. In
the reset mode, all internal registers are initialized,
and all device outputs are forced inactive including
the HIPPI Source-to-Destination INTERCONNECT
[SDIC] output. The ability to control the phase of the
25MHz clock (and the READ_CLOCK output) which
is generated by dividing the 50_MHZ input by 2 is
also provided by this mode.
DATA AND PARITY
The Source Host presents the HIPPI I-Field and
Data to the HIPPI Source device on the TTL DATA
AND PARITY interface.
32_DATA_+_4_PARITY (inputs) [DATxx,PARxx]
Mode 1 (01) is the board test mode. In this mode,
the Source device provides a means to verify
connection and operation of the interface between
the Source Host and the Source device completely
independent of the HIPPI channel. In this mode, the
Source-to-Destination INTERCONNECT [SDIC]
signal is forced inactive. When the Source Host
initiates a Connection Request by asserting
CONNECT_REQUEST, the Source device advances
the FIFO to the first I-Field, reads the I-Field, and then
simulates a Connect Accept on the HIPPI channel,
asserting the CONNECT_OUT and ACCEPT/ REJECT
signals to the Source Host. The Source Host will then
provide ‘test’ data bursts to the Source device
through the FIFO, as it would for a functional data
transfer, and the Source device will pass the ‘test’
data through the LLRC and parity check functions.
The data will also appear at the HIPPI-side data
outputs, but since the Source device is not in the
functional or wait Modes the Source-to-
Destination INTERCONNECT signal is inactive. The
only difference to the Source Host between a
functional transfer and a ‘test’ transfer is that the first
data word of each ‘test’ burst must be the expected
LLRC of the previous ‘test’ burst. By providing the
expected LLRC, the Source device can compare its
generated LLRC with the Host’s expected LLRC,
These lines are used for the I-Field during the connection
sequence and for data during Burst transfers.
INPUT_PARITY_ERROR (output) [INPRR]
Parity is checked just before the data leaves the
Source device (i.e. at the inputs to the differential
drivers of the HIPPI channel). Parity errors are
reported on a word by word basis. Upon detecting a
parity error for a given word, this signal is set high
for the duration of the next word’s clock cycle
(approximately 40 nsec).
Note: All parity errors are indicated but no recovery
action is taken by the Source device. If there is a
parity error detected, then the data and the bad
parity are passed through the Source.
CHIP STATUS/CONTROL
Overall control of the HIPPI Source device is provided
to the Source Host by the STATUS/CONTROL
interface, which allows the Source Host to control the
device clock frequency and phase (if necessary), and
to select the operating mode of the Source device.
50_MHZ (input) [50MHZ]
This 50 MHz TTL clock is divided by 2 to generate a
50% duty cycle 25 MHz clock for all internal timing
functions of the Source device and as the generated
and transmitted HIPPI channel CLOCK signal. This
*The active state of MODE_SELECT_2 is used for manufacturing test of
the Source device.
7
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 6. HIPPI Destination Block Diagram
HIPPI-side
Host-side
source available
connect request
connect in
accept/reject
32 data + 4 parity
request
Connect
Control
burst out
packet out
packet
burst
Data/
FIFO
Control
ready in
not reset ready
clock
HIPPI
Dest.
data valid
write clock
32 data + 4 parity
Rx parity error
Signals
connect
ready
Rx LLRC error
Data
sync error
mode select 0
mode select 1
mode select 2
25 MHz
50 MHz
Select 0
Select 1
Select 2
Status/
Control
interconnects
85 ECL, 1 TTL
57 TTL
S2021 HIPPI DESTINATION DEVICE
and thus verify the integrity of the DATA, PARITY,
and DATA/FIFO CONTROL busses. This test routine
continues until the Mode is changed or until a mis-
compare is detected between the Host’s expected
LLRC and the device’s generated LLRC. When a
mis-compare is detected, the simulated connection
is terminated and CONNECT_OUT is deactivated.
Mode 0 (reset) clears the board test mode.
This chip meets the signalling protocol requirements
for a HIPPI-Destination, i.e., it controls the reverse
signals and receives the forward signals.
The HIPPI-side consists of 40 differential ECL inputs
(forward going signals), 2 differential ECL outputs
(reverse signals), 1 single-ended ECL input (Source-
to-Destination INTERCONNECT signal), and 1
single-ended TTL output (Destination-to-Source
INTERCONNECT signal).
Mode 2 (10) is the WAIT mode. This mode provides
an interlock device between the Source Host and the
HIPPI channel that requires the Source Host to
acknowledge an inactive Destination-to-Source
INTERCONNECT [DSIC] before an active DSIC
signal is processed. In this mode the Source-to-
Destination INTERCONNECT [SDIC] is active. The
requirement upon the Source Host is that if
DESTINATION_AVAILABLE is inactive and the
Source Host is waiting for it to become active, the
Source device must be put into Mode 2. Once
DESTINATION_AVAILABLE is active, the Source
device must be put into Mode 3 to initiate further
operations.
The Host side consists of 45 single-ended TTL
outputs used for data, FIFO control and status, 9
single-ended TTL inputs used for chip control, a 25
MHz clock and a 50 MHz clock and 3 TTL
Bidirectional I/O.
In addition to the signal translation and control
handshake functions, the Destination device
provides a four stage “elastic store” for the buffering
of the data, parity, and control information received
from the HIPPI channel. This internal FIFO (not to be
confused with the external multi-Burst size FIFO)
together with a digital phase locked loop structure
allow the HIPPI channel clocked information to be
synchronized to the local (Host-side) 25 MHz clock.
The use of the combined 50 MHz and 25 MHz clocks
allow tracking of the synchronizer through more than
1200 degrees of phase “slip” or error between
received HIPPI clock and the local clock. In a
normally operating HIPPI channel, the accumulated
Mode 3 (11) is the operational mode. This mode
activates the Source-to-Destination INTERCONNECT
signal and enables the functional operation of all the
Source device interfaces.
NOTE: The only time DESTINATION_AVAILABLE will go from inactive to
active is if Destination-to-Source INTERCONNECT is active while the
Source device is brought from Mode 0 (reset) to Mode 3 (operational) or if
the Source device is in Mode 2 (wait).
8
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HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 7. SYNC/RESYNC Block Diagram
SYNC
DATA
Rank 0
SYNC
REGISTERS
and
Raw Data
Rank 1
Rank 2
Rank 3
HIPPI
INTERFACE
HIPPI
RESYNC
REGISTERS
Channel Clock
Signals
LATCHES
Sync Indicator
Resync Select
Local Clock
Rank
PHASE
GENERATOR
SYNC
CONTROL
Select
Local
Clock
Phase Select
PHASE
DETECTOR
PHASE
CONTROL
Resync
Phase Adjust
Sync Error
HIPPI State — Packet/Burst
phase error is re-zeroed during the inter-burst/packet
Wait period by resynchronization. Since multiple
nodes could be in the channel between the
originating Source and the final Destination, the
inter-burst Wait states may have been “consumed”
before the data is received. The large phase
tolerance of the synch/resynch circuitry (shown in
Figure 7) in the Destination device allows 48
consecutive Bursts with missing Wait states to be
received before synchronization is lost. A maximum
rate transfer through a chain of 30 nodes, all with
worst-case jitter, operating at progressively worse
frequency margins, and all requiring a ‘dropped’
cycle at the same time would be required between
the originating Source and the final Destination to
produce 48 consecutive missing Wait cycles.
This network is only required if switching control of
the INTERCONNECT signal by the Destination
device is desired. The network may be omitted and a
simple pull-down of the Destination-to-Source
INTERCONNECT via a 220 Ohm resistor to Vee
may be used as indicated in the ANSI standard. For
the Source-to-Destination INTERCONNECT (input
signal), the required network is shown in Figure 11.
CONNECTION LATENCY
The connection latency through the Destination
device consists of two parts:
1) the time between the arrival of the REQUEST
signal on the HIPPI channel from the Source device,
to the presentation by the Destination device of the
I-field to the TTL data lines and assertion of
CONNECT_REQUEST ranges from 4 to 5 clock
cycles;
ELECTRICAL REQUIREMENTS
The resistors needed to complete the electrical
requirements of the HIPPI-Destination interface are
four 330 Ohm 2% resistors, one per pin of differential
ECL outputs, and forty 110 Ohm 2% resistors, one per
pair of differential ECL inputs
2) the time between assertion of CONNECT_IN signal
by the host (to accept the connection request), to the
assertion of the CONNECT signal by the Destination
device on the HIPPI channel is 2 clock cycles.
The two INTERCONNECT signals require external
transmit and receive networks to reliably implement
the signal swing required by the ANSI standard. For
the Destination-to-Source INTERCONNECT (output
signal), the required network is shown in Figure 10.
The Destination device connection latency therefore
ranges from 6 to 7 clock cycles. This does not include
local host connection processing (the time it takes the
host to decide whether or not to accept a particular
connection request).
9
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
holding this input high will maintain an asserted
CONNECT signal on the HIPPI channel, while
DATA LATENCY
The data latency through the Destination device is
defined as the time between detection of the BURST
signal by the Destination device from the HIPPI, to
the presentation of the data to the FIFO on the TTL
data lines and the assertion of the DATA_VALID
line. The data latency ranges from 2 to 6 clock
cycles. There is no response by the Destination
device on the HIPPI channel to data reception.
dropping this input will deassert the CONNECT
signal (Disconnect Function). If a Connect Request
is rejected, holding this input high will maintain a
deasserted CONNECT signal on the HIPPI channel
(after the four cycle reject sequence) and disable
further Connect Requests, while dropping this input
will also maintain a deasserted CONNECT signal but
will enable further Connect Requests.
ACCEPT_REJECT (input) [ACCRJ]
CONNECT CONTROL
This input specifies the response to generate when
CONNECT_IN is asserted during a Connect Request.
A high on this input when CONNECT_IN is asserted
will generate an Accept response, i.e., the CONNECT
signal on the HIPPI channel will be asserted and will
remain asserted until a Disconnect Function is initiated
(CONNECT_IN is deasserted). A low on this input
when CONNECT_IN is asserted will generate a Reject
response, i.e., the CONNECT signal on the HIPPI
channel will be asserted for four cycles then fall and
remain deasserted until the response for the next
Connect Request is initiated. The ACCEPT_REJECT
signal needs to be valid only for the first cycle of the
asserted CONNECT_IN input.
Connection control is provided via the four signals in
the “Connect Control” area on the Host-side of the
Destination device. With this interface, the Host can
monitor when a Connect Request or Disconnect
Request comes in from the HIPPI Source, and then
initiate the appropriate action in response to the
request.
SOURCE_AVAILABLE (output) [SRCAV]
High indicates an active Source-to-Destination
INTERCONNECT signal while the Destination
device is in the on-line mode. Low indicates an
inactive Source-to-Destination INTERCONNECT
signal or the Destination device commanded to the
off-line or disabled mode.
Note: The host can have the Destination device
automatically respond to connection requests by
tying the CONNECT_REQUEST output to the
CONNECT_IN input. In this case, the ACCEPT/
REJECT signal would be used as an “available/busy”
signal. While ACCEPT/REJECT was held low all
connection requests would be rejected.
CONNECT_REQUEST (output) [CONRQ]
This signal indicates the state of the REQUEST signal
on the HIPPI channel. High indicates a Connect
Request function from the HIPPI channel, resulting
from an asserted REQUEST signal while the Desti-
nation device is in a functional operating mode with
Connect Requests enabled. Low indicates either a
false REQUEST signal on the HIPPI channel, a
disabled Connect Request at this device, or that the
Destination device is in a non-functional mode.
DATA/FIFO CONTROL
This interface provides control to the Destination
Host system over the flow of data transfers on the
HIPPI channel, and provides control of data transfer
from the Destination device into the Destination Host
system. It is intended for this interface to attach to an
external synchronous FIFO or DMA mechanism
which, in turn, attaches to the Destination Host
memory system. Recommended FIFO’s capable of
buffering 4 or more full Bursts are:
CONNECT_IN (input) [CONIN]
This signal controls the Connect Request and
Response functions of the Destination device on the
HIPPI channel. A low on this input will hold the
CONNECT signal on the HIPPI channel inactive, and
will enable the REQUEST signal from the HIPPI
channel to control the CONNECT_REQUEST output
of this Destination device.
IDT P/N 72225LB20 1K x 18 bits
IDT P/N 72235LB20 2K x 18 bits
IDT P/N 72245LB20 4K x 18 bits
During a Connect Request, asserting this input
initiates one of two responses to the Request;
Accept or Reject the Request. The desired response
is selected with the ACCEPT_REJECT input,
described next. If a Connect Request is accepted,
The signals of this interface can be divided into three
groups: Destination FLOW control, Destination FIFO
control, and HIPPI data control.
10
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Burst counter contents will result in that same
difference between the READY and Buffer counters.
When a subsequent HIPPI connection is accepted, the
Destination FLOW control circuit will automatically
send the correct number (equal to the number of
currently available buffers in the Destination Host) of
READY pulses.
DESTINATION FLOW CONTROL
After a HIPPI connection is established, data transfer
from the Source Host to the Destination Host is
enabled by the presence of data from the Source Host
and the current ability of the Destination Host to accept
that data. Although this function is performed at the
HIPPI Source, the HIPPI Destination signals its current
buffer capacity to the Source via the READY signal on
the HIPPI channel.
The Destination FLOW control signals are:
READY_IN (input) [RDYIN]
This input controls the Destination FLOW control
circuit’s Buffer and READY counters. A rising edge on
this input will increment the Buffer counter and, if a
Connect Request has been accepted, generate a
READY pulse on the HIPPI channel as well as
increment the READY counter by one. This input can
be driven by a free-running 12.5 MHz clock for
maximum throughput on the HIPPI channel (repre-
senting infinite Host buffer capacity), or it can be
controlled by the Host memory system. If controlled by
the Destination Host system, after initialization with one
edge for each available buffer, the Host may generate
one rising edge on this input after it processes and
releases each used 256 word buffer.
The Destination FLOW control circuit consists of a set
of modulo 64K counters that maintains the current
Buffer capacity, the number of READYs sent to the
HIPPI Source, and the number of Bursts received from
the HIPPI Source. At initialization (Destination device
reset) all of these counters are reset. When the
Source-to-Destination INTERCONNECT [SDIC] signal
is true and the Destination device is in a functional
mode, the Destination Host may initialize the Buffer
counter to the number of HIPPI Bursts that it can
accept. When a Connect Request is accepted, the
Destination device will automatically generate legal
READY pulses and increment the READY counter for
each pulse until the READY counter equals the Buffer
counter. If the Buffer counter was not initialized before
the Connect Request, then no READY pulses will be
generated. If the Buffer counter is incremented after
the Connection is made, then READY pulses will
automatically be generated until the READY and Buffer
counters are equal. The Buffer counter will be disabled
when it equals Burst count -1, thereby putting a limit of
64K on the number of pending READY pulses.
NOT_RESET_READY (input) [NRRDY]
This signal is an active low TTL input that erases the
stored count of available Host system buffers by
resetting the Buffer, Ready and Burst counters to
their initial states.
DESTINATION FIFO CONTROL
When a data Burst is received over the HIPPI
channel, the Destination FIFO Control provides the
signals necessary to transfer the received data from
the Destination device to the Destination Host FIFO
system. In addition to transferring received data
Bursts, the Destination device will also transfer the
HIPPI I-Field, and the channel and device status
words as specified in the FIFO Control Signal Table.
To provide flexibility at this interface, the Destination
device identifies each type of information presented
to the Destination Host, so that each implementation
may customize its use of the information.
If the Burst counter is not equal to the READY counter
as a data Burst is received, then the Burst counter is
incremented and the data is automatically transferred
to the Destination Host. If the Burst counter is equal to
the READY counter as a data Burst is received, then
the data is not transferred to the Destination Host and
an Overflow error is reported.
When the HIPPI connection is terminated, one of two
operations may be performed by the Destination Host:
the Destination FLOW control counters may be reset
(and initialized), or the current buffer capacity may be
automatically saved for the next HIPPI connection. To
reset and initialize, the Destination Host must maintain
a set of buffer counters, or empty the buffers before the
next connection. To automatically save the current
buffer capacity, the Destination device will initialize the
READY counter to the Burst counter: at the end of a
HIPPI connection, the number of remaining available
buffers at the Destination Host is the difference
between the Burst counter and the Buffer counter.
Therefore, initializing the READY counter to the
The Destination FIFO Control signals are:
WRITE_CLOCK (output) [WRCLK]
This signal is a buffered 25 MHz TTL clock
synchronized to the internal local clock. It is intended
for use with the VALID signal to transfer data to the
write port of the FIFO and to serve as the timing
reference for critical input and output control signals
of the Host-side of the Destination device.
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HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
HIPPI DATA CONTROL
SELECT_0, 1, 2 (bi-directional) [SELBx]
These signals are used in conjunction with the
MODE_SELECT inputs during manufacturing testing to
confirm the function of the internal counters and state
machines. In the functional mode [Mode value 5 (101)]
the value of the SELECT (SELECT_2 is MSB) bus
indicates the type of data available on the DOUT_0,31
signals. Select value 0 (000) indicates burst data on
the outputs. Select value 1 (001) indicates I-Field data
on the outputs. Select value 2 (010) indicates the LLRC
word, and Select value 3 (011) indicates internal status
data during inter-BURST wait states. When there is no
connection on the HIPPI channel, the select value will
sequence and repeat 5,6,7 (101, 110, 111) until
connection is requested. Select value 4 is reserved to
indicate sequence error status for advanced link
diagnostics. For most applications these latter values
can be ignored.
The data and control signals, received on the HIPPI
channel, are resynchronized to the 25_MHz local
clock, converted to TTL, and then presented to the
data and control interface used by the host.
The HIPPI data control signals are:
BURST_OUT (output) [BROUT]
This signal indicates the state of the BURST line on
the HIPPI channel. High indicates an active BURST
and is presented with each word of the received
burst. Low indicates an inactive BURST and is
presented when there is no received data.
PACKET_OUT (output) [PKOUT]
This signal indicates the state of the PACKET line on
the HIPPI channel. High indicates an active PACKET
and is presented as long as PACKET is active on the
HIPPI channel. Low indicates an inactive PACKET
and is presented as long as PACKET is inactive on
the HIPPI channel.
DATA_VALID (output) [DTVAL]
This signal is intended to be used together with the
SELECT_0,1,2 outputs to gate the clocking of received
data into the FIFO or register set selected by the select
lines. All received data will be presented to the data
outputs of the Destination device and will be
accompanied by a DATA_VALID signal.
Note: The BURST_OUT and PACKET_OUT signals
are provided to delimit the data into the FIFO the
same way it is delimited on the HIPPI channel.
These signals may not be needed by the Host.
FIFO Control Signal Table
SELB(2:0)
HOST data
HIPPI Burst
HIPPI I-Field
HIPPI LLRC
DATA_VALID
1 (high)
1 (high)
1 (high)
1 (high)
1 (high)
1 (high)
0 (low)
Comment
000
for duration of data received Burst
001
for duration of HIPPI Connect Request
010
one word, after last word of each Burst
one word, beginning each Packet received on channel (accomp. start of PACKET_OUT)
one word, end of each Burst, after LLRC*
011
gen. op. status
one word, end of each Packet (accompanies deactivation of PACKET_OUT)*
multiple words, while connection is estab. across channel, but channel has no data
011
100
gen. op. status
SEQUENCE
ERROR
one word, when a HIPPI sequence error is detected, or when an illegal signal sequence
disrupts the devices's state machines
1 (high)
1 (high)
1 (high)
1 (high)
one word, in sequence with FLOW status words (below), continuously while channel is
disconnected
101
110
111
idle/disab. status
FLOW status
word 1
one word, in sequence with FLOW status word 2 and idle/disab. status, continuously while
channel is disconnected
FLOW status
word 2
one word, in sequence with FLOW status word 1 and idle/disab. status, continuously while
channel is disconnected
*Only one general operational status word (Select code 011) will be presented if the BURST and PACKET terminations coincide, i.e., BURST deasserted,
followed by PACKET deasserted.
12
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HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
The Destination device counts the number of data
words it receives from the HIPPI channel and uses
this number as the “seed” for the LLRC it computes
and checks against the received LLRC word.
DATA AND PARITY
32_DATA_+_4_PARITY (outputs) [DTOxx, PAROx]
These signals reflect what was received on the data
and parity lines of the HIPPI channel, resynchronized
to local clock. During a connection request
(CONNECT_REQUEST going high and remaining
high) the I-field is presented on these signals. The
LLRC is also presented to this interface after the last
word of each burst.
SYNC_ERROR (output) [SYNER]
This signal high indicates the loss of synchronization
with the HIPPI channel (overrun or underrun).
CHIP STATUS/CONTROL
MODE_SELECT_0, 1, and 2 (inputs) [MSELx]
Note: All parity errors are indicated but no recovery
action is taken by the Destination device. If there is a
parity error detected, then the data and bad parity
are passed through the Destination device.
There are several operating modes in which the
Destination device can be placed. Operational and
diagnostic modes are controlled by the data placed
on the MODE_SELECT bus. MODE_SELECT_2 is
the MSB and MODE_SELECT_0 is the LSB of this
bus. Mode value 0 (000) is to be used as the master
reset mode for all internal counters and state
machines and should be used for power-up
initialization. Mode value 4 (100) is the board test or
diagnostic mode. In this mode an internal “walking
zero” pattern generator will exercise all Host-side
TTL outputs and the parity error circuitry. The
SELECT_0, 1, 2 outputs will count through all eight
states allowing exercise of any external I-Field or
status registers driven by the Destination device.
Mode value 5 (101) is the normal functional mode for
the Destination device.
RX_PARITY_ERROR (output) [RPERR]
High indicates a detected parity error on a data word
received over the HIPPI channel. This is valid for
each word received; however, there may be a time
skew between this indication and the presentation of
data. See Figure 9 for details. The bad parity bit(s) is
presented with its associated data word.
During a connection request the data lines contain the
I-field. RX_PARITY_ERROR indication presented to
the host logic when a connection has not been
established tells the host that an I- field parity error has
been detected. The RX_PARITY_ERROR signal is
valid for every clock that I-field is presented. Bad
parity on the I-field will result in the chip raising
RX_PARITY_ERROR until one of the following things
happen:
25_MHz (INPUT) [25MHZ]
This signal provides the Destination device with a
25MHz TTL clock (also called local clock) and is
used to resynchronize the HIPPI channel clock and
data.
• The I-field changes (stabilizes) so that the
parity is good
50_MHz (INPUT) [50MHZ]
• The host logic accepts or rejects the connection
request based on I-field content and the state
of RX_PARITY_ERROR
This signal provides the Destination device with a 50
MHz TTL clock and is used for internal state
machine control, and for resynchronization. The
phase requirements between this clock and 25_MHz
are shown in Figure 9.
• The HIPPI channel source drops REQUEST
RX_LLRC_ERROR (output) [RLLER]
This signal high means that an LLRC error was
detected on a received burst. This signal is
presented to the host along with the LLRC following
the last word of the burst.
13
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Absolute Maximum Ratings
ECL Supply Voltage VEE (V CC = 0)
–8.0VDC
GND to VEE
–50mA DC
7.0V
ECL Input Voltage (VCC = 0)
ECL Output Source Current (continuous)
TTL Supply Voltage VCC (V EE = 0)
TTL Input Voltage (VEE = 0)
5.5V
0°C to 70°C
Ambient
Operating Temperature
Operating Junction Temperature TJ
Storage Temperature
+130°C
–65° to +150°C
ECL 10K Input/Output DC
Recommended Operating Conditions
Characteristics VEE = –5.2V1
PARAMETER
MIN
NOM
MAX
UNITS
V
T
ambient
ECL Supply Voltage
–4.94
–5.2
–5.46
0°C
25°C
75°C
–650
UNIT
mV
mV
mV
mV
mV
mV
mV
mV
µA
(VEE
)
–770
–720
–1000
–1145
–1490
–1625
–1980
–2000
–0
–730
–680
–980
–1105
–1475
–1620
–1980
–2000
30
V
OHmax
IHmax
OHmin
TTL Supply Voltage
4.75
5.0
5.25
20
V
(VCC
TTL Output Current
Low (I OL
)
–600
–920
–1045
–1450
–1585
–1980
–2000
30
V
V
V
V
V
V
V
I
mA
)
IHmin
ILmax
OLmax
OLmin
ILmin
Ambient Temperature
Junction Temperature
0
70
°C
°C
<130
S2020 — ICC
— IEE
65
421
1530
91
589
mA
mA
mW
— POEF
inHmax
inLmax
S2021 — ICC
— IEE
125
307
90
174
429
mA
mA
mW
I
–.5
–.5
–.5
µA
— POEF
TTL Input/Output DC Characteristics
COMMERCIAL 0°/+70°C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN TYP
MAX
3
V
Input HIGH voltage
Input LOW voltage
Guaranteed input HIGH voltage for all inputs
Guaranteed input LOW voltage for all inputs
2.0
V
IH
3
V
V
V
0.8
V
V
V
IL
Input clamp diode voltage
Output HIGH voltage
–.8
–1.2
V
V
= Min, I = –18mA
IN
CC
CC
IK
2.7
3.4
= Min, I
= Min
= –1mA
OH
OH
I
I
= 8mA
0.5
0.5
V
V
OL
Output LOW voltage
V
OL
V
CC
= 20mA
OI
V
V
V
V
= Max, V = 2.7V
Input HIGH current
CC
CC
CC
IN
110
1
µΑ
mA
µΑ
I
I
I
I
IH
= Max, V = 5.25V
IN
Input HIGH current at Max.
Input LOW current
I
= Max, V = 0.5V
110
–100
IN
IL
OS
Output short circuit current
= Max, V = 0.5V
–25
mA
CC
IN
1. Data measured with VEE = –5.2 ± .1V assuming a +50°C rise between ambient (ta) and junction temperature (TJ) for 0°C, +25°C, and +70°C. Specification
will vary based upon TJ. These conditions will be met with an ambient 70°C airflow of 200 LFM.
2. Typical limits are at 25°C, VCC = 5.0V.
3. These input levels provide zero noise immunity and should only be tested in a static, noise-free environment.
14
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
225 PGA
15
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 8. S2020 Source Device Timing
t
period
t
t
MPW MPW
50 MHZ
t
t
HMS
SUMS
MODE SELECT (2:0)
1. Control Inputs:
t
PDRC
SHORT_BURST
PACKET_AVAILABLE
BURST_AVAILABLE
DATA_AVAILABLE
CONNECT_REQUEST
RDCLK
t
t
HCI
SUCI
1
Control Inputs
t
t
SUDP HDP
DATA PARITY INPUTS
2. Status &Control Outputs:
CONNECT_ OUT
t
SCO
2
Status & Control Outputs
ACCEPT_REJECT
ERROR
SOURCE_NOT_DEST
t
t
RNRN
NREN
NRDEN
t
IFNRN
IFLD (SHBST = 1, PKTAV = 0
t
INPUT_PARITY_ERROR
DESTINATION_AVAILABLE
DATA_REQUEST
IPE
t
DAO
t
DRO
BANRN
t
BURST_AVAIL.
and DATAV = 1
S2020 Source Timing Table
Min
nsec
Typ
nsec
Max
nsec
Notes
3
—
5.55
7
20
—
—
—
11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17
—
—
—
—
17
14
10
17
10
19
19
17
tPERIOD
3
tMPW
tSUMS
Relative to 50MHz INPUT
For Reference Only
0
tHMS
tPDRC
5
21
0
tSUCI
tHCI
tSUDP
tHDP
tSCO
14
0
—
—
—
—
—
—
—
—
4
tNREN
Relative to RDCLK Rising Edge
4
tIPE
4
tDAO
4
tDRO
4
tIFNRN
4
tRNRN
4
tBANRN
3. Guaranteed but not tested
16
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 9. S2021 Destination Device Timing
t
period
50_MHZ
(input)
t
t
MPW
MPW
t
t
H25
SU25
1. Control Outputs:
25_MHZ
(input)
PARITY_ERROR
LLRC_ERROR
CONNECT_REQUEST
PACKET_OUTLE
BURST_OUT
t
t
HMS
SUM
MSEL (2:0)
t
t
PWCR
PWCF
WRITE_CLOCK
(output)
t
PDP
2. Control Inputs:
CONNECT_ IN
ACCEPT/REJECT
READY_IN
32 DATA_ + _4 PARITY + SELB
(output)
t
PCO
Control Outputs1
t
PSAV
SOURCE_AVAILABLE, SYNC_ERROR
t
PDV
DATA_VALID
Control Inputs2
t
t
SUIC
HCI
I
t
M PW
READY_IN
(input)
t
RDYPER
t
HRRDY
N RSTRDY
t
SURRDY
S2021 Destination Timing Table
Min
Typ
Max
Notes
nsec
—
5.55
5
nsec
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
nsec
—
—
14
15
—
—
13
13
18
16
—
—
—
—
—
—
—
3
t
t
t
t
t
t
t
t
t
t
t
t
t
PERIOD
3
MPW
4
PWCF
4
5
PWCR
Relative to 50MHz Falling Edge
2
SU25
H25
2.5
—
—
—
—
9
4
PDP
4
PCO
4
PSAV
Relative to WRCLK Falling Edge
4
PDV
SUCI
HCI
0
3
3
RDYPER
SURRDY
40
8
t
t
t
Relative to WRCLK falling edge or RDYIN rising edge
3
8
HRRDY
SUM
HMS
5
t
5
3. Guaranteed but not tested
4. Assumes 5pf load for ECL and 15pf for TTL
17
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
SOURCE
1
2
3
4
5
6
7
P1
8
9
10
11
12
13
14
15
16
17
18
NC
NC
ND27
NC
D28
D29
ND31
D30
NP0
P2
P3
TPWR TGND PAR02 DAT31 DAT28 DAT25 DAT22 DAT19
U
T
D26
ND28
NC
ND29
D27
EGND
ND30
GND
P0
NP2
NP1
GND
NP3
–5.2V
–5.2V
TSTO* PAR03 PAR00 DAT30 DAT27 DAT24 DAT21
NC
DAT18
ND25
ND24
D22
D25
EGND
+5V
D31
GND
–5.2V PAR01 DAT29 DAT26 DAT23 DAT20
NC
DAT16 DAT15
S
R
P
N
M
L
D24
ND26
EGND
D23
+5V
–5.2V
GND
GND
GND
+5V
+5V
+5V
DAT17 DAT13 DAT12
DAT14 DAT10 DAT09
DAT11 DTREQ NRDEN
DATO0 RDCLK DSTAV
INPRR CNOUT ACREJ
ND23
D21
+5V
ND21
EGND
ND19
ND18
D17
GND
GND
GND
–5.2V
–5.2V
GND
GND
GND
+5V
GND
GND
GND
–5.2V
–5.2V
GND
GND
GND
+5V
D20
ND22
ND20
–5.2V
–5.2V
ND15
D13
BOTTOM VIEW
D19
D18
–5.2V
–5.2V
SDIC
SRNDS
K
J
ND17
ND16
D14
TGND SQERR
D16
DAT04 DAT06 DAT07
DAT00 DAT03 DAT05
SHBST DAT01 DAT02
MSEL2 BSTAV PKTAV
EGND CNREQ DATAV
H
G
F
D15
ND14 GTRO* ND12
ND13
D11
D12
ND11
ND10
NC
EGND
D09
NC
E
D
C
B
A
+5V
+5V
GND
D05
GND
ND04
D02
GND
ND02
D01
–5.2V
–5.2V
D00
-5.2V
–5.2V
NCLK
CLK
GND
NPKT
REQ
GND
THDI*
PKT
GND
VBB
+5V
+5V
D10
NC
ND08
D06
EGND
ND05
D04
RDY
CON
NC
MSEL0 MSEL1
ND09
NC
D07
D03
BRST
EGND EGND EGND
NC
50MHZ
NC
D08
ND07
ND06
ND03
EGND ND01
ND00
NREQ
EGND NBRST THDO*
DSIC
NRDY
NCON
*Indicates signal used for component testing—make no connection
HIPPI INTERCONNECT PAIR
DSIC = Destination to Source Interconnect
SDIC = Source to Destination Interconnect
EGND = TGND = GND = 0V
TPWR = +5V
18
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
DESTINATION
1
2
CON
NC
3
4
5
6
7
P2
8
9
10
11
12
D30
13
ND28
D28
14
D27
15
ND25
D25
16
ND24
D24
17
D23
NC
18
NC
NC
NREQ BRST
THDI* NBRST
CLK
PKT
REQ
+5V
NP3
P1
P0
ACCRJ
ND31
–5.2V
–5.2V
D31
U
T
NRDY
CONIN
NPKT
GND
P3
NP1
NP2
GND
NP0
–5.2V
–5.2V
ND30
ND29
GND
D29
ND26
NRRDY
ND21
D20
TGND THDO*
SELB1 SELB0
NC
NCON
+5V
NCLK
GND
ND27
GND
D26
RDYIN ND23
NC
D22
ND20
D19
S
R
P
N
M
L
RDY
GND
+5V
+5V
+5V
ND22
D21
25MHZ 50MHZ TPWR
+5V
ND18
ND17
D16
DTO00 DSIC
SELB2
GND
GND
GND
–5.2V
–5.2V
GND
GND
GND
+5V
GND
GND
GND
–5.2V
–5.2V
GND
GND
GND
+5V
ND19 MSEL2
DTO03 DTO01 DTVAL
DTO05 DTO04 DTO02
DTO07 DTO06 –5.2V
DTO08 DTO09 –5.2V
TPWR TGND DTO11
DTO10 DTO12 DTO15
DTO13 DTO14 DTO18
DTO16 DTO17 DTO21
DTO19 DTO20 DTO22
D18
D17
BOTTOM VIEW
ND16
–5.2V
–5.2V
ND11
ND09
D08
ND15
ND14
D15
D14
K
J
ND13 MSEL1
ND12
D11
D13
D12
H
G
F
D10
ND10
D09
NC
MSEL0 ND08
E
D
C
B
A
+5V
+5V
GND
GND
GND
–5.2V
–5.2V
–5.2V
GND
GND
D00
GND
ND01
VBB
+5V
SDIC
D01
+5V
ND05
NC
D07
D06
NC
ND07
ND06
D05
TPWR TGND
NC
DTO25 DTO28 TGND PARO0 RPERR –5.2V
SSO1*
D04
DTO23
NC
NC
DTO26 DTO29 DTO30 PARO1 PARO3 SRCAV CONRQ PKOUT TGND SSO2*
ND02
D02
ND03
D03
DTO24 DTO27 TPWR DTO31 PARO2 SYNER BROUT WRCLK RLLER TPWR SSO0* SSEN* ND00
ND04
NC
*Indicates signal used for component testing only
— Connect SSEN to GROUND (0V)
— Make no connection to other pins mark with asterisk (*)
HIPPI INTERCONNECT PAIR
DSIC = Destination to Source Interconnect
SDIC = Source to Destination Interconnect
EGND = TGND = GND = 0V
TPWR = +5V
19
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
PIN NO. NAME
PIN NO. NAME
PIN NO. NAME
PIN NO. NAME
1
GND
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
GND
+5V
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
GND
GND
ND09
D09
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
GND
2
GND
+5V
3
DAT18
DAT17
DAT16
DAT15
DAT14
DAT13
DAT12
DAT11
DAT10
DAT09
DAT08
–5.2V
NCON
CON
EGND
NRDY
RDY
ND27
D27
4
5
ND10
D10
ND28
D28
6
7
EGND
ND11
D11
EGND
ND29
D29
8
EGND
DSIC
VBB
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
ND12
D12
ND30
D30
EGND
–5.2V
–5.2V
GND
GND
BRST
NBRST
PKT
ND13
D13
ND31
D31
–5.2V
–5.2V
GND
GND
ND14
D14
–5.2V
–5.2V
GND
–5.2V
GND
GND
GND
DTREQ
NRDEN
RDCLK
INPRR
DSTAV
CNOUT
ACREJ
SDIC
NP0
NPKT
EGND
REQ
NREQ
NCLK
CLK
P0
ND15
D15
NP1
P1
ND16
D16
NP2
P2
ND17
D17
NP3
GND
GND
+5V
P3
SRNDS
GND
GND
GND
+5V
GND
GND
GND
ND00
D00
+5V
+5V
ND18
D18
TST0
TGND
PAR03
PAR02
PAR01
PAR00
DAT31
DAT30
GND
SQERR
DAT07
DAT06
DAT05
DAT04
DAT03
DAT02
DAT01
–5.2V
ND01
D01
ND19
D19
GND
ND02
D02
EGND
ND20
D20
ND03
D03
ND21
D21
GND
GND
–5.2V
–5.2V
ND04
D04
–5.2V
–5.2V
GND
GND
ND22
D22
GND
–5.2V
–5.2V
–5.2V
DAT29
DAT28
DAT27
DAT26
DAT25
DAT24
DAT23
DAT22
DAT21
DAT20
DAT19
+5V
GND
GND
DAT00
PKTAV
BSTAV
SHBST
DATAV
CNREQ
MSEL2
MSEL1
MSEL0
50MHZ
GND
ND05
D05
ND23
D23
ND06
D06
ND24
D24
EGND
ND07
D07
ND25
D25
ND08
D08
ND26
D26
+5V
GND
EGND = TGND = GND = 0V;
TPWR = +5V
20
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
PIN NO. NAME
PIN NO. NAME
PIN NO. NAME
PIN NO. NAME
1
NRRDY
ND22
D22
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
GND
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
GND
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
NCON
2
+5V
DTO23
DTO22
DTO21
DTO20
DTO19
DTO18
DTO17
DTO16
DTO15
–5.2V
–5.2V
GND
NREQ
REQ
NBRST
BRST
NPKT
PKT
3
ND04
D04
4
ND21
D21
5
ND03
D03
6
ND20
D20
7
SDIC
8
ND19
D19
ND02
D02
CLK
9
NCLK
–5.2V
–5.2V
GND
GND
CONIN
NP3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
ND18
D18
ND01
D01
–5.2V
–5.2V
GND
GND
MSEL2
ND17
D17
ND00
D00
–5.2V
–5.2V
GND
GND
DTO14
DTO13
DTO12
DTO11
DTO10
TGND
DTO09
DTO08
GND
P3
GND
NP2
VBB
P2
ND16
D16
SSEN
SSO2
SSO1
SSO0
PKOUT
RLLER
GND
NP1
P1
ND15
D15
NP0
P0
ND14
D14
GND
GND
+5V
GND
GND
GND
+5V
+5V
GND
DTO07
DTO06
DTO05
DTO04
DTO03
DTO02
DTO01
DTO00
DSIC
ACCRJ
ND31
D31
+5V
MSEL1
ND13
D13
WRCLK
CONRQ
BROUT
SRCAV
SYNER
RPERR
PARO3
PARO2
PARO1
GND
ND30
D30
ND12
D12
ND29
D29
ND11
D11
ND28
D28
ND10
D10
–5.2V
–5.2V
GND
GND
GND
–5.2V
–5.2V
ND27
D27
–5.2V
–5.2V
GND
GND
ND09
D09
GND
GND
–5.2V
–5.2V
PARO0
DTO31
DTO30
TGND
DTO29
DTO28
DTO27
DTO26
DTO25
DTO24
+5V
DTVAL
25MHZ
50MHZ
SELB2
SELB1
SELB0
TPWR
TGND
RDY
ND26
D26
ND08
D08
ND25
D25
ND07
D07
RDYIN
ND24
D24
MSEL0
ND06
D06
NRDY
GND
ND23
D23
ND05
D05
GND
+5V
+5V
GND
GND
GND
GND
CON
EGND = TGND = GND = 0V;
TPWR = +5V
21
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Figure 10. Interconnect (output) Network
From Interconnect Output
To HIPPI Cable
Interconnect Signal
(K–17, SDIC OF S2020
N–2 DSIC OF S2021
+5V
VCC
220 Ohm
2%
10K
5%
2N3905
PNP or
Equivalent
N-CHANNEL MOSFET
W/R ON < 5 Ohm
VGS = 5V e.g.
VN0300L, MFE990
5%
2.2K
5%
2.2K
GND
VEE -5.2V
Figure 11. Interconnect (input) Network
Silicon
Junction Diodes*
100Ω 5%
From HIPPI Cable
Interconnect Signal
To Interconnect Input
(A-15, DSIC of S2020
C-14, SDIC of S2021)
220Ω
5%
.01µ Fd
VBB
(C-13 of S2020
B-13 of S2021)
GND
GND
330 to
500Ω
*IN914 or IN4148
VEE -5.2
ORDERING INFORMATION
GRADE
FUNCTION
PACKAGE
2020 — Hippi Source
2021 — Hippi Destination
2022 — Hippi Evaluation Kit
(contains 2 source and 2
destination parts)
A = 225 PGA
B = 208 TEP
S-Commercial
X XXXX X
22
S2020/S2021
HIPPI SOURCE/DESTINATION INTERFACE CIRCUITS
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 • (800)755-2622 • Fax: (619) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1995 Applied Micro Circuits Corporation
August 16, 1995
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