S3006D-6 [AMCC]
TRANSCEIVER, PQFP80, HEAT SINK, PLASTIC, QFP-80;
| 型号： | S3006D-6 |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | TRANSCEIVER, PQFP80, HEAT SINK, PLASTIC, QFP-80 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总28页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DEVICE SPECIFICATION
S3005/S3006
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
GENERAL DESCRIPTION
FEATURES
• Complies with ANSI, Bellcore, and ITU-T
specifications
• On-chip high-frequency PLL for clock
generation and clock recovery
The S3005/S3006 Synchronous Electrical Transmit
Interface, SETI, and Synchronous Electrical Receive
Interface, SERI, SONET/SDH and E4 transmitter
and receiver chips are the first fully integrated serial-
ization/deserialization interface devices covering E4
(139.264 Mbit/s), SONET OC-3 (155.52 Mbit/s) and
SONET OC-12 (622.08 Mbit/s). With architecture de-
veloped by PMC-Sierra, the chipset performs all
necessary serial-to-parallel and parallel-to-serial
functions in conformance with SONET/SDH and E4
transmissions standards. Figure 1 shows a typical
network application.
• Supports 139.264 Mbit/s (E4), 155.52 Mbit/s
(OC-3), and 622.08 Mbit/s (OC-12)
transmission rates
• Supports 139.264 Mbit/s and 155.52 Mbit/s
Code Mark Inversion (CMI) interfaces
• Selectable reference frequencies of 19.44,
38.88, 51.84, and 77.76 MHz (OC-3/12) and
17.408, 34.816, 46.421, and 69.632 MHz(E4)
• Interface to both ECL and TTL logic
• 8-bit TTL/CMOS datapath
• Bypass mode for off-chip clocking
• Local and line loopback mode
• Lock detect
• Low jitter ECL interface
• Low power
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3005 SETI
transmitter chip allowing the use of a slower external
transmit clock reference. Clock recovery is per-
formed on the S3006 SERI receiver chip by
synchronizing its on-chip VCO directly to the incom-
ing data stream. The S3006 also performs SONET/
SDH frame detection. The chipset can be used with
19.44, 38.88, 51.84, and 77.76 MHz reference
clocks when operated in the SONET/SDH OC-3 or
OC-12 modes. In the E4 mode the chipset can be
operated with 17.408, 34.816, and 69.632 MHz ref-
erence clocks in support of existing system clocking
schemes. On-chip code-mark-inversion (CMI) encod-
ing and decoding is provided for 139.264 Mbit/s and
155.52 Mbit/s interfaces. If desired, both clock gen-
eration and recovery can be bypassed, allowing the
use of externally generated and recovered clocks.
• 80 PQFP or 68 LDCC package
APPLICATIONS
• SONET/SDH or E4-based transmission systems
• SONET/SDH or E4 modules
• SONET/SDH or E4 test equipment
• ATM over SONET
• Section repeaters
• Add drop multiplexors
• Broadband cross-connects
• Fiber optic terminators
The very low jitter ECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore, ANSI, and ITU-T standards. The S3005/
S3006 SETI and SERI chipset is packaged in a 50
mil pitch, 68-pin LDCC or 25 mil pitch, 80 PQFP
package, offering designers a small package outline.
• Fiber optic test equipment
Figure 1. System Block Diagram
S3005
SONET/SDH
Transmitter
(SETI)
Transmit
Overhead
Processor
8
8
Receive
Overhead
Processor
S3006
SONET/SDH
Receiver
(SERI)
OTX
ORX
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
1
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Figure 2. SONET Structure
SONET OVERVIEW
Functions
Layer Overhead
(Embedded Ops
Channel)
Synchronous Optical Network (SONET) is a stan-
dard for connecting one fiber system to another at
the optical level. SONET, together with the Synchro-
nous Digital Hierarchy (SDH) administered by the
ITU-T, forms a single international standard for fiber
interconnect between telephone networks of differ-
ent countries. SONET is capable of accommodating
a variety of transmission rates and applications.
Payload to
SPE mapping
Path layer
Line layer
Path layer
Maintenance,
protection,
switching
576 Kbps
192 Kbps
0 bps
Line layer
Section layer
Photonic layer
Scrambling,
framing
Section layer
Photonic layer
The SONET standard is a layered protocol with four
separate layers defined. These are:
Optical
transmission
• Photonic
• Section
• Line
Fiber Cable
End Equipment
End Equipment
• Path
Figure 2 shows the layers and their functions. Each
of the layers has overhead bandwidth dedicated to
administration and maintenance. The photonic layer
simply handles the conversion from electrical to optical
and back with no overhead. It is responsible for
transmitting the electrical signals in optical form over the
physical media. The section layer handles the transport
of the framed electrical signals across the optical
cable from one end to the next. Key functions of this
layer are framing, scrambling, and error monitoring.
The line layer is responsible for the reliable transmis-
sion of the path layer information stream carrying
voice, data, and video signals. Its main functions are
synchronization, multiplexing, and reliable transport.
The path layer is responsible for the actual transport
of services at the appropriate signaling rates.
Table 1. SONET Signal Hierarchy
Data Rate
(Mbit/s)
Elec.
ITU-T
Optical
STS-1
OC-1
51.84
STS-3
STM-1
STM-4
OC-3
155.52
466.56
622.08
933.12
1244.16
1866.24
2488.32
STS-9
OC-9
STS-12
STS-18
STS-24
STS-36
STS-48
OC-12
OC-18
OC-24
OC-36
OC-48
STM-16
Data Rates and Signal Hierarchy
Table 1 contains the data rates and signal designations
of the SONET hierarchy. The lowest level is the basic
SONET signal referred to as the synchronous transport
signal level-1 (STS-1). An STS-N signal is made up of
N byte-interleaved STS-1 signals. The optical counter-
part of each STS-N signal is an optical carrier level-N
signal (OC-N). The S3005/S3006 chipset supports OC-3
rates (155.52 Mbit/s) and OC-12 (622.08 Mbit/s) rates.
Figure 3. STS–3/OC–3 Frame Format
A1
B1
D1
H1
B2
D4
D7
D10
Z1
A1
*
A1
*
A2
E1
D2
H2
K1
D5
D8
D11
Z2
A2
*
A2
*
C1
F1
C1
*
C1
*
*
*
*
*
D3
H3
K2
D6
D9
D12
E2
*
*
9 x 261 =
2349 bytes
H1
B2
*
H1
B2
*
H2
*
H2
*
H3
*
H3
*
9
Rows
*
*
*
*
*
*
*
*
*
*
Frame and Byte Boundary Detection
*
*
*
*
*
*
The SONET/SDH fundamental frame format for STS-3
consists of nine transport overhead bytes followed by
Synchronous Payload Envelope (SPE) bytes. This
pattern of 9 overhead and 261 SPE bytes is repeated
nine times in each frame. Frame and byte boundaries
are detected using the A1 and A2 bytes found in the
transport overhead. (See Figure 3)
Z1
Z1
Z2
Z2
*
*
Transport Overhead
9 Columns
Synchronous Payload
Envelope
261 Columns
125 µsec
For more details on SONET operations, refer to the
ANSI SONET standard document.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Receiver
S3005/S3006 OVERVIEW
1. Clock and data recovery from serial input
2. CMI decoding (optional)
3. Frame detection
4. Serial-to-parallel conversion
5. 8-bit parallel output
The S3005 SETI and S3006 SERI implement
SONET/SDH serialization/deserialization, transmission,
and frame detection/recovery functions. The block
diagrams in Figures 4 and 5 show basic operation of
both chips. These chips can be used to implement the
front end of SONET equipment, which consists primarily
of the serial transmit interface (S3005) and the serial
receive interface (S3006). The chipset handles all
the functions of these two elements, including paral-
lel-to-serial and serial-to-parallel conversion, clock
generation and recovery, and system timing, which
includes management of the datastream, framing, and
clock distribution throughout the front end.
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 10 through 18. On-chip clock generation can
be bypassed and an externally generated clock used
in its place, providing an additional measure of
design flexibility.
A lock detect feature is provided on both chips.
Suggested Interface Devices
Operation of the S3005/S3006 chips is straightfor-
ward. The sequence of operations is as follows:
PMC PM5345
PMC PM5355
IGT WAC–013–A
SUNI
Saturn User Network Interface
Saturn User Network Interface
SONET LAN ATM Processor
Network Termination Controller
Section Terminating Transceiver
Transport Terminating Transceiver
SUNI-622
Transmitter
1. 8-bit parallel input
Fujitsu MB86683B NTC
2. Parallel-to-serial conversion
3. CMI encoding (optional)
4. Serial output
PMC PM5301
PMC PM5312
SSTX
STTX
AT&T ASTROTEC1227/1230
Mitsubishi MF-622DF-T12-XXX 622 Mbit/s
AT&T ASTROTEC 1310 650 Mbit/s
Mitsubishi MF-622DS-R1X-XXX 622 Mbit/s
650 Mbit/s
Fiber Optic Transmitter
Fiber Optic Transmitter
Fiber Optic Receiver
Fiber Optic Receiver
Figure 4. SONET/SDH Transmitter Functional Block Diagram
DLEB
LLEB
2
LLDP/N
2
DLDP/N
LLCLKP/N
2
2
8
D
TSDP/N
PIN[7:0]
8:1 PARALLEL
TO SERIAL
CMI
PICLK
DLCV
LOAD
TSCLKP/N
PCLK
PAE
TIMING
GEN
SYNC
BYTCLKIP
TESTEN
CLOCK
SYNTHESIZER
3
2
2
MODE[2:0]
REFSEL[1:0]
REFCLKP/N
RSTB
LOCKDET
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
For applications that provide a high-frequency bit
clock externally, the internal synthesizer may be by-
passed. Reference frequencies of 19.44 MHz, 38.88
MHz, 51.84 MHz, or 77.76 MHz are selectable for
SONET/SDH by the two reference select input pins.
In E4 applications, these same pins can select the
reference frequency from 17.408 MHz, 34.816 MHz,
46.421 MHz, or 69.632 MHz.
S3005 TRANSMITTER FUNCTIONAL
DESCRIPTION
The S3005 SETI transmitter chip performs the serial-
izing stage in the processing of a transmit SONET
STS-12, STS-3, or ITU-T E4 bit serial data stream. It
converts the byte serial data stream to bit serial for-
mat at 622.08, 155.52, or 139.264 Mbit/s depending
on the control settings and reference frequency pro-
vided by the user. A Coded-Mark-Inversion (CMI) is
available for use during 155.52 Mbit/s STS-3 (electri-
cal) and 139.264 Mbit/s E4 operational modes. (See
Other Operating Modes.)
Loopback modes are provided for diagnostic
loopback (transmitter to receiver), or line loopback
(receiver to transmitter) when used with the compat-
ible S3006. (See Other Operating Modes.)
The operating mode is selected by three mode pro-
gramming inputs to be 622.08 Mbit/s, 155.52 Mbit/s,
155.52 Mbit/s with Coded-Mark-Inversion (CMI) en-
coding, or 139.264 Mbit/s with CMI encoding.
A high-frequency bit clock can be generated from a
variety of lower frequency references by using the
integral frequency synthesizer consisting of a phase-
locked loop circuit with an adjustable divider in the loop.
Figure 5. SONET/SDH Receiver Functional Block Diagram
LCV
LOS
8
C
M
I
1:8 SERIAL
POUT[7:0]
TO PARALLEL
TIMING
GEN
OOF
POCLK
FP
FRAME
BYTE
DETECT
DLEB
2
2
M
U
X
RSDP/N
DLDP/N
BACKUP
REFERENCE
GEN
BYTCLKIP
2
2
2
REFCLKP/N
REFSEL[1:0]
MODE[2:0]
LLDP/N
CLOCK
RECOVERY
2
3
LLCLKP/N
LOCKDET
TESTEN
RSTB
TESTRST
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6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Clock Synthesizer
Timing Generator
The Timing Generator function, seen in Figure 4, pro-
vides two separate functions. It provides a byte rate
version of the TSCLK, and a mechanism for aligning
the phase between the incoming byte clock and the
clock which loads the parallel-to-serial shift register.
The Clock Synthesizer, shown in the block diagram
in Figure 4, is a monolithic PLL that generates the
serial output clock phase synchronized with the input
reference clock (REFCLK). There are three select-
able output clock frequencies that are synthesizable
from any of four selectable reference frequencies for
SONET/SDH operation.
The PCLK output is a byte rate version of TSCLK.
For STS-12, the PCLK frequency is 77.76 MHz, and
for NRZ or CMI coded STS-3, its frequency is 19.44
MHz. For CMI coded E4, its frequency is 17.408
MHz. PCLK is intended for use as a byte speed clock
for upstream multiplexing and overhead processing
circuits. Using PCLK for upstream circuits will ensure
a stable frequency and phase relationship between
the data coming into and leaving the S3005 device.
The MODE[2:0] inputs select the output serial clock
frequency to be 622.08 MHz for STS-12, 311.04
MHz for CMI-encoded STS-3, 155.52 MHz for STS-
3, or 278.528 MHz for CMI-encoded E4. Their
frequencies are selected as shown in Table 2.
The REFSEL[1:0] inputs in combination with the
MODE[2:0] inputs select the ratio between the out-
put clock frequency and the reference input
frequency, as shown in Tables 3 and 4. This ratio is
adjusted for each of the four modes so that the refer-
ence frequency selected by the REFSEL[1:0] is the
same for all modes.
Table 3. Reference Frequency Options
REFSEL
[1:0]
REFERENCE CLOCK
FREQUENCY
19.44 MHz
OPERATING
MODE
STS–12,STS–3
00
01
10
11
38.88 MHz
51.84 MHz
77.76 MHz
STS–12,STS–3
STS–12,STS–3
STS–12
The REFCLK input must be generated from a differ-
ential ECL crystal oscillator which has a frequency
accuracy of better than 20 ppm in order for the
TSCLK frequency to have the same accuracy re-
quired for operation in a SONET system.
Table 4. E4CMI Reference Frequency Options
In order to meet the .01 UI SONET jitter specifications,
the maximum reference clock jitter must be guaran-
teed over the 12KHz to 1MHz bandwidth. For details
of reference clock jitter requirements, see Table 5.
REFSEL
[1:0]
REFERENCE CLOCK
FREQUENCY
OPERATING
MODE
—
00
17.408 MHz
01
10
11
34.816 MHz
46.421 MHz
69.632 MHz
—
—
—
The on–chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLK input, a loop filter which
converts the phase detector output into a smooth DC
voltage, and a VCO, whose frequency is varied by
this voltage.
Table 5. Reference Jitter Limits
The loop filter generates a VCO control voltage based
on the average DC level of the phase discriminator
output pulses. The loop filter’s corner frequency is
optimized to minimize output phase jitter. The loop
filter capacitor is included on the package.
Maximum Reference Clock Jitter
in 12 KHz to 1 MHz Band
Operating
Mode
14 ps
28 ps
56 ps
STS–12
STS–3 CMI
STS–3
Table 2. Clock Frequency Options
OUTPUT CLOCK
FREQUENCY
OPERATING
MODE
MODE[2:0]
100
001
010
011
622.08 MHz
311.04 MHz
155.52 MHz
278.528 MHz
STS–12
STS–3 CMI
STS–3
E4 CMI
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
In the parallel-to-serial conversion process, the in-
coming data is passed from the PICLK byte clock
timing domain to the internally generated byte clock
timing domain, which is phase aligned to TSCLK.
Although the frequency of PICLK and the internally
generated byte clock is the same, their phase rela-
tionship is arbitrary. To prevent errors caused by
short setup or hold times between the two timing
domains, the timing generator circuitry monitors the
phase relationship between PICLK and the internally
generated byte clock. Should the magnitude of the
phase difference be less than one bit period, and if
the SYNC input is high, the timing block inverts the
internal byte clock.
S3006 RECEIVER FUNCTIONAL
DESCRIPTION
The S3006 SERI receiver chip provides the first
stage of digital processing of a receive SONET STS-
12, STS-3, or ITU-T E4 bit serial stream. It converts
the bit-serial 622.08, 155.52, or 139.264 Mbit/s data
stream into 78 Mbyte/s, 19 Mbyte/s, or 17 Mbyte/s
byte-serial data format depending on the control set-
tings and reference frequency provided by the user.
A Coded Mark Inversion (CMI) decoder can be en-
abled during 155.52 Mbit/s and 139.264 Mbit/s
operation for decoding STS-3 electrical and E4 sig-
nals. These modes are selected by three input pins.
Clock recovery is performed on the incoming
scrambled NRZ or CMI–coded data stream. A refer-
ence clock is required for phase locked loop start-up
and proper operation under loss of signal conditions.
An integral prescaler and phase locked loop circuit is
used to multiply this reference frequency to the
nominal bit rate. Reference frequencies of 19.44
MHz, 38.88 MHz, 51.84 MHz, or 77.76 MHz are se-
lectable for SONET/SDH by the two reference select
input pins. In E4 applications, these same pins can
select the reference frequency from 17.408 MHz,
34.816 MHz, 46.421 MHz, or 69.632 MHz. For appli-
cations that provide a high-frequency bit clock
externally, the internal synthesizer may be by-
passed. (See Other Operating Modes.)
Since the inversion of the internal byte clock will cor-
rupt one byte of data, SYNC should be held low
except when a phase correction is desired. When a
timing domain phase difference of less than one bit
period is detected, the Phase Alignment Event out-
put (PAE) pulses high for one PCLK clock period. If
the condition persists, PAE will remain high. When
PAE conditions occur, SYNC should be activated un-
til the condition is no longer present.
The Timing Generator also produces a feedback ref-
erence clock to the Clock Synthesizer (BYTCLKIP).
A counter divides the synthesized clock down to the
same frequency as the reference clock REFCLK.
The PLL in the Clock Synthesizer maintains the sta-
bility of the synthesized clock by comparing the
phase of the BYTCLKIP clock with that of the refer-
ence clock (REFCLK). The modulus of the counter is
a function of the reference clock frequency and the
operating frequency.
A loopback mode is provided for diagnostic loopback
(transmitter to receiver). Signal pins are provided to
allow for line loopback (receiver to transmitter) when
used with the compatible S3005 device.
Clock Recovery
Parallel-to-Serial Converter
The Clock Recovery function, as shown in the block
diagram in Figure 5, generates a clock that is fre-
quency matched to the incoming data baud rate at
the RSD or DLD differential inputs. The clock is
phase aligned by a PLL so that it samples the data
in the center of the data eye pattern.
The Parallel-to-Serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first regis-
ter latches the data from the PIN[7:0] bus on the
rising edge of PICLK. The second register is a paral-
lel loadable shift register which takes its parallel
input from the first register.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared
by a phase/frequency discriminator. Output pulses
from the discriminator indicate the required direction
of phase corrections. These pulses are smoothed by
an integral loop filter. The output of the loop filter
controls the frequency of the Voltage Controlled Os-
cillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) to
which the PLL locks when data is lost.
An internally generated byte clock, which is phase
aligned to the transmit serial clock as described in
the Timing Generator description, activates the par-
allel data transfer between registers. In STS-12 and
STS-3 NRZ modes, the serial data is shifted out of
the second register at the TSCLK rate. In STS–3
CMI and E4 CMI modes, the serial data shifts out at
the TSCLK/2 rate to the CMI encoder.
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6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Backup Reference Generator
The MODE[2:0] inputs select the recovered serial
clock frequency to be 622.08 MHz for STS-12,
311.04 MHz for CMI-encoded STS-3, 278.528 MHz
for CMI-encoded E4, or 155.52 MHz for STS-3 NRZ.
These frequencies are selected as shown in Table 2.
The Backup Reference Generator seen in Figure 5
provides backup reference clock signals to the clock
recovery block when the clock recovery block de-
tects a loss of signal condition. It contains a counter
that divides the clock output from the clock recovery
block down to the same frequency as the reference
clock REFCLK. The modulus of the counter is a
function of the reference clock frequency and the
operating frequency. The frequency of the reference
clock is selected by the REFSEL[1:0] inputs, as
shown in Tables 3 and 4.
The clock recovery circuit monitors the incoming
data stream for loss of signal. If the incoming en-
coded data stream has been low continuously for
4000 to 8000 recovered clock cycles, loss of signal
is declared and the PLL will switch from locking onto
the incoming data to locking onto the reference
clock. Alternatively, the loss-of-signal (LOS) input
can be used to force a loss-of-signal condition.
When active, LOS squelches the incoming data
stream, and causes the PLL to switch its source of
reference. Loss-of-signal condition is removed when
LOS is inactive, and good data, with acceptable
pulse density and run length, returns on the incoming
data stream.
Frame and Byte Boundary Detection
The Frame and Byte Boundary Detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. This pattern occurs in both STS-3 and STS-12.
Framing pattern detection is enabled and disabled
by the out-of-frame (OOF) input. Detection is enabled
by a rising edge on OOF, and remains enabled for
the duration OOF is set high. It is disabled when a
framing pattern is detected and OOF is no longer set
high. When framing pattern detection is enabled, the
framing pattern is used to locate byte and frame
boundaries in the incoming data stream (RSD or
DLD). The timing generator block takes the located
byte boundary and uses it to block the incoming data
stream into bytes for output on the parallel output
data bus (POUT[7:0]). The frame boundary is re-
ported on the frame pulse (FP) output when any
48-bit pattern matching the framing pattern is de-
tected on the incoming data stream. When framing
pattern detection is disabled, the byte boundary is
frozen to the location found when detection was pre-
viously enabled. Only framing patterns aligned to the
fixed byte boundary are indicated on the FP output.
When the test clock enable (TESTEN) input is set
high, the clock recovery block is disabled. The reference
clock (REFCLK) is used as the bit rate clock input in
place of the recovered clock. The frequency of the
REFCLK should be appropriate for the desired data
rate. The reference selection inputs REFSEL[1:0]
have no effect when TESTEN is set high.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET data
signal. This transfer function yields a typical capture
time of 32 µs for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which meets, with ample margin,
the minimum tolerance proposed for SONET equipment
by the T1X1.6/91-022 document, shown in Figure 6.
Figure 6. Clock Recovery Jitter Tolerance
The probability that random data in an STS-3 or
STS-12 stream will generate the 48-bit framing pattern
is extremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. Therefore,
the time to match the first frame pattern and to verify it
with down-stream circuitry, at the next occurrence of
the pattern, is expected to be less than the required
250 µs, even for extremely high bit error rates.
Sinusodal
Input Jitter
Amplitude
15
(UI p-p)
1.5
0.15
Once down-stream overhead circuitry has verified that
frame and byte synchronization are correct, the OOF
input can be set low to disable the frame search process
from trying to synchronize to a mimic frame pattern.
f0
f2
f2
f3
f3
ft
f1
OC/STS
Level
f0
(Hz)
f1
ft
(Hz)
(Hz) (kHz) (kHz)
3
10
10
30
300
300
6.5
25
75
12
30
250
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
The Frame and Byte boundary Detection function is
not utilized in the E4 operating mode. It is recom-
mended that the OOF input remain low at all times
for E4 operation to avoid spurious realignment of the
byte boundary, and the FP output should be ignored.
OTHER OPERATING MODES
CMI Encoding and Decoding
Coded Mark Inversion format (CMI) ensures at least
one data transition per bit period, thus aiding the
clock recovery process. Zeros are represented by a
Low state for one half a bit period, followed by a
High state for the rest of that bit period. Ones are
represented by a steady Low or High state for a full
bit period. The state of the ones bit period alter-
nates at each occurrence of a one. Figure 7 shows
an example of CMI-encoded data. The STS-3 elec-
trical interface and the E4 interface are specified to
have CMI-encoded data.
Serial to Parallel Converter
The Serial to Parallel Converter consists of three
8-bit registers. The first is a serial-in, parallel-out
shift register, which performs serial to parallel con-
version clocked by the clock generated by the clock
recovery block. The second is an 8-bit internal hold-
ing register, which transfers data from the serial to
parallel register on byte boundaries as determined
by the frame and byte boundary detection block. On
the falling edge of the free running POCLK, the data
in the holding register is transferred to an output
holding register which drives POUT[7:0].
The CMI encoder on the S3005 SETI accepts serial
data from the Parallel-to-Serial converter block at
one half the TSCLK rate. The data is then encoded
into CMI format, and the result is shifted out into the
output selection logic at the TSCLK rate (311.04
MHz for STS-3 electrical, 278.528 MHz for E4). The
MODE[2:0] inputs control whether the CMI encoder
is in the data path. The encoder is only in the data
path when the STS-3 CMI or the E4 CMI modes are
selected. A single CMI violation can be inserted for
diagnostic purposes by applying a low-to-high tran-
sition on DLCV. This violation is either an inverted
zero code or an inversion of the alternating ones
logic level, depending on the state of the data. Sub-
sequent one codes take into account the induced
violation to avoid error multiplication.
The delay through the Serial to Parallel converter can
vary from 1.5 to 2.5 byte periods (12 to 20 serial bit
periods) measured from the first bit of an incoming
byte to the beginning of the parallel output of that byte.
The variation in the delay is dependent on the alignment
of the internal parallel load timing, which is synchro-
nized to the data byte boundaries, with respect to
the falling edge of POCLK, which is independent of
the byte boundaries. The advantage of this serial to
parallel converter is that POCLK is neither truncated
nor extended during reframe sequences.
Figure 7. CMI Encoded Data
Figure 8. Loopback Diagram
Data In
0
0
1
0
1
1
1
0
Data Out
Control
S3006
S3005
CLK
A2
A1
t
S3006
S3005
Data Out
CLK
Data In
Control
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Line Loopback
The CMI decoder block on the S3006 SERI accepts
serial data from the RSDP/N input at the TSCLK rate
(311.04 MHz or 278.528 MHz). The data is then de-
coded from CMI to NRZ format and converted from
serial to parallel at one half the TSCLK rate.
The Line Loopback circuitry consists of alternate
clock and data output drivers. For the S3005, it selects
the source of the data and clock which is output on TSD
and TSCLK. When the Line Loopback Enable input
(LLEB) is high, it selects data and clock from the Parallel
to Serial Converter block or the CMI Encoder block.
When LLEB is low, it forces the output data multiplexor
to select data and clock from the LLD and LLCLK
inputs. When these inputs are connected to the Line
Loop Clock (LLCLK) and Line Loop Data (LLD) out-
puts of a S3006 receiver, a receive-to-transmit
loopback can be established at the serial data rate.
Note that in CMI operating mode, the data bit rate is
one half of the recovered clock rate.
Diagnostic Loopback
The Diagnostic Loopback path consists of alternate
serial data outputs (in the case of the S3005) and
inputs (in the case of the S3006).
On the S3005, the differential ECL output DLD pro-
vides Diagnostic Loopback serial data. When the
Diagnostic Loopback Enable (DLEB) input is low,
this data output is a replica of TSD. When DLD is
connected to the S3006, a loopback from the trans-
mitter to the receiver at the serial data rate can be
set up for diagnostic purposes. When DLEB is high,
DLD is held in the inactive state, with the positive
output high and the negative output low. In the inac-
tive state, there will be no interference from the
transmitter to the receiver. The DLD outputs on the
S3005 should be held inactive (DLEB high) when not
in use to avoid potential crosstalk of the asynchro-
nous DLD signals with the serial data signals.
Test and Bypass Modes
The Test Clock Enable (TESTEN) inputs on both
chips provide access to the PLL.
The PLL-generated clock source on both the S3005
and S3006 can be bypassed by setting TESTEN
high. In this mode, an externally generated bit serial
clock source must be applied at the REFCLK input.
Table 6 lists the possible combinations allowed in
bypass mode.
On the receiver side, the differential ECL input DLD
is the Diagnostic Loopback serial data input. When
the Diagnostic Loopback Enable (DLEB) input is set
low, the DLD input is routed in place of the normal
data stream (RSD).
Table 6. Bypass Mode
TESTEN
MODE[2:0]
Reference Clock Frequency
Serial Data Rate
(Mbit/s)
In Bypass Mode
0
XXX
Normal Operating Mode
(See Table 2)
—
1
1
1
1
100
101
101
110
622.08
311.04
278.528
155.52
622.08
155.52 CMI
139.264 CMI
155.52
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3005 Pin Assignment and Descriptions
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
TTL
I
37
36
33
32
31
30
29
28
2
3
Parallel data input, a 77.76 Mbyte/s, 19.44 Mbyte/s,
or 17.408 Mbyte/s word, aligned to the PICLK
parallel input clock. PIN7 is the most significant bit
(corresponding to bit 1 of each PCM word, the first
bit transmitted). PIN0 is the least significant bit
(corresponding to bit 8 of each PCM word, the last
bit transmitted). PIN(7-0) is sampled on the rising
edge of PICLK.
5
8
9
10
12
14
PICLK
TTL
I
48
60
Parallel input clock, a 77.76 MHz, 19.44 MHz, or
17.408 MHz nominally 50% duty cycle input clock,
to which PIN(7-0) is aligned. PICLK is used to
transfer the data on the PIN inputs into a holding
register in the parallel-to-serial converter. The rising
edge of PICLK samples PIN(7-0).
TESTEN
SYNC
TTL
TTL
I
I
6
31
58
Test clock enable signal, set high to provide access
to the PLL during production tests. (See Table 6.)
50
Active high synchronization enable input that
enables the timing generator to invert the internal
byte transfer clock if transfers from the PIN(7-0)
input holding register are occurring less than one bit
period before or after clocking new data into the
holding register. The SYNC pin is an asynchronous
input.
REFCLKP
REFCLKN
Diff.
ECL
I
I
I
77
75
36
38
Inputs used as the reference for the internal bit clock
frequency synthesizer, or used as an externally
provided bit clock. (See Tables 3 and 4.)
REFSEL1
REFSEL0
TTL
TTL
10
11
28
27
Inputs used to select the reference frequency for the
internal clock synthesizer. (See Tables 3 and 4.)
MODE2
MODE1
MODE0
43
45
44
66
63
65
Inputs used to select the operating mode of the
device as 622.08 Mbit/s (STS-12); 155.52 Mbit/s
(STS-3); 155.52 Mbit/s CMI (STS-3 electrical); or
139.764 Mbit/s (E4 CMI). (See Table 2.)
LLDP
LLDN
Diff.
ECL
I
I
64
62
49
51
Line loopback data inputs normally provided from a
companion S3006 device. Used to implement a line
loopback, in which the received bit serial data and
clock signals are regenerated and passed through
the S3005 transmitter. An internal 100-Ω resistor
terminates LLDP to LLDN.
LLCLKP
LLCLKN
Diff.
ECL
68
66
45
47
Line loopback clock inputs normally provided from a
companion S3006 device. Used to implement a line
loopback, in which the received bit serial data and
clock signals are regenerated and passed through
the S3005 transmitter. An internal 100-Ω resistor
terminates LLCLKP to LLCLKN.
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3005 Pin Assignment and Descriptions (Continued)
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
DLCV
TTL
TTL
I
I
49
12
59
26
Diagnostic line code violation input. A rising edge
causes a CMI code violation in the serial output
data. DLCV is an asynchronous input which is only
valid when CMI is enabled.
DLEB
Diagnostic loopback enable signal. Enables the DLD
output when low. When DLEB is high, the DLD
output is held in the inactive state to prevent
interference between the transmit and receive
devices. Will not affect the TSD signals.
LLEB
RSTB
TTL
TTL
I
51
9
57
29
Line loopback enable input. When low, the LLD and
LLCLK inputs are connected to the TSD and TSCLK
outputs to implement line loopback. When in normal
mode (LLEB high), the internally generated data and
clock signals are output at TSD and TSCLK.
I
Reset input for the device, active low.
TSDP
TSDN
Diff.
ECL
O
74
72
39
41
High-speed source-terminated serial data stream
signals, normally connected to an optical transmitter
module. Updated on the falling edge of TSCLK.
DLDP
DLDN
Diff.
ECL
O
O
25
24
15
16
High-speed diff. ECL serial data stream signals,
normally connected to a companion S3006 device
for diagnostic loopback purposes. The DLD outputs
are updated on the falling edge of TSCLK. They are
held in the inactive state, except when DLEB is low.
TSCLKP
TSCLKN
Diff.
ECL
69
70
44
43
High-speed source-terminated diff. ECL transmit
serial clock. Phase-aligned with the TSD and DLD
output signals. TSCLK can be a buffered version of
the internal frequency synthesizer clock, of the
REFCLK inputs during clock bypass (TESTEN high),
or of the LLCLK inputs during line loopback (LLEB
low).
PCLK
PAE
TTL/
O
O
16
18
23
20
A reference clock generated by dividing the internal
bit clock by eight. It is normally used to coordinate
byte-wide transfers between upstream logic and the
S3005 device.
CMOS
TTL/
CMOS
Phase alignment event signal, that pulses high
during each PCLK cycle for which there is less than
one bit period between the internal byte clock and
PICLK timing domains. PAE is updated on the
falling edge of the PCLK outputs.
BYTCLKIP
TTL/
CMOS
O
17
21
Reference feedback clock. It is compared with the
reference clock (REFCLK) to maintain stability of the
clock synthesis PLL. BYTCLKIP is at the same
frequency as REFCLK and is an asynchronous
output.
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3005 Pin Assignment and Descriptions (Continued)
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
LOCKDET
TTL
O
52
56
Lock detect signal. Goes high after the PLL has had
time to lock onto the clock provided on the REFCLK
pins (approx. 2000 REFCLK cycles). LOCKDET is
an asynchronous output.
CAP1
CAP2
–
I
–
–
The loop filter capacitor is connected to these pins.
The capacitor value should be 0.01µf ±10%
tolerance, X7R dielectric. 50 V is recommended (16
V is acceptable).
1,2,
79, 80
AGND
AVEE
GND
–
–
5, 56, 65,
71, 76
32, 37, Analog Ground (0V)
42, 48, 54
–4.5V
4, 57, 63,
67, 73
33, 40, Power Supply (–4.5V)
46, 50, 53
ECLGND
GND
–
7, 15, 19, 4, 13, 18, ECL Ground (0V)
22, 26, 25, 34,
35, 39, 52, 61, 68
42, 46, 54
VEE
–4.5V
GND
–
–
8, 14, 27, 6, 7, 11, Power Supply (–4.5V)
34, 47, 53 24, 30, 62
TTLGND
20, 41
21, 40
22, 64, 67 TTL Ground (0V)
1, 17, 19 Power Supply (+5V)
VCC
NC
+5V
–
–
–
3, 13, 23,
38, 55,
35, 55
No connection
58, 59,
60, 61, 78
Applied Micro Circuits Corporation
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3006 Pin Assignment and Descriptions
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
RSDP
RSDN
Diff.
ECL
I
62
64
51
49
High-speed diff. ECL receive serial data stream
signals, normally connected to an optical receiver
module. When internal clock recovery is used, clock
is recovered from transitions on the RSD inputs.
When external clock recovery is used, the RSD
inputs are sampled on the rising edge of the
reference (REFCLK). An internal 100-Ω termination
resistor is connected across RSDP and RSDN.
DLDP
DLDN
Diff.
ECL
I
66
68
47
45
High-speed diff. ECL diagnostic loopback data.
Serial data stream signals, normally connected to a
companion S3005 device for diagnostic loopback
purposes. Clock is recovered from transitions on the
DLD inputs while in diagnostic loopback. An internal
100- termination resistor is connected across
DLDP and DLDN.
DLEB
TTL
TTL
TTL
I
I
I
51
6
57
31
58
Selects diagnostic loopback. When DLEB is high,
the S3006 device uses the primary data (RSD)
input. When low, the S3006 device uses the
diagnostic loopback data (DLD) input.
TESTEN
OOF
Test clock enable signal, set high to provide access
to the PLL during production tests. Can also be
used to enable an external clock source in bypass
mode (see Table 6).
50
Out of frame indicator used to enable framing
pattern detection logic in the S3006. This logic is
enabled by a rising edge on OOF, and remains
enabled until frame boundary is detected or when
OOF is set low, whichever is longer. OOF is an
asynchronous signal with a minimum pulse width of
one POCLK period. (See Figures 17 and 18.)
LOS
ECL
I
16
23
An active-high, single-ended 10K ECL input to be
driven by the external optical receiver module to
indicate a loss of received optical power (Loss of
Signal). When LOS is high, the data on the Serial
Data In (RSDP/N) pins will be internally forced to a
constant zero, LOCKDET will be forced low, and the
PLL will lock to the REFCKINP/N inputs. This signal
must be used to assure correct automatic
reacquisition to serial data following an interruption
and subsequent reconnection of the optical path.
(This ensures that the PLL does not "wander" out of
reacquisition range by tracking the random
phase/frequency content of the optical detector's
noise floor while monitoring "dark" fiber.) When LOS
is low, data on the RSDP/N pins will be processed
normally.
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3006 Pin Assignment and Descriptions (Continued)
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
REFCLKP
REFCLKN
Diff.
ECL
I
77
75
36
38
Input normally used as the reference for the integral
clock recovery PLL. (See Tables 3 and 4.) When the
test clock enable (TESTEN) input is set high,
REFCLK replaces the bit rate recovered clock. (See
Table 6.)
REFSEL1
REFSEL0
TTL
TTL
I
I
12
11
26
27
Inputs used to select the reference frequency for the
internal clock synthesizer. (See Tables 3 and 4.)
MODE2
MODE1
MODE0
49
10
9
59
28
29
Inputs used to select the operating mode of the
device as 622.08 Mbit/s (STS-12); 155.52 Mbit/s
(STS-3); 155.52 Mbit/s CMI (STS-3 electrical); or
139.764 Mbit/s (E4 CMI). (See Table 2.)
TESTRST
RSTB
TTL
TTL
I
18
17
20
21
Used to reset portions of the clock recovery PLL
during production testing. Held low for normal
operation.
I
Reset input for the device, active low. After reset,
frame boundary detection is disabled.
LLDP
LLDN
Diff.
ECL
O
72
74
41
39
High-speed source-terminated diff. ECL line
loopback data. A regenerated version of either the
incoming data stream (RSD) input in normal mode,
or the diagnostic loopback data (DLD) input in
diagnostic loopback mode (DLEB set high). LLD is
updated on the rising edge of LLCLK.
LLCLKP
LLCLKN
Diff.
ECL
O
O
69
70
44
43
High-speed source-terminated diff. ECL line
loopback clock, phase-aligned with the LLD output
signals. LLCLK can be a buffered version of the
internally recovered bit clock, or the reference clock
(REFCLK) input when clock recovery is bypassed
(TESTEN set high).
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
TTL/
CMOS
37
36
33
32
31
30
29
28
2
3
Parallel data output, a 77.76 Mbyte/s, 19.44
Mbyte/s, or 17.408 Mbyte/s word, aligned to the
POCLK parallel output clock. POUT7 is the most
significant bit (corresponding to bit 1 of each PCM
word, the first bit transmitted). POUT0 is the least
significant bit (corresponding to bit 8 of each PCM
word, the last bit transmitted). POUT(7-0) is updated
on the falling edge of POCLK.
5
8
9
10
12
14
LCV
TTL/
CMOS
O
44
65
Line code violation output signal, set high to indicate
that one or more bits of the byte currently presented
on POUT(7– 0) contains a CMI line code violation.
LCV is only active in STS-3 CMI and E4 CMI
modes. LCV is updated on the falling edge of
POCLK.
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3006 Pin Assignment and Descriptions (Continued)
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
FP
TTL/
CMOS
O
24
16
Frame pulse, indicates frame boundaries in the
incoming data stream (RSD). If framing pattern
detection is enabled, as controlled by the OOF
input, FP pulses high for one POCLK cycle when a
48-bit sequence matching the framing pattern is
detected on the RSD inputs.
POCLK
TTL/
O
O
O
48
45
52
60
63
56
Parallel output clock, a 77.76 MHz, 19.44 MHz, or
17.408 MHz nominally 50% duty cycle, byte rate
output clock, that is aligned to POUT(7-0) byte serial
output data. POUT(7-0), FP and LCV are updated
on the falling edge of POCLK.
CMOS
BYTCLKIP
LOCKDET
TTL/
CMOS
Reference feedback clock, compared with the
reference clock (REFCLK) to maintain stability of the
clock recovery PLL when it is in loss of signal state.
BYTCLKIP is at the same frequency as REFCLK
and is an asynchronous output.
TTL
Clock recovery indicator. Set high when the internal
clock recovery has locked onto the incoming data
stream. LOCKDET will go low if the incoming
encoded data stream has been low continuously for
4000 to 8000 bit times. LOCKDET will go high if
LOS is low and good data with acceptable run
length and transition density returns on the incoming
data stream. LOCKDET is an asynchronous output.
CAP1
CAP2
–
I
1, 2
79, 80
–
–
The loop filter capacitor is connected to these pins.
The capacitor value should be 0.01µf ±10%
tolerance, X7R dielectric. 50 V is recommended (16
V is acceptable).
AGND
AVEE
GND
–
–
5, 56, 65,
71, 76
32, 37, Analog Ground (0V)
42, 48, 54
–4.5V
4, 57, 63,
67, 73
33, 40, Power Supply (–4.5V)
46, 50, 53
ECLGND
Gnd
–
–
7, 15, 19, 4, 13, 18, ECL Ground (0V)
22, 26, 25, 34,
35, 39, 52, 61, 68
42, 46, 54
VEE
–4.5V
8, 14, 27, 6, 7, 11, Power Supply (–4.5V)
34, 47, 53 24, 30, 62
Applied Micro Circuits Corporation
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15
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
S3006 Pin Assignment and Descriptions (Continued)
Pin #
Pin #
Pin Name
Level I/O
Description
(80 PQFP) (68 LDCC)
TTLGND
GND
+5V
–
–
–
–
20, 25, 41 22, 64, 67 TTL Ground (0V)
VCC
NC
21, 38, 40 1, 17, 19 Power Supply (+5V)
3, 13, 23,
43, 55,
35, 55 No connection
58, 59,
60, 61, 78
Applied Micro Circuits Corporation
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Figure 9. 68 LDCC Package
35
51
.300 – 400 min
.
34
52
ceramic side
18
68
17
1
0.050 ± .005
Capacitor
0.065 ±.015
0.120±.010
.
+.015
–.010
.950
.300 – 400 min
Formed lead detail:
Capacitor
.055 ± .010
COPLANAR TO .004
.055 ± .005
1.180
± .020
All dimensions nominal in inches.
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
80 PQFP Package
80
78
76
74
72
70
68
66
64
62 61
1
2
60
59
57
55
53
51
49
47
4
6
8
10
12
14
16
18
20
Embedded
Heatsink
2.70 ± 0.1
45
43
41
Top View
0.88
0.65
0.30
Side View
21
23
25
27
29
31
33
35
37
39 40
14.0 ± 0.1
17.2 ± 0.25
All dimensions nominal in mm.
S3005 and S3006 80 PQFP Pinouts
CAP1
CAP1
NC
1
2
60 NC
59 NC
NC
CAP1
CAP1
NC
1
2
60 NC
59 NC
NC
AVEE3
AGND3
TESTEN
ECLGND
VEE
4
6
8
57 AVEE1
AGND1
55 NC
ECLGND
53 VEE
LOCKDET
51 LLEB
SYNC
49 DLCV
PICLK
47 VEE
ECLGND
45 MODE1
MODE0
43 MODE2
ECLGND
41 TTLGND
AVEE3
AGND3
TESTEN
ECLGND
VEE
4
6
8
57 AVEE1
AGND1
55 NC
ECLGND
53 VEE
LOCKDET
51 DLEB
OOF
RSTB
MODE0
S3005
Embedded
Heatsink
S3006
Embedded
Heatsink
REFSEL1 10
REFSEL0
DLEB 12
NC
MODE1 10
REFSEL0
REFSEL1 12
NC
VEE 14
ECLGND
LOS 16
MODE2
POCLK
49
VEE 14
47 VEE
ECLGND
45 BYTCLKIP
LCV
43 NC
ECLGND
41 TTLGND
ECLGND
PCLK 16
BYTCLKIP
PAE 18
ECLGND
TTLGND 20
RSTB
TESTRST 18
ECLGND
TTLGND 20
Top View
Top View
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SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Table 7. Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Given REFCLK = SERCLK ÷ 8,
12, 16 or 32 per REFSEL<1:0>
settings
Nominal VCO
Center Frequency
622.08
MHz
Given the jitter on REFCLK
(12KHz to 1 MHz band) is less
than:
ECL Data Output Jitter
(S3005 TSDP/N, DLDP/N)
• 56 ps rms (OC–3)
OC–3/STS–3
OC–STS–3 CMI
OC–12/STS-12
64
32
16
ps (rms)
ps (rms)
ps (rms)
• 28 ps rms (OC–STS–3 CMI)
• 14 ps rms (OC–12),
REFCLK = 77.76 MHz
1
Reference Clock
Frequency Tolerance
Clock Synthesis
Required to meet SONET output
frequency specification
S3005 REFCKINP/N
S3006 REFCKINP/N
-20
-100
20
100
ppm
ppm
OC–3/STS–3 &
OC–12/STS–12
Capture Range
±200
ppm
%
With respect to fixed reference
frequency
Minimum transition density of
20%
Lock Range
+8, -12
2
Acquisition Lock Time
OC-3/STS-3
OC-STS-3 CMI
OC-12/STS-12
64
32
16
With device already powered up
and valid REFCLK
µsec
Reference Clock
Input Duty Cycle
30
70
% of period
ns
Reference Clock Rise &
Fall Times
2.0
10% to 90% of amplitude
ECL Output Rise & Fall
Times (S3005 DLDP/N)
20% to 80%, 50Ω to -2V
equivalent load, as per Figure 19
600
450
ps
ps
Source Terminated
Differential ECL
Compatible Outputs
Rise and Fall Times
20% to 80%, 100Ω line to line,
as per Figure 19
1. For REFCLK =19.44, 38.88 or 51.84 MHz, multiply the specified value by three.
2. Specifications based on design values. Not tested.
Applied Micro Circuits Corporation
19
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Absolute Maximum Ratings
Typ Max
Min
-55
Unit
PARAMETER
Case Temperature under Bias
125 °C
150 °C
150 °C
Junction Temperature under Bias
Storage Temperature
-55
-65
-0.5
+0.5
-0.5
-3
Voltage on VCC with Respect to GND
Voltage on VEE with Respect to GND
Voltage on Any TTL Input Pin
Voltage on Any ECL Input Pin
TTL/CMOS Output Sink Current
TTL/CMOS Output Source Current
High Speed ECL Output Source
or Sink Current
+7.0
-8.0
+5.5
0
V
V
V
V
20 mA
25 mA
50 mA
V
Static Discharge Voltage
500
Recommended Operating Conditions
Typ Max Unit
Min
PARAMETER
Ambient Temperature under Bias
Junction Temperature under Bias
Voltage on VCC with Respect to GND
-40
85
°C
-10
130 °C
4.75 5.0
5.25
V
V
1
Voltage on VEE with Respect to GND
Voltage on Any TTL Input Pin
Voltage on Any ECL Input Pin
TTL/CMOS Output Sink Current
TTL/CMOS Output Source Current
ECL Output Source Current
-4.2 -4.5/-5.2 -5.46
0
VCC
V
-2.0
0
8
V
mA
20 mA
25 mA
Source Terminated Diff. ECL Compatible
Output Source or Sink Current
10
52
mA
mA
ICC
S3005
41
IEE
314 402 mA
54 69 mA
324 414 mA
ICC
S3006
IEE
1. VEE (min) = -4.2V for Ambient Temperature ≥ 0˚C, -4.5V for
Ambient Temperature <0˚C.
Thermal Management
Θja Still
Max Still
Air
Air/70˚C
for 100˚C Tj
Device
Package
Θjc
Power
Air/70˚C
Air/85˚C
AIr
S3005
68 LDCC
2.5˚C/W
33.9˚C/W
26.4˚C/W
30˚C/W
2.4W
49˚C
66˚C
58˚C
75˚C
42˚C
61˚C
52˚C
70˚C
200 LFPM 500 LFPM 750 LFPM
<50 LFPM 140 LFPM 210 LFPM
200 LFPM 700 LFPM 1050 LFPM
w/45-20 HS
80 TEP
2.4W
2.4W
2.4W
2.6W
2.6W
2.6W
2.6W
S3005
S3006
S3006
2.0˚C/W
2.5˚C/W
2.0˚C/W
w/45-28 HS
68 LDCC
23˚C/W
N/A
200 LFPM 300 LFPM
33.9˚C/W
26.4˚C/W
30˚C/W
310 LFPM 600 LFPM 900 LFPM
100 LFPM 150 LFPM 230 LFPM
300 LFPM 750 LFPM 1130 LFPM
w/45-20 HS
80 TEP
w/45-28 HS
23˚C/W
N/A
250 LFPM 380 LFPM
Applied Micro Circuits Corporation
20
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
TTL Input/Output DC Characteristics1
(TA = -40°C to +85°C, VCC = 5 V ±5%, VEE = -4.5 V ±7% or -5.2 ± 5%)
Symbol
Parameter
Conditions
Min
Max
Unit
Volts
Volts
2
V
Input LOW Voltage
Guaranteed Input LOW Voltage
Guaranteed Input HIGH Voltage
0.8
IL
2
V
Input HIGH Voltage
2.0
IH
I
Input LOW Current
-400.0
uA
uA
mA
V
V
V
V
V
= MAX, V = 0.5V
IN
IL
CC
CC
CC
CC
CC
I
Input HIGH Current
= MAX, V = 2.7V
IN
50.0
1.0
IH
I
Input HIGH Current at Max VCC
Output Short Circuit Current
= MAX, V = 5.25V
IN
I
I
= MAX, V
= MAX, V
= MAX, V
= 0.5V
-100.0
-50.0
-25.0
50.0
50.0
mA
uA
OS
OUT
I
= 0.4V
Output Three-State Current LOW
Output Three-State Current HIGH
Input Clamp Diode Voltage
OZL
OL
I
V
V
V
= 2.4V
-50.0
-1.2
uA
OZH
CC
CC
CC
OH
V
= MIN, I = -18mA
IN
Volts
Volts
IK
V
TTL Output LOW Voltage
= MIN, I
= 8mA
OL
0.5
0.4
OL
V
V
TTL Output HIGH Voltage
2.4
3.4
Volts
Volts
V
= MIN, I
= -1.0mA
= 100uA
OH
CC
OH
V
CMOS Compatible Output
LOW Voltage
V
= MIN, I
OL
CC
OH
CMOS Compatible Output
HIGH Voltage
Volts
V
= MIN, I
= -100uA
OH
CC
OH
1. These conditions will be met with an airflow of 400 LFPM.
2. These input levels provide zero noise immunity and should only be tested in a static, noise-free environment.
ECL Input/Output DC Characteristics7
(TA = -40°C to +85°C, VCC = 5 V ±5%, VEE = -4.5 V ±7% or -5.2 ± 5%)
Symbol
Parameter
Conditions
Signal Name
Min
Max
Unit
Guaranteed Input LOW Voltage
for all single ended inputs
1
V
Input LOW Voltage
-2.00
-1.47
Volts
IL
Guaranteed Input HIGH Voltage
for all single ended inputs
1
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input DIFF Voltage
-1.18
-2.00
-1.75
0.25
-0.80
-0.70
-0.45
1.40
Volts
Volts
Volts
Volts
IH
Guaranteed Input LOW Voltage
for all differential inputs
2
V
IL
Guaranteed Input HIGH Voltage
for all differential inputs
2
V
IH
Guaranteed Input DIFF Voltage
for all differential inputs
2
V
ID
6
20.00
-3.50
-2.80
uA
mA
mA
V
= MAX, V = -1.95V
IL
LOS
-0.50
-7.00
EE
I
Input LOW Current
IL
5
5
LLDP ,LLCLKP ,
V
= MAX, V
= 0.5V
EE
DIFF
DIFF
6,
6
RSDP DLDP
5
5
LLDN , LLCLKN ,
-8.30
V
= MAX, V
= 0.5V
EE
6
6
RSDN , DLDN
5,6
REFCLKP
REFCLKN
,
V
V
= MAX, V
= 0.5V
DIFF
-1.00
-0.50
3.50
20.00
20.00
7.00
uA
uA
mA
EE
5,6
6
= MAX, V = -0.80V
IH
LOS
EE
EE
I
Input HIGH Current
IH
5
6
5
LLDP , LLCLKP ,
RSDP , DLDP
V
= MAX, V
= 0.5V
DIFF
6
5
5
LLDN , LLCLKN ,
V
V
= MAX, V
= MAX, V
= 0.5V
= 0.5V
2.80
8.30
mA
uA
EE
DIFF
6
6
RSDN , DLDN
REFCLKP
REFCLKN
5,6
,
-1.00
20.00
EE
DIFF
5,6
3
V
50Ω to -2V termination
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output DIFF Voltage
-2.00
-1.11
-2.50
-2.20
0.30
-1.50
-0.62
-0.80
-0.50
1.00
Volts
Volts
Volts
Volts
Volts
OL
3
V
50Ω to -2V termination
OH
4
V
100Ω between differential outputs
100Ω between differential outputs
100Ω between differential outputs
OL
4
V
OH
4
V
OD
1. Single Ended ECL Inputs
2. Differential ECL Inputs
3. Standard ECL Outputs
4. Source Terminated Differential ECL Compatible Outputs
5. S3005 Signals
6. S3006 Signals
7. These conditions will be met with an airflow of 400 LFPM.
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
21
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Table 8. S3005 AC Timing Characteristics
(TA = -40°C to +85°C, VCC = 5 V ±5%, VEE = -4.5 V ±7% or -5.2V ± 5%)
Symbol
Description
Min
Max
Units
TSCLK Frequency (nom. 155, 311, or 622 MHz)
640
MHz
TSCLK Duty Cycle
40
33
60
67
%
%
PICLK Duty Cycle
tSPIN
tHPIN
tSLLD
tHLLD
PIN [7.0] Set-up Time w.r.t. PICLK
PIN [7.0] Hold Time w.r.t. PICLK
LLD Set-Up Time w.r.t. LLCLK
LLD Hold Time w.r.t. LLCLK
LLCLK Duty Cycle
2.0
1.0
100
100
40
ns
ns
ps
ps
%
60
tPTSD
tSTSD
tHTSD
tPPAE1
TSCLK Low to TSD Valid Propagation Delay
TSD Set-Up Time w.r.t. TSCLK
TSD Hold Time w.r.t. TSCLK
PCLK Low to PAE Valid Propagation Delay
TSD ± Edge Skew
440
ps
ps
ps
ns
ps
ps
400
400
3.0
100
100
TSD1
ESK
TSCLK1
TSCLK ± Edge Skew
ESK
1 Guaranteed but not tested.
Figure 10. PIN AC Input Timing
PICLK
Figure 11. LLD AC Input Timing
LLCLK
tS
tH
tS
tH
LLD
LLD
PIN
PIN
LLD
PIN[7:0]
1. When a set-up time is specified on TTL signals between an input and a clock, the set-up time is the time in picoseconds from the 50% point of the input to
the 50% point of the clock.
2. When a hold time is specified on TTL signals between an input and a clock, the hold time is the time in picoseconds from the 50% point of the clock to the
50% point of the input.
3. When a set-up time is specified on differential ECL signals between an input and a clock, the set-up time is the time in picoseconds from the cross-over
point of the input to the cross-over point of the clock.
4. When a hold time is specified on differential ECL signals between an input and a clock, the hold time is the time in picoseconds from the cross-over point
of the clock to the cross-over point of the input.
Figure 12. Output Timing
Figure 13. PAE Output Timing
PCLK
TSCLK
tP
tP
PAE
TSD
PAE
TSD+
Notes on TTL Output Timing
Notes on High-Speed PECL Output Timing
1. Output propagation delay time is the time in nanoseconds from the
50% point of the reference signal to the 30% or 70% point of the output.
2. Maximum output propagation delays are measured with a 15pF load on
the outputs.
1. Output propagation delay time is the time in nanoseconds from the cross-
over point of the reference signal to the cross-over point of the output.
Table 9. S3005 External Clock Mode Timing
Description
Min
Max
Units
REFCLK in Bypass Mode (nom. 155, 311, or 622 MHz)
640
MHz
REFCLK in Bypass Mode duty cycle
33
67
%
Applied Micro Circuits Corporation
22
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Table 10. S3006 AC Timing Characteristics
Symbol
Description
Min
Max
Units
1
POCLK Duty Cycle
40
60
%
POCLK Low to POUT [7:0] Valid Prop. Delay @ STS-3
POCLK Low to POUT [7:0] Valid Prop. Delay @ STS-12
0
0
5
1.5
ns
ns
tP
POUT
POCLK Low to FP Valid Propagation Delay @ STS-3
POCLK Low to FP Valid Propagation Delay @ STS-12
0
0
5
1.5
ns
ns
tP
FP
LLCLK Frequency
LLCLK Duty Cycle
640
60
MHz
%
40
LLCLK Low to LLD Valid Propagation Delay @ STS-3
LLCLK Low to LLD Valid Propagation Delay @ STS-12
-800
-500
800
500
ps
ps
tP
LLD
1 Driving CMOS with a 2.5V threshold and a 500Ω load, or driving TTL with a 1.4V threshold and a 150Ω load.
Figure 14. Input Timing - External Clock Mode
Figure 15. Output Timing Diagram
POCLK
RFCLK+
tP
POUT
tS
tS
tH
tH
RSD
DLD
RSD
DLD
POUT[7:0]
RSD
tP
FP
FP
DLD
LLCLK
Notes on Input Timing:
1. When a set-up time is specified between a data input and a
clock input, the set-up time is the time in picoseconds from the
crossover point of the differential data input to the crossover
point of the differential clock input.
tP
LLD
LLD
2. When a hold time is specified between a data input and a
clock input, the hold time is the time in picoseconds from the
crossover point of the differential clock input to the crossover
point of the differential data input.
Notes on Output Timing:
1. Output timing specification are valid when terminating all
outputs with 500Ω to GND.
2. Output propagation delay time of TTL outputs is the time in
picoseconds from the 50% point of the reference signal to
the 30% or 70% point of the output.
3. Maximum output propagation delays of TTL outputs are
measured with a 15 pF load on the outputs.
4. Output propagation delay time of high speed ECL outputs is
the time in picoseconds from the cross-over point of the
reference signal to the cross-over point of the output.
5. Maximum output propagation delays of TTL outputs are
measured with a 50Ω transmission line on the outputs.
Table 11. S3006 External Clock Mode Timing
Symbol
Description
REFCLK Freq. (Nominally 622/311//155 MHz)
REFCLK Duty Cycle
Min
Max
640
67
Units
MHz
%
33
tS
RSD to REFCLK Set-up Time
300
ps
RSD
REFCLK to RSD Hold Time @ STS-3
REFCLK to RSD Hold Time @ STS-12
1.0
100
ns
ps
tH
RSD
DLD to REFCLK Set-up Time
300
ps
tS
tH
DLD
REFCLK to DLD Hold Time @ STS-3
REFCLK to DLD Hold Time @ STS-12
1.0
100
ns
ps
DLD
Applied Micro Circuits Corporation
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6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
RECEIVER FRAMING
at least one framing pattern has been detected since
the rising edge of OOF, boundary detection is dis-
abled when OOF is set low.
Figure 16 shows a typical reframe sequence in
which a byte realignment is made. The frame and
byte boundary detection is enabled by the rising
edge of OOF and remains enabled while OOF is
high. Both boundaries are recognized upon receipt
of the third A2 byte which is the first data byte to be
reported with the correct byte alignment on the out-
going data bus (POUT[7:0]). Concurrently, the frame
pulse is set high for one POCLK cycle.
The frame and byte boundary detection block is acti-
vated by the rising edge of OOF, and stays active
until the first FP pulse or until OOF goes low, which-
ever occurs last. Figure 17 shows a typical OOF
timing pattern which occurs when the S3006 is con-
nected to a down stream section terminating device.
OOF remains high for one full frame after the first FP
pulse. The frame and byte boundary detection block
is active until OOF goes low.
When interfacing with a section terminating device,
the OOF input remains high for one full frame after
the first frame pulse while the section terminating
device verifies internally that the frame and byte
alignment are correct, as shown in Figure 17. Since
Figure 18 shows the frame and byte boundary detec-
tion activation by a rising edge of OOF, and
deactivated by the first FP pulse.
Figure 16. Frame and Byte Detection
NOTE 1: Range of input to output delay can be 1.5 to 2.5 POCLK cycles
Figure 17. OOF Operation Timing with SSTX
Figure 18. Alternate OOF Timing
Boundary Detection Enabled
Boundary Detection Enabled
OOF
FP
OOF
FP
Applied Micro Circuits Corporation
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6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Figure 19. Differential ECL Input and Output Applications
50 Ω
Internal 100
Ω termination
S3006 LLDP/N to S3005 LLDP/N
S3006 LLCLKP/N to S3005 LLCLKP/N
Electrical to
optical
100 Ω
S3005 TSDP/N to Fiber Optic Transmitter
100 Ω
330 Ω
VEE
330 Ω
Reference Clock Crystal Oscillator Source
(ECL Driver) to REFCLK Input
330 Ω
330 Ω
VEE
Internal 100
Ω termination
S3005 DLDP/N to S3006 DLDP/N
Fiber Optic Receiver to S3006 RSDP/N
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
25
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
STS-12/STS-3 OPTICAL INTERFACE
receive and transmit overhead processors on the
equipment side and electrical-to-optical converters
on the line side to realize the core of a typical
SONET transceiver.
The S3005 and S3006 devices are designed to in-
terface seamlessly to make a SONET transceiver for
STS-12, CMI-encoded STS-3, and STS-3. Figure 20
shows these two devices connected together with
Figure 20. OC-12 Application
77.74 MHz
TX Overhead
500Ω
REFCLK
OC-12
TX
PCLK
STS-3
POUT[7:0]
TX
PIN[7:0]
PICLK
LLD
TSD
POCLK
E/O
TSCLK
LLCLK
DLD
S3005
S3006
MODE2
SYNC
PAE
TO/FROM
COMMON
CONTROL
STTX
DLEB
LLEB
STS-3
RX
REFCLK
LLCLK
OC-12
RX
DLD
RSD
LOS
LLD
PIN[7:0]
PICLK
FPIN
POUT[7:0]
O/E
POCLK
FP
OOF
OOF
500Ω
RX Overhead
TESTEN = LOW
REFSEL[1] = HIGH
REFSEL[0] = HIGH
MODE[2] = CONNECTED to LLEB
MODE[1] = LOW
MODE[0] = LOW
STS-3 CMI ELECTRICAL INTERFACE
With the S3006 devices optioned for CMI-coded
STS-3, an electrical SONET transceiver can be
implemented as shown in Figure 21 In this case, a
clock reference of 51.84 MHz was selected. TSD
would be coupled through a line driver and trans-
former to a coaxial cable for short span applications.
Figure 21. CMI Electrical Interface
51.84 MHz
TX Overhead
REFCLK
PCLK
TSD
STS-1
TX
PIN[7:0]
PICLK
LLD
POUT[7:0]
POCLK
S3005
DLD
LLCLK
SYNC
PAE
TO/FROM
COMMON
CONTROL
SLTX SSTX
DLEB
DCLV
LLEB
STS-1
RX
REFCLK
LLCLK
STS-3
CMI
RX
DLD
RSD
LLD
PIN[7:0]
PICLK
FPIN
POUT[7:0]
POCLK
S3006
FP
LCV
OOF
OOF
RX Overhead
MODE[2] = LOW REFSEL[1] = HIGH
TESTEN = LOW MODE[1] = LOW REFSEL[0] = LOW
MODE[0] = HIGH
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
26
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
EXTERNAL CLOCK APPLICATION
S3005/S3006
for STS-12 with external clock recovery on the re-
ceive side, and an external transmit clock connected
to REFCLK of the S3005 device.
The S3006 can receive data at SONET or other
standard data rates by bypassing the internal clock
recovery PLL and supplying the appropriate clock to
the REFCLK input. Figure 22 shows an application
Figure 22. OC-12 External Clock Application
622.08 MHz
TX Overhead
PCLK
REFCLK
OC-12
TX
STS-1
TX
TSD
TSCLK
E/O
POUT[7:0]
POCLK
PIN[7:0]
PICLK
LLD
LLCLK
S3005
DLD
DLD
SYNC
TO/FROM
COMMON
CONTROL
PAE
SLTX SSTX
DLEB
LLEB
STS-1
RX
REFCLK
LLCLK
LLD
Recovered
Clock
OC-12
RX
PIN[7:0]
PICLK
FPIN
POUT[7:0]
E/O
RSD
LOS
POCLK
FP
OOF
OOF
S3006
RX Overhead
MODE[2] = HIGH
MODE[1] = HIGH
MODE[0] = LOW
REFSEL[1] = NOT APPLICABLE
REFSEL[0] = NOT APPLICABLE
TESTEN = HIGH
Applied Micro Circuits Corporation
27
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
SONET/SDH OC-3/12 TRANSMITTER AND RECEIVER
S3005/S3006
Ordering Information
GRADE
TRANSMITTER
PACKAGE
SPEED GRADE
1 – 139 Mbit/s
1 – 139 Mbit/s CMI
1 – 155 Mbit/s
S – commercial
3005
A – 68 LDCC
with straight leads
B – Bare Die
1 – 155 Mbit/s CMI
6 – 622 Mbit/s
C – 68 LDCC
lead formed
D – 80 PQFP
GRADE
TRANSMITTER
PACKAGE
SPEED GRADE
1 – 139 Mbit/s
1 – 139 Mbit/s CMI
1 – 155 Mbit/s
1 – 155 Mbit/s CMI
6 – 622 Mbit/s
S – commercial
3006
A – 68 LDCC
with straight leads
B – Bare Die
C – 68 LDCC
lead formed
D – 80 PQFP
X XXXX
X
X
Grade Part number
Package
Speed Grade
Applied Micro Circuits Corporation • 6195 Lusk Blvd., San Diego, CA 92121
Phone: (619) 450-9333 Fax: (619) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1997 Applied Micro Circuits Corporation
June 2, 1997
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