S3050A [AMCC]
Clock Recovery Circuit, 1-Func, Bipolar, LLCC-32;
| 型号： | S3050A |
| 厂家： | 
APPLIED MICRO CIRCUITS CORPORATION |
| 描述： | Clock Recovery Circuit, 1-Func, Bipolar, LLCC-32 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总15页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
This product is not released
and the specifications herein
are subject to change.
PRELIMINARY DEVICE
SPECIFICATION
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
FEATURES
GENERAL DESCRIPTION
The function of the S3050 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3050 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
•
•
Micro-power Bipolar technology
Complies with ANSI, Bellcore, and ITU-T
specifications for jitter tolerance, jitter
transfer and jitter generation
The S3050 receives an OC-48, OC-24, OC-12, or
OC-3 scrambled NRZ signal and recovers the clock
from the data. The chip outputs a differential bit
clock and retimed data.
•
•
On-chip high frequency PLL with internal
loop filter for clock recovery
Supports clock recovery for:
OC-48 (2488.32 Mbps),
OC-24 (1244.16 Mbps),
OC-12 (622.08 Mbps),
OC-3 (155.52 Mbps) NRZ data
The S3050 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a voltage
controlled oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
•
•
•
•
155 MHz reference frequency
Lock detect—monitors frequency
Low-jitter serial interface
+5V supply
Figure 1. System Block Diagram
8
8
8
8
8
8
S3041
Tx
S3042
8
8
OTX
8
8
ORX
S3050
OTX
Rx
8
8
8
8
8
8
8
8
8
8
S3042
Rx
S3041
Tx
S3050
ORX
January 22, 1999 / Revision A
1
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Suggested Interface Devices
S3050 OVERVIEW
Sumitomo
OC-48 Optical Receiver
OC-48 Receiver
The S3050 supports clock recovery for the OC-48,
OC-24, OC-12, or OC-3 data rate. Differential serial
data is input to the chip at the specified rate and clock
recovery is performed on the incoming data stream.
An external oscillator is required to minimize the PLL
lock time and provide a stable output clock source in
the absence of serial input data. Retimed data and
clock are output from the S3050.
AMCC S3044
AMCC S3042
OC-48 Receiver
Figure 2. S3050 Functional Block Diagram
LOOP
FILTER
VCO
CAP 1,2
2
REFCLKP/N
2
TESTEN
SERCLKOP/N
CLOCK
DIVIDER
2
RATESEL0/1
LOCK
DETECTOR
LOCKDET
LCKREFN
PHASE DETECTOR
2
SERDATOP/N
BYPASS
SDN
2
SERDATIP/N
January 22, 1999 / Revision A
2
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Lock Detect
S3050 FUNCTIONAL DESCRIPTION
The S3050 clock recovery device performs the clock
recovery function for SONET OC-48, OC-24, OC-12,
or OC-3 serial data links. The chip extracts the clock
from the serial data inputs and provides retimed clock
and data outputs. A 155.52 MHz reference clock is
required for phase locked loop start up and proper
operation under loss of signal conditions. An integral
prescaler and phase locked loop circuit is used to
multiply this reference to the nominal bit rate. The
input data rate is selected by the RATSEL Inputs.
(See Table 1.)
The S3050 contains a lock detect circuit which monitors
the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be
forced to lock to the local reference clock. This will
maintain the correct frequency of the recovered clock
output under loss of signal or loss of lock conditions. If
the recovered clock frequency deviates from the local
reference clock frequency by more than approximately
600 ppm, the PLL will be declared out of lock. The lock
detect circuit will poll the input data stream in an attempt
to reacquire lock to data. If the recovered clock fre-
quency is determined to be within approximately 300
ppm, the PLL will be declared in lock and the lock de-
tect output will go active.
Clock Recovery
Clock Recovery, as shown in the block diagram in
Figure 2, generates a clock that is at the same fre-
quency as the incoming data bit rate at the Serial
Data input. The clock is phase aligned by a PLL so
that it samples the data in the center of the data eye
pattern.
Backup Reference Generator
The Backup Reference Generator seen in Figure 2
provides backup reference clock signals to the clock
recovery block when the clock recovery block detects
a loss of signal condition. It contains a counter that
divides the clock output from the clock recovery block
down to the same frequency as the reference clock
REFCLKP/N.
The phase relationship between the edge transi-
tions of the data and those of the generated clock
are compared by a phase/frequency discriminator.
Output pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of
the Voltage Controlled Oscillator (VCO), which
generates the recovered clock.
Table 1. Data Rate Select
RATESEL0
RATESEL1
Operating Mode
0
0
1
1
0
1
0
1
OC-48
OC-24
OC-12
OC-3
Frequency stability without incoming data is guaran-
teed by an alternate reference input (REFCLK) that
the PLL locks onto when data is lost. If the Fre-
quency of the incoming signal varies by greater than
approximately 600 ppm with respect to REFCLKP/N,
the PLL will be declared out of lock, and the PLL will
lock to the reference clock. The assertion of SDN will
also cause an out of lock condition.
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal. This transfer function yields a typical
capture time of 32 µs for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TA-NWT-000253 standard, shown in Figure 4.
January 22, 1999 / Revision A
3
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 3. Input Jitter Tolerance Specification
CHARACTERISTICS
Performance
Sinusodal
Input Jitter
Amplitude
The S3050 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
Bellcore Specifications: GR-253-CORE, Issue 2, De-
cember 1995 and ITU-T Recommendations: G.958
document, when used with differential inputs and out-
puts.
15
1.5
(UI p-p)
0.40
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to
peak amplitude of sinusoidal jitter applied on the
input signal that causes an equivalent 1 dB opti-
cal/electrical power penalty. SONET input jitter
tolerance requirements are shown in Figure 3.
The measurement condition is the input jitter am-
plitude which causes an equivalent of 1 dB power
penalty.
f0
f2
f3
ft
f1
Frequency
OC/STS
Level
f0
(Hz)
f1
(Hz)
f2
f3
ft
(Hz) (kHz) (kHz)
48
10
600
6000
100
1000
24
Jitter Transfer
12
10
10
30
30
300
300
25
250
65
Jitter transfer function is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 4.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 3 be applied.
3
6.5
Figure 4. Jitter Transfer Specification
Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed .01 U.I. rms when a serial data input
with no jitter is presented to the serial data inputs.
(See Table 4).
P
slope = -20 dB/decade
Jitter
Transfer
Acceptable
Range
fc
Frequency
OC/STS
fc
(KHz)
P
(dB)
Level1,2
48
24
12
3
2000
0.1
500
225
0.1
0.1
1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995.
2. ITU-T Recommendations: G.958.
January 22, 1999 / Revision A
4
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 2. Pin Assignment and Descriptions
Pin Name
Level
I/O
Pin#
Description
SERDATIP
SERDATIN
Diff.
PECL
5
6
Serial Data In. (Internal Termination.) Clock is recovered from the
transitions on these inputs.
I
I
Test Input Signal used for production test. Leave open for normal
operation.
TESTEN
TTL
1
Signal Detect. Active Low. A single-ended 10K PECL input to be
driven by the external optical receiver module to indicate a loss of
received optical power. When SDN is inactive, the data on the
Serial Data In (SERDATIP/N) pins will be internally forced to a
constant zero, and the PLL will be forced to lock to the REFCLK
inputs. When SDN is active, data on the SERDATIP/N pins will be
processed normally. If not used, leave open.
SDN
PECL
I
I
11
Reference Clock. 155 MHz input used to establish the initial
operating frequency of the clock recovery PLL and also used as
a standby clock in the absence of data, during reset or when SDN
is inactive.
REFCLKP
REFCLKN
Diff.
PECL
8
9
CAP1
CAP2
28
27
Loop Filter Capacitor. The loop filter capacitor and resistors are
connected to these pins.
I
I
Lock to Reference. Active Low. When active, the serial clock
output will be forced to lock to the local reference clock input
[REFCLK].
LCKREFN
TTL
10
RATESEL0
RATESEL1
31
24
TTL
I
I
Selects the operating mode (See Table 1).
Resets digital circuitry. Used for testing. To be open during
normal operation.
RESET
SPECL
32
Serial Data Out. This signal is the delayed version of the incoming
data stream (SERDATI) updated on the falling edge of Serial
Clock Out (SERCLKOP).
SERDATOP
SERDATON
19
18
CML
CML
TTL
O
O
O
SERCLKOP
SERCLKON
23
22
Serial Clock Out. This signal is phase aligned with Serial Data Out
(SERDATOP/N). (See Figure 7.)
Lock Detect. Clock recovery indicator. Set high when the internal
clock recovery has locked onto the incoming data stream.
LOCKDET is an asynchronous output.
LOCKDET
16
VCOD32
BYPASS
TTL
TTL
O
I
17
20
VCO clock divided by 32.
Bypass Enable. Active High. Used during production test to
bypass the VCO in the PLL. Tie to ground for normal operation.
January 22, 1999 / Revision A
5
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 2. Pin Assignment and Descriptions (Continued)
Pin Name
Level
I/O
Pin#
Description
2
29
AVCC
+5V
Analog power supply.
3
4
21
30
AVEE
VCC
GND
Analog GND connection.
Power Supply.
12
14
25
+5V
13
15
26
VEE
NC
GND
Ground connection.
No connection.
7
January 22, 1999 / Revision A
6
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 5. S3050 Pinout-32 LLCC
RATESEL1
SERCLKOP
SERCLKON
AVEE
TESTEN
AVCC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
AVEE
AVEE
SERDATIP
SERDATIN
NC
S3050
BYPASS
SERDATOP
SERDATON
VCOD32
REFCLKP
Table 3. Thermal Management (32 LLCC Package)
Symbol
Θja
Description
Air Flow
Value
33
Units
Thermal resistance from junction to ambient in still air
Thermal resistance from junction to ambient
Thermal resistance from junction to ambient
Thermal resistance from junction to ambient
Thermal resistance from junction to ambient
Still Air
˚ C/W
˚ C/W
˚ C/W
˚ C/W
˚ C/W
Θja
100 LFPM
200 LFPM
300 LFPM
400 LFPM
31
Θja
29
Θja
28
Θja
27
January 22, 1999 / Revision A
7
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 6. 32 LLCC Package
Top View
Bottom View
Note: The S3050 package is equipped with an embedded conductive heatsink on the bottom (board side). Active circuitry and vias should not
appear in the area immediately under the package. This heatsink is electrically biased to the Vee potential of the S3050. For optimum thermal
management, a foil surface at ground (or Vee if other than ground) is recommended immediately under the package, and connected with
multiple vias to the internal plane(s) of similar potential. Thermally conductive epoxy or other conductive interposer can be used to establish a
good thermal dissipation path.
January 22, 1999 / Revision A
8
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 4. Performance Specifications
Parameter
Min
Typ
Max
Units
Condition
Nominal VCO
Center Frequency
2.5
±12%
GHz
Data Output Jitter with VCO
locked to REFCLK
STS-12
155 MHz Ref. Clk.
0.01
0.01
UI (rms)
UI (rms)
rms jitter, SDN active.
Data Output Jitter with VCO
locked to SERDATIP/N
STS-48
With no jitter on serial data inputs.
Reference Clock Frequency
Tolerance
-100
+100
ppm
Capture Range
Lock Range
±200ppm
±12%
With respect to fixed reference
frequency
Minimum transition density of
20%
Acquisition Lock Time
16
µsec
With device already powered up
and valid ref. clk.
Reference Clock
Input Duty Cycle
30%
70%
% of UI
Reference Clock Rise & Fall
Times
1.0
ns
ps
20% to 80% of amplitude
20% to 80%, 50Ω load,
1 pf cap
CML Output Rise & Fall Times
100
600
150
Frequency difference at which
out of lock is declared
(REFCLK compared to the
divided down VCO clock)
488
244
732
366
ppm
ppm
Frequency difference at which
receive PLL is declared in lock
(REFCLK compared to the
divided down VCO clock)
300
tSU
100
300
500
OC-48
OC-24
OC-12
OC-3
ps
ps
2500
tH
100
300
500
OC-48
OC-24
OC-12
OC-3
2500
January 22, 1999 / Revision A
9
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 5. Recommended Operating Conditions
Parameter
Min
-40
Typ
Max
+851
+70
Unit
˚ C
˚ C
˚ C
V
Ambient Temperature under Bias (industrial)
Ambient Temperature under Bias (commercial)
Junction Temperature under Bias
Voltage on VCC with Respect to GND
Voltage on Any TTL Input Pin
Voltage on Any PECL Input Pin
ICC Supply Current
0
-10
+130
5.25
VCC
VCC
342
4.75
0.0
5.0
V
VCC -2
V
251
mA
1. Maximum specification for case temperature at 85˚C.
Table 6. Absolute Maximum Ratings
Parameter
Min
Typ
Max
Unit
Case Temperature under Bias
Junction Temperature under Bias
Storage Temperature
-55
-55
+125
+150
+150
+7.0
+5.5
VCC
20
˚ C
˚ C
˚ C
V
-65
Voltage on VCC with Respect to GND
Voltage on any TTL Input Pin
Voltage on any PECL Input Pin
TTL Output Sink Current
-0.5
-0.5
V
VCC -2.0
V
mA
mA
V
TTL Output Source Current
Static Discharge Voltage1
10
500
1. Except for CAP1, CAP2, SERDATIP/N, SERCLKOP/N and SERDATOP/N.
Figure 7. Receiver Output Timing Diagram
Duty Cycle MAX
Duty Cycle MIN
50%
SERCLKOP
tS
tH
SERDATOP/N
Note: Output propagation delay time of high speed CML outputs is the time in pico seconds from the cross-over point of the
reference signal to the cross-over point of the output.
January 22, 1999 / Revision A
10
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Table 7. Serial Input/Output DC Characteristics1
(TA = -40°C to +85°C, VCC = 5 V ±5%)
Symbol
Parameter
Conditions
Signal Name
Min
Max
Unit
Guaranteed Input LOW Voltage
for all single ended inputs
2
V
Input LOW Voltage
VCC -2.00 VCC -1.47
VCC -1.18 VCC -0.80
VCC -2.00 VCC -0.70
VCC -1.75 VCC -0.45
Volts
IL
Guaranteed Input HIGH Voltage
for all single ended inputs
2
V
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input DIFF Voltage
Volts
Volts
Volts
Volts
IH
Guaranteed Input LOW Voltage
for all differential inputs
2
V
IL
Guaranteed Input HIGH Voltage
for all differential inputs
2
V
IH
Guaranteed Input DIFF Voltage
for all differential inputs
2
V
0.25
1.40
ID
600
5.4
uA
SDN, TESTSIG, RESET
SERDATIP/N
0
V
= MAX, V = Vcc -2V
IL
cc
I
Input LOW Current
IL
V
= MAX, V
= 0.5V
DIFF
3.0
mA
cc
REFCLKP
REFCLKN
SDN, TESTSIG, RESET
V
V
= MAX, V =Vcc -2V
IL
100
100
4.0
300
500
6.4
uA
uA
mA
cc
= MAX, V =Vcc -0.80V
IH
cc
cc
I
Input HIGH Current
IH
V
= MAX, V
= 0.5V
DIFF
SERDATIP/N
REFCLKP
REFCLKN
Vcc = MAX, V =Vcc -0.80V
IH
150
350
uA
100Ω Line to Line
100Ω Line to Line
100Ω Line to Line
V
Output LOW Voltage
Output HIGH Voltage
VCC -1.2 VCC -.5
VCC -.4 VCC -.1
Volts
Volts
mV
OL
V
OH
∆V
Output Single-Ended
Voltage
400
800
SERDATOP/N
SERCLKOP/N
OUTSINGLE
1. These conditions will be met with no airflow.
2. These input levels provide a zero-noise immunity and should only be tested in a static, noise-free environment.
Table 8. TTL Input/Output DC Characteristics1
(TA = -40°C to +85°C, VCC = 5 V ±5%)
Symbol
Parameter
Test Conditions
Min
Max
Unit
Volts
Volts
2
IL
V
Input LOW Voltage
Guaranteed Input LOW Voltage for all inputs
Guaranteed Input HIGH Voltage for all inputs
0.8
2
V
Input HIGH Voltage
2.0
-1
IH
I
Input LOW Current
mA
uA
V
V
V
V
V
V
= MAX, V = 0.5V
IN
IL
CC
CC
CC
CC
CC
CC
I
Input HIGH Current
= MAX, V = 2.7V
IN
50.0
1.0
IH
I
I
Input HIGH Current at Max VCC
mA
= MAX, V = 5.25V
IN
I
Output Short Circuit Current
Input Clamp Diode Voltage
TTL Output LOW Voltage
= MAX, V
= 0.5V
-40
-5.0
mA
Volts
Volts
Volts
OS
OUT
= MIN, I = -18.0mA
V
-1.2
IK
IN
V
= MIN, I
= MIN, I
= 4mA
0.5
OL
OL
V
TTL Output HIGH Voltage
2.4
V
= -1.0mA
OH
CC
OH
1. These conditions will be met with no airflow.
2. These input levels provide a zero-noise immunity and should only be tested in a static, noise-free environment.
January 22, 1999 / Revision A
11
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 8. +5V Differential PECL Driver to S3050 Input Direct Coupled Termination
+5V
+5V
Vcc -.4V
330Ω
330Ω
100Ω
Vcc -.4V
S3050
SERDATIP/N
Figure 9. +5V Differential PECL Driver to S3050 Input AC Coupled Termination
+5V
+5V
Vcc -.4V
.01µf
330Ω
100Ω
330Ω
.01µf
Vcc -.4V
S3050
SERDATIP/N
Figure 10. S3050 to S3042/S3044 Terminations
+5V
+3.3V
Vcc -.65
100Ω
.01µf
.01µf
Vcc -.65
S3050
SERDATOP/N
SERCLKOP/N
S3042/44
SERDATIP/N
SERCLKIP/N
January 22, 1999 / Revision A
12
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 11. +3.3V Single Ended LVPECL Driver to S3050 Reference Clock
Input AC Coupled Termination
+3.3V
+5V
Vcc -1.3V
.01µf
150Ω
50Ω
.01µf
Vcc -1.3V
S3041/43
155MCK
S3050
REFCLKP/N
Figure 12. +5V Differential PECL Driver to S3050 Reference Clock
Input AC Coupled Termination
+5V
+5V
Vcc -1.3V
.01µf
.01µf
330Ω
330Ω
100Ω
Vcc -1.3V
155 MHZ
S3050
OSCILLATOR
REFCLKP/N
Figure 13. Loop Filter Capacitor Connections
39Ω
CAP1
CAP2
2.2 µf
39Ω
S3050
January 22, 1999 / Revision A
13
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Figure 14. SERDATIP/N Input Signal Minimum
Rise/Fall Time Requirement
Application Information
The rise and fall times of the input signal at
SERDATIP/N should be greater than 100 ps in order
to assure proper functionality of the input stage.
80% Peak
SERDATIP/N
20% Peak
100 ps Min
January 22, 1999 / Revision A
14
S3050
MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT
Ordering Information
GRADE
PART NO.
PACKAGE
S- Commercial / Industrial
3050
A – 32 LLCC
XXXX
Part Number
X
X
Grade
Package
Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121
Phone: (619) 450-9333 • (800)755-2622 • Fax: (619) 450-9885
http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and
advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it
convey any license under its patent rights nor the rights of others.
AMCC reserves the right to ship devices of higher grade in place of those of lower grade.
AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
AMCC is a registered trademark of Applied Micro Circuits Corporation.
Copyright ® 1999 Applied Micro Circuits Corporation
January 22, 1999 / Revision A
15
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