AM29DL320GB40EF_技术文档

Am29DL320G

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29JL032H (for TSOP packages) and S29PL032J (for FBGA packages) supersede AM29DL320G as

the factory-recommended migration path. Please refer to each respective datasheets for specifica-

tions and ordering information. Availability of this document is retained for reference and historical

purposes only.

April 2005

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 25769 Revision C Amendment +3 Issue Date May 25, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29DL320G

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

This product has been retired and is not recommended for designs. For new and current designs, S29JL032H (for TSOP packages) and S29PL032J (for FBGA packages) supersede

AM29DL320G as the factory-recommended migration path. Please refer to each respective datasheets for specifications and ordering information. Availability of this document is re-

tained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

Minimum 1 million write cycles guaranteed per sector

Simultaneous Read/Write operations

20 year data retention at 125°C

— Data can be continuously read from one bank while

executing erase/program functions in another bank

— Reliable operation for the life of the system

SOFTWARE FEATURES

— Zero latency between read and write operations

Flexible Bank^TMarchitecture

Data Management Software (DMS)

— AMD-supplied software manages data programming,

enabling EEPROM emulation

— Read may occur in any of the three banks not being

written or erased.

— Eases historical sector erase flash limitations

— Four banks may be grouped by customer to achieve

desired bank divisions.

Supports Common Flash Memory Interface (CFI)

256-byte SecSi™ (Secured Silicon) Sector

Erase Suspend/Erase Resume

— Factory locked and identifiable: 16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

— Suspends erase operations to allow reading from

other sectors in the same bank

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

— Customer lockable: One time programmable. Once

Unlock Bypass Program command

locked, data cannot be changed.

— Reduces overall programming time when issuing

multiple program command sequences

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

HARDWARE FEATURES

Any combination of sectors can be erased

Package options

— 63-ball FBGA

— 48-ball FBGA

— 48-pin TSOP

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

— 64-ball Fortified BGA

Top or bottom boot blocks

WP#/ACC input pin

Manufactured on 0.17 µm process technology

Compatible with JEDEC standards

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect

status

— Pinout and software compatible with

single-power-supply flash standard

— Acceleration (ACC) function accelerates program

timing

PERFORMANCE CHARACTERISTICS

Sector protection

High performance

— Access time as fast 70 ns

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

— Program time: 4 µs/word typical utilizing Accelerate

function

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

Publication# 25769

Rev: C Amendment/3

Issue Date: May 25, 2005

Refer to AMD’s Website (www.amd.com) for the latest information.

GENERAL DESCRIPTION

The Am29DL320G is a 32 megabit, 3.0 volt-only flash

memory device, organized as 2,097,152 words of 16

bits each or 4,194,304 bytes of 8 bits each. Word

mode data appears on DQ15–DQ0; byte mode data

appears on DQ7–DQ0. The device is designed to be

programmed in-system with the standard 3.0 volt V_CC

supply, and can also be programmed in standard

EPROM programmers.

32 Mbit Am29DL32x devices had a larger SecSi

Sector. Factory locked parts provide several options.

The SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both.

DMS (Data Management Software) allows systems

to remove EEPROM devices. by simplifying system

software: DMS performs all functions necessary to

modify data in file structures, instead of using sin-

gle-byte modifications. To write or update a particular

piece of data (a phone number or configuration data,

for example), the user only needs to state which piece

of data is to be updated, and where the updated data

is located in the system. This is an advantage com-

pared to systems where user-written software must

keep track of the old data location, status, logical to

physical translation of the data onto the Flash memory

device (or memory devices), and more. Using DMS,

user-written software does not need to interface with

the Flash memory directly. Instead, the user's software

accesses the Flash memory by calling one of only six

functions. AMD provides this software to simplify sys-

tem design and software integration efforts.

The device is available with an access time of 70, 90,

or 120 ns. The devices are offered in 48-pin TSOP,

48-ball or 63-ball FBGA packages, and 64-ball Forti-

fied BGA. Standard control pins—chip enable (CE#),

write enable (WE#), and output enable (OE#)—control

normal read and write operations, and avoid bus con-

tention issues.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into four banks, two 4 Mb banks with small and

large sectors, and two 12 Mb banks of large sectors.

Sector addresses are fixed, system software can be

used to form user-defined bank groups.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write timings.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

During an Erase/Program operation, any of the three

non-busy banks may be read from. Note that only two

banks can operate simultaneously. The device allows

a host system to program or erase in one bank, then

immediately and simultaneously read from the other

bank, with zero latency. This releases the system from

waiting for the completion of program or erase

operations.

The host system can detect whether a program or

erase operation is complete by using the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

The Am29DL320G can be organized as either a top or

bottom boot sector configuration.

Bank

Megabits

Sector Sizes

Eight 8 Kbyte/4 Kword,

Seven 64 Kbyte/32 Kword

Bank 1

4 Mb

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

Bank 2

Bank 3

Bank 4

12 Mb

4 Mb

Twenty-four 64 Kbyte/32 Kword

Eight 64 Kbyte/32 Kword

Am29DL320G Features

The SecSi^TM(Secured Silicon) Sector is an 256 byte

extra sector capable of being permanently locked by

AMD or customers. The SecSi Indicator Bit (DQ7) is

permanently set to a 1 if the part is factory locked,

and set to a 0 if customer lockable. This way, cus-

tomer lockable parts can never be used to replace a

factory locked part. Note that some previous AMD

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

2

Am29DL320G

TABLE OF CONTENTS

Sector Erase Command Sequence ..............................................26

Erase Suspend/Erase Resume Commands ................................27

Figure 5. Erase Operation .................................................................... 27

Table 13. Command Definitions ........................................................... 28

DQ7: Data# Polling ......................................................................29

Figure 6. Data# Polling Algorithm......................................................... 29

RY/BY#: Ready/Busy# ................................................................. 30

DQ6: Toggle Bit I ..........................................................................30

Figure 7. Toggle Bit Algorithm .............................................................. 30

DQ2: Toggle Bit II .........................................................................31

Reading Toggle Bits DQ6/DQ2 ....................................................31

DQ5: Exceeded Timing Limits ......................................................31

DQ3: Sector Erase Timer .............................................................31

Table 14. Write Operation Status .........................................................32

Figure 8. Maximum Negative Overshoot Waveform............................. 33

Figure 9. Maximum Positive Overshoot Waveform .............................. 33

Figure 10. I_CC1Current vs. Time (Showing Active and

Automatic Sleep Currents).................................................................... 35

Figure 11. Typical I_CC1vs. Frequency................................................... 35

Figure 12. Test Setup .......................................................................... 36

Figure 13. Input Waveforms and Measurement Levels ........................ 36

Figure 14. Read Operation Timings...................................................... 37

Figure 15. Reset Timings...................................................................... 38

Word/Byte Configuration (BYTE#) ...............................................39

Figure 16. BYTE# Timings for Read Operations .................................. 39

Figure 17. BYTE# Timings for Write Operations .................................. 39

Erase and Program Operations ...................................................40

Figure 18. Program Operation Timings ................................................ 41

Figure 19. Accelerated Program Timing Diagram ................................ 41

Figure 20. Chip/Sector Erase Operation Timings ................................. 42

Figure 21. Back-to-back Read/Write Cycle Timings ............................. 43

Figure 22. Data# Polling Timings (During Embedded Algorithms) ....... 43

Figure 23. Toggle Bit Timings (During Embedded Algorithms) ............ 44

Figure 24. DQ2 vs. DQ6 ....................................................................... 44

Temporary Sector Unprotect ........................................................45

Figure 25. Temporary Sector Unprotect Timing Diagram..................... 45

Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram 46

Alternate CE# Controlled Erase and Program Operations ...........47

Figure 27. Alternate CE# Controlled Write (Erase/Program)

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Special Package Handling Instructions ..........................................6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Device Bus Operations .............................................................9

Word/Byte Configuration ................................................................ 9

Requirements for Reading Array Data ...........................................9

Writing Commands/Command Sequences ..................................10

Simultaneous Read/Write Operations

with Zero Latency .........................................................................10

Standby Mode .............................................................................. 10

Automatic Sleep Mode .................................................................10

RESET#: Hardware Reset Pin .....................................................11

Output Disable Mode ...................................................................11

Table 2. Top Boot Sector Addresses ...................................................12

Table 3. Top Boot SecSi^TMSector Addresses ..................................... 13

Table 4. Bottom Boot Sector Addresses ...............................................14

Table 5. Bottom Boot SecSi^TMSector Addresses................................ 15

Autoselect Mode .......................................................................... 16

Table 6. Autoselect Codes, (High Voltage Method) .............................16

Sector/Sector Block Protection and Unprotection ........................ 17

Table 7. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection ...................................................................17

Table 8. Bottom Boot Sector/Sector Block Addresses

for Protection/Unprotection ...................................................................17

Write Protect (WP#) .....................................................................18

Temporary Sector Unprotect ........................................................18

Figure 1. Temporary Sector Unprotect Operation................................. 18

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms ............................................................ 19

SecSi^TM(Secured Silicon) Sector

Flash Memory Region ..................................................................20

Figure 3. SecSi Sector Protect Verify.................................................... 21

Hardware Data Protection ............................................................21

Common Flash Memory Interface (CFI) . . . . . . . 21

Table 9. CFI Query Identification String................................................ 22

Table 10. System Interface String......................................................... 22

Table 11. Device Geometry Definition .................................................. 23

Table 12. Primary Vendor-Specific Extended Query ............................ 23

Reading Array Data ......................................................................24

Reset Command ..........................................................................24

Autoselect Command Sequence ..................................................24

Enter SecSi^TMSector/Exit SecSi Sector

Command Sequence ...................................................................25

Byte/Word Program Command Sequence ...................................25

Figure 4. Program Operation ................................................................ 26

Chip Erase Command Sequence .................................................26

Operation Timings ................................................................................ 48

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 49

TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 49

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm .50

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm .........................51

TS 048—Thin Small Outline Package ..........................................52

Am29DL320G

3

PRODUCT SELECTOR GUIDE

Part Number

Am29DL320G

Speed Rating

Standard Voltage Range: V_CC= 2.7–3.6 V

70

30

90

40

120

50

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

BLOCK DIAGRAM

V

CC

OE# BYTE#

SS

Mux

Bank 1

Bank 1 Address

A20–A0

X-Decoder

Bank 2 Address

RY/BY#

Bank 2

X-Decoder

A20–A0

RESET#

STATE

CONTROL

&

Status

WE#

DQ15–DQ0

COMMAND

REGISTER

CE#

BYTE#

WP#/ACC

Control

Mux

DQ15–DQ0

X-Decoder

Bank 3

Bank 3 Address

Bank 4 Address

X-Decoder

Bank 4

A20–A0

Mux

4

Am29DL320G

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

48-Pin Standard TSOP

A19

A20

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

WP#/ACC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

63-Ball Fine-pitch BGA (8 x 14 mm)

L8

M8

A8

B8

Top View, Balls Facing Down

NC

NC*

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

V_SS

NC

NC*

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

NC

A19

DQ5

DQ12

DQ4

C4 D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

A2

V_SS

CE#

OE#

NC*

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

Am29DL320G

5

CONNECTION DIAGRAMS

48-Ball Fine-pitch BGA (6 x 12 mm)

Top View, Balls Facing Down

C7

D7

E7

F7

G7

H7

J7

K7

V_SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

NC

A19

DQ5

DQ12

DQ4

C4 D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

V_SS

CE#

OE#

64-Ball Fortified BGA (11 x 13 mm)

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

H8

RFU

V_IO

V_SS

RFU

A7

B7

C7

D7

E7

F7

G7

H7

A13

A12

A14

A15

A16

BYTE#

DQ15

V_SS

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

DQ6

A10

A11

DQ7

DQ14

DQ13

A5

B5

C5

D5

E5

F5

G5

H5

WE# RESET#

A21

A19

DQ5

DQ12

V_CC

DQ4

A4 B4

C4

D4

E4

F4

G4

H4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

CE#

OE#

V_SS

A1

B1

C1

D1

E1

F1

G1

H1

RFU

V_IO

RFU

compromised if the package body is exposed to

temperatures above 150°C for prolonged periods of

time.

Special Package Handling Instructions

Special handling is required for Flash Memory products

in molded packages (TSOP, BGA, SSOP, PLCC,

PDIP). The package and/or data integrity may be

6

Am29DL320G

PIN DESCRIPTION

LOGIC SYMBOL

A20–A0

= 21 Addresses

21

DQ14–DQ0 = 15 Data Inputs/Outputs

A20–A0

16 or 8

DQ15/A-1

= DQ15 (Data Input/Output, word

mode), A-1 (LSB Address Input, byte

mode)

DQ15–DQ0

(A-1)

CE#

OE#

CE#

OE#

WE#

= Chip Enable

= Output Enable

= Write Enable

WE#

WP#/ACC

RESET#

BYTE#

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RY/BY#

RESET#

BYTE#

RY/BY#

V_CC

= Hardware Reset Pin, Active Low

= Selects 8-bit or 16-bit mode

= Ready/Busy Output

= 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_SS

NC

= Device Ground

= Pin Not Connected Internally

Am29DL320G

7

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29DL320G

T

70

E

I

OPTIONAL PROCESSING

Blank = Standard Processing

N

=

16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-free Package

F

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

WD

WM

PC

63-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 8 x 14 mm package (FBD063)

48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 12 mm package (FBD048)

64-Ball Fortified-Pitch Ball Grid Array (FBGA)

1.00 mm pitch, 11 x 13 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top boot sectors

Bottom boot sectors

DEVICE NUMBER/DESCRIPTION

Am29DL320G

32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29DL320GT70,

AM29DL320GB70

D320GT70V,

D320GB70V

AM29DL320GT90,

AM29DL320GB90

AM29DL320GB70

WDI,

EI, EIN, EF

AM29DL320GT90,

AM29DL320GB90

WDIN, D320GT90V,

I, F

AM29DL320GT120,

AM29DL320GB120

WDF,

D320GB90V

WDFN

AM29DL320GT120,

AM29DL320GB120

D320GT12V,

D320GB12V

Valid Combinations

AM29DL320GT70,

AM29DL320GB70

D320GT70U,

D320GB70U

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

WMI,

AM29DL320GT90,

AM29DL320GB90

WMIN,” D320GT90U,

WMF, D320GB90U

I, F

WMFN

AM29DL320GT120,

AM29DL320GB120

D320GT12U,

D320GB12U

Valid Combinations for Fortified BGA Packages

Order Number Package Marking

AM29DL320GT70, D320GT70P,

AM29DL320GB70

D320GB70P

AM29DL320GT90,

AM29DL320GB90

PCI,

PCF

D320GT90P,

D320GB90P

I, F

AM29DL320GT120,

AM29DL320GB120

D320GT12P,

D320GB12P

8

Am29DL320G

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Device Bus Operations

DQ15–DQ8

BYTE#

Addresses

(Note 2)

BYTE#

= V_IH

DQ7–

DQ0

Operation

CE# OE# WE# RESET# WP#/ACC

= V_IL

Read

Write

L

H

L

H

L/H

A_IN

D_OUT

D_IN

D_OUT

D_IN

DQ8–DQ14 =

High-Z, DQ15 = A-1

H

(Note 3)

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

H

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

L/H

X

High-Z

X

SA, A6 = L,

A1 = H, A0 = L

Sector Protect (Note 2)

L

X

H

X

L

X

V_ID

L/H

X

D_IN

SA, A6 = H,

A1 = H, A0 = L

Sector Unprotect (Note 2)

(Note 3)

Temporary Sector

Unprotect

A_IN

D_IN

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 8.5–12.5 V, V_HH= 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A20:A0 in word mode (BYTE# = V_IH), A20:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

3. If WP#/ACC = V_IL, the two outermost boot sectors remain protected. If WP#/ACC = V_IH, the two outermost boot sector

protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block

Protection and Unprotection”. If WP#/ACC = V_HH, all sectors will be unprotected.

Word/Byte Configuration

Requirements for Reading Array Data

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ15–DQ0 are active and controlled by

CE# and OE#.

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH. The BYTE# pin determines

whether the device outputs array data in words or

bytes.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ7–DQ0 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

Am29DL320G

9

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

mal operation. Note that the WP#/ACC pin must not be

at V_HHfor operations other than accelerated program-

ming, or device damage may result. In addition, the

WP#/ACC pin must not be left floating or unconnected;

inconsistent behavior of the device may result.

See “Requirements for Reading Array Data” for more

information. Refer to the AC Read-Only Operations

table for timing specifications and to Figure 14 for the

timing diagram. I_CC1in the DC Characteristics table

represents the active current specification for reading

array data.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

Simultaneous Read/Write Operations

with Zero Latency

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more in-

formation.

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 21 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. I_CC6and I_CC7in the DC Characteristics table

represent the current specifications for read-while-pro-

gram and read-while-erase, respectively.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The

“Word/Byte Configuration” section has details on pro-

gramming data to the device using both standard and

Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies. The device address

space is divided into two banks: Bank 1 contains the

boot/parameter sectors, and Bank 2 contains the

larger, code sectors of uniform size. A “bank address”

is the address bits required to uniquely select a bank.

Similarly, a “sector address” is the address bits re-

quired to uniquely select a sector.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC± 0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I_CC3in the DC Characteristics table represents the

standby current specification.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

V_HHfrom the WP#/ACC pin returns the device to nor-

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

+

10

Am29DL320G

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

I_CC5in the DC Characteristics table represents the

automatic sleep mode current specification.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

I_CC4in the DC Characteristics table represents the

reset current. Also refer to AC Characteristics tables

for RESET# timing parameters and to Figure 15 for the

timing diagram.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will

be greater.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

Am29DL320G

11

Table 2. Top Boot Sector Addresses

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA0

SA1

000000xxx

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

64/32

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

000000h–07FFFh

008000h–0FFFFh

010000h–17FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

12

Am29DL320G

Table 2. Top Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

110000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

64/32

8/4

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

3F0000h–3F1FFFh

3F2000h–3F3FFFh

3F4000h–3F5FFFh

3F6000h–3F7FFFh

3F8000h–3F9FFFh

3FA000h–3FBFFFh

3FC000h–3FDFFFh

3FE000h–3FFFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1F8FFFh

1F9000h–1F9FFFh

1FA000h–1FAFFFh

1FB000h–1FBFFFh

1FC000h–1FCFFFh

1FD000h–1FDFFFh

1FE000h–1FEFFFh

1FF000h–1FFFFFh

8/4

Note: The address range is A20:A-1 in byte mode (BYTE#=V_IL) or A20:A0 in word mode (BYTE#=V_IH). The bank address bits are A20–A18 for

Am29DL322, A20 and A19 for Am29DL323, and A20 for Am29DL324.

Table 3. Top Boot SecSi^TMSector Addresses

Sector Address

A20–A12

Sector Size

(Bytes/Words)

(x8)

(x16)

Address Range

Device

Address Range

Am29DL32xGT

111111xxx

256/128

3FE000h–3FE0FFh

1FF000h–1FF07Fh

Am29DL320G

13

Table 4. Bottom Boot Sector Addresses

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA0

SA1

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

8/4

000000h–001FFFh

002000h–003FFFh

004000h–005FFFh

006000h–007FFFh

008000h–009FFFh

00A000h–00BFFFh

00C000h–00DFFFh

00E000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

8/4

SA2

8/4

SA3

8/4

SA4

8/4

SA5

8/4

SA6

8/4

SA7

8/4

SA8

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

64/32

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

14

Am29DL320G

Table 4. Bottom Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

(x16)

Address Range

Sector

Address Range

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

111000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111xxx

64/32

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

3F0000h–3FFFFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Note: The address range is A20:A-1 in byte mode (BYTE#=V_IL) or A20:A0 in word mode (BYTE#=V_IH). The bank address bits

are A20–A18 for Am29DL322, A20 and A19 for Am29DL323, and A20 for Am29DL324.

Table 5. Bottom Boot SecSi^TMSector Addresses

Sector Address

A20–A12

Sector Size

(Bytes/Words)

(x8)

(x16)

Address Range

Device

Address Range

Am29DL32xGB

000000xxx

256/128

000000h–0000FFh

00000h–00007Fh

Am29DL320G

15

Table 6. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order address bits (see Table 2). Table 6

shows the remaining address bits that are don’t care.

When all necessary bits have been set as required,

the programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 13. This method

does not require V_ID. Refer to the Autoselect Com-

mand Sequence section for more information.

When using programming equipment, the autoselect

mode requires V_ID(8.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in

Table 6. Autoselect Codes, (High Voltage Method)

DQ15 to DQ8

A20 A11

to to

A8

to

A5

to

DQ7

to

BYTE# BYTE#

Description

CE# OE# WE# A12 A10 A9 A7 A6 A4

A1 A0

= V_IH

= V_IL

DQ0

A3

A2

Manufacturer ID:

AMD

V_ID

L

H

BA

X

L

X

L

X

01h

V_ID

Read Cycle 1

Read Cycle 2

Read Cycle 3

L

H

BA

X

L

X

L

H

L

H

L

H

L

22h

X

7Eh

0Ah

H

01h (T), 00h (B)

Sector Protection

Verification

01h (protected),

00h (unprotected)

V_ID

L

H

SA

BA

X

L

X

H

L

X

82h (factory locked),

02h (not factory

locked)

SecSi™ Indicator

Bit (DQ7)

H

Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X =

Don’t care.

Notes:

1. The bank address bits are A20–A18.

2. The device ID must be read across three cycles.

16

Am29DL320G

Table 8. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/Sector Block Protection and

Unprotection

Sector/Sector Block

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Tables

2 and 4).

Sector

A20–A12

Size

SA70

111111XXX

64 Kbytes

111110XXX,

111101XXX,

111100XXX

SA69-SA67

192 (3x64) Kbytes

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

SA66-SA63

SA62-SA59

SA58-SA55

SA54-SA51

SA50-SA47

SA46-SA43

SA42-SA39

SA38-SA35

SA34-SA31

SA30-SA27

SA26-SA23

SA22–SA19

SA18-SA15

SA14-SA11

1110XXXXX

1101XXXXX

1100XXXXX

1011XXXXX

1010XXXXX

1001XXXXX

1000XXXXX

0111XXXXX

0110XXXXX

0101XXXXX

0100XXXXX

0011XXXXX

0010XXXXX

0001XXXXX

256 (4x64) Kbytes

Table 7. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection

Sector/

Sector

A20–A12

Sector Block Size

SA0

000000XXX

64 Kbytes

000001XXX,

000010XXX

000011XXX

SA1-SA3

192 (3x64) Kbytes

SA4-SA7

0001XXXXX

0010XXXXX

0011XXXXX

0100XXXXX

0101XXXXX

0110XXXXX

0111XXXXX

1000XXXXX

1001XXXXX

1010XXXXX

1011XXXXX

1100XXXXX

1101XXXXX

1110XXXXX

256 (4x64) Kbytes

000011XXX,

000010XXX,

000001XXX

SA8-SA11

SA10-SA8

192 (3x64) Kbytes

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

000000111

000000110

000000101

000000100

000000011

000000010

000000001

000000000

8 Kbytes

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 26 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect

write cycle.

111100XXX,

111101XXX,

111110XXX

SA60-SA62

192 (3x64) Kbytes

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

8 Kbytes

The sector unprotect algorithm unprotects all sectors

in parallel. All previously protected sectors must be in-

dividually re-protected. To change data in protected

sectors efficiently, the temporary sector unprotect

function is available. See “Temporary Sector Unpro-

tect”.

Am29DL320G

17

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices.

Publication number 22244 contains further details;

contact an AMD representative to request a copy.

Temporary Sector Unprotect

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (Tables 2

and 4).

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 1 shows the algorithm, and

Figure 25 shows the timing diagrams, for this feature.

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode sec-

tion for details.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting certain boot sectors without

using V_ID. This function is one of two provided by the

WP#/ACC pin.

START

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in the two

“outermost” 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected

using the method described in “Sector/Sector Block

Protection and Unprotection”. The two outermost 8

Kbyte boot sectors are the two sectors containing the

lowest addresses in a bottom-boot-configured device,

or the two sectors containing the highest addresses in

a top-boot-configured device.

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether the two outermost 8K Byte

boot sectors were last set to be protected or unpro-

tected. That is, sector protection or unprotection for

these two sectors depends on whether they were last

protected or unprotected using the method described

in “Sector/Sector Block Protection and Unprotection”.

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

1. All protected sectors unprotected (If WP#/ACC = V_IL,

outermost boot sectors will remain protected).

2. All previously protected sectors are protected once

again.

Figure 1. Temporary Sector Unprotect Operation

18

Am29DL320G

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 μs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Write 60h to any

address with

A6 = 1, A1 = 1,

A0 = 0

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms

Am29DL320G

19

SecSi^TM(Secured Silicon) Sector

Flash Memory Region

In devices that have an ESN, a Bottom Boot device will

have the 16-byte ESN at addresses

000000h–000007h

in

word

mode

(or

The SecSi (Secured Silicon) Sector feature provides a

256-byte Flash memory region that enables perma-

nent part identification through an Electronic Serial

Number (ESN). The SecSi Sector uses a SecSi Sector

Indicator Bit (DQ7) to indicate whether or not the

SecSi Sector is locked when shipped from the factory.

This bit is permanently set at the factory and cannot

be changed, which prevents cloning of a factory locked

part. This ensures the security of the ESN once the

product is shipped to the field.

000000h–00000Fh in byte mode). In the Top Boot de-

vice the ESN will be at addresses

1FF000h–1FF007Fh in word mode (or addresses

3FE000h–3FE0FFh in byte mode).

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the SecSi Sector permanently locked.

Contact an AMD representative for details on using

AMD’s ExpressFlash service.

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to utilize the that

sector in any manner they choose. The customer-lock-

able version has the SecSi (Secured Silicon) Sector

Indicator Bit permanently set to a “0.” Thus, the SecSi

Sector Indicator Bit prevents customer-lockable de-

vices from being used to replace devices that are fac-

tory locked.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional 256-byte Flash mem-

ory space, expanding the size of the available Flash

array. Additionally, note the difference in the loca-

tion of the ESN compared to previous Am29DL32x

top boot factory locked devices. The SecSi Sector

is one-time programmable, may not be erased, and

can be locked only once. Note that the accelerated

programming (ACC) and unlock bypass functions are

not available when programming the SecSi Sector.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi^TMSector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the boot sectors.

The SecSi Sector area can be protected using one of

the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

■ To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is available preprogrammed with one of the fol-

lowing:

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

The SecSi Sector protection must be used with cau-

tion since, once protected, there is no procedure avail-

able for unprotecting the SecSi Sector area and none

of the bits in the SecSi Sector memory space can be

modified in any way.

■ A random, secure ESN only

■ Customer code through the ExpressFlash service

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

20

Am29DL320G

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

START

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# =

V_IHor V_ID

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

Wait 1 μs

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

COMMON FLASH MEMORY INTERFACE

(CFI)

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The

system can read CFI information at the addresses

given in Tables 9–12. To terminate reading CFI data,

the system must write the reset command. The CFI

Query mode is not accessible when the device is exe-

cuting an Embedded Program or Embedded Erase al-

gorithm.

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 13 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 9–12. The

system must write the reset command to return the

device to reading array data.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Am29DL320G

21

Table 9. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

Table 10. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data Description

V_CCMin. (write/erase)

0027h

1Bh

1Ch

36h

38h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

22

Am29DL320G

Table 11. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0016h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0002h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

003Eh

0000h

0001h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Table 12. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Silicon Revision Number

00h = 0.23 µm, 01h = 0.17 µm

45h

46h

47h

48h

49h

4Ah

4Bh

8Ah

8Ch

8Eh

90h

92h

94h

96h

0001h

0002h

0001h

0004h

0038h

0000h

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

Simultaneous Operation

Number of Sectors (excluding Bank 1)

Burst Mode Type

00 = Not Supported, 01 = Supported

Am29DL320G

23

Addresses

(Word Mode)

(Byte Mode)

Data

Description

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Ch

4Dh

98h

9Ah

0000h

ACC (Acceleration) Supply Minimum

0085h

0095h

000Xh

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

4Eh

4Fh

9Ch

9Eh

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

02h = Bottom Boot Device, 03h = Top Boot Device

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 13 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence may

place the device in an unknown state. A reset com-

mand is required to return the device to reading array

data.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure be-

gins, however, the device ignores reset commands

until the operation is complete.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to the read mode. If the

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, however,

the device ignores reset commands until the operation

is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. After completing a programming operation

in the Erase Suspend mode, the system may once

again read array data with the same exception. See

the Erase Suspend/Erase Resume Commands sec-

tion for more information.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

next section, Reset Command, for more information.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 13 shows the address and data requirements.

This method is an alternative to that shown in Table 6,

which is intended for PROM programmers and re-

quires V_IDon address pin A9. The autoselect com-

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The Read-Only Operations table provides the read pa-

rameters, and Figure 14 shows the timing diagram.

24

Am29DL320G

mand sequence may be written to an address within a

bank that is either in the read or erase-suspend-read

mode. The autoselect command may not be written

while the device is actively programming or erasing in

the other bank.

system is not required to provide further controls or

timings. The device automatically provides internally

generated program pulses and verifies the pro-

grammed cell margin. Table 13 shows the address and

data requirements for the byte program command se-

quence.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the autose-

lect mode. The system may read at any address within

the same bank any number of times without initiating

another autoselect command sequence:

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refer to the Write Operation

Status section for information on these status bits.

■ A read cycle at address (BA)XX00h (where BA is

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity.

the bank address) returns the manufacturer code.

■ A read cycle at address (BA)XX01h in word mode

(or (BA)XX02h in byte mode) returns the device

code.

■ A read cycle to an address containing a sector ad-

dress (SA) within the same bank, and the address

02h on A7–A0 in word mode (or the address 04h on

A6–A-1 in byte mode) returns 01h if the sector is

protected, or 00h if it is unprotected. (Refer to Table

2 for valid sector addresses).

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

Unlock Bypass Command Sequence

Enter SecSi^TMSector/Exit SecSi Sector

Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write

cycle containing the unlock bypass command, 20h.

That bank then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass pro-

gram command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Table 13 shows the require-

ments for the command sequence.

The SecSi Sector region provides a secured data area

containing a random, sixteen-byte electronic serial

number (ESN). The system can access the SecSi

Sector region by issuing the three-cycle Enter SecSi

Sector command sequence. The device continues to

access the SecSi Sector region until the system is-

sues the four-cycle Exit SecSi Sector command se-

quence. The Exit SecSi Sector command sequence

returns the device to normal operation. The SecSi

Sector is not accessible when the device is executing

an Embedded Program or Embedded Erase algo-

rithm. Table 13 shows the address and data require-

ments for both command sequences. See also

“SecSi^{T M}(Secured Silicon) Sector Flash

Memory Region” for further information. Note that the

ACC function and unlock bypass modes are unavail-

able when the SecSi Sector is enabled.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the bank

address and the data 90h. The second cycle need

only contain the data 00h. The bank then returns to

the read mode.

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

Am29DL320G

25

V

_HHon the WP#/ACC pin, the device automatically en-

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 13

shows the address and data requirements for the chip

erase command sequence.

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Write Operation Status sec-

tion for information on these status bits.

Figure 4 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 18 for timing diagrams.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

START

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 20 section for timing diagrams.

Write Program

Command Sequence

Data Poll

from System

Sector Erase Command Sequence

Embedded

Program

algorithm

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 13 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

in progress

Verify Data?

No

Yes

No

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Increment Address

Last Address?

Yes

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands (for sectors within the same bank) may be writ-

ten. Loading the sector erase buffer may be done in

any sequence, and the number of sectors may be from

one sector to all sectors. The time between these ad-

ditional cycles must be less than 50 µs, otherwise era-

sure may begin. Any sector erase address and

command following the exceeded time-out may or may

not be accepted. It is recommended that processor in-

terrupts be disabled during this time to ensure all com-

mands are accepted. The interrupts can be re-enabled

after the last Sector Erase command is written. Any

command other than Sector Erase or Erase Sus-

Note: See Table 13 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

26

Am29DL320G

pend during the time-out period resets that bank

to the read mode. The system must rewrite the com-

mand sequence and any additional addresses and

commands.

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Byte Program operation.

Refer to the Write Operation Status section for more

information.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing bank. The system can de-

termine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer

to the Write Operation Status section for information

on these status bits.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

Autoselect Mode and Autoselect Command Sequence

sections for details.

To resume the sector erase operation, the system

must write the Erase Resume command. The bank

address of the erase-suspended bank is required

when writing this command. Further writes of the Re-

sume command are ignored. Another Erase Suspend

command can be written after the chip has resumed

erasing.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 20 section for timing diagrams.

START

Write Erase

Command Sequence

(Notes 1, 2)

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the 50 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

Yes

Erasure Completed

Notes:

1. See Table 13 for erase command sequence.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

2. See the section on DQ3 for information on the sector

erase timer.

Figure 5. Erase Operation

Am29DL320G

27

Table 13. Command Definitions

Bus Cycles (Notes 2–5)

Third Fourth

Addr Addr Data

Command

Sequence

(Note 1)

First

Second

Fifth

Sixth

Addr

Addr Data Addr Data

Data

Addr Data

Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

AAA

555

AAA

555

AAA

555

RD

F0

Word

Byte

2AA

555

2AA

555

2AA

555

2AA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

Manufacturer ID

4

AA

55

90 (BA)X00 01

(BA)X01

Word

Byte

(BA)X0E

0A

(BA)X0F

(BA)X1E

00/

01

Device ID (Note 9)

90

7E

(BA)X02

(BA)X03

(BA)X06

(SA)X02

(BA)X1C

Word

Byte

SecSi™ Sector Factory

Protect (Note 10)

90

82/02

Sector/Sector Block

Protect Verify

(Note 11)

Word

4

AA

55

90

00/01

Byte

AAA

555

(BA)AAA

(SA)X04

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

2AA

555

2AA

555

PA

555

AAA

555

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

AA

55

88

90

A0

20

XXX

PA

00

AAA

555

AAA

555

PD

AAA

555

AAA

555

Unlock Bypass

AAA

XXX

AAA

Unlock Bypass Program (Note 12)

Unlock Bypass Reset (Note 13)

A0

90

PD

00

2

BA

555

AAA

555

AAA

BA

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

55

555

Chip Erase

6

AA

55

80

AA

10

30

Byte

Word

Byte

555

AAA

2AA

55

Sector Erase

SA

AAA

555

Erase Suspend (Note 14)

Erase Resume (Note 15)

1

B0

30

BA

Word

Byte

55

CFI Query (Note 16)

1

98

AA

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A20–A12 uniquely select any sector.

BA = Address of the bank that is being switched to autoselect mode, is

in bypass mode, or is being erased.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

Notes:

1. See Table 1 for description of bus operations.

9. The device ID must be read across three cycles. The device ID is

00h for bottom boot devices, and 01h for top boot devices.

2. All values are in hexadecimal.

10. The data is 82h for factory locked and 02h for not factory locked.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

11. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

12. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

5. Unless otherwise noted, address bits A20–A11 are don’t cares.

13. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

6. No unlock or command cycles required when bank is reading

array data.

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high (while

the bank is providing status information).

15. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or SecSi Sector factory protect

information. Data bits DQ15–DQ8 are don’t care. See the

Autoselect Command Sequence section for more information.

16. Command is valid when device is ready to read array data or when

device is in autoselect mode.

28

Am29DL320G

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 14 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

invalid. Valid data on DQ7–DQ0 will appear on suc-

cessive read cycles.

Table 14 shows the outputs for Data# Polling on DQ7.

Figure 6 shows the Data# Polling algorithm. Figure 22

in the AC Characteristics section shows the Data#

Polling timing diagram.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

bank returns to the read mode. If not all selected sec-

tors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ0–DQ6 may be still

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 6. Data# Polling Algorithm

Am29DL320G

29

Table 14 shows the outputs for Toggle Bit I on DQ6.

Figure 7 shows the toggle bit algorithm. Figure 23 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 24 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

START

Read DQ7–DQ0

Table 14 shows the outputs for RY/BY#.

Read DQ7–DQ0

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

No

Toggle Bit

= Toggle?

Yes

No

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Toggle Bit

= Toggle?

No

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling).

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Figure 7. Toggle Bit Algorithm

30

Am29DL320G

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 7).

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 14 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

Figure 7 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 23 shows the toggle bit timing diagram. Figure

24 shows the differences between DQ2 and DQ6 in

graphical form.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 14 shows the status of DQ3 relative to the other

status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

Am29DL320G

31

Table 14. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

32

Am29DL320G

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Figure 8. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 8. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 9.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 8. Maximum

DC input voltage on pin A9 is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP#/ACC is +9.5 V which may

overshoot to +12.0 V for periods up to 20 ns.

2.0 V

20 ns

Figure 9. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

V

_CCSupply Voltages

V_CCfor standard voltage range . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

Am29DL320G

33

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

_IN= V_SSto V_CC

Min

Typ

Max

±1.0

35

Unit

µA

V

,

I_LI

Input Load Current

V_CC= V_{CC max}

I_LIT

A9 Input Load Current

Output Leakage Current

Reset# Input Load Current

V_CC= V_{CC max}; A9 = 12.5 V

_OUT= V_SSto V_CC

V_CC= V_{CC max}

µA

V

,

I_LO

±1.0

µA

I_LR

V_CC= V_{CC max,}RESET#= 12.5 V

35

16

4

µA

5 MHz

10

2

CE# = V_IL,OE# = V_IH,

Byte Mode

1 MHz

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

5 MHz

10

2

16

4

CE# = V_IL,OE# = V_IH,

Word Mode

1 MHz

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Notes 2, 3) CE# = V_IL,OE# = V_IH, WE# = V_IL

15

0.2

30

5

mA

µA

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC± 0.3 V

RESET# = V_SS± 0.3 V

5

V

_IH= V_CC± 0.3 V;

I_CC5

Automatic Sleep Mode (Notes 2, 4)

0.2

5

µA

V_IL= V_SS± 0.3 V

Byte

Word

Byte

21

45

V_CCActive Read-While-Program

Current (Notes 1, 2)

I_CC6

CE# = V_IL, OE# = V_IH

mA

V_CCActive Read-While-Erase

Current (Notes 1, 2)

I_CC7

I_CC8

I_ACC

CE# = V_IL, OE# = V_IH

mA

Word

V_CCActive

Program-While-Erase-Suspended

Current (Notes 2, 5)

17

35

ACC pin

V_CCpin

5

10

30

mA

V

ACC Accelerated Program Current,

Word or Byte

15

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

0.8

0.7 x V_CC

V_CC+ 0.3

V

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration

V_HH

V_CC= 3.0 V ± 10%

8.5

9.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V_CC= 3.0 V ± 10%

12.5

0.45

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

0.85 V_CC

V_CC–0.4

2.3

Output High Voltage

Low V_CCLock-Out Voltage (Note 5)

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep mode current is

200 nA.

5. Not 100% tested.

34

Am29DL320G

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 10. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 11. Typical I_CC1vs. Frequency

Am29DL320G

35

TEST CONDITIONS

Table 15. Test Specifications

3.3 V

Test Condition

70, 90

120

Unit

Output Load

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

100

pF

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

V

C

L

6.2 kΩ

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 13. Input Waveforms and Measurement Levels

36

Am29DL320G

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

JEDEC Std. Description

Test Setup

70

90

40

16

120

Unit

ns

t_AVAV

t_AVQV

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_RCRead Cycle Time (Note 1)

Min

Max

70

30

120

50

t_ACCAddress to Output Delay

CE#, OE# = V_IL

OE# = V_IL

ns

t_CEChip Enable to Output Delay

ns

t_OEOutput Enable to Output Delay

t_DFChip Enable to Output High Z (Note 1)

t_DFOutput Enable to Output High Z (Note 1)

ns

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold Time

t_OEH

Toggle and

Data# Polling

(Note 1)

10

Notes:

1. Not 100% tested.

2. See Figure 12 and Table 15 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 14. Read Operation Timings

Am29DL320G

37

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 15. Reset Timings

38

Am29DL320G

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

t_ELFL/t_ELFH

t_FLQZ

Description

70

90

5

120

Unit

ns

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

16

90

ns

t_FHQV

70

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ14–DQ0)

Data Output

(DQ7–DQ0)

BYTE#

DQ14–DQ0

Switching

from word

to byte

Address

Input

DQ15

Output

mode

DQ15/A-1

BYTE#

t_FLQZ

t_ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ7–DQ0)

Data Output

(DQ14–DQ0)

DQ14–DQ0

DQ15/A-1

mode

Address

Input

DQ15

Output

t_FHQV

Figure 16. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t_SET

(t_AS

)

t_HOLD(t_AH

)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 17. BYTE# Timings for Write Operations

Am29DL320G

39

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

70

90

0

120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

70

120

t_AVWL

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

45

15

ns

t_WLAX

45

0

50

ns

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Data Hold Time

Min

35

45

0

ns

20

t_OEPH

Output Enable High during toggle bit polling

Min

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

0

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

0

ns

CE# Hold Time

t_WP

Write Pulse Width

30

35

30

0

50

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

Byte

5

t_WHWH1

t_WHWH1Programming Operation (Note 2)

µs

Word

7

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

t_WHWH1

Typ

4

t_WHWH2Sector Erase Operation (Note 2)

Typ

Min

0.4

50

0

sec

µs

t_VCS

t_RB

V_CCSetup Time (Note 1)

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

40

Am29DL320G

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 18. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 19. Accelerated Program Timing Diagram

Am29DL320G

41

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

42

Am29DL320G

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 21. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 22. Data# Polling Timings (During Embedded Algorithms)

Am29DL320G

43

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 24. DQ2 vs. DQ6

44

Am29DL320G

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 25. Temporary Sector Unprotect Timing Diagram

Am29DL320G

45

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector/Sector Block Protect or Unprotect

60h 60h

Verify

40h

Data

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram

46

Am29DL320G

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

70

90

0

120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

70

120

t_AVWL

t_ELAX

t_DVEH

t_EHDX

ns

t_AH

t_DS

t_DH

45

35

45

0

50

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

30

35

30

5

50

t_CPH

Byte

Programming Operation

(Note 2)

t_WHWH1

µs

Word

7

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

Typ

4

µs

t_WHWH2

Notes:

Sector Erase Operation (Note 2)

0.4

sec

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Am29DL320G

47

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings

48

Am29DL320G

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time

0.4

28

5

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

Byte Program Time

Accelerated Byte/Word Program Time

Word Program Time

150

120

210

63

4

µs

Excludes system level

overhead (Note 5)

7

µs

Byte Mode

Word Mode

21

14

Chip Program Time

(Note 3)

sec

42

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V (3.0 V for regulated devices), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

13 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

6

Max

7.5

12

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

Am29DL320G

49

PHYSICAL DIMENSIONS

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm

Dwg rev AF; 10/99

50

Am29DL320G

PHYSICAL DIMENSIONS

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm

Dwg rev AG; 7/2000

FBD 048

6.00 mm x 12.00 mm

PACKAGE

1.20

0.20

0.84

12.00 BSC

0.94

6.00 BSC

5.60 BSC

4.00 BSC

8

6

48

0.25 0.30

0.35

0.80 BSC

0.40 BSC

Am29DL320G

51

PHYSICAL DIMENSIONS

TS 048—Thin Small Outline Package

Dwg rev AA; 10/99

52

Am29DL320G

PHYSICAL DIMENSIONS

LAA064—64-ball Fortified Ball Grid Array (FBGA)

11 x 13 mm package

Am29DL320G

53

REVISION SUMMARY

Revision A (December 6, 2001)

Initial release.

Replaced second bullet, added the two paragraphs

under bullet and Figure 3.

Common Flash Memory Interface (CFI)

Modified third and fourth paragraphs.

Command Definitions

Revision A+1 (February 19, 2002)

Ordering Information

Corrected package marking for 6 x 12 mm FBGA

package.

Modified information for array data.

Enter SecSi Sector/Exit SecSi Sector Command

Sequence

Revision B (July 31, 2002)

Global

Added ACC function note to end of paragraph.

Table 13 Command Definitions

Changed fourth data from 81/01 to 82/02.

Operating Ranges

Added LAA064 package.

Ordering Information

Corrected package marking for FBGA.

AC Characteristics

Removed extended (E) devices information.

DC characteristics - CMOS Compatible

Added I_LRinformation.

Added 70 ns speed grade to Test Specifications and

Read-Only Operations

Revision C (October 13, 2003)

Global

Trademarks

Changed Advance Information datasheet status to

Final.

Updated to 2003 standards.

Revision C + 1 (May 27, 2004)

Ordering Information

Removed standard products E temperature range,

and EE & EEN from Valid Combinations for TSOP

packages.

Added Lead-free (Pb-free) options to the Temperature

range breakout of the OPN Table and the Valid Combi-

nations table.

Table 6 Autoselect Codes

Revision C + 2 (September 27, 2004)

Cover sheet and title page

Changed SecSi Indicator Bit (DQ7) for BYTE# = V_IL

from X to 82, and DQ7 to Q10 to 82h (factory locked),

02h (not factory locked).

Added notation to superseding documents.

Customer Lockable: SecSi Sector NOT Pro-

grammed or Protected At the Factory

Revision C + 3 (May 25, 2005)

Cover sheet and title page

Added notation to superseding documents.

54

Am29DL320G

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to

you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de-

vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea-

sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29DL320G

55

Representatives in U.S. and Canada

Sales Offices and Representatives

ARIZONA,

North America

Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(480)839-2320

CALIFORNIA,

ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(256)830-9192

ARIZONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(602)242-4400

CALIFORNIA,

Calabasas - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(818)878-5800

Irvine - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (949)261-2123

San Diego - Centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(858)278-4950

Santa Clara - Fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . .(408)350-4800

CANADA,

Burnaby, B.C. - Davetek Marketing. . . . . . . . . . . . . . . . . . . .(604)430-3680

Calgary,Alberta - Davetek Marketing. . . . . . . . . . . . . . . . .(403)283-3577

Kanata, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . . .(613)592-9540

Mississauga, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . .(905)672-2030

St Laurent, Quebec - J-Squared Tech. . . . . . . . . . . . . . . . ( 5 1 4 ) 74 7 - 1 2 1 1

COLORADO,

Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(949)450-7500

Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(408)732-2400

COLORADO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(303)741-2900

CONNECTICUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(203)264-7800

FLORIDA,

Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(727)793-0055

Miami (Lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 3 0 5 ) 8 2 0 - 1 1 1 3

GEORGIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(770)814-0224

ILLINOIS,

Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(630)773-4422

MASSACHUSETTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (781)213-6400

MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(248)471-6294

MINNESOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(612)745-0005

NEW JERSEY,

Chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 97 3 ) 7 0 1 - 1 7 7 7

NEWYORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(716)425-8050

NORTH CAROLINA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(919)840-8080

OREGON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(503)245-0080

PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 1 5 ) 3 4 0 - 1 1 8 7

SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(605)692-5777

TEXAS,

Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . .(303)277-0456

FLORIDA,

Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . .(321)728-7706

Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . .(954)527-4949

Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . .(407)872-5775

St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . .(727)894-3603

GEORGIA,

Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . (678)584-1128

ILLINOIS,

Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . .(847)967-8430

INDIANA,

Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (765)457-7241

IOWA,

Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . (319)294-1000

KANSAS,

Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 1 3 ) 4 69 - 1 3 1 2

MASSACHUSETTS,

Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)346-7830

Dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(972)985-1344

Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(281)376-8084

VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(703)736-9568

Burlington - Synergy Associates . . . . . . . . . . . . . . . . . . . . .(781)238-0870

MICHIGAN,

Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(810)227-0007

MINNESOTA,

St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . .(651)699-0200

MISSOURI,

St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . . (314)997-4558

NEW JERSEY,

International

AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . .TEL(61)2-88-777-222

BELGIUM,Antwerpen . . . . . . . . . . . . . . . . . . . . . . . .TEL(32)3-248-43-00

BRAZIL, San Paulo . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(55)11-5501-2105

CHINA,

Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)10-6510-2188

Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)21-635-00838

Shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(86)755-246-1550

FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 5 8 ) 8 8 1 - 3 1 1 7

FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 3 ) - 1 - 4 975 1 0 1 0

GERMANY,

Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(49)-6172-92670

Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 4 9 ) - 8 9 - 4 5 0 5 3 0

HONG KONG, Causeway Bay . . . . . . . . . . . . . . . . . . .TEL(85)2-2956-0388

ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 3 9 ) - 0 2 - 3 8 1 9 6 1

INDIA, New Delhi . . . . . . . . . . . . . . . . . . . . . . . . . . T E L ( 9 1 ) 1 1 - 62 3 - 8 62 0

JAPAN,

es

Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . .(856)866-1234

NEWYORK,

Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 1 6 ) 74 1 - 7 1 1 6

East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . (315)437-8343

Pittsford - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . . (716)586-3660

Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . . (516)536-4242

NORTH CAROLINA,

Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . .(919)846-5728

OHIO,

Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . . (440)816-1660

Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . (614)781-0725

Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . .(937)898-9610

Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . (614)523-1990

OREGON,

Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . .(503)670-0557

UTAH,

Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . .(801)288-2500

VIRGINIA,

Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)6-6243-3250

Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)3-3346-7600

KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(82)2-3468-2600

RUSSIA, Moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(7)-095-795-06-22

SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(46)8-562-540-00

TAIWAN,Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(886)2-8773-1555

UNITED KINGDOM,

Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(44)1276-803100

Haydock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(44)1942-272888

Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . ( 4 1 0 ) 76 1 - 2 2 5 5

WASHINGTON,

Kirkland - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(425)822-9220

WISCONSIN,

Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . .(262)574-9393

Advanced Micro Devices reserves the right to make changes in its product without notice

in order to improve design or performance characteristics.The performance

characteristics listed in this document are guaranteed by specific tests, guard banding,

design and other practices common to the industry. For specific testing details, contact

your local AMD sales representative.The company assumes no responsibility for the use of

any circuits described herein.

Representatives in Latin America

ARGENTINA,

Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655

CHILE,

Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993

COLUMBIA,

Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 5 7 1 ) 4 1 0 - 4 1 8 2

MEXICO,

Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . .(523)817-3900

Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . .(525)752-2727

Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828

PUERTO RICO,

AMD, the AMD Arrow logo and combination thereof, are trademarks of

Advanced Micro Devices, Inc. Other product names are for informational purposes only

and may be trademarks of their respective companies.

Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . .(787)851-6000

One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400

TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com

01/03

Printed in USA


型号：	AM29DL320GB40EF
厂家：	AMD
描述：	32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory 32兆位（ 4米×8位/ 2的M× 16位） CMOS 3.0伏只，同时操作闪存闪存
文件：	总58页 (文件大小：1190K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29DL320GB40EF [AMD]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E