AM29DL400BB-120ECB_技术文档

PRELIMINARY

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Simultaneous Read/Write operations

■ Sector protection

— Host system can program or erase in one bank,

then immediately and simultaneously read from

the other bank

— Hardware method of locking a sector to prevent

any program or erase operation within that

sector

— Zero latency between read and write operations

— Read-while-erase

— Sectors can be locked in-system or via

programming equipment

— Temporary Sector Unprotect feature allows code

changes in previously locked sectors

— Read-while-program

■ Single power supply operation

■ Top or bottom boot block configurations

— 2.7 to 3.6 volt read and write operations for

battery-powered applications

available

■ Embedded Algorithms

■ Manufactured on 0.35 µm process technology

■ High performance

— Embedded Erase algorithm automatically

pre-programs and erases sectors or entire chip

— Access times as fast as 70 ns

— Embedded Program algorithm automatically

programs and verifies data at specified address

■ Low current consumption (typical values

at 5 MHz)

■ Minimum 1 million program/erase cycles

— 7 mA active read current

guaranteed per sector

— 21 mA active read-while-program or read-while-

erase current

■ Package options

— 44-pin SO

— 17 mA active program-while-erase-suspended

current

— 48-pin TSOP

■ Compatible with JEDEC standards

— 200 nA in standby mode

— Pinout and software compatible with

single-power-supply flash standard

— 200 nA in automatic sleep mode

— Standard t_CEchip enable access time applies to

transition from automatic sleep mode to active

mode

— Superior inadvertent write protection

■ Data# Polling and Toggle Bits

■ Flexible sector architecture

— Provides a software method of detecting

program or erase cycle completion

— Two 16 Kword, two 8 Kword, four 4 Kword, and

six 32 Kword sectors in word mode

■ Ready/Busy# output (RY/BY#)

— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and

six 64 Kbyte sectors in byte mode

— Hardware method for detecting program or

erase cycle completion

— Any combination of sectors can be erased

— Supports full chip erase

■ Erase Suspend/Erase Resume

— Suspends or resumes erasing sectors to allow

reading and programming in other sectors

■ Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

— No need to suspend if sector is in the other bank

■ Hardware reset pin (RESET#)

— Hardware method of resetting the device to

reading array data

Publication# 21606 Rev: C Amendment/0

Issue Date: April 1998

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29DL400B is an 4 Mbit, 3.0 volt-only flash

memory device, organized as 262,144 words or

524,288 bytes. The device is offered in 44-pin SO and

48-pin TSOP packages. The word-wide (x16) data ap-

pears on DQ0–DQ15; the byte-wide (x8) data appears

on DQ0–DQ7. This device requires only a single 3.0

volt V_CCsupply to perform read, program, and erase

operations. A standard EPROM programmer can also

be used to program and erase the device.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device automatically returns to

reading array data.

The standard device offers access times of 70, 80, 90,

and 120 ns, allowing high-speed microprocessors to

operate without wait states. Standard control pins—

chip enable (CE#), write enable (WE#), and output en-

able (OE#)—control read and write operations, and

avoid bus contention issues.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The device requires only a single 3.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides si-

multaneous operation by dividing the memory space

into two banks. Bank 1 contains boot/parameter sec-

tors, and Bank 2 consists of larger, code sectors of uni-

form size. The device can improve overall system

performance by allowing a host system to program or

erase in one bank, then immediately and simultane-

ously read from the other bank, with zero latency. This

releases the system from waiting for the completion of

program or erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector within that bank that is

not selected for erasure. True background erase can

thus be achieved. There is no need to suspend the

erase operation if the read data is in the other bank.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device to reading array data, enabling the sys-

tem microprocessor to read the boot-up firmware from

the Flash memory.

Am29DL400B Features

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write timings.

Register contents serve as input to an internal state

machine that controls the erase and programming

circuitry. Write cycles also internally latch addresses

and data needed for the programming and erase

operations. Reading data out of the device is similar to

reading from other Flash or EPROM devices.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

AMD’s Flash technology combines years of Flash mem-

ory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The

device electrically erases all bits within a sector simulta-

neously via Fowler-Nordheim tunneling. The bytes are

programmed one byte or word at a time using hot elec-

tron injection.

2

Am29DL400B

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Family Part Number

Am29DL400B

Speed Options (Full Voltage Range: V

Max Access Time (ns)

CE# Access (ns)

= 2.7 – 3.6 V)

-70

-80

-90

90

35

-120

120

50

CC

70

30

80

30

OE# Access (ns)

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

OE# BYTE#

V

CC

SS

Upper Bank Address

A0–A17

Upper Bank

X-Decoder

RY/BY#

A0–A17

RESET#

STATE

CONTROL

&

COMMAND

REGISTER

Status

WE#

CE#

DQ0–DQ15

Control

BYTE#

DQ0–DQ15

X-Decoder

Lower Bank

A0–A17

Lower Bank Address

OE# BYTE#

21606C-1

Am29DL400B

3

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

V_CC

WE#

RESET#

NC

RY/BY#

NC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

Standard TSOP

A17

A7

A6

A5

A4

A3

A2

A1

A16

BYTE#

V_SS

1

2

3

4

5

6

7

8

9

48

A15

A14

A13

A12

A11

A10

A9

A8

NC

WE#

RESET#

NC

RY/BY#

NC

A17

A7

A6

A5

A4

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Reverse TSOP

A3

A2

A1

CE#

A0

21606C-2

4

Am29DL400B

P R E L I M I N A R Y

CONNECTION DIAGRAMS

RY/BY#

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

NC

A17

A7

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

CE# 12

V_SS13

35 A15

34 A16

SO

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

21606C-3

Am29DL400B

5

P R E L I M I N A R Y

PIN DESCRIPTION

LOGIC SYMBOL

A0-A17

= 18 Addresses

18

DQ0-DQ14= 15 Data Inputs/Outputs

A0–A17

16 or 8

DQ15/A-1 = DQ15 (Data Input/Output, word mode),

A-1 (LSB Address Input, byte mode)

DQ0–DQ15

(A-1)

CE#

= Chip Enable

OE#

= Output Enable

CE#

OE#

WE#

BYTE#

= Write Enable

= Selects 8-bit or 16-bit mode

WE#

RESET# = Hardware Reset Pin, Active Low

RESET#

BYTE#

RY/BY#

V_CC

= Ready/Busy Output

RY/BY#

= 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

21606C-4

V_SS

NC

= Device Ground

= Pin Not Connected Internally

6

Am29DL400B

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29DL400B

T

-70

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAGE TYPE

E

F

S

=

40-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 040)

40-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR040)

44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations to

check on newly released combinations.

Valid Combinations

EC, EI, FC, FI,

Am29DL400BT-70

Am29DL400BB-70

SC, SI

Am29DL400BT-80

Am29DL400BB-80

EC, EI, EE,

FC, FI, FE,

SC, SI, SE

Am29DL400BT-90

Am29DL400BB-90

Am29DL400BT-120

Am29DL400BB-120

Am29DL400B

7

P R E L I M I N A R Y

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is a latch used to store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. Table 1 lists the device bus operations, the

inputs and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29DL400B Device Bus Operations

DQ8–DQ15

BYTE#

= V

Addresses

(Note 1)

DQ0– BYTE#

Operation

CE# OE# WE# RESET#

DQ7

= V

IH

IL

Read

L

H

A

D

DQ8–DQ14 = High-Z,

DQ15 = A-1

IN

OUT

Write

L

H

L

H

A

D

IN

V

0.3 V

±

V

0.3 V

±

CC

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V

D

X

ID

IN

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V

D

X

ID

IN

Temporary Sector Unprotect

X

A

D

High-Z

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out

IL

IH

ID

IN

OUT

Notes:

1. Addresses are A17:A0 in word mode (BYTE# = V ), A17:A-1 in byte mode (BYTE# = V ).

IH

IL

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

The internal state machine is set for reading array

Word/Byte Configuration

data upon device power-up, or after a hardware reset.

The BYTE# pin controls whether the device data I/O

This ensures that no spurious alteration of the mem-

pins operate in the byte or word configuration. If the

ory content occurs during the power transition. No

BYTE# pin is set at logic ‘1’, the device is in word con-

command is necessary in this mode to obtain array

figuration, DQ0-15 are active and controlled by CE#

data. Standard microprocessor read cycles that as-

and OE# .

sert valid addresses on the device address inputs pro-

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

duce valid data on the device data outputs. Each bank

remains enabled for read access until the command

register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read-Only Operations table for timing spec-

ifications and to Figure 13 for the timing diagram. I_CC1

in the DC Characteristics table represents the active

current specification for reading array data.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE# should

remain at V_IH. The BYTE# pin determines whether the

device outputs array data in words or bytes.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

8

Am29DL400B

P R E L I M I N A R Y

sectors of memory), the system must drive WE# and

Figure 19 shows how read and write cycles may be in-

itiated for simultaneous operation with zero latency.

I_CC6and I_CC7in the DC Characteristics table represent

the current specifications for read-while-program and

read-while-erase, respectively.

CE# to V_IL, and OE# to V_IH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more in-

formation.

Standby Mode

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Unlock

Bypass mode, only two write cycles are required to pro-

gram a word or byte, instead of four. The “Byte/Word

Program Command Sequence” section has details on

programming data to the device using both standard and

Unlock Bypass command sequences.

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. The device

address space is divided into two banks: Bank 1 con-

tains the boot/parameter sectors, and Bank 2 contains

the larger, code sectors of uniform size. A “bank ad-

dress” is the address bits required to uniquely select a

bank. Similarly, a “sector address” is the address bits

required to uniquely select a sector.

V

_CC± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires

standard access time (t_CE) for read access when the

device is in either of these standby modes, before it is

ready to read data.

The device also enters the standby mode when the RE-

SET# pin is driven low. Refer to the next section, “RE-

SET#: Hardware Reset Pin”.

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the Autoselect Mode and Autoselect

Command Sequence sections for more information.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I_CC3in the DC Characteristics table represents the

standby current specification.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification ta-

bles and timing diagrams for write operations.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC+ 30

ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address

access timings provide new data when addresses are

changed. While in sleep mode, output data is latched

and always available to the system. I_CC4in the DC

Characteristics table represents the automatic sleep

mode current specification.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank of

memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being erased).

Am29DL400B

9

P R E L I M I N A R Y

memory, enabling the system to read the boot-up

RESET#: Hardware Reset Pin

firmware from the Flash memory.

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all read/

write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to

reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept

another command sequence, to ensure data integrity.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS±0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current will

be greater.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

Output Disable Mode

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

10

Am29DL400B

P R E L I M I N A R Y

Table 2. Am29DL400BT Top Boot Sector Architecture

Sector Address

Bank

Address

Sector Size

(Kbytes/

Kwords)

(x8)

(x16)

Bank

Sector A17 A16 A15 A14 A13 A12

Address Range

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–63FFFh

Address Range

SA0

SA1

SA2

SA3

SA4

SA5

SA6

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

64/32

16/8

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–31FFFh

Bank 2

SA7

1

0

32/16

64000h–6BFFFh

32000h–35FFFh

SA8

SA9

1

0

1

8/4

6C000h–6DFFFh

6E000h–6FFFFh

70000h–71FFFh

72000h–73FFFh

36000h–36FFFh

37000h–37FFFh

38000h–38FFFh

39000h–39FFFh

1

Bank 1

SA10

SA11

0

1

X

SA12

SA13

1

32/16

16/8

74000h–7BFFFh

7C000h–7FFFFh

3A000h–3DFFFh

3E000h–3FFFFh

Note: The address range is A17:A-1 if in byte mode (BYTE# = V ). The address range is A17:A0 if in word mode (BYTE# = V ).

IL

IH

Am29DL400B

11

P R E L I M I N A R Y

Table 3. Am29DL400BB Bottom Boot Sector Architecture

Sector Address

Bank

Address

Sector Size

(x8)

(x16)

Bank

Sector A17 A16 A15 A14 A13 A12

(Kbytes/Kwords)

Address Range

SA13

SA12

SA11

SA10

SA9

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

0

1

0

X

1

0

1

0

1

0

1

0

X

1

64/32

16/8

70000h–7FFFFh

60000h–6FFFFh

50000h–5FFFFh

40000h–4FFFFh

30000h–3FFFFh

20000h–2FFFFh

1C000h–1FFFFh

38000h–3FFFFh

30000h–37FFFh

28000h–2FFFFh

20000h–27FFFh

18000h–1FFFFh

10000h–17FFFh

0E000h–0FFFFh

Bank 2

SA8

SA7

SA6

0

1

32/16

14000h–1BFFFh

0A000h–0DFFFh

SA5

SA4

SA3

SA2

0

1

0

8/4

12000h–13FFFh

10000h–11FFFh

0E000h–0FFFFh

0C000h–0DFFFh

09000h–09FFFh

08000h–08FFFh

07000h–07FFFh

06000h–06FFFh

0

Bank 1

1

0

X

SA1

SA0

0

32/16

16/8

04000h–0BFFFh

00000h–03FFFh

02000h–05FFFh

00000h–01FFFh

Note: The address range is A17:A-1 if in byte mode (BYTE# = V ). The address range is A17:A0 if in word mode (BYTE# = V ).

IL

IH

Table 4. In addition, when verifying sector protection,

the sector address must appear on the appropriate

highest order address bits (see Tables 2 and 3). Table

4 shows the remaining address bits that are don’t care.

When all necessary bits have been set as required, the

programming equipment may then read the corre-

sponding identifier code on DQ7-DQ0.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5. This method

does not require V_ID. Refer to the Autoselect Command

Sequence section for more information.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

12

Am29DL400B

P R E L I M I N A R Y

Table 4. Am29DL400B Autoselect Codes (High Voltage Method)

A17 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

DQ15

DQ7

to

DQ0

Description

A6

A1

A0

Manufacturer ID: AMD

L

H

BA

X

V

X

L

X

L

X

01h

0C

ID

Device ID:

Am29DL400B

(Top Boot Block)

Word

Byte

Word

Byte

22h

BA

X

V

X

L

X

L

H

ID

L

H

X

22h

X

0C

0F

Device ID:

Am29DL400B

(Bottom Boot Block)

BA

SA

X

V

X

ID

01h

(protected)

X

Sector Protection Verification

L

H

L

H

L

ID

00h

(unprotected)

Note: L = Logic Low = V , H = Logic High = V , BA = Bank Address, SA = Sector Address, X = Don’t care.

IL

IH

SET# pin to V_ID(11.5 V – 12.5 V). During this mode,

formerly protected sectors can be programmed or

erased by selecting the sector addresses. Once V_IDis

removed from the RESET# pin, all the previously pro-

tected sectors are protected again. Figure 1 shows the

algorithm, and Figure 23 shows the timing diagrams,

for this feature.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both pro-

gram and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 2 shows the algo-

rithms and Figure 24 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect write

cycle.

START

RESET# = V

ID

(Note 1)

The alternate method intended only for programming

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier 3.0 volt-only AMD flash devices. Pub-

lication number 22145 contains further details; contact

an AMD representative to request a copy.

Perform Erase or

Program Operations

RESET# = V

IH

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

Temporary Sector

Unprotect Completed

(Note 2)

It is possible to determine whether a sector is protected

or unprotected. See the Autoselect Mode section for

details.

21606C-5

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

Figure 1. Temporary Sector Unprotect Operation

Am29DL400B

13

P R E L I M I N A R Y

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

21606C-6

Figure 2. In-System Sector Protect/Unprotect Algorithms

Am29DL400B

14

P R E L I M I N A R Y

prevent unintentional writes when V_CCis greater than

V_LKO

Hardware Data Protection

.

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up and

power-down transitions, or from system noise.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept

any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets to reading array data. Subsequent writes

are ignored until V_CCis greater than V_LKO. The system

must provide the proper signals to the control pins to

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 5 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence resets

the device to reading array data.

The Read-Only Operations table provides the read pa-

rameters, and Figure 13 shows the timing diagram.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the AC

Characteristics section.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the bank to which the sys-

tem was writing to reading array data. Once erasure

begins, however, the device ignores reset commands

until the operation is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the bank to

which the system was writing to the reading array data.

If the program command sequence is written to a bank

that is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-suspend-read

mode. Once programming begins, however, the device

ignores reset commands until the operation is com-

plete.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-suspend-

read mode, after which the system can read data from

any non-erase-suspended sector within the same

bank. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See the Erase

Suspend/Erase Resume Commands section for more

information.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data. If a bank en-

tered the autoselect mode while in the Erase Suspend

mode, writing the reset command returns that bank to

the erase-suspend-read mode.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase operation,

or if the bank is in the autoselect mode. See the next

section, Reset Command, for more information.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to reading

array data (or erase-suspend-read mode if that bank

was in Erase Suspend).

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

Am29DL400B

15

P R E L I M I N A R Y

5 shows the address and data requirements for the

Autoselect Command Sequence

byte program command sequence.

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 5 shows the address and data requirements. This

method is an alternative to that shown in Table 4, which

is intended for PROM programmers and requires V_ID

on address pin A9. The autoselect command sequence

may be written to an address within a bank that is either

in the read or erase-suspend-read mode. The autose-

lect command may not be written while the device is

actively programming or erasing in the other bank.

When the Embedded Program algorithm is complete,

that bank then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7,

DQ6, or RY/BY#. Note that while the Embedded Pro-

gram operation is in progress, the system can read

data from the non-programming bank. Refer to the

Write Operation Status section for information on these

status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should be

reinitiated once that bank has returned to reading array

data, to ensure data integrity.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The addressed bank then enters

the autoselect mode. The system may read at any ad-

dress within the same bank any number of times with-

out initiating another autoselect command sequence:

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may cause

that bank to set DQ5 = 1, or cause the DQ7 and DQ6

status bits to indicate the operation was successful.

However, a succeeding read will show that the data is

still “0.” Only erase operations can convert a “0” to a

“1.”

■ A read cycle at address (BA)XX00h (where BA is

the bank address) returns the manufacturer code.

■ A read cycle at address (BA)XX01h in word mode

(or (BA)XX02h in byte mode) returns the device

code.

■ A read cycle to an address containing a sector ad-

dress (SA) within the same bank, and the address

02h on A7–A0 in word mode (or the address 04h on

A6–A-1 in byte mode) returns 01h if the sector is

protected, or 00h if it is unprotected. Refer to Tables

2 and 3 for valid sector addresses.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to a bank faster than using the

standard program command sequence. The unlock by-

pass command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. That

bank then enters the unlock bypass mode. A two-cycle

unlock bypass program command sequence is all that

is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 5 shows the requirements for the com-

mand sequence.

The system may continue to read array data from the

other bank while a bank is in the autoselect mode. To

exit the autoselect mode, the system must write the

reset command to return both banks to reading array

data. If a bank enters the autoselect mode while erase

suspended, a reset command returns that bank to the

erase-suspend-read mode. A subsequent Erase

Resume command returns the bank to the erase oper-

ation.

Byte/Word Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically generates the program

pulses and verifies the programmed cell margin. Table

During the unlock bypass mode, only the Unlock Bypass

Program and Unlock Bypass Reset commands are

valid. To exit the unlock bypass mode, the system must

issue the two-cycle unlock bypass reset command se-

quence. The first cycle must contain the bank address

and the data 90h. The second cycle need only contain

the data 00h. The bank then returns to reading array

data.

16

Am29DL400B

P R E L I M I N A R Y

Figure 3 illustrates the algorithm for the program oper-

tus of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. Refer to the Write Operation Status section for

information on these status bits.

ation. Refer to the Erase and Program Operations table

in the AC Characteristics section for parameters, and

Figure 17 for timing diagrams.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading array

data, to ensure data integrity.

START

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations tables

in the AC Characteristics section for parameters, and

Figure 18 section for timing diagrams.

Write Program

Command Sequence

Sector Erase Command Sequence

Data Poll

from System

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two un-

lock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed

by the address of the sector to be erased, and the sec-

tor erase command. Table 5 shows the address and

data requirements for the sector erase command se-

quence.

Embedded

Program

algorithm

in progress

Verify Data?

No

Yes

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

No

Increment Address

Last Address?

Yes

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command may not be

accepted, and erasure may begin. It is recommended

that processor interrupts be disabled during this time to

ensure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

that bank to reading array data. The system must re-

write the command sequence and any additional ad-

dresses and commands.

21606C-7

Note: See Table 5 for program command sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 5 shows

the address and data requirements for the chip erase

command sequence.

The system can monitor DQ3 (in the erasing bank) to

determine if the sector erase timer has timed out (See

the section on DQ3: Sector Erase Timer.). The time-out

begins from the rising edge of the final WE# pulse in the

command sequence.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded Erase

operation is in progress, the system can read data from

When the Embedded Erase algorithm is complete, that

bank returns to reading array data and addresses are

no longer latched. The system can determine the sta-

Am29DL400B

17

P R E L I M I N A R Y

the non-erasing bank. The system can determine the

gram operation using the DQ7 or DQ6 status bits, just

as in the standard Byte Program operation. Refer to the

Write Operation Status section for more information.

status of the erase operation by reading DQ7, DQ6,

DQ2, or RY/BY# in the erasing bank. Refer to the Write

Operation Status section for information on these sta-

tus bits.

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

Autoselect Mode and Autoselect Command Sequence

sections for details.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the sector erase command sequence should be

reinitiated once that bank has returned to reading array

data, to ensure data integrity.

To resume the sector erase operation, the system must

write the Erase Resume command. The bank address

of the erase-suspended bank is required when writing

this command. Further writes of the Resume command

are ignored. Another Erase Suspend command can be

written after the chip has resumed erasing.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations tables

in the AC Characteristics section for parameters, and

Figure 18 section for timing diagrams.

START

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then

read data from, or program data to, any sector not se-

lected for erasure. The bank address is required when

writing this command. This command is valid only dur-

ing the sector erase operation, including the 50 µs

time-out period during the sector erase command se-

quence. The Erase Suspend command is ignored if

written during the chip erase operation or Embedded

Program algorithm.

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

Erase

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase suspends”

all sectors selected for erasure.) Reading at any ad-

dress within erase-suspended sectors produces status

information on DQ7–DQ0. The system can use DQ7,

or DQ6 and DQ2 together, to determine if a sector is

actively erasing or is erase-suspended. Refer to the

Write Operation Status section for information on these

status bits.

21606C-8

Notes:

1. See Table 5 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 4. Erase Operation

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the pro-

18

Am29DL400B

P R E L I M I N A R Y

Table 5. Am29DL400B Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Addr

Fifth

Sixth

Addr Data Addr Data

Data

Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

(BA)555

(BA)AAA

(BA)555

(BA)AAA

(BA)555

(BA)AAA

Manufacturer ID

4

AA

55

90 (BA)X00

01

AAA

555

(BA)X01 220C

Device ID,

Top Boot Block

90

AAA

555

(BA)X02

0C

(BA)X01 220F

Device ID,

Bottom Boot Block

AAA

(BA)X02

0F

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

(BA)555

(BA)AAA

Sector Protect

Verify (Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

555

AAA

555

AAA

XXX

BA

2AA

555

2AA

555

PA

555

AAA

555

Program

4

3

AA

55

A0

20

PA

PD

Unlock Bypass

AAA

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

BA

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

AAA

Word

Sector Erase

Byte

SA

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

BA

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A17–A12 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

BA = Address of the bank that is being switched to autoselect

mode, is in bypass mode, or is being erased. Address bits A17–

A16 select a bank.

Notes:

1. See Table 1 for description of bus operations.

8. The fourth cycle of the autoselect command sequence is a

read cycle. The system must provide the bank address to

obtain the manufacturer or device ID information.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles

are write operations.

9. The data is 00h for an unprotected sector and 01h for a

protected sector. See the Autoselect Command Sequence

section for more information.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command

cycles in word mode.

10. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

5. Address bits A17–A11 are don’t cares for unlock and

command cycles, unless bank address (BA) is required.

11. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass

mode.

6. No unlock or command cycles required when bank is in read

mode.

7. The Reset command is required to return to reading array

data (or to the erase-suspend-read mode if previously in

Erase Suspend) when a bank is in the autoselect mode, or if

DQ5 is goes high (while the bank is providing status

information).

12. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector

erase operation, and requires the bank address.

13. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

Am29DL400B

19

P R E L I M I N A R Y

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation in the bank where a program or

erase operation is in progress: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 6 and the following subsec-

tions describe the function of these bits. DQ7, RY/BY#,

and DQ6 each offer a method for determining whether

a program or erase operation is complete or in

progress. These three bits are discussed first.

invalid. Valid data on DQ0–DQ7 will appear on succes-

sive read cycles.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm. Figure 20

in the AC Characteristics section shows the Data# Poll-

ing timing diagram.

DQ7: Data# Polling

START

The Data# Polling bit, DQ7, indicates to the host sys-

tem whether an Embedded Program or Erase algo-

rithm is in progress or completed, or whether a bank is

in Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the command sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for ap-

proximately 1 µs, then that bank returns to reading

array data.

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the

bank returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected sector,

the status may not be valid.

No

PASS

FAIL

21606C-9

Notes:

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing sta-

tus information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ0–DQ6 may be still

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

20

Am29DL400B

P R E L I M I N A R Y

DQ6 also toggles during the erase-suspend-program

RY/BY#: Ready/Busy#

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-

ure 6 shows the toggle bit algorithm. Figure 21 in the

“AC Characteristics” section shows the toggle bit timing

diagrams. Figure 22 shows the differences between

DQ2 and DQ6 in graphical form. See also the subsec-

tion on DQ2: Toggle Bit II.

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data, is in the standby

mode, or one of the banks is in the erase-suspend-read

mode.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

Table 6 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for eras-

ure. (The system may use either OE# or CE# to control

the read cycles.) But DQ2 cannot distinguish whether

the sector is actively erasing or is erase-suspended.

DQ6, by comparison, indicates whether the device is

actively erasing, or is in Erase Suspend, but cannot dis-

tinguish which sectors are selected for erasure. Thus,

both status bits are required for sector and mode infor-

mation. Refer to Table 6 to compare outputs for DQ2

and DQ6.

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address within

the programming or erasing bank, and is valid after the

rising edge of the final WE# pulse in the command se-

quence (prior to the program or erase operation), and

during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address within

the programming or erasing bank cause DQ6 to toggle.

The system may use either OE# or CE# to control the

read cycles. When the operation is complete, DQ6

stops toggling.

Figure 6 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 21 shows the toggle bit timing diagram. Figure

22 shows the differences between DQ2 and DQ6 in

graphical form.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, DQ6 toggles for

approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sec-

tors, and ignores the selected sectors that are

protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6 for the following discussion. Whenever

the system initially begins reading toggle bit status, it

must read DQ7–DQ0 at least twice in a row to determine

whether a toggle bit is toggling. Typically, the system

would note and store the value of the toggle bit after the

first read. After the second read, the system would com-

pare the new value of the toggle bit with the first. If the

toggle bit is not toggling, the device has completed the

program or erase operation. The system can read array

data on DQ7–DQ0 on the following read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When a bank is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When that bank enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on DQ7: Data# Polling).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling just as

DQ5 went high. If the toggle bit is no longer toggling,

the device has successfully completed the program or

erase operation. If it is still toggling, the device did not

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Am29DL400B

21

P R E L I M I N A R Y

completed the operation successfully, and the system

must write the reset command to return to reading

array data.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1,” indicating that

the program or erase cycle was not successfully com-

pleted.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 6).

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the timing limit has been

exceeded, DQ5 produces a “1”.

Under both these conditions, the system must write the

reset command to return to reading array data (or to the

erase-suspend-read mode if a bank was previously in

the erase-suspend-program mode).

START

DQ3: Sector Erase Timer

Read DQ7–DQ0

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional sectors

are selected for erasure, the entire time-out also ap-

plies after each additional sector erase command.

When the time-out period is complete, DQ3 switches

from a “0” to a “1”. If the system can guarantee the time

between additional sector erase commands to be less

than 50 µs, it need not monitor DQ3. See also the Sec-

tor Erase Command Sequence section.

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

Yes

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1”, the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0”, the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase command.

If DQ3 is high on the second status check, the last com-

mand might not have been accepted.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Table 6 shows the status of DQ3 relative to the other

status bits.

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

Figure 6. Toggle Bit Algorithm

22

Am29DL400B

P R E L I M I N A R Y

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase-Suspend-

Read

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

Am29DL400B

23

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

20 ns

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#,

and RESET# (Note 2). . . . . . . . .–0.5 V to +12.5 V

20 ns

All other pins

(Note 1). . . . . . . . . . . . . . . . . –0.5 V to V_CC+0.5 V

21606C-11

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

Figure 7. Maximum Negative

Overshoot Waveform

voltage transitions, input or I/O pins may undershoot V

SS

to –2.0 V for periods of up to 20 ns. Maximum DC voltage

on input or I/O pins is V +0.5 V. See Figure 7. During

CC

voltage transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See Figure 8.

CC

20 ns

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

V

CC

+2.0 V

V

+0.5 V

RESET# may undershoot V to –2.0 V for periods of up

SS

to 20 ns. See Figure 7. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

CC

2.0 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

20 ns

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this data sheet is not implied. Exposure of

the device to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

21606C-12

Figure 8. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T_A) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (T_A) . . . . . . . . –55°C to +125°C

V_CCSupply Voltages

V_CCfor all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

24

Am29DL400B

P R E L I M I N A R Y

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

= V to V

Min

Typ

Max

±1.0

35

Unit

µA

V

,

CC

IN

SS

I

Input Load Current

LI

= V

CC

CC max

I

A9 Input Load Current

Output Leakage Current

V

= V

; A9 = 12.5 V

µA

LIT

CC

CC max

V

= V to V

,

OUT

SS

CC

I

±1.0

µA

LO

= V

CC

CC max

5 MHz

1 MHz

5 MHz

1 MHz

7

2

7

2

12

4

CE# = V OE# = V ,

Byte Mode

IL,

IH

V

Active Read Current

CC

I

mA

CC1

(Note 1)

12

4

CE# = V OE# = V ,

IL,

IH

Word Mode

V

Active Write Current

CC

I

CE# = V OE# = V , WE# = V

IL

15

0.2

30

5

mA

µA

CC2

CC3

CC4

CC5

IL,

IH

(Note 2)

V

Standby Current

V

= V

; OE# = V ;

CC

CC max IL

(CE# Controlled)

CE#, RESET# = V ± 0.3 V

CC

V

Reset Current

V

= V

;

CC

CC max

5

(RESET# Controlled)

RESET# = V ± 0.3 V

SS

V

= V ± 0.3 V;

CC

IH

IL

Automatic Sleep Mode (Note 3)

5

= V ± 0.3 V

SS

Byte

Word

Byte

21

45

V

Active Read-While-

CE# = V

CC

IL,

IH

I

mA

CC6

CC7

Program Current (Notes 1, 4)

OE#

V

=

V

Active Read-While-Erase CE# = V

CC

IL,

IH

Current (Notes 1, 4)

=

Word

V

Active Program-While-

CC

CE# = V

IL,

IH

I

Erase-Suspended Current

(Note 4)

17

35

mA

CC8

OE#

V

=

V

Input Low Voltage

Input High Voltage

–0.5

0.8

V

IL

V

0.7 x V

V

+ 0.3

CC

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 3.0 V ± 10%

CC

11.5

12.5

0.45

V

ID

V

Output Low Voltage

I

= 4.0 mA, V = V

CC min

V

OL

OH

CC

V

= –2.0 mA, V = V

CC min

0.85 V

OH1

OH2

CC

Output High Voltage

V

= –100 µA, V = V

V

–0.4

CC

CC min

Low V Lock-Out Voltage

(Note 4)

CC

V

2.3

2.5

V

LKO

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V .

CC

IH

2. I active while Embedded Erase or Embedded Program is in progress.

CC

3. Automatic sleep mode enables the low power mode when addresses remain stable for t

current is 200 nA.

+ 30 ns. Typical sleep mode

ACC

4. Not 100% tested.

Am29DL400B

25

P R E L I M I N A R Y

DC CHARACTERISTICS

Zero-Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

21606C-13

Figure 9. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

10

8

3.6 V

2.7 V

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

21606C-14

Figure 10. Typical I_CC1vs. Frequency

26

Am29DL400B

P R E L I M I N A R Y

TEST CONDITIONS

Table 7. Test Specifications

All

3.3 V

Test Condition

-70, -80

others Unit

2.7 kΩ

Output Load

1 TTL gate

Device

Under

Test

Output Load Capacitance, C

(including jig capacitance)

L

30

100

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

5

ns

0.0–3.0

1.5

V

Input timing measurement

reference levels

V

Note: Diodes are IN3064 or equivalent

Output timing measurement

reference levels

1.5

21606C-15

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

21606C-16

Figure 12. Input Waveforms and Measurement Levels

Am29DL400B

27

P R E L I M I N A R Y

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

JEDEC Std. Description

Test Setup

-70

70

30

25

-80

80

30

25

-90

80

35

30

-120 Unit

t

Read Cycle Time (Note 1)

Min

Max

120

50

ns

AVAV

RC

t

Address to Output Delay

CE#, OE# = V

IL

AVQV

ELQV

GLQV

EHQZ

GHQZ

ACC

t

Chip Enable to Output Delay

OE# = V

IL

CE

OE

t

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

t

30

DF

t

30

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First

t

Min

0

ns

AXQX

OH

Read

Output Enable Hold

t

OEH

Toggle and

Data# Polling

Time (Note 1)

10

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 7 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

21606C-17

Figure 13. Read Operation Timings

28

Am29DL400B

P R E L I M I N A R Y

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t

Max

20

µs

Ready

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t

Max

500

ns

Ready

t

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RP

t

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

RPD

t

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

21606C-18

Figure 14. Reset Timings

Am29DL400B

29

P R E L I M I N A R Y

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

JEDEC

Std.

Description

-70

-80

-90

-120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

ELFL/ ELFH

25

70

25

80

30

90

30

ns

FLQZ

FHQV

120

ns

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

DQ15/A-1

Switching

from word

to byte

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t

FHQV

21606C-19

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(t

)

AS

t

(t

)

HOLD AH

Note: Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

21606C-20

Figure 16. BYTE# Timings for Write Operations

Am29DL400B

30

P R E L I M I N A R Y

AC CHARACTERISTICS

Erase and Program Operations

Parameter

JEDEC

Std.

Description

-70

-80

-90

-120 Unit

t

Write Cycle Time (Note 1)

Min

70

80

90

120

ns

AVAV

WC

t

Address Setup Time

0

AVWL

WLAX

AS

t

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

45

50

ASO

t

AH

Address Hold Time From CE# or OE# high

during toggle bit polling

t

Min

0

ns

AHT

t

Data Setup Time

Min

35

20

35

20

45

20

50

25

ns

DVWH

DS

t

Data Hold Time

WHDX

DH

t

Output Enable High during toggle bit polling

OEPH

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

ELWL

WHEH

WLWH

CS

CH

WP

t

CE# Hold Time

t

Write Pulse Width

35

50

t

Write Pulse Width High

Zero Latency Between Read and Write Operations

30

0

WHDL

WPH

t

SR/W

Byte

Programming Operation (Note 2)

Word

9

t

µs

WHWH1

WHWH2

WHWH1

11

0.7

50

0

t

Sector Erase Operation (Note 2)

sec

µs

WHWH2

t

V

Setup Time (Note 1)

VCS

CC

t

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

RB

t

90

ns

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29DL400B

31

P R E L I M I N A R Y

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_GHWL

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

21606C-21

Figure 17. Program Operation Timings

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_GHWL

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Progress

Data

Complete

55h

30h

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

21606C-22

Figure 18. Chip/Sector Erase Operation Timings

Am29DL400B

32

P R E L I M I N A R Y

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

21606C-23

Figure 19. Back-to-Back Read/Write Cycle Timings

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

High Z

DQ0–DQ6

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21606C-24

Figure 20. Data# Polling Timings (During Embedded Algorithms)

Am29DL400B

33

P R E L I M I N A R Y

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

21606C-25

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

21606C-26

Figure 22. DQ2 vs. DQ6

34

Am29DL400B

P R E L I M I N A R Y

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std.

Description

Rise and Fall Time (See Note)

All Speed Options

Unit

t

V

Min

500

ns

VIDR

ID

RESET# Setup Time for Temporary Sector

Unprotect

t

4

µs

RSP

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t

Min

4

RRB

Note: Not 100% tested.

12 V

RESET#

0 V or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

21606C-27

Figure 23. Temporary Sector Unprotect Timing Diagram

Am29DL400B

35

P R E L I M I N A R Y

AC CHARACTERISTICS

V

ID

IH

V

RESET#

SA, A6,

A1, A0

Valid*

Sector Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector Protect: 100 µs

Sector Unprotect: 10 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

21606C-28

Figure 24. Sector Protect/Unprotect Timing Diagram

36

Am29DL400B

P R E L I M I N A R Y

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

JEDEC

Std.

Description

-70

-80

-90

-120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

70

80

90

120

AVAV

WC

t

0

ns

AVWL

AS

AH

DS

DH

t

45

35

45

35

45

50

ns

ELAX

DVEH

EHDX

t

ns

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

ns

GHEL

WLEL

GHEL

t

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

WS

t

EHWH

WH

t

CE# Pulse Width

CE# Pulse Width High

35

50

ELEH

EHEL

CP

t

30

9

CPH

Byte

t

Programming Operation (Note 2)

µs

WHWH1

Word

11

0.7

t

Sector Erase Operation (Note 2)

sec

WHWH2

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29DL400B

37

P R E L I M I N A R Y

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data, DQ7# = complement of the data written to the device,

= data written to the device.

D

OUT

3. Waveforms are for the word mode.

21606C-29

Figure 25. Alternate CE# Controlled Erase/Program Operation Timings

38

Am29DL400B

P R E L I M I N A R Y

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time

Chip Erase Time

Byte Program Time

Word Program Time

0.7

10

9

15

Excludes 00h programming

prior to erasure (Note 4)

300

360

13.5

8.7

11

4.5

2.9

µs

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

Chip Program Time

(Note 3)

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 2.7 V, 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 5 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE#, and RESET#)

SS

–1.0 V

12.5 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

CC

SS

V

Current

–100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.

CC

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

Typ

6

Max

7.5

12

Unit

pF

C

V

= 0

IN

C

Output Capacitance

Control Pin Capacitance

V

= 0

8.5

7.5

pF

OUT

C

V

= 0

IN

9

pF

IN2

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

Am29DL400B

39

P R E L I M I N A R Y

PHYSICAL DIMENSIONS*

TS 048—48-Pin Standard TSOP (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

48

11.90

12.10

0.50 BSC

24

25

0.05

0.15

18.30

18.50

19.80

20.20

16-038-TS48-2

TS 048

DT95

0.08

0.20

0.10

0.21

1.20

MAX

8-8-96 lv

0°

5°

0.25MM (0.0098") BSC

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering

TSR048—48-Pin Reverse TSOP (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

48

11.90

12.10

0.50 BSC

24

25

0.05

0.15

18.30

18.50

19.80

20.20

SEATING PLANE

16-038-TS48

TSR048

DT95

0.08

0.20

8-8-96 lv

1.20

MAX

0.10

0.21

0°

5°

0.25MM (0.0098") BSC

0.50

0.70

* For reference only. BSC is an ANSI standard for Basic Space Centering.

40

Am29DL400B

P R E L I M I N A R Y

PHYSICAL DIMENSIONS (continued)

SO 044—44-Pin Small Outline (measured in millimeters)

44

23

13.10

13.50

15.70

16.30

1

22

1.27 NOM.

TOP VIEW

28.00

28.40

0.10

0.21

2.17

2.45

2.80

MAX.

0°

8°

SEATING

PLANE

0.60

1.00

0.35

0.50

0.10

0.35

END VIEW

SIDE VIEW

16-038-SO44-2

SO 044

DF83

8-8-96 lv

Am29DL400B

41

P R E L I M I N A R Y

REVISION SUMMARY

Revision B

DC Characteristics

Added Note 4 reference to I_CC6and I_CC7

.

Expanded data sheet from Advance Information to Pre-

liminary version.

Erase and Program Operations

Revision C

Corrected note references for t_WHWH1, t_WHWH2, and

t_VCS

Global

Temporary Sector Unprotect

Changed -70R speed option to -70.

Added note reference to t_VIDR

.

Figure 1, In-system Sector Protect/Unprotect

Algorithm

Figure 24, Sector Protect/Unprotect Timing

Diagram

Added “PSLSCNT=1” to sector protect algorithm.

Updated figure to correct address waveform—valid ad-

dress not required in first cycle.

Reset Command

Deleted last paragraph; applies only to hardware reset.

Alternate CE# Controlled Erase/Program

Operations

DQ6: Toggle Bit I

Corrected note references for t_WHWH1, t_WHWH2

First and second para., clarified that the toggle bit may

be read “at any address within the programming or

erasing bank,” not at “any address.” Fourth para., clar-

ified “device” to “bank”

Erase and Programming Performance

In Note 2, changed worst case endurance to 1 million

cycles.

Operating Ranges

Deleted reference to regulated voltage range

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

42

Am29DL400B


型号：	AM29DL400BB-120ECB
厂家：	AMD
描述：	4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory 4兆位（ 512K的×8位/ 256千×16位） CMOS 3.0伏只，同时操作闪存闪存内存集成电路光电二极管
文件：	总42页 (文件大小：502K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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