AM29F100B-120SC_技术文档

FINAL

Am29F100

1 Megabit (128 K x 8-bit/64 K x 16-bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Embedded Algorithms

— 5.0 V ± 10% for read, erase, and program

— Embedded Erase algorithm automatically

pre-programs and erases the chip or any

combination of designated sector

operations

— Simplifies system-level power requirements

— Embedded Program algorithm automatically

programs and verifies data at specified address

■ High performance

— 70 ns maximum access time

■ Minimum 100,000 program/erase cycles

■ Low power consumption

guaranteed

— 20 mA typical active read current for byte mode

— 28 mA typical active read current for word mode

— 30 mA typical program/erase current

— 25 µA typical standby current

■ Package options

— 44-pin SO

— 48-pin TSOP

■ Compatible with JEDEC standards

■ Flexible sector architecture

— Pinout and software compatible with

single-power-supply flash

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

one 64 Kbyte sectors (byte mode)

— Superior inadvertent write protection

— One 8 Kword, two 4 Kword, one 16 Kword, and

one 32 Kword sectors (word mode)

■ Data# Polling and Toggle Bits

— Provides a software method of detecting

program or erase cycle completion

— Any combination of sectors can be erased

— Supports full chip erase

■ Ready/Busy pin (RY/BY#)

■ Top or bottom boot block configurations

— Provides a hardware method for detecting

program or erase cycle completion

available

■ Sector protection

■ Erase Suspend/Erase Resume

— Hardware-based feature that disables/re-

enables program and erase operations in any

combination of sectors

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

— Sector protection/unprotection can be

implemented using standard PROM

programming equipment

■ Hardware RESET# pin

— Hardware method of resetting the device to

reading array data

— Temporary Sector Unprotect feature allows in-

system code changes in protected sectors

Publication# 18926 Rev: C Amendment/+2

Issue Date: March 1998

GENERAL DESCRIPTION

The Am29F100 is a 1 Mbit, 5.0 Volt-only Flash memory

organized as 131,072 bytes or 65,536 words. The

Am29F100 is offered in 44-pin SO and 48-pin TSOP

packages. Word-wide data appears on DQ0-DQ15;

byte-wide data on DQ0-DQ7. The device is designed to

be programmed in-system with the standard system

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

5.0 Volt V

supply. A 12.0 volt V is not required for

CC

PP

program or erase operations. The device can also be

programmed or erased in standard EPROM program-

mers.

The Erase Suspend feature enables the system to put

erase on hold for any period of time to read data from,

or program data to, a sector that is not being erased.

The standard device offers access times of 70, 90,

120, and 150 ns, allowing high-speed microproces-

sors to operate without wait states. To eliminate bus

contention the device has separate chip enable

(CE#), write enable (WE#) and output enable (OE#)

controls.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is erased

when shipped from the factory.

The device requires only a single 5.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The hardware data protection measures include a

low V_CCdetector automatically inhibits write operations

during power transitions. The hardware sector pro-

tection feature disables both program and erase oper-

ations in any combination of the sectors of memory,

and is implemented using standard EPROM program-

mers. The temporary sector unprotect feature allows

in-system changes to protected sectors.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state machine that controls

the erase and programming circuitry. Write cycles also

internally latch addresses and data needed for the pro-

gramming and erase operations. Reading data out of

the device is similar to reading from other Flash or

EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

Device programming occurs by executing the program

command sequence. This invokes the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

The system can place the device into the standby mode.

Power consumption is greatly reduced in this mode.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability, and cost

effectiveness. The device electrically erases all bits

within a sector simultaneously via Fowler-Nordheim

tunneling. The bytes are programmed one byte at a

time using the EPROM programming mechanism of

hot electron injection.

Device erasure occurs by executing the erase com-

mand sequence. This invokes the Embedded Erase

algorithm—an internal algorithm that automatically pre-

programs the array (if it is not already programmed) be-

fore executing the erase operation. During erase, the

2

Am29F100

PRODUCT SELECTOR GUIDE

Family Part Number

Am29F100

Speed Option (V = 5.0 V ± 10%)

-70

70

30

-90

90

35

-120

120

50

-150

150

55

CC

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

Note: See the AC Characteristics section for full specifications.

BLOCK DIAGRAM

DQ0–DQ15

RY/BY#

Buffer

V

CC

Erase Voltage

Generator

Input/Output

Buffers

V

SS

State

Control

WE#

BYTE#

Command

Register

RESET#

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V

Detector

Timer

CC

Cell Matrix

A0–A15

A-1

18926C-1

Am29F100

3

CONNECTION DIAGRAMS

NC

BYTE#

V_SS

DQ15/A-1

DQ7

1

2

3

4

5

6

7

A15

A14

A13

A12

A11

A10

A9

A8

NC

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DQ14

DQ6

8

9

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

10

11

12

13

14

15

16

17

18

19

20

WE#

RESET#

NC

RY/BY#

Standard TSOP

NC

A7

A6

A5

A4

A3

21

22

23

24

OE#

V_SS

CE#

A0

A2

A1

18926C-2

NC

BYTE#

V_SS

1

2

3

4

5

6

7

A15

A14

A13

A12

A11

A10

A9

A8

NC

WE#

RESET#

NC

RY/BY#

NC

A7

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

8

9

10

11

12

13

14

15

16

17

18

19

20

Reverse TSOP

A6

A5

A4

A3

A2

A1

OE#

V_SS

CE#

A0

21

22

23

24

18926C-3

4

Am29F100

CONNECTION DIAGRAMS

NC

RY/BY#

NC

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

A7

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

CE# 12

V_SS13

35 A15

34 NC

SO

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

18926C-4

PIN CONFIGURATION

LOGIC SYMBOL

A0–A15

= 16 Addresses

DQ0–DQ14= 15 Data Inputs/Outputs

16

DQ15/A-1 = DQ15 (Data Input/Output, word mode),

A-1 (LSB Address Input, byte mode)

A0–A15

CE#

16 or 8

DQ0–DQ15

(A-1)

CE#

= Chip Enable

OE#

= Output Enable

OE#

WE#

BYTE#

= Write Enable

WE#

= Selects 8-bit or 16-bit mode

RESET#

RESET# = Hardware Reset Pin, Active Low

BYTE#

RY/BY#

V_CC

= Ready/Busy Output

= +5.0 Volt Single Power Supply

(See Product Selector Guide for speed

options and voltage supply tolerances)

18926C-5

V_SS

NC

= Device Ground

= Pin Not Connected Internally

Am29F100

5

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the elements below.

Am29F100

T

-70

E

C

B

OPTIONAL PROCESSING

Blank = Standard Processing

B

= Burn-In

(Contact an AMD representative for more infor-

mation.)

TEMPERATURE RANGE

C

I

=

Commercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Extended (–55°C to +125°C)

E

PACKAGE TYPE

E

F

S

=

48-Pin Thin Small Outline Package

(TSOP) Standard Pinout (TS 048)

48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout (TSR048)

44-Pin Small Outline Package

(SO 044)

SPEED OPTION

See Product Selector Guide and

Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29F100

1 Megabit (128 K x 8-Bit/64 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

AM29F100T-70,

AM29F100B-70

AM29F100T-90,

AM29F100B-90

EC, EI, EE,

FC, FI, FE,

SC, SI, SE

AM29F100T-120,

AM29F100B-120

AM29F100T-150,

AM29F100B-150

6

Am29F100

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register itself

does not occupy any addressable memory location.

The register is composed of latches that store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. The appropriate device bus operations table

lists the inputs and control levels required, and the re-

sulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F100 Device Bus Operations

DQ8–DQ15

BYTE#

Addresses

(Note 1)

DQ0–

DQ7

BYTE#

Operation

CE#

L

OE# WE# RESET#

= V

IH

IL

Read

L

H

X

H

X

H

L

H

A

D

OUT

IN

OUT

DQ8–DQ14 = High-Z,

DQ15 = A-1

Write

L

H

A

D

IN

Standby

V

± 0.5 V

X

H

X

V

± 0.5 V

X

High-Z

CC

Output Disable

Hardware Reset

L

H

L

X

Temporary Sector

Unprotect

X

V

A

D

IN

High-Z

ID

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Addresses In, D = Data In, D = Data Out

IL

IH ID

IN

OUT

Notes:

1. Addresses are A15:A0 in word mode (BYTE# = V ), A15:A-1 in byte mode (BYTE# = V ).

IH

IL

2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-

tection/Unprotection” section.

memory content occurs during the power transition.

Word/Byte Configuration

No command is necessary in this mode to obtain

The BYTE# pin controls whether the device data I/O

array data. Standard microprocessor read cycles that

pins DQ15–DQ0 operate in the byte or word configura-

assert valid addresses on the device address inputs

tion. If the BYTE# pin is set at logic ‘1’, the device is in

produce valid data on the device data outputs. The

word configuration, DQ15–DQ0 are active and con-

device remains enabled for read access until the

trolled by CE# and OE#.

command register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte

See “Reading Array Data” for more information. Refer

configuration, and only data I/O pins DQ0–DQ7 are ac-

to the AC Read Operations table for timing specifica-

tive and controlled by CE# and OE#. The data I/O pins

tions and to the Read Operations Timings diagram for

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

the timing waveforms. I_CC1in the DC Characteristics

an input for the LSB (A-1) address function.

table represents the active current specification for

reading array data.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

main at V_IH. The BYTE# pin determines whether the de-

vice outputs array data in words or bytes.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes

or words. Refer to “Word/Byte Configuration” for

more information.

The internal state machine is set for reading array

data upon device power-up, or after a hardware re-

set. This ensures that no spurious alteration of the

Am29F100

7

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables

indicate the address space that each sector occupies.

A “sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the en-

tire chip, or suspending/resuming the erase operation.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics tables, I_CC3represents the

standby current specification.

RESET#: HARDWARE RESET PIN

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the system

drives the RESET# pin low for at least a period of t_RP

,

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is ready

to accept another command sequence, to ensure data

integrity.

I_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_IL, the device enters

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I_CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section for timing diagrams.

the TTL standby mode; if RESET# is held at V_SS

0.5 V, the device enters the CMOS standby mode.

±

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

Standby Mode

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the in-

ternal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when CE#

and RESET# pins are both held at V_CC± 0.5 V. (Note

that this is a more restricted voltage range than V_IH.)

The device enters the TTL standby mode when CE#

and RESET# pins are both held at V_IH. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

Refer to the AC Characteristics tables for RESET# pa-

rameters and timing diagram.

Output Disable Mode

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

“RESET#: Hardware Reset Pin”.

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

8

Am29F100

Table 2. Sector Addresses Tables (Am29F100T)

A15

0

A14

X

A13

X

A12

X

(x8) Address Range

00000h-0FFFFh

10000h-17FFFh

18000h-19FFFh

1A000h-1BFFFh

1C000h-1FFFFh

(x16) Address Range

00000h-07FFFh

08000h-0BFFFh

0C000h-0CFFFh

0D000h-0DFFFh

0E000h-0FFFFh

SA0

SA1

SA2

SA3

SA4

1

0

X

1

0

1

0

1

X

Table 3. Sector Addresses Tables (Am29F100B)

A15

0

A14

0

A13

0

A12

X

(x8) Address Range

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-0FFFFh

10000h-1FFFFh

(x16) Address Range

00000h-01FFFh

02000h-02FFFh

03000h-03FFFh

04000h-07FFFh

08000h-0FFFFh

SA0

SA1

SA2

SA3

SA4

0

1

0

1

0

1

X

1

X

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

dress must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions table shows

the remaining address bits that are don’t care. When all

necessary bits have been set as required, the program-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

tions table. This method does not require V_ID. See

“Command Definitions” for details on using the autose-

lect mode.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Autoselect Codes (High Voltage Method) table. In ad-

dition, when verifying sector protection, the sector ad-

Table 4. Am29F100 Autoselect Codes (High Voltage Method)

A15 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V

X

L

X

L

X

01h

D9h

ID

Device ID:

Am29F100

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V

L

H

ID

L

H

X

22h

X

D9h

DFh

Device ID:

Am29F100

(Bottom Boot Block)

X

V

X

H

L

ID

01h

(protected)

X

Sector Protection Verification

L

H

SA

L

H

00h

(unprotected)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

Am29F100

9

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The

hardware sector unprotection feature re-enables

both program and erase operations in previously pro-

tected sectors.

START

RESET# = V

(Note 1)

ID

Sector protection/unprotection must be implemented

using programming equipment. The procedure re-

quires a high voltage (V_ID) on address pin A9 and the

control pins. Details on this method are provided in a

supplement, publication number 20373. Contact an

AMD representative to obtain a copy of the appropriate

document.

Perform Erase or

Program Operations

RESET# = V

IH

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

Temporary Sector

Unprotect

Completed (Note 2)

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

18926C-6

Notes:

1. All protected sectors unprotected.

Temporary Sector Unprotect

2. All previously protected sectors are protected once

again.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system.

The Sector Unprotect mode is activated by setting the

RESET# pin to V_ID. During this mode, formerly pro-

tected sectors can be programmed or erased by se-

lecting the sector addresses. Once V_IDis removed

from the RESET# pin, all the previously protected

sectors are protected again. Figure 1 shows the algo-

rithm, and the Temporary Sector Unprotect (Figure

17) diagram shows the timing waveforms, for this fea-

ture.

Figure 1. Temporary Sector Unprotect Operation

10

Am29F100

proper signals to the control pins to prevent uninten-

Hardware Data Protection

tional writes when V_CCis greater than V_LKO

.

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures prevent accidental erasure or pro-

gramming, which might otherwise be caused by spuri-

ous system level signals during V_CCpower-up and

power-down transitions, or from system noise.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of OE#

= V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cy-

cle, CE# and WE# must be a logical zero while OE#

is a logical one.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide the

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power

up, the device does not accept commands on the

rising edge of WE#. The internal state machine is

automatically reset to reading array data on

power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

ters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don’t care

for this command.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See “Erase Suspend/

Erase Resume Commands” for more information on

this mode.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

The system must issue the reset command to re-en-

able the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the “Reset Com-

mand” section, next.

Am29F100

11

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the device has reset to read-

ing array data, to ensure data integrity.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements. This method is an alternative to

that shown in the Autoselect Codes (High Voltage

Method) table, which is intended for PROM program-

mers and requires V_IDon address bit A9.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h or retrieves the manu-

facturer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code.

A read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protected, or 00h if it is un-

protected. Refer to the Sector Address tables for valid

sector addresses.

START

Write Program

Command Sequence

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Data Poll

from System

Embedded

Program

algorithm

in progress

Word/Byte Program Command Sequence

The system may program the device by byte or word,

on depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically provides internally gen-

erated program pulses and verify the programmed cell

margin. The Command Definitions take shows the ad-

dress and data requirements for the byte program com-

mand sequence.

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

for information on these status bits.

18926C-7

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 2. Program Operation

12

Am29F100

accepted, and erasure may begin. It is recommended

that processor interrupts be disabled during this time to

ensure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. If the time between additional sector erase

commands can be assumed to be less than 50 µs, the

system need not monitor DQ3. Any command other

than Sector Erase or Erase Suspend during the

time-out period resets the device to reading array

data. The system must rewrite the command sequence

and any additional sector addresses and commands.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector

Erase Timer” section.) The time-out begins from the ris-

ing edge of the final WE# pulse in the command se-

quence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Note that a hardware

reset during the chip erase operation immediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data integrity.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the op-

eration. The Sector Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

The system can determine the status of the erase

operation by using DQ7, DQ6, or RY/BY#. See

“Write Operation Status” for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data

and addresses are no longer latched.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, or RY/

BY#. Refer to “Write Operation Status” for information

on these status bits.

Figure 3 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to the Chip/Sector

Erase Operation Timings for timing waveforms.

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

the Sector Erase Operations Timing diagram for timing

waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock write cycles are then followed by the ad-

dress of the sector to be erased, and the sector erase

command. The Command Definitions table shows the

address and data requirements for the sector erase

command sequence.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to in-

terrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. Ad-

dresses are “don’t-cares” when writing the Erase Sus-

pend command.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time be-

tween these additional cycles must be less than 50 µs,

otherwise the last address and command might not be

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

Am29F100

13

minates the time-out period and suspends the erase

operation.

Erase Suspend command can be written after the de-

vice has resumed erasing.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system

can use DQ7 to determine if a sector is actively erasing

or is erase-suspended. See “Write Operation Status”

for information on these status bits.

START

Write Erase

Command Sequence

Data Poll

from System

Embedded

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine the

status of the program operation using the DQ7 or DQ6

status bits, just as in the standard program operation.

See “Write Operation Status” for more information.

Erase

algorithm

in progress

No

Data = FFh?

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

Yes

Erasure Completed

18926C-8

Notes:

1. See the appropriate Command Definitions table for erase

command sequence.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

14

Am29F100

Table 5. Am29F100 Command Definitions

Bus Cycles (Notes 2–4)

Third Fourth

Addr Data Addr Data Addr Data Addr Data

Command

Sequence

(Note 1)

First

Addr Data Addr Data

RA RD

Second

Fifth

Sixth

Read (Note 5)

Reset (Note 6)

1

XXXX F0

Word

Byte

Word

Byte

Word

Byte

5555

AA

2AAA

5555

2AAA

5555

2AAA

5555

AAAA

5555

Manufacturer ID

4

55

90 XX00

01

AAAA

5555

AA

XX01 22D9

XX02 D9

XX01 22DF

Device ID,

Top Boot Block

90

AAAA

5555

AA

Device ID,

Bottom Boot Block

AAAA

XX02

DF

XX00

XX01

00

(SA)

X02

Word

Byte

5555

AA

2AAA

5555

Sector Protect Verify

(Note 8)

4

55

90

(SA)

X04

AAAA

01

Word

Byte

Word

Byte

Word

Byte

5555

AA

2AAA

5555

2AAA

5555

2AAA

5555

AAAA

5555

Program

4

6

55

A0

80

PA

PD

AA

AAAA

5555

AA

5555

AAAA

5555

2AAA

5555

2AAA

5555

Chip Erase

55

10

30

AAAA

5555

AAAA

5555

AA

Sector Erase

SA

AAAA

Erase Suspend (Note 9)

Erase Resume (Note 10)

1

XXXX B0

XXXX 30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A15–A12 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

7. The fourth cycle of the autoselect command sequence is a

read operation.

2. All values are in hexadecimal.

8. The data is 00h for an unprotected sector and 01h for a

protected sector. See “Autoselect Command Sequence” for

more information.

3. Except when reading array or autoselect data, all bus cycles

are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.

9. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a

sector erase operation.

5. No unlock or command cycles required when reading array

data.

6. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

10. The Erase Resume command is valid only during the Erase

Suspend mode.

Am29F100

15

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: DQ3, DQ5, DQ6, DQ7, and

RY/BY#. Table 6 and the following subsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

Read DQ7–DQ0

Addr = VA

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# Polling is valid after the ris-

ing edge of the final WE# pulse in the program or

erase command sequence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for ap-

proximately 2 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active for approximately 100 µs, then the de-

vice returns to reading array data. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

18926C-9

following read cycles. This is because DQ7

DQ0 on the

Figure 4. Data# Polling Algorithm

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. The Data# Poll-

ing Timings (During Embedded Algorithms) figure in

the “AC Characteristics” section illustrates this.

16

Am29F100

system would note and store the value of the toggle

bit after the first read. After the second read, the sys-

tem would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

the system must write the reset command to return to

reading array data.

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

Table 6 shows the outputs for RY/BY#. The timing dia-

grams for read, reset, program, and erase shows the

relationship of RY/BY# to other signals.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 5).

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

DQ3: Sector Erase Timer

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” The system may ignore DQ3

if the system can guarantee that the time between ad-

ditional sector erase commands will always be less

Reading Toggle Bit DQ6

Refer to Figure 5 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

Am29F100

17

than 50 µs. See also the “Sector Erase Command Se-

quence” section.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other than Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

START

Read DQ7–DQ0

1

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

(Notes

1, 2)

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

18926C-10

Figure 5. Toggle Bit Algorithm

18

Am29F100

Table 6. Write Operation Status

DQ7

DQ5

Operation

(Note 1)

DQ7#

0

DQ6

(Note 2)

DQ3

N/A

1

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

1

Erase

Suspend

Mode

Reading within Non-Erase Suspended

Sector

Data

0

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Am29F100

19

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C

20 ns

+0.8 V

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –55°C to +125°C

–0.5 V

–2.0 V

Voltage with Respect to Ground

V_CC(Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +13.5 V

All other pins (Note 1) . . . . . . . . . . . .–2.0 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

20 ns

18926C-11

Notes:

Figure 6. Maximum Negative Overshoot

Waveform

1. Minimum DC voltage on input or I/O pin is –0.5 V. During

voltage transitions, inputs may overshoot V to –2.0 V

SS

for periods of up to 20 ns. See Figure 6. Maximum DC

voltage on input and I/O pins is V + 0.5 V. During volt-

CC

age transitions, input and I/O pins may overshoot to V

+ 2.0 V for periods up to 20 ns. See Figure 7.

CC

20 ns

2. Minimum DC input voltage on A9 pin is –0.5V. During

V

voltage transitions, A9 pins may overshoot V to –2.0 V

CC

SS

+2.0 V

V

+0.5 V

for periods of up to 20 ns. See Figure 6. Maximum DC in-

put voltage on A9 is +12.5 V which may overshoot to 13.5

V for periods up to 20 ns.

CC

3. No more than one output shorted at a time. Duration of

the short circuit should not be greater than one second.

2.0 V

20 ns

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these

or any other conditions above those indicated in the opera-

tional sections of this specification is not implied. Exposure of

the device to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

18926C-12

Figure 7. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Case Temperature (T_A) . . . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Case Temperature (T_A) . . . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Case Temperature (T_A) . . . . . . . . . . –55°C to +125°C

V

Supply Voltages

CC

V_CCfor all devices . . . . . . . . . . . . .+4.50 V to +5.50 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

20

Am29F100

DC CHARACTERISTICS

TTL/NMOS Compatible

Parameter

Symbol

Parameter Description

Test Description

= V to V , V = V Max

Min

Max

±1.0

50

Unit

µA

mA

V

I

Input Load Current

V

LI

IN

SS

CC

I

A9 Input Load Current

Output Leakage Current

= V Max, A9 = 12.5 V

LIT

CC

OUT

CC

I

= V to V , V = V Max

±1.0

40

LO

SS

CC

Byte

V

= V Max, CE# = V

CC IL,

CC

I

V

Active Current (Note 1)

CC1

CC

OE# = V

IH

Word

50

I

V

Active Current (Notes 2, 3)

Standby Current

V

= V Max, CE# = V OE# = V

IH

60

CC2

CC3

CC

IL,

V

Max, CE#

V

, OE# = V

IH

1.0

0.8

CC

CC = CC

=

IH

V

Input Low Voltage

–0.5

2.0

IL

V

Input High Voltage

V

+ 0.5

V

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 5.0 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

Output High Voltage

I

= 5.8 mA, V = V Min

V

OL

CC

V

= –2.5 mA, V = V Min

2.4

3.2

OH

CC

V

Low V Lock-out Voltage

4.2

LKO

CC

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V .

CC

IH

2. I active while Embedded Program or Embedded Erase Algorithm is in progress.

CC

3. Not 100% tested.

Am29F100

21

DC CHARACTERISTICS (continued)

CMOS Compatible

Parameter

Symbol

Parameter Description

Input Load Current

Test Description

= V to V , V = V Max

Min

Max

±1.0

50

Unit

µA

I

V

LI

IN

SS

CC

I

A9 Input Load Current

Output Leakage Current

= V Max, A9 = 12.5 V

µA

LIT

CC

OUT

CC

I

= V to V , V = V Max

±1.0

40

µA

LO

SS

CC

Byte

V

= V Max,

CC

I

V

Active Current (Note 1)

mA

CC1

CC2

CC

CE# = V OE# = V

IL,

IH

Word

50

Active Current (Notes 2, 3)

V

= V Max, CE# = V OE# = V

IH

60

CC

IL,

= V Max, OE# = V

CC

IH,

I

V

Standby Current

CE# and RESET# = V ± 0.5 V

100

µA

CC3

CC

V

Input Low Voltage

–0.5

0.8

V

IL

V

Input High Voltage

0.7 x V

V

+ 0.5

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 5.0 V

CC

11.5

12.5

0.45

V

ID

V

Output Low Voltage

I

= 5.8 mA, V = V Min

V

OL

OH

CC

V

= –2.5 mA, V = V Min

0.85 V

OH1

OH2

LKO

CC

Output High Voltage

= –100 µA, V = V Min

V

–0.4

CC

Low V Lock-out Voltage

3.2

4.2

CC

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V .

CC

IH

2. I active while Embedded Program or Embedded Erase Algorithm is in progress.

CC

3. Not 100% tested.

22

Am29F100

TEST CONDITIONS

Table 7. Test Specifications

5.0 V

Test Condition

-70

All others Unit

Output Load

1 TTL gate

100

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C

(including jig capacitance)

L

30

5

pF

C

L

Input Rise and Fall Times

Input Pulse Levels

20

ns

6.2 kΩ

0.0–3.0 0.45–2.4

V

Input timing measurement

reference levels

1.5

0.8

2.0

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

18926C-13

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

Am29F100

23

AC CHARACTERISTICS

Read-only Operations Characteristics

Parameter

Symbol

JEDEC

Std.

Parameter Description

Read Cycle Time (Note 1)

Test Setup

-70

-90

-120 -150 Unit

t

Min

70

90

120

150

ns

AVAV

RC

CE# = V

IL

t

Address to Output Delay

Max

70

90

AVQV

ACC

OE# = V

IL

t

Chip Enable to Output Delay

OE# = V

Max

70

30

20

90

35

20

120

50

150

55

ns

ELQV

GLQV

EHQZ

CE

IL

t

Output Enable to Output Delay

Chip Enable to Output High Z (Notes 1, 2)

OE

t

30

35

DF

Output Enable to Output High Z

(Notes 1, 2)

t

Max

Min

20

30

35

ns

GHQZ

Read

0

t

Output Enable Hold Time (Note 1)

OEH

Toggle and Data

Polling

10

Output Hold Time From Addresses CE# or

OE#, Whichever Occurs First

t

Min

0

ns

AXQX

OH

Notes:

1. Not 100% tested.

2. Output Driver Disable Time.

3. See Figure 8 and Table 7 for test specifications.

t_RC

Addresses Stable

Addresses

CE#

t_ACC

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

18926C-14

Figure 9. Read Operations Timings

24

Am29F100

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std Description

Test Setup

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t

Max

20

µs

READY

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

Max

500

ns

t

RESET# Pulse Width

Min

500

50

0

ns

RP

RH

RB

RESET# High Time Before Read (See Note)

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

18926C-15

Figure 10. RESET# Timings

Am29F100

25

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

JEDEC

Std.

Description

-70

-90

-120

-150 Unit

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

ns

ELFL/ ELFH

20

70

20

90

30

35

ns

FLQZ

FHQV

120

150

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

Switching

from word

to byte

DQ0–DQ14

DQ15/A-1

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t

FHQV

18926C-16

Figure 11. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(t

)

AS

t

(t

)

HOLD AH

Note:

Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

18926C-17

Figure 12. BYTE# Timings for Write Operations

26

Am29F100

AC CHARACTERISTICS

Erase and Program Operations

Parameter Symbol

JEDEC

Standard

Parameter Description

Write Cycle Time (Note 1)

-70

-90

-120

-150 Unit

t

Min

70

90

120

150

ns

AVAV

WC

t

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

0

AVWL

WLAX

AS

AH

DS

DH

t

45

30

45

50

t

DVWH

WHDX

0

Read Recover Time Before Write

(OE# High to WE# Low)

t

Min

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

µs

sec

µs

ns

ELWL

WHEH

WLWH

WHWL

CS

CH

WP

t

CE# Hold Time

t

Write Pulse Width

35

45

50

t

Write Pulse Width High

Byte Programming Operation (Note 2)

Chip/Sector Erase Operation (Note 2)

20

14

1.5

50

0

WPH

t

WHWH1

WHWH2

WHWH1

WHWH2

t

V

Set Up Time (Note 1)

CC

VCS

t

Recovery Time from RY/BY#

RB

t

Program/Erase Valid to RY/BY# Delay

30

35

50

55

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29F100

27

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_GHWL

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

18926C-13

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

Figure 13. Program Operation Timings

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

t_WC

VA

Addresses

CE#

2AAh

SA

555h for chip erase

t_AH

t_GHWL

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

18926C-13

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 14. Chip/Sector Erase Operation Timings

28

Am29F100

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

18926C-18

Figure 15. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

18926C-19

Figure 16. Toggle Bit Timings (During Embedded Algorithms)

Am29F100

29

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std.

Description

Rise and Fall Time (See Note)

All Speed Options

Unit

t

V

Min

500

ns

VIDR

ID

RESET# Setup Time for Temporary Sector

Unprotect

t

4

µs

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 5 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

18926C-20

Figure 17. Temporary Sector Unprotect Timing Diagram

30

Am29F100

AC CHARACTERISTICS

Erase and Program Operations

Alternate CE# Controlled Writes

Parameter Symbol

JEDEC

Standard

Parameter Description

Write Cycle Time (Note 1)

-70

-90

-120

-150

Unit

ns

µs

sec

t

Min

Typ

70

90

120

150

AVAV

AVEL

ELAX

WC

t

Address Setup Time

0

AS

AH

DS

DH

t

Address Hold Time

45

30

45

50

t

Data Setup Time

DVEH

EHDX

Data Hold Time

0

t

Output Enable Setup Time

Read Recover Time Before Write

WE# Setup Time

OES

t

GHEL

WLEL

t

WS

WH

t

WE# Hold Time

EHWH

t

CE# Pulse Width

35

45

50

ELEH

EHEL

CP

t

CE# Pulse Width High

Byte Programming Operation (Note 2)

Chip/Sector Erase Operation (Note 2)

20

14

CPH

t

WHWH1

WHWH2

WHWH1

WHWH2

1.5

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29F100

31

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

= Array Data.

18926C-21

OUT

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 18. Alternate CE# Controlled Write Operation Timings

32

Am29F100

ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Excludes 00h programming prior to

erasure (Note 4)

Chip/Sector Erase Time

1.5

15

sec

Byte Programming Time

14

28

1000

2000

12.5

µs

Excludes system-level overhead

(Note 5)

Word Programming Time

Chip Programming Time (Note 3)

1.8

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 5.0 V V , 100,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 4.5 V, 100,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.

LATCHUP CHARACTERISTIC

Parameter Description

Input Voltage with respect to V on I/O pins

Min

Max

+ 1.0 V

–1.0 V

V

CC

SS

V

Current

–100 mA

+100 mA

CC

Note: Includes all pins except V . Test conditions: V = 5.0 Volt, one pin at a time.

CC

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Conditions

Typ

6

Max

7.5

12

Unit

pF

C

V

= 0

IN

C

Output Capacitance

= 0

8.5

8

pF

OUT

C

Control Pin Capacitance

10

pF

IN2

IN

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

Am29F100

33

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

44

23

13.10

13.50

15.70

16.30

1

22

1.27 NOM.

TOP VIEW

28.00

28.40

0.10

0.21

2.17

2.45

2.80

MAX.

0°

8°

SEATING

PLANE

0.60

1.00

0.35

0.50

0.10

0.35

END VIEW

SIDE VIEW

16-038-SO44-2

SO 044

DF83

8-8-96 lv

34

Am29F100

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

48

11.90

12.10

0.50 BSC

24

25

0.05

0.15

18.30

18.50

19.80

20.20

16-038-TS48-2

TS 048

DT95

0.08

0.20

0.10

0.21

1.20

MAX

8-8-96 lv

0°

5°

0.25MM (0.0098") BSC

0.50

0.70

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

48

11.90

12.10

0.50 BSC

24

25

0.05

0.15

18.30

18.50

19.80

20.20

SEATING PLANE

16-038-TS48

TSR048

DT95

0.08

0.20

8-8-96 lv

1.20

MAX

0.10

0.21

0°

5°

0.25MM (0.0098") BSC

0.50

0.70

Am29F100

35

REVISION SUMMARY FOR AM29F100

Revision B+1

chip/sector erase times (t_WHWH1and t_WHWH2, respec-

tively).

Product Selector Guide

Erase and Programming Performance

Replaced the -75 column (70 ns, ±5%) with the -70 col-

umn (70 ns, ±10%).

Combined sector and chip erase times, added word

programming times and erase/program cycle times.

Updated specifications.

Ordering Information, Standard Products

The -70 designation is now listed in the part number ex-

ample.

Revision C

Global

Valid Combinations: Replaced the -75 combinations

with -70. The 70 ns speed grade is now available in the

same combinations as the other speed grades.

Made formatting and layout consistent with other data

sheets. Used updated common tables and diagrams.

Operating Ranges

Revision C+1

V_CCSupply Voltages: Changed the -75 designation

to -70.

Table 5, Command Definitions

Address bits A0–A14 are required for unlock cycles.

Therefore, addresses for second and fifth write cycles

are 2AAAh in word mode and 5555h in byte mode. Ad-

dresses for first, third, fourth, and sixth cycles are

5555h in word mode and AAAAh in byte mode. Read

cycles are not affected. Deleted Note 5 to reflect the

correction.

AC Characteristics

Read Only Operations: Changed the -75 column head

to -70. All parameters remain the same.

Figure 7, Test Conditions: Changed C_Lin Note 1 from -

75 to -70.

Write/Erase/Program Operations: Changed the -75

column head to -70. Changed byte programming and

chip/sector erase times (t_WHWH1and t_WHWH2, respec-

tively).

Revision C+2

AC Characteristics

Erase/Program Operations; Erase and Program Oper-

ations Alternate CE# Controlled Writes: Corrected the

notes reference for t_WHWH1and t_WHWH2. These param-

eters are 100% tested. Corrected the note reference

for t_VCS. This parameter is not 100% tested.

Switching Waveforms

Temporary Sector Unprotect Timing Diagram, Figure

18: Corrected the top waveform. RESET# begins at 0

V, then rises to 12 V in t_VIDR

.

Temporary Sector Unprotect Table

AC Characteristics

Added note reference for t_VIDR. This parameter is not

100% tested.

Alternate CE# Controlled Writes: Changed the -75 col-

umn head to -70. Changed byte programming and

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

36

Am29F100


型号：	AM29F100B-120SC
厂家：	AMD
描述：	1 Megabit (128 K x 8-bit/64 K x 16-bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory 1兆位（ 128千×8位/ 64千×16位） CMOS 5.0伏只，引导扇区闪存闪存内存集成电路光电二极管
文件：	总36页 (文件大小：423K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29F100B-120SC [AMD]

相关型号：

AM29F100B-120SCB

AM29F100B-120SE

AM29F100B-120SEB

AM29F100B-120SI

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AM29F100B-150EE

AM29F100B-150EEB

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