AM29F200BT-55_技术文档

Am29F200B

2 Megabit (256 K x 8-Bit/128 K x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ 5.0 V ± 10% for read and write operations

■ Embedded Algorithms

— Minimizes system level power requirements

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

■ Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29F200A device

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■ High performance

— Access times as fast as 45 ns

■ Minimum 1,000,000 write/erase cycles guaranteed

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package options

■ Low power consumption

— 20 mA typical active read current (byte mode)

— 28 mA typical active read current for

(word mode)

— 44-pin SO

— 30 mA typical program/erase current

— 48-pin TSOP

— 1 µA typical standby current

— Known Good Die (KGD)

(see publication number 21257)

■ Sector erase architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

three 64 Kbyte sectors (byte mode)

■ Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash

— One 8 Kword, two 4 Kword, one 16 Kword, and

three 32 Kword sectors (word mode)

— Superior inadvertent write protection

— Supports full chip erase

■ Data# Polling and Toggle Bit

— Sector Protection features:

— Detects program or erase cycle completion

■ Ready/Busy# output (RY/BY#)

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

— Hardware method for detection of program or

erase cycle completion

Sectors can be locked via programming equipment

■ Erase Suspend/Erase Resume

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

— Supports reading data from a sector not

being erased

■ Top or bottom boot block configurations available

■ Hardware RESET# pin

— Resets internal state machine to the reading

array data

Publication# 21526 Rev: B Amendment/+2

Issue Date: July 2, 1999

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

GENERAL DESCRIPTION

The Am29F200B is a 2 Mbit, 5.0 Volt-only Flash

memory organized as 262,144 bytes or 131,072 words.

The 8 bits of data appear on DQ0–DQ7; the 16 bits on

DQ0–DQ15. The Am29F200B is offered in 44-pin SO

and 48-pin TSOP packages. The device is also avail-

able in Known Good Die (KGD) form. For more

information, refer to publication number 21257. This

device is designed to be programmed in-system with

the standard system 5.0 volt V_CCsupply. A 12.0 volt

V_PPis not required for program or erase operations.

The device can also be reprogrammed in standard

EPROM programmers.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automati-

cally preprograms the array (if it is not already

programmed) before executing the erase operation.

During erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6/

DQ2 (toggle) status bits. After a program or erase

cycle has been completed, the device is ready to read

array data or accept another command.

This device is manufactured using AMD’s 0.32 µm

process technology, and offers all the features and

benefits of the Am29F200A, which was manufactured

using 0.5 µm process technology.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The standard device offers access times of 45, 50, 55,

70, 90, and 120 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus

contention the device has separate chip enable (CE#),

write enable (WE#) and output enable (OE#) controls.

Hardware data protection measures include a low

detector that automatically inhibits write opera-

V_CC

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of memory.

This can be achieved via programming equipment.

The device requires only a single 5.0 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the standby

mode. Power consumption is greatly reduced in this mode.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

2

Am29F200B

PRODUCT SELECTOR GUIDE

Family Part Number

Am29F200B

V

= 5.0 V ± 5%

= 5.0 V ± 10%

-45

-50

CC

Speed Option

-55

-70

70

30

-90

90

35

-120

120

50

CC

Max access time, ns (t

)

45

30

50

30

55

30

ACC

Max CE# access time, ns (t

)

CE

Max OE# access time, ns (t

)

OE

BLOCK DIAGRAM

DQ0–DQ15

RY/BY#

Buffer

RY/BY#

V

CC

Input/Output

Buffers

SS

Erase Voltage

Generator

State

Control

WE#

BYTE#

Command

Register

RESET#

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V

Detector

Timer

CC

X-Decoder

Cell Matrix

A0–A16

A-1

21526B-1

Am29F200B

3

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21257 for

more information.

NC

RY/BY#

NC

1

2

3

4

5

6

7

8

9

44 RESET#

43 WE#

42 A8

A7

41 A9

A6

40 A10

A5

39 A11

A4

38 A12

A3

37 A13

A2

36 A14

A1 10

A0 11

CE# 12

V_SS13

35 A15

34 A16

SO

33 BYTE#

32 V_SS

OE# 14

DQ0 15

DQ8 16

DQ1 17

DQ9 18

DQ2 19

DQ10 20

DQ3 21

DQ11 22

31 DQ15/A-1

30 DQ7

29 DQ14

28 DQ6

27 DQ13

26 DQ5

25 DQ12

24 DQ4

23 V_CC

21526B-2

4

Am29F200B

CONNECTION DIAGRAMS

This device is also available in Known Good Die (KGD) form. Refer to publication number 21257 for

more information.

A16

1

2

3

4

5

6

7

A15

A14

A13

A12

A11

A10

A9

A8

NC

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

BYTE#

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

8

9

10

11

12

13

14

15

16

17

18

19

20

DQ12

DQ4

WE#

RESET#

NC

RY/BY#

V

CC

Standard TSOP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

NC

A7

A6

A5

A4

A3

21

22

23

24

V

SS

CE#

A0

A2

A1

21526B-3

A16

1

2

3

4

5

6

7

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A15

A14

A13

A12

A11

A10

A9

A8

NC

WE#

RESET#

NC

RY/BY#

NC

A7

BYTE#

V

SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

8

9

DQ12

DQ4

10

11

12

13

14

15

16

17

18

19

20

Reverse TSOP

V

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

A6

A5

A4

A3

A2

A1

21

22

23

24

V

SS

CE#

A0

21526B-4

Am29F200B

5

PIN CONFIGURATION

LOGIC SYMBOL

A0–A16

=

17 addresses

17

DQ0–DQ14 = 15 data inputs/outputs

A0–A16

16 or 8

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

DQ0–DQ15

(A-1)

BYTE#

CE#

=

Selects 8-bit or 16-bit mode

Chip enable

CE#

OE#

Output enable

WE#

Write enable

RESET#

BYTE#

RESET#

RY/BY#

V_CC

Hardware reset pin, active low

Ready/Busy output

RY/BY#

+5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

21526B-5

V_SS

NC

=

Device ground

Pin not connected internally

6

Am29F200B

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

Am29F200B

T

-45

E

C

OPTIONAL PROCESSING

Blank = Standard Processing

B

=

Burn-In

(Contact an AMD representative for more information)

TEMPERATURE RANGE

C

I

=

Commercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Extended (–55°C to +125°C)

E

PACKAGE TYPE

E

F

S

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

44-Pin Small Outline Package (SO 044)

This device is also available in Known Good Die (KGD) form. See publication number

21257 for more information.

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29F200B

2 Megabit (256 K x 8-Bit128 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

AM29F200BT-45,

AM29F200BB-45

EC, EI, FC, FI, SC, SI

AM29F200BT-50,

AM29F200BB-50

AM29F200BT-55,

AM29F200BB-55

EC, EI, EE,

FC, FI, FE,

SC, SI, SE

AM29F200BT-70,

AM29F200BB-70

AM29F200BT-90,

AM29F200BB-90

AM29F200BT-120,

AM29F200BB-120

Am29F200B

7

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. The appropriate device bus

operations table lists the inputs and control levels

required, and the resulting output. The following sub-

sections describe each of these operations in further

detail.

Table 1. Am29F200B Device Bus Operations

DQ8–DQ15

BYTE# BYTE#

Operation

CE#

L

OE# WE#

RESET#

A0–A16

DQ0–DQ7

= V

IH

IL

Read

Write

L

H

X

H

X

H

L

H

A

D

High-Z

IN

OUT

L

D

IN

CMOS Standby

TTL Standby

V

± 0.5 V

X

H

X

V

± 0.5 V

CC

X

High-Z

High-Z High-Z

CC

H

L

H

L

X

Output Disable

Hardware Reset

X

Temporary Sector Unprotect

(See Note)

X

V

A

D

IN

X

ID

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, D = Data In, D

= Data Out, A = Address In

IN

IL

IH

ID

IN

OUT

Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.

content occurs during the power transition. No

Word/Byte Configuration

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert

valid addresses on the device address inputs produce

valid data on the device data outputs. The device

remains enabled for read access until the command

register contents are altered.

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. I_CC1in the DC Characteristics

table represents the active current specification for

reading array data.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

should remain at V_IH. On x16 (word-wide) devices, the

BYTE# pin determines whether the device outputs

array data in words or bytes.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

On x16 (word-wide) devices, for program operations,

the BYTE# pin determines whether the device accepts

program data in bytes or words. Refer to “Word/Byte

Configuration” for more information.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

8

Am29F200B

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Tables

indicate the address space that each sector occupies.

A “sector address” consists of the address bits required

to uniquely select a sector. See the “Command Defini-

tions” section for details on erasing a sector or the

entire chip, or suspending/resuming the erase

operation.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics tables, I_CC3represents the

standby current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the system

After the system writes the autoselect command

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings apply

in this mode. Refer to the “Autoselect Mode” and

“Autoselect Command Sequence” sections for more

information.

drives the RESET# pin low for at least a period of t_RP

,

the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state

machine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to

ensure data integrity.

I_CC2in the DC Characteristics table represents the

active current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_IL, the device enters

the TTL standby mode; if RESET# is held at V_SS

0.5 V, the device enters the CMOS standby mode.

±

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I_CC

read specifications apply. Refer to “Write Operation

Status” for more information, and to each AC Charac-

teristics section in the appropriate data sheet for timing

diagrams.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the

RESET# pin returns to V_IH.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when CE#

and RESET# pins are both held at V_CC± 0.5 V. (Note

that this is a more restricted voltage range than V_IH.)

The device enters the TTL standby mode when CE#

and RESET# pins are both held at V_IH. The device

requires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

Refer to the AC Characteristics tables for RESET#

parameters and timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high imped-

ance state.

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

“RESET#: Hardware Reset Pin”.

Am29F200B

9

Table 2. Am29F200T Top Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

A16

0

A15

0

A14

X

A13

X

A12

X

Kwords)

Address Range

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–37FFFh

38000h–39FFFh

3A000h–3BFFFh

3C000h–3FFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1BFFFh

1C000h–1CFFFh

1D000h–1DFFFh

1E000h–1FFFFh

0

1

X

1

0

X

1

0

X

1

0

1

0

1

8/4

1

X

16/8

Table 3. Am29F200B Bottom Boot Block Sector Address Table

Address Range (in hexadecimal)

Sector Size

(Kbytes/

(x8)

(x16)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

A16

0

A15

0

A14

0

A13

0

A12

X

Kwords)

Address Range

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

0

1

0

1

8/4

0

1

X

32/16

64/32

0

1

X

1

0

X

1

X

Note for Tables 2 and 3: Address range is A16:A-1 in byte mode and A16:A0 in word mode. See the “Word/Byte Configuration”

sectionfor more information.

Autoselect Mode

The autoselect mode provides manufacturer and

device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

address must appear on the appropriate highest order

address bits. Refer to the corresponding Sector

Address Tables. The Command Definitions table

shows the remaining address bits that are don’t care.

When all necessary bits have been set as required, the

programming equipment may then read the corre-

sponding identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

tions table. This method does not require V_ID. See

“Autoselect Command Sequence” for details on using

the autoselect mode.

When using programming equipment, the autoselect

mode requires V_ID(11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Autoselect Codes (High Voltage Method) table. In addi-

tion, when verifying sector protection, the sector

10

Am29F200B

Table 4. Am29F200B Autoselect Codes (High Voltage Method)

A16 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

DQ15

DQ7

to

DQ0

Description

A6

A1

A0

Manufacturer ID: AMD

L

H

X

V

X

L

X

L

X

01h

51h

ID

Device ID:

Am29F200B

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V

X

L

X

L

H

ID

L

H

X

22h

X

51h

57h

Device ID:

Am29F200B

(Bottom Boot Block)

X

V

X

ID

01h

(protected)

X

Sector Protection Verification

L

H

SA

L

H

L

ID

00h

(unprotected)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors.

START

RESET# = V

(Note 1)

ID

Sector protection/unprotection must be implemented

using programming equipment. The procedure

requires a high voltage (V_ID) on address pin A9 and the

control pins. Details on this method are provided in a

supplement, publication number 20551. Contact an

AMD representative to obtain a copy of the appropriate

document.

Perform Erase or

Program Operations

RESET# = V

IH

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

Temporary Sector

Unprotect

Completed (Note 2)

It is possible to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

21526B-6

Notes:

1. All protected sectors unprotected.

Temporary Sector Unprotect

2. All previously protected sectors are protected once

again.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the

RESET# pin to V_ID. During this mode, formerly pro-

tected sectors can be programmed or erased by

selecting the sector addresses. Once V_IDis removed

from the RESET# pin, all the previously protected

sectors are protected again. Figure 1 shows the algo-

rithm, and the Temporary Sector Unprotect diagram

(Figure 18) shows the timing waveforms, for this

feature.

Figure 1. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection measures prevent accidental erasure or pro-

Am29F200B

11

gramming, which might otherwise be caused by

spurious system level signals during V_CCpower-up and

power-down transitions, or from system noise.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Low V

Write Inhibit

CC

Logical Inhibit

When V_CCis less than V_LKO, the device does not

accept any write cycles. This protects data during V_CC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until V_CC

is greater than V_LKO. The system must provide the

proper signals to the control pins to prevent uninten-

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

tional writes when V_CCis greater than V_LKO

.

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the

improper sequence resets the device to reading array

data.

ters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Characteristics” section.

The reset command may be written between the

sequence cycles in an erase command sequence

before erasing begins. This resets the device to reading

array data. Once erasure begins, however, the device

ignores reset commands until the operation is

complete.

Reading Array Data

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or

Embedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The

system can read array data using the standard read

timings, except that if it reads at an address within

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to

reading array data (also applies during Erase

Suspend).

The system must issue the reset command to re-

enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the “Reset

Command” section, next.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements. This method is an alternative to

that shown in the Autoselect Codes (High Voltage

See also “Requirements for Reading Array Data” in the

“Device Bus Operations” section for more information.

The Read Operations table provides the read parame-

12

Am29F200B

Method) table, which is intended for PROM program-

mers and requires V_IDon address bit A9.

START

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

Write Program

Command Sequence

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code. A

read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode)

returns 01h if that sector is protected, or 00h if it is

unprotected. Refer to the Sector Address tables for

valid sector addresses.

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

No

Increment Address

Last Address?

Yes

The system may program the device by byte or word,

on depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up command.

The program address and data are written next, which

in turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

ings. The device automatically provides internally

generated program pulses and verify the programmed

cell margin. The Command Definitions take shows the

address and data requirements for the byte program

command sequence.

Programming

Completed

21526B-6

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 2. Program Operation

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See “Write Operation Status”

for information on these status bits.

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the device has reset to

reading array data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. Note that a

hardware reset during the chip erase operation imme-

diately terminates the operation. The Chip Erase

command sequence should be reinitiated once the

device has returned to reading array data, to ensure

data integrity.

Am29F200B

13

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write

Operation Status” for information on these status bits.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched.

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to “Write Operation Status” for infor-

mation on these status bits.

Figure 3 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in “AC

Characteristics” for parameters, and to the Chip/Sector

Erase Operation Timings for timing waveforms.

Figure 3 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations tables in

the “AC Characteristics” section for parameters, and to

the Sector Erase Operations Timing diagram for timing

waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the

sector erase command sequence.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to

interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation.

Addresses are “don’t-cares” when writing the Erase

Suspend command.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of

sectors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

rewrite the command sequence and any additional

sector addresses and commands.

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended

sectors produces status data on DQ7–DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to

determine if a sector is actively erasing or is erase-sus-

pended. See “Write Operation Status” for information

on these status bits.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

Timer” section.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

After an erase-suspended program operation is com-

plete, the system can once again read array data within

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See “Write Operation Status” for more

information.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the

operation. The Sector Erase command sequence

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

14

Am29F200B

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

START

Write Erase

Command Sequence

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the

device has resumed erasing.

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

21526B-7

Notes:

1. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

Am29F200B

15

Table 5. Am29F200B Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

Byte

Word

Byte

Word

Byte

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

AAA

555

X01

X02

X01

X02

2251

51

Device ID,

Top Boot Block

AAA

555

AAA

555

2257

57

Device ID,

Bottom Boot Block

AAA

XX00

XX01

00

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

2AA

555

AAA

555

Program

4

6

AA

55

A0

80

PA

PD

AA

555

AAA

555

2AA

555

2AA

555

Chip Erase

55

10

30

AAA

555

AAA

555

AAA

Sector Erase

SA

AAA

XXX

AAA

Erase Suspend (Note 10)

Erase Resume (Note 11)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A16–A12 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

1. See Table 1 for description of bus operations.

8. The fourth cycle of the autoselect command sequence is a

read cycle.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector and 01h for a

protected sector. See “Autoselect Command Sequence” for

more information.

3. Except when reading array or autoselect data, all bus cycles

are write operations.

4. Data bits DQ15–DQ8 are don’t cares for unlock and

command cycles.

10. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend

mode. The Erase Suspend command is valid only during a

sector erase operation.

5. Address bits A16–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

6. No unlock or command cycles required when reading array

data.

11. The Erase Resume command is valid only during the Erase

Suspend mode.

7. The Reset command is required to return to reading array

data when device is in the autoselect mode, or if DQ5 goes

high (while the device is providing status data).

16

Am29F200B

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 1 and the following subsec-

tions describe the functions of these bits. DQ7, RY/

BY#, and DQ6 each offer a method for determining

whether a program or erase operation is complete or in

progress. These three bits are discussed first.

Table 1 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

START

DQ7: Data# Polling

Read DQ7–DQ0

Addr = VA

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in progress

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

Yes

DQ7 = Data?

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 2 µs, then the device returns to reading

array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

21526B-8

following read cycles. This is because DQ7

DQ0 on the

Figure 4. Data# Polling Algorithm

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. The Data#

Polling Timings (During Embedded Algorithms) figure

in the “AC Characteristics” section illustrates this.

Am29F200B

17

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

The DQ2 vs. DQ6 figure shows the differences

between DQ2 and DQ6 in graphical form. See also the

subsection on “DQ2: Toggle Bit II”.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output,

several RY/BY# pins can be tied together in parallel

with a pull-up resistor to V_CC

.

DQ2: Toggle Bit II

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

Table 1 shows the outputs for RY/BY#. The timing dia-

grams for read, reset, program, and erase shows the

relationship of RY/BY# to other signals.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to

control the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 1 to compare outputs

for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

cause DQ6 to toggle. (The system may use either OE#

or CE# to control the read cycles.) When the operation

is complete, DQ6 stops toggling.

Figure 5 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the “DQ6: Toggle Bit I” subsection.

Refer to the Toggle Bit Timings figure for the toggle bit

timing diagram. The DQ2 vs. DQ6 figure shows the dif-

ferences between DQ2 and DQ6 in graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 toggles

for approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are

protected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5 for the following discussion. When-

ever the system initially begins reading toggle bit

status, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has com-

pleted the program or erase operation. The system can

read array data on DQ7–DQ0 on the following read

cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is erase-

suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6

toggles. When the device enters the Erase Suspend

mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing

or erase-suspended. Alternatively, the system can use

DQ7 (see the subsection on “DQ7: Data# Polling”).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

18

Am29F200B

the system must write the reset command to return to

reading array data.

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 1 shows the outputs for DQ3.

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 5).

START

Read DQ7–DQ0

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

Read DQ7–DQ0

(Note 1)

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

No

Toggle Bit

= Toggle?

Yes

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

No

DQ5 = 1?

Yes

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” The system may ignore DQ3 if the

system can guarantee that the time between additional

sector erase commands will always be less than 50 µs.

See also the “Sector Erase Command Sequence”

section.

(Notes

1, 2)

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

21526B-9

Figure 5. Toggle Bit Algorithm

Am29F200B

19

Table 1. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 1)

DQ6

(Note 2)

DQ3

N/A

1

(Note 1)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend Reading within Non-Erase

Data

0

Data

N/A

Data

N/A

1

0

Mode

Suspended Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

20

Am29F200B

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature

Commercial (C) Devices

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature (T_A) . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Ambient Temperature (T_A) . . . . . . . . .–40°C to +85°C

Extended (E) Devices

Voltage with Respect to Ground

V_CC(Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

Ambient Temperature (T_A) . . . . . . . .–55°C to +125°C

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V

V

_CCSupply Voltages

V_CCfor ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V

V_CCfor± 10% devices. . . . . . . . . . . . +4.5 V to +5.5 V

All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Note: Operating ranges define those limits between which

the functionality of the device is guaranteed.

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot V

SS

to –2.0 V for periods of up to 20 ns. See Figure 6.

Maximum DC voltage on input or I/O pins is V +0.5 V.

CC

During voltage transitions, input or I/O pins may overshoot

to V +2.0 V for periods up to 20 ns. See Figure 7.

CC

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot V to –2.0 V for periods of up

SS

to 20 ns. See Figure 6. Maximum DC input voltage on pin

A9 is +12.5 V which may overshoot to +13.5 V for periods

up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Note: Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the op-

erational sections of this data sheet is not implied. Exposure

of the device to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

20 ns

+0.8 V

V

CC

+2.0 V

–0.5 V

–2.0 V

V

CC

+0.5 V

2.0 V

20 ns

21526B-11

21526B-10

Figure 6. Maximum Negative Overshoot

Waveform

Figure 7. Maximum Positive Overshoot

Waveform

Am29F200B

21

DC CHARACTERISTICS

TTL/NMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

= V to V , V = V Max

Min

Max

Unit

I

Input Load Current

V

±1.0

µA

LI

IN

SS

CC CC

CC

A9, OE#, RESET# Input Load

Current

V

= V Max,

CC CC

I

50

µA

LIT

A9, OE#, RESET# = 12.5 V

I

Output Leakage Current

V

= V to V , V = V Max

±1.0

40

LO

OUT

SS

CC CC

CC

Byte

I

V

Active Read Current (Notes 1, 2) CE# = V , OE# = V

mA

CC1

CC

IL

IH

Word

50

Active Program/Erase Current

CC

I

CE# = V , OE# = V

60

CC2

CC3

IL

IH

(Notes 2, 3, 4)

V

Standby Current (Note 2)

V

= V Max, CE# = V , OE# = V

IH

1.0

0.8

mA

V

CC

IH

V

Input Low Voltage

Input High Voltage

–0.5

2.0

IL

V

+ 0.5

CC

V

IH

Voltage for Autoselect and Temporary

Sector Unprotect

V

= 5.0 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

Output High Voltage

I

= 5.8 mA, V = V Min

V

OL

CC

V

= –2.5 mA, V = V Min

2.4

3.2

OH

CC

V

Low V Lock-Out Voltage

4.2

LKO

CC

Notes:

1. The I current is typically less than 2 mA/MHz, with OE# at V

.

IH

CC

2. Maximum I specifications are tested with V = V .

CCmax

CC

3. I active while Embedded Program or Erase Algorithm is in progress.

CC

4. Not 100% tested.

22

Am29F200B

DC CHARACTERISTICS (Continued)

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

= V to V , V = V Max

Min

Typ

Max

Unit

I

Input Load Current

V

±1.0

µA

LI

IN

SS

CC CC

CC

A9, OE#, RESET# Input

Load Current

V

= V Max;

CC CC

I

50

µA

LIT

A9, OE#, RESET# = 12.5 V

I

Output Leakage Current

V

= V to V , V = V Max

±1.0

40

LO

OUT

SS

CC CC

CC

Byte

20

28

V

Active Read Current

CC

I

CE# = V , OE# = V

mA

CC1

IL

IH

(Notes 1, 2)

Word

50

V

Active Program/Erase

CC

I

CE# = V , OE# = V

30

1

50

mA

µA

CC2

CC3

IL

Current (Notes 2, 3, 4)

V

Standby Current

CC

CE# = V ± 0.5 V, OE# = V

5

CC

IH

Note (Note 5)

V

Input Low Voltage

Input High Voltage

–0.5

0.8

V

IL

V

0.7 x V

V

+ 0.3

CC

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 5.0 V

11.5

12.5

0.45

V

ID

CC

V

Output Low Voltage

I

= 5.8 mA, V = V Min

V

OL

OH

CC

V

= –2.5 mA, V = V Min

0.85 V

OH1

OH2

CC

Output Low Voltage

= –100 µA, V = V Min

V

– 0.4

CC

V

Low V Lock-Out Voltage

3.2

4.2

LKO

CC

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V .

CC

IH

2. Maximum I specifications are tested with V = V .

CCmax

CC

3. I active while Embedded Program or Erase Algorithm is in progress.

CC

4. Not 100% tested.

5. I

for extended temperature is 20 µA max (>+85°C).

CC3

Am29F200B

23

TEST CONDITIONS

Table 6. Test Specifications

5.0

-45, -50,

-55

All

others

Test Condition

Output Load

Unit

2.7 kΩ

1 TTL gate

100

Device

Under

Test

Output Load Capacitance, C

(including jig capacitance)

L

30

5

pF

C

L

6.2 kΩ

Input Rise and Fall Times

Input Pulse Levels

20

ns

0.0–3.0 0.45–2.4

V

Input timing measurement

reference levels

1.5

0.8, 2.0

V

Note:

Output timing measurement

reference levels

Diodes are IN3064 or equivalents.

21526B-12

Figure 8. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

24

Am29F200B

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC Std Description

Test Setup

-45

-50

-55

-70

-90 -120 Unit

t

Read Cycle Time (Note 1)

Address to Output Delay

Chip Enable to Output Delay

Min

Max

45

50

55

70

90

35

120

50

ns

AVAV

RC

CE# = V

OE# = V

IL

t

45

30

50

30

55

30

70

30

AVQV

ELQV

GLQV

ACC

t

OE# = V

CE

IL

Output Enable to Output Delay

(Note 1)

t

OE

Chip Enable to Output High Z

(Note 1)

t

Max

20

30

ns

EHQZ

GHQZ

DF

Output Enable to Output High Z

(Note 1)

t

Max

Min

ns

Read

0

Output Enable

t

Hold Time

(Note 1)

OEH

Toggle and

Data# Polling

10

Output Hold Time From

t

Addresses, CE# or OE#,

Whichever Occurs First (Note 1)

Min

0

ns

AXQX

OH

Notes:

1. Not 100% tested.

2. See Figure 8 and Table 6 for test specifications

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 9. Read Operations Timings

Am29F200B

25

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std Description

RESET# Pin Low (During Embedded

Test Setup

All Speed Options

Unit

t

Max

20

µs

READY

Algorithms) to Read or Write (See Note)

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

Max

500

ns

READY

t

RESET# Pulse Width

Min

500

50

0

ns

RP

RH

RB

RESET# High Time Before Read (See Note)

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

21526B-13

Figure 10. RESET# Timings

26

Am29F200B

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

Description

-45

-50

-55

-70

-90

-120 Unit

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

5

ns

ELFL/ ELFH

20

45

20

50

20

55

20

70

20

90

30

ns

FLQZ

FHQV

120

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

DQ0–DQ14

DQ15/A-1

Switching

from word

to byte

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t

FHQV

21526B-14

Figure 11. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(t

)

AS

t

(t

)

HOLD AH

Note:

Refer to the Erase/Program Operations table for t and t specifications.

AS

AH

21526B-15

Figure 12. BYTE# Timings for Write Operations

Am29F200B

27

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

-45

-50

-55

-70

-90

-120 Unit

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

45

50

55

70

90

120

ns

AVAV

WC

t

0

AVWL

WLAX

DVWH

WHDX

AS

AH

DS

DH

t

45

25

45

25

45

25

45

30

45

50

t

Data Hold Time

0

t

Output Enable Setup Time

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

ELWL

WHEH

WLWH

WHWL

CS

CH

WP

t

CE# Hold Time

t

Write Pulse Width

Write Pulse Width High

30

35

45

50

t

20

7

WPH

Byte

Word

Programming Operation

(Note 2)

t

µs

WHWH1

WHWH2

WHWH1

12

1

t

Sector Erase Operation (Note 2)

sec

µs

WHWH2

t

V

Setup Time (Note 1)

50

0

VCS

CC

t

Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

ns

RB

t

30

35

50

ns

BUSY

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

28

Am29F200B

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_GHWL

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

21526B-16

Figure 13. Program Operation Timings

Am29F200B

29

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_GHWL

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (”see “Write Operation Status”).

2. Illustration shows device in word mode.

21526B-17

Figure 14. Chip/Sector Erase Operation Timings

30

Am29F200B

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Status Data

True

Valid Data

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21526B-18

Figure 15. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

21526B-19

Figure 16. Toggle Bit Timings (During Embedded Algorithms)

Am29F200B

31

AC CHARACTERISTICS

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use OE# or CE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within the erase-sus-

pended sector.

21526B-20

Figure 17. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

Rise and Fall Time (See Note)

All Speed Options

Unit

t

V

Min

500

ns

VIDR

ID

RESET# Setup Time for Temporary Sector

Unprotect

t

4

µs

RSP

Note: Not 100% tested.

12 V

RESET#

0 or 5 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

21526B-21

Figure 18. Temporary Sector Unprotect Timing Diagram

32

Am29F200B

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

Std

Description

-45

-50

-55

-70

-90

-120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

45

50

55

70

90

120

AVAV

AVEL

ELAX

DVEH

EHDX

WC

t

0

ns

AS

AH

DS

DH

t

45

25

45

25

45

25

45

30

45

50

ns

t

ns

t

Data Hold Time

0

ns

t

Output Enable Setup Time

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHEL

WLEL

GHEL

t

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

WS

t

EHWH

WH

t

CE# Pulse Width

CE# Pulse Width High

30

35

45

50

ELEH

EHEL

CP

t

20

7

CPH

Byte

Word

Programming Operation

(Note 2)

t

µs

WHWH1

12

1

t

Sector Erase Operation (Note 2)

sec

WHWH2

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Am29F200B

33

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, D

= Array Data.

21526B-22

OUT

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 19. Alternate CE# Controlled Write Operation Timings

34

Am29F200B

ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter

Sector Erase Time

Typ (Note 1)

Max (Note 2)

Unit

sec

µs

Comments

1

5

8

Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time

Byte Programming Time

Word Programming Time

Chip Programming Time (Note 3)

7

300

500

5.4

Excludes system-level overhead

(Note 5)

12

1.8

µs

sec

Notes:

1. Typical program and erase times assume the following conditions: 25×C, 5.0 V V , 1,000,000 cycles. Additionally,

CC

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V = 4.5 V (V = 4.75 V for ±5% devices), 1,000,000 cycles.

CC

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Parameter Description

Input Voltage with respect to V on all I/O pins

Min

Max

+ 1.0 V

–1.0 V

V

CC

SS

V

Current

–100 mA

+100 mA

CC

Note: Includes all pins except V . Test conditions: V = 5.0 V, one pin at a time.

CC

TSOP AND SO PIN CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

= 0

Typ

6

Max

7.5

12

Unit

pF

C

V

IN

C

Output Capacitance

V

= 0

8.5

8

pF

OUT

C

Control Pin Capacitance

V

= 0

10

pF

IN2

IN

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

Am29F200B

35

PHYSICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

44

23

13.10

13.50

15.70

16.30

1

22

1.27 NOM.

TOP VIEW

28.00

28.40

0.10

0.21

2.17

2.45

2.80

MAX.

0°

8°

SEATING

PLANE

0.60

1.00

0.35

0.50

0.10

0.35

END VIEW

SIDE VIEW

16-038-SO44-2

SO 044

DF83

8-8-96 lv

36

Am29F200B

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

48

11.90

12.10

0.50 BSC

24

25

0.05

0.15

18.30

18.50

19.80

20.20

16-038-TS48-2

TS 048

DT95

0.08

0.20

0.10

0.21

1.20

MAX

8-8-96 lv

0°

5°

0.25MM (0.0098") BSC

0.50

0.70

Am29F200B

37

PHYSICAL DIMENSIONS

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

0.95

1.05

Pin 1 I.D.

1

48

11.90

12.10

0.50 BSC

24

25

0.05

0.15

18.30

18.50

19.80

20.20

SEATING PLANE

16-038-TS48

TSR048

DT95

0.08

0.20

8-8-96 lv

1.20

MAX

0.10

0.21

0°

5°

0.25MM (0.0098") BSC

0.50

0.70

38

Am29F200B

REVISION SUMMARY

Revision A

AC Characteristics

Figure 15. Data# Polling Timings (During Embedded

Algorithms): Added text to note.

Global: Made formatting and layout consistent with other

data sheets. Used updated common tables and diagrams

Figure 16. Toggle Bit Timings (During Embedded Algo-

rithms): Added text to note.

Revision B

Distinctive Characteristics

Added bullet for 20-year data retention at 125°C

Revision B+1 (April 12, 1999)

Product Selector Guide

Ordering Information

The 55 ns option now has a V_CCoperating range of

±10%.

Optional Processing: Deleted “B = Burn-in”.

DC Characteristics—TTL/NMOS Compatible

Revision B+2 (July 2, 1999)

I_CC1, I_CC2, I_CC3: Added Note 2 “Maximum I_CCspecifi-

cations are tested with V_CC= V_CCmax”.

Global

Added references to availability of device in Known

Good Die (KGD) form.

DC Characteristics—CMOS Compatible

I_CC1, I_CC2, I_CC3: Added Note 2 “Maximum I_CCspecifi-

cations are tested with V_CC= V_CCmax”.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

Am29F200B

39


型号：	AM29F200BT-55
厂家：	AMD
描述：	2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory 2兆位（ 256千×8位/ 128的K× 16位） CMOS 5.0伏只，引导扇区闪存闪存
文件：	总39页 (文件大小：486K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29F200BT-55 [AMD]

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