AM29LV001BT-45REE [AMD]
1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory; 1兆位（ 128千×8位） CMOS 3.0伏只引导扇区闪存
| 型号： | AM29LV001BT-45REE |
| 厂家： | 
AMD |
| 描述： | 1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory |
| 文件： | 总38页 (文件大小：425K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Am29LV001B
1 Megabit (128 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Unlock Bypass Mode Program Command
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Reduces overall programming time when
issuing multiple program command sequences
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■ Top or bottom boot block configurations
available
■ Embedded Algorithms
■ Manufactured on 0.35 µm process technology
■ High performance
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Full voltage range: access times as fast as 55 ns
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
— Regulated voltage range: access times as fast
as 45 ns
■ Minimum 1,000,000 write cycle guarantee per
■ Ultra low power consumption (typical values at
sector
5 MHz)
■ Package option
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 32-pin TSOP
— 32-pin PLCC
■ Compatibility with JEDEC standards
— 15 mA program/erase current
— Pinout and software compatible with single-
power supply Flash
■ Flexible sector architecture
— One 8 Kbyte, two 4 Kbyte, and seven 16 Kbyte
— Supports full chip erase
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Sector Protection features:
— Provides a software method of detecting
program or erase operation completion
Hardware method of locking a sector to prevent
any program or erase operations within that
sector
■ Erase Suspend/Erase Resume
Sectors can be locked in-system or via
programming equipment
— Supports reading data from or programming
data to a sector that is not being erased
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■ Hardware reset pin (RESET#)
— Hardware method for resetting the device to
reading array data
Publication# 21557 Rev: C Amendment/0
Issue Date: April 1998
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash
memory device organized as 131,072 bytes. The
Am29LV001B has a boot sector architecture.
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The device is offered in 32-pin PLCC and 32-pin TSOP
packages. The byte-wide (x8) data appears on DQ7–
DQ0. All read, erase, and program operations are
accomplished using only a single power supply. The
device can also be programmed in standard EPROM
programmers.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
The standard Am29LV001B offers access times of 45,
55, 70, and 90 ns, allowing high speed microproces-
sors to operate without wait states. To eliminate bus
contention, the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
Hardware data protection measures include a low
detector that automatically inhibits write opera-
VCC
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device requires only a single power supply (2.7
V–3.6V) for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The Am29LV001B is entirely command set compatible
with the JEDEC single-power-supply Flash
standard. Commands are written to the command reg-
ister using standard microprocessor write timings. Reg-
ister contents serve as input to an internal state-
machine that controls the erase and programming cir-
cuitry. Write cycles also internally latch addresses and
data needed for the programming and erase opera-
tions. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
The device offers two power-saving features. When ad-
dresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
Am29LV001B
2
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV001B
Regulated Voltage Range: V =3.0–3.6 V
-45R
CC
Speed Options
Max access time, ns (t
Full Voltage Range: V = 2.7–3.6 V
-55
-70
70
70
30
-90
90
90
35
CC
)
45
45
25
55
55
30
ACC
Max CE# access time, ns (t
)
CE
Max OE# access time, ns (t
)
OE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ7
V
CC
Sector Switches
V
SS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
X-Decoder
Y-Gating
STB
V
Detector
Timer
CC
Cell Matrix
A0–A16
21557C-1
3
Am29LV001B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A11
A9
A8
OE#
A10
CE#
1
2
3
32
31
30
A13
A14
NC
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
29
28
27
26
25
24
23
22
21
20
19
18
17
WE#
VCC
RESET#
A16
A15
A12
A7
32-Pin Standard TSOP
A6
A5
A4
A1
A2
A3
1
2
3
A11
A9
A8
OE#
A10
CE#
32
31
30
4
5
6
7
8
9
10
11
12
13
14
15
16
A13
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
29
28
27
26
25
24
23
22
21
20
19
18
17
A14
NC
WE#
VCC
32-Pin Reverse TSOP
RESET#
A16
A15
A12
A7
A6
A5
A1
A2
A3
A4
4
3 2 1 32 31 30
A7
A6
5
6
A14
A13
29
28
A5
A4
7
A8
27
26
25
24
23
22
21
8
A9
PLCC
A3
9
A11
OE#
A10
CE#
DQ7
A2
10
11
12
13
A1
A0
DQ0
16 17
19 20
18
15
14
21557C-2
Am29LV001B
4
P R E L I M I N A R Y
PIN CONFIGURATION
LOGIC SYMBOL
A0–A16
= 17 addresses
17
DQ0–DQ7 = 8 data inputs/outputs
A0–A16
8
CE#
=
=
=
=
=
Chip enable
DQ0–DQ7
OE#
Output enable
WE#
RESET#
VCC
Write enable
CE#
OE#
Hardware reset pin, active low
WE#
3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
RESET#
VSS
NC
=
=
Device ground
Pin not connected internally
21557C-3
5
Am29LV001B
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV001B
T
-45R
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
(Contact an AMD representative for more information)
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E
F
J
=
=
=
32-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 032)
32-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR032)
32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV001B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29LV001BT-45R,
Am29LV001BB-45R,
EC, FC, JC
Am29LV001BT-55,
Am29LV001BB-55,
EC, EI, EE,
FC, FI, FE,
JC, JI, JE
Am29LV001BT-70,
Am29LV001BB-70,
Am29LV001BT-90,
Am29LV001BB-90,
Am29LV001B
6
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV001B Device Bus Operations
Operation
CE#
L
OE#
L
WE#
H
RESET#
Addresses (Note 1)
DQ0–DQ7
Read
H
H
A
A
D
OUT
IN
IN
Write
L
H
L
D
IN
Standby
V
± 0.3 V
X
X
V
± 0.3 V
X
High-Z
High-Z
High-Z
CC
CC
Output Disable
Reset
L
H
H
H
L
X
X
X
X
X
Sector Address, A6 = L,
A1 = H, A0 = L
Sector Protect (Note 2)
L
H
L
V
D
D
, D
, D
ID
IN
OUT
OUT
Sector Address, A6 = H,
A1 = H, A0 = L
Sector Unprotect (Note 2)
L
H
X
L
V
V
ID
IN
Temporary Sector Unprotect
X
X
A
D
IN
ID
IN
Legend:
L = Logic Low = V , H = Logic High = V , V = 12.0 ± 0.5 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out
IL
IH
ID
IN
IN
OUT
Notes:
1. Addresses are A16–A0.
2. The in-system method of sector protection/unprotection is available. Sector protection/unprotection can be implemented by
using programming equipment. See the “Sector Protection/Unprotection” section.
Requirements for Reading Array Data
Writing Commands/Command Sequences
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at VIH.
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command
is necessary in this mode to obtain array data. Stand-
ard microprocessor read cycles that assert valid ad-
dresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicate the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has de-
tails on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
7
Am29LV001B
P R E L I M I N A R Y
nal register (which is separate from the memory array)
Automatic Sleep Mode
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC5 in the DC
Characteristics table represents the automatic sleep
mode current specification.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
V
CC ± 0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up
firmware from the Flash memory.The system may use
the RESET# pin to force the device into the standby
mode. Refer to the “Standby Mode” section for more in-
formation.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, RE-
SET#: Hardware Reset Pin.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
ICC3 in the DC Characteristics table represents the
standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
Am29LV001B
8
P R E L I M I N A R Y
Table 2. Am29LV001B Top Boot Sector Architecture
Sector Size
Address Range
(in hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
A16
A15
A14
A13
A12
(Kbytes)
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
8 Kbytes
0
0
0
X
X
00000h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1CFFFh
1D000h–1DFFFh
1E000h–1FFFFh
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
0
0
1
1
1
0
1
1
1
1
1
X
Table 3. Am29LV001B Bottom Boot Sector Architecture
Sector Size
Address Range (in
hexadecimal)
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
A16
A15
A14
A13
A12
(Kbytes)
8 Kbytes
4 Kbytes
4 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
0
0
0
0
X
00000h–01FFFh
02000h–02FFFh
03000h–03FFFh
04000h–07FFFh
08000h–0BFFFh
0C000h–0FFFFh
10000h–13FFFh
14000h–17FFFh
18000h–1BFFFh
1C000h–1FFFFh
0
0
0
1
0
0
0
0
1
1
0
0
1
X
X
0
1
0
X
X
0
1
1
X
X
1
0
0
X
X
1
0
1
X
X
1
1
0
X
X
1
1
1
X
X
9
Am29LV001B
P R E L I M I N A R Y
Table 4. In addition, when verifying sector protection,
Autoselect Mode
the sector address must appear on the appropriate
highest order address bits (see Table 2). Table 4 shows
the remaining address bits that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7-DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 4. Am29LV001B Autoselect Codes
A16 A11
to to
OE# WE# A12 A10
A8
to
A7
A5
to
A2
DQ7
to
DQ0
Description
CE#
A9
A6
A1
A0
Manufacturer ID: AMD
L
L
L
H
H
X
X
X
X
V
X
X
L
X
X
L
L
01h
ID
ID
Device ID: Am29LV001BT
(Top Boot Block)
L
L
V
L
L
L
L
H
H
EDh
Device ID: Am29LV001BB
(Bottom Boot Block)
L
L
H
H
X
X
X
V
X
X
X
X
6Dh
ID
ID
01h
(protected)
Sector Protection Verification
L
SA
V
L
H
L
00h
(unprotected)
L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.
IL
IH
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 1 shows the algo-
rithms and Figure 21 shows the timing diagram. This
method uses standard microprocessor bus cycle tim-
ing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect write
cycle.
Temporary Sector Unprotect
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RE-
SET# pin, all the previously protected sectors are
protected again. Figure 2 shows the algorithm, and
Figure 20 shows the timing diagrams, for this feature.
The alternate method intended only for programming
equipment requires VID on address pin A9, OE#, and
RESET#. This method is compatible with programmer
routines written for earlier 3.0 volt-only AMD flash de-
vices. Publication number 22134 contains further de-
tails; contact an AMD representative to request a copy.
Am29LV001B
10
P R E L I M I N A R Y
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 µs
Wait 1 µs
unprotect address
No
First Write
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
21557C-4
Figure 1. In-System Sector Protect/Unprotect Algorithms
Am29LV001B
11
P R E L I M I N A R Y
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
START
RESET# = V
(Note 1)
ID
Low V
Write Inhibit
CC
Perform Erase or
Program Operations
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
tional writes when VCC is greater than VLKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
21557C-5
Logical Inhibit
Notes:
1. All protected sectors unprotected.
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
2. All previously protected sectors are protected once
again.
Figure 2. Temporary Sector Unprotect Operation
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing incorrect address and data val-
ues or writing them in the improper sequence resets
the device to reading array data.
After the device accepts an Erase Suspend com-
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard
read timings, except that if it reads at an address
within erase-suspended sectors, the device outputs
status data. After completing a programming opera-
tion in the Erase Suspend mode, the system may
once again read array data with the same exception.
See “Erase Suspend/Erase Resume Commands” for
more information on this mode.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
The system must issue the reset command to re-ena-
ble the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 13 shows the timing diagram.
Am29LV001B
12
P R E L I M I N A R Y
program address and data are written next, which in
Reset Command
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim-
ings. The device automatically provides internally gen-
erated program pulses and verify the programmed cell
margin. Table 5 shows the address and data require-
ments for the byte program command sequence.
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using DQ7
or DQ6. See “Write Operation Status” for information
on these status bits.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command se-
quence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1,” or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
See “AC Characteristics” for parameters, and to Figure
14 for the timing diagram.
Unlock Bypass Command Sequence
Autoselect Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes to the device faster than using the standard
program command sequence. The unlock bypass com-
mand sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then en-
ters the unlock bypass mode. A two-cycle unlock by-
pass program command sequence is all that is required
to program in this mode. The first cycle in this se-
quence contains the unlock bypass program com-
mand, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 5 shows the requirements for the com-
mand sequence.
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 shows the address and data requirements. This
method is an alternative to that shown in Table 4, which
is intended for PROM programmers and requires VID
on address bit A9.
The autoselect command sequence is initiated by writ-
ing two unlock cycles, followed by the autoselect com-
mand. The device then enters the autoselect mode,
and the system may read at any address any number
of times, without initiating another command sequence.
A read cycle at address XX00h retrieves the manufac-
turer code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address
(SA) and the address 02h returns 01h if that sector is
protected, or 00h if it is unprotected. Refer to Table 2 for
valid sector addresses.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are
don’t cares for both cycles. The device then returns to
reading array data.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The device programs one byte of data for each program
operation. The command sequence requires four bus
cycles, and is initiated by writing two unlock write cy-
cles, followed by the program set-up command. The
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
13
Am29LV001B
P R E L I M I N A R Y
Characteristics” for parameters, and to Figure 15 for
timing diagrams.
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, or DQ2. See “Write Oper-
ation Status” for information on these status bits. When
the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no
longer latched.
START
Write Program
Figure 4 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to Figure 16 for
timing diagrams.
Command Sequence
Data Poll
from System
Sector Erase Command Sequence
Embedded
Program
algorithm
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 shows the address and data
requirements for the sector erase command sequence.
in progress
Verify Data?
Yes
No
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
No
Increment Address
Last Address?
Yes
Programming
Completed
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
21557C-6
Note:
See Table 5 for program command sequence.
Figure 3. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 5 shows
the address and data requirements for the chip erase
command sequence.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
Am29LV001B
14
P R E L I M I N A R Y
sector erase operation immediately terminates the op-
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
for more information.
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, or DQ2.
(Refer to “Write Operation Status” for information on
these status bits.)
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the de-
vice has resumed erasing.
Figure 4 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
Figure 16 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
When the Erase Suspend command is written during
a sector erase operation, the device requires a maxi-
mum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
No
Data = FFh?
Yes
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
Erasure Completed
21557C-7
Notes:
1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.
Figure 4. Erase Operation
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program oper-
ation. See “Write Operation Status” for more informa-
tion.
15
Am29LV001B
P R E L I M I N A R Y
Table 5. Am29LV001B Command Definitions
Bus Cycles (Notes 2–4)
Command Sequence
(Note 1)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5)
Reset (Note 6)
Manufacturer ID
1
1
4
RA
XXX
555
RD
F0
AA
2AA
2AA
55
55
555
555
90
90
X00
X01
01
Device ID, Top Boot
Block
ED
4
555
AA
Device ID, Bottom
Boot Block
6D
00
01
Sector Protect
Verify (Note 8)
SA
X02
4
555
AA
2AA
55
555
90
Byte Program
Unlock Bypass
4
3
555
555
AA
AA
2AA
2AA
55
55
555
555
A0
20
PA
PD
Unlock Bypass Program
(Note 9)
2
2
XXX
XXX
A0
90
PA
PD
00
Unlock Bypass Reset
(Note 10)
XXX
Chip Erase
6
6
1
1
555
555
AA
AA
B0
30
2AA
2AA
55
55
555
555
80
80
555
555
AA
AA
2AA
2AA
55
55
555
SA
10
30
Sector Erase
Erase Suspend (Note 11)
Erase Resume (Note 12)
XXX
XXX
Legend:
X = Don’t care
PD = Data to be programmed at location PA. Data is latched
on the rising edge of WE# or CE# pulse.
RA = Address of the memory location to be read.
SA = Address of the sector to be erased or verified. Address
bits A16–A12 uniquely select any sector.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses are latched on the falling edge of the WE# or CE#
pulse.
Notes:
1. See Table 1 for descriptions of bus operations.
8. The data is 00h for an unprotected sector and 01h for a
protected sector. The complete bus address in the fourth
cycle is composed of the sector address (A16–A12),
A1 = 1, and A0 = 0.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus
cycles are write operations.
9. The Unlock Bypass command is required prior to the
Unlock Bypass Program command.
4. Address bits A16–A11 are don’t care for unlock and
command cycles, unless SA or PA required.
10. The Unlock Bypass Reset command is required to return
to reading array data when the device is in the Unlock
Bypass mode.
5. No unlock or command cycles required when device is in
read mode.
6. The Reset command is required to return to the read
mode when the device is in the autoselect mode or if DQ5
goes high.
11. The system may read and program functions in non-
erasing sectors, or enter the autoselect mode, when in the
Erase Suspend mode. The Erase Suspend command is
valid only during a sector erase operation.
7. The fourth cycle of the autoselect command sequence is
a read cycle.
12. The Erase Resume command is valid only during the
Erase Suspend mode.
Am29LV001B
16
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 6 and the following subsections describe
the functions of these bits. DQ7, and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits
are discussed first.
START
Read DQ7–DQ0
Addr = VA
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
Yes
DQ7 = Data?
No
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for ap-
proximately 1 µs, then the device returns to reading
array data.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
21557C-8
Figure 5. Data# Polling Algorithm
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7–
following read cycles. This is because DQ7
DQ0 on the
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 17, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
17
Am29LV001B
P R E L I M I N A R Y
system may use either OE# or CE# to control the read
DQ6: Toggle Bit I
cycles.) But DQ2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. DQ6, by com-
parison, indicates whether the device is actively erasing,
or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Thus, both status bits
are required for sector and mode information. Refer to
Table 6 to compare outputs for DQ2 and DQ6.
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase op-
eration), and during the sector erase time-out.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “Reading Toggle Bits DQ6/DQ2”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 18 shows the toggle bit timing dia-
gram. Figure 19 shows the differences between DQ2
and DQ6 in graphical form.
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle (The system may use either OE# or CE#
to control the read cycles). When the operation is com-
plete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unpro-
tected sectors, and ignores the selected sectors that
are protected.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or
erase operation. If it is still toggling, the device did not
completed the operation successfully, and the system
must write the reset command to return to reading
array data.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm in flowchart form,
and the section “Reading Toggle Bits DQ6/DQ2” ex-
plains the algorithm. Figure 18 in the “AC Characteris-
tics” section shows the toggle bit timing diagrams.
Figure 19 shows the differences between DQ2 and
DQ6 in graphical form. See also the subsection on
DQ2: Toggle Bit II.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles, de-
termining the status as described in the previous para-
graph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation (top of Figure 6).
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
Table 6 shows the outputs for Toggle Bit I on DQ6. Fig-
ure 6 shows the toggle bit algorithm. Figure 18 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 19 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
DQ2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
Am29LV001B
18
P R E L I M I N A R Y
DQ5: Exceeded Timing Limits
START
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
Read DQ7–DQ0
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously pro-
grammed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has ex-
ceeded the timing limits, DQ5 produces a “1.”
Read DQ7–DQ0
(Note 1)
No
Toggle Bit
= Toggle?
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
Yes
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from “0” to
“1.” If the time between additional sector erase com-
mands from the system can be assumed to be less than
50 µs, the system need not monitor DQ3. See also the
“Sector Erase Command Sequence” section.
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has be-
gun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If
DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been ac-
cepted. Table 6 shows the outputs for DQ3.
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
21557C-9
Figure 6. Toggle Bit Algorithm
19
Am29LV001B
P R E L I M I N A R Y
Table 6. Write Operation Status
DQ7
DQ5
DQ2
Operation
(Note 2)
DQ7#
0
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
0
0
No toggle
Toggle
Standard
Mode
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
Am29LV001B
20
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
+0.8 V
Voltage with Respect to Ground
All pins except A9, OE# and RESET#
(Note 1) . . . . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V
–0.5 V
–2.0 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . .–0.5 V to +3.6 V
A9, OE#, and RESET# (Note 2) . . .–0.5 V to +12.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
20 ns
Notes:
21557C-10
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may undershoot V
SS
Figure7. MaximumNegativeOvershootWaveform
to –2.0 V for periods of up to 20 ns. See Figure 7.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot
to V +2.0 V for periods up to 20 ns. See Figure 8.
CC
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
20 ns
RESET# may undershoot V to –2.0 V for periods of up
V
SS
CC
to 20 ns. See Figure 7. Maximum DC input voltage on pin
A9 is +12.5 V which may overshoot to 14.0 V for periods
up to 20 ns.
+2.0 V
V
CC
+0.5 V
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
2.0 V
20 ns
20 ns
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the de-
vice at these or any other conditions above those indi-
cated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rat-
ing conditions for extended periods may affect device re-
liability.
21557C-1
Figure 8. Maximum Positive Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range. . . . . .+3.0 V to 3.6 V
VCC for full voltage range . . . . . . . . . . .+2.7 V to 3.6 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
21
Am29LV001B
P R E L I M I N A R Y
Test Conditions
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Min
Typ
Max
±1.0
35
Unit
µA
V
V
= V to V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 12.5 V
µA
LIT
CC
CC max
V
V
= V to V
,
CC
OUT
SS
I
±1.0
µA
LO
= V
CC
CC max
5 MHz
1 MHz
7
2
12
4
V
Active Read Current
CC
I
CE# = V OE#
V
V
mA
CC1
IL,
=
=
IH
(Note 1)
V
Active Write Current
CC
I
I
I
I
CE# = V OE#
15
0.2
0.2
0.2
30
5
mA
µA
µA
µA
CC2
CC3
CC4
CC5
IL,
IH
(Notes 2 and 4)
V
= V
;
CC max
CC
V
V
Standby Current
Reset Current
CC
CE#, RESET# = V ±0.3 V
CC
V
= V
;
CC max
CC
5
CC
RESET# = V ± 0.3 V
SS
V
V
= V ± 0.3 V;
CC
IH
IL
Automatic Sleep Mode (Note 3)
5
= V ± 0.3 V
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
V
0.7 x V
V
+ 0.3
IH
CC
CC
Voltage for Autoselect and
Temporary Sector Unprotect
V
= 3.3 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
I
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
OH
OH
CC
V
= –2.0 mA, V = V
0.85 V
OH1
OH2
CC
CC min
CC min
CC
Output High Voltage
V
= –100 µA, V = V
V
–0.4
CC
CC
Low V Lock-Out Voltage
(Note 4)
CC
V
2.3
2.5
V
LKO
Notes:
1. The I current listed is typically less than 2 mA/MHz, with OE# at V
.
IH
CC
2. I active while Embedded Erase or Embedded Program is in progress.
CC
3. Automatic sleep mode enables the low power mode when addresses remain stable for t
current is 200 nA.
+ 30 ns. Typical sleep mode
ACC
4. Not 100% tested.
Am29LV001B
22
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
Zero Power Flash
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
21557C-12
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
21557C-13
Figure 10. Typical ICC1 vs. Frequency
23
Am29LV001B
P R E L I M I N A R Y
TEST CONDITIONS
Table 7. Test Specifications
3.3 V
-45R,
-55
-70,
-90
Test Condition
Output Load
Unit
2.7 kΩ
Device
Under
Test
1 TTL gate
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
Input timing measurement
reference levels
1.5
1.5
V
V
Note:
Diodes are IN3064 or equivalent
Output timing measurement
reference levels
21557C-14
Figure 11. Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
21557C-15
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
21557C-16
Figure 12. Input Waveforms and Measurement Levels
Am29LV001B
24
P R E L I M I N A R Y
AC CHARACTERISTICS
Read Operations
Parameter
Speed Option
JEDEC
Std. Description
Test Setup
Min
-45R
-55
-70
-90
Unit
t
t
Read Cycle Time (Note 1)
Address to Output Delay
45
55
70
90
ns
AVAV
RC
CE# = V
IL
IL
t
t
Max
45
55
70
90
ns
AVQV
ACC
OE# = V
t
t
t
Chip Enable to Output Delay
OE# = V
Max
Max
Max
Max
Min
45
25
10
10
55
30
15
15
70
30
25
25
90
35
30
30
ns
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
IL
t
t
Output Enable to Output Delay
OE
t
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
DF
DF
t
t
Read
0
Output Enable
t
OEH
Toggle and
Data# Polling
Hold Time (Note 1)
Min
Min
10
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
t
t
0
AXQX
OH
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
21557C-17
Figure 13. Read Operations Timings
25
Am29LV001B
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std. Description
Test Setup
Max
All Speed Options
Unit
RESET# Pin Low (During Embedded
t
20
µs
READY
Algorithms) to Read or Write (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
t
Max
500
ns
READY
t
t
RESET# Pulse Width
Min
Min
Min
500
50
ns
ns
µs
RP
RESET# High Time Before Read (See Note)
RESET# Low to Standby Mode
RH
t
20
RPD
Note:
Not 100% tested.
CE#, OE#
tRH
RESET#
n/a Am29F002NB
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
RESET#
n/a Am29F002NB
tRP
21557C-18
Figure 14. RESET# Timings
Am29LV001B
26
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC
Std.
Description
-45R
-55
-70
-90
Unit
ns
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
45
55
70
90
AVAV
WC
t
t
0
ns
AVWL
WLAX
AS
AH
DS
DH
t
t
35
20
45
20
45
35
45
45
ns
t
t
t
ns
DVWH
WHDX
t
0
0
ns
t
Output Enable Setup Time (Note 1)
Min
Min
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
0
ns
GHWL
GHWL
t
t
t
CE# Setup Time
Min
Min
Min
Min
Typ
Typ
Min
0
0
ns
ns
ELWL
WHEH
WLWH
WHWL
CS
CH
WP
t
t
CE# Hold Time
t
Write Pulse Width
25
30
35
35
ns
t
t
Write Pulse Width High
Programming Operation (Note 2)
Sector Erase Operation (Note 2)
30
9
ns
WPH
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
t
t
0.7
50
sec
µs
t
V
Setup Time (Note 1)
VCS
CC
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” Section for more information.
27
Am29LV001B
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
PA
tWC
Addresses
555h
PA
PA
tAH
CE#
OE#
tCH
tGHWL
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
Data
VCC
tVCS
Notes:
1. PA = program address, PD = program data, D
is the true data at the program address.
OUT
21557C-19
Figure 15. Program Operation Timings
Am29LV001B
28
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tGHWL
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
VCC
Complete
55h
30h
Progress
10 for Chip Erase
tVCS
Note:
SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
21557C-20
Figure 16. Chip/Sector Erase Operation Timings
29
Am29LV001B
P R E L I M I N A R Y
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
WE#
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
21557C-21
Figure 17. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
CE#
VA
tACC
tCE
VA
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
(second read)
(stops toggling)
Note:
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle,
and array data read cycle.
21557C-22
Figure 18. Toggle Bit Timings (During Embedded Algorithms)
Am29LV001B
30
P R E L I M I N A R Y
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note:
The system can use OE# or CE# to toggle DQ2/DQ6. DQ2 toggles only when read at an address within an erase-suspended
sector.
21557C-23
Figure 19. DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std.
Description
Rise and Fall Time
All Speed Options
Unit
t
V
Min
Min
500
ns
VIDR
ID
RESET# Setup Time for Temporary Sector
Unprotect
t
4
µs
RSP
Note: Not 100% tested.
12 V
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
21557C-24
Figure 20. Temporary Sector Unprotect Timing Diagram
31
Am29LV001B
P R E L I M I N A R Y
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Sector Protect/Unprotect
60h 60h
Valid*
Valid*
Status
Verify
40h
Data
Sector Protect: 100 µs
Sector Unprotect: 10 ms
1 µs
CE#
WE#
OE#
Note:
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
21557C-25
Figure 21. In-System Sector Protect/Unprotect Timing Diagram
Am29LV001B
32
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC
Std.
Description
-45
-55
-70
-90
Unit
ns
t
t
t
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Min
Min
Min
Min
Min
Min
45
55
70
90
AVAV
AVEL
ELAX
DVEH
EHDX
WC
t
0
ns
AS
AH
DS
DH
t
t
35
20
45
20
45
35
45
45
ns
t
t
t
ns
t
Data Hold Time
0
0
ns
t
Output Enable Setup Time (Note 1)
ns
OES
Read Recovery Time Before Write
(OE# High to WE# Low)
t
t
t
Min
0
ns
GHEL
WLEL
GHEL
t
WE# Setup Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
WS
t
t
WE# Hold Time
EHWH
WH
t
t
CE# Pulse Width
25
30
35
35
ns
ELEH
EHEL
CP
t
t
CE# Pulse Width High
Programming Operation (Notes 1, 2)
Sector Erase Operation (Notes 1, 2)
30
9
ns
CPH
t
t
µs
WHWH1
WHWH2
WHWH1
WHWH2
t
t
0.7
sec
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” Section for more information.
33
Am29LV001B
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tDS
tDH
DQ7#
DOUT
Data
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
Notes:
1. Figure indicates the last two bus cycles of the program or erase command sequence.
2. PA program address, SA = Sector Address, PD = program data, DQ7# = complement of the data written to the device,
= data written to the device.
D
OUT
21557C-26
Figure 22. Alternate CE# Controlled Write Operation Timings
Am29LV001B
34
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
s
Comments
Sector Erase Time
0.7
7
15
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
s
Byte Programming Time
Chip Programming Time (Note 3)
9
300
µs
s
Excludes system level
overhead (Note 5)
1.1
3.3
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V , 1,000,000 cycles. Additionally,
CC
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V = 2.7 V (3.0 V for -45R), 1,000,000 cycles.
CC
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 5 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to V on all pins except I/O pins
(including A9, OE#, and RESET#)
SS
–1.0 V
13.0 V
Input voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
CC
SS
V
Current
–100 mA
+100 mA
CC
Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
TSOP PIN CAPACITANCE
Parameter
Symbol
Parameter Description
Input Capacitance
Test Setup
= 0
Typ
6
Max
7.5
12
Unit
pF
C
V
IN
IN
C
Output Capacitance
Control Pin Capacitance
V
= 0
8.5
7.5
pF
OUT
OUT
C
V
= 0
IN
9
pF
IN2
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
PLCC PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
Max
6
Unit
pF
C
Input Capacitance
V
V
V
4
8
8
IN
IN
C
Output Capacitance
Control Pin Capacitance
= 0
= 0
12
12
pF
OUT
OUT
C
pF
IN2
PP
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
35
Am29LV001B
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
PL 032
32-Pin Plastic Leaded Chip Carrier (measured in inches)
.485
.495
.447
.453
.009
.015
.042
.056
.125
.140
.585
.595
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
16-038FPO-5
PL 032
DA79
.026
.032
TOP VIEW
SIDE VIEW
6-28-94 ae
Am29LV001B
36
P R E L I M I N A R Y
PHYSICAL DIMENSIONS*
TS 032
32-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
7.90
8.10
0.50 BSC
0.05
0.15
18.30
18.50
19.80
20.20
0.08
16-038-TSOP-2
TS 032
DA95
1.20
MAX
0.20
0.10
0.21
3-25-97 lv
0˚
5˚
0.50
0.70
* For reference only. BSC is an ANSI standard for Basic Space Centering
37
Am29LV001B
P R E L I M I N A R Y
PHYSICAL DIMENSIONS*
TSR032
32-Pin Reverse Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
7.90
8.10
0.50 BSC
0.05
0.15
18.30
18.50
19.80
20.20
16-038-TSOP-2
TSR032
DA95
0.08
1.20
MAX
0.20
0.10
0.21
4-4-95 ae
0°
5°
0.25MM (0.0098") BSC
0.50
0.70
* For reference only. BSC is an ANSI standard for Basic Space Centering
Distinctive Characteristics
REVISION SUMMARY FOR AM29LV001B
Revision B
Changed process technology to 0.33 µm.
Temporary Sector Unprotect
Split the Am29LV001B/Am29LV010B data sheet, with
the elimination of all references to Am29LV010B.
Entered timing specifications for tVIDR and tRSP
.
Erase and Programming Performance
Revision C
Changed endurance in Note 2 to 1 million cycles;
added worst case voltage for -45R speed option.
Global
Deleted 120 ns speed option; added 90 ns speed
option.
Trademarks
Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
Am29LV001B
38
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