AM29LV160MT70REI_技术文档

Am29LV160M

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not available for designs. For new and current designs,

S29GL016A supersedes Am29LV160M and is the factory-recommended migration path. Please refer

to the S29GL016A datasheet for specifications and ordering information. Availability of this docu-

ment is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 25974 Revision B Amendment 5 Issue Date January 31, 2007

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29LV160M

TM

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBit

3.0 Volt-only Boot Sector Flash Memory

This product has been retired and is not available for designs. For new and current designs, S29GL016A supersedes Am29LV160M and is the factory-recom-

mended migration path. Please refer to the S29GL016A datasheet for specifications and ordering information. Availability of this document is retained for

reference and historical purposes only.

Distinctive Characteristics

Low power consumption (typical values at 5 MHz)

Architectural Advantages

— 400 nA standby mode current

— 15 mA read current

Single power supply operation

— 3 V for read, erase, and program operations

Manufactured on 0.23 µm MirrorBit^TMprocess

technology

— 40 mA program/erase current

— 400 nA Automatic Sleep mode current

— Fully compatible with Am29LV160D device

Package options

Secured Silicon Sector region

— 48-ball Fine-pitch BGA

— 64-ball Fortified BGA

— 48-pin TSOP

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

Software Features

— May be programmed and locked at the factory or by

the customer

— Program Suspend & Resume: read other sectors

before programming operation is completed

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

— Data# polling & toggle bits provide status

— Unlock Bypass Program command reduces overall

multiple-word programming time

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-

one 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and thirty-

one 32 Kword sectors (word mode)

Compatibility with JEDEC standards

— Provides pinout and software compatibility for single-

power supply flash, and superior inadvertent write

protection

Hardware Features

Top or bottom boot block configurations available

Minimum 100,000 erase cycle guarantee per sector

20-year data retention at 125°C

— Sector Protection: hardware-level method of

preventing write operations within a sector

— Temporary Sector Unprotect: V_ID-level method of

changing code in locked sectors

Performance Characteristics

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) indicates program or

erase cycle completion

High performance

— Access times as fast as 70 ns

— 0.7 s typical sector erase time

Publication Number 25974 Revision B Amendment 5 Issue Date January 31, 2007

This Data Sheet states AMD’s current specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications

due to changes in technical specifications.

D a t a S h e e t

General Description

The Am29LV160M is a 16 Mbit, 3.0 Volt-only Flash memory organized as

2,097,152 bytes or 1,048,576 words. The device is offered in a 48-ball Fine-pitch

BGA, 64-ball Fortified BGA, and 48-pin TSOP packages. The word-wide data (x16)

appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. The de-

vice requires only a single 3.0 volt power supply for both read and write

functions, designed to be programmed in-system with the standard system 3.0

volt V_CCsupply. The device can also be programmed in standard

EPROM programmers.

The device offers access times of 70, 85, 90, and 100 ns. To eliminate bus conten-

tion the device contains separate chip enable (CE#), write enable (WE#) and

output enable (OE#) controls.

The device is entirely command set compatible with the JEDEC single-power-

supply Flash standard. Commands are written to the device using standard

microprocessor write timing. Write cycles also internally latch addresses and data

needed for the programming and erase operations.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Device programming and erasure are initiated through command sequences.

Once a program or erase operation starts, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#

(RY/BY#) output to determine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces command sequence overhead

by requiring only two write cycles to program data instead of four.

Hardware data protection measures include a low V_CCdetector that automati-

cally inhibits write operations during power transitions. The hardware sector

protection feature disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or via programming

equipment.

The Erase Suspend/Erase Resume feature allows the host system to pause an

erase operation in a given sector to read or program any other sector and then

complete the erase operation. The Program Suspend/Program Resume fea-

ture enables the host system to pause a program operation in a given sector to

read any other sector and then complete the program operation.

The hardware RESET# pin terminates any operation in progress and resets the

device, after which it is then ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would thus also reset the de-

vice, enabling the host system to read boot-up firmware from the Flash memory

device.

The device reduces power consumption in the standby mode when it detects

specific voltage levels on CE# and RESET#, or when addresses are stable for a

specified period of time.

The Secured Silicon Sector provides a 128-word/256-byte area for code or

data that can be permanently protected. Once this sector is protected, no further

changes within the sector can occur.

MirrorBit flash technology combines years of Flash memory manufacturing expe-

rience to produce the highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector simultaneously via hot-hole

assisted erase. The data is programmed using hot electron injection.

2

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Table of Contents

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Am29LV160M Device Bus Operations .......................10

Word/Byte Configuration .................................................................. 10

Requirements for Reading Array Data ........................................... 10

Writing Commands/Command Sequences .....................................11

Program and Erase Operation Status ...............................................11

Standby Mode ...........................................................................................11

Automatic Sleep Mode .........................................................................12

RESET#: Hardware Reset Pin .............................................................12

Output Disable Mode ...........................................................................12

Table 2. Sector Address Tables (Am29LV160MT) ...................13

Table 3. Sector Address Tables (Am29LV160MB) ...................14

DQ7: Data# Polling ..............................................................................33

Figure 7. Data# Polling Algorithm....................................... 34

RY/BY#: Ready/Busy# ..........................................................................34

DQ6: Toggle Bit I ..................................................................................35

DQ2: Toggle Bit II .................................................................................35

Reading Toggle Bits DQ6/DQ2 ........................................................36

Figure 8. Toggle Bit Algorithm............................................ 37

DQ5: Exceeded Timing Limits ..........................................................37

DQ3: Sector Erase Timer ...................................................................38

Table 12. Write Operation Status ........................................38

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . .39

Figure 9. Maximum Negative Overshoot Waveform ............... 39

Figure 10. Maximum Positive Overshoot Waveform ............... 39

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 39

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 11. Test Setup........................................................ 41

Table 13. Test Specifications ..............................................41

Figure 12. Input Waveforms and Measurement Levels ........... 41

Autoselect Mode ....................................................................................15

Table 4. Autoselect Codes (High Voltage Method) ..................15

Sector Protection/Unprotection .......................................................15

Temporary Sector Unprotect ............................................................16

Figure 1. Temporary Sector Unprotect Operation................... 16

Figure 2. In-System Single High Voltage Sector Protect/

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .42

Read Operations ...................................................................................42

Figure 13. Read Operations Timings.................................... 42

Hardware Reset (RESET#) .................................................................43

Figure 14. RESET# Timings ............................................... 43

Word/Byte Configuration (BYTE#) ..............................................44

Figure 15. BYTE# Timings for Read Operations..................... 44

Figure 16. BYTE# Timings for Write Operations .................... 44

Erase/Program Operations ................................................................45

Figure 17. Program Operation Timings ................................ 46

Figure 18. Chip/Sector Erase Operation Timings ................... 47

Figure 19. Data# Polling Timings

(During Embedded Algorithms) .......................................... 48

Figure 20. Toggle Bit Timings

Unprotect Algorithms ........................................................ 17

Secured Silicon Sector Flash Memory Region .............................. 18

Table 5. Secured Silicon Sector Addressing ...........................18

Customer Lockable: Secured Silicon Sector NOT Programmed

or Protected At the Factory .............................................................. 18

Figure 3. Secured Silicon Sector Protect Verify...................... 19

Common Flash Memory Interface (CFI) ....................................... 20

Table 6. CFI Query Identification String ...............................20

Table 7. System Interface String .........................................21

Table 8. Device Geometry Definition ....................................21

Table 9. Primary Vendor-Specific Extended Query .................22

(During Embedded Algorithms) .......................................... 48

Figure 21. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations................................................. 49

Figure 22. Temporary Sector Unprotect/Timing Diagram........ 49

Figure 23. Sector Protect/Unprotect Timing Diagram............. 50

Figure 24. Alternate CE# Controlled Write Operation Timings . 52

Hardware Data Protection ................................................................22

Low V_CCWrite Inhibit ........................................................................22

Write Pulse “Glitch” Protection ......................................................22

Logical Inhibit ..........................................................................................23

Power-Up Write Inhibit ......................................................................23

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data ..............................................................................23

Reset Command ....................................................................................23

Autoselect Command Sequence ......................................................24

Word/Byte Program Command Sequence ...................................24

Erase and Programming Performance . . . . . . . . .53

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 53

TSOP Pin and BGA Package Capacitance . . . . . 53

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .54

TS 048—48-Pin Standard TSOP ......................................................54

TSR048—48-Pin Reverse TSOP ......................................................55

FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)

6 x 8 mm Package .................................................................................56

LAA064—64-Ball Fortified Ball Grid Array (BGA)

13 x 11 mm Package ................................................................................57

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58

Unlock Bypass Command Sequence ...............................................25

Figure 4. Program Operation .............................................. 26

Chip Erase Command Sequence ......................................................26

Sector Erase Command Sequence ...................................................27

Erase Suspend/Erase Resume Commands .....................................27

Figure 5. Erase Operation .................................................. 29

Program Suspend/Program Resume Command Sequence .......29

Figure 6. Program Suspend/Program Resume ....................... 30

Command Definitions Tables .............................................................31

Write Operation Status . . . . . . . . . . . . . . . . . . . . 33

January 31, 2007 25974B5

Am29LV160M

3

D a t a S h e e t

Product Selector Guide

Family Part Number

Am29LV160M

85

70R

(Note 2)

Regulated Voltage Range: V_CC= 3.0–3.6 V

Speed Option

Full Voltage Range: V_CC= 2.7–3.6 V

)

(Note 2)

90

35

100

50

Max access time, ns (t_ACC

70

30

85

35

Max CE# access time, ns (t_CE

)

Max OE# access time, ns (t_OE

)

Notes:

1. See “AC Characteristics” on page 42 for full specifications.

2. Contact sales office or representative for availability and ordering information.

Block Diagram

DQ15–DQ0 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A19–A0

4

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Connection Diagrams

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

V_CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

Standard TSOP

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

OE#

V_SS

CE#

A0

1

2

3

4

5

6

7

8

A15

A14

A13

A12

A11

A10

A9

A8

A19

NC

48

A16

BYTE#

V_SS

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

V_CC

Reverse TSOP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

NC

RY/BY#

A18

A17

A7

A6

A5

A4

A3

A2

A1

OE#

V_SS

CE#

A0

January 31, 2007 25974B5

Am29LV160M

5

D a t a S h e e t

Connection Diagrams

Fine-pitch BGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

NC

D4

E4

F4

G4

H4

WE#

RESET#

A19

DQ5

DQ12

V_CC

DQ4

A3

B3

NC

C3

D3

NC

E3

F3

G3

H3

RY/BY#

A18

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

6

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Connection Diagrams

64-Ball Fortified BGA

Top View, Balls Facing Down

A8

NC

B8

NC

C8

NC

D8

NC

E8

F8

G8

NC

H8

NC

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

A12

A14

A15

A16

BYTE# DQ15/A-1

V_SS

A13

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

A10

A11

DQ7

DQ14

DQ13

DQ6

A5

B5

C5

NC

D5

E5

F5

G5

H5

RESET#

A19

DQ5

DQ12

V_CC

DQ4

WE#

A4

B4

NC

C4

D4

NC

E4

F4

G4

H4

RY/BY#

A18

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

V_SS

CE#

OE#

A1

NC

B1

NC

C1

NC

D1

NC

E1

F1

G1

NC

H1

NC

Special Package Handling Instructions

Special handling is required for Flash Memory products in molded packages

(TSOP, BGA, SSOP, PDIP, PLCC). The package and/or data integrity may be

compromised if the package body is exposed to temperatures above 150°C for

prolonged periods of time.

January 31, 2007 25974B5

Am29LV160M

7

D a t a S h e e t

Pin Configuration

A19–A0

DQ14–DQ0

DQ15/A-1

=

20 addresses

15 data inputs/outputs

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

BYTE#

CE#

OE#

=

Selects 8-bit or 16-bit mode

Chip enable

Output enable

Write enable

Hardware reset pin

Ready/Busy output

WE#

RESET#

RY/BY#

V_CC

3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_SS

NC

=

Device ground

Pin not connected internally

Logic Symbol

20

A19–A0

16 or 8

DQ15–DQ0

(A-1)

CE#

OE#

WE#

RESET#

BYTE#

RY/BY#

8

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Ordering Information

Standard Products

Spansion standard products are available in several packages and operating

ranges. The order number (Valid Combination) is formed by a combination of the

elements below.

Am29LV160M

T

100

E

I

TEMPERATURE RANGE

I

= Industrial (–40°C to +85°C)

PACKAGE TYPE

E

F

WA

=

48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)

48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)

48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package (FBA048)

PC

=

64-ball Fortified Ball Grid Array (BGA)

1.0 mm pitch, 13 x 11 mm package (LAA064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29LV160M

16 Megabit (2M x 8-Bit/1M x 16-Bit) MirrorBit^TMFlash Memory

3.0 Volt-only Read, Program, and Erase

Access

Time

(ns)

V_CC

Voltage

Range

Valid Combinations for FBGA Packages

Package

Access

Time Voltage

(ns)

V_CC

Valid Combinations

for TSOP Packages

Order Number

Marking

Range

Am29LV160MT90,

90

L160MT90VI,

L160MB90VI

Am29LV160MB90

WAI

PCI

EI, FI

2.7–3.6 V

Am29LV160MT90,

Am29LV160MB90

90

Am29LV160MT100,

Am29LV160MB100

100

L160MT90PI,

L160MB90PI

2.7–

3.6 V

L160MT10VI,

L160MB10VI

WAI

PCI

Am29LV160MT100,

Am29LV160MB100

100

L160MT10PI,

L160MB10PI

Note: For 70R and 85 speed options shown in product selector

guide, contact a sales office or representative for availability

and ordering information.

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device.

Consult your local sales office to confirm availability of specific valid combinations and to

check on newly released combinations.

January 31, 2007 25974B5

Am29LV160M

9

D a t a S h e e t

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory location. The register is com-

posed of latches that store the commands, along with the address and data

information needed to execute the command. The contents of the register serve

as inputs to the internal state machine. The state machine outputs dictate the

function of the device. Table 1 lists the device bus operations, the inputs and con-

trol levels they require, and the resulting output. The following subsections

describe each of these operations in further detail.

Table 1. Am29LV160M Device Bus Operations

DQ8–DQ15

BYTE#

= V

Addresses

(Note 1)

DQ0– BYTE#

Operation

CE# OE# WE# RESET#

DQ7

D_OUT

D_IN

= V

IH

IL

Read

Write

L

H

L

H

A_IN

D_OUT

D_IN

DQ8–DQ14 = High-Z,

DQ15 = A-1

H

V_CC

0.3 V

±

V_CC±

0.3 V

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V_ID

D_IN

X

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V_ID

D_IN

X

Temporary Sector

Unprotect

X

A_IN

D_IN

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 12.0 ± 0.5 V, X = Don’t Care, A_IN= Address In, D_IN= Data In, D_OUT

= Data Out

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V_IH), A19:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector

Protection/Unprotection” on page 15.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in

the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only

data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/

O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the

LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE# pins

to V_IL. CE# is the power control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should remain at V_IH. The BYTE#

pin determines whether the device outputs array data in words or bytes.

10

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

The internal state machine is set for reading array data upon device power-up,

or after a hardware reset. This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No command is necessary in

this mode to obtain array data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs produce valid data on the

device data outputs. The device remains enabled for read access until the com-

mand register contents are altered.

See “Reading Array Data” on page 23 for more information. Refer to the table

“Read Operations” on page 42 for timing specifications and to Figure 13, on page

42 for the timing diagram. I_CC1in the table “CMOS Compatible” on page 40 rep-

resents the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH

.

For program operations, the BYTE# pin determines whether the device accepts

program data in bytes or words. Refer to “Word/Byte Configuration” on page 10

for more information.

The device features an Unlock Bypass mode to facilitate faster programming.

Once the device enters the Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The “Word/Byte Program

Command Sequence” on page 24 contains details on programming data to the

device using both standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 2, on page 13 and Table 3, on page 14 indicate the address space that each

sector occupies. A “sector address” consists of the address bits required to

uniquely select a sector. The sector “Command Definitions” on page 23 contains

details on erasing a sector or the entire chip, or suspending/resuming the erase

operation.

After the system writes the autoselect command sequence, the device enters the

autoselect mode. The system can then read autoselect codes from the internal

register (which is separate from the memory array) on DQ7–DQ0. Standard read

cycle timings apply in this mode. Refer to the sections “Autoselect Mode” on

page 15 and “Autoselect Command Sequence” on page 24 for more information.

I_CC2in the DC Characteristics table represents the active current specification for

the write mode. The section “AC Characteristics” on page 42 contains timing

specification tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the

operation by reading the status bits on DQ7–DQ0. Standard read cycle timings

and I_CCread specifications apply. Refer to “Write Operation Status” on page 33

for more information, and to “AC Characteristics” on page 42 for timing diagrams.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

January 31, 2007 25974B5

Am29LV160M

11

D a t a S h e e t

The device enters the CMOS standby mode when the CE# and RESET# pins are

both held at V_CC± 0.3 V. (Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within V_CC± 0.3 V, the device

is in the standby mode, but the standby current is greater. The device requires

standard access time (t_CE) for read access when the device is in either of these

standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

In the table “CMOS Compatible” on page 40, I_CC3and I_CC4represents the standby

current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The

device automatically enables this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE#

control signals. Standard address access timings provide new data when

addresses are changed. While in sleep mode, output data is latched and always

available to the system. I_CC4in the table “CMOS Compatible” on page 40

represents the automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the system drives the RESET# pin to V_ILfor at least a period of

t_RP, the device immediately terminates any operation in progress, tristates all

data output pins, and ignores all read/write attempts for the duration of the RE-

SET# pulse. The device also resets the internal state machine to reading array

data. The operation that was interrupted should be reinitiated once the device is

ready to accept another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held

at V_SS±0.3 V, the device draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS±0.3 V, the standby current is greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-

mains a “0” (busy) until the internal reset operation is complete, which requires

a time of t_READY(during Embedded Algorithms). The system can thus monitor

RY/BY# to determine whether the reset operation is complete. If RESET# is as-

serted when a program or erase operation is not executing (RY/BY# pin is “1”),

the reset operation is completed within a time of t_READY(not during Embedded

Algorithms). The system can read data t_RHafter the RESET# pin returns to V_IH

.

Refer to the “AC Characteristics” on page 42 for RESET# parameters and to Fig-

ure 14, on page 43 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is disabled. The output pins

are placed in the high impedance state.

12

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Table 2. Sector Address Tables (Am29LV160MT)

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

Sector A19 A18 A17 A16 A15 A14 A13 A12

Byte Mode (x8)

000000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1F7FFF

1F8000–1F9FFF

1FA000–1FBFFF

1FC000–1FFFFF

Word Mode (x16)

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FBFFF

0FC000–0FCFFF

0FD000–0FDFFF

0FE000–0FFFFF

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

X

0

1

X

64/32

32/16

8/4

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

8/4

16/8

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” on page 10

section.

January 31, 2007 25974B5

Am29LV160M

13

D a t a S h e e t

Table 3. Sector Address Tables (Am29LV160MB)

Sector Size

(Kbytes/

Kwords)

Address Range (in hexadecimal)

Sector A19 A18 A17 A16 A15 A14 A13 A12

Byte Mode (x8)

000000–003FFF

004000–005FFF

006000–007FFF

008000–00FFFF

010000–01FFFF

020000–02FFFF

030000–03FFFF

040000–04FFFF

050000–05FFFF

060000–06FFFF

070000–07FFFF

080000–08FFFF

090000–09FFFF

0A0000–0AFFFF

0B0000–0BFFFF

0C0000–0CFFFF

0D0000–0DFFFF

0E0000–0EFFFF

0F0000–0FFFFF

100000–10FFFF

110000–11FFFF

120000–12FFFF

130000–13FFFF

140000–14FFFF

150000–15FFFF

160000–16FFFF

170000–17FFFF

180000–18FFFF

190000–19FFFF

1A0000–1AFFFF

1B0000–1BFFFF

1C0000–1CFFFF

1D0000–1DFFFF

1E0000–1EFFFF

1F0000–1FFFFF

Word Mode (x16)

000000–001FFF

002000–002FFF

003000–003FFF

004000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

SA0

SA1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

X

16/8

8/4

SA2

8/4

SA3

32/16

64/32

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” on page 10

section.

14

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector

protection verification, through identifier codes output on DQ7–DQ0. This mode

is primarily intended for programming equipment to automatically match a device

to be programmed with its corresponding programming algorithm. However, the

autoselect codes can also be accessed in-system through the command register.

When using programming equipment, the autoselect mode requires V_ID(11.5 V

to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in

Table 4. In addition, when verifying sector protection, the sector address must

appear on the appropriate highest order address bits (see Table 2, on page 13

and Table 3, on page 14). Table 3 shows the remaining address bits that are don’t

care. When all necessary bits are set as required, the programming equipment

may then read the corresponding identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host system can issue the autose-

lect command via the command register, as shown in Table 10, on page 31 and

Table 11, on page 32. This method does not require V_ID. See “Command Defini-

tions” on page 23 for details on using the autoselect mode.

Table 4. Autoselect Codes (High Voltage Method)

A19 A11

to to

CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Mod

e

Description

A6

A1

Manufacturer ID

L

H

X

V_ID

X

L

X

L

X

01h (AMD)

C4h

Device ID:

Am29LV160M

(Top Boot Block)

Word

Byte

Word

22h

X

V_ID

X

L

X

L

H

L

H

X

C4h

49h

Device ID:

Am29LV160M

(Bottom Boot

Block)

22h

X

SA

X

V_ID

X

H

L

Byte

L

H

X

49h

01h

(protected)

X

Sector Protection

Verification

L

H

L

H

L

00h

(unprotected)

83h (factory

locked

03h (not

Secured Silicon Sector

Indicator Bit (DQ7)

L

H

X

factory locked)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

Note: The autoselect codes may also be accessed in-system via command sequences. See Table 10, on page 31 and

Table 11, on page 32.

Sector Protection/Unprotection

The hardware sector protection feature disables both program and erase opera-

tions in any sector. The hardware sector unprotection feature re-enables both

program and erase operations in previously protected sectors.

The device is normally shipped with all sectors unprotected. However, the Ex-

pressFlash™ Service offers the option of programming and protecting sectors at

January 31, 2007 25974B5

Am29LV160M

15

D a t a S h e e t

the factory prior to shipping the device. Contact a sales office or representative

for details.

It is possible to determine whether a sector is protected or unprotected. See “Au-

toselect Mode” on page 15 for details.

Sector protection and unprotection requires V_IDon the RESET# pin only, and can

be implemented either in-system or via programming equipment. Figure 2, on

page 17 shows the algorithms and Figure 23, on page 50 shows the timing dia-

gram. This method uses standard microprocessor bus cycle timing. For sector

unprotect, all unprotected sectors must first be protected prior to the first sector

unprotect write cycle.

Temporary Sector Unprotect

This feature allows temporary unprotection of previously protected sectors to

change data in-system. The Sector Unprotect mode is activated by setting the

RESET# pin to V_ID. During this mode, formerly protected sectors can be pro-

grammed or erased by selecting the sector addresses. Once V_IDis removed from

the RESET# pin, all the previously protected sectors are protected again. Figure

2, on page 17 shows the algorithm, and Figure 22, on page 49 shows the timing

diagrams, for this feature.

START

RESET# = V

(Note 1)

ID

Perform Erase or

Program Operations

RESET# = V

IH

Temporary Sector

Unprotect Completed

(Note 2)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

16

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

START

Protect all sectors:

PLSCNT = 1

RESET# = V_ID

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

RESET# = V_ID

Wait 1 ms

unprotect address

No

First Write

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Cycle = 60h?

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

No

from RESET#

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

In-System Single

High Voltage

from RESET#

In-System Single

High Voltage

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

Algorithm

Sector Unprotect

complete

Figure 2. In-System Single High Voltage Sector Protect/Unprotect Algorithms

January 31, 2007 25974B5 Am29LV160M

17

D a t a S h e e t

Secured Silicon Sector Flash Memory Region

The Secured Silicon Sector feature provides a Flash memory region that enables

permanent part identification through an Electronic Serial Number (ESN). The

Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector

Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is

locked when shipped from the factory. This bit is permanently set at the factory

and cannot be changed, which prevents cloning of a factory locked part. This en-

sures the security of the ESN once the product is shipped to the field.

The device is offered with the Secured Silicon Sector either customer lockable

(standard shipping option) or factory locked (contact a sales office or represen-

tative for ordering information). The customer-lockable version is shipped with

the Secured Silicon Sector unprotected, allowing customers to program the sec-

tor after receiving the device. The customer-lockable version also has the

Secured Silicon Sector Indicator Bit permanently set to a “0.” The factory-locked

version is always protected when shipped from the factory, and has the Secured

Silicon Sector Indicator Bit permanently set to a “1.” Thus, the Secured Silicon

Sector Indicator Bit prevents customer-lockable devices from being used to re-

place devices that are factory locked. Note that the ACC function and unlock

bypass modes are not available when the Secured Silicon Sector is enabled.

The Secured Silicon sector address space in this device is allocated as follows:

Table 5. Secured Silicon Sector Addressing

Secured Silicon Sector Address

Range

Customer

Lockable

ESN Factory

Locked

ExpressFlash

Factory Locked

x16

x8

0F8000h–

0F8007h

1F0000h–

1F000Fh

ESN or determined

by customer

ESN

Determined by

customer

0F8008h–

0F807Fh

1F0010h–

1F00FFh

Determined

by customer

Unavailable

The system accesses the Secured Silicon Sector through a command sequence

(see “Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-

quence”). After the system writes the Enter Secured Silicon Sector command

sequence, it may read the Secured Silicon Sector by using the addresses given

in Table 5. This mode of operation continues until the system issues the Exit Se-

cured Silicon Sector command sequence, or until power is removed from the

device. On power-up, or following a hardware reset, the device reverts to send-

ing commands to sector SA0.

Customer Lockable: Secured Silicon Sector NOT Programmed or

Protected At the Factory

Unless otherwise specified, the device is shipped such that the customer may

program and protect the 256-byte Secured Silicon sector.

The system may program the Secured Silicon Sector using the write-buffer, ac-

celerated and/or unlock bypass methods, in addition to the standard

programming command sequence. See “Command Definitions” on page 23.

Programming and protecting the Secured Silicon Sector must be used with cau-

tion since, once protected, there is no procedure available for unprotecting the

Secured Silicon Sector area and none of the bits in the Secured Silicon Sector

memory space can be modified in any way.

18

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

The Secured Silicon Sector area can be protected using one of the following

procedures:

Write the three-cycle Enter Secured Silicon Sector Region command se-

quence, and then follow the in-system sector protect algorithm as shown in

Figure 2, on page 17, except that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the Secured Silicon Sector without raising any

device pin to a high voltage. Note that this method is only applicable to the

Secured Silicon Sector.

To verify the protect/unprotect status of the Secured Silicon Sector, follow the

algorithm shown in Figure 3.

Once the Secured Silicon Sector is programmed, locked and verified, the system

must write the Exit Secured Silicon Sector Region command sequence to return

to reading and writing within the remainder of the array.

Factory Locked: Secured Silicon Sector Programmed and

Protected At the Factory

In devices with an ESN, the Secured Silicon Sector is protected when the device

is shipped from the factory. The Secured Silicon Sector cannot be modified in any

way. An ESN Factory Locked device has a 16-byte random ESN at addresses

0F8000h–0F8007h. Please contact your local sales office or representative for

details on ordering ESN Factory Locked devices.

Customers may opt to have their code programmed by the manufacturer

through the ExpressFlash service (Express Flash Factory Locked). The devices

are then shipped from the factory with the Secured Silicon Sector permanently

locked. Contact an sales office or representative for details on using the Ex-

pressFlash service.

START

If data = 00h,

RESET# =

SecSi Sector is

unprotected.

V_IHor V_ID

If data = 01h,

SecSi Sector is

protected.

Wait 1 ms

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

A1 = 1, A0 = 0

SecSi Sector

Protect Verify

complete

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Figure 3. Secured Silicon Sector Protect Verify

January 31, 2007 25974B5

Am29LV160M

19

D a t a S h e e t

Common Flash Memory Interface (CFI)

The Common Flash Interface (CFI) specification outlines device and host system

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The system can read CFI information

at the addresses given in Table 6, on page 20 to Table 9, on page 22. In word

mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading

CFI data, the system must write the reset command.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Table 6, on page 20 to Table 9, on page 22.

The system must write the reset command to return the device to the read/reset

mode.

For further information, please refer to the CFI Specification and CFI Publication

100, available online at http://www.amd.com/flash/cfi. Alternatively, contact an

sales office or representative for copies of these documents.

Table 6. CFI Query Identification String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

20

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Table 7. System Interface String

Addresses

(Word Mode)

(Byte Mode)

Data

Description

V_CCMin. (write/erase)

0027h

1Bh

1Ch

36h

38h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

0036h

D7–D4: volt, D3–D0: 100 millivolt

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0007h

0000h

000Ah

0000h

0001h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

Table 8. Device Geometry Definition

Addresses

(Word Mode)

(Byte Mode)

Data

Description

27h

4Eh

0015h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0004h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0000h

0040h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

0001h

0000h

0020h

0000h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

0080h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

001Eh

0000h

0001h

January 31, 2007 25974B5

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21

D a t a S h e e t

Table 9. Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

(Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bit 1–0)

0b = Required, 1b = Not Required

45h

8Ah

0008h

Process Technology (Bits 7–2)

0010b = 0.23 µm MirrorBit

Erase Suspend

46h

47h

48h

8Ch

8Eh

90h

0002h

0001h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

49h

92h

0004h

01 = 29F040 mode, 02 = 29F016 mode,

03 = 29F400 mode, 04 = 29LV800A mode

Simultaneous Operation

00 = Not Supported, 01 = Supported

4Ah

4Bh

4Ch

94h

96h

98h

0000h

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes (refer to Table 10, on page 31

and Table 11, on page 32 for command definitions). In addition, the following

hardware data protection measures prevent accidental erasure or programming,

which might otherwise be caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system noise.

Low V

Write Inhibit

CC

When V_CCis less than V_LKO, the device does not accept any write cycles. This pro-

tects data during V_CCpower-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets. Subsequent

writes are ignored until V_CCis greater than V_LKO. The system must provide the

proper signals to the control pins to prevent unintentional writes when V_CCis

greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write

cycle.

22

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25974B5 January 31, 2007

D a t a S h e e t

Logical Inhibit

Write cycles are inhibited by holding any one of OE# = V_IL, CE# = V_IHor WE# =

_IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a

V

logical one.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up, the device does not accept

commands on the rising edge of WE#. The internal state machine is automatically

reset to reading array data on power-up.

Command Definitions

Writing specific address and data commands or sequences into the command

register initiates device operations. Table 10, on page 31 and Table 11, on

page 32 define the valid register command sequences. Note that writing incorrect

address and data values or writing them in the improper sequence may place the

device in an unknown state. A reset command is then required to set the device

for the next operation.

All addresses are latched on the falling edge of WE# or CE#, whichever happens

later. All data is latched on the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in “AC Characteristics” on page 42.

Reading Array Data

The device is automatically set to reading array data after device power-up. No

commands are required to retrieve data. The device is also ready to read array

data after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the device enters the

Erase Suspend mode. The system can read array data using the standard read

timings, except that if it reads at an address within erase-suspended sectors,

the device outputs status data. After completing a programming operation in

the Erase Suspend mode, the system may once again read array data with the

same exception. See “Erase Suspend/Erase Resume Commands” on page 27

for more information on this mode.

The system must issue the reset command to re-enable the device for reading

array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com-

mand” section, next.

See also “Requirements for Reading Array Data” on page 10 for more informa-

tion. The table “Read Operations” on page 42s provides the read parameters, and

Figure 13, on page 42 shows the timing diagram.

Reset Command

Writing the reset command to the device resets the device to reading array data.

Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase

command sequence before erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the sequence cycles in a program

command sequence before programming begins. This resets the device to read-

ing array data (also applies to programming in Erase Suspend mode). Once

January 31, 2007 25974B5

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23

D a t a S h e e t

programming begins, however, the device ignores reset commands until the op-

eration is complete.

The reset command may be written between the sequence cycles in an autoselect

command sequence. Once in the autoselect mode, the reset command must be

written to return to reading array data (also applies to autoselect during Erase

Suspend).

If DQ5 goes high during a program or erase operation, writing the reset command

returns the device to reading array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-

facturer and devices codes, and determine whether or not a sector is protected.

Table 10, on page 31 and Table 11, on page 32 show the address and data re-

quirements. This method is an alternative to that shown in Table 4, on page 15,

which is intended for PROM programmers and requires V_IDon address bit A9.

The autoselect command sequence is initiated by writing two unlock cycles, fol-

lowed by the autoselect command. The device then enters the autoselect mode,

and the system may read at any address any number of times, without initiating

another command sequence.

A read cycle at address XX00h retrieves the manufacturer code. A read cycle at

address XX01h returns the device code. A read cycle containing a sector address

(SA) and the address XX02h in word mode (or XX04h in byte mode) returns

XX01h if that sector is protected, or 00h if it is unprotected. Refer to Table 2, on

page 13 and Table 3, on page 14 for valid sector addresses.

The system must write the reset command to exit the autoselect mode and return

to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte, depending on the state

of the BYTE# pin. Programming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock write cycles, followed by

the program set-up command. The program address and data are written next,

which in turn initiate the Embedded Program algorithm. The system is not re-

quired to provide further controls or timings. The device automatically

generates the program pulses and verifies the programmed cell margin.

Table 10, on page 31 and Table 11, on page 32 show the address and data re-

quirements for the byte program command sequence. Note that the Secured

Silicon Sector, autoselect, and CFI functions are unavailable when a program

operation is in progress.

When the Embedded Program algorithm is complete, the device then returns to

reading array data and addresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7, DQ6, or RY/BY#. See

“Write Operation Status” on page 33 for information on these status bits.

Any commands written to the device during the Embedded Program Algorithm

are ignored. Note that a hardware reset immediately terminates the program-

ming operation. The Byte Program command sequence should be reinitiated once

the device resets to reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector boundaries. A bit

cannot be programmed from a “0” back to a “1”. Attempting to do so may

halt the operation and set DQ5 to “1,” or cause the Data# Polling algorithm to

24

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

indicate the operation was successful. However, a succeeding read shows that the

data is still “0”. Only erase operations can convert a “0” to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to the

device faster than using the standard program command sequence. The unlock

bypass command sequence is initiated by first writing two unlock cycles. This is

followed by a third write cycle containing the unlock bypass command, 20h. The

device then enters the unlock bypass mode. A two-cycle unlock bypass program

command sequence is all that is required to program in this mode. The first cycle

in this sequence contains the unlock bypass program command, A0h; the second

cycle contains the program address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial two unlock cycles required

in the standard program command sequence, resulting in faster total program-

ming time. Table 10, on page 31 and Table 11, on page 32 show the

requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-

pass Reset commands are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset command sequence. The first cycle

must contain the data 90h; the second cycle the data 00h. Addresses are don’t

care for both cycles. The device then returns to reading array data.

Figure 4, on page 26 illustrates the algorithm for the program operation. See the

table “Erase/Program Operations” on page 45 for parameters, and Figure 17, on

page 46 for timing diagrams.

January 31, 2007 25974B5

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D a t a S h e e t

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

Programming

Completed

Notes: See Tables 10 and 11 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system to preprogram prior to erase. The Embedded Erase algorithm auto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these operations. Table 10, on page 31 and Table 11, on page 32

show the address and data requirements for the chip erase command sequence.

Note that the Secured Silicon Sector, autoselect, and CFI functions are unavail-

able when an erase operation is in progress.

Any commands written to the chip during the Embedded Erase algorithm are ig-

nored. Note that a hardware reset during the chip erase operation immediately

terminates the operation. The Chip Erase command sequence should be reiniti-

ated once the device returns to reading array data, to ensure data integrity.

The system can determine the status of the erase operation by using DQ7, DQ6,

DQ2, or RY/BY#. See “Autoselect Command Sequence” on page 24 for informa-

tion on these status bits. When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are no longer latched.

26

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Figure 5, on page 29 illustrates the algorithm for the erase operation. See the

table “Erase/Program Operations” on page 45 for parameters, and Figure 18, on

page 47 for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock write cycles are then followed by the address of the sector to be

erased, and the sector erase command. Table 10, on page 31 and Table 11, on

page 32 show the address and data requirements for the sector erase command

sequence. Note that the Secured Silicon Sector, autoselect, and CFI functions

are unavailable when an erase operation is in progress.

The device does not require the system to preprogram the memory prior to erase.

The Embedded Erase algorithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-out of 50 µs begins.

During the time-out period, additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector to all sectors. The

time between these additional cycles must be less than 50 µs, otherwise the last

address and command might not be accepted, and erasure may begin. It is rec-

ommended that processor interrupts be disabled during this time to ensure all

commands are accepted. The interrupts can be re-enabled after the last Sector

Erase command is written. If the time between additional sector erase commands

can be assumed to be less than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase Suspend during the time-out

period resets the device to reading array data. The system must rewrite the

command sequence and any additional sector addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer timed out.

(See “DQ3: Sector Erase Timer” on page 38.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Once the sector erase operation starts, only the Erase Suspend command is valid.

All other commands are ignored. Note that a hardware reset during the sector

erase operation immediately terminates the operation. The Sector Erase com-

mand sequence should be reinitiated once the device returns to reading array

data, to ensure data integrity.

When the Embedded Erase algorithm is complete, the device returns to reading

array data and addresses are no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to

“Write Operation Status” on page 33 for information on these status bits.)

Figure 5, on page 29 illustrates the algorithm for the erase operation. Refer to the

table “Erase/Program Operations” on page 45 for parameters, and Figure 18, on

page 47 for timing diagrams.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to interrupt a sector erase oper-

ation and then read data from, or program data to, any sector not selected for

erasure. This command is valid only during the sector erase operation, including

the 50 µs time-out period during the sector erase command sequence. The Erase

January 31, 2007 25974B5

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D a t a S h e e t

Suspend command is ignored if written during the chip erase operation or Em-

bedded Program algorithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the time-out period and suspends

the erase operation. Addresses are “don’t-cares” when writing the Erase Suspend

command.

When the Erase Suspend command is written during a sector erase operation, the

device requires a maximum of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during the sector erase time-out,

the device immediately terminates the time-out period and suspends the erase

operation.

After the erase operation is suspended, the system can read array data from or

program data to any sector not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Normal read and write timings and

command definitions apply. Reading at any address within erase-suspended sec-

tors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and

DQ2 together, to determine if a sector is actively erasing or is erase-suspended.

See “Write Operation Status” on page 33 for information on these status bits.

After an erase-suspended program operation is complete, the system can once

again read array data within non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or DQ6 status bits, just as in

the standard program operation. See “Write Operation Status” on page 33 for

more information.

The system may also write the autoselect command sequence when the device

is in the Erase Suspend mode. The device allows reading autoselect codes even

at addresses within erasing sectors, since the codes are not stored in the memory

array. When the device exits the autoselect mode, the device reverts to the Erase

Suspend mode, and is ready for another valid operation. See “Autoselect Com-

mand Sequence” on page 24 for more information.

The system must write the Erase Resume command (address bits are “don’t

care”) to exit the erase suspend mode and continue the sector erase operation.

Further writes of the Resume command are ignored. Another Erase Suspend

command can be written after the device resumes erasing.

Note: During an erase operation, this flash device performs multiple internal op-

erations which are invisible to the system. When an erase operation is

suspended, any of the internal operations that were not fully completed must be

restarted. As such, if this flash device is continually issued suspend/resume com-

mands in rapid succession, erase progress is impeded as a function of the number

of suspends. The result is a longer cumulative erase time than without suspends.

Note that the additional suspends do not affect device reliability or future perfor-

mance. In most systems rapid erase/suspend activity occurs only briefly. In such

cases, erase performance is not significantly impacted.

28

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

START

Write Erase

Command Sequence

Data Poll

from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 10, on page 31 and Table 11, on page 32 for erase command sequence.

2. See “DQ3: Sector Erase Timer” on page 38 for more information.

Figure 5. Erase Operation

Program Suspend/Program Resume Command Sequence

The Program Suspend command allows the system to interrupt a programming

operation so that data can be read from any non-suspended sector. When the

Program Suspend command is written during a programming process, the de-

vice halts the program operation within 15 μs maximum (5 μs typical) and

updates the status bits. Addresses are not required when writing the Program

Suspend command.

After the programming operation is suspended, the system can read array data

from any non-suspended sector. The Program Suspend command may also be

issued during a programming operation while an erase is suspended. In this

case, data may be read from any addresses not in Erase Suspend or Program

Suspend. If a read is needed from the Secured Silicon Sector area (One-time

Program area), then user must use the proper command sequences to enter and

exit this region.

The system may also write the autoselect command sequence when the device

is in the Program Suspend mode. The system can read as many autoselect

codes as required. When the device exits the autoselect mode, the device re-

verts to the Program Suspend mode, and is ready for another valid operation.

See Autoselect Command Sequence for more information.

After the Program Resume command is written, the device reverts to program-

ming. The system can determine the status of the program operation using the

January 31, 2007 25974B5

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D a t a S h e e t

DQ7 or DQ6 status bits, just as in the standard program operation. See “Write

Operation Status” on page 33 for more information.

The system must write the Program Resume command (address bits are don’t

care) to exit the Program Suspend mode and continue the programming opera-

tion. Further writes of the Resume command are ignored. Another Program

Suspend command can be written after the device resumes programming.

Program Operation

Sequence in Progress

Write Program Suspend

Write address/data

XXXh/B0h

Command Sequence

Command is also valid for

Erase-suspended-program

operations

Wait 15 ms

Autoselect and SecSi Sector

Read data as

required

read operations are also allowed

Data cannot be read from erase- or

program-suspended sectors

Done

No

reading?

Yes

Write Program Resume

Command Sequence

Write address/data

XXXh/30h

Device reverts to

operation prior to

Program Suspend

Figure 6. Program Suspend/Program Resume

30

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25974B5 January 31, 2007

D a t a S h e e t

Command Definitions Tables

Table 10. Command Definitions (x16 Mode, BYTE# = V

)

IH

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

Manufacturer ID

1

4

6

RA

RD

F0

XXX

555

AA

2AA

55

555

90

X00

X01

0001

Device ID, Top Boot (Note 8)

22C4

2249

Device ID, Bottom Boot (Note 8)

Secured Silicon Sector Factory

Protect

4

555

AA

2AA

55

555

90

X03

83/03

00/01

(Note 15)

Sector Group Protect Verify

(Note 9)

4

555

AA

2AA

55

555

90

(SA)X02

Enter Secured Silicon Sector Region

Exit Secured Silicon Sector Region

Program

3

4

3

2

6

1

555

XXX

555

XXX

55

AA

A0

90

AA

B0

30

98

2AA

PA

55

PD

00

55

555

88

90

A0

20

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

Chip Erase

XXX

2AA

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Program/Erase Suspend (Note 12)

Program/Erase Resume (Note 13)

CFI Query (Note 14)

Legend:

X = Don’t care

RA = Read Address of memory location to be read.

RD = Read Data read from location RA during read operation.

PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later.

PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A19–A15 uniquely select any sector.

Notes:

1. See Table 1, on page 10 for description of bus operations.

9. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

2. All values are in hexadecimal.

10. Unlock Bypass command is required prior to Unlock

Bypass Program command.

3. Shaded cells indicate read cycles. All others are write

cycles.

11. Unlock Bypass Reset command is required to return to

read mode when device is in unlock bypass mode.

4. During unlock and command cycles, when lower address

bits are 555 or 2AA as shown in table, address bits above

A11 and data bits above DQ7 are don’t care.

12. System may read and program in non-erasing sectors, or

enter autoselect mode, when in Erase Suspend mode.

Erase Suspend command is valid only during a sector

erase operation.

5. No unlock or command cycles required when device is in

read mode.

6. Reset command is required to return to read mode (or to

erase-suspend-read mode if previously in Erase Suspend)

when device is in autoselect mode, or if DQ5 goes high

while device is providing status information.

13. Erase Resume command is valid only during Erase

Suspend mode.

14. Command is valid when device is ready to read array data

or when device is in autoselect mode.

7. Fourth cycle of the autoselect command sequence is a

read cycle. Data bits DQ15–DQ8 are don’t care. See

“Autoselect Command Sequence” on page 24 for more

information.

15. Data is 83h for factory locked and 03h for not factory

locked.

8. Device ID must be read in three cycles.

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Table 11. Command Definitions (x8 Mode, BYTE# = V )

IL

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data

Addr

Data

Addr

Data

Addr

Data

Addr Data Addr Data

Read (Note 5)

Reset (Note 6)

Manufacturer ID

1

4

6

RA

RD

F0

XXX

AAA

AA

555

55

AAA

90

X00

X02

01

C4

Device ID, Top Boot (Note 8)

Device ID, Bottom Boot (Note

8)

6

4

AAA

AA

555

55

AAA

90

X02

49

Secured Silicon Sector Factory

Protect

(Note 15)

X06

83/03

00/01

Sector Group Protect Verify

(Note 9)

(SA)X04

Enter Secured Silicon Sector Region

Exit Secured Silicon Sector Region

Program

3

4

3

2

6

1

AAA

XXX

AAA

XXX

AA

A0

90

AA

B0

30

98

555

PA

55

PD

00

55

AAA

88

90

A0

20

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

Chip Erase

XXX

555

AAA

80

AAA

AA

555

55

AAA

SA

10

30

Sector Erase

Program/Erase Suspend (Note 12)

Program/Erase Resume (Note 13)

CFI Query (Note 14)

Legend:

X = Don’t care

RA = Read Address of memory location to be read.

RD = Read Data read from location RA during read operation.

PA = Program Address. Addresses latch on falling edge of WE# or CE# pulse, whichever happens later.

PD = Program Data for location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first.

SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A19–A15 uniquely select any sector.

Notes:

1. See Table 1, on page 10 for description of bus operations.

9. Data is 00h for an unprotected sector group and 01h for a

protected sector group.

2. All values are in hexadecimal.

10. Unlock Bypass command is required prior to Unlock

Bypass Program command.

3. Shaded cells indicate read cycles. All others are write

cycles.

11. Unlock Bypass Reset command is required to return to

read mode when device is in unlock bypass mode.

4. During unlock and command cycles, when lower address

bits are 555 or AAA as shown in table, address bits above

A11 are don’t care.

12. System may read and program in non-erasing sectors, or

enter autoselect mode, when in Erase Suspend mode.

Erase Suspend command is valid only during a sector

erase operation.

5. No unlock or command cycles required when device is in

read mode.

6. Reset command is required to return to read mode (or to

erase-suspend-read mode if previously in Erase Suspend)

when device is in autoselect mode, or if DQ5 goes high

while device is providing status information.

13. Erase Resume command is valid only during Erase

Suspend mode.

14. Command is valid when device is ready to read array data

or when device is in autoselect mode.

7. Fourth cycle of autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. See

“Autoselect Command Sequence” on page 24 for more

information.

15. Data is 83h for factory locked and 03h for not factory

locked.

8. Device ID must be read in three cycles.

32

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25974B5 January 31, 2007

D a t a S h e e t

Write Operation Status

The device provides several bits to determine the status of a write operation:

DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 12, on page 38 and the following

subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each

offer a method for determining whether a program or erase operation is complete

or in progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded

Algorithm is in progress or completed, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final WE# pulse in the program

or erase command sequence.

During the Embedded Program algorithm, the device outputs on DQ7 the com-

plement of the datum programmed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to DQ7. The system must

provide the program address to read valid status information on DQ7. If a pro-

gram address falls within a protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading array data.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the device enters the

Erase Suspend mode, Data# Polling produces a “1” on DQ7. This is analogous to

the complement/true datum output described for the Embedded Program algo-

rithm: the erase function changes all the bits in a sector to “1”; prior to this, the

device outputs the “complement,” or “0.” The system must provide an address

within any of the sectors selected for erasure to read valid status information on

DQ7.

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the

device returns to reading array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the system detects DQ7 changes from the complement to true data, it can

read valid data at DQ7–DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is as-

serted low. Figure 19, on page 48, Data# Polling Timings

(During Embedded Algorithms), illustrates this.

Table 12, on page 38 shows the outputs for Data# Polling on DQ7. Figure 7, on

page 34 shows the Data# Polling algorithm.

January 31, 2007 25974B5

Am29LV160M

33

D a t a S h e e t

START

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector erase operation, a valid

address is an address within any sector selected for erasure. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simulta-

neously with DQ5.

Figure 7. Data# Polling Algorithm

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that indicates whether an Em-

bedded Algorithm is in progress or complete. The RY/BY# status is valid after the

rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an

open-drain output, several RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

34

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

If the output is low (Busy), the device is actively erasing or programming. (This

includes programming in the Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during the Erase Suspend

mode), or is in the standby mode.

Table 12, on page 38 shows the outputs for RY/BY#. Figure 13, on page 42, Fig-

ure 14, on page 43, Figure 17, on page 46 and Figure 18, on page 47 show RY/

BY# for read, reset, program, and erase operations, respectively.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is valid after the rising edge

of the final WE# pulse in the command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. (The system may use either OE# or CE#

to control the read cycles.) When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the selected sectors that are

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac-

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 µs after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

Table 12, on page 38 shows the outputs for Toggle Bit I on DQ6. Figure 8, on page

37 shows the toggle bit algorithm in flowchart form, and the section “Reading

Toggle Bits DQ6/DQ2” on page 36 explains the algorithm. Figure 20, on page 48

in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure

21, on page 49 shows the differences between DQ2 and DQ6 in graphical form.

See also the subsection on “DQ2: Toggle Bit II”.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular

sector is actively erasing (that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit II is valid after the rising

edge of the final WE# pulse in the command sequence.

DQ2 toggles when the system reads at addresses within those sectors that were

selected for erasure. (The system may use either OE# or CE# to control the read

cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is

erase-suspended. DQ6, by comparison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected

January 31, 2007 25974B5

Am29LV160M

35

D a t a S h e e t

for erasure. Thus, both status bits are required for sector and mode information.

Refer to Table 12, on page 38 to compare outputs for DQ2 and DQ6.

Figure 8, on page 37 shows the toggle bit algorithm in flowchart form, and the

section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. See also the

“DQ6: Toggle Bit I” on page 35 subsection.Figure 20, on page 48 shows the tog-

gle bit timing diagram. Figure 21, on page 49 shows the differences between DQ2

and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 8, on page 37 for the following discussion. Whenever the system

initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice

in a row to determine whether a toggle bit is toggling. Typically, the system

would note and store the value of the toggle bit after the first read. After the

second read, the system would compare the new value of the toggle bit with

the first. If the toggle bit is not toggling, the device completed the program or

erase operation. The system can read array data on DQ7–DQ0 on the following

read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer toggling, the device success-

fully completed the program or erase operation. If it is still toggling, the device

did not complete the operation successfully, and the system must write the reset

command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 did not go high. The system may continue to monitor the tog-

gle bit and DQ5 through successive read cycles, determining the status as

described in the previous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the operation (top of Figure

8, on page 37).

36

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

START

Read DQ7–DQ0

(Note 1)

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

Yes

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

(Notes

1, 2)

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Figure 8. Toggle Bit Algorithm

Notes:

1. Read toggle bit twice to determine whether or not it is toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time exceeded a specified internal

pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was not successfully

completed.

The DQ5 failure condition may appear if the system tries to program a “1” to a

location that is previously programmed to “0.” Only an erase operation can

January 31, 2007 25974B5

Am29LV160M

37

D a t a S h e e t

change a “0” back to a “1.” Under this condition, the device halts the opera-

tion, and when the operation exceeds the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue the reset command to return

the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-

termine whether or not an erase operation starts. (The sector erase timer does

not apply to the chip erase command.) If additional sectors are selected for era-

sure, the entire time-out also applies after each additional sector erase command.

When the time-out is complete, DQ3 switches from “0” to “1.” The system may

ignore DQ3 if the system can guarantee that the time between additional sec-

tor erase commands is always less than 50 μs. See also the “Sector Erase

Command Sequence” on page 27.

After the sector erase command sequence is written, the system should read the

status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device accepted

the command sequence, and then read DQ3. If DQ3 is “1”, the internally con-

trolled erase cycle started; all further commands (other than Erase Suspend) are

ignored until the erase operation is complete. If DQ3 is “0”, the device accepts

additional sector erase commands. To ensure the command is accepted, the sys-

tem software should check the status of DQ3 prior to and following each

subsequent sector erase command. If DQ3 is high on the second status check,

the last command might not have been accepted. Table 12 shows the outputs for

DQ3.

Table 12. Write Operation Status

DQ7

(Note

2)

DQ5

(Note 1)

DQ2

(Note 2)

Operation

DQ6

DQ3

N/A

1

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Program-

Suspend Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Invalid (not allowed)

Data

1

Program

Suspend

Mode

Suspended Sector

Non-Program

Suspended Sector

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

Erase

Suspend Reading within Non-Erase Suspended

Data

0

Data

N/A

Data

N/A

1

0

Mode

Sector

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits.

See “DQ5: Exceeded Timing Limits” on page 37 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

38

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Absolute Maximum Ratings

Storage Temperature, Plastic Packages. . . . . . . . . . . . . . . . .–65°C to +150°C

Ambient Temperature with Power Applied . . . . . . . . . . . . . . .–65°C to +125°C

Voltage with Respect to Ground

V_CC(Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

All other pins (Note 1). . . . . . . . . . . . . . . . . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,

input or I/O pins may overshoot V to –2.0 V for periods of up to 20 ns. See Figure

SS

9. Maximum DC voltage on input or I/O pins is V_CC+0.5 V. During voltage

transitions, input or I/O pins may overshoot to V +2.0 V for periods up to 20 ns.

CC

See Figure 10.

2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage

transitions, A9, OE#, and RESET# may overshoot V to –2.0 V for periods of up

SS

to 20 ns. See Figure 9. Maximum DC input voltage on pin A9 is +12.5 V which

may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short

circuit should not be greater than one second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those indicated in the operational sections of

this data sheet is not implied. Exposure of the device to absolute maximum rating con-

ditions for extended periods may affect device reliability.

20 ns

V

+0.8 V

CC

+2.0 V

V

–0.5 V

–2.0 V

CC

+0.5 V

2.0 V

20 ns

Figure 9. Maximum Negative

Overshoot Waveform

Figure 10. Maximum Positive

Overshoot Waveform

Operating Ranges

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

_CCSupply Voltages

V_CCfor regulated voltage range . . . . . . . . . . . . . . . . . . . . . . .3.0 V to 3.6 V

_CCfor full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

V

Operating ranges define those limits between which the functionality of the device is

guaranteed.

January 31, 2007 25974B5

Am29LV160M

39

D a t a S h e e t

DC Characteristics

CMOS Compatible

Parameter

Description

Test Conditions

Min

Typ

Max

1.0

Unit

V_IN= V_SSto V_CC

,

I_LI

Input Load Current

±

µA

V_CC= V_{CC max}

I_LIT

A9 Input Load Current

Reset Leakage Current

V_CC= V_{CC max}; A9 = 12.5 V

35

µA

I

V

= V

; RESET# = 12.5 V

LR

CC

CC max

V_OUT= V_SSto V_CC

V_CC= V_{CC max}

,

I_LO

Output Leakage Current

±1.0

µA

5 MHz

1 MHz

5 MHz

1 MHz

15

2

30

10

30

10

CE# = V_IL,OE# ₌V_IH,

Byte Mode

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

15

2

CE# = V_IL,OE# ₌V_IH,

Word Mode

V_CCActive Write Current

(Notes 2, 3, 5)

I_CC2

I_CC3

I_CC4

CE# = V_IL,OE# = V_IH

40

0.4

0.8

60

5

mA

µA

V_CCStandby Current (Notes 2, 4) CE#, RESET# = V_CC

±0.3 V

V_CCStandby Current During Reset

(Notes 2, 4)

RESET# = V_SS

±

0.3 V

5

Automatic Sleep Mode

(Notes 2, 4, 6)

V_IH= V_CC

V_IL= V_SS

±

0.3 V;

I_CC5

0.4

5

µA

±

0.3 V

V_IL1

V_IH1

V_IL2

V_IH2

Input Low Voltage 1(6, 7)

Input High Voltage 1 (6, 7)

Input Low Voltage 2 (6, 8)

Input High Voltage 2 (6, 8)

–0.5

1.9

0.8

V

V_CC+ 0.5

0.3 x V_IO

V_IO+ 0.5

–0.5

1.9

Voltage for Autoselect and

Temporary Sector Unprotect

V_ID

V_CC= 3.3 V

11.5

12.5

0.45

V

V_OL

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

_OH= -2.0 mA, V_CC= V_{CC min}

I_OH= -100 µA, V_CC= V_{CC min}

V

V_OH1

V_OH2

V_LKO

I

0.85 x V_CC

V_CC–0.4

2.3

Output High Voltage

Low V_CCLock-Out Voltage (Note 4)

2.5

V

Notes:

1. The I current listed is typically less than 2 mA/MHz, with OE# at V . Typical V is 3.0 V.

CC

IH

CC

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns.

6. Not 100% tested.

7. V_CCvoltage requirements.

8. V_IOvoltage requirements.

40

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Test Conditions

Table 13. Test Specifications

3.3 V

70R,

Test Condition

85

90, 100 Unit

2.7 kΩ

Output Load

1 TTL gate

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

C

6.2 k

Ω

L

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

V

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 11. Test Setup

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

Input

Measurement Level

Output

0.0 V

Figure 12. Input Waveforms and Measurement Levels

January 31, 2007 25974B5

Am29LV160M

41

D a t a S h e e t

AC Characteristics

Read Operations

Parameter

Speed Options

JEDEC

Std

Description

Test Setup

70R

85

90

100 Unit

t_AVAV

t_RC

Read Cycle Time (Note 1)

Min

70

85

90

100

ns

CE# = V_IL

OE# = V_IL

t_AVQV

t_ACC

Address to Output Delay

Max

70

85

90

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

OE# = V_IL

Max

Min

70

30

25

85

35

30

90

35

30

100

50

ns

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

30

Read

0

Output Enable

Hold Time (Note 1)

t_OEH

Toggle and

Data# Polling

Min

10

ns

Output Hold Time From Addresses, CE#

or OE#, Whichever Occurs First (Note 1)

t_AXQX

t_OH

0

Notes:

1. Not 100% tested.

2. See Figure 11, on page 41 and Table 13, on page 42 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operations Timings

42

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

AC Characteristics

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

Max

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read or Write (See Note)

t_READY

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

t_READY

Max

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

RESET# High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. RESET# Timings

January 31, 2007 25974B5

Am29LV160M

43

D a t a S h e e t

AC Characteristics

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std

Description

70R

85

90

100

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

ELFL/ ELFH

FLQZ

25

70

30

85

30

90

30

ns

100

ns

FHQV

CE#

OE#

BYTE#

DQ0–DQ14

DQ15/A-1

t

ELFL

Data Output

(DQ0–DQ7)

BYTE#

(DQ0–DQ14)

Switching

from word

to byte

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

DQ0–DQ14

DQ15/A-1

(DQ0–DQ14)

mode

Address

Input

DQ15

Output

t

FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

(t

SET

AS

)

t

(t

)

HOLD AH

Figure 16. BYTE# Timings for Write Operations

Note: Refer to the table “Erase/Program Operations” on page 45 for t_ASand t_AHspecifications.

44

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

AC Characteristics

Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

70R

85

90

100

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

85

90

100

t_AVWL

t_WLAX

t_DVWH

t_WHDX

0

ns

t_AH

45

35

45

50

ns

t_DS

t_DH

t_OES

ns

Data Hold Time

0

ns

Output Enable Setup Time

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHWL

t_CS

t_CH

CE# Setup Time

CE# Hold Time

Min

Typ

Min

Max

0

ns

t_WP

Write Pulse Width

Write Pulse Width High

35

50

t_WPH

30

12

Byte

t_WHWH1

t_WHWH2

t_WHWH1

Programming Operation (Note 2)

µs

Word

t_WHWH2Sector Erase Operation (Note 2)

0.7

50

0

sec

µs

ns

µs

t_VCS

t_RB

t_BUSY

t_POLL

V_CCSetup Time (Note 1)

Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

90

4

Program Valid Before Status Polling (Note 3)

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” on page 59 section for more information.

3. When using the program suspend/resume feature, if the suspend command is issued within t_POLL, t_POLLmust

be fully re-applied upon resuming the programming operation. If the suspend command is issued after t_POLL

_POLLis not required again prior to reading the status bits upon resuming.

,

t

January 31, 2007 25974B5

Am29LV160M

45

D a t a S h e e t

AC Characteristics

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_POLL

t_WP

WE#

t_WPH

t_WHWH1

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

Data

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

46

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

AC Characteristics

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

t_VCS

V_CC

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

January 31, 2007 25974B5

Am29LV160M

47

D a t a S h e e t

AC Characteristics

t_RC

VA

Addresses

VA

t_POLL

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ15 and DQ7

Valid Data

Complement

Status Data

True

DQ14–DQ8, DQ6–DQ0

Status Data

True

Valid Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array

data read cycle.

Figure 19. Data# Polling Timings

(During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last

status read cycle, and array data read cycle.

Figure 20. Toggle Bit Timings

(During Embedded Algorithms)

48

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

AC Characteristics

Enter

Erase

Suspend

Enter Erase

Suspend Program

Embedded

Erase

Resume

Erasing

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6 for Erase and

Erase Suspend Operations

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Note: Not 100% tested.

12 V

RESET#

0 or 3 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 22. Temporary Sector Unprotect/Timing Diagram

January 31, 2007 25974B5

Am29LV160M

49

D a t a S h e e t

AC Characteristics

V

ID

V

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

Data

60h

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect Timing Diagram

50

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

AC Characteristics

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

t_AVEL

Std

t_WC

t_AS

Description

70R

85

90

100

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

70

85

90

100

0

ns

t_ELAX

t_AH

45

35

45

50

ns

t_DVEH

t_EHDX

t_DS

t_DH

t_OES

ns

Data Hold Time

0

ns

Output Enable Setup Time

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

35

50

t_CPH

30

12

Byte

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

Programming Operation (Note 2)

Sector Erase Operation (Note 2)

µs

Word

12

0.7

sec

Notes:

1. Not 100% tested.

2. See “Erase and Programming Performance” on page 59 for more information.

January 31, 2007 25974B5

Am29LV160M

51

D a t a S h e e t

AC Characteristics

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_AS

t_AH

t_WH

WE#

OE#

t_POLL

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#,

DQ15

D_OUT

Data

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, D_OUT= data written to

the device.

2. Figure indicates the last two bus cycles of the command sequence.

3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

52

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Erase and Programming Performance

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

Chip Erase Time

0.7

32

18

36

19

15

Excludes 00h programming prior to

erasure (Note 4)

sec

Byte Programming Time

Word Programming Time

300

100

66

µs

Excludes system level overhead

(Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 3)

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, V_CC= 3.0V, 100,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 10, on page 31 and Table 11, on page 32 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

Latchup Characteristics

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

SS

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V on all I/O pins

–1.0 V

V

+ 1.0 V

CC

SS

V

Current

–100 mA

+100 mA

CC

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP Pin and BGA Package Capacitance

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5.0

12

Unit

pF

TSOP

C

Input Capacitance

V

= 0

IN

Fine-pitch BGA

TSOP

4.2

8.5

5.4

7.5

3.9

pF

C

Output Capacitance

V

OUT

Fine-pitch BGA

TSOP

6.5

9

pF

C

Control Pin Capacitance

V

IN

IN2

Fine-pitch BGA

4.7

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

Data Retention

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

January 31, 2007 25974B5

Am29LV160M

53

D a t a S h e e t

Physical Dimensions

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

Note: BSC is an ANSI standard for Basic Space Centering.

54

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Physical Dimensions

TSR048—48-Pin Reverse TSOP

Dwg rev AA; 10/99

Note: BSC is an ANSI standard for Basic Space Centering.

January 31, 2007 25974B5

Am29LV160M

55

D a t a S h e e t

Physical Dimensions

FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA)

6 x 8 mm Package

Dwg rev AF; 10/99

Note: BSC is an ANSI standard for Basic Space Centering.

56

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Physical Dimensions

LAA064—64-Ball Fortified Ball Grid Array (BGA)

13 x 11 mm Package

Note: BSC is an ANSI standard for Basic Space Centering.

January 31, 2007 25974B5

Am29LV160M

57

D a t a S h e e t

Revision Summary

Revision A (June 24, 2002)

Initial release.

Revision A+1 (July 3, 2002)

Added LAA064 package.

Corrected power consumption currents.

Changed DC Characteristics Zero Power Flash tables to TBD.

Corrected minimum erase and program cycle endurance.

Revision A+2 (December 6, 2002)

Global

Removed 44-pin SO package. Deleted dashes from ordering part numbers.

Distinctive Characteristics

Added information for Secured Silicon sector, Program Suspend & Resume. Cor-

rected erase endurance to 100K cycles. Changed section flow to match other

MirrorBit data sheets.

General Description

Changed section flow to match other MirrorBit data sheets.

Connection Diagrams

Corrected Fortified BGA diagram: balls C5, D8, D4, and F1 are now NC.

Ordering Information and Operating Ranges

Removed Commercial and Extended temperature ranges. Corrected Fine-pitch

BGA type to 6 x 8 mm package, FBA048.

Added package markings for the LAA064.

Secured Silicon Sector Flash Memory Region

Added section.

Program Suspend/Program Resume Command Sequence

Added text and flowchart.

Sector Protection/Unprotection

Deleted reference to alternate, high-voltage method of sector protection.

Command Definitions

Modified introductory paragraph to indicate device behavior when presented with

incorrect commands and data. Added mode restrictions to first paragraphs of pro-

gram, sector erase and chip erase subsections.

Command Definitions tables

Replaced previous table with two tables. Byte mode and word mode are now

shown separately. Added Secured Silicon Sector Factory Protect command

sequence.

Table 10. Write Operation Status

Added Program Suspend Mode rows to table.

BGA and TSOP Capacitance

Added fine-pitch BGA capacitance to table.

AC Characteristics tables

Typical sector erase time is now 0.4 s in all tables.

58

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Physical Dimensions

Corrected Fortified BGA drawing to FBA048.

Revision A+3 (January 6, 2003)

Global

Deleted references to WP# and ACC. The Am29LV160M does not offer those

features.

Command Definitions table

Deleted references to write buffers. This device does not offer that feature.

AC Characteristics

Erase and Program Operations table; Alternate CE# Controlled Erase/Operations

table: Changed t_WHWH1to TBD.

Revision A+4 (June 16, 2003)

Global

Changed status from Advance Information to Preliminary.

Modified speed options available.

Product Selector Guide

Added Note #2.

Ordering Information

Corrected OPN tables and added Note.

Secured Silicon Sector Flash Memory Region

Replaced text in this section.

Command Definitions

Modified Legend.

Erase/Program Operations and Alternate CE# Controlled Erase/

Program Operations

Inserted values for all TBD.

Erase and Programming Performance

Inserted values for all TBD.

Revision B (August 11, 2003)

Global

Modified speed options available. Converted document formatting to Spansion

template. Changed data sheet status from Advance Information to Preliminary.

Revision B+1 (February 27, 2004)

Autoselect Mode, Table 4

Added Secured Silicon Sector Indicator Bit (DQ7).

Secured Silicon Sector Flash Memory Region, Table 5

Corrected Secured Silicon Sector Address Ranges.

Factory Locked: Secured Silicon Sector Programmed and Protected At the Fac-

tory: Corrected addresses associated with 16-byte random ESN.

Command Definitions Tables

Tables 10 and 11: Corrected Fourth Address of Secured Silicon Sector Factory

Protect.

January 31, 2007 25974B5

Am29LV160M

59

D a t a S h e e t

AC Characteristics

Added t_POLL

.

Revision B+2 (September 24, 2004)

Erase and Programming Performance

Corrected chip erase, byte/word programming, and chip programming

specifications.

Command Definitions, Table 10

Corrected command definitions for Secured Silicon Sector Factory Protect and

Program

Command Definitions, Table 11

Corrected command definitions for Secured Silicon Sector Factory Protect.

Cover sheet and Title page

Added notation referencing superseding documentation.

Revision B+3 (November 11, 2004)

Global

Added cross-reference links.

Secured Silicon Sector Addressing Table

Updated the x8 address ranges.

Revision B+4 (January 10, 2006)

This product has been retired and is not available for designs. For new and cur-

rent designs, S29GL016A supersedes Am29LV160M and is the factory-

recommended migration path. Please refer to the S29GL016A datasheet for spec-

ifications and ordering information. Availability of this document is retained for

reference and historical purposes only.

Revision B5 (January 31, 2007)

Global

Changed SecSi to Secured Silicon.

Erase and Program Operations table

Changed t_BUSYto a maximum specification.

60

Am29LV160M

25974B5 January 31, 2007

D a t a S h e e t

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary

industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that

includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal

injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control,

medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and

artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-men-

tioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other

abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under

the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products

Trademarks and Notice

marks of Spansion Inc. Other company and product names used in this publication are for identification purposes only and may be trademarks of their re-

spective companies.

vanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes

only and may be trademarks of their respective companies.

January 31, 2007 25974B5

Am29LV160M

61


型号：	AM29LV160MT70REI
厂家：	AMD
描述：	16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBit TM 3.0 Volt-only Boot Sector Flash Memory 16兆位（2M ×8位/ 1的M× 16位）的MirrorBit TM 3.0伏只引导扇区闪存闪存内存集成电路光电二极管
文件：	总63页 (文件大小：1389K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV160MT70REI [AMD]

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