AM29LV320DB90WMC [AMD]
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory; 32兆位( 4米×8位/ 2的M× 16位) CMOS 3.0伏只,引导扇区闪存型号: | AM29LV320DB90WMC |
厂家: | AMD |
描述: | 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory |
文件: | 总57页 (文件大小:1070K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Am29LV320D
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not available for designs. For new and current designs,
S29AL032D supersedes Am29LV320D and is the factory-recommended migration path. Please refer
to the S29AL032D datasheet for specifications and ordering information. Availability of this docu-
ment is retained for reference and historical purposes only.
April 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 23579 Revision C Amendment 8 Issue Date December 14, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29LV320D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory
This product has been retired and is not available for designs. For new and current designs, S29AL032D supersedes Am29LV320D and is the factory-recommended migration path. Please
refer to the S29AL032D datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Minimum 1 million erase cycles guaranteed per
sector
Secured Silicon
20 Year data retention at 125°C
— 64 Kbyte Sector Size; Replacement/substitute
— Reliable operation for the life of the system
devices (such as Mirrorbit™) have 256 bytes.
— Factory locked and identifiable: 16 bytes (8 words)
available for secure, random factory Electronic Serial
Number; verifiable as factory locked through
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
autoselect function. ExpressFlash option allows
entire sector to be available for factory-secured data
— Suspends erase operations to allow programming in
non-suspended sectors
— Customer lockable: Can be programmed once and
then permanently locked after being shipped from
AMD
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
Zero Power Operation
Unlock Bypass Program command
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
— Reduces overall programming time when issuing
multiple program command sequences
Package options
— 48-pin TSOP
— 48-ball FBGA
HARDWARE FEATURES
Any combination of sectors can be erased
Ready/Busy# output (RY/BY#)
Sector Architecture
— Hardware method for detecting program or erase
cycle completion
— Eight 8 Kbyte sectors
— Sixty-three 64 Kbyte sectors
Top or bottom boot block
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
Manufactured on 0.23 µm process technology
Compatible with JEDEC standards
WP#/ACC input pin
— Pinout and software compatible with
single-power-supply flash standard
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
PERFORMANCE CHARACTERISTICS
— Acceleration (ACC) function provides accelerated
program times
High performance
— Access time as fast 90 ns
Sector protection
— Program time: 7µs/word typical utilizing Accelerate
function
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
Publication# 23579
Issue Date: December 14, 2005
Rev: C Amendment/8
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29LV320D is a 32 megabit, 3.0 volt-only flash
memory device, organized as 2,097,152 words of 16
bits each or 4,194,304 bytes of 8 bits each. Word
mode data appears on DQ0–DQ15; byte mode data
appears on DQ0–DQ7. The device is designed to be
programmed in-system with the standard 3.0 volt VCC
supply, and can also be programmed in standard
EPROM programmers.
or both. Customer Lockable parts may utilize the Se-
cured Silicon sector as bonus space, reading and writ-
ing like any other flash sector, or may permanently
lock their own code there.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The device is available with an access time of 90 or
120 ns. The devices are offered in 48-pin TSOP and
48-ball FBGA packages. Standard control pins—chip
enable (CE#), write enable (WE#), and output enable
(OE#)—control normal read and write operations, and
avoid bus contention issues.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
is completed, the device automatically returns to the
read mode.
The device requires only a single 3.0 volt power sup-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Am29LV320D Features
The Secured Silicon sector is an extra sector capa-
ble of being permanently locked by AMD or custom-
ers. The Secured Silicon Indicator Bit (DQ7) is
permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, cus-
tomer lockable parts can never be used to replace a
factory locked part. Note that the Am29LV320D has
a Secured Silicon sector size of 64 Kbytes. AMD
devices designated as replacements or substi-
tutes, such as the Am29LV320M, have 256 bytes.
This should be considered during system design.
Hardware data protection measures include a low
VCC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses are stable for a specified amount of time,
the device enters the automatic sleep mode. The
system can also place the device into the standby
mode. Power consumption is greatly reduced in both
modes.
Factory locked parts provide several options. The Se-
cured Silicon sector may store a secure, random 16
byte ESN (Electronic Serial Number), customer code
(programmed through AMD’s ExpressFlash service),
2
Am29LV320D
December 14, 2005
D A T A S H E E T
TABLE OF CONTENTS
Continuity of Specifications ....................................................... i
For More Information ................................................................. i
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1
ARCHITECTURAL ADVANTAGES ...................................... 1
PERFORMANCE CHARACTERISTICS ............................... 1
SOFTWARE FEATURES ..................................................... 1
HARDWARE FEATURES .................................................... 1
General Description . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 6
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29LV320D Device Bus Operations ..............................10
Word/Byte Configuration ........................................................ 11
Requirements for Reading Array Data ................................... 11
Writing Commands/Command Sequences ............................ 11
Accelerated Program Operation .......................................... 11
Autoselect Functions ........................................................... 11
Standby Mode ........................................................................ 12
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Top Boot Sector Addresses (Am29LV320DT) ..................13
Table 3. Top Boot Secured Silicon Sector Addresses ................... 14
Table 4. Bottom Boot Sector Addresses (Am29LV320DB) .............14
Table 5. Bottom Boot Secured Silicon Sector Addresses.............. 15
Autoselect Mode ..................................................................... 16
Table 6. Autoselect Codes (High Voltage Method) ........................16
Sector/Sector Block Protection and Unprotection .................. 17
Table 7. Top Boot Sector/Sector Block Addresses
Reset Command ..................................................................... 25
Autoselect Command Sequence ............................................ 25
Table 13. Autoselect Codes ........................................................... 25
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence ..............................................................25
Byte/Word Program Command Sequence ............................. 26
Unlock Bypass Command Sequence .................................. 26
Figure 4. Program Operation ......................................................... 27
Chip Erase Command Sequence ........................................... 27
Sector Erase Command Sequence ........................................ 27
Erase Suspend/Erase Resume Commands ...........................28
Figure 5. Erase Operation.............................................................. 28
Command Definitions ............................................................. 29
Table 14. Am29LV320D Command Definitions ............................. 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data# Polling ................................................................. 30
Figure 6. Data# Polling Algorithm .................................................. 30
RY/BY#: Ready/Busy# ............................................................ 31
DQ6: Toggle Bit I .................................................................... 31
Figure 7. Toggle Bit Algorithm........................................................ 31
DQ2: Toggle Bit II ................................................................... 31
Reading Toggle Bits DQ6/DQ2 ............................................... 32
DQ5: Exceeded Timing Limits ................................................ 32
DQ3: Sector Erase Timer ....................................................... 32
Table 15. Write Operation Status ................................................... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 8. Maximum Negative Overshoot Waveform ...................... 34
Figure 9. Maximum Positive Overshoot Waveform........................ 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
CMOS Compatible .................................................................. 35
Zero-Power Flash ................................................................. 36
Figure 10. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents)............................................................. 36
Figure 11. Typical ICC1 vs. Frequency............................................ 36
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 12. Test Setup.................................................................... 37
Table 16. Test Specifications ......................................................... 37
Figure 13. Input Waveforms and Measurement Levels ................. 37
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Read-Only Operations ........................................................... 38
Figure 14. Read Operation Timings............................................... 38
Hardware Reset (RESET#) .................................................... 39
Figure 15. Reset Timings............................................................... 39
Word/Byte Configuration (BYTE#) ............................................. 40
Figure 16. BYTE# Timings for Read Operations............................ 40
Figure 17. BYTE# Timings for Write Operations............................ 40
Erase and Program Operations ................................................. 41
Figure 18. Program Operation Timings.......................................... 42
Figure 19. Chip/Sector Erase Operation Timings .......................... 43
Figure 20. Data# Polling Timings (During Embedded Algorithms). 44
Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 45
Figure 22. DQ2 vs. DQ6................................................................. 45
Temporary Sector Unprotect ..................................................... 46
Figure 23. Temporary Sector Unprotect Timing Diagram .............. 46
Figure 24. Accelerated Program Timing Diagram.......................... 46
Figure 25. Sector/Sector Block Protect and
for Protection/Unprotection .............................................................17
Table 8. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................17
Write Protect (WP#) ................................................................ 18
Temporary Sector Unprotect .................................................. 18
Figure 1. Temporary Sector Unprotect Operation........................... 18
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 19
Secured Silicon Sector Flash Memory Region ....................... 20
Factory Locked: Secured Silicon Sector Programmed
and Protected at the Factory ............................................... 20
Customer Lockable: Secured Silicon Sector NOT Programmed
or Protected at the Factory .................................................. 20
Figure 3. Secured Silicon Sector Protect Verify.............................. 21
Hardware Data Protection ...................................................... 21
Low VCC Write Inhibit ......................................................... 21
Write Pulse “Glitch” Protection ............................................ 21
Logical Inhibit ...................................................................... 21
Power-Up Write Inhibit ......................................................... 21
Common Flash Memory Interface (CFI) . . . . . . .21
Table 9. CFI Query Identification String.......................................... 22
Table 10. System Interface String................................................... 22
Table 11. Device Geometry Definition ............................................ 23
Table 12. Primary Vendor-Specific Extended Query ...................... 24
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Reading Array Data ................................................................ 25
Unprotect Timing Diagram ............................................................. 47
Alternate CE# Controlled Erase and Program Operations ........ 48
Figure 26. Alternate CE# Controlled Write
December 14, 2005
Am29LV320D
3
D A T A S H E E T
(Erase/Program) Operation Timings ............................................... 49
Ordering Information ............................................................ 53
Secured Silicon Flash Memory Region ............................... 53
Command Definitions .......................................................... 53
AC Characteristics ............................................................... 53
DC Characteristics ............................................................... 53
TSOP, SO, and BGA Package Capacitance ....................... 53
Distinctive Characteristics ................................................... 53
Secured Silicon Flash Memory Region ............................... 53
Command Definitions .......................................................... 54
Erase and Programming Performance ................................ 54
Distinctive Characteristics ................................................... 54
Secured Silicon Sector ........................................................ 54
Valid Combinations ..............................................................54
Command Definitions .......................................................... 54
Ordering Information ............................................................ 54
Product Selector Guide ....................................................... 54
Global .................................................................................. 54
Ordering Information ............................................................ 54
Erase and Programming Performance ................................ 54
AC Characteristics ............................................................... 54
Erase and Program Operations ........................................... 54
Alternate CE# Control Erase and Program Operations ....... 54
Command Definitions .......................................................... 54
Global .................................................................................. 54
Common Flash Memory Interfacte (CFI) ............................. 54
Global .................................................................................. 54
Erase And Programming Performance . . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 50
TSOP and BGA Package Capacitance . . . . . . . 50
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)
6 x 12 mm package ................................................................... 51
TS 048—48-Pin Standard TSOP ............................................... 52
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53
Ordering Information ............................................................ 53
Connection Diagrams .......................................................... 53
Global .................................................................................. 53
Table 3, Top Boot Secured Silicon Sector Addresses ......... 53
Sector/Sector Block Protection and Unprotection ............... 53
Secured Silicon Sector Flash Memory Region .................... 53
Global .................................................................................. 53
Ordering Information ............................................................ 53
Table 1, Am29LV320D Device Bus Operations ................... 53
Secured Silicon Sector Flash Memory Region .................... 53
Autoselect Command Sequence ......................................... 53
Table 14, Am29LV320D Command Definitions ................... 53
Erase and Program Operations table .................................. 53
Figure 3, Secured Silicon Sector Protect Verify ................... 53
Distinctive Characteristics ................................................... 53
Connection Diagrams .......................................................... 53
4
Am29LV320D
December 14, 2005
D A T A S H E E T
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV320D
Standard Voltage Range: VCC = 2.7–3.6 V
90R Standard Voltage Range: VCC = 3.0–3.6 V
Speed Option
90
120
120
120
50
Max Access Time (ns)
CE# Access (ns)
90
90
40
OE# Access (ns)
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
Input/Output
Buffers
RESET#
State
Control
WE#
BYTE#
Command
Register
PGM Voltage
Generator
Data
Latch
Chip Enable
Output Enable
Logic
STB
CE#
OE#
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
Cell Matrix
X-Decoder
A0–A20
December 14, 2005
Am29LV320D
5
D A T A S H E E T
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48-Pin Standard TSOP
A19
A20
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
6
Am29LV320D
December 14, 2005
D A T A S H E E T
CONNECTION DIAGRAMS
48-Ball FBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
VSS
A13
A12
A14
A15
A16
BYTE# DQ15/A-1
A5
A9
B5
A8
C5
D5
E5
F5
G5
H5
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
VCC
WE# RESET#
NC
A19
DQ5
DQ12
DQ4
A3 B3
C3
D3
E3
F3
G3
H3
RY/BY# WP#/ACC A18
A20
DQ2
DQ10
DQ11
DQ3
A2
A7
B2
C2
A6
D2
A5
E2
F2
G2
H2
A17
DQ0
DQ8
DQ9
DQ1
A1
A3
B1
A4
C1
A2
D1
A1
E1
A0
F1
G1
H1
VSS
CE#
OE#
Special Package Handling Instructions
Special handling is required for Flash Memory prod-
ucts in molded (TSOP, BGA) packages.
The package and/or data integrity may be compro-
mised if the package body is exposed to temperatures
above 150°C for prolonged periods of time.
December 14, 2005
Am29LV320D
7
D A T A S H E E T
PIN DESCRIPTION
LOGIC SYMBOL
A0–A20
= 21 Addresses
21
DQ0–DQ14 = 15 Data Inputs/Outputs
A0–A20
16 or 8
DQ15/A-1
= DQ15 (Data Input/Output, word
mode), A-1 (LSB Address Input, byte
mode)
DQ0–DQ15
(A-1)
CE#
OE#
CE#
OE#
WE#
= Chip Enable
= Output Enable
= Write Enable
WE#
WP#/ACC
RESET#
BYTE#
WP#/ACC = Hardware Write Protect/
Acceleration Pin
RY/BY#
RESET#
BYTE#
RY/BY#
VCC
= Hardware Reset Pin, Active Low
= Selects 8-bit or 16-bit mode
= Ready/Busy Output
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS
NC
= Device Ground
= Pin Not Connected Internally
8
Am29LV320D
December 14, 2005
D A T A S H E E T
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the following:
Am29LV320D
T
90
E
C
TEMPERATURE RANGE
I
=
=
=
=
=
=
Industrial (–40°C to +85°C)
Industrial (–40°C to +85°C) with Pb-free package
Commercial (0°C to +70°C)
Commercial (0°C to +70°C) with Pb-free package
Automotive In-Cabin (-40°C to +105°C)
Automotive In-Cabin (-40°C to +105°C) with Pb-free package
F
C
D
V
Y
PACKAGE TYPE
E
=
48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
WM
=
48-ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 12 mm package (FBD048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top boot sector
Bottom boot sector
DEVICE NUMBER/DESCRIPTION
Am29LV320D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Boot Sector Flash Memory
3.0 Volt-only Read, Program and Erase
Valid Combinations for TSOP
Packages
Speed
(Ns)
VCC
Range
Valid Combinations for FBGA Packages
Order Number Package Marking
AM29LV320DT90,
AM29LV320DT90R,
AM29LV320DB90R
L320DT90V,
L320DB90V
WMC,
WMI,
WMD,
WMF
90
90
3.0– 3.6V
2.7– 3.6V
2.7– 3.6V
2.7 – 3,6V
AM29LV320DB90
C, I,
D, F
Am29LV320DT90,
Am29LV320DB90
EC, EI,
ED, EF
AM29LV320DT120,
AM29LV320DB120
L320DT12V,
L320DB12V
AM29LV320DT120,
AM29LV320DB120
Am29LV320DT120
Am29LV320DB120
L320DT12V
L320DB12V
120
120
WNV
V, Y
Am29LV320DT120
Am29LV320DB120
EV, EY
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
December 14, 2005
Am29LV320D
9
D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV320D Device Bus Operations
DQ8–DQ15
BYTE#
Addresses
(Note 2)
DQ0–
DQ7
BYTE#
= VIH
Operation
CE# OE# WE# RESET# WP#/ACC
= VIL
Read
Write
L
L
L
H
H
H
L
L
H
H
L/H
(Note 3)
VHH
AIN
AIN
AIN
DOUT
DOUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
(Note 4) (Note 4)
(Note 4) (Note 4)
Accelerated Program
Standby
L
H
VCC
0.3 V
±
VCC ±
0.3 V
X
X
H
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
L/H
L/H
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
SA, A6 = L,
A1 = H, A0 = L
Sector Protect (Note 2)
L
L
H
H
X
L
L
VID
VID
VID
L/H
(Note 4)
(Note 4)
X
X
X
X
Sector Unprotect
(Note 2)
SA, A6 = H,
A1 = H, A0 = L
(Note 3)
(Note 3)
Temporary Sector
Unprotect
X
X
AIN
(Note 4) (Note 4)
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See “Sector/Sector
Block Protection and Unprotection” on page 17.
3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection” on page 17. If WP#/ACC = VHH, all sectors are unprotected.
4. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
10
Am29LV320D
December 14, 2005
D A T A S H E E T
Unlock Bypass mode, only two write cycles are re-
Word/Byte Configuration
quired to program a word or byte, instead of four. The
“Word/Byte Configuration” on page 11 section con-
tains details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 on page 13 through
Table 5 on page 15 indicate the address space that
each sector occupies. A “sector address” is the ad-
dress bits required to uniquely select a sector.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” on page 38 section contains timing
specification tables and timing diagrams for write oper-
ations.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
If the system asserts VHH on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not be
at VHH for operations other than accelerated program-
ming, or device damage may result. In addition, the
WP#/ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
See “Requirements for Reading Array Data” on
page 11 for more information. Refer to the AC
Read-Only Operations table for timing specifications
and to Figure 14, on page 38 for the timing diagram.
ICC1 in the DC Characteristics table represents the ac-
tive current specification for reading array data.
Autoselect Functions
Writing Commands/Command Sequences
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the “Autoselect Mode” on page 16
and “Autoselect Command Sequence” on page 25
sections for more information.
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” on page 11
for more information.
ICC6 and ICC7 in the DC Characteristics table represent
the current specifications for read-while-program and
read-while-erase, respectively.
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
December 14, 2005
Am29LV320D
11
D A T A S H E E T
SET# pin is driven low for at least a period of tRP, the
Standby Mode
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC 0.3 V, the device is in the standby mode, but the
standby current is greater. The device requires stan-
dard access time (tCE) for read access when the de-
vice is in either of these standby modes, before it is
ready to read data.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS 0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS 0.3 V, the standby current is
greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for tACC
+
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
ICC4 in the “DC Characteristics” on page 35 table rep-
resents the automatic sleep mode current specifica-
tion.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 15, on page 39 for the timing
diagram.
Output Disable Mode
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
12
Am29LV320D
December 14, 2005
D A T A S H E E T
Table 2. Top Boot Sector Addresses (Am29LV320DT) (Sheet 1 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
SA0
Address Range
000000xxx
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
110000xxx
110001xxx
110010xxx
110011xxx
110100xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000h–00FFFFh
010000h–01FFFFh
020000h–02FFFFh
030000h–03FFFFh
040000h–04FFFFh
050000h–05FFFFh
060000h–06FFFFh
070000h–07FFFFh
080000h–08FFFFh
090000h–09FFFFh
0A0000h–0AFFFFh
0B0000h–0BFFFFh
0C0000h–0CFFFFh
0D0000h–0DFFFFh
0E0000h–0EFFFFh
0F0000h–0FFFFFh
100000h–10FFFFh
110000h–11FFFFh
120000h–12FFFFh
130000h–13FFFFh
140000h–14FFFFh
150000h–15FFFFh
160000h–16FFFFh
170000h–17FFFFh
180000h–18FFFFh
190000h–19FFFFh
1A0000h–1AFFFFh
1B0000h–1BFFFFh
1C0000h–1CFFFFh
1D0000h–1DFFFFh
1E0000h–1EFFFFh
1F0000h–1FFFFFh
200000h–20FFFFh
210000h–21FFFFh
220000h–22FFFFh
230000h–23FFFFh
240000h–24FFFFh
250000h–25FFFFh
260000h–26FFFFh
270000h–27FFFFh
280000h–28FFFFh
290000h–29FFFFh
2A0000h–2AFFFFh
2B0000h–2BFFFFh
2C0000h–2CFFFFh
2D0000h–2DFFFFh
2E0000h–2EFFFFh
2F0000h–2FFFFFh
300000h–30FFFFh
310000h–31FFFFh
320000h–32FFFFh
330000h–33FFFFh
340000h–34FFFFh
000000h–07FFFh
008000h–0FFFFh
010000h–17FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
December 14, 2005
Am29LV320D
13
D A T A S H E E T
Table 2. Top Boot Sector Addresses (Am29LV320DT) (Sheet 2 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Address Range
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
350000h–35FFFFh
360000h–36FFFFh
370000h–37FFFFh
380000h–38FFFFh
390000h–39FFFFh
3A0000h–3AFFFFh
3B0000h–3BFFFFh
3C0000h–3CFFFFh
3D0000h–3DFFFFh
3E0000h–3EFFFFh
3F0000h–3F1FFFh
3F2000h–3F3FFFh
3F4000h–3F5FFFh
3F6000h–3F7FFFh
3F8000h–3F9FFFh
3FA000h–3FBFFFh
3FC000h–3FDFFFh
3FE000h–3FFFFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1F8FFFh
1F9000h–1F9FFFh
1FA000h–1FAFFFh
1FB000h–1FBFFFh
1FC000h–1FCFFFh
1FD000h–1FDFFFh
1FE000h–1FEFFFh
1FF000h–1FFFFFh
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).
Table 3. Top Boot Secured Silicon Sector Addresses
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Address Range
111111xxx
64/32
3F0000h–3FFFFFh
1F8000h–1FFFFFh
Table 4. Bottom Boot Sector Addresses (Am29LV320DB) (Sheet 1 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
SA0
Address Range
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001xxx
000010xxx
000011xxx
000100xxx
000101xxx
000110xxx
000111xxx
001000xxx
001001xxx
001010xxx
001011xxx
001100xxx
001101xxx
001110xxx
001111xxx
010000xxx
010001xxx
010010xxx
010011xxx
010100xxx
010101xxx
010110xxx
8/4
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
000000h–000FFFh
001000h–001FFFh
002000h–002FFFh
003000h–003FFFh
004000h–004FFFh
005000h–005FFFh
006000h–006FFFh
007000h–007FFFh
008000h–00FFFFh
010000h–017FFFh
018000h–01FFFFh
020000h–027FFFh
028000h–02FFFFh
030000h–037FFFh
038000h–03FFFFh
040000h–047FFFh
048000h–04FFFFh
050000h–057FFFh
058000h–05FFFFh
060000h–067FFFh
068000h–06FFFFh
070000h–077FFFh
078000h–07FFFFh
080000h–087FFFh
088000h–08FFFFh
090000h–097FFFh
098000h–09FFFFh
0A0000h–0A7FFFh
0A8000h–0AFFFFh
0B0000h–0B7FFFh
SA1
8/4
SA2
8/4
SA3
8/4
SA4
8/4
SA5
8/4
SA6
8/4
SA7
8/4
SA8
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
14
Am29LV320D
December 14, 2005
D A T A S H E E T
Table 4. Bottom Boot Sector Addresses (Am29LV320DB) (Sheet 2 of 2)
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Sector
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
Address Range
010111xxx
011000xxx
011001xxx
011010xxx
011011xxx
011100xxx
011101xxx
011110xxx
011111xxx
100000xxx
100001xxx
100010xxx
100011xxx
100100xxx
100101xxx
100110xxx
100111xxx
101000xxx
101001xxx
101010xxx
101011xxx
101100xxx
101101xxx
101110xxx
101111xxx
111000xxx
110001xxx
110010xxx
110011xxx
110100xxx
110101xxx
110110xxx
110111xxx
111000xxx
111001xxx
111010xxx
111011xxx
111100xxx
111101xxx
111110xxx
111111xxx
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
0B8000h–0BFFFFh
0C0000h–0C7FFFh
0C8000h–0CFFFFh
0D0000h–0D7FFFh
0D8000h–0DFFFFh
0E0000h–0E7FFFh
0E8000h–0EFFFFh
0F0000h–0F7FFFh
0F8000h–0FFFFFh
100000h–107FFFh
108000h–10FFFFh
110000h–117FFFh
118000h–11FFFFh
120000h–127FFFh
128000h–12FFFFh
130000h–137FFFh
138000h–13FFFFh
140000h–147FFFh
148000h–14FFFFh
150000h–157FFFh
158000h–15FFFFh
160000h–167FFFh
168000h–16FFFFh
170000h–177FFFh
178000h–17FFFFh
180000h–187FFFh
188000h–18FFFFh
190000h–197FFFh
198000h–19FFFFh
1A0000h–1A7FFFh
1A8000h–1AFFFFh
1B0000h–1B7FFFh
1B8000h–1BFFFFh
1C0000h–1C7FFFh
1C8000h–1CFFFFh
1D0000h–1D7FFFh
1D8000h–1DFFFFh
1E0000h–1E7FFFh
1E8000h–1EFFFFh
1F0000h–1F7FFFh
1F8000h–1FFFFFh
Note: The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).
Table 5. Bottom Boot Secured Silicon Sector Addresses
Sector Address
A20–A12
Sector Size
(Kbytes/Kwords)
(x8)
(x16)
Address Range
Address Range
000000xxx
64/32
000000h-00FFFFh
00000h-07FFFh
December 14, 2005
Am29LV320D
15
D A T A S H E E T
protection, the sector address must appear on the ap-
Autoselect Mode
propriate highest order address bits (see Table 2 on
page 13 through Table 5 on page 15). Table 6 on
page 16 shows the remaining address bits that are
don’t care. When all necessary bits are set as re-
quired, the programming equipment may then read the
corresponding identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and de-
vice identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equip-
ment to automatically match a device to be pro-
grammed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 14 on page 29.
This method does not require VID. Refer to the “Au-
toselect Command Sequence” on page 25 section for
more information.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 6 on page 16. In addition, when verifying sector
Table 6. Autoselect Codes (High Voltage Method)
DQ8 to DQ15
A20
to
A11
to
A8
to
A5
to
DQ7
to
BYTE#= BYTE#
Description
Manufacturer ID: AMD
Device ID: Am29LV320D
CE# OE#
WE#
H
A12
A10
A9
A7
A6
L
A2
A1
L
A0
L
VIH
= VIL
DQ0
VID
L
L
L
L
X
X
X
X
X
X
X
X
X
X
01h
VID
VID
H
L
L
H
22h
X
F6 (T), F9h (B)
01h (protected),
00h (unprotected)
Sector Protection Verification
L
L
L
L
H
H
SA
X
X
X
X
X
L
L
X
X
H
H
L
X
X
X
X
Secured Silicon Sector
Indicator Bit (DQ7)
99h (factory locked),
19h (not factory locked)
VID
H
Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t
care.
16
Am29LV320D
December 14, 2005
D A T A S H E E T
Sector/Sector Block Protection and
Unprotection
Sector / Sector
Block
A20–A12
Sector/Sector Block Size
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA62-SA59
SA58-SA55
SA54-SA51
SA50-SA47
SA46-SA43
SA42-SA39
SA38-SA35
SA34-SA31
SA30-SA27
SA26-SA23
SA22–SA19
SA18-SA15
SA14-SA11
1101XXXXX
1100XXXXX
1011XXXXX
1010XXXXX
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXXX
The hardware sector protection feature disables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both pro-
gram and erase operations in previously protected
sectors. Sector protection/unprotection can be imple-
mented via two methods.
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see
Table 7 on page 17 and Table 8 on page 17).
Table 7. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection
000011XXX,
000010XXX,
000001XXX
SA10-SA8
192 (3x64) Kbytes
Sector / Sector
Block
A20–A12
Sector/Sector Block Size
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
000000XXX,
000001XXX,
000010XXX
000011XXX
SA0-SA3
256 (4x64) Kbytes
SA4-SA7
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
Sector Protection and unprotection requires VID on the
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 2, on
page 19 shows the algorithms and Figure 25, on page
47 shows the timing diagram. This method uses stan-
dard microprocessor bus cycle timing. For sector un-
protect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle.
The sector unprotect algorithm unprotects all sectors
in parallel. All previously protected sectors must be in-
dividually re-protected. To change data in protected
sectors efficiently, the temporary sector unprotect
function is available. See “Temporary Sector Unpro-
tect” on page 18.
111100XXX,
111101XXX,
111110XXX
SA60-SA62
192 (3x64) Kbytes
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
The alternate method intended only for programming
equipment, and requires VID on address pin A9 and
OE#. This method is compatible with programmer rou-
tines written for earlier 3.0 volt-only AMD flash de-
vices. For detailed information, contact an AMD
representative.
Table 8. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
Sector / Sector
Block
A20–A12
Sector/Sector Block Size
256 (4x64) Kbytes
111111XXX,
111110XXX,
111101XXX,
111100XXX
SA70-SA67
SA66-SA63
It is possible to determine whether a sector is pro-
tected or unprotected. See “Autoselect Mode” on
page 16 for details.
1110XXXXX
256 (4x64) Kbytes
December 14, 2005
Am29LV320D
17
D A T A S H E E T
erased by selecting the sector addresses. Once VID is
Write Protect (WP#)
removed from the RESET# pin, all the previously pro-
tected sectors are protected again. Figure 1, on page
18 shows the algorithm, and Figure 23, on page 46
shows the timing diagrams, for this feature.
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using VID. This function is one of two provided by the
WP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin, the de-
vice disables program and erase functions in the two
“outermost” 8 Kbyte boot sectors independently of
whether those sectors were protected or unprotected
using the method described in “Sector/Sector Block
Protection and Unprotection” on page 17. The two out-
ermost 8 Kbyte boot sectors are the two sectors con-
START
RESET# = VID
(Note 1)
taining
the
lowest
addresses
in
a
bottom-boot-configured device, or the two sectors con-
taining the highest addresses in a top-boot-configured
device.
Perform Erase or
Program Operations
If the system asserts VIH on the WP#/ACC pin, the de-
vice reverts to whether the two outermost 8K Byte
boot sectors were last set to be protected or unpro-
tected. That is, sector protection or unprotection for
these two sectors depends on whether they were last
protected or unprotected using the method described
in “Sector/Sector Block Protection and Unprotection”
on page 17.
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors remain protected).
Temporary Sector Unprotect
2. All previously protected sectors are protected once
again.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RE-
SET# pin to VID (11.5 V – 12.5 V). During this mode,
formerly protected sectors can be programmed or
Figure 1. Temporary Sector Unprotect Operation
18
Am29LV320D
December 14, 2005
D A T A S H E E T
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT = 1
PLSCNT = 1
RESET# = VID
RESET# = VID
unprotected sectors
prior to issuing the
first sector
Wait 1 μs
Wait 1 μs
unprotect address
No
First Write
Cycle = 60h?
No
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Wait 150 µs
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
Reset
PLSCNT = 1
Increment
PLSCNT
Wait 15 ms
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
Data = 01h?
Yes
A1 = 1, A0 = 0
No
Yes
Set up
next sector
address
Yes
No
PLSCNT
= 1000?
Protect another
sector?
Data = 00h?
Yes
Device failed
No
Yes
Remove VID
from RESET#
No
Last sector
verified?
Device failed
Write reset
command
Yes
Remove VID
Sector Unprotect
Algorithm
from RESET#
Sector Protect
Algorithm
Sector Protect
complete
Write reset
command
Sector Unprotect
complete
Figure 2. In-System Sector Protect/Unprotect Algorithms
December 14, 2005
Am29LV320D
19
D A T A S H E E T
In devices that have an ESN, a Bottom Boot device
Secured Silicon Sector Flash Memory
Region
has the 16-byte (8-word) ESN in sector 0 at addresses
00000h–0000Fh in byte mode (or 00000h–00007h in
word mode). In the Top Boot device the ESN is in sec-
tor 63 at addresses 3F0000h–3F000Fh in byte mode
(or 1F8000h–1F8007h in word mode). Note that in up-
coming top boot versions of this device, the ESN is lo-
cated in sector 70 at addresses 3FE000h–3FE00Fh in
byte mode (or 1FF000h–1FF007h in word mode).
The Secured Silicon sector provides a Flash memory
region that enables permanent part identification
through an Electronic Serial Number (ESN). The Se-
cured Silicon sector uses a Secured Silicon Indicator
Bit (DQ7) to indicate whether or not the Secured Sili-
con sector is locked when shipped from the factory.
This bit is permanently set at the factory and cannot
be changed, which prevents cloning of a factory locked
part. This ensures the security of the ESN once the
product is shipped to the field. Note that the
Am29LV320D has a Secured Silicon sector size of
64 Kbytes. AMD devices designated as replace-
ments or substitutes, such as the Am29LV320M,
have 256 bytes. This should be considered during
system design.
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. AMD
programs the customer’s code, with or without the ran-
dom ESN. The devices are then shipped from AMD’s
factory with the Secured Silicon Sector permanently
locked. Contact an AMD representative for details on
using AMD’s ExpressFlash service.
Customer Lockable: Secured Silicon Sector NOT
Programmed or Protected at the Factory
AMD offers the device with the Secured Silicon sector
either factory locked or customer lockable. The fac-
tory-locked version is always protected when shipped
from the factory, and has the Secured Silicon sector
Indicator Bit permanently set to a “1.” The cus-
tomer-lockable version is shipped with the Secured
Silicon sector unprotected, allowing customers to uti-
lize the that sector in any manner they choose. The
customer-lockable version has the Secured Silicon In-
dicator Bit permanently set to a “0.” Thus, the Secured
Silicon Indicator Bit prevents customer-lockable de-
vices from being used to replace devices that are fac-
tory locked.
The customer lockable version allows the Secured Sil-
icon Sector to be programmed once and then perma-
nently locked after it ships from AMD. Note that the
Am29LV320D has a Secured Silicon Sector size of
64 Kbytes. AMD devices designated as replace-
ments or substitutes, such as the Am29LV320M,
have 256 bytes. This should be considered during
system design. Additionally, note the change in
the location of the ESN in upcoming top boot fac-
tory locked devices. Note that the accelerated pro-
gramming (ACC) and unlock bypass functions are not
available when programming the Secured Silicon Sec-
tor.
The system accesses the Secured Silicon sector
through a command sequence (see “Enter Secured
Silicon Sector/Exit Secured Silicon Sector
Command Sequence” on page 25). After the system
writes the Enter Secured Silicon sector command se-
quence, it may read the Secured Silicon Sector by
using the addresses normally occupied by the boot
sectors. This mode of operation continues until the
system issues the Exit Secured Silicon Sector com-
mand sequence, or until power is removed from the
device. On power-up, or following a hardware reset,
the device reverts to sending commands to the boot
sectors.
The Secured Silicon Sector area can be protected
using the following procedures:
■ Write the three-cycle Enter Secured Silicon Sector
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, on
page 19, except that RESET# may be at either VIH
or VID. This allows in-system protection of the Se-
cured Silicon Sector without raising any device pin
to a high voltage. Note that this method is only ap-
plicable to the Secured Silicon Sector.
■ To verify the protect/unprotect status of the Secured
Silicon Sector, follow the algorithm shown in Figure
3, on page 21.
Factory Locked: Secured Silicon Sector
Programmed and Protected at the Factory
Once the Secured Silicon Sector is locked and veri-
fied, the system must write the Exit Secured Silicon
Sector command sequence to return to reading and
writing the remainder of the array.
In a factory locked device, the Secured Silicon Sector
is protected when the device is shipped from the fac-
tory. The Secured Silicon Sector cannot be modified in
any way. The device is available preprogrammed with
one of the following:
The Secured Silicon Sector protection must be used
with caution since, once protected, there is no proce-
dure available for unprotecting the Secured Silicon
Sector area and none of the bits in the Secured Silicon
Sector memory space can be modified in any way.
■ A random, secure ESN only
■ Customer code through the ExpressFlash service
■ Both a random, secure ESN and customer code
through the ExpressFlash service.
20
Am29LV320D
December 14, 2005
D A T A S H E E T
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
START
Logical Inhibit
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
RESET# =
VIH or VID
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Wait 1 μs
Power-Up Write Inhibit
Write 60h to
any address
Remove VIH or VID
from RESET#
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
Write 40h to SecSi
Sector address
with A6 = 0,
Write reset
command
A1 = 1, A0 = 0
COMMON FLASH MEMORY INTERFACE
(CFI)
SecSi Sector
Protect Verify
complete
Read from SecSi
Sector address
with A6 = 0,
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
A1 = 1, A0 = 0
Figure 3. Secured Silicon Sector Protect Verify
Hardware Data Protection
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The sys-
tem can read CFI information at the addresses given
in Table 9 on page 22 through Table 12 on page 24. To
terminate reading CFI data, the system must write the
reset command.
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 14 on
page 29 for command definitions). In addition, the fol-
lowing hardware data protection measures prevent ac-
cidental erasure or programming, which might
otherwise be caused by spurious system level signals
during VCC power-up and power-down transitions, or
from system noise.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Table 9 on page 22
through Table 12 on page 24. The system must write
the reset command to return the device to the reading
array data.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when VCC is
For further information, please refer to the CFI Specifi-
cation, CFI Publication 100, and the application note
“Common Flash Interface Version 1.4 Vendor Specific
Extensions”. Contact an AMD representative for cop-
ies of these documents.
greater than VLKO
.
December 14, 2005
Am29LV320D
21
D A T A S H E E T
Table 9. CFI Query Identification String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Table 10. System Interface String
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data Description
VCC Min. (write/erase)
0027h
1Bh
1Ch
36h
38h
D7–D4: volt, D3–D0: 100 millivolt
VCC Max. (write/erase)
0036h
D7–D4: volt, D3–D0: 100 millivolt
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
3Ah
3Ch
3Eh
40h
42h
44h
46h
48h
4Ah
4Ch
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
VPP Min. voltage (00h = no VPP pin present)
VPP Max. voltage (00h = no VPP pin present)
Typical timeout per single byte/word write 2N µs
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical (00h = not supported)
22
Am29LV320D
December 14, 2005
D A T A S H E E T
Table 11. Device Geometry Definition
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
27h
4Eh
0016h
Device Size = 2N byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
003Eh
0000h
0000h
0001h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
December 14, 2005
Am29LV320D
23
D A T A S H E E T
Table 12. Primary Vendor-Specific Extended Query
Addresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
44h
86h
88h
0031h
0031h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
45h
8Ah
0000h
Silicon Revision Number (Bits 7-2)
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46h
47h
48h
49h
4Ah
4Bh
4Ch
8Ch
8Eh
90h
92h
94h
96h
98h
0002h
0004h
0001h
0004h
0000h
0000h
0000h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
04 = 29LV800 mode
Simultaneous Operation
00 = Not Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh
4Eh
4Fh
9Ah
9Ch
9Eh
00B5h
00C5h
000Xh
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
24
Am29LV320D
December 14, 2005
D A T A S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 14 on page 29 defines the valid
register command sequences. Note that writing incor-
rect address and data values or writing them in the im-
proper sequence may place the device in an unknown
state. A reset command is required to return the de-
vice to normal operation.
pend-read mode. Once programming begins, however,
the device ignores reset commands until the operation
is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If the de-
vice entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns the
device to the erase-suspend-read mode.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to the
read mode (or erase-suspend-read mode if the device
was in Erase Suspend).
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to read several identifier codes at specific ad-
dresses:
Table 13. Autoselect Codes
After the device accepts an Erase Suspend command,
the device enters the erase-suspend-read mode, after
which the system can read data from any
non-erase-suspended sector. After completing a pro-
gramming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See “Erase Suspend/Erase Resume Com-
mands” on page 28 for more information.
Identifier Code
Manufacturer ID
Device ID
Address
00h
01h
Secured Silicon Sector
Factory Protect
03h
Sector Group Protect Verify
(SA)02h
Table 14 on page 29 shows the address and data re-
quirements. This method is an alternative to that
shown in Table 6 on page 16, which is intended for
PROM programmers and requires VID on address pin
A9. The autoselect command sequence may be writ-
ten to an address within sector that is either in the read
or erase-suspend-read mode. The autoselect com-
mand may not be written while the device is actively
programming or erasing.
The system must issue the reset command to return
the device to the read (or erase-suspend-read) mode if
DQ5 goes high during an active program or erase op-
eration, or if the device is in the autoselect mode. See
the next section, “Reset Command, for more informa-
tion.
See also “Requirements for Reading Array Data” on
page 11 for more information. The Read-Only Opera-
tions table provides the read parameters, and Figure
14, on page 38 shows the timing diagram.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the autoselect command. The
device then enters the autoselect mode. The system
may read at any address any number of times without
initiating another autoselect command sequence.
Reset Command
Writing the reset command resets the device to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the de-
vice was previously in Erase Suspend).
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to which the
system was writing to the read mode. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
Enter Secured Silicon Sector/Exit Secured
Silicon Sector Command Sequence
The Secured Silicon sector provides a secured data
area containing a random, sixteen-byte electronic se-
rial number (ESN). The system can access the Se-
cured Silicon sector by issuing the three-cycle Enter
Secured Silicon sector command sequence. The de-
vice continues to access the Secured Silicon sector
until the system issues the four-cycle Exit Secured Sil-
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
which the system was writing to the read mode. If the
program command sequence is written to a sector that
is in the Erase Suspend mode, writing the reset
command returns the device to the erase-sus-
December 14, 2005
Am29LV320D
25
D A T A S H E E T
icon sector command sequence. The Exit Secured Sil- data is still “0.” Only erase operations can convert a “0”
icon sector command sequence returns the device to
normal operation. Table 14 on page 29 shows the ad-
dress and data requirements for both command se-
quences. Note that the ACC function and unlock
bypass modes are not available when the device en-
ters the Secured Silicon sector. See also “Secured Sil-
icon Sector Flash Memory Region” on page 20 for
further information.
to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 14 on page 29 shows
the requirements for the command sequence.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Program-
ming is a four-bus-cycle operation. The program com-
mand sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in
turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or
timings. The device automatically provides internally
generated program pulses and verifies the pro-
grammed cell margin. Table 14 on page 29 shows the
address and data requirements for the byte program
command sequence. Note that the autoselect, Se-
cured Silicon sector, and CFI modes are unavailable
while a programming operation is in progress.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
90h. The second cycle need only contain the data 00h.
The device then re turns to the read mode.
When the Embedded Program algorithm is complete,
the device then returns to the read mode and ad-
dresses are no longer latched. The system can deter-
mine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to “Write Operation Sta-
tus” on page 30 for information on these status bits.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically en-
ters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device dam-
age may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once the device returns to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause the device to set DQ5 = 1, or cause the DQ7
and DQ6 status bits to indicate the operation was suc-
cessful. However, a succeeding read shows that the
Figure 4, on page 27 illustrates the algorithm for the
program operation. Refer to the table “Erase and Pro-
gram Operations” on page 41 for parameters, and Fig-
ure 18, on page 42 for timing diagrams.
26
Am29LV320D
December 14, 2005
D A T A S H E E T
RY/BY#. Refer to “Write Operation Status” on page 30
for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the chip erase command sequence should be
reinitiated once the device returns to reading array
data, to ensure data integrity.
START
Write Program
Command Sequence
Figure 5, on page 28 illustrates the algorithm for the
erase operation. Refer to table “Erase and Program
Operations” on page 41 for parameters, and Figure
19, on page 43 section for timing diagrams.
Data Poll
from System
Embedded
Program
algorithm
in progress
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Table 14 on page 29
shows the address and data requirements for the sec-
tor erase command sequence. Note that the autose-
lect, Secured Silicon sector, and CFI modes are
unavailable while an erase operation is in progress.
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
Programming
Completed
Note: See Table 14 on page 29 for program command
sequence.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than
50 µs, otherwise the last address and command may
not be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to the read
mode. The system must rewrite the command se-
quence and any additional addresses and commands.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 14 on
page 29 shows the address and data requirements for
the chip erase command sequence. Note that the au-
toselect, Secured Silicon sector, and CFI modes are
unavailable while an erase operation is in progress.
The system can monitor DQ3 to determine if the sec-
tor erase timer timed out (See the section “DQ3: Sec-
tor Erase Timer” on page 32.). The time-out begins
from the rising edge of the final WE# pulse in the com-
mand sequence.
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6,
December 14, 2005
Am29LV320D
27
D A T A S H E E T
DQ2, or RY/BY# in the erasing sector. Refer to “Write
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to “Write Operation Status” on page 30 for more
information.
Operation Status” on page 30 for information on these
status bits.
Once the sector erase operation begins, only the
Erase Suspend command is valid. All other com-
mands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once the device returns to read-
ing array data, to ensure data integrity.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to
“Autoselect Mode” on page 16 and “Autoselect Com-
mand Sequence” on page 25 for details.
To resume the sector erase operation, the system
must write the Erase Resume command. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the chip
resumes erasing.
Figure 5, on page 28 illustrates the algorithm for the
erase operation. Refer to table “Erase and Program
Operations” on page 41 for parameters, and Figure
19, on page 43 for timing diagrams.
Erase Suspend/Erase Resume
Commands
START
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
Write Erase
Command Sequence
(Notes 1, 2)
Data Poll to Erasing
Bank from System
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
during the sector erase time-out, the device immedi-
ately terminates the time-out period and suspends the
erase operation.
Embedded
Erase
algorithm
in progress
No
Data = FFh?
After the erase operation is suspended, the device en-
ters the erase-suspend-read mode. The system can
read data from or program data to any sector not se-
lected for erasure. (The device “erase suspends” all
sectors selected for erasure.) Reading at any address
within erase-suspended sectors produces status infor-
mation on DQ7–DQ0. The system can use DQ7, or
DQ6 and DQ2 together, to determine if a sector is ac-
tively erasing or is erase-suspended. Refer to the
“Write Operation Status” on page 30 section for infor-
mation on these status bits.
Yes
Erasure Completed
Notes:
1. See Table 14 on page 29 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Figure 5. Erase Operation
After an erase-suspended program operation is com-
plete, the device returns to the erase-suspend-read
28
Am29LV320D
December 14, 2005
D A T A S H E E T
Command Definitions
Table 14. Am29LV320D Command Definitions
Bus Cycles (Notes 2–5)
Command
Sequence
(Note 1)
First
Second
Third
Addr
Fourth
Fifth
Sixth
Addr Data Addr Data
Data
Addr
Data
Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
RA
XXX
555
AAA
555
AAA
555
RD
F0
Word
Manufacturer ID
Byte
2AA
555
2AA
555
2AA
555
AAA
555
4
4
AA
AA
55
55
90
90
X00
01
Word
X01
X02
X03
(see
Table 6)
Device ID
Byte
AAA
555
Secured Silicon
Factory Protect (Note
9)
Word
4
AA
55
90
99/19
00/01
Byte
AAA
555
AAA
X06
Word
Byte
Word
Byte
555
AAA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
PA
555
AAA
555
(SA)X02
(SA)X04
Sector Protect Verify
(Note 10)
4
3
4
4
3
AA
AA
AA
AA
AA
55
55
55
55
55
90
88
90
A0
20
Enter Secured Silicon Sector
Exit Secured Silicon Sector
Program
AAA
555
AAA
555
Word
Byte
XXX
PA
00
AAA
555
AAA
555
Word
Byte
PD
AAA
555
AAA
555
Word
Byte
Unlock Bypass
AAA
XXX
AAA
Unlock Bypass Program (Note 11)
Unlock Bypass Reset (Note 12)
A0
90
PD
00
2
2
XXX
555
AAA
555
AAA
XXX
XXX
55
XXX
2AA
555
2AA
555
Word
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
Byte
6
AA
AA
55
55
80
80
AA
AA
55
55
10
30
AAA
Word
Sector Erase
Byte
6
SA
AAA
AAA
Erase Suspend (Note 13)
Erase Resume (Note 14)
1
1
B0
30
Word
CFI Query (Note 15)
Byte
1
98
AA
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A20–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
9. The data is 99h for factory locked and 19h for not factory locked.
2. All values are in hexadecimal.
10. The data is 00h for an unprotected sector and 01h for a protected
sector.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
12. The Unlock Bypass Reset command is required to return to the
read mode when the device is in the unlock bypass mode.
5. Unless otherwise noted, address bits A20–A11 are don’t cares.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
6. No unlock or command cycles required when device is in read
mode.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a device is in the autoselect mode, or if DQ5 goes high
(while the device is providing status information).
14. The Erase Resume command is valid only during the Erase
Suspend mode.
15. Command is valid when device is ready to read array data or when
device is in autoselect mode.
8. The fourth cycle of the autoselect command sequence is a read
cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect
Command Sequence section for more information.
December 14, 2005
Am29LV320D
29
D A T A S H E E T
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 15 on page 33 and the following
subsections describe the function of these bits. DQ7
and DQ6 each offer a method for determining whether
a program or erase operation is complete or in
progress. The device also provides a hardware-based
output signal, RY/BY#, to determine whether an Em-
bedded Program or Erase operation is in progress or
is completed.
the program or erase operation and DQ7 contains
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 appears on succes-
sive read cycles.
Table 15 on page 33 shows the outputs for Data# Poll-
ing on DQ7. Figure 6, on page 30 shows the Data#
Polling algorithm. Figure 20, on page 44 in the AC
Characteristics section shows the Data# Polling timing
diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether an Embedded Program or Erase algo-
rithm is in progress or completed, or whether a device
is in Erase Suspend. Data# Polling is valid after the
rising edge of the final WE# pulse in the command se-
quence.
START
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to the read
mode.
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device completes
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
30
Am29LV320D
December 14, 2005
D A T A S H E E T
gorithm. Figure 21, on page 45 in the “AC Characteris-
RY/BY#: Ready/Busy#
tics” section shows the toggle bit timing diagrams.
Figure 22, on page 45 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, sev-
eral RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC
.
START
If the output is low (Busy), the device is actively eras-
ing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or in the erase-suspend-read mode. Table 15
on page 33 shows the outputs for RY/BY#.
Read DQ7–DQ0
Read DQ7–DQ0
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or com-
plete, or whether the device entered the Erase Sus-
pend mode. Toggle Bit I may be read at any address,
and is valid after the rising edge of the final WE# pulse
in the command sequence (prior to the program or
erase operation), and during the sector erase time-out.
No
Toggle Bit
= Toggle?
Yes
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
No
DQ5 = 1?
Yes
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are pro-
tected.
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on “DQ7: Data#
Polling” on page 30).
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Figure 7. Toggle Bit Algorithm
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
gram algorithm is complete.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
Table 15 on page 33 shows the outputs for Toggle Bit I
on DQ6. Figure 7, on page 31 shows the toggle bit al-
December 14, 2005
Am29LV320D
31
D A T A S H E E T
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time ex-
ceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1,” indicating that
the program or erase cycle was not successfully
completed.
DQ2 toggles when the system reads at addresses
within those sectors that were selected for erasure.
(The system may use either OE# or CE# to control the
read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6,
by comparison, indicates whether the device is ac-
tively erasing, or is in Erase Suspend, but cannot dis-
tinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode infor-
mation. Refer to Table 15 on page 33 to compare out-
puts for DQ2 and DQ6.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit is
exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if the device was previ-
ously in the erase-suspend-program mode).
Figure 7, on page 31 shows the toggle bit algorithm in
flowchart form, and the section “DQ2: Toggle Bit II” on
page 31 explains the algorithm. See also the DQ6:
Toggle Bit I subsection. Figure 21, on page 45 shows
the toggle bit timing diagram. Figure 22, on page 45
shows the differences between DQ2 and DQ6 in
graphical form.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure started. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7, on page 31 for the following discus-
sion. Whenever the system initially begins reading tog-
gle bit status, it must read DQ7–DQ0 at least twice in a
row to determine whether a toggle bit is toggling. Typi-
cally, the system would note and store the value of the
toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
completed the program or erase operation. The sys-
tem can read array data on DQ7–DQ0 on the following
read cycle.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device accepted the
command sequence, and then read DQ3. If DQ3 is “1,”
the Embedded Erase algorithm started; all further
commands (except Erase Suspend) are ignored until
the erase operation is complete. If DQ3 is “0,” the de-
vice accepts additional sector erase commands. To
ensure the command is accepted, the system software
should check the status of DQ3 prior to and following
each subsequent sector erase command. If DQ3 is
high on the second status check, the last command
might not have been accepted.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device successfully completed the pro-
gram or erase operation. If it is still toggling, the device
did not completed the operation successfully, and the
system must write the reset command to return to
reading array data.
Table 15 on page 33 shows the status of DQ3 relative
to the other status bits.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 7, on
page 31).
32
Am29LV320D
December 14, 2005
D A T A S H E E T
Table 15. Write Operation Status
DQ7
DQ5
DQ2
Status
(Note 2)
DQ6
(Note 1)
DQ3
N/A
1
(Note 2)
RY/BY#
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend-
Read
DQ7#
0
Toggle
Toggle
0
0
No toggle
Toggle
0
0
Standard
Mode
1
No toggle
0
N/A
Toggle
1
Suspended Sector
Erase
Suspend
Mode
Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
DQ7#
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. Refer
to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
December 14, 2005
Am29LV320D
33
D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
VCC (Note 1). . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
A9, OE#, RESET#,
Ambient Temperature
and WP#/ACC (Note 2) . . . . . . . –0.5 V to +12.5 V
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
All other pins (Note 1) . . . . . .–0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . . 200 mA
Voltage with Respect to Ground
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot VSS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 8, on page 34. During voltage transitions,
input or I/O pins may overshoot to VCC +2.0 V for periods
up to 20 ns. See Figure 9, on page 34.
20 ns
20 ns
+0.8 V
V
SS–0.5 V
VSS–2.0 V
2. Minimum DC input voltage on pins A9, OE#, RESET#,
and WP#/ACC is –0.5 V. During voltage transitions, A9,
OE#, WP#/ACC, and RESET# may overshoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 8, on page
34. Maximum DC input voltage on pin A9 is +12.5 V
which may overshoot to +14.0 V for periods up to 20 ns.
Maximum DC input voltage on WP#/ACC is +9.5 V which
may overshoot to +12.0 V for periods up to 20 ns.
20 ns
Figure 8. Maximum Negative
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
20 ns
VCC+2.0 V
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
V
CC+0.5 V
2.0 V
20 ns
20 ns
Figure 9. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
V
CC for all devices . . . . . . . . . . . . . . . . .2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
34
Am29LV320D
December 14, 2005
D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
IN = VSS to VCC
VCC = VCC max
Min
Typ
Max
Unit
V
,
ILI
Input Load Current
±3.0
µA
ILIT
ILR
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
35
35
µA
µA
RESET# Input Load Current
VCC = VCC max; RESET# = 12.5 V
V
OUT = VSS to VCC
,
ILO
Output Leakage Current
±1.0
µA
VCC = VCC max
5 MHz
1 MHz
5 MHz
1 MHz
10
2
16
4
CE# = VIL, OE# = VIH,
Byte Mode
VCC Active Read Current
(Notes 1, 2)
ICC1
mA
10
2
16
4
CE# = VIL, OE# = VIH,
Word Mode
ICC2
ICC3
ICC4
VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL
15
0.2
0.2
30
5
mA
µA
µA
VCC Standby Current (Note 2)
VCC Reset Current (Note 2)
CE#, RESET# = VCC ± 0.3 V
RESET# = VSS ± 0.3 V
5
V
IH = VCC ± 0.3 V;
ICC5
Automatic Sleep Mode (Notes 2, 4)
0.2
5
µA
VIL = VSS ± 0.3 V
VIL
VIH
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
0.7 x VCC
VCC + 0.3
Voltage for WP#/ACC Sector
Protect/Unprotect and Program
Acceleration
VHH
VCC = 3.0 V 10%
11.5
11.5
12.5
V
V
Voltage for Autoselect and Temporary
Sector Unprotect
VID
VCC = 3.0 V ± 10%
12.5
0.45
VOL
VOH1
VOH2
VLKO
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
IOH = –2.0 mA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
V
V
0.85 VCC
VCC–0.4
2.3
Output High Voltage
Low VCC Lock-Out Voltage (Note 5)
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
5. Not 100% tested.
December 14, 2005
Am29LV320D
35
D A T A S H E E T
DC CHARACTERISTICS
Zero-Power Flash
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
10
8
3.6 V
2.7 V
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 11. Typical ICC1 vs. Frequency
36
Am29LV320D
December 14, 2005
D A T A S H E E T
TEST CONDITIONS
Table 16. Test Specifications
3.3 V
Test Condition
Output Load
90
120
Unit
1 TTL gate
2.7 kΩ
Device
Under
Test
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
Input Rise and Fall Times
Input Pulse Levels
5
0.0–3.0
ns
V
C
L
6.2 kΩ
Input timing measurement
reference levels
1.5
1.5
V
V
Output timing measurement
reference levels
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
Key To Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
3.0 V
0.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
Figure 13. Input Waveforms and Measurement Levels
December 14, 2005
Am29LV320D
37
D A T A S H E E T
AC CHARACTERISTICS
Read-Only Operations
Parameter
Speed Options
JEDEC
tAVAV
Std. Description
Test Setup
90
90
90
90
40
120
120
120
120
50
Unit
ns
tRC
tACC
tCE
tOE
tDF
Read Cycle Time (Note 1)
Min
Max
Max
Max
Max
Max
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
Address to Output Delay
CE#, OE# = VIL
OE# = VIL
ns
Chip Enable to Output Delay
ns
Output Enable to Output Delay
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
ns
16
16
ns
tDF
ns
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
tAXQX
tOH
Min
Min
Min
0
0
ns
ns
ns
Read
Output Enable Hold
Time (Note 1)
tOEH
Toggle and
10
Data# Polling
Notes:
1. Not 100% tested.
2. See Figure 12, on page 37 and Table 16 on page 37 for test
specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 14. Read Operation Timings
38
Am29LV320D
December 14, 2005
D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
tReady
Max
Max
20
µs
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
tReady
500
ns
tRP
tRH
tRPD
tRB
RESET# Pulse Width
Min
Min
Min
Min
500
50
20
0
ns
ns
µs
ns
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Note: Not 100% tested.
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
t
RH
tRP
Figure 15. Reset Timings
December 14, 2005
Am29LV320D
39
D A T A S H E E T
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std.
tELFL/ ELFH
tFLQZ
Description
90
120
Unit
ns
t
CE# to BYTE# Switching Low or High
BYTE# Switching Low to Output HIGH Z
BYTE# Switching High to Output Active
Max
Max
Min
5
16
ns
tFHQV
90
120
ns
CE#
OE#
BYTE#
tELFL
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
BYTE#
DQ0–DQ14
Switching
from word
to byte
Address
Input
DQ15
Output
mode
DQ15/A-1
BYTE#
tFLQZ
tELFH
BYTE#
Switching
from byte
to word
Data Output
(DQ0–DQ7)
Data Output
(DQ0–DQ14)
DQ0–DQ14
DQ15/A-1
mode
Address
Input
DQ15
Output
tFHQV
Figure 16. BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS
)
tHOLD (tAH
)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 17. BYTE# Timings for Write Operations
40
Am29LV320D
December 14, 2005
D A T A S H E E T
AC CHARACTERISTICS
Erase and Program Operations
Parameter
JEDEC
tAVAV
Std.
tWC
tAS
Description
90
120
Unit
ns
Write Cycle Time (Note 1)
Min
Min
Min
Min
90
120
tAVWL
Address Setup Time
0
ns
tASO
tAH
Address Setup Time to OE# low during toggle bit polling
Address Hold Time
15
ns
tWLAX
45
45
50
50
ns
Address Hold Time From CE# or OE# high
during toggle bit polling
tAHT
Min
0
ns
tDVWH
tWHDX
tDS
tDH
Data Setup Time
Min
Min
Min
ns
ns
ns
Data Hold Time
0
tOEPH
Output Enable High during toggle bit polling
20
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHWL
tGHWL
Min
0
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
CE# Setup Time
Min
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
ns
CE# Hold Time
tWP
Write Pulse Width
35
50
tWPH
tSR/W
Write Pulse Width High
Latency Between Read and Write Operations
Byte
30
0
9
tWHWH1
tWHWH1 Programming Operation (Note 2)
µs
µs
Word
11
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
tWHWH1
Typ
7
tWHWH2 Sector Erase Operation (Note 2)
Typ
Min
Min
Max
0.7
50
0
sec
µs
tVCS
tRB
VCC Setup Time (Note 1)
Write Recovery Time from RY/BY#
Program/Erase Valid to RY/BY# Delay
ns
tBUSY
90
ns
Notes:
1. Not 100% tested.
2. See “Erase And Programming Performance” on page 50 for more information.
December 14, 2005
Am29LV320D
41
D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
OE#
tCH
tWHWH1
tWP
WE#
Data
tWPH
tCS
tDS
tDH
PD
DOUT
A0h
Status
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 18. Program Operation Timings
42
Am29LV320D
December 14, 2005
D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data
VA
tAS
SA
tWC
VA
Addresses
CE#
2AAh
555h for chip erase
tAH
tCH
OE#
tWP
WE#
tWPH
tWHWH2
tCS
tDS
tDH
In
Data
Complete
55h
30h
Progress
10 for Chip Erase
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status” on
page 30).
2. These waveforms are for the word mode.
Figure 19. Chip/Sector Erase Operation Timings
December 14, 2005
Am29LV320D
43
D A T A S H E E T
AC CHARACTERISTICS
tRC
VA
Addresses
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Valid Data
Complement
Complement
Status Data
True
DQ0–DQ6
Valid Data
Status Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 20. Data# Polling Timings (During Embedded Algorithms)
44
Am29LV320D
December 14, 2005
D A T A S H E E T
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
WE#
tCEPH
tOEPH
OE#
tDH
Valid Data
tOE
Valid
Status
Valid
Status
Valid
Status
DQ6/DQ2
Valid Data
(first read)
(second read)
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle
Figure 21. Toggle Bit Timings (During Embedded Algorithms)
Enter
Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase
Complete
WE#
Erase
Erase Suspend
Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 22. DQ2 vs. DQ6
December 14, 2005
Am29LV320D
45
D A T A S H E E T
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std.
tVIDR
tVHH
Description
All Speed Options
Unit
ns
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
Min
Min
500
250
ns
RESET# Setup Time for Temporary Sector
Unprotect
tRSP
Min
Min
4
4
µs
µs
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
tRRB
Note: Not 100% tested.
VID
VID
RESET#
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 23. Temporary Sector Unprotect Timing Diagram
VHH
VIL or VIH
VIL or VIH
WP#/ACC
tVHH
tVHH
Figure 24. Accelerated Program Timing Diagram
46
Am29LV320D
December 14, 2005
D A T A S H E E T
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Valid*
Status
Sector/Sector Block Protect or Unprotect
60h 60h
Verify
40h
Data
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 25. Sector/Sector Block Protect and
Unprotect Timing Diagram
December 14, 2005
Am29LV320D
47
D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
JEDEC
tAVAV
Std.
tWC
tAS
Description
90
120
Unit
ns
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
90
120
tAVWL
tELAX
tDVEH
tEHDX
0
ns
tAH
45
45
50
50
ns
tDS
ns
tDH
0
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
tGHEL
tGHEL
Min
ns
tWLEL
tEHWH
tELEH
tEHEL
tWS
tWH
tCP
WE# Setup Time
WE# Hold Time
Min
Min
Min
Min
Typ
Typ
0
0
ns
ns
ns
ns
CE# Pulse Width
CE# Pulse Width High
45
50
tCPH
30
9
Byte
Programming Operation
(Note 2)
tWHWH1
tWHWH1
µs
Word
11
Accelerated Programming Operation,
Word or Byte (Note 2)
tWHWH1
tWHWH2
Notes:
tWHWH1
Typ
Typ
7
µs
tWHWH2 Sector Erase Operation (Note 2)
0.7
sec
1. Not 100% tested.
2. See “Erase And Programming Performance” on page 50 for more information.
48
Am29LV320D
December 14, 2005
D A T A S H E E T
AC CHARACTERISTICS
555 for program
PA for program
2AA for erase
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tWH
tAS
tAH
WE#
OE#
tGHEL
tWHWH1 or 2
tCP
CE#
Data
tWS
tCPH
tDS
tBUSY
tDH
DQ7#
DOUT
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings
December 14, 2005
Am29LV320D
49
D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
sec
sec
µs
Comments
Sector Erase Time
0.7
50
9
15
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
Byte Program Time
Word Program Time
Accelerated Byte/Word Program Time
300
360
210
108
72
11
7
µs
Excludes system level
overhead (Note 5)
µs
Byte Mode
36
24
Chip Program Time
(Note 3)
sec
Word Mode
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V,
4. In the pre-programming step of the Embedded Erase
algorithm, all bytes are programmed to 00h before erasure.
1,000,000 cycles.
3. The typical chip programming time is considerably less than
the maximum chip programming time listed, since most
bytes program faster than the maximum program times
listed.
5. System-level overhead is the time required to execute the
two- or four-bus-cycle sequence for the program command.
See Table 14 on page 29 for further information on
command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
+100 mA
V
CC Current
–100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
TSOP AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
Typ
6
Max
7.5
5.0
12
Unit
pF
pF
pF
pF
pF
pF
TSOP
CIN
Input Capacitance
VIN = 0
VOUT = 0
VIN = 0
Fine-pitch BGA
TSOP
4.2
8.5
5.4
7.5
3.9
COUT
Output Capacitance
Fine-pitch BGA
TSOP
6.5
9
CIN2
Control Pin Capacitance
Fine-pitch BGA
4.7
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
125°C
20
50
Am29LV320D
December 14, 2005
D A T A S H E E T
PHYSICAL DIMENSIONS
FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)
6 x 12 mm package
Dwg rev AF; 1/2000
xFBD 048
6.00 mm x 12.00 mm
PACKAGE
1.20
0.20
0.84
12.00 BSC
0.94
6.00 BSC
5.60 BSC
4.00 BSC
8
6
48
0.25 0.30
0.35
0.80 BSC
0.40 BSC
December 14, 2005
Am29LV320D
51
D A T A S H E E T
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
52
Am29LV320D
December 14, 2005
D A T A S H E E T
REVISION SUMMARY
Revision A (November 1, 2000)
Initial release.
Erase and Program Operations table
Corrected to indicate tBUSY specification is a maximum
value.
Revision A+1 (January 23, 2001)
Revision B+1 (July 30, 2002)
Ordering Information
Figure 3, Secured Silicon Sector Protect Verify
Corrected FBGA part number table to include bottom
boot part numbers.
Deleted fifth block in flowchart and modified text in
fourth block.
Revision A+2 (February 1, 2001)
Revision C (October 25, 2002)
Connection Diagrams
Distinctive Characteristics
Corrected FBGA ball matrix.
Changed endurance from “write” to “erase” cycles.
Revision A+3 (July 2, 2001)
Connection Diagrams
Global
Deleted ultrasonic reference and added package
types to special package handling text.
Changed data sheet status from Advance Information
to Preliminary.
Ordering Information
Table 3, Top Boot Secured Silicon Sector
Addresses
Added commercial temperature range and removed
extended temperature range.
Corrected sector block size for SA60–SA62 to 3x64.
Secured Silicon Flash Memory Region
Sector/Sector Block Protection and Unprotection
Customer Lockable subsection: Deleted reference to
alternate method of sector protection.
Noted that sectors are erased in parallel.
Secured Silicon Sector Flash Memory Region
Command Definitions
Noted changes for upcoming versions of these de-
vices: reduced Secured Silicons ector size, different
ESN location for top boot devices, and deletion of Se-
cured Silicon erase functionality. Current versions of
these devices remain unaffected.
Noted the following:
Autoselect, Secured Silicon, and CFI functions are not
available during a program or erase operation.
ACC and unlock bypass modes are not available when
the Secured Silicon Sector is enabled.
Revision B (July 12, 2002)
Writing incorrect data or commands may place the de-
vice in an unknown state. A reset command is then re-
quired.
Global
Deleted Preliminary status from document.
Ordering Information
AC Characteristics
Deleted burn-in option.
Read-only Operations; Word/Byte Configuration:
Changed tDF and tFLQZ to 16 ns for all speed options.
Table 1, Am29LV320D Device Bus Operations
DC Characteristics
In the legend, corrected VHH maximum voltage to 12.5
V.
Deleted IACC and added ILR specifications from table.
Secured Silicon Sector Flash Memory Region
TSOP, SO, and BGA Package Capacitance
Added description of Secured Silicon protection verifi-
cation.
Added BGA capacitance to table.
Revision C+1 (February 16, 2003)
Autoselect Command Sequence
Distinctive Characteristics
Clarified description of function.
Added reference to MirrorBit in Secured Silicon sec-
tion.
Table 14, Am29LV320D Command Definitions
Corrected autoselect codes for Secured Silicon Fac-
tory Protect.
Added Sector Architecture section.
Secured Silicon Flash Memory Region
Referenced MirrorBit for an example in last sentence
of first paragraph.
December 14, 2005
Am29LV320D
53
D A T A S H E E T
Command Definitions
Erase and Programming Performance
Changed the first address of the Unlock Bypass Reset
from BA to XXX.
Updated Chip Erase Time.
AC Characteristics
Erase and Programming Performance
Added tRH line to Figure 15.
Corrected the Sector Erase Time Typical to 0.7.
Erase and Program Operations
t
Revision C+2 (April 4, 2003)
Corrected Sector Erase Operation time ( WHWH2)
Distinctive Characteristics
Alternate CE# Control Erase and Program
Operations
Clarified reference to MirrorBit in Secured Silicon sec-
tion.
t
Corrected Sector Erase Operation time ( WHWH2)
Secured Silicon Sector
Command Definitions
Clarified reference of MirrorBit for an example in last
sentence of first paragraph.
Update text in Sector Erase Command Sequence
paragraph.
Revision C+3 (September 19, 2003)
Revision C+7 (July 11, 2005)
Valid Combinations
Global
Added the 90R package to table.
Added text to first page of data sheet and cover page
indicating that the Am29LV320D is now superceded by
the S29AL032D device.
Revision C+4 (April 5, 2004)
Command Definitions
Replaced all occurences of “SecSi Sector” with “Se-
cured Silicon Sector” to reflect change of terminology.
Changed first address data for Erase Suspend/Re-
sume from BA to XXX.
Common Flash Memory Interfacte (CFI)
Revision C+5 (June 4, 2004)
Added reference to application note. Deleted link to
CFI documents available on the world wide web.
Ordering Information
Added Lead-free (Pb-free) options to the temperature
ranges breakout table and valid combinations table.
Revision C+8 (December 14, 2005)
Global
Product Selector Guide
This product has been retired and is not available for
designs. For new and current designs, S29AL032D
supersedes Am29LV320D and is the factory-recom-
mended migration path. Please refer to the
S29AL032D datasheet for specifications and ordering
information. Availability of this document is retained for
reference and historical purposes only.
Added 90R voltage range.
Revision C+6 (November 15, 2004)
Global
Added Colophon. Updated Trademarks. Added refer-
ence links
Ordering Information
Added Automotive In-Cabin temperature range and
associated part numbers in the valid combination ta-
ble.
54
Am29LV320D
December 14, 2005
D A T A S H E E T
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-
tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-
templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-
thorization by the respective government entity will be required for export of those products.
Trademarks
Copyright © 2000-2005 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
December 14, 2005
Am29LV320D
55
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