AM29LV320DB90WMI_技术文档

Am29LV320D

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 23579 Revision C Amendment +6 Issue Date November 15, 2004

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29LV320D

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Minimum 1 million erase cycles guaranteed

ARCHITECTURAL ADVANTAGES

■ Secured Silicon (SecSi^TMSector)

per sector

■ 20 Year data retention at 125°C

— Reliable operation for the life of the system

— 64 Kbyte Sector Size; Replacement/substitute

devices (such as Mirrorbit™) have 256 bytes.

— Factory locked and identifiable: 16 bytes (8

words) available for secure, random factory

Electronic Serial Number; verifiable as factory

locked through autoselect function.

SOFTWARE FEATURES

■ Supports Common Flash Memory Interface

(CFI)

ExpressFlash option allows entire sector to be

available for factory-secured data

— Customer lockable: Can be programmed once

and then permanently locked after being

shipped from AMD

■ Erase Suspend/Erase Resume

— Suspends erase operations to allow

programming in non-suspended sectors

■ Data# Polling and Toggle Bits

— Provides a software method of detecting the

status of program or erase cycles

■ Zero Power Operation

— Sophisticated power management circuits

reduce power consumed during inactive

periods to nearly zero.

■ Unlock Bypass Program command

— Reduces overall programming time when

issuing multiple program command sequences

■ Package options

— 48-pin TSOP

HARDWARE FEATURES

■ Any combination of sectors can be erased

■ Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or

erase cycle completion

■ Hardware reset pin (RESET#)

— Hardware method of resetting the internal

state machine to the read mode

■ WP#/ACC input pin

— 48-ball FBGA

■ Sector Architecture

— Eight 8 Kbyte sectors

— Sixty-three 64 Kbyte sectors

■ Top or bottom boot block

■ Manufactured on 0.23 µm process

technology

■ Compatible with JEDEC standards

— Write protect (WP#) function allows protection

of two outermost boot sectors, regardless of

sector protect status

— Pinout and software compatible with

single-power-supply flash standard

— Acceleration (ACC) function provides

accelerated program times

■ Sector protection

PERFORMANCE CHARACTERISTICS

■ High performance

— Access time as fast 90 ns

— Program time: 7µs/word typical utilizing

Accelerate function

— Hardware method of locking a sector, either

in-system or using programming equipment,

to prevent any program or erase operation

within that sector

— Temporary Sector Unprotect allows changing

data in protected sectors in-system

■ Ultra low power consumption (typical

values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

Publication# 23579

Rev: C Amendment/+6

Issue Date: November 15, 2004

GENERAL DESCRIPTION

The Am29LV320D is a 32 megabit, 3.0

volt-only flash memory device, organized as

2,097,152 words of 16 bits each or 4,194,304

bytes of 8 bits each. Word mode data appears

on DQ0–DQ15; byte mode data appears on

DQ0–DQ7. The device is designed to be pro-

grammed in-system with the standard 3.0 volt

V_CCsupply, and can also be programmed in

standard EPROM programmers.

tomer code (programmed through AMD’s Ex-

pressFlash service), or both. Customer

Lockable parts may utilize the SecSi Sector as

bonus space, reading and writing like any other

flash sector, or may permanently lock their own

code there.

The device offers complete compatibility with

the JEDEC single-power-supply Flash com-

mand set standard. Commands are written to

the command register using standard micro-

processor write timings. Reading data out of

the device is similar to reading from other Flash

or EPROM devices.

The device is available with an access time of

90 or 120 ns. The devices are offered in 48-pin

TSOP and 48-ball FBGA packages. Standard

control pins—chip enable (CE#), write enable

(WE#), and output enable (OE#)—control nor-

mal read and write operations, and avoid bus

contention issues.

The host system can detect whether a program

or erase operation is complete by using the de-

vice status bits: RY/BY# pin, DQ7 (Data# Poll-

ing) and DQ6/DQ2 (toggle bits). After a

program or erase cycle is completed, the device

automatically returns to the read mode.

The device requires only a single 3.0 volt

power supply for both read and write func-

tions. Internally generated and regulated volt-

ages are provided for the program and erase

operations.

The sector erase architecture allows mem-

ory sectors to be erased and reprogrammed

without affecting the data contents of other

sectors. The device is fully erased when

shipped from the factory.

Am29LV320D Features

The SecSi^TMSector (Secured Silicon) is an

extra sector capable of being permanently

locked by AMD or customers. The SecSi Indi-

cator Bit (DQ7) is permanently set to a 1 if the

part is factory locked, and set to a 0 if cus-

tomer lockable. This way, customer lockable

parts can never be used to replace a factory

locked part. Note that the Am29LV320D has

a SecSi Sector size of 64 Kbytes. AMD de-

vices designated as replacements or sub-

stitutes, such as the Am29LV320M, have

256 bytes. This should be considered dur-

ing system design.

Hardware data protection measures include

a low V_CCdetector that automatically inhibits

write operations during power transitions. The

hardware sector protection feature disables

both program and erase operations in any com-

bination of the sectors of memory. This can be

achieved in-system or via programming equip-

ment.

The device offers two power-saving features.

When addresses are stable for a specified

amount of time, the device enters the auto-

matic sleep mode. The system can also place

the device into the standby mode. Power con-

sumption is greatly reduced in both modes.

Factory locked parts provide several options.

The SecSi Sector may store a secure, random

16 byte ESN (Electronic Serial Number), cus-

4

Am29LV320D

November 15, 2004

TABLE OF CONTENTS

Figure 4. Program Operation ......................................................... 27

Chip Erase Command Sequence ........................................... 27

Sector Erase Command Sequence ........................................27

Erase Suspend/Erase Resume Commands ...........................28

Figure 5. Erase Operation.............................................................. 28

Command Definitions ............................................................. 29

Table 14. Am29LV320D Command Definitions ............................. 29

Write Operation Status . . . . . . . . . . . . . . . . . . . . 30

DQ7: Data# Polling .................................................................30

Figure 6. Data# Polling Algorithm .................................................. 30

RY/BY#: Ready/Busy# ............................................................ 31

DQ6: Toggle Bit I ....................................................................31

Figure 7. Toggle Bit Algorithm........................................................ 31

DQ2: Toggle Bit II ................................................................... 32

Reading Toggle Bits DQ6/DQ2 ...............................................32

DQ5: Exceeded Timing Limits ................................................ 32

DQ3: Sector Erase Timer ....................................................... 32

Table 15. Write Operation Status ................................................... 33

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34

Figure 8. Maximum Negative Overshoot Waveform ...................... 34

Figure 9. Maximum Positive Overshoot Waveform........................ 34

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 34

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 10. I_CC1Current vs. Time (Showing Active and

Automatic Sleep Currents)............................................................. 36

Figure 11. Typical I_CC1vs. Frequency............................................ 36

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 12. Test Setup.................................................................... 37

Table 16. Test Specifications ......................................................... 37

Figure 13. Input Waveforms and Measurement Levels ................. 37

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 14. Read Operation Timings ............................................... 38

Figure 15. Reset Timings ............................................................... 39

Word/Byte Configuration (BYTE#) ............................................. 40

Figure 16. BYTE# Timings for Read Operations............................ 40

Figure 17. BYTE# Timings for Write Operations............................ 40

Erase and Program Operations ................................................. 41

Figure 18. Program Operation Timings.......................................... 42

Figure 19. Chip/Sector Erase Operation Timings .......................... 43

Figure 20. Data# Polling Timings (During Embedded Algorithms). 44

Figure 21. Toggle Bit Timings (During Embedded Algorithms)...... 45

Figure 22. DQ2 vs. DQ6................................................................. 45

Temporary Sector Unprotect .....................................................46

Figure 23. Temporary Sector Unprotect Timing Diagram .............. 46

Figure 24. Accelerated Program Timing Diagram.......................... 46

Figure 25. Sector/Sector Block Protect and

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 8

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11

Table 1. Am29LV320D Device Bus Operations ..............................11

Word/Byte Configuration ........................................................ 11

Requirements for Reading Array Data ...................................11

Writing Commands/Command Sequences ............................12

Accelerated Program Operation ..........................................12

Autoselect Functions ...........................................................12

Standby Mode ........................................................................ 12

Automatic Sleep Mode ...........................................................13

RESET#: Hardware Reset Pin ...............................................13

Output Disable Mode .............................................................. 13

Table 2. Top Boot Sector Addresses (Am29LV320DT) ..................13

Table 3. Top Boot SecSi^TMSector Addresses................................ 14

Table 4. Bottom Boot Sector Addresses (Am29LV320DB) .............15

Table 5. Bottom Boot SecSi^TMSector Addresses .......................... 16

Autoselect Mode ..................................................................... 16

Table 6. Autoselect Codes (High Voltage Method) ........................16

Sector/Sector Block Protection and Unprotection .................. 17

Table 7. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection .............................................................17

Table 8. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection ...........................................17

Write Protect (WP#) ................................................................18

Temporary Sector Unprotect ..................................................18

Figure 1. Temporary Sector Unprotect Operation........................... 18

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 19

SecSi^TMSector (Secured Silicon) Flash Memory Region .......20

Factory Locked: SecSi Sector Programmed

and Protected at the Factory ...............................................20

Customer Lockable: SecSi Sector NOT Programmed

or Protected at the Factory ..................................................20

Figure 3. SecSi Sector Protect Verify.............................................. 21

Hardware Data Protection ......................................................21

Low VCC Write Inhibit .........................................................21

Write Pulse “Glitch” Protection ............................................21

Logical Inhibit ......................................................................21

Power-Up Write Inhibit .........................................................21

Common Flash Memory Interface (CFI) . . . . . . .21

Table 9. CFI Query Identification String.......................................... 22

Table 10. System Interface String................................................... 22

Table 11. Device Geometry Definition ............................................ 23

Table 12. Primary Vendor-Specific Extended Query ...................... 24

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25

Reading Array Data ................................................................25

Reset Command .....................................................................25

Autoselect Command Sequence ............................................25

Table 13. Autoselect Codes ............................................................25

Enter SecSi^TMSector/Exit SecSi Sector

Unprotect Timing Diagram ............................................................. 47

Alternate CE# Controlled Erase and Program Operations ........48

Figure 26. Alternate CE# Controlled Write

(Erase/Program) Operation Timings .............................................. 49

Erase And Programming Performance . . . . . . . 50

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 50

TSOP and BGA Package Capacitance . . . . . . . . 50

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51

FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)

Command Sequence .............................................................. 26

Byte/Word Program Command Sequence ............................. 26

Unlock Bypass Command Sequence .................................. 26

6 x 12 mm package ................................................................... 51

TS 048—48-Pin Standard TSOP ...............................................52

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53

November 15, 2004

Am29LV320D

5

PRODUCT SELECTOR GUIDE

Family Part Number

Am29LV320D

90 120

Standard Voltage Range: V

90R Standard Voltage Range: V

= 2.7–3.6 V

= 3.0–3.6 V

CC

Speed Option

CC

Max Access Time (ns)

CE# Access (ns)

90

40

120

50

OE# Access (ns)

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

X-Decoder

A0–A20

6

Am29LV320D

November 15, 2004

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A9

A8

A19

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

V_SS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

48-Pin Standard

TSOP

9

A20

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

DQ12

DQ4

V_CC

WE#

RESET#

NC

WP#/ACC

RY/BY#

A18

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

V_SS

CE#

A0

A17

A7

A6

A5

A4

A3

A2

A1

November 15, 2004

Am29LV320D

7

CONNECTION DIAGRAMS

48-Ball FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

V_SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

V_CC

WE# RESET#

NC

A19

DQ5

DQ12

DQ4

A3 B3

C3

D3

E3

F3

G3

H3

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

V_SS

CE#

OE#

The package and/or data integrity may be com-

promised if the package body is exposed to

temperatures above 150°C for prolonged peri-

ods of time.

Special Package Handling Instructions

Special handling is required for Flash Memory

products in molded (TSOP, BGA) packages.

8

Am29LV320D

November 15, 2004

PIN DESCRIPTION

LOGIC SYMBOL

A0–A20

= 21 Addresses

21

DQ0–DQ14 = 15 Data Inputs/Outputs

A0–A2

16 or 8

DQ15/A-1 = DQ15 (Data Input/Output, word

mode), A-1 (LSB Address Input,

byte mode)

DQ0–DQ15

(A-1)

CE#

OE#

CE#

OE#

WE#

= Chip Enable

= Output Enable

= Write Enable

WE#

WP#/ACC

RESET#

BYTE#

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RY/BY#

RESET#

BYTE#

RY/BY#

V_CC

= Hardware Reset Pin, Active Low

= Selects 8-bit or 16-bit mode

= Ready/Busy Output

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed

options and voltage supply toler-

ances)

V_SS

NC

= Device Ground

= Pin Not Connected Internally

November 15, 2004

Am29LV320D

9

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number

(Valid Combination) is formed by a combination of the following:

Am29LV32

0D

T

90

E

C

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-free package

Commercial (0°C to +70°C)

Commercial (0°C to +70°C) with Pb-free package

Automotive In-Cabin (-40°C to +105°C)

Automotive In-Cabin (-40°C to +105°C) with Pb-free package

F

C

D

V

Y

PACKAGE TYPE

E

=

48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

WM

=

48-ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 12 mm package (FBD048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top boot sector

Bottom boot sector

DEVICE NUMBER/DESCRIPTION

Am29LV320D

32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Boot Sector Flash Memory

3.0 Volt-only Read, Program and Erase

Valid Combinations for

TSOP Packages

AM29LV320DT90R,

AM29LV320DB90R

Speed

(Ns)

V_CC

Range

Valid Combinations for FBGA Packages

Order Number

Package Marking

AM29LV320DT90,

AM29LV320DB90

L320DT90V,

L320DB90V

90

3.0– 3.6V

2.7– 3.6V

2.7 – 3,6V

WMC,W

MI,

C, I,

D, F

Am29LV320DT90,

Am29LV320DB90

EC, EI,

ED, EF

WMD,

WMF

AM29LV320DT120,

AM29LV320DB120

L320DT12V,

L320DB12V

90

AM29LV320DT120,

AM29LV320DB120

Am29LV320DT120

Am29LV320DB120

L320DT12V

L320DB12V

120

WNV

V, Y

Am29LV320DT120

Am29LV320DB120

EV, EY

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific

valid combinations and to check on newly released

combinations.

10

Am29LV320D

November 15, 2004

DEVICE BUS OPERATIONS

This section describes the requirements and

use of the device bus operations, which are ini-

tiated through the internal command register.

The command register itself does not occupy

any addressable memory location. The register

is a latch used to store the commands, along

with the address and data information needed

to execute the command. The contents of the

register serve as inputs to the internal state

machine. The state machine outputs dictate the

function of the device. Table 1 lists the device

bus operations, the inputs and control levels

they require, and the resulting output. The fol-

lowing subsections describe each of these oper-

ations in further detail.

Table 1. Am29LV320D Device Bus Operations

DQ8–DQ15

BYTE

WE RESET WP#/AC Addresses

DQ0–

DQ7

#

= V_IH

BYTE#

= V_IL

Operation

CE# OE#

#

H

L

#

H

C

(Note 2)

Read

Write

L

H

L/H

A_IN

D_OUT

DQ8–DQ14

= High-Z,

DQ15 = A-1

(Note 3)

V_HH

(Note 4) (Note 4)

Accelerated Program

Standby

L

V_CC

0.3 V

V_CC

0.3 V

X

H

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

L/H

X

High-Z

X

SA, A6 = L,

A1 = H, A0 = L

Sector Protect (Note 2)

L

H

X

L

V_ID

L/H

(Note 4)

X

Sector Unprotect

(Note 2)

SA, A6 = H,

A1 = H, A0 = L

(Note 3)

Temporary Sector

Unprotect

X

A_IN

(Note 4) (Note 4)

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 11.5–12.5 V, X = Don’t Care, SA

= Sector Address, A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A20:A0 in word mode (BYTE# = V_IH), A20:A-1 in byte mode (BYTE# = V_IL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See

“Sector/Sector Block Protection and Unprotection” on page 17.

3. If WP#/ACC = V_IL, the two outermost boot sectors remain protected. If WP#/ACC = V_IH, the two outermost boot

sector protection depends on whether they were last protected or unprotected using the method described in

“Sector/Sector Block Protection and Unprotection” on page 17. If WP#/ACC = V_HH, all sectors are unprotected.

4. D_INor D_OUTas required by command sequence, data polling, or sector protection algorithm.

tri-stated, and the DQ15 pin is used as an input

for the LSB (A-1) address function.

Word/Byte Configuration

The BYTE# pin controls whether the device

data I/O pins operate in the byte or word con-

figuration. If the BYTE# pin is set at logic ‘1’,

the device is in word configuration, DQ0–DQ15

are active and controlled by CE# and OE#.

Requirements for Reading Array Data

To read array data from the outputs, the sys-

tem must drive the CE# and OE# pins to V_IL.

CE# is the power control and selects the de-

vice. OE# is the output control and gates array

data to the output pins. WE# should remain at

V_IH. The BYTE# pin determines whether the de-

vice outputs array data in words or bytes.

If the BYTE# pin is set at logic ‘0’, the device is

in byte configuration, and only data I/O pins

DQ0–DQ7 are active and controlled by CE# and

OE#. The data I/O pins DQ8–DQ14 are

November 15, 2004

Am29LV320D

11

The internal state machine is set for reading

array data upon device power-up, or after a

hardware reset. This ensures that no spurious

alteration of the memory content occurs during

the power transition. No command is necessary

in this mode to obtain array data. Standard mi-

croprocessor read cycles that assert valid ad-

dresses on the device address inputs produce

valid data on the device data outputs. The de-

vice remains enabled for read access until the

command register contents are altered.

This function is primarily intended to allow

faster manufacturing throughput at the factory.

If the system asserts V_HHon this pin, the device

automatically enters the aforementioned Un-

lock Bypass mode, temporarily unprotects any

protected sectors, and uses the higher voltage

on the pin to reduce the time required for pro-

gram operations. The system would use a

two-cycle program command sequence as re-

quired by the Unlock Bypass mode. Removing

V_HHfrom the WP#/ACC pin returns the device

to normal operation. Note that the WP#/ACC

pin must not be at V_HHfor operations other

than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin

must not be left floating or unconnected; incon-

sistent behavior of the device may result.

See “Requirements for Reading Array Data” on

page 11 for more information. Refer to the AC

Read-Only Operations table for timing specifi-

cations and to Figure 14, on page 38 for the

timing diagram. I_CC1in the DC Characteristics

table represents the active current specification

for reading array data.

Autoselect Functions

Writing Commands/Command Sequences

If the system writes the autoselect command

sequence, the device enters the autoselect

mode. The system can then read autoselect

codes from the internal register (which is sepa-

rate from the memory array) on DQ7–DQ0.

Standard read cycle timings apply in this mode.

Refer to the “Autoselect Mode” on page 16 and

“Autoselect Command Sequence” on page 25

sections for more information.

To write a command or command sequence

(which includes programming data to the de-

vice and erasing sectors of memory), the sys-

tem must drive WE# and CE# to V_IL, and OE#

to V_IH.

For program operations, the BYTE# pin deter-

mines whether the device accepts program

data in bytes or words. Refer to “Word/Byte

Configuration” on page 11 for more informa-

tion.

I_CC6and I_CC7in the DC Characteristics table

represent the current specifications for

read-while-program and read-while-erase, re-

spectively.

The device features an Unlock Bypass mode

to facilitate faster programming. Once the de-

vice enters the Unlock Bypass mode, only two

write cycles are required to program a word or

byte, instead of four. The “Word/Byte Configu-

ration” on page 11 section contains details on

programming data to the device using both

standard and Unlock Bypass command se-

quences.

Standby Mode

When the system is not reading or writing to

the device, it can place the device in the

standby mode. In this mode, current consump-

tion is greatly reduced, and the outputs are

placed in the high impedance state, indepen-

dent of the OE# input.

An erase operation can erase one sector, multi-

ple sectors, or the entire device. Table 2, on

page 13 through Table 5, on page 16 indicate

the address space that each sector occupies. A

“sector address” is the address bits required to

uniquely select a sector.

The device enters the CMOS standby mode

when the CE# and RESET# pins are both held

at V_CC± 0.3 V. (Note that this is a more re-

stricted voltage range than V_IH.) If CE# and RE-

SET# are held at V_IH, but not within V_CC± 0.3

V, the device is in the standby mode, but the

standby current is greater. The device requires

standard access time (t_CE) for read access when

the device is in either of these standby modes,

before it is ready to read data.

I_CC2in the DC Characteristics table represents

the active current specification for the write

mode. The “AC Characteristics” on page 38 sec-

tion contains timing specification tables and

timing diagrams for write operations.

If the device is deselected during erasure or

programming, the device draws active current

until the operation is completed.

Accelerated Program Operation

The device offers accelerated program opera-

tions through the ACC function. This is one of

two functions provided by the WP#/ACC pin.

I_CC3in the DC Characteristics table represents

the standby current specification.

12

Am29LV320D

November 15, 2004

(I_CC4). If RESET# is held at V_ILbut not within

V_SS±0.3 V, the standby current is greater.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash de-

vice energy consumption. The device automati-

cally enables this mode when addresses remain

stable for t_ACC+ 30 ns. The automatic sleep

mode is independent of the CE#, WE#, and

OE# control signals. Standard address access

timings provide new data when addresses are

changed. While in sleep mode, output data is

latched and always available to the system. I_CC4

in the “DC Characteristics” on page 35 table

represents the automatic sleep mode current

specification.

The RESET# pin may be tied to the system

reset circuitry. A system reset would thus also

reset the Flash memory, enabling the system to

read the boot-up firmware from the Flash

memory.

If RESET# is asserted during a program or

erase operation, the RY/BY# pin remains a “0”

(busy) until the internal reset operation is com-

plete, which requires a time of t_READY(during

Embedded Algorithms). The system can thus

monitor RY/BY# to determine whether the

reset operation is complete. If RESET# is as-

serted when a program or erase operation is

not executing (RY/BY# pin is “1”), the reset op-

eration is completed within a time of t_READY(not

during Embedded Algorithms). The system can

read data t_RHafter the RESET# pin returns to

V_IH.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method

of resetting the device to reading array data.

When the RESET# pin is driven low for at least

a period of t_RP, the device immediately termi-

nates any operation in progress, tristates all

output pins, and ignores all read/write com-

mands for the duration of the RESET# pulse.

The device also resets the internal state ma-

chine to reading array data. The operation that

was interrupted should be reinitiated once the

device is ready to accept another command se-

quence, to ensure data integrity.

Refer to the AC Characteristics tables for RE-

SET# parameters and to Figure 15, on page 39

for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the

device is disabled. The output pins are placed in

the high impedance state.

Current is reduced for the duration of the RE-

SET# pulse. When RESET# is held at V_SS±0.3

V, the device draws CMOS standby current

Table 2. Top Boot Sector Addresses (Am29LV320DT) (Sheet 1 of 2)

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Sector

SA0

SA1

000000xxx

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

64/32

000000h–00FFFFh

010000h–01FFFFh

020000h–02FFFFh

030000h–03FFFFh

040000h–04FFFFh

050000h–05FFFFh

060000h–06FFFFh

070000h–07FFFFh

080000h–08FFFFh

090000h–09FFFFh

0A0000h–0AFFFFh

0B0000h–0BFFFFh

0C0000h–0CFFFFh

0D0000h–0DFFFFh

0E0000h–0EFFFFh

0F0000h–0FFFFFh

100000h–10FFFFh

110000h–11FFFFh

120000h–12FFFFh

000000h–07FFFh

008000h–0FFFFh

010000h–17FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

November 15, 2004

Am29LV320D

13

Table 2. Top Boot Sector Addresses (Am29LV320DT) (Sheet 2 of 2)

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Sector

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

110000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

64/32

8/4

130000h–13FFFFh

140000h–14FFFFh

150000h–15FFFFh

160000h–16FFFFh

170000h–17FFFFh

180000h–18FFFFh

190000h–19FFFFh

1A0000h–1AFFFFh

1B0000h–1BFFFFh

1C0000h–1CFFFFh

1D0000h–1DFFFFh

1E0000h–1EFFFFh

1F0000h–1FFFFFh

200000h–20FFFFh

210000h–21FFFFh

220000h–22FFFFh

230000h–23FFFFh

240000h–24FFFFh

250000h–25FFFFh

260000h–26FFFFh

270000h–27FFFFh

280000h–28FFFFh

290000h–29FFFFh

2A0000h–2AFFFFh

2B0000h–2BFFFFh

2C0000h–2CFFFFh

2D0000h–2DFFFFh

2E0000h–2EFFFFh

2F0000h–2FFFFFh

300000h–30FFFFh

310000h–31FFFFh

320000h–32FFFFh

330000h–33FFFFh

340000h–34FFFFh

350000h–35FFFFh

360000h–36FFFFh

370000h–37FFFFh

380000h–38FFFFh

390000h–39FFFFh

3A0000h–3AFFFFh

3B0000h–3BFFFFh

3C0000h–3CFFFFh

3D0000h–3DFFFFh

3E0000h–3EFFFFh

3F0000h–3F1FFFh

3F2000h–3F3FFFh

3F4000h–3F5FFFh

3F6000h–3F7FFFh

3F8000h–3F9FFFh

3FA000h–3FBFFFh

3FC000h–3FDFFFh

3FE000h–3FFFFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1F8FFFh

1F9000h–1F9FFFh

1FA000h–1FAFFFh

1FB000h–1FBFFFh

1FC000h–1FCFFFh

1FD000h–1FDFFFh

1FE000h–1FEFFFh

1FF000h–1FFFFFh

8/4

Note: The address range is A20:A-1 in byte mode (BYTE#=V_IL) or A20:A0 in word mode (BYTE#=V_IH).

Table 3. Top Boot SecSi^TMSector Addresses

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

111111xxx

64/32

3F0000h–3FFFFFh

1F8000h–1FFFFFh

14

Am29LV320D

November 15, 2004

Table 4. Bottom Boot Sector Addresses (Am29LV320DB) (Sheet 1 of 2)

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Sector

SA0

SA1

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

8/4

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

00E000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

8/4

SA2

8/4

SA3

8/4

SA4

8/4

SA5

8/4

SA6

8/4

SA7

8/4

SA8

64/32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

November 15, 2004

Am29LV320D

15

Table 4. Bottom Boot Sector Addresses (Am29LV320DB) (Sheet 2 of 2)

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

Sector

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

101110xxx

101111xxx

111000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111xxx

64/32

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Note: The address range is A20:A-1 in byte mode (BYTE#=V_IL) or A20:A0 in word mode (BYTE#=V_IH).

Table 5. Bottom Boot SecSi^TMSector Addresses

Sector Address

A20–A12

Sector Size

(Kbytes/Kwords)

(x8)

Address Range

(x16)

Address Range

000000xxx

64/32

000000h-00FFFFh

00000h-07FFFh

sector address must appear on the appropriate

highest order address bits (see Table 2, on

page 13 through Table 5, on page 16). Table 6,

on page 16 shows the remaining address bits

that are don’t care. When all necessary bits are

set as required, the programming equipment

may then read the corresponding identifier

code on DQ7–DQ0.

Autoselect Mode

The autoselect mode provides manufacturer

and device identification, and sector protection

verification, through identifier codes output on

DQ7–DQ0. This mode is primarily intended for

programming equipment to automatically

match a device to be programmed with its cor-

responding programming algorithm. However,

the autoselect codes can also be accessed

in-system through the command register.

To access the autoselect codes in-system, the

host system can issue the autoselect command

via the command register, as shown in

Table 14, on page 29. This method does not re-

quire V_ID. Refer to the “Autoselect Command

Sequence” on page 25 section for more infor-

mation.

When using programming equipment, the au-

toselect mode requires V_ID(11.5 V to 12.5 V)

on address pin A9. Address pins A6, A1, and A0

must be as shown in Table 6, on page 16. In

addition, when verifying sector protection, the

Table 6. Autoselect Codes (High Voltage Method)

DQ8 to DQ15

A20

to

A12

A11

to

A10

A8

to

A7

A5

to

A2

DQ7

to

DQ0

Description

CE# OE# WE#

A9

A6

A1

A0

BYTE# BYTE#

= V_IH

= V_IL

V_ID

Manufacturer ID: AMD

L

H

X

L

X

L

X

01h

Device ID: Am29LV320D

H

22h

F6 (T), F9h (B)

Sector Protection

Verification

01h (protected),

V_ID

L

H

SA

X

L

X

H

L

X

00h (unprotected)

99h (factory locked),

19h (not factory

locked)

SecSi^TMSector Indicator

Bit (DQ7)

H

Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector

Address, X = Don’t care.

16

Am29LV320D

November 15, 2004

Table 8. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/Sector Block Protection and

Unprotection

Sector / Sector

Block

Sector/Sector Block

Size

The hardware sector protection feature disables

both program and erase operations in any sec-

tor. The hardware sector unprotection feature

re-enables both program and erase operations

in previously protected sectors. Sector protec-

tion/unprotection can be implemented via two

methods.

A20–A12

111111XXX,

111110XXX,

111101XXX,

111100XXX

SA70-SA67

256 (4x64) Kbytes

SA66-SA63

SA62-SA59

SA58-SA55

SA54-SA51

SA50-SA47

SA46-SA43

SA42-SA39

SA38-SA35

SA34-SA31

SA30-SA27

SA26-SA23

SA22–SA19

SA18-SA15

SA14-SA11

1110XXXXX

1101XXXXX

1100XXXXX

1011XXXXX

1010XXXXX

1001XXXXX

1000XXXXX

0111XXXXX

0110XXXXX

0101XXXXX

0100XXXXX

0011XXXXX

0010XXXXX

0001XXXXX

256 (4x64) Kbytes

(Note: For the following discussion, the term

“sector” applies to both sectors and sector

blocks. A sector block consists of two or more

adjacent sectors that are protected or unpro-

tected at the same time (see Table 7, on

page 17 and Table 8, on page 17).

Table 7. Top Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector / Sector

Block

Sector/Sector Block

Size

A20–A12

000000XXX,

000001XXX,

000010XXX

000011XXX

SA0-SA3

256 (4x64) Kbytes

000011XXX,

000010XXX,

000001XXX

SA10-SA8

192 (3x64) Kbytes

SA4-SA7

0001XXXXX

0010XXXXX

0011XXXXX

0100XXXXX

0101XXXXX

0110XXXXX

0111XXXXX

1000XXXXX

1001XXXXX

1010XXXXX

1011XXXXX

1100XXXXX

1101XXXXX

1110XXXXX

256 (4x64) Kbytes

SA7

SA6

SA5

SA4

SA3

SA2

SA1

SA0

000000111

000000110

000000101

000000100

000000011

000000010

000000001

000000000

8 Kbytes

SA8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

Sector Protection and unprotection requires V_ID

on the RESET# pin only, and can be imple-

mented either in-system or via programming

equipment. Figure 2, on page 19 shows the al-

gorithms and Figure 25, on page 47 shows the

timing diagram. This method uses standard mi-

croprocessor bus cycle timing. For sector un-

protect, all unprotected sectors must first be

protected prior to the first sector unprotect

write cycle.

111100XXX,

111101XXX,

111110XXX

SA60-SA62

192 (3x64) Kbytes

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

8 Kbytes

The sector unprotect algorithm unprotects all

sectors in parallel. All previously protected sec-

tors must be individually re-protected. To

change data in protected sectors efficiently, the

temporary sector unprotect function is avail-

able. See “Temporary Sector Unprotect” on

page 18.

The alternate method intended only for pro-

gramming equipment, and requires V_IDon ad-

dress pin A9 and OE#. This method is

November 15, 2004

Am29LV320D

17

compatible with programmer routines written

for earlier 3.0 volt-only AMD flash devices. For

detailed information, contact an AMD represen-

tative.

23, on page 46 shows the timing diagrams, for

this feature.

The device is shipped with all sectors unpro-

tected. AMD offers the option of programming

and protecting sectors at its factory prior to

shipping the device through AMD’s Express-

Flash™ Service. Contact an AMD representative

for details.

START

RESET# = V_ID

(Note 1)

It is possible to determine whether a sector is

protected or unprotected. See “Autoselect

Mode” on page 16 for details.

Perform Erase or

Program

Write Protect (WP#)

RESET# = V_IH

The Write Protect function provides a hardware

method of protecting certain boot sectors with-

out using V_ID. This function is one of two pro-

vided by the WP#/ACC pin.

Temporary Sector

Unprotect Completed

(Note 2)

If the system asserts V_ILon the WP#/ACC pin,

the device disables program and erase func-

tions in the two “outermost” 8 Kbyte boot sec-

tors independently of whether those sectors

were protected or unprotected using the

method described in “Sector/Sector Block Pro-

tection and Unprotection” on page 17. The two

outermost 8 Kbyte boot sectors are the two

sectors containing the lowest addresses in a

bottom-boot-configured device, or the two sec-

tors containing the highest addresses in a

top-boot-configured device.

Notes:

1. All protected sectors unprotected (If WP#/ACC =

V_IL, outermost boot sectors remain protected).

2. All previously protected sectors are protected

once again.

Figure 1. Temporary Sector Unprotect

Operation

If the system asserts V_IHon the WP#/ACC pin,

the device reverts to whether the two outer-

most 8K Byte boot sectors were last set to be

protected or unprotected. That is, sector pro-

tection or unprotection for these two sectors

depends on whether they were last protected

or unprotected using the method described in

“Sector/Sector Block Protection and Unprotec-

tion” on page 17.

Note that the WP#/ACC pin must not be left

floating or unconnected; inconsistent behavior

of the device may result.

Temporary Sector Unprotect

This feature allows temporary unprotection of

previously protected sectors to change data

in-system. The Sector Unprotect mode is acti-

vated by setting the RESET# pin to V_ID(11.5 V

– 12.5 V). During this mode, formerly pro-

tected sectors can be programmed or erased by

selecting the sector addresses. Once V_IDis re-

moved from the RESET# pin, all the previously

protected sectors are protected again. Figure 1,

on page 18 shows the algorithm, and Figure

18

Am29LV320D

November 15, 2004

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 µs

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 2. In-System Sector Protect/Unprotect Algorithms

November 15, 2004

Am29LV320D

19

SecSi^TMSector (Secured Silicon) Flash

Memory Region

■ Customer code through the ExpressFlash

service

■ Both a random, secure ESN and customer

The Secured Silicon Sector (SecSi Sector) fea-

ture provides a Flash memory region that en-

ables permanent part identification through an

Electronic Serial Number (ESN). The SecSi Sec-

tor uses a SecSi Sector Indicator Bit (DQ7) to

indicate whether or not the SecSi Sector is

locked when shipped from the factory. This bit

is permanently set at the factory and cannot be

changed, which prevents cloning of a factory

locked part. This ensures the security of the

ESN once the product is shipped to the field.

Note that the Am29LV320D has a SecSi

Sector size of 64 Kbytes. AMD devices des-

ignated as replacements or substitutes,

such as the Am29LV320M, have 256 bytes.

This should be considered during system

design.

code through the ExpressFlash service.

In devices that have an ESN, a Bottom Boot de-

vice has the 16-byte (8-word) ESN in sector 0

at addresses 00000h–0000Fh in byte mode (or

00000h–00007h in word mode). In the Top

Boot device the ESN is in sector 63 at ad-

dresses 3F0000h–3F000Fh in byte mode (or

1F8000h–1F8007h in word mode). Note that in

upcoming top boot versions of this device, the

ESN is located in sector 70 at addresses

3FE000h–3FE00Fh in byte mode (or

1FF000h–1FF007h in word mode).

Customers may opt to have their code pro-

grammed by AMD through the AMD Express-

Flash service. AMD programs the customer’s

code, with or without the random ESN. The de-

vices are then shipped from AMD’s factory with

the SecSi Sector permanently locked. Contact

an AMD representative for details on using

AMD’s ExpressFlash service.

AMD offers the device with the SecSi Sector ei-

ther factory locked or customer lockable. The

factory-locked version is always protected

when shipped from the factory, and has the

SecSi Sector Indicator Bit permanently set to a

“1.” The customer-lockable version is shipped

with the SecSi Sector unprotected, allowing

customers to utilize the that sector in any man-

ner they choose. The customer-lockable ver-

sion has the SecSi Sector Indicator Bit

permanently set to a “0.” Thus, the SecSi Sec-

tor Indicator Bit prevents customer-lockable

devices from being used to replace devices that

are factory locked.

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the Factory

The customer lockable version allows the SecSi

Sector to be programmed once and then per-

manently locked after it ships from AMD. Note

that the Am29LV320D has a SecSi Sector

size of 64 Kbytes. AMD devices designated

as replacements or substitutes, such as

the Am29LV320M, have 256 bytes. This

should be considered during system de-

sign. Additionally, note the change in the

location of the ESN in upcoming top boot

factory locked devices. Note that the accel-

erated programming (ACC) and unlock bypass

functions are not available when programming

the SecSi Sector.

The system accesses the SecSi Sector through

a command sequence (see “Enter SecSi^TMSec-

tor/Exit SecSi Sector Command Sequence” on

page 26). After the system writes the Enter

SecSi Sector command sequence, it may read

the SecSi Sector by using the addresses nor-

mally occupied by the boot sectors. This mode

of operation continues until the system issues

the Exit SecSi Sector command sequence, or

until power is removed from the device. On

power-up, or following a hardware reset, the

device reverts to sending commands to the

boot sectors.

The SecSi Sector area can be protected using

the following procedures:

■ Write the three-cycle Enter SecSi Region

command sequence, and then follow the

in-system sector protect algorithm as shown

in Figure 2, on page 19, except that RESET#

may be at either V_IHor V_ID. This allows

in-system protection of the SecSi Sector

without raising any device pin to a high volt-

age. Note that this method is only applicable

to the SecSi Sector.

Factory Locked: SecSi Sector Programmed

and Protected at the Factory

In a factory locked device, the SecSi Sector is

protected when the device is shipped from the

factory. The SecSi Sector cannot be modified in

any way. The device is available prepro-

grammed with one of the following:

■ To verify the protect/unprotect status of the

SecSi Sector, follow the algorithm shown in

Figure 3, on page 21.

■ A random, secure ESN only

20

Am29LV320D

November 15, 2004

Once the SecSi Sector is locked and verified,

the system must write the Exit SecSi Sector

Region command sequence to return to reading

and writing the remainder of the array.

until V_CCis greater than V_LKO. The system must

provide the proper signals to the control pins to

prevent unintentional writes when V_CCis

greater than V_LKO

.

The SecSi Sector protection must be used with

caution since, once protected, there is no pro-

cedure available for unprotecting the SecSi

Sector area and none of the bits in the SecSi

Sector memory space can be modified in any

way.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#,

CE# or WE# do not initiate a write cycle.

Logical Inhibit

Write cycles are inhibited by holding any one of

OE# = V_IL, CE# = V_IHor WE# = V_IH. To initiate

a write cycle, CE# and WE# must be a logical

zero while OE# is a logical one.

START

Power-Up Write Inhibit

If data = 00h,

RESET# =

If WE# = CE# = V_ILand OE# = V_IHduring

power up, the device does not accept com-

mands on the rising edge of WE#. The internal

state machine is automatically reset to the read

mode on power-up.

SecSi Sector is

V_IHor V_ID

unprotected.

If data = 01h,

SecSi Sector is

protected.

Wait 1 µs

Write 60h to

any address

COMMON FLASH MEMORY

INTERFACE (CFI)

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

command

A1 = 1, A0 = 0

The Common Flash Interface (CFI) specification

outlines device and host system software inter-

rogation handshake, which allows specific ven-

dor-specified software algorithms to be used

for entire families of devices. Software support

can then be device-independent, JEDEC ID-in-

dependent, and forward- and backward-com-

patible for the specified flash device families.

Flash vendors can standardize their existing in-

terfaces for long-term compatibility.

Write reset

SecSi Sector

Read from SecSi

Protect Verify

Sector address

complete

with A6 = 0,

A1 = 1, A0 = 0

This device enters the CFI Query mode when

the system writes the CFI Query command,

98h, to address 55h in word mode (or address

AAh in byte mode), any time the device is

ready to read array data. The system can read

CFI information at the addresses given in

Table 9, on page 22 through Table 12, on

page 24. To terminate reading CFI data, the

system must write the reset command.

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock

cycles for programming or erasing provides

data protection against inadvertent writes (re-

fer to Table 14, on page 29 for command defi-

nitions). In addition, the following hardware

data protection measures prevent accidental

erasure or programming, which might other-

wise be caused by spurious system level signals

during V_CCpower-up and power-down transi-

tions, or from system noise.

The system can also write the CFI query com-

mand when the device is in the autoselect

mode. The device enters the CFI query mode,

and the system can read CFI data at the ad-

dresses given in Table 9, on page 22 through

Table 12, on page 24. The system must write

the reset command to return the device to the

reading array data.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not

accept any write cycles. This protects data dur-

ing V_CCpower-up and power-down. The com-

mand register and all internal program/erase

circuits are disabled, and the device resets to

the read mode. Subsequent writes are ignored

For further information, please refer to the CFI

Specification and CFI Publication 100, available

via

the

World

Wide

Web

at

http://www.amd.com/flash/cfi. Alternatively,

contact an AMD representative for copies of

these documents.

November 15, 2004

Am29LV320D

21

Table 9. CFI Query Identification String

Addresses

(Word Mode) (Byte Mode)

Data

Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

26h

28h

0002h

0000h

Primary OEM Command Set

15h

16h

2Ah

2Ch

0040h

0000h

Address for Primary Extended Table

17h

18h

2Eh

30h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

32h

34h

0000h

Table 10. System Interface String

Addresses

(Word Mode) (Byte Mode)

Data

Description

V_CCMin. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Bh

1Ch

36h

38h

0027h

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

3Ah

3Ch

3Eh

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

0004h

0000h

000Ah

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

22

Am29LV320D

November 15, 2004

Table 11. Device Geometry Definition

Addresses

(Word Mode) (Byte Mode)

Data

Description

27h

4Eh

0016h

Device Size = 2^Nbyte

28h

29h

50h

52h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

54h

56h

0000h

Max. number of bytes in multi-byte write = 2^N

(00h = not supported)

2Ch

58h

0002h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

003Eh

0000h

0001h

Erase Block Region 2 Information

Erase Block Region 3 Information

Erase Block Region 4 Information

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

November 15, 2004

Am29LV320D

23

Table 12. Primary Vendor-Specific Extended Query

Addresses

(Word Mode) (Byte Mode)

Data

Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

86h

88h

0031h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

8Ah

0000h

Silicon Revision Number (Bits 7-2)

Erase Suspend

46h

47h

48h

49h

4Ah

4Bh

4Ch

4Dh

8Ch

8Eh

90h

92h

94h

96h

98h

9Ah

0002h

0004h

0001h

0004h

0000h

00B5h

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

4Eh

4Fh

9Ch

9Eh

00C5h

000Xh

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

02h = Bottom Boot Device, 03h = Top Boot Device

24

Am29LV320D

November 15, 2004

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates

device operations. Table 14, on page 29 defines

the valid register command sequences. Note

that writing incorrect address and data values

or writing them in the improper sequence may

place the device in an unknown state. A reset

command is required to return the device to

normal operation.

quence before programming begins. This resets

the device to which the system was writing to

the read mode. If the program command se-

quence is written to a sector that is in the Erase

Suspend mode, writing the reset command re-

turns the device to the erase-suspend-read

mode. Once programming begins, however, the

device ignores reset commands until the opera-

tion is complete.

All addresses are latched on the falling edge of

WE# or CE#, whichever happens later. All data

is latched on the rising edge of WE# or CE#,

whichever happens first. Refer to the AC Char-

acteristics section for timing diagrams.

The reset command may be written between

the sequence cycles in an autoselect command

sequence. Once in the autoselect mode, the

reset command must be written to return to

the read mode. If the device entered the au-

toselect mode while in the Erase Suspend

mode, writing the reset command returns the

device to the erase-suspend-read mode.

Reading Array Data

The device is automatically set to reading array

data after device power-up. No commands are

required to retrieve data. The device is ready to

read array data after completing an Embedded

Program or Embedded Erase algorithm.

If DQ5 goes high during a program or erase op-

eration, writing the reset command returns the

device to the read mode (or erase-sus-

pend-read mode if the device was in Erase Sus-

pend).

After the device accepts an Erase Suspend

command, the device enters the erase-sus-

pend-read mode, after which the system can

read data from any non-erase-suspended sec-

tor. After completing a programming operation

in the Erase Suspend mode, the system may

once again read array data with the same ex-

ception. See “Erase Suspend/Erase Resume

Commands” on page 28 for more information.

Autoselect Command Sequence

The autoselect command sequence allows the

host system to read several identifier codes at

specific addresses:

Table 13. Autoselect Codes

Identifier Code

Manufacturer ID

Address

00h

The system must issue the reset command to

return the device to the read (or erase-sus-

pend-read) mode if DQ5 goes high during an

active program or erase operation, or if the de-

vice is in the autoselect mode. See the next

section, “Reset Command, for more informa-

tion.

Device ID

01h

SecSi Sector Factory Protect

Sector Group Protect Verify

03h

(SA)02h

Table 14, on page 29 shows the address and

data requirements. This method is an alterna-

tive to that shown in Table 6, on page 16,

which is intended for PROM programmers and

requires V_IDon address pin A9. The autoselect

command sequence may be written to an ad-

dress within sector that is either in the read or

erase-suspend-read mode. The autoselect

command may not be written while the device

is actively programming or erasing.

See also “Requirements for Reading Array

Data” on page 11 for more information. The

Read-Only Operations table provides the read

parameters, and Figure 14, on page 38 shows

the timing diagram.

Reset Command

Writing the reset command resets the device to

the read or erase-suspend-read mode. Address

bits are don’t cares for this command.

The autoselect command sequence is initiated

by first writing two unlock cycles. This is fol-

lowed by a third write cycle that contains the

autoselect command. The device then enters

the autoselect mode. The system may read at

any address any number of times without initi-

ating another autoselect command sequence.

The reset command may be written between

the sequence cycles in an erase command se-

quence before erasing begins. This resets the

device to which the system was writing to the

read mode. Once erasure begins, however, the

device ignores reset commands until the opera-

tion is complete.

The system must write the reset command to

return to the read mode (or erase-sus-

pend-read mode if the device was previously in

Erase Suspend).

The reset command may be written between

the sequence cycles in a program command se-

November 15, 2004

Am29LV320D

25

Enter SecSi^TMSector/Exit SecSi Sector

Command Sequence

tempting to do so may cause the device to set

DQ5 = 1, or cause the DQ7 and DQ6 status bits

to indicate the operation was successful. How-

ever, a succeeding read shows that the data is

still “0.” Only erase operations can convert a

“0” to a “1.”

The SecSi Sector region provides a secured

data area containing a random, sixteen-byte

electronic serial number (ESN). The system can

access the SecSi Sector region by issuing the

three-cycle Enter SecSi Sector command se-

quence. The device continues to access the

SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command se-

quence. The Exit SecSi Sector command se-

quence returns the device to normal operation.

Table 14, on page 29 shows the address and

data requirements for both command se-

quences. Note that the ACC function and unlock

bypass modes are not available when the de-

vice enters the SecSi Sector. See also “SecSi^TM

Sector (Secured Silicon) Flash Memory Region”

on page 20 for further information.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to

program bytes or words to the device faster

than using the standard program command se-

quence. The unlock bypass command sequence

is initiated by first writing two unlock cycles.

This is followed by a third write cycle containing

the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cy-

cle unlock bypass program command sequence

is all that is required to program in this mode.

The first cycle in this sequence contains the un-

lock bypass program command, A0h; the sec-

ond cycle contains the program address and

data. Additional data is programmed in the

same manner. This mode dispenses with the

initial two unlock cycles required in the stan-

dard program command sequence, resulting in

faster total programming time. Table 14, on

page 29 shows the requirements for the com-

mand sequence.

Byte/Word Program Command Sequence

The system may program the device by word or

byte, depending on the state of the BYTE# pin.

Programming is a four-bus-cycle operation. The

program command sequence is initiated by

writing two unlock write cycles, followed by the

program set-up command. The program ad-

dress and data are written next, which in turn

initiate the Embedded Program algorithm. The

system is not required to provide further con-

trols or timings. The device automatically pro-

vides internally generated program pulses and

verifies the programmed cell margin. Table 14,

on page 29 shows the address and data re-

quirements for the byte program command se-

quence. Note that the autoselect, SecSi Sector,

and CFI modes are unavailable while a pro-

gramming operation is in progress.

During the unlock bypass mode, only the Un-

lock Bypass Program and Unlock Bypass Reset

commands are valid. To exit the unlock bypass

mode, the system must issue the two-cycle un-

lock bypass reset command sequence. The first

cycle must contain the data 90h. The second

cycle need only contain the data 00h. The de-

vice then re turns to the read mode.

The device offers accelerated program opera-

tions through the WP#/ACC pin. When the sys-

tem asserts V_HHon the WP#/ACC pin, the

device automatically enters the Unlock Bypass

mode. The system may then write the two-cy-

cle Unlock Bypass program command se-

quence. The device uses the higher voltage on

the WP#/ACC pin to accelerate the operation.

Note that the WP#/ACC pin must not be at V_HH

any operation other than accelerated program-

ming, or device damage may result. In addi-

tion, the WP#/ACC pin must not be left floating

or unconnected; inconsistent behavior of the

device may result.

When the Embedded Program algorithm is

complete, the device then returns to the read

mode and addresses are no longer latched. The

system can determine the status of the pro-

gram operation by using DQ7, DQ6, or RY/BY#.

Refer to “Write Operation Status” on page 30

for information on these status bits.

Any commands written to the device during the

Embedded Program Algorithm are ignored.

Note that a hardware reset immediately ter-

minates the program operation. The program

command sequence should be reinitiated once

the device returns to the read mode, to ensure

data integrity.

Figure 4, on page 27 illustrates the algorithm

for the program operation. Refer to the table

“Erase and Program Operations” on page 41 for

parameters, and Figure 18, on page 42 for tim-

ing diagrams.

Programming is allowed in any sequence and

across sector boundaries. A bit cannot be

programmed from “0” back to a “1.” At-

26

Am29LV320D

November 15, 2004

When the Embedded Erase algorithm is com-

plete, the device returns to the read mode and

addresses are no longer latched. The system

can determine the status of the erase operation

by using DQ7, DQ6, DQ2, or RY/BY#. Refer to

“Write Operation Status” on page 30 for infor-

mation on these status bits.

START

Write Program

Any commands written during the chip erase

operation are ignored. However, note that a

hardware reset immediately terminates the

erase operation. If that occurs, the chip erase

command sequence should be reinitiated once

the device returns to reading array data, to en-

sure data integrity.

Command Sequence

Data Poll

from System

Embedded

Program

algorithm

in progress

Figure 5, on page 28 illustrates the algorithm

for the erase operation. Refer to table “Erase

and Program Operations” on page 41 for pa-

rameters, and Figure 19, on page 43 section for

timing diagrams.

Verify Data?

Yes

No

Sector Erase Command Sequence

No

Increment Address

Last Address?

Yes

Sector erase is a six bus cycle operation. The

sector erase command sequence is initiated by

writing two unlock cycles, followed by a set-up

command. Two additional unlock cycles are

written, and are then followed by the address

of the sector to be erased, and the sector erase

command. Table 14, on page 29 shows the ad-

dress and data requirements for the sector

erase command sequence. Note that the au-

toselect, SecSi Sector, and CFI modes are un-

available while an erase operation is in

progress.

Programming

Completed

Note: See Table 14, on page 29 for program

command sequence.

Figure 4. Program Operation

The device does not require the system to pre-

program prior to erase. The Embedded Erase

algorithm automatically programs and verifies

the entire memory for an all zero data pattern

prior to electrical erase. The system is not re-

quired to provide any controls or timings during

these operations.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip

erase command sequence is initiated by writing

two unlock cycles, followed by a set-up com-

mand. Two additional unlock write cycles are

then followed by the chip erase command,

which in turn invokes the Embedded Erase al-

gorithm. The device does not require the sys-

tem to preprogram prior to erase. The

Embedded Erase algorithm automatically pre-

programs and verifies the entire memory for an

all zero data pattern prior to electrical erase.

The system is not required to provide any con-

trols or timings during these operations.

Table 14, on page 29 shows the address and

data requirements for the chip erase command

sequence. Note that the autoselect, SecSi Sec-

tor, and CFI modes are unavailable while an

erase operation is in progress.

After the command sequence is written, a sec-

tor erase time-out of 50 µs occurs. During the

time-out period, additional sector addresses

and sector erase commands may be written.

Loading the sector erase buffer may be done in

any sequence, and the number of sectors may

be from one sector to all sectors. The time be-

tween these additional cycles must be less than

50 µs, otherwise the last address and com-

mand may not be accepted, and erasure may

begin. It is recommended that processor inter-

rupts be disabled during this time to ensure all

commands are accepted. The interrupts can be

re-enabled after the last Sector Erase com-

mand is written. Any command other than

Sector Erase or Erase Suspend during the

November 15, 2004

Am29LV320D

27

time-out period resets the device to the

read mode. The system must rewrite the com-

mand sequence and any additional addresses

and commands.

pended sectors produces status information on

DQ7–DQ0. The system can use DQ7, or DQ6

and DQ2 together, to determine if a sector is

actively erasing or is erase-suspended. Refer to

the “Write Operation Status” on page 30 sec-

tion for information on these status bits.

The system can monitor DQ3 to determine if

the sector erase timer timed out (See the sec-

tion “DQ3: Sector Erase Timer” on page 32.).

The time-out begins from the rising edge of the

final WE# pulse in the command sequence.

After an erase-suspended program operation is

complete, the device returns to the erase-sus-

pend-read mode. The system can determine

the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard

Byte Program operation. Refer to “Write Opera-

tion Status” on page 30 for more information.

When the Embedded Erase algorithm is com-

plete, the device returns to reading array data

and addresses are no longer latched. The sys-

tem can determine the status of the erase op-

eration by reading DQ7, DQ6, DQ2, or RY/BY#

in the erasing sector. Refer to “Write Operation

Status” on page 30 for information on these

status bits.

In the erase-suspend-read mode, the system

can also issue the autoselect command se-

quence. Refer to “Autoselect Mode” on page 16

and “Autoselect Command Sequence” on

page 25 for details.

Once the sector erase operation begins, only

the Erase Suspend command is valid. All other

commands are ignored. However, note that a

hardware reset immediately terminates the

erase operation. If that occurs, the sector erase

command sequence should be reinitiated once

the device returns to reading array data, to en-

sure data integrity.

To resume the sector erase operation, the sys-

tem must write the Erase Resume command.

Further writes of the Resume command are ig-

nored. Another Erase Suspend command can

be written after the chip resumes erasing.

Figure 5, on page 28 illustrates the algorithm

for the erase operation. Refer to table “Erase

and Program Operations” on page 41 for pa-

rameters, and Figure 19, on page 43 for timing

diagrams.

START

Write Erase

Command Sequence

(Notes 1, 2)

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the

system to interrupt a sector erase operation

and then read data from, or program data to,

any sector not selected for erasure. This com-

mand is valid only during the sector erase oper-

ation, including the 50 µs time-out period

during the sector erase command sequence.

The Erase Suspend command is ignored if writ-

ten during the chip erase operation or Embed-

ded Program algorithm.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

When the Erase Suspend command is written

during the sector erase operation, the device

requires a maximum of 20 µs to suspend the

erase operation. However, when the Erase Sus-

pend command is written during the sector

erase time-out, the device immediately termi-

nates the time-out period and suspends the

erase operation.

Yes

Erasure Completed

Notes:

1. See Table 14, on page 29 for erase command

sequence.

After the erase operation is suspended, the de-

vice enters the erase-suspend-read mode. The

system can read data from or program data to

any sector not selected for erasure. (The device

“erase suspends” all sectors selected for era-

sure.) Reading at any address within erase-sus-

2. See the section on DQ3 for information on the

sector erase timer.

Figure 5. Erase Operation

28

Am29LV320D

November 15, 2004

Command Definitions

Table 14. Am29LV320D Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Data

Fifth

Sixth

Addr Data Addr Data

Addr Data Addr

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

RD

F0

XXX

555

AAA

555

AAA

555

Word

Manufacturer ID

Byte

2AA

555

2AA

555

2AA

555

AAA

555

AAA

555

4

AA

55

90

X00

01

Word

X01

X02

X03

(see

Table 6)

Device ID

Byte

SecSi Sector

Factory Protect

(Note 9)

Word

4

AA

55

90

99/19

00/01

Byte

AAA

555

AAA

555

2AA

555

AAA

555

AAA

X06

(SA)X0

2

Word

Byte

Sector Protect

Verify (Note 10)

(SA)X0

4

Word

Byte

Word

Byte

Word

Byte

Word

Byte

555

AAA

555

AAA

555

AAA

555

AAA

2AA

555

2AA

555

2AA

555

2AA

555

AAA

555

AAA

555

AAA

555

AAA

Enter SecSi™ Sector

Region

3

4

3

AA

55

88

90

A0

20

Exit SecSi Sector Region

Program

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note

11)

2

6

XXX

A0

90

AA

PA

PD

00

55

Unlock Bypass Reset (Note 12)

XXX

555

AAA

555

AAA

XXX

55

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

AAA

555

AAA

2AA

555

2AA

555

AAA

Chip Erase

Byte

80

AA

55

10

30

Word

Sector Erase

Byte

6

AA

55

SA

Erase Suspend (Note 13)

Erase Resume (Note 14)

1

B0

30

Word

CFI Query (Note 15)

Byte

1

98

AA

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

PD = Data to be programmed at location PA. Data latches on

the rising edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode)

or erased. Address bits A20–A12 uniquely select any sector.

Notes:

10. The data is 00h for an unprotected sector and 01h for a

protected sector.

11. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

12. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

13. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

5. Unless otherwise noted, address bits A20–A11 are don’t cares.

6. No unlock or command cycles required when device is in read

mode.

7. The Reset command is required to return to the read mode (or

to the erase-suspend-read mode if previously in Erase Suspend)

when a device is in the autoselect mode, or if DQ5 goes high

(while the device is providing status information).

8. The fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect

Command Sequence section for more information.

14. The Erase Resume command is valid only during the Erase

Suspend mode.

15. Command is valid when device is ready to read array data or

when device is in autoselect mode.

9. The data is 99h for factory locked and 19h for not factory

locked.

November 15, 2004

Am29LV320D

29

WRITE OPERATION STATUS

The device provides several bits to determine

the status of a program or erase operation:

DQ2, DQ3, DQ5, DQ6, and DQ7. Table 15, on

page 33 and the following subsections describe

the function of these bits. DQ7 and DQ6 each

offer a method for determining whether a pro-

gram or erase operation is complete or in

progress. The device also provides a hard-

ware-based output signal, RY/BY#, to deter-

mine whether an Embedded Program or Erase

operation is in progress or is completed.

when the system samples the DQ7 output, it

may read the status or valid data. Even if the

device completes the program or erase opera-

tion and DQ7 contains valid data, the data out-

puts on DQ0–DQ6 may be still invalid. Valid

data on DQ0–DQ7 appears on successive read

cycles.

Table 15, on page 33 shows the outputs for

Data# Polling on DQ7. Figure 6, on page 30

shows the Data# Polling algorithm. Figure 20,

on page 44 in the AC Characteristics section

shows the Data# Polling timing diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the

host system whether an Embedded Program or

Erase algorithm is in progress or completed, or

whether a device is in Erase Suspend. Data#

Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

START

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the

device outputs on DQ7 the complement of the

datum programmed to DQ7. This DQ7 status

also applies to programming during Erase Sus-

pend. When the Embedded Program algorithm

is complete, the device outputs the datum pro-

grammed to DQ7. The system must provide the

program address to read valid status informa-

tion on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active

for approximately 1 µs, then the device returns

to the read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data#

Polling produces a “0” on DQ7. When the Em-

bedded Erase algorithm is complete, or if the

device enters the Erase Suspend mode, Data#

Polling produces a “1” on DQ7. The system

must provide an address within any of the sec-

tors selected for erasure to read valid status in-

formation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

Yes

DQ7 = Data?

After an erase command sequence is written, if

all sectors selected for erasing are protected,

Data# Polling on DQ7 is active for approxi-

mately 100 µs, then the device returns to the

read mode. If not all selected sectors are pro-

tected, the Embedded Erase algorithm erases

the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if

the system reads DQ7 at an address within a

protected sector, the status may not be valid.

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a

sector erase operation, a valid address is any

sector address within the sector being erased.

During chip erase, a valid address is any

non-protected sector address.

Just prior to the completion of an Embedded

Program or Erase operation, DQ7 may change

asynchronously with DQ0–DQ6 while Output

Enable (OE#) is asserted low. That is, the de-

vice may change from providing status infor-

mation to valid data on DQ7. Depending on

2. DQ7 should be rechecked even if DQ5 = “1”

because DQ7 may change simultaneously with

DQ5.

Figure 6. Data# Polling Algorithm

30

Am29LV320D

November 15, 2004

DQ6 also toggles during the erase-sus-

pend-program mode, and stops toggling once

the Embedded Program algorithm is complete.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output

pin which indicates whether an Embedded Al-

gorithm is in progress or complete. The RY/BY#

status is valid after the rising edge of the final

WE# pulse in the command sequence. Since

RY/BY# is an open-drain output, several

RY/BY# pins can be tied together in parallel

with a pull-up resistor to V_CC.

Table 15, on page 33 shows the outputs for

Toggle Bit I on DQ6. Figure 7, on page 31

shows the toggle bit algorithm. Figure 21, on

page 45 in the “AC Characteristics” section

shows the toggle bit timing diagrams. Figure

22, on page 45 shows the differences between

DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

If the output is low (Busy), the device is ac-

tively erasing or programming. (This includes

programming in the Erase Suspend mode.) If

the output is high (Ready), the device is in the

read mode, the standby mode, or in the

erase-suspend-read mode. Table 15, on

page 33 shows the outputs for RY/BY#.

START

DQ6: Toggle Bit I

Read DQ7–DQ0

Toggle Bit I on DQ6 indicates whether an Em-

bedded Program or Erase algorithm is in

progress or complete, or whether the device

entered the Erase Suspend mode. Toggle Bit I

may be read at any address, and is valid after

the rising edge of the final WE# pulse in the

command sequence (prior to the program or

erase operation), and during the sector erase

time-out.

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

During an Embedded Program or Erase algo-

rithm operation, successive read cycles to any

address cause DQ6 to toggle. The system may

use either OE# or CE# to control the read cy-

cles. When the operation is complete, DQ6

stops toggling.

Yes

No

DQ5 = 1?

Yes

After an erase command sequence is written, if

all sectors selected for erasing are protected,

DQ6 toggles for approximately 100 µs, then re-

turns to reading array data. If not all selected

sectors are protected, the Embedded Erase al-

gorithm erases the unprotected sectors, and ig-

nores the selected sectors that are protected.

Read DQ7–DQ0

Twice

Toggle Bit

= Toggle?

No

The system can use DQ6 and DQ2 together to

determine whether a sector is actively erasing

or is erase-suspended. When the device is ac-

tively erasing (that is, the Embedded Erase al-

gorithm is in progress), DQ6 toggles. When the

device enters the Erase Suspend mode, DQ6

stops toggling. However, the system must also

use DQ2 to determine which sectors are eras-

ing or erase-suspended. Alternatively, the sys-

tem can use DQ7 (see the subsection on “DQ7:

Data# Polling” on page 30).

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit

even if DQ5 = “1” because the toggle bit may stop

toggling as DQ5 changes to “1.” See the subsections

on DQ6 and DQ2 for more information.

If a program address falls within a protected

sector, DQ6 toggles for approximately 1 µs

after the program command sequence is writ-

ten, then returns to reading array data.

Figure 7. Toggle Bit Algorithm

November 15, 2004

Am29LV320D

31

write the reset command to return to reading

array data.

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with

DQ6, indicates whether a particular sector is

actively erasing (that is, the Embedded Erase

algorithm is in progress), or whether that sec-

tor is erase-suspended. Toggle Bit II is valid

after the rising edge of the final WE# pulse in

the command sequence.

The remaining scenario is that the system ini-

tially determines that the toggle bit is toggling

and DQ5 has not gone high. The system may

continue to monitor the toggle bit and DQ5

through successive read cycles, determining

the status as described in the previous para-

graph. Alternatively, it may choose to perform

other system tasks. In this case, the system

must start at the beginning of the algorithm

when it returns to determine the status of the

operation (top of Figure 7, on page 31).

DQ2 toggles when the system reads at ad-

dresses within those sectors that were selected

for erasure. (The system may use either OE#

or CE# to control the read cycles.) But DQ2

cannot distinguish whether the sector is ac-

tively erasing or is erase-suspended. DQ6, by

comparison, indicates whether the device is ac-

tively erasing, or is in Erase Suspend, but can-

not distinguish which sectors are selected for

erasure. Thus, both status bits are required for

sector and mode information. Refer to Table 15,

on page 33 to compare outputs for DQ2 and

DQ6.

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase

time exceeded a specified internal pulse count

limit. Under these conditions DQ5 produces a

“1,” indicating that the program or erase cycle

was not successfully completed.

The device may output a “1” on DQ5 if the sys-

tem tries to program a “1” to a location that

was previously programmed to “0.” Only an

erase operation can change a “0” back to a

“1.” Under this condition, the device halts the

operation, and when the timing limit is ex-

ceeded, DQ5 produces a “1.”

Figure 7, on page 31 shows the toggle bit algo-

rithm in flowchart form, and the section “DQ2:

Toggle Bit II” on page 32 explains the algo-

rithm. See also the DQ6: Toggle Bit I subsec-

tion. Figure 21, on page 45 shows the toggle bit

timing diagram. Figure 22, on page 45 shows

the differences between DQ2 and DQ6 in

graphical form.

Under both these conditions, the system must

write the reset command to return to the read

mode (or to the erase-suspend-read mode if

the device was previously in the erase-sus-

pend-program mode).

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7, on page 31 for the following

discussion. Whenever the system initially be-

gins reading toggle bit status, it must read

DQ7–DQ0 at least twice in a row to determine

whether a toggle bit is toggling. Typically, the

system would note and store the value of the

toggle bit after the first read. After the second

read, the system would compare the new value

of the toggle bit with the first. If the toggle bit

is not toggling, the device completed the pro-

gram or erase operation. The system can read

array data on DQ7–DQ0 on the following read

cycle.

DQ3: Sector Erase Timer

After writing a sector erase command se-

quence, the system may read DQ3 to deter-

mine whether or not erasure started. (The

sector erase timer does not apply to the chip

erase command.) If additional sectors are se-

lected for erasure, the entire time-out also ap-

plies after each additional sector erase

command. When the time-out period is com-

plete, DQ3 switches from a “0” to a “1.” If the

time between additional sector erase com-

mands from the system can be assumed to be

less than 50 µs, the system need not monitor

DQ3. See also the Sector Erase Command Se-

quence section.

However, if after the initial two read cycles, the

system determines that the toggle bit is still

toggling, the system also should note whether

the value of DQ5 is high (see the section on

DQ5). If it is, the system should then deter-

mine again whether the toggle bit is toggling,

since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no

longer toggling, the device successfully com-

pleted the program or erase operation. If it is

still toggling, the device did not completed the

operation successfully, and the system must

After the sector erase command is written, the

system should read the status of DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure that the

device accepted the command sequence, and

then read DQ3. If DQ3 is “1,” the Embedded

Erase algorithm started; all further commands

(except Erase Suspend) are ignored until the

erase operation is complete. If DQ3 is “0,” the

32

Am29LV320D

November 15, 2004

device accepts additional sector erase com-

mands. To ensure the command is accepted,

the system software should check the status of

DQ3 prior to and following each subsequent

sector erase command. If DQ3 is high on the

second status check, the last command might

not have been accepted.

Table 15, on page 33 shows the status of DQ3

relative to the other status bits.

Table 15. Write Operation Status

DQ7

(Note

2)

DQ7#

0

DQ5

DQ2

Status

DQ6

Toggle

(Note 1) DQ3 (Note 2) RY/BY#

0

N/A

1

No toggle

Toggle

0

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-R

ead

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum

timing limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection

for further details.

November 15, 2004

Am29LV320D

33

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

V_CC(Note 1) . . . . . . . . . . –0.5 V to +4.0 V

Plastic Packages. . . . . . . . . . –65°C to +150°C

A9, OE#, RESET#,

Ambient Temperature

and WP#/ACC (Note 2). . –0.5 V to +12.5 V

with Power Applied. . . . . . . . –65°C to +125°C

All other pins (Note 1) –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3). 200 mA

Voltage with Respect to Ground

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5

V. During voltage transitions, input or I/O pins

may overshoot V_SSto –2.0 V for periods of up to

20 ns. Maximum DC voltage on input or I/O pins

is V_CC+0.5 V. See Figure 8, on page 34. During

voltage transitions, input or I/O pins may

overshoot to V_CC+2.0 V for periods up to 20 ns.

See Figure 9, on page 34.

20 ns

+0.8

V_SS–0.5

V_SS–2.0

2. Minimum DC input voltage on pins A9, OE#,

RESET#, and WP#/ACC is –0.5 V. During voltage

transitions, A9, OE#, WP#/ACC, and RESET#

may overshoot V_SSto –2.0 V for periods of up to

20 ns. See Figure 8, on page 34. Maximum DC

input voltage on pin A9 is +12.5 V which may

overshoot to +14.0 V for periods up to 20 ns.

Maximum DC input voltage on WP#/ACC is +9.5

V which may overshoot to +12.0 V for periods up

to 20 ns.

20 ns

Figure 8. Maximum Negative

Overshoot Waveform

20 ns

V_CC+2.0

3. No more than one output may be shorted to

ground at a time. Duration of the short circuit

should not be greater than one second.

V_CC+0.5

2.0 V

Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only; functional

operation of the device at these or any other

conditions above those indicated in the operational

sections of this data sheet is not implied. Exposure

of the device to absolute maximum rating conditions

for extended periods may affect device reliability.

20 ns

Figure 9. Maximum Positive

Overshoot Waveform

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A). . . . –40°C to +85°C

V_CCSupply Voltages

V_CCfor all devices . . . . . . . . . . 2.7 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

34

Am29LV320D

November 15, 2004

DC CHARACTERISTICS

CMOS Compatible

Paramet

er

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

V_IN= V_SSto V_CC

V_CC= V_{CC max}

,

I_LI

Input Load Current

3.0

µA

I_LIT

I_LR

A9 Input Load Current

V_CC= V_{CC max}; A9 = 12.5 V

35

µA

RESET# Input Load Current

V_CC= V_{CC max}; RESET# = 12.5 V

V_OUT= V_SSto V_CC

V_CC= V_{CC max}

,

I_LO

Output Leakage Current

1.0

µA

5 MHz

1 MHz

5 MHz

1 MHz

10

2

16

4

CE# = V_IL,OE# ₌V_IH

Byte Mode

,

V_CCActive Read Current

(Notes 1, 2)

I_CC1

mA

10

2

16

4

CE# = V_IL,OE# ₌V_IH

Word Mode

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Notes 2, 3) CE# = V_IL,OE# ₌V_IH, WE# = V_IL

15

0.2

30

5

mA

µA

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC0.3 V

RESET# = V_SS0.3 V

5

V_IH= V_CC0.3 V;

V_IL= V_SS0.3 V

I_CC5

Automatic Sleep Mode (Notes 2, 4)

0.2

5

µA

V_IL

Input Low Voltage

Input High Voltage

–0.5

0.8

V

V_IH

0.7 x V_CC

V_CC+ 0.3

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration

V_HH

V_CC= 3.0 V ± 10%

V_CC= 3.0 V 10%

11.5

12.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

12.5

0.45

V_OL

Output Low Voltage

I_OL= 4.0 mA, V_CC= V_{CC min}

I_OH= –2.0 mA, V_CC= V_{CC min}

I_OH= –100 µA, V_CC= V_{CC min}

V

V_OH1

V_OH2

V_LKO

0.85 V_CC

V_CC–0.4

2.3

Output High Voltage

Low V_CCLock-Out Voltage (Note 5)

2.5

V

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for t_ACC+ 30 ns. Typical sleep

mode current is 200 nA.

5. Not 100% tested.

November 15, 2004

Am29LV320D

35

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 10. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

12

3.6 V

10

2.7 V

8

6

4

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 11. Typical I_CC1vs. Frequency

36

Am29LV320D

November 15, 2004

TEST CONDITIONS

Table 16. Test Specifications

3.3 V

Test Condition

90

120

Unit

Output Load

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

100

pF

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

V

C

L

6.2 kΩ

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

Key To Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

Input

Measurement Level

Output

0.0 V

Figure 13. Input Waveforms and Measurement Levels

November 15, 2004

Am29LV320D

37

AC CHARACTERISTICS

Read-Only Operations

Speed

Parameter

Options

JEDEC

t_AVAV

Std. Description

Test Setup

90

120 Unit

t_RC

t_ACC

t_CE

Read Cycle Time (Note 1)

Min

Max

90

40

120

50

ns

t_AVQV

Address to Output Delay

CE#, OE# = V_IL

OE# = V_IL

t_ELQV

Chip Enable to Output Delay

t_GLQV

t_EHQZ

t_GHQZ

t_OE

t_DF

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

16

t_DF

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold Time

(Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 12, on page 37 and Table 16, on page 37 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 14. Read Operation Timings

38

Am29LV320D

November 15, 2004

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms) to

Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t

RH

t_RP

Figure 15. Reset Timings

November 15, 2004

Am29LV320D

39

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

JEDEC

Std.

t_ELFL/t_ELFH

t_FLQZ

Description

90

120

Unit

ns

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

5

16

ns

t_FHQV

90

120

ns

CE#

OE#

BYTE#

t_ELFL

Data Output

(DQ0–DQ14)

Data

BYTE#

DQ0–DQ14

Output

Switchin

g from

word to

byte

Address

Input

DQ15

Output

DQ15/A-1

BYTE#

mode

t_FLQZ

t_ELFH

BYTE#

Switchin

g from

byte to

word

Data

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

Output

Address

Input

DQ15

Output

mode

t_FHQ

Figure 16. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE#

WE#

BYTE#

t_SET

(t_AS)

t_HOLD(t_AH)

Note: Refer to the Erase/Program Operations table for t_ASand t_AHspecifications.

Figure 17. BYTE# Timings for Write Operations

40

Am29LV320D

November 15, 2004

AC CHARACTERISTICS

Erase and Program Operations

Parameter

JEDEC

t_AVAV

Std.

t_WC

Description

90

120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

90

120

t_AVWL

t_AS

0

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

ns

t_WLAX

45

50

ns

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

ns

Data Hold Time

0

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

0

ns

CE# Hold Time

t_WP

Write Pulse Width

35

50

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

30

0

Byte

9

t_WHWH1

Programming Operation (Note 2)

Word

µs

11

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

t_WHWH1

Typ

7

t_WHWH2

t_VCS

Sector Erase Operation (Note 2)

V_CCSetup Time (Note 1)

Typ

Min

Max

0.7

50

0

sec

µs

ns

t_RB

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

t_BUSY

90

ns

Notes:

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 50 for more information.

November 15, 2004

Am29LV320D

41

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 18. Program Operation Timings

42

Am29LV320D

November 15, 2004

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation

Status” on page 30).

2. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

November 15, 2004

Am29LV320D

43

AC CHARACTERISTICS

t_RC

VA

t_ACC

t_CE

Addresses

VA

CE#

t_CH

t_OE

OE#

t_OEH

t_DF

t_OH

WE#

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle,

and array data read cycle.

Figure 20. Data# Polling Timings (During Embedded Algorithms)

44

Am29LV320D

November 15, 2004

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command

sequence, last status read cycle, and array data read cycle

Figure 21. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE#

or CE# to toggle DQ2 and DQ6.

Figure 22. DQ2 vs. DQ6

November 15, 2004

Am29LV320D

45

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std. Description

All Speed Options

Unit

ns

t_VIDR

t_VHH

V_IDRise and Fall Time (See Note)

Min

500

250

V_HHRise and Fall Time (See Note)

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 23. Temporary Sector Unprotect Timing Diagram

V_HH

V_ILor V_IH

WP#/ACC

t_VHH

Figure 24. Accelerated Program Timing Diagram

46

Am29LV320D

November 15, 2004

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector/Sector Block Protect or Unprotect

60h 60h

Verify

40h

Data

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 25. Sector/Sector Block Protect and

Unprotect Timing Diagram

November 15, 2004

Am29LV320D

47

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

90

120

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

90

120

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

ns

t_AH

45

50

ns

t_DS

ns

t_DH

Data Hold Time

0

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

CE# Pulse Width

CE# Pulse Width High

45

50

t_CPH

30

9

Byte

Programming Operation

(Note 2)

t_WHWH1

µs

Word

11

Accelerated Programming Operation,

Word or Byte (Note 2)

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

Typ

7

µs

Sector Erase Operation (Note 2)

0.7

sec

Notes:

1. Not 100% tested.

2. See “Erase And Programming Performance” on page 50 for more information.

48

Am29LV320D

November 15, 2004

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

November 15, 2004

Am29LV320D

49

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time

0.7

50

9

15

Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time

Byte Program Time

Word Program Time

Accelerated Byte/Word Program Time

300

360

210

108

72

11

7

µs

Excludes system level

overhead (Note 5)

µs

Byte Mode

36

24

Chip Program Time

(Note 3)

sec

Word Mode

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles.

Additionally, programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since

most bytes program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before

erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program

command. See Table 14, on page 29 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

TSOP AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5.0

12

Unit

pF

TSOP

C_IN

Input Capacitance

V_IN= 0

V_OUT= 0

V_IN= 0

Fine-pitch BGA

TSOP

4.2

8.5

5.4

7.5

3.9

pF

C_OUT

Output Capacitance

Fine-pitch BGA

TSOP

6.5

9

pF

C_IN2

Control Pin Capacitance

Fine-pitch BGA

4.7

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

50

Am29LV320D

November 15, 2004

PHYSICAL DIMENSIONS

FBD048—48-ball Fine-Pitch Ball Grid Array (FBGA)

6 x 12 mm package

Dwg rev AF; 1/2000

xFBD 048

6.00 mm x 12.00 mm

PACKAGE

1.20

0.20

0.84

12.00 BSC

0.94

6.00 BSC

5.60 BSC

4.00 BSC

8

6

48

0.25 0.30

0.35

0.80 BSC

0.40 BSC

November 15, 2004

Am29LV320D

51

PHYSICAL DIMENSIONS

TS 048—48-Pin Standard TSOP

Dwg rev AA; 10/99

52

Am29LV320D

November 15, 2004

REVISION SUMMARY

Revision A (November 1, 2000)

Initial release.

Table 14, Am29LV320D Command Definitions

Corrected autoselect codes for SecSi Sector

Factory Protect.

Revision A+1 (January 23, 2001)

Erase and Program Operations table

Ordering Information

Corrected to indicate t_BUSYspecification is a

maximum value.

Corrected FBGA part number table to include

bottom boot part numbers.

Revision B+1 (July 30, 2002)

Revision A+2 (February 1, 2001)

Figure 3, SecSi Sector Protect Verify

Connection Diagrams

Deleted fifth block in flowchart and modified

text in fourth block.

Corrected FBGA ball matrix.

Revision A+3 (July 2, 2001)

Revision C (October 25, 2002)

Global

Distinctive Characteristics

Changed data sheet status from Advance Infor-

mation to Preliminary.

Table 3, Top Boot SecSi^TMSector Addresses

Changed endurance from “write” to “erase” cy-

cles.

Connection Diagrams

Corrected sector block size for SA60–SA62 to

3x64.

Deleted ultrasonic reference and added pack-

age types to special package handling text.

Sector/Sector Block Protection and

Unprotection

Ordering Information

Noted that sectors are erased in parallel.

SecSi^TMSector (Secured Silicon) Flash Memory

Region

Added commercial temperature range and re-

moved extended temperature range.

SecSi Sector Flash Memory Region

Noted changes for upcoming versions of these

devices: reduced SecSi Sector size, different

ESN location for top boot devices, and deletion

of SecSi Sector erase functionality. Current ver-

sions of these devices remain unaffected.

Customer Lockable subsection: Deleted refer-

ence to alternate method of sector protection.

Command Definitions

Noted the following:

Autoselect, SecSi Sector, and CFI functions are

not available during a program or erase opera-

tion.

Revision B (July 12, 2002)

Global

Deleted Preliminary status from document.

ACC and unlock bypass modes are not available

when the SecSi Sector is enabled.

Ordering Information

Deleted burn-in option.

Writing incorrect data or commands may place

the device in an unknown state. A reset com-

mand is then required.

Table 1, Am29LV320D Device Bus Operations

In the legend, corrected V_HHmaximum voltage

to 12.5 V.

AC Characteristics

Read-only Operations; Word/Byte Configura-

tion: Changed t_DFand t_FLQZto 16 ns for all

speed options.

SecSi^TMSector (Secured Silicon) Flash Memory

Region

Added description of SecSi Sector protection

verification.

DC Characteristics

Deleted I_ACCand added I_LRspecifications from

table.

Autoselect Command Sequence

Clarified description of function.

TSOP, SO, and BGA Package Capacitance

Added BGA capacitance to table.

November 15, 2004

Am29LV320D

53

Ordering Information

Revision C+1 (February 16, 2003)

Added Automotive In-Cabin temperature range

and associated part numbers in the valid com-

bination table.

Distinctive Characteristics

Added reference to MirrorBit in Secured Silicon

section.

Erase and Programming Performance

Added Sector Architecture section.

Updated Chip Erase Time

SecSi Sector Flash Memory Region

AC Characteristics

Referenced MirrorBit for an example in last sen-

tence of first paragraph.

Added t_RHline to Figure 15.

Erase and Program Operations

Command Definitions

Corrected Sector Erase Operation time

t

Changed the first address of the Unlock Bypass

Reset from BA to XXX.

( WHWH2)

Alternate CE# Control Erase and Program Operations

Corrected Sector Erase Operation time

Erase and Programming Performance

t

( WHWH2)

Corrected the Sector Erase Time Typical to 0.7.

Command Definitions

Revision C+2 (April 4, 2003)

Update text in Sector Erase Command Se-

quence paragraph.

Distinctive Characteristics

Clarified reference to MirrorBit in Secured Sili-

con section.

SecSi Sector Flash Memory Region

Clarified reference of MirrorBit for an example

in last sentence of first paragraph.

Revision C+3 (September 19, 2003)

Valid Combinations

Added the 90R package to table.

Revision C+4 (April 5, 2004)

Command Definitions

Changed first address data for Erase Sus-

pend/Resume from BA to XXX.

Revision C+5 (June 4, 2004)

Ordering Information

Added Lead-free (Pb-free) options to the tem-

perature ranges breakout table and valid com-

binations table.

Product Selector Guide

Added 90R voltage range.

Revision C+6 (November 15, 2004)

Global

Added Colophon

Updated Trademarks

Added reference links

54

Am29LV320D

November 15, 2004

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, includ-

ing without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, de-

veloped and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high

safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical

damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport

control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is

intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or

any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating

safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current

levels and other abnormal operating conditions. If any products described in this document represent goods or technologies

subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Adminis-

tration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will

be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective compa-

nies

.

November 15, 2004

Am29LV320D

55


型号：	AM29LV320DB90WMI
厂家：	SPANSION
描述：	32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Boot Sector Flash Memory 32兆位（ 4米×8位/ 2的M× 16位） CMOS 3.0伏只，引导扇区闪存闪存存储内存集成电路
文件：	总55页 (文件大小：887K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29LV320DB90WMI [SPANSION]

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