AM29SL400DT120WAI_技术文档

Am29SL400D

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number Am29SL400D Revision A Amendment +1 Issue Date April 13, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

ADVANCE INFORMATION

Am29SL400D

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super

Low Voltage Flash Memory

DISTINCTIVE CHARACTERISTICS

■ Single power supply operation

■ Unlock Bypass Program Command

— 1.65 to 1.95 V for read, program, and erase

operations

— Reduces overall programming time when

issuing multiple program command sequences

— Ideal for battery-powered applications

■ Manufactured on 0.23 µm process technology

■ High performance

■ Top or bottom boot block configurations

available

■ Minimum 1,000,000 erase cycle guarantee per

— Access times as fast as 90 ns

sector

■ Ultra low power consumption (typical values at

■ 20-year data retention at 125°C

5 MHz)

■ Package option

— 0.2 µA Automatic Sleep Mode current

— 0.2 µA standby mode current

— 5 mA read current

— 48-ball FBGA

■ Compatibility with JEDEC standards

— Pinout and software compatible with

single-power supply Flash

— 15 mA program/erase current

■ Flexible sector architecture

— Superior inadvertent write protection

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors (byte mode)

■ Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

— One 8 Kword, two 4 Kword, one 16 Kword, and

seven 32 Kword sectors (word mode)

— Supports full chip erase

■ Ready/Busy# pin (RY/BY#)

— Sector Protection features:

— Provides a hardware method of detecting

program or erase cycle completion

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

■ Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■ Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

Pubication Am29SL400D Revision A Amendment +1

Issue Date: April 13, 2005

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Visit www.amd.com for the latest information.

A D V A N C E I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29SL400D is an 4Mbit, 1.8 V volt-only Flash

memory organized as 524,288 bytes or 262,144 words.

The device is offered in a 48-ball FBGA package. The

word-wide data (x16) appears on DQ15–DQ0; the

byte-wide (x8) data appears on DQ7–DQ0. This device

is designed to be programmed and erased in-system

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

with a single 1.8 volt V supply. No V is required for

write or erase operations. The device can also be pro-

grammed in standard EPROM programmers.

CC

PP

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

The standard device offers access times of 90, 100,

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus contention

the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

Hardware data protection measures include a low

V

detector that automatically inhibits write opera-

CC

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of

memory. This can be achieved in-system or via pro-

gramming equipment.

The device requires only a single 1.8 volt power

supply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state-machine that con-

trols the erase and programming circuitry. Write cycles

also internally latch addresses and data needed for the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM devices.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector

simultaneously via Fowler-Nordheim tunneling. The

data is programmed using hot electron injection.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automati-

cally preprograms the array (if it is not already pro-

grammed) before executing the erase operation.

During erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

2

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Special Handling Instructions for FBGA Packages .................. 5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . .7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .8

Table 1. Am29SL400D Device Bus Operations ................................8

Word/Byte Configuration .......................................................... 8

Requirements for Reading Array Data ..................................... 8

Writing Commands/Command Sequences .............................. 9

Program and Erase Operation Status ...................................... 9

Standby Mode .......................................................................... 9

Automatic Sleep Mode ............................................................. 9

RESET#: Hardware Reset Pin ................................................. 9

Output Disable Mode .............................................................. 10

Table 2. Am29SL400DT Top Boot Block Sector Address Table .....10

Table 3. Am29SL400DB Bottom Boot Block Sector Address Table 10

Autoselect Mode ..................................................................... 11

Table 4. Am29SL400D Autoselect Codes (High Voltage Method) ..11

Sector Protection/Unprotection ............................................... 11

Temporary Sector Unprotect .................................................. 11

Figure 1. In-system Sector Protection/Unprotection Algorithms ..... 12

Figure 2. Temporary Sector Unprotect Operation........................... 13

Hardware Data Protection ...................................................... 13

Reading Toggle Bits DQ6/DQ2 ............................................... 19

Figure 6. Toggle Bit Algorithm........................................................ 20

DQ5: Exceeded Timing Limits ................................................ 20

DQ3: Sector Erase Timer ....................................................... 20

Table 6. Write Operation Status ..................................................... 21

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22

Figure 7. Maximum Negative Overshoot Waveform ...................... 22

Figure 8. Maximum Positive Overshoot Waveform........................ 22

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. I

Current vs. Time (Showing Active and Automatic

CC1

Sleep Currents).............................................................................. 24

Figure 10. Typical I vs. Frequency ........................................... 24

CC1

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Test Setup..................................................................... 25

Table 7. Test Specifications ........................................................... 25

Key to Switching Waveforms .................................................. 25

Figure 12. Input Waveforms and Measurement Levels ................. 25

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Operations .................................................................... 26

Figure 13. Read Operations Timings ............................................. 26

Figure 14. RESET# Timings .......................................................... 27

Word/Byte Configuration (BYTE#) ........................................ 28

Figure 15. BYTE# Timings for Read Operations............................ 28

Figure 16. BYTE# Timings for Write Operations............................ 28

Erase/Program Operations ..................................................... 29

Figure 17. Program Operation Timings.......................................... 30

Figure 18. Chip/Sector Erase Operation Timings .......................... 31

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . 32

Figure 19. Data# Polling Timings (During Embedded Algorithms). 32

Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 32

Figure 21. DQ2 vs. DQ6................................................................. 33

Temporary Sector Unprotect .................................................. 33

Figure 22. Temporary Sector Unprotect Timing Diagram .............. 33

Figure 23. Sector Protect/Unprotect Timing Diagram .................... 34

Alternate CE# Controlled Erase/Program Operations ............ 35

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 24. Alternate CE# Controlled Write Operation Timings ...... 36

Erase and Programming Performance . . . . . . . 37

Low V Write Inhibit .............................................................. 13

CC

Write Pulse “Glitch” Protection ............................................... 13

Logical Inhibit .......................................................................... 13

Power-Up Write Inhibit ............................................................ 13

Command Definitions . . . . . . . . . . . . . . . . . . . . . 13

Reading Array Data ................................................................ 13

Reset Command ..................................................................... 13

Autoselect Command Sequence ............................................ 14

Word/Byte Program Command Sequence ............................. 14

Unlock Bypass Command Sequence ..................................... 14

Figure 3. Program Operation .......................................................... 15

Chip Erase Command Sequence ........................................... 15

Sector Erase Command Sequence ........................................ 15

Figure 4. Erase Operation............................................................... 16

Table 5. Am29SL400D Command Definitions ................................17

Write Operation Status ........................................................... 18

DQ7: Data# Polling ................................................................. 18

Figure 5. Data# Polling Algorithm ................................................... 18

RY/BY#: Ready/Busy# ........................................................... 18

DQ6: Toggle Bit I .................................................................... 19

DQ2: Toggle Bit II ................................................................... 19

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 37

TSOP Pin and BGA Package Capacitance . . . . . 37

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38

FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm

Package .................................................................................. 38

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39

April 13, 2005 Rev. A Amend. +1

Am29SL400D

3

A D V A N C E I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Family Part Number

Speed Options

Am29SL400D

Standard Voltage Range V = 1.65–1.95 V

90

30

100

35

120

50

CC

Max access time, ns (t

)

ACC

Max CE# access time, ns (t

)

CE

Max OE# access time, ns (t

)

OE

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V

CC

Sector Switches

V

SS

Erase Voltage

Generator

Input/Output

Buffers

RESET#

State

Control

WE#

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

Y-Gating

STB

V

Detector

Timer

CC

Cell Matrix

X-Decoder

A0–A17

4

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

CONNECTION DIAGRAM

48-Ball FBGA

(Top View, Balls Facing Down)

A6

B6

C6

D6

E6

F6

G6

H6

A13

A12

A14

A15

A16

BYTE# DQ15/A-1 V_SS

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

WE# RESET#

NC

DQ5

DQ12

V_CC

DQ4

A3

B3

C3

D3

E3

F3

G3

H3

RY/BY#

NC

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

CE#

OE#

V_SS

SSOP). The package and/or data integrity may be

compromised if the package body is exposed to tem-

^{peratures about 150}°C for prolonged periods of time.

Special Handling Instructions for FBGA

Packages

Special handling is required for Flash Memory products

in molded packages (TSOP, BGA, PLCC, PDIP,

April 13, 2005 Rev. A Amend. +1

Am29SL400D

5

A D V A N C E I N F O R M A T I O N

PIN CONFIGURATION

LOGIC SYMBOL

A0–A17

=

18 addresses

18

DQ0–DQ14 = 15 data inputs/outputs

A0–A17

16 or 8

DQ15/A-1

=

DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

DQ0–DQ15

(A-1)

BYTE#

CE#

=

Selects 8-bit or 16-bit mode

Chip enable

CE#

OE#

Output enable

WE#

Write enable

RESET#

BYTE#

RESET#

RY/BY#

Hardware reset pin, active low

Ready/Busy# output

1.65–1.95 V single power supply

Device ground

RY/BY#

V

CC

SS

NC

Pin not connected internally

6

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Am29SL400D

T

90

E

C

TEMPERATURE RANGE

C

D

I

=

Commercial (0°C to +70°C)

Commercial (0°C to +70°C) with Pb-free Package

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Pb-free Package

F

PACKAGE TYPE

WA = 48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 8 mm package (FBA048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top Sector

Bottom Sector

DEVICE NUMBER/DESCRIPTION

Am29SL400D

4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the local

AMD sales office to confirm availability of specific valid

combinations and to check on newly released combi-

nations.

Valid Combinations for FBGA Packages

Order Number Package Marking

AM29SL400DT90,

A400DT90V,

A400DB90V

AM29SL400DB90

WAC,

C, I,

D, F

AM29SL400DT100,

AM29SL400DB100

WAI, A400DT10V,

WAD, A400DB10V

WAF

AM29SL400DT120,

AM29SL400DB120

A400DT12V,

A400DB12V

April 13, 2005 Rev. A Amend. +1

Am29SL400D

7

A D V A N C E I N F O R M A T I O N

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state

machine. The state machine outputs dictate the func-

tion of the device. Table 1 lists the device bus opera-

tions, the inputs and control levels they require, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29SL400D Device Bus Operations

DQ8–DQ15

BYTE#

Addresses

(Note 1)

DQ0– BYTE#

Operation

CE# OE# WE# RESET#

DQ7

= V

IH

IL

Read

Write

L

H

L

H

A

D

OUT

IN

OUT

DQ8–DQ14 = High-Z,

DQ15 = A-1

H

D

IN

V

0.2 V

±

V

0.2 V

±

CC

Standby

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Protect (Note 2)

L

H

L

V

D

X

ID

IN

Sector Address,

A6 = H, A1 = H,

A0 = L

Sector Unprotect (Note 2)

L

H

X

L

V

D

X

ID

IN

Temporary Sector Unprotect

X

A

D

High-Z

IN

Legend:

L = Logic Low = V , H = Logic High = V , V = 10 ± ±1.0 V, X = Don’t Care, A = Address In, D = Data In, D = Data Out

IL

IH

ID

IN

OUT

Notes:

1. Addresses are A17:A0 in word mode (BYTE# = V ), A17:A-1 in byte mode (BYTE# = V ).

IH

IL

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

control and selects the device. OE# is the output

control and gates array data to the output pins. WE#

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

should remain at V . The BYTE# pin determines

IH

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert

valid addresses on the device address inputs produce

valid data on the device data outputs. The device

remains enabled for read access until the command

register contents are altered.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V . CE# is the power

IL

8

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

See “ Reading Array Data, on page 13 for more infor-

mation. Refer to the AC Read Operations table for

timing specifications and to Figure 13, on page 26 for

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

the timing diagram. I

in the DC Characteristics table

CC1

represents the active current specification for reading

array data.

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC± 0.2 V.

(Note that this is a more restricted voltage range than

V .) If CE# and RESET# are held at V , but not within

IH

V

_CC± 0.2 V, the device will be in the standby mode, but

CE# to V , and OE# to V .

IL

IH

the standby current will be greater. The device requires

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to Word/Byte Configuration, on page 8

for more information.

standard access time (t ) for read access when the

device is in either of these standby modes, before it is

ready to read data.

CE

The device also enters the standby mode when the

RESET# pin is driven low. Refer to the next section,

RESET#: Hardware Reset Pin.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are

required to program a word or byte, instead of four. The

Word/Byte Program Command Sequence, on page 14

has details on programming data to the device using

both standard and Unlock Bypass command

sequences.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

I

in the DC Characteristics table represents the

CC3

standby current specification.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector

address” consists of the address bits required to

uniquely select a sector. The Command

Definitions, on page 17 has details on erasing a sector

or the entire chip, or suspending/resuming the erase

operation.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically enables

this mode when addresses remain stable for t

+ 50

ACC

ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address

access timings provide new data when addresses are

changed. While in sleep mode, output data is latched

and always available to the system. I

Characteristics table represents the automatic sleep

mode current specification.

After the system writes the autoselect command

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings apply

in this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

in the DC

CC4

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of reset-

ting the device to reading array data. When the

RESET# pin is driven low for at least a period of t , the

RP

I

in the DC Characteristics table represents the

CC2

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state

machine to reading array data. The operation that was

interrupted should be reinitiated once the device is

ready to accept another command sequence, to

ensure data integrity.

active current specification for the write mode. The AC

Characteristics, on page 26 contains timing specifica-

tion tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

CC

Current is reduced for the duration of the RESET#

read specifications apply. Refer to Write Operation

Status, on page 18 for more information, and to AC

Characteristics, on page 26 for timing diagrams.

pulse. When RESET# is held at V

0.2 V, the device

SS

draws CMOS standby current (I

). If RESET# is held

CC4

at V but not within V

0.2 V, the standby current will

IL

SS

be greater.

April 13, 2005 Rev. A Amend. +1

Am29SL400D

9

A D V A N C E I N F O R M A T I O N

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

within a time of t

rithms). The system can read data t

RESET# pin returns to V .

(not during Embedded Algo-

READY

after the

RH

IH

Refer to AC Characteristics, on page 26 for RESET#

parameters and to Figure 14, on page 27 for the timing

diagram.

If RESET# is asserted during a program or erase oper-

ation, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

Output Disable Mode

time of t

(during Embedded Algorithms). The

READY

system can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

When the OE# input is at V , output from the device is

IH

disabled. The output pins are placed in the high imped-

ance state.

Table 2. Am29SL400DT Top Boot Block Sector Address Table

Sector Size Address Range (in hexadecimal)

(Kbytes/

Kwords)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A17

0

A16

0

A15

0

A14

X

0

A13

X

A12

X

(x8) Address Range (x16) Address Range

64/32

32/16

8/4

00000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–77FFFh

78000h–79FFFh

7A000h–7BFFFh

7C000h–7FFFFh

00000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3BFFFh

3C000h–3CFFFh

3D000h–3DFFFh

3E000h–3FFFFh

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

1

0

1

0

1

8/4

1

X

16/8

Table 3. Am29SL400DB Bottom Boot Block Sector Address Table

Sector Size

(Kbytes/

Address Range (in hexadecimal)

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

A17

0

A16

0

A15

0

A14

0

A13

0

A12

X

Kwords)

(x8) Address Range (x16) Address Range

16/8

8/4

00000h–03FFFh

04000h–05FFFh

06000h–07FFFh

08000h–0FFFFh

10000h–1FFFFh

20000h–2FFFFh

30000h–3FFFFh

40000h–4FFFFh

50000h–5FFFFh

60000h–6FFFFh

70000h–7FFFFh

00000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

0

1

0

1

8/4

0

1

X

32/16

64/32

0

1

X

0

1

0

X

0

1

X

1

0

X

1

0

1

X

1

0

X

1

X

Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration”

section for more information.

10

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

address must appear on the appropriate highest order

Autoselect Mode

address bits (see Tables 2 and 3). Table 4 shows the

remaining address bits that are don’t care. When all

necessary bits have been set as required, the program-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

The autoselect mode provides manufacturer and

device identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equipment

to automatically match a device to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 5 on page 17.

This method does not require VID. See “ Command

Definitions, on page 13 for details on using the autose-

lect mode.

When using programming equipment, the autoselect

mode requires VID on address pin A9. Address pins

A6, A1, and A0 must be as shown in Table 4. In addi-

tion, when verifying sector protection, the sector

Table 4. Am29SL400D Autoselect Codes (High Voltage Method)

A17 A11

to to

Mode CE# OE# WE# A12 A10 A9

A8

to

A7

A5

to

A2

DQ8

to

A0 DQ15

DQ7

to

DQ0

Description

A6

A1

Manufacturer ID: AMD

L

H

X

V

X

L

X

L

X

01h

70h

ID

Device ID:

Am29SL400D

(Top Boot Block)

Word

Byte

Word

Byte

22h

X

V

L

H

ID

L

H

X

22h

X

70h

F1h

Device ID:

Am29SL400D

(Bottom Boot Block)

X

V

X

H

L

ID

01h

(protected)

X

Sector Protection Verification

L

H

SA

L

H

ID

00h

(unprotected)

L = Logic Low = V , H = Logic High = V , SA = Sector Address, X = Don’t care.

IL

IH

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection/unprotection can be imple-

mented via two methods.

It is possible to determine whether a sector is protected

or unprotected. See Autoselect Mode, on page 11 for

details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the

Sector protection/unprotection requires V on the

ID

RESET# pin only, and can be implemented either

in-system or via programming equipment. Figure 1, on

page 12 shows the algorithms and Figure 23, on

page 34 shows the timing diagram. This method uses

standard microprocessor bus cycle timing. For sector

unprotect, all unprotected sectors must first be pro-

tected prior to the first sector unprotect write cycle.

RESET# pin to V . During this mode, formerly pro-

ID

tected sectors can be programmed or erased by

selecting the sector addresses. Once V is removed

ID

from the RESET# pin, all the previously protected

sectors are protected again. Figure 2, on page 13

shows the algorithm, and Figure 22, on page 33 shows

the timing diagrams, for this feature.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

April 13, 2005 Rev. A Amend. +1

Am29SL400D

11

A D V A N C E I N F O R M A T I O N

START

Protect all sectors:

PLSCNT = 1

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

RESET# = V_ID

Wait 1 µs

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 1. In-system Sector Protection/Unprotection Algorithms

12

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

for command definitions). In addition, the following

hardware data protection measures prevent accidental

erasure or programming, which might otherwise be

START

caused by spurious system level signals during V

CC

power-up and power-down transitions, or from system

noise.

RESET# = V

ID

Low V

Write Inhibit

CC

When V

is less than V

, the device does not

LKO

CC

Perform Erase or

Program Operations

accept any write cycles. This protects data during V

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

CC

RESET# = V

device resets. Subsequent writes are ignored until V

IH

CC

is greater than V

. The system must provide the

LKO

proper signals to the control pins to prevent uninten-

tional writes when V is greater than V

.

CC

LKO

Temporary Sector

Unprotect Completed

(Note 2)

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Notes:

Logical Inhibit

1. All protected sectors unprotected.

Write cycles are inhibited by holding any one of OE# =

2. All previously protected sectors are protected once

again.

V , CE# = V or WE# = V . To initiate a write cycle,

IL

IH

CE# and WE# must be a logical zero while OE# is a

logical one.

Figure 2. Temporary Sector Unprotect Operation

Power-Up Write Inhibit

Hardware Data Protection

If WE# = CE# = V and OE# = V during power up, the

IL

IH

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 5 on page 17

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 5 on page 17 defines the valid reg-

ister command sequences. Writing incorrect address

and data values or writing them in the improper

sequence resets the device to reading array data.

erase-suspended sectors, the device outputs status

data. After completing a programming operation in the

Erase Suspend mode, the system may once again

read array data with the same exception. See “Erase

Suspend/Erase Resume Commands” for more infor-

mation on this mode.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in AC

Characteristics, on page 26.

The system must issue the reset command to

re-enable the device for reading array data if DQ5 goes

high, or while in the autoselect mode. See the Reset

Command section, next.

See also Requirements for Reading Array Data, on

page 8 for more information. The Read Operations

table provides the read parameters, and Figure 13, on

page 26 shows the timing diagram.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or

Embedded Erase algorithm.

Reset Command

Writing the reset command to the device resets the

device to reading array data. Address bits are don’t

care for this command.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The

system can read array data using the standard read

timings, except that if it reads at an address within

The reset command may be written between the

sequence cycles in an erase command sequence

April 13, 2005 Rev. A Amend. +1

Am29SL400D

13

A D V A N C E I N F O R M A T I O N

before erasing begins. This resets the device to reading

ings. The device automatically generates the program

pulses and verifies the programmed cell margin.

Table 5 on page 17 shows the address and data

requirements for the byte program command

sequence.

array data. Once erasure begins, however, the device

ignores reset commands until the operation is com-

plete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See Write Operation

Status, on page 18 for information on these status bits.

The reset command may be written between the

sequence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The Byte Program command

sequence should be reinitiated once the device has

reset to reading array data, to ensure data integrity.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to

reading array data (also applies during Erase Sus-

pend).

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 5 on page 17 shows the address and data

requirements. This method is an alternative to that

shown in Table 4 on page 11, which is intended for

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to

program bytes or words to the device faster than using

the standard program command sequence. The unlock

bypass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The

device then enters the unlock bypass mode. A

two-cycle unlock bypass program command sequence

is all that is required to program in this mode. The first

cycle in this sequence contains the unlock bypass

program command, A0h; the second cycle contains the

program address and data. Additional data is pro-

grammed in the same manner. This mode dispenses

with the initial two unlock cycles required in the stan-

dard program command sequence, resulting in faster

total programming time. Write Operation Status, on

page 18 shows the requirements for the command

sequence.

PROM programmers and requires V on address bit

ID

A9.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence. A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address 01h in

word mode (or 02h in byte mode) returns the device

code. A read cycle containing a sector address (SA)

and the address 02h in word mode (or 04h in byte

mode) returns 01h if that sector is protected, or 00h if it

is unprotected. Refer to Table 2 on page 10 and Table 3

on page 10 for valid sector addresses.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset

command sequence. The first cycle must contain the

data 90h; the second cycle the data 00h. Addresses

are don’t cares. The device then returns to reading

array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program

command sequence is initiated by writing two unlock

write cycles, followed by the program set-up command.

The program address and data are written next, which

in turn initiate the Embedded Program algorithm. The

system is not required to provide further controls or tim-

Figure 3, on page 15 illustrates the algorithm for the

program operation. See the Erase/Program

14

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

Operations, on page 29 for parameters, and to

Figure 17, on page 30 for timing diagrams.

hardware reset during the chip erase operation imme-

diately terminates the operation. The Chip Erase

command sequence should be reinitiated once the

device has returned to reading array data, to ensure

data integrity.

START

The system can determine the status of the erase oper-

ation by using DQ7, DQ6, DQ2, or RY/BY#. See Write

Operation Status, on page 18 for information on these

status bits. When the Embedded Erase algorithm is

complete, the device returns to reading array data and

addresses are no longer latched.

Write Program

Command Sequence

Figure 4, on page 16 illustrates the algorithm for the

erase operation. See the Erase/Program

Operations, on page 29 for parameters, and to

Figure 18, on page 31 for timing diagrams.

Data Poll

from System

Embedded

Program

algorithm

in progress

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. Table 5 on page 17 shows the

address and data requirements for the sector erase

command sequence.

Verify Data?

No

Yes

No

Increment Address

Last Address?

Yes

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

Programming

Completed

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of

sectors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The

interrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional

sector erase commands can be assumed to be less

than 50 µs, the system need not monitor DQ3. Any

command other than Sector Erase or Erase

Suspend during the time-out period resets the

device to reading array data. The system must

rewrite the command sequence and any additional

sector addresses and commands.

Note: See Table 5 on page 17 for program command

sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 5 on

page 17 shows the address and data requirements for

the chip erase command sequence.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See DQ3: Sector Erase

Timer, on page 20.) The time-out begins from the rising

edge of the final WE# pulse in the command sequence.

Any commands written to the chip during the

Embedded Erase algorithm are ignored. Note that a

April 13, 2005 Rev. A Amend. +1

Am29SL400D

15

A D V A N C E I N F O R M A T I O N

Once the sector erase operation has begun, only the

non-suspended sectors. The system can determine

the status of the program operation using the DQ7 or

DQ6 status bits, just as in the standard program oper-

ation. See Write Operation Status, on page 18 for

more information.

Erase Suspend command is valid. All other commands

are ignored. Note that a hardware reset during the

sector erase operation immediately terminates the

operation. The Sector Erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

The system may also write the autoselect command

sequence when the device is in the Erase Suspend

mode. The device allows reading autoselect codes

even at addresses within erasing sectors, since the

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See Autoselect Command

Sequence, on page 14 for more information.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched. The system can determine the

status of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. (Refer to Write Operation Status, on

page 18 for information on these status bits.)

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations, on

page 29 for parameters, and to Figure 18, on page 31

for timing diagrams.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the

device has resumed erasing.

Erase Suspend/Erase Resume Commands

The Erase Suspend command allows the system to

interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for

erasure. This command is valid only during the sector

erase operation, including the 50 µs time-out period

during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program algo-

rithm. Writing the Erase Suspend command during the

Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation.

Addresses are “don’t-cares” when writing the Erase

Suspend command.

START

Write Erase

Command Sequence

Data Poll

from System

When the Erase Suspend command is written during a

sector erase operation, the device requires a maximum

of 20 µs to suspend the erase operation. However,

when the Erase Suspend command is written during

the sector erase time-out, the device immediately ter-

minates the time-out period and suspends the erase

operation.

Embedded

Erase

algorithm

in progress

No

Data = FFh?

After the erase operation has been suspended, the

system can read array data from or program data to

any sector not selected for erasure. (The device “erase

suspends” all sectors selected for erasure.) Normal

read and write timings and command definitions apply.

Reading at any address within erase-suspended

sectors produces status data on DQ7–DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to

determine if a sector is actively erasing or is erase-sus-

pended. See Write Operation Status, on page 18 for

information on these status bits.

Yes

Erasure Completed

Notes:

1. See Table 5 on page 17 for erase command sequence.

2. See DQ3: Sector Erase Timer, on page 20 for more infor-

mation.

Figure 4. Erase Operation

After an erase-suspended program operation is com-

plete, the system can once again read array data within

16

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

Command Definitions

Table 5. Am29SL400D Command Definitions

Bus Cycles (Notes 2-5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data Addr Data Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

1

RA

XXX

555

RD

F0

Word

2AA

555

2AA

555

2AA

555

AAA

555

Manufacturer ID

4

AA

55

90

X00

01

Byte

Word

Byte

Word

Byte

AAA

555

X01

X02

X01

X02

70h

F1h

XX00

XX01

00

Device ID,

Top Boot Block

AAA

555

AAA

555

Device ID,

Bottom Boot Block

AAA

(SA)

X02

Word

Byte

555

2AA

555

Sector Protect Verify

(Note 9)

4

AA

55

90

(SA)

X04

AAA

01

Word

Byte

Word

Byte

555

AAA

555

2AA

555

2AA

555

PA

555

AAA

555

Program

Unlock Bypass

4

3

AA

55

A0

20

PA

PD

AAA

XXX

555

AAA

Unlock Bypass Program (Note 10)

Unlock Bypass Reset (Note 11)

2

A0

90

PD

00

XXX

2AA

555

2AA

555

Word

555

AAA

555

AAA

555

2AA

555

2AA

555

Chip Erase

Byte

6

AA

55

80

AA

55

10

30

AAA

555

AAA

Word

Sector Erase

Byte

SA

AAA

XXX

AAA

Erase Suspend (Note 12)

Erase Resume (Note 13)

1

B0

30

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the

rising edge of WE# or CE# pulse, whichever happens first.

RA = Address of the memory location to be read.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A17–A12 uniquely select any sector.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed.

Addresses latch on the falling edge of the WE# or CE# pulse,

whichever happens later.

Notes:

1. See Table 1 on page 8 for description of bus operations.

9. The data is 00h for an unprotected sector and 01h for a protected

sector. See Autoselect Command Sequence, on page 14 for

more information.

2. All values are in hexadecimal.

3. Except when reading array or autoselect data, all bus cycles are

write operations.

10. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

4. Data bits DQ15–DQ8 are don’t cares for unlock and command

cycles.

11. The Unlock Bypass Reset command is required to return to

reading array data when the device is in the unlock bypass mode.

5. Address bits A17–A11 are don’t cares for unlock and command

cycles, unless SA or PA required.

12. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

6. No unlock or command cycles required when reading array data,

unless SA or PA required.

7. The Reset command is required to return to reading array data

when device is in the autoselect mode, or if DQ5 goes high (while

the device is providing status data).

13. The Erase Resume command is valid only during the Erase Suspend

mode.

8. The fourth cycle of the autoselect command sequence is a read

cycle.

April 13, 2005 Rev. A Amend. +1

Am29SL400D

17

A D V A N C E I N F O R M A T I O N

Write Operation Status

The device provides several bits to determine the status

of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and

RY/BY#. Table 6 on page 21 and the following subsec-

tions describe the functions of these bits. DQ7, RY/BY#,

and DQ6 each offer a method for determining whether

a program or erase operation is complete or in progress.

These three bits are discussed first.

START

Read DQ7–DQ0

Addr = VA

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend.

Data# Polling is valid after the rising edge of the final

WE# pulse in the program or erase command

sequence.

Yes

DQ7 = Data?

No

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the Embedded

Program algorithm is complete, the device outputs the

datum programmed to DQ7. The system must provide

the program address to read valid status information on

DQ7. If a program address falls within a protected

sector, Data# Polling on DQ7 is active for approximately

1 µs, then the device returns to reading array data.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Addr = VA

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or “0.”

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protected.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the following read cycles. This is because

DQ7 may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 19, on

page 32, Data# Polling Timings (During Embedded

Algorithms), illustrates this.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output,

several RY/BY# pins can be tied together in parallel with

Table 6 on page 21 shows the outputs for Data# Polling

on DQ7. Figure 5 shows the Data# Polling algorithm.

a pull-up resistor to V

.

CC

18

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

If the output is low (Busy), the device is actively erasing

DQ2: Toggle Bit II

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence. The device toggles DQ2 with

each OE# or CE# read cycle.

Table 6 on page 21 shows the outputs for RY/BY#.

Figure 14, on page 27, Figure 17, on page 30 and

Figure 18, on page 31 shows RY/BY# for reset, pro-

gram, and erase operations, respectively.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. But DQ2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. DQ6, by com-

parison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish

which sectors are selected for erasure. Thus, both

status bits are required for sector and mode informa-

tion. Refer to Table 6 on page 21 to compare outputs

for DQ2 and DQ6.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase

operation), and during the sector erase time-out.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

cause DQ6 to toggle (The system may use either OE#

or CE# to control the read cycles). When the operation

is complete, DQ6 stops toggling.

Figure 6, on page 20 shows the toggle bit algorithm in

flowchart form, and the section “DQ2: Toggle Bit II”

explains the algorithm. See also the DQ6: Toggle Bit I

subsection. Figure 20, on page 32 shows the toggle bit

timing diagram. Figure 21, on page 33 shows the dif-

ferences between DQ2 and DQ6 in graphical form.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 toggles

for approximately 100 µs, then returns to reading array

data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6, on page 20 for the following discus-

sion. Whenever the system initially begins reading

toggle bit status, it must read DQ7–DQ0 at least twice

in a row to determine whether a toggle bit is toggling.

Typically, the system would note and store the value of

the toggle bit after the first read. After the second read,

the system would compare the new value of the toggle

bit with the first. If the toggle bit is not toggling, the

device has completed the program or erase operation.

The system can read array data on DQ7–DQ0 on the

following read cycle.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the

system must also use DQ2 to determine which sectors

are erasing or erase-suspended. Alternatively, the

system can use DQ7 (see the subsection on DQ7:

Data# Polling).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not completed the operation successfully,

and the system must write the reset command to return

to reading array data.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

Table 6 on page 21 shows the outputs for Toggle Bit I

on DQ6. Figure 6, on page 20 shows the toggle bit

algorithm. Figure 20, on page 32 shows the toggle bit

timing diagrams. Figure 21, on page 33 shows the dif-

ferences between DQ2 and DQ6 in graphical form. See

also the subsection on DQ2: Toggle Bit II.

The remaining scenario is that the system initially

determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous

paragraph. Alternatively, it may choose to perform

April 13, 2005 Rev. A Amend. +1

Am29SL400D

19

A D V A N C E I N F O R M A T I O N

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 6).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

START

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Read DQ7–DQ0

(Note 1)

Read DQ7–DQ0

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

No

Toggle Bit

= Toggle?

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire

time-out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1.” If the time between additional

sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the “ Sector Erase Command

Sequence, on page 15 section.

Yes

No

DQ5 = 1?

Yes

(Notes

1, 2)

Read DQ7–DQ0

Twice

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 6 on page 21 shows the outputs for

DQ3.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

Figure 6. Toggle Bit Algorithm

20

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

Table 6. Write Operation Status

DQ7

DQ5

DQ2

Operation

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

Reading within Erase

Suspended Sector

1

No toggle

0

N/A

Toggle

1

Erase

Suspend

Mode

Reading within Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See DQ5: Exceeded Timing Limits, on page 20 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

April 13, 2005 Rev. A Amend. +1

Am29SL400D

21

A D V A N C E I N F O R M A T I O N

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

0.0 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

(Note 1). . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

CC

A9, OE#,

and RESET# (Note 2) . . . . . . . . . . .–0.5 V to +11.0 V

20 ns

All other pins (Note 1) . . . . . . . . –0.5 V to V +0.5 V

CC

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Figure 7. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may overshoot V to

SS

–2.0 V for periods of up to 20 ns. See Figure 7. Maximum

DC voltage on input or I/O pins is V +0.5 V. During

CC

voltage transitions, input or I/O pins may overshoot to V

+2.0 V for periods up to 20 ns. See Figure 8.

CC

20 ns

2. Minimum DC input voltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

V

CC

+2.0 V

RESET# may overshoot V to –2.0 V for periods of up to

SS

V

CC

20 ns. See Maximum DC input voltage on pin A9 is +11.0

V which may overshoot to 12.5 V for periods up to 20 ns.

+0.5 V

2.0 V

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

20 ns

Figure 8. Maximum Positive

Overshoot Waveform

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (T ) . . . . . . . . . . . 0°C to +70°C

A

Industrial (I) Devices

Ambient Temperature (T ) . . . . . . . . . –40°C to +85°C

A

V

Supply Voltages

CC

V

for all speed options . . . . . . . .+1.65 V to +1.95 V

CC

Operating ranges define those limits between which the

functionality of the device is guaranteed.

22

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS

CMOS Compatible

Parameter

Description

Test Conditions

= V to V

Min

Typ

Max

± 1.0

35

Unit

µA

V

,

CC

IN

SS

I

Input Load Current

LI

= V

CC

CC max

I

A9 Input Load Current

Output Leakage Current

V

= V

; A9 = 11.0 V

µA

LIT

CC

CC max

V

= V to V

,

CC

OUT

SS

I

± 1.0

µA

LO

= V

CC

CC max

5 MHz

1 MHz

5 MHz

1 MHz

5

1

5

1

10

3

CE# = V OE#

Byte Mode

V

IL,

=

IH,

V

Active Read Current

CC

I

mA

CC1

(Notes 1, 2)

10

3

CE# = V OE#

V

IL,

Word Mode

V

Active Write Current

CC

I

CE# = V OE#

V

15

30

mA

CC2

IL,

=

IH

(Notes 2, 3, 5)

I

V

Standby Current (Note 2)

CE#, RESET# = V ± ±0.2 V

0.2

5

µA

CC3

CC

Reset Current (Note 2)

RESET# = V ± ±0.2 V

CC4

SS

Automatic Sleep Mode

(Notes 2, 3)

V

= V ± ±0.2 V;

IH

IL

CC

I

0.2

5

µA

CC5

= V ± ±0.2 V

SS

V

Input Low Voltage

Input High Voltage

–0.5

0.3 x V

V

IL

CC

V

0.7 x V

V

+ 0.3

IH

CC

Voltage for Autoselect and

Temporary Sector Unprotect

V

= 2.0 V

9.0

11.0

V

ID

CC

V

I

= 2.0 mA, V = V

0.25

0.1

V

OL1

OL2

OH1

OH2

OL

OH

CC

CC min

Output Low Voltage

Output High Voltage

= 100 µA, V = V

CC

V

= –2.0 mA, V = V

0.85 x V

CC

CC min

= –100 µA, V = V

V

–0.1

CC

Low V Lock-Out Voltage

(Note 4)

CC

V

1.2

1.5

V

LKO

Notes:

1. The I current listed is typically less than 1 mA/MHz, with OE# at V . Typical V is 2.0 V.

CC

IH

CC

2. The maximum I specifications are tested with V = V max.

CC

3. I active while Embedded Erase or Embedded Program is in progress.

CC

4. Automatic sleep mode enables the low power mode when addresses remain stable for t

5. Not 100% tested.

+ 50 ns.

ACC

April 13, 2005 Rev. A Amend. +1

Am29SL400D

23

A D V A N C E I N F O R M A T I O N

DC CHARACTERISTICS (Continued)

Zero Power Flash

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 9.

I

Current vs. Time (Showing Active and Automatic Sleep Currents)

CC1

10

8

6

4

1.8 V

2

0

1

2

3

4

5

Frequency in MHz

Note: T = 25 °C

Figure 10. Typical I

vs. Frequency

CC1

24

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

TEST CONDITIONS

Table 7. Test Specifications

Test Condition

All Speed Options Unit

Output Load Capacitance, C

(including jig capacitance)

L

30

pF

Device

Under

Test

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

0.0–2.0

C

L

Input timing measurement

reference levels

1.0

V

Output timing measurement

reference levels

Figure 11. Test Setup

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

2.0 V

0.0 V

1.0 V

Input

Measurement Level

Output

Figure 12. Input Waveforms and Measurement Levels

April 13, 2005 Rev. A Amend. +1

Am29SL400D

25

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Read Operations

Parameter

Speed Options

JEDEC

Std

Description

Read Cycle Time (Note 1)

Test Setup

90

100

120

Unit

t

Min

90

100

120

ns

AVAV

RC

CE# = V

OE# = V

IL

t

Address to Output Delay

Max

90

100

ns

AVQV

ACC

t

Chip Enable to Output Delay

OE# = V

Max

Min

90

30

100

35

16

0

120

50

ns

ELQV

GLQV

EHQZ

GHQZ

CE

IL

t

Output Enable to Output Delay

OE

t

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

DF

t

Read

Output Enable

Hold Time (Note 1)

t

OEH

Toggle and

Data# Polling

Min

30

0

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1)

t

OH

AXQX

Notes:

1. Not 100% tested.

2. See Figure 11, on page 25 and Table 7 on page 25 for test specifications.

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operations Timings

26

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

Test Setup

Max

All Speed Options

Unit

RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note)

t

20

µs

READY

RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note)

Max

500

ns

READY

t

RESET# Pulse Width

Min

500

200

20

ns

µs

ns

RP

RESET# High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

RH

t

RPD

t

0

RB

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. RESET# Timings

April 13, 2005 Rev. A Amend. +1

Am29SL400D

27

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

Speed Options

JEDEC

Std.

Description

90

100

10

120

Unit

ns

t

CE# to BYTE# Switching Low or High

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

Max

Min

ELFL/ ELFH

50

90

50

60

ns

FLQZ

FHQV

100

120

ns

CE#

OE#

BYTE#

t

ELFL

Data Output

(DQ0–DQ14)

Data Output

(DQ0–DQ7)

BYTE#

Switching

from word

to byte

DQ0–DQ14

DQ15/A-1

Address

Input

DQ15

Output

mode

t

FLQZ

t

ELFH

BYTE#

Switching

from byte

to word

Data Output

(DQ0–DQ7)

Data Output

(DQ0–DQ14)

DQ0–DQ14

DQ15/A-1

mode

Address

Input

DQ15

Output

t

FHQV

Figure 15. BYTE# Timings for Read Operations

CE#

The falling edge of the last WE# signal

WE#

BYTE#

t

SET

(t

)

AS

t

(t

)

HOLD AH

Note: Refer to the Erase/Program Operations, on page 29 for t and t specifications.

AS

AH

Figure 16. BYTE# Timings for Write Operations

28

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase/Program Operations

Parameter

Speed Options

JEDEC

Std.

Description

Write Cycle Time (Note 1)

90

100

0

120

Unit

ns

t

Min

90

120

AVAV

WC

t

Address Setup Time

Address Hold Time

Data Setup Time

ns

AVWL

WLAX

DVWH

WHDX

AS

AH

DS

DH

t

45

50

0

60

ns

t

ns

t

Data Hold Time

ns

t

Output Enable Setup Time

0

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHWL

t

CE# Setup Time

Min

Typ

Min

0

ns

ELWL

WHEH

WLWH

WHWL

CS

t

CE# Hold Time

CH

t

Write Pulse Width

Write Pulse Width High

45

50

30

5

60

WP

t

WPH

Byte

t

Programming Operation (Notes 1, 2)

µs

WHWH1

WHWH2

WHWH1

Word

7

Sector Erase Operation (Notes 1, 2)

0.7

50

0

sec

µs

WHWH2

t

V

Setup Time

CC

VCS

t

Recovery Time from RY/BY#

ns

RB

t

Program/Erase Valid to RY/BY# Delay

200

ns

BUSY

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance, on page 37 for more information.

April 13, 2005 Rev. A Amend. +1

Am29SL400D

29

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D

is the true data at the program address.

OUT

2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

30

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

April 13, 2005 Rev. A Amend. +1

Am29SL400D

31

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

t_RC

VA

t_ACC

t_CE

Addresses

VA

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ6/DQ2

RY/BY#

Valid Status

(first read)

Valid Status

Valid Data

(second read)

(stops toggling)

t_BUSY

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle.

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

32

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Enter

Erase

Suspend

Enter Erase

Suspend Program

Embedded

Erase

Resume

Erasing

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 21. DQ2 vs. DQ6

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

Rise and Fall Time

ID

All Speed Options

Unit

t

V

Min

500

ns

VIDR

RESET# Setup Time for Temporary Sector

Unprotect

t

4

µs

RSP

10 V

RESET#

0 or 1.8 V

t_VIDR

0 or 1.8 V

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RSP

RY/BY#

Figure 22. Temporary Sector Unprotect Timing Diagram

April 13, 2005 Rev. A Amend. +1

Am29SL400D

33

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

V

ID

V

IH

RESET#

SA, A6,

A1, A0

Valid*

Status

Sector Protect/Unprotect

Verify

40h

Data

60h

Sector Protect: 150 µs

Sector Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Protect/Unprotect Timing Diagram

34

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Parameter

Speed Options

JEDEC

Std.

Description

90

100

0

120

Unit

ns

t

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Min

90

120

AVAV

AVEL

ELAX

DVEH

EHDX

WC

t

ns

AS

AH

DS

DH

t

45

50

0

60

ns

t

ns

t

Data Hold Time

ns

t

Output Enable Setup Time

0

ns

OES

Read Recovery Time Before Write

(OE# High to WE# Low)

t

Min

0

ns

GHEL

WLEL

GHEL

t

WE# Setup Time

WE# Hold Time

Min

Typ

0

ns

WS

t

EHWH

WH

t

CE# Pulse Width

CE# Pulse Width High

45

50

30

5

60

ELEH

EHEL

CP

t

CPH

Byte

Programming Operation

(Notes 1, 2)

t

µs

WHWH1

Word

7

Sector Erase Operation (Notes 1, 2)

0.7

sec

WHWH2

Notes:

1. Not 100% tested.

2. See Erase and Programming Performance, on page 37 for more information.

April 13, 2005 Rev. A Amend. +1

Am29SL400D

35

A D V A N C E I N F O R M A T I O N

AC CHARACTERISTICS

555 for program

2AA for erase

PA for program

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. PA = program address, PD = program data, DQ7# = complement of the data written, D

2. Figure indicates the last two bus cycles of command sequence.

3. Word mode address used as an example.

= data written

OUT

Figure 24. Alternate CE# Controlled Write Operation Timings

36

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

s

Comments

Sector Erase Time

Chip Erase Time

0.7

38

10

12

5

15

Excludes 00h programming

prior to erasure (Note 4)

s

Byte Programming Time

Word Programming Time

300

360

40

µs

s

Excludes system level

overhead (Note 5)

Byte Mode

Word Mode

Chip Programming Time

(Note 3)

3.5

30

s

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 1.8 V V_CC, 1,000,000 cycles. Additionally, programming

typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 1.8 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program

faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5

on page 17 for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V on all pins except I/O pins

(including A9, OE#, and RESET#)

SS

–1.0 V

11.0 V

Input voltage with respect to V on all I/O pins

–0.5 V

V

+ 0.5 V

CC

SS

V

Current

–100 mA

+100 mA

CC

Includes all pins except V . Test conditions: V = 1.8 V, one pin at a time.

CC

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5.0

12

Unit

pF

TSOP

C

Input Capacitance

V

= 0

IN

Fine-pitch BGA

TSOP

4.2

8.5

5.4

7.5

3.9

C

Output Capacitance

V

= 0

OUT

Fine-pitch BGA

TSOP

6.5

9

C

Control Pin Capacitance

V

= 0

IN2

IN

Fine-pitch BGA

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions T = 25°C, f = 1.0 MHz.

A

DATA RETENTION

Parameter

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

April 13, 2005 Rev. A Amend. +1

Am29SL400D

37

A D V A N C E I N F O R M A T I O N

PHYSICAL DIMENSIONS

FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm Package

Dwg rev AF; 10/99

38

Am29SL400D

Rev. A Amend. +1 April 13, 2005

A D V A N C E I N F O R M A T I O N

Valid Combination Table,

REVISION SUMMARY

Added package designators for Pb-free options.

Revision A (February 12, 2004)

Global

Initial release.

Added Colophon.

Revision A+1 (April 13, 2005)

Ordering Information

Updated Trademark.

Added Cover Page.

Added Commercial and Industrial Pb-free options.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

April 13, 2005 Rev. A Amend. +1

Am29SL400D

39


型号：	AM29SL400DT120WAI
厂家：	AMD
描述：	4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super Low Voltage Flash Memory 4兆位（ 512K的×8位/ 256千×16位） CMOS 1.8伏只超低电压闪存闪存内存集成电路
文件：	总41页 (文件大小：775K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM29SL400DT120WAI [AMD]

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