AM53CF94KCW_技术文档

PRELIMINARY

Advanced

Micro

Am53CF94/Am53CF96

Devices

Enhanced SCSI-2 Controller (ESC)

DISTINCTIVE CHARACTERISTICS

■ Pin/function compatible with Emulex

FAS216/236

■ AMD’s exclusive programmable power-down

feature

■ AMD’s Patented programmable GLITCH

EATER^TMCircuitry on REQ and ACK inputs

■ 10 Mbytes/s synchronous Fast SCSI transfer

rate

■ 24-Bit extended transfer counter allows for

data block transfer of up to 16 Mbytes

■ Independently programmable 3-byte message

and group 2 identification

■ 20 Mbytes/s DMA transfer rate

■ 16-Bit DMA interface plus 2 bits of parity

■ Flexible three bus architecture

■ Single-ended SCSI bus supported by

Am53CF94

■ Differential SCSI bus supported by Am53CF96

■ Selection of multiplexed or non-multiplexed

address and data bus

■ Additional check for ID message during

bus-initiated Select with ATN

■ Reselection has QTAG features of ATN3

■ Access FIFO Command

■ Delayed enable signal for differential drivers

avoid contention on SCSI differential lines

■ Programmable Active Negation on REQ, ACK

and Data lines

■ Register programmable control of assertion/

deassertion delay for REQ and ACK lines

■ Part-unique ID code

■ Am53CF94 available in 84-pin PLCC package

■ Am53CF96 available in 100-pin PQFP package

■ Am53CF94 available in 3.3 V version

■ Supports clock operating frequencies from

10 MHz–40 MHz

■ High current drivers (48 mA) for direct

connection to the single-ended SCSI bus

■ Supports Disconnect and Reselect commands

■ Supports burst mode DMA operation with a

threshold of eight

■ Supports 3-byte tagged-queueing as per the

SCSI-2 specification

■ Supports group 2 and 5 command recognition

as per the SCSI-2 specification

■ Supports Scatter-Gather or Back-to-Back

synchronous data transfers

■ Advanced CMOS process for lower power

consumption

GENERAL DESCRIPTION

The Enhanced SCSI-2 Controller (ESC) was designed

to support Fast SCSI-2 transfer rates of up to

10 Mbytes/s in synchronous mode and up to 7 Mbytes/s

in the asynchronous mode. The ESC is downward com-

patiblewiththeAm53C94/96, combiningitsfunctionality

with features such as Fast SCSI, programmable Active

Negation, a 24-bit transfer counter, and a part-unique ID

code containing manufacturer and serial # information.

AMD’s proprietary features such as power-down mode

for SCSI transceivers, programmable GLITCH EATER,

and extended Target command set are also included for

improved product performance.

reselection, information transfer and disconnection

commands are directly supported.

The 16-byte-internal FIFO further assists in minimizing

host involvement. The FIFO provides a temporary stor-

ageforallcommand, data, statusandmessagebytesas

they are transferred between the 16-bit host data bus

and the 8-bit SCSI data bus. During DMA operations the

FIFO acts as a buffer to allow greater latency in the DMA

channel. This permits the DMA channel to be sus-

pended for higher priority operations such as DRAM re-

fresh or reception of an ISDN packet.

Parity on the DMA bus is optional. Parity can either be

generated and checked or it can be simply passed

through.

The Enhanced SCSI-2 Controller (ESC) has a flexible

three bus architecture. The ESC has a 16-bit DMA inter-

face, an 8-bit host data interface and an 8-bit SCSI data

interface. The ESC is designed to minimize host inter-

vention by implementing common SCSI sequences in

hardware. An on-chip state machine reduces protocol

overheads by performing the required sequences in re-

sponse to a single command from the host. Selection,

The Target command set for the Am53CF94/96 in-

cludes an additional command, the Access FIFO com-

mand, to allow the host or DMA controller to remove re-

maining FIFO data following the host’s issuance of a

Target abort DMA command or following an abort due to

Publication# 17348 Rev. B Amendment/0

This document contains information on a product under development at Advanced Micro Devices Inc. The information is intended

to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

Issue Date: May 1993

AMD

P R E L I M I N A R Y

parity error. This command facilitates data recovery and

thereby minimizes the need to re-transmit data.

removing glitches that may cause system failure. The

GLITCH EATER Circuitry is implemented on the ACK

and REQ lines since they are most susceptible to

electrical anomalies such as reflections and voltage

spikes. Such signal inconsistencies can trigger false

REQ/ACKhandshaking, falsedatatransfers, additionof

random data, and double clocking. AMD’s GLITCH

EATER Circuitry therefore maintains system perform-

ance and improves reliability. The following diagram

illustrates this circuit’s operation.

AMD’s exclusive power-down feature can be enabled to

help reduce power consumption during the chip’s sleep

mode. The receivers on the SCSI bus may be turned off

to eliminate current that may flow because termination

power (~3 V) is close to the trip point of the input buffers.

The patented GLITCH EATER Circuitry in the

Enhanced SCSI-2 Controller can be programmed to

filter glitches with widths up to 35 ns. It is designed to

dramatically increase system reliability by detecting and

The Am53CF94 is also available in a 3.3 V version.

GLITCH EATER Circuitry in SCSI Environment

SCSI Environment

Device without the

GLITCH EATER Circuit

Glitch Window

AMD’s Device with the

GLITCH EATER Circuit

Note:

The Glitch Window is programmable via Control Register Four (0DH), bits 6 & 7. Window may be set to 35 ns (max). Default

setting is 12 ns (single-ended).

17348B-1

SYSTEM BLOCK DIAGRAM

Addr

4

9

SCSI Data

CPU

8

16

Data

DMA

Am53CF94/96

9

SCSI Control

16

DMA

Memory

17348B-2

2

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

SYSTEM BUS MODE DIAGRAMS

BUSMD 1

DMAWR

BUSMD 0

WR

RD

Address Bus

Am53CF94/96

A 3–0

Host

Processor

Bus

Controller

8-Bit Data Bus

DMA 7–0

DREQ

DACK

DMA

Controller

17348B-3

Bus Mode 0

Single Bus Architecture: 8-Bit DMA, 8-Bit Processor

V_DD

BUSMD 1

BUSMD 0

DMAWR

WR

RD

Am53CF94/96

Address Bus

Data Bus

8

A 3–0

Host

Processor

Bus

Controller

DMA 15–0

DREQ

DACK

16

DMA

Controller

17348B-4

Bus Mode 1

Single Bus Architecture: 16-Bit DMA, 8-Bit Processor

3

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

SYSTEM BUS MODE DIAGRAMS

V_DD

BUSMD 1

WR

BUSMD 0

RD

Host

Processor

ALE

8-Bit Data Bus

16-Bit Data Bus

AD 7–0

Am53CF94/96

DMA 15–0

AS0

BHE

DMA

DMARD

DMAWR

DREQ

DACK

Controller

Bus Mode 2

17348B-5

Dual Bus Architecture: 16-Bit DMA with Byte Control,

8-Bit Multiplexed Processor Address Data

V_DD

BUSMD 1

BUSMD 0

WR

RD

Host

Processor

Address Bus

A 3–0

8-Bit Data Bus

AD 7–0

Am53CF94/96

16-Bit Data Bus

DMA 15–0

DMA

Controller

DMAWR

DREQ

DACK

Bus Mode 3

17348B-6

Dual Bus Architecture: 16-Bit DMA,

8-Bit Processor

4

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

BLOCK DIAGRAM

18

16 x 9 FIFO

(including parity)

SCSI Bus

Data + Parity

(Single Ended)

DMA_15-0

9

DMAP

1-0

Parity Logic

4

SCSI Bus

Data + Parity

Direction Control

DMA Control

8

AD_7-0

6

Host Control

Register

Bank

Main

Sequencer

CS

BUSMD_1-0

9

7

SCSI Control

DFMODE

CLK

SCSI Control

Direction Control

8

RESET

SCSI

Sequencer

17348B-7

5

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

CONNECTION DIAGRAMS

Top View

11 10

9

8

7

6

5

4

3

2

1

84 83 82 81 80 79 78 77 76 75

74

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SD0

SD1

SD2

DMAWR

DACK

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

DREQ

AD7

AD6

AD5

AD4

VSS

AD3

SD3

SD4

SD5

SD6

SD7

SDP

Am53CF94

84-Pin PLCC

V

DD

AD2

AD1

AD0

V

SS

SDC0

SDC1

SDC2

V

DD

CLK

SDC3

ALE [A3]

DMARD [A2]

BHE [A1]

AS0 [A0]

CS

V

SS

SDC4

SDC5

SDC6

SDC7

SDCP

RD

WR

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

17348B-8

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

CS

AS0 [A0]

50

49

48

SDC 6

SDC 5

SDC 4

81

82

BHE [A1]

83

84

85

V

DMARD [A2]

ALE [A3]

47

46

SS

V

SS

SDC 3

CLK

45

44

43

42

86

87

88

89

90

DFMODE

SDC 2

SDC 1

SDC 0

V

DD

Am53CF96

100-Pin PQFP

NC

AD0

V

41

40

39

SS

V

AD1

AD2

91

92

93

94

SS

NC

V

AD3

38

37

36

35

34

DD

V

SD P

SD 7

SS

V

95

96

SS

AD4

AD5

SD 6

SD 5

97

AD6

AD7

98

33

32

31

SD 4

SD 3

SD 2

99

DREQ

100

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

17348B-9

6

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

LOGIC SYMBOL

SD 7–0

SD P

DMA 15–0

SDC 7–0

DMAP 1–0

ALE [A3]

SDC P

MSG

DMARD [A2]

C/D

BHE [A1]

I/O

AS0 [A0]

DREQ

ATN

BSY

SEL

RST

REQ

ACK

DACK

AD 7–0

DMAWR

RD

Am53CF94/96

WR

BSYC

SELC

RSTC

REQC

CS

INT

BUSMD 1–0

*DFMODE

CLK

ACKC

*ISEL

*TSEL

RESET

Note:

17348B-10

*Pins available on the Am53CF96 only.

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7

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of:

AM53CF96

K

C

/W

ALTERNATE PACKAGING OPTION

/W = Trimmed and Formed in a Tray

Blank = Molded Carrier Ring (36 mm)

TEMPERATURE RANGE

C = Commercial

PACKAGE TYPE

J = 84-Pin PLCC (PL 084)

K = 100-Pin Metric PQFP (PQR100)

DEVICE NUMBER/DESCRIPTION

Am53CF94/Am53CF96

Enhanced SCSI-2 Controller

Valid Combinations

Valid Combinations list configurations planned to be

supported in volume for this device. Consult the lo-

cal AMD sales office to confirm availability of specific

valid combinations or to check on newly released

combinations.

AM53CF94

AM53CF96

JC

KC, KC/W

8

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

SCSI OUTPUT CONNECTIONS

SD 7–0, P

Am53CF94

SDC 7–0, P

SEL, BSY, REQ, ACK, RST

SELC, BSYC, REQC,

ACKC, RSTC

MSG, C/D, I/O, ATN

17348B-11

Am53CF94 Single Ended SCSI Bus Configuration

9

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

SCSI OUTPUT CONNECTIONS

SD 7–0, P

Am53CF96

SDC 7–0, P

SEL, BSY, REQ, ACK, RST

SELC, BSYC, REQC,

ACKC, RSTC

MSG, C/D, I/O, ATN

DFMODE

V_CC

17348B-12

Am53CF96 Single Ended SCSI Bus Configuration

SD 7–0, P

DT

Am53CF96

SDC 7–0, P

SEL, BSY, RST

SELC, BSYC, RSTC

DT

ATN, ACK

ISEL

MSG, C/D, I/O, REQ

TSEL

DFMODE

17348B-13

Am53CF96 Differential SCSI Bus Configuration

10

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

TSEL

MSG

– MSG

+ MSG

TSEL

C/D

– C/D

+ C/D

SDC 0

SD 0

TSEL

– SD 0

+ SD 0

I/O

– I/O

+ I/O

SDC 1

SD 1

75ALS170

– SD 1

+ SD 1

ISEL

SDC 2

SD 2

ATN

– ATN

+ ATN

– SD 2

+ SD 2

75ALS170

SDC 3

SD 3

– SD 3

+ SD 3

SDC 4

SD 4

75ALS170

– SD 4

+ SD 4

Vcc

SELC

GND

SDC 5

SD 5

– SEL

+ SEL

– SD 5

+ SD 5

SEL

BSYC

GND

75ALS170

– BSY

+ BSY

BSY

SDC 6

SD 6

RSTC

GND

– SD 6

+ SD 6

– RST

+ RST

RST

GND

SDC 7

SD 7

75ALS171

– SD 7

+ SD 7

Vcc

TSEL

REQC

SDC P

SD P

– REQ

+ REQ

REQ

– SD P

+ SD P

ISEL

ACKC

75ALS170

– ACK

+ ACK

ACK

GND

75ALS171

17348B-14

Differential Transceiver Connections for the Differential SCSI Bus Configuration

Using 75ALS170 and 75ALS171 Transceivers

11

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

TSEL

SDC 0

SD 0

MSG

– SD 0

+ SD 0

– MSG

+ MSG

MSG

SD 0

SDC 0

TSEL

SDC 1

SD 1

C/D

– SD 1

+ SD 1

– C/D

+ C/D

C/D

SD 1

SDC 1

TSEL

SDC 2

SD 2

I/O

– SD 2

+ SD 2

– I/O

+ I/O

SD 2

I/O

TSEL

SDC 2

SDC 3

SD 3

ISEL

ATN

– SD 3

+ SD 3

– ATN

+ ATN

ATN

SD 3

ISEL

SDC 3

SELC

SDC 4

SD 4

GND

– SD 4

+ SD 4

– SEL

+ SEL

SEL

SD 4

GND

SDC 4

SDC 5

SD 5

BSYC

GND

– SD 5

+ SD 5

– BSY

+ BSY

SD 5

BSY

SDC 5

GND

SDC 6

SD 6

RSTC

GND

– RST

+ RST

– SD 6

+ SD 6

SD 6

RST

SDC 6

GND

SDC 7

SD 7

TSEL

REQC

– REQ

+ REQ

– SD 7

+ SD 7

REQ

SD 7

GND

SDC 7

SDC P

SD P

ISEL

ACKC

– SD P

+ SD P

– ACK

+ ACK

SD P

ACK

SDC P

GND

17348B-15

Differential Transceiver Connections for the Differential

SCSI Bus Configuration Using 75176A Transceiver

12

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

PIN DESCRIPTION

Host Interface Signals

AS0 [A0]

Address Status [Address 0]

(Input, Active High)

DMA 15–0

Data/DMA Bus

This is a dual function input. When the device is config-

ured for the dual bus mode (two buses, multiplexed and

byte control), this input acts as AS0. As AS0, this input

works in conjunction with BHE to indicate the lines on

which data transfer will take place. When the device is

configured for all other bus modes, this input acts as A0.

As A0, this input is the zeroth bit of the address bus.

(Input/Output, Active High, Internal Pull-up)

The configuration of this bus depends on the Bus Mode

1–0 (BUSMD 1–0) inputs. When the device is config-

ured for single bus operation, the host can access the

internal register set on the lower eight lines while DMA

accesses can be made to the FIFO using the entire bus.

When using the Byte Mode via the BHE and A0 inputs

the data can be transferred on either the upper or lower

half of the DMA 15–0 bus.

The following is the decoding for the BHE and AS0

inputs:

BHE

AS0 Bus Used

DMAP 1–0

Data/DMA Parity Bus

(Input/Output, Active High, Internal Pull-up)

1

0

1

0

1

0

Upper Bus – DMA 15–8, DMAP 1

Full Bus – DMA 15–0, DMAP 1–0

Reserved

These lines are odd parity for the DMA 15–0 bus. DMAP

1 is the parity for the upper half of the bus (DMA 15–8)

and DMAP 0 is the parity for the lower half of the bus

(DMA 7–0).

Lower Bus – DMA 7–0, DMAP 0

ALE [A3]

Address Latch Enable [Address 3]

(Input, Active High)

DREQ

DMA Request

(Output, Active High, Hi-Z)

This is a dual function input. When the device is config-

ured for the dual bus mode (two buses, multiplexed and

byte control), this input acts as ALE. As ALE, this input

latches the address on the AD 7–0 bus on its low going

edge. When the device is configured for all other bus

modes, this input acts as A3. As A3, this input is the third

bit of the address bus.

This output signal to the DMA controller will be active

during DMA read and write cycles. During a DMA read

cycle it will be active as long as there is a word (or a byte

in the byte mode) in the FIFO to be transferred to mem-

ory. During a DMA write cycle it will be active as long as

there is an empty space for a word (or a byte in mode 2)

in the FIFO.

DMARD [A2]

DMA Read [Address 2]

(Input, Active Low [Active High])

DACK

DMA Acknowledge

(Input, Active Low)

This is a dual function input. When the device is config-

ured for the dual bus mode (two buses, multiplexed and

byte control), this input acts as DMARD. As DMARD,

this input is the read signal for the DMA 15–0 bus. When

the device is configured for all other bus modes, this in-

put acts as A2. As A2, this input is the second bit of the

address bus.

This input signal from the DMA controller will be active

during DMA read and write cycles. The DACK signal is

used to access the DMA FIFO only and should never be

active simultaneously with the CS signal, which ac-

cesses the registers only.

AD 7–0

Host Address Data Bus

(Input/Output, Active High, Internal Pull-up)

BHE [A1]

Bus High Enable [Address 1]

(Input, Active High)

This bus is used only in the dual bus mode. This bus al-

lows the host processor to access the device’s internal

registers while the DMA bus is transferring data. When

using multiplexed bus, these lines can be used for ad-

dress and data. When using non multiplexed bus these

lines can be used for the data only.

This is a dual function input. When the device is config-

ured for the dual bus mode (two buses, multiplexed and

byte control), this input acts as BHE. As BHE, this input

works in conjunction with AS0 to indicate the lines on

which data transfer will take place. When the device is

configured for all other bus modes this input acts as A1.

As A1, this input is the first bit of the address bus.

13

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

DMAWR

DMA Write

BUSMD 1–0

Bus Mode

(Input, Active Low)

(Input, Active High)

This signal writes the data onto the DMA 15–0 and

DMAP 1–0 bus into the internal FIFO when DACK is

also active. When in the single bus mode this signal

must be tied to the WR signal.

These inputs configure the device for single bus or dual

bus operation and the DMA bus width.

BUSMD1 BUSMD0 Bus Configuration

1

0

1

0

1

0

Two buses: 8-bit Host Bus

and 16-bit DMA Bus

Register Address on A 3–0

and Data on AD Bus

RD

Read

(Input Active Low)

This signal reads the internal device registers and

places their contents on the data bus, when either CS

signal or DACK signal is active.

Two buses: Multiplexed

and byte control

Register Address on AD 3–0

and Data on AD Bus

WR

Write

(Input Active Low)

Single bus: 8-bit Host Bus

and 16-bit DMA Bus

Register Address on A 3–0

and Data on DMA Bus

This signal writes the internal device registers with the

value present on the (AD 7–0 bus or the DMA 15–0 and

DMAP 1–0 bus), when the CS signal is also active.

Single bus: 8-bit Host Bus

and 8-bit DMA Bus

Register Address on A 3–0

and Data on DMA Bus

CS

Chip Select

(Input Active Low)

This signal enables the read and write of the device reg-

isters. CS enables access to any register (including the

FIFO) while the DACK enables access only to the FIFO.

CS and DACK should never be active simultaneously in

the single bus mode, they may however be active simul-

taneouslyinthedualbusmodeprovidedtheCSsignalis

not enabling access to the FIFO.

CLK

Clock

(Input)

Clock input used to generate all the internal device tim-

ings. The maximum frequency of this input is 40 MHz.

and a minimum of 10 MHz to maintain the SCSI bus

timings.

INT

Interrupt

(Output, Active Low, Open Drain)

RESET

Reset

(Input, Active High)

This signal is a non-maskable interrupt flag to the host

processor. This signal is latched on the output on the

highgoingedgeoftheclock. Thisflagmaybeclearedby

reading the Interrupt Status Register (ISTAT) or by per-

forming a device reset (hard or soft). This flag is not

cleared by a SCSI reset.

This input when active resets the device. The RESET in-

put must be active for at least two CLK periods after the

voltage on the power inputs have reached Vcc

minimum.

SCSI Interface Signals

DFMODE

Differential Mode

(Input, Active Low)

SD 7–0

SCSI Data

This input is available only on the Am53CF96. This input

configures the SCSI bus to either single ended or differ-

ential mode. When this input is active, the device oper-

ates in the differential SCSI mode. The SCSI data is

available on the SD 7–0 lines and the high active trans-

ceiver enables on the SDC 7–0 outputs. When this input

is inactive, the device operates in the single ended SCSI

mode. The SCSI input data is available on SD 7–0 lines

and the output data is available on SDC 7–0 lines. In the

single ended SCSI mode, the SD 7–0 and the SDC 7–0

buses can be tied together externally.

(Input/Output, Active Low, Schmitt Trigger)

When the device is configured in the Single Ended SCSI

Mode (DFMODE inactive) these pins are defined as in-

puts for the SCSI data bus. When the device is config-

ured in the Differential SCSI Mode (DFMODE active)

these pins are defined as bidirectional SCSI data bus.

14

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

be asserted when the Initiator detects a parity error or it

can be asserted via certain Initiator commands.

SD P

SCSI Data Parity

(Input/Output, Active Low, Schmitt Trigger)

BSY

Busy

When the device is configured in the Single Ended SCSI

Mode (DFMODEinactive) this pin is defined as the input

for the SCSI data parity. When the device is configured

in the Differential SCSI Mode (DFMODE active) this pin

is defined as bidirectional SCSI data parity.

(Input, Active Low, Schmitt Trigger)

This is a SCSI input signal with a Schmitt trigger.

SEL

SDC 7–0

SCSI Data Control

Select

(Input, Active Low, Schmitt Trigger)

(Output, Active Low, Open Drain)

This is a SCSI input signal with a Schmitt trigger.

When the device is configured in the Single Ended SCSI

Mode (DFMODEinactive) these pins are defined as out-

puts for the SCSI data bus. When the device is config-

ured in the Differential SCSI Mode (DFMODE active)

these pins are defined as direction controls for the exter-

nal differential transceivers. In this mode, a signal high

state corresponds to an output to the SCSI bus and a

low state corresponds to an input from the SCSI bus.

RST

Reset

(Input, Active Low, Schmitt Trigger)

This is a SCSI input signal with a Schmitt trigger.

REQ

Request

(Input, Active Low, Schmitt Trigger)

SDC P

SCSI Data Control Parity

This is a SCSI input signal with a Schmitt trigger.

(Output, Active Low, Open Drain)

ACK

Acknowledge

(Input, Active Low, Schmitt Trigger)

When the device is configured in the Single Ended SCSI

Mode (DFMODE inactive) this pin is defined as an out-

put for the SCSI data parity. When the device is config-

ured in the Differential SCSI Mode (DFMODE active)

this pin is defined as the direction control for the external

differential transceiver. In this mode, a signal high state

corresponds to an output to the SCSI bus and a low

state corresponds to an input from the SCSI bus.

This is a SCSI input signal with a Schmitt trigger.

BSYC

Busy Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. When the device

isconfiguredintheSingleEndedSCSIMode(DFMODE

inactive) this pin is defined as a BSY output for the SCSI

bus. When the device is configured in the Differential

SCSI Mode (DFMODE active) this pin is defined as the

direction control for the external differential transceiver.

In this mode, a signal high state corresponds to an out-

put to the SCSI bus and a low state corresponds to an

input from the SCSI bus.

MSG

Message

(Input/Output, Active Low, Schmitt Trigger)

This is a bidirectional signal with 48 mA output driver.

It is an output in the Target mode and a Schmitt trigger

input in the Initiator mode.

C/D

Command/Data

(Input/Output, Schmitt Trigger)

SELC

Select Control

(Output, Active Low, Open Drain)

This is a bidirectional signal with 48 mA output driver.

It is an output in the Target mode and a Schmitt trigger

input in the Initiator mode.

This is a SCSI output with 48 mA drive. When the device

isconfiguredintheSingleEndedSCSIMode(DFMODE

inactive) this pin is defined as a SEL output for the SCSI

bus. When the device is configured in the Differential

SCSI Mode (DFMODE active) this pin is defined as the

direction control for the external differential transceiver.

In this mode, a signal high state corresponds to an out-

put to the SCSI bus and a low state corresponds to an

input from the SCSI bus.

I/O

Input/Output

(Input/Output, Schmitt Trigger)

This is a bidirectional signal with 48 mA output driver.

It is an output in the Target mode and a Schmitt trigger

input in the Initiator mode.

ATN

Attention

(Input/Output, Active Low, Schmitt Trigger)

This signal is a 48 mA output in the Initiator mode and a

Schmitt trigger input in the Target mode. This signal will

15

Am53CF94/Am53CF96

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P R E L I M I N A R Y

RSTC

Reset Control

ACKC

Acknowledge Control

(Output, Active Low, Open Drain)

This is a SCSI output with 48 mA drive. The Reset SCSI

command will cause the device to drive RSTC active for

25 ms–40 ms, which will depend on the CLK frequency

and the conversion factor. When the device is config-

ured in the Single Ended SCSI Mode (DFMODE inac-

tive) this pin is defined as a RSToutput for the SCSI bus.

When the device is configured in the Differential SCSI

Mode (DFMODE active) this pin is defined as the direc-

tion control for the external differential transceiver. In

this mode, a signal high state corresponds to an output

to the SCSI bus and a low state corresponds to an input

from the SCSI bus.

This is a SCSI output with 48 mA drive. This signal is ac-

tivated only in the Initiator mode.

ISEL

Initiator Select

(Output, Active High)

This signal is available on the Am53CF96 only. This sig-

nal is active whenever the device is in the Initiator mode.

In the differential mode this signal is used to enable the

Initiator signals ACKC and ATN and the device also

drives these signals.

TSEL

Target Select

(Output, Active High)

REQC

Request Control

(Output, Active Low, Open Drain)

This signal is available on the Am53CF96 only. This sig-

nal is active whenever the device is in the Target mode.

In the differential mode this signal is used to enable the

Target signals REQC, MSG, C/Dand I/Oand the device

also drives these signals.

This is a SCSI output with 48 mA drive. This signal is

activated only in the Target mode.

FUNCTIONAL DESCRIPTION

Register Map

Address

(Hex.) Operation Register

Address

(Hex.) Operation Register

00

01

Read

Write

Read

Write

Current Transfer Count

Register Low

Start Transfer Count Register

Low

Current Transfer Count

Register Middle

Start Transfer Count Register

Middle

07

Read

Current FIFO/Internal State

Register

Synchronous Offset Register

07

08

09

0A

0B

0C

0D

0E

Write

Read/Write Control Register 1

Write

Clock Factor Register

Forced Test Mode Register

Read/Write Control Register 2

Read/Write Control Register 3

Read/Write Control Register 4

02

03

04

05

06

Read/Write FIFO Register

Read/Write Command Register

Read

Write

Current Transfer Count

Register High

Start Transfer Count

Register High

Read

Write

Read

Write

Read

Write

Status Register

SCSI Destination ID Register

Interrupt Status Register

SCSI Timeout Register

Internal State Register

Synchronous Transfer Period

Register

0E

0F

Data Alignment Register

Note:

Not all registers in this device are both readable and writable. Some read only registers share the same address with write only

registers. The registers can be accessed by asserting the CSsignal and then asserting either RD or WRsignal depending on the

operation to be performed. Only the FIFO Register can be accessed by asserting either CS or DACK in conjunction with RD and

WR signals or DMARD and DMAWR signals. The register address inputs are ignored when DACK is used but must be valid

when CS is used.

16

Am53CF94/Am53CF96

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AMD

In the Initiator mode, the counter is decremented by the

active edge of DACK during the Synchronous Data-In

phase or by ACKC during the Asynchronous Data-In

phase and by DACK during the Data-Out phase.

Current Transfer Count Register

(00H, 01H, 0EH) Read Only

Current Transfer Count Register

CTCREG

Address: 00H, 01H, 0EH

Type: Read

Start Transfer Count Register

(00H, 01H, 0EH) Write Only

23

22

21

20

19

18

17 16

CRVL23 CRVL22 CRVL21 CRVL20 CRVL19 CRVL18 CRVL17 CRVL16

Start Transfer Count Register

STCREG

Address: 00H–01H

Type: Write

x

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

STVL23 STVL22 STVL21 STVL20 STVL19 STVL18 STVL17 STVL16

CRVL15 CRVL14 CRVL13 CRVL12 CRVL11 CRVL10 CRVL9

CRVL8

x

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

STVL15 STVL14 STVL13 STVL12 STVL11 STVL10 STVL9 STVL8

CRVL7

CRVL6 CRVL5

CRVL4

CRVL3

CRVL2 CRVL1

CRVL0

x

7

6

5

4

3

2

1

0

17348B-16

STVL7 STVL6

STVL5

STVL4 STVL3 STVL2

STVL1 STVL0

CTCREG – Bits 23:0 – CRVL 23:0 – Current

Value 23:0

x

17348B-17

This is a three-byte register which decrements to keep

track of the number of bytes transferred during a DMA

transfer. Reading these registers returns the current

value of the counter. The counter will decrement by one

foreverybyteandbytwoforeverywordtransferred. The

transaction is complete when the count reaches zero,

and bit 4 of the Status Register (04H) is set. Should the

sequence terminate early, the sum of the values in the

Current FIFO (07H) and the Current Transfer Count

Register reflect the number of bytes remaining.

STCREG – Bits 15:0 – STVL 15:0 – Start Value 15:0

This is a three-byte register which contains the number

of bytes to be transferred during a DMA operation. The

value in the Start Transfer Count Register must be pro-

grammed prior to command execution.

The least significant byte is located at address 00H, the

middle byte is located at address 01H, and the most sig-

nificant byte is located at address 0EH. Register 0EH

extends the total width of the register from 16 to 24 bits,

and is only enabled when the Enable Features bit (bit 6)

of Control Register Two is set to a value of ‘1’. This sets

the maximum transfer count to 16.78 MBytes. When a

value of ‘0’ is written to these registers, the transfer

count will be set to the maximum. A DMA NOP com-

mand must be issued before the transfer counter values

can be written to 00H, 01H, and 0EH.

The least significant byte is located at address 00H, the

middle byte is located at address 01H, and the most sig-

nificant byte is located at address 0EH. Register 0EH

extends the total width of the register from 16 to 24

bits, and is only enabled when the Enable Features

bit (bit 6) of Control Register Two is set to a value

of ‘1’.

These registers are automatically loaded with the val-

ues in the Start Transfer Count Register every time a

DMA command is issued. However, following a chip or

power on reset, up until the time register 0EH is loaded,

the Am53CF94/96’s part-unique ID can be obtained by

reading register 0EH.

These registers retain their value until overwritten, and

are therefore unaffected by a hardware or software re-

set. This reduces programming redundancy since it is

no longer necessary to reprogram the count for subse-

quent DMA transfers of the same size.

In the Target mode, this counter is decremented by the

active edge of DACK during the Data-In phase and by

REQC during the Data-Out phase.

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Am53CF94/Am53CF96

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P R E L I M I N A R Y

Commands to the ESC are issued by writing to this reg-

FIFO Register (02H) Read/Write

ister which is two bytes deep. Commands may be

queued, and will be read from the bottom of the queue.

At the completion of the bottom command, the top com-

mand, if present, will drop to the bottom of the register to

begin execution. All commands are executed within six

clock cycles of dropping to the bottom of the Command

Register, with the exception of the Reset SCSI Bus, Re-

set Device, and DMA Stop commands. These com-

mands are not queued and are executed within four

clock cycles of being loaded into the top this register.

FIFO Register

FFREG

Address: 02H

Type: Read/Write

7

6

5

4

3

2

1

0

FF7

FF6

FF5

FF4

FF3

FF2

FF1

FF0

0

17348B-18

FFREG – Bits 7:0 – FF 7:0 – FIFO 7:0

Interrupts are sometimes generated upon command

completion. Should both commands generate inter-

rupts, and the first interrupt has not been serviced, the

interrupt from the second (top) command will bestacked

behind the first. The Status Register, Interrupt Register,

and Internal State Register will be updated to apply to

the second interrupt after the microprocessor services

the first interrupt.

The FIFO on the Am53CF94/96 is 16 bytes deep and is

used to transfer SCSI data to and from the ESC. The

bottom of the FIFO may be accessed via a read or write

to this register. This is the only register that can also be

accessed by DACK along with DMARD or DMAWR or

with REQ or ACK. This register is reset to zero by hard-

ware or software reset, or at the start of a selection or

reselection sequence, or if Clear FIFO command is

issued.

Reading this register will return the command currently

being executed (or the last command executed if there

are no pending commands). When this register is

cleared, existing commands will be terminated and any

queued commands will be ignored. However, it does not

reset the register bits to ‘00H’.

Command Register (03H) Read/Write

Command Register

CMDREG

Address: 03H

Type: Read/Write

CMDREG – Bit 7 – DMA – Direct Memory Access

7

6

5

4

3

2

1

0

When set, this bit notifies the device that the command

is a DMA instruction, when reset it is a non-DMA instruc-

tion. For DMA instructions the Current Transfer Count

Register (CTCREG) will be loaded with the contents of

the Start Transfer Count Register (STCREG). The data

is then transferred and the CTCREG is decremented for

each byte until it reaches zero.

DMA

CMD6

CMD5

CMD4

CMD3

CMD2

CMD1

CMD0

x

Command 6:0

CMDREG – Bits 6:0 – CMD 6:0 – Command 6:0

These command bits decode the commands that the

device needs to perform. There are a total of 31 com-

mands grouped into four categories. The groups are

Initiator Commands, Target Commands, Selection/

Reselection Commands and General Purpose Com-

mands.

Direct Memory

Access

17348B-19

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Am53CF94/Am53CF96

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AMD

Initiator Commands

CMD6 CMD5

CMD4

CMD3

CMD2

CMD1

CMD0 Command

0

1

0

1

0

1

0

1

0

1

0

1

Information Transfer

Initiator Command Complete Steps

Message Accepted

Transfer Pad Bytes

*Set ATN

*Reset ATN

Target Commands

CMD6 CMD5

CMD4

CMD3

CMD2

CMD1

CMD0 Command

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Send Message

Send Status

Send Data

Disconnect Steps

Terminate Steps

Target Command Complete Steps

*Disconnect

Receive Message Steps

Receive Command

Receive Data

Receive Command Steps

*DMA Stop

Access FIFO Command

Idle Commands

CMD6 CMD5

CMD4

CMD3

CMD2

CMD1

CMD0 Command

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reselect Steps

Select without ATN Steps

Select with ATN Steps

Select with ATN and Stop Steps

*Enable Selection/Reselection

Disable Selection/Reselection

Select with ATN3 Steps

Reselect with ATN3 Steps

General Commands

CMD6 CMD5

CMD4

CMD3

CMD2

CMD1

CMD0 Command

0

1

0

1

0

1

*No Operation

*Clear FIFO

*Reset Device

Reset SCSI Bus

Note:

*Denotes commands which do not generate interrupts upon completion.

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P R E L I M I N A R Y

Status Register (04H) Read

Status Register

STATREG

Address: 04H

Type: Read

7

6

5

4

3

2

1

0

INT

IOE

PE

CTZ

GCV

MSG

C/D

I/O

0

x

Input/Output

Command/Data

Message

Group Code Valid

Count to Zero

Parity Error

Illegal Operation Error

Interrupt

17348B-20

This read only register contains flags to indicate the

status and phase of the SCSI transactions. It indicates

whether an interrupt or error condition exists. It should

be read every time the host is interrupted to determine

which device is asserting an interrupt. If the ENF bit is

set (CNTLREG2, bit 6), the SCSI bus phase of the last

complete command (preceding the interrupt) will be

latched until the Interrupt Status Register (INSTREG) is

read. If the ENF bit is disabled, this register will reflect

the current bus phase. If command stacking is used, two

interrupts might occur. Reading this register will clear

the status information for the first interrupt and update

the Status Register for the second interrupt.

(CNTLREG2). The combination of enabled options will

determine if parity is generated from the data bytes

internally by the chip, or if it is passed between buffer

and SCSI Bus without being altered. Detection of a

parity error condition will not cause an interrupt but will

be reported with other interrupt causing conditions.

This bit will be cleared by reading the Interrupt Status

Register (INSTREG) or by a hard or soft reset.

STATREG – Bit 4 – CTZ – Count To Zero

The CTZ bit is set when the Current Transfer Count

Register (CTCREG) has counted down to zero. This bit

will be reset when the CTCREG is written with a non-

zero value.

STATREG – Bit 7 – INT – Interrupt

Reading the Interrupt Status Register (INSTREG) will

not affect this bit. This bit will however be cleared by a

hard or soft reset.

The INT bit is set when the device asserts the interrupt

output. This bit will be cleared by a hardware or software

reset. Reading the Interrupt Status Register (INSTREG)

will deassert the interrupt output and also clear this bit.

Note:

A non-DMA NOP will not reset the CTZ bit since it does

not load the CTCREG. However, a DMA NOP will reset

this bit since it loads the CTCREG.

STATREG – Bit 6 – IOE – Illegal Operation Error

The IOE bit is set when an illegal operation is attempted.

This condition will not cause an interrupt, it will be de-

tected by reading the Status Register (STATREG) while

servicing another interrupt. The following conditions will

cause the IOE bit to be set:

STATREG – Bit 3 – GCV – Group Code Valid

The GCV bit is set if the group code field in the Com-

mand Descriptor Block (CDB) is one that is defined by

the ANSI Committee in their document X3.131 – 1986. If

the SCSI-2 Feature Enable (S2FE) bit in the Control

Register 2 (CNTLREG2) is set, Group 2 commands will

betreatedastenbytecommandsandtheGCVbitwillbe

set. If S2FE is reset then Group 2 commands will be

treated as reserved commands. Group 3 and 4 com-

mands will always be considered reserved commands.

The device will treat all reserved commands as six byte

commands. Group 6 commands will always be treated

as vendor unique six byte commands and Group 7 com-

mands will always be treated as vendor unique ten byte

commands.

■ DMA and SCSI transfer directions are opposite.

■ FIFO overflows or data is overwritten.

■ In Initiator mode an unexpected phase change

detected during synchronous data transfer.

■ Command Register overwritten.

This bit will be cleared by reading the Interrupt Status

Register (INSTREG) or by a hard or soft reset.

STATREG – Bit 5 – PE – Parity Error

The PE bit is set if any of the parity checking options are

enabled and the device detects a parity error on bytes

sent or received on the SCSI Bus. Parity options are

controlled by bits 5:4 in Control Register One

(CNTLREG1), and by bits 2:0 in Control Register Two

The GCV bit is cleared by reading the Interrupt Status

Register (INSTREG) or by a hard or soft reset.

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Am53CF94/Am53CF96

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AMD

STATREG – Bit 2 – MSG – Message

STATREG – Bit 1 – C/D – Command/Data

STATREG – Bit 0 – I/O – Input/Output

The MSG, C/D and I/O bits together can be referred to

as the SCSI Phase bits. They indicate the phase of the

SCSI bus. These bits may be latched or unlatched

depending on whether or not the ENF bit in Control

Register Two is set.

Bit2

MSG

Bit1

C/D

Bit0

I/O

In the latched mode the SCSI phase bits are latched at

the end of a command and the latch is opened when the

Interrupt Status Register (INSTREG) is read. In the un-

latched mode, they indicate the phase of the SCSI bus

when this register is read.

SCSI Phase

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Message In

Message Out

Reserved

Status

Command

Data_In

Data_Out

SCSI Destination ID Register (04H) Write

SCSI Destination ID Register

SDIDREG

Address: 04H

Type: Write

7

6

5

4

3

2

1

0

RES

DID2

DID1

DID0

0

x

SCSI Destination ID 2:0

Reserved

17348B-21

SDIDREG – Bits 7:3 – RES – Reserved

DID2

DID1

DID0

SCSI ID

SDIDREG – Bits 2:0 – DID 2:0 – Destination ID 2:0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

7

6

5

4

3

2

1

0

The DID 2:0 bits are the encoded SCSI ID of the device

on the SCSI bus which needs to be selected or

reselected.

Atpower-upthestateofthesebitsisundefined. TheDID

2:0 bits are not affected by reset.

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Am53CF94/Am53CF96

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P R E L I M I N A R Y

Interrupt Status Register (05H) Read

Interrupt Status Register

INSTREG

Address: 05h

Type: READ

7

6

5

4

3

2

1

0

SRST

ICMD

DIS

SR

SO

RESEL

SELA

SEL

0

Selected

Selected with Attention

Reselected

Successful Operation

Service Request

Disconnected

Invalid Command

SCSI Reset

17348B-22

The Interrupt Status Register (INSTREG) will indicate

the reason for the interrupt. This register is used with the

Status Register (STATREG) and Internal State Register

(ISREG) to determine the reason for the interrupt.

Reading the INSTREG will clear all three registers.

Therefore the Status Register (STATREG) and Internal

State Register (ISREG) should be examined prior to

reading the INSTREG.

request. In the Target mode this bit will be set when the

Initiator asserts the ATN signal. In the Initiator mode this

bit is set when a Command Steps Successfully Com-

pleted Command is issued.

INSTREG – Bit 3 – SO – Successful Operation

The SO bit can be set in the Target or the Initiator mode

when an operation has successfully completed. In the

Target mode this bit will be set when any Target or Idle

state command is completed. In the Initiator mode this

bit is set after a Target has been successfully selected,

after a command has successfully completed and after

an information transfer command when the Target

requests a Message In phase.

INSTREG – Bit 7 – SRST – SCSI Reset

The SRST bit will be set if a SCSI Reset is detected and

SCSI reset reporting is enabled via the DISR (bit 6) of

Control Register One (CNTLREG1).

INSTREG – Bit 6 – ICMD – Invalid Command

INSTREG – Bit 2 – RESEL – Reselected

The ICMD bit will be set if the device detects an illegal

command code. This bit is also set if a command code is

detected from a mode that is different from the mode the

device is currently in. Once this bit is set, and invalid

command interrupt will be generated.

The RESEL bit is set at the end of the reselection phase

indicating that the device has been reselected as an

Initiator.

INSTREG – Bit 1 – SELA – Selected with Attention

INSTREG – Bit 5 – DIS – Disconnected

TheSELAbitissetattheendoftheselectionphaseindi-

cating that the device has been selected as a Target by

the Initiator and that the ATN signal was active during

the selection.

The DIS bit can be set in the Target or the Initiator mode

when the device disconnects from the SCSI bus. In the

Target mode this bit will be set if a Terminate or a Com-

mand Complete steps causes the device to disconnect

from the SCSI bus. In the Initiator mode this bit will be

set if the Target disconnects; while in Idle mode, this bit

will be set if a selection or reselection timeout occurs.

INSTREG – Bit 0 – SEL – Selected

The SEL bit is set at the end of the selection phase indi-

cating that the device has been selected as a Target by

the Initiator and that the ATN signal was inactive during

the selection.

INSTREG – Bit 4 – SR – Service Request

The SR bit can be set in the Target or the Initiator mode

when another device on the SCSI bus has a service

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Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

STIMREG – Bits 7:0 – STIM 7:0 – SCSI Timer 7:0

SCSI Timeout Register (05H) Write

The value loaded in STIM 7:0 can be calculated as

shown below:

SCSI Timeout Register

STIMREG

Address: 05H

Type: Write

STIM 7:0 =

7

6

5

4

3

2

1

0

[(SCSI Time Out) (Clock Frequency) / (8192 (Clock

Factor))]

STIM7

STIM6

STIM5

STIM4

STIM3

STIM2

STIM1

STIM0

Example:

x

SCSI Time Out (in seconds): 250 ms. (Recommended

by the ANSI Standard) = 250 x 10–3 s.

17348B-23

This register determines how long the Initiator (Target)

will wait for a response to a Selection (Reselection)

before timing out. It should be set to yield 250 ms to

comply with ANSI standards for SCSI, but the maximum

time out period may be calculated using the following

formulas.

Clock Frequency: 20 MHz. (assume) = 20 x 106 Hz.

Clock Factor: CLKF 2:0 from Clock ConversionRegister

(09H) = 5

STIM 7:0 = (250 x 10–3) X (20 x 106) / (8192 (5)) = 122

decimal

Note: A hardware reset will clear this register.

Internal State Register (06H) Read

Internal State Register

ISREG

Address: 06H

Type: Read

7

6

5

4

3

2

1

0

RES

IS2

IS1

IS0

SOF

x

0

Internal State 2:0

Synchronous Offset Flag

Reserved

17348B-24

The Internal State Register (ISREG) tracks theprogress

of a sequence-type command. It is updated after each

successful completion of an intermediate operation. If

an error occurs, the host can read this register to

determine the point where the command failed and take

the necessary procedure for recovery. Reading the

Interrupt Status Register (INSTREG) while an interrupt

is pending will clear this register. A hard or soft reset will

also zero this register .

ISREG – Bit 3 – SOF – Synchronous Offset Flag

TheSOFisresetwhentheSynchronousOffsetRegister

(SOFREG) has reached its maximum value.

Note:

The SOF bit is active Low.

ISREG – Bits 2:0 – IS 2:0 – Internal State 2:0

The IS 2:0 bits along with the Interrupt Status Register

(INSTREG) indicates the status of the successfully

completed intermediate operation. Refer to the Status

Decode section for more details.

ISREG – Bits 7:4 – RES – Reserved

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Am53CF94/Am53CF96

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P R E L I M I N A R Y

Initiator Select without ATN Steps

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

Bits 7:0 (Hex)

0

4

3

20

18

Arbitration steps completed. Selection time-out occurred, then disconnected

Selection without ATN steps fully executed

Sequence halted during command transfer due to premature phase change

(Target)

2

18

Arbitration and selection completed; sequence halted because Target failed to

assert command phase

Initiator Select with ATN Steps

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

0

Bits 7:0 (Hex)

20

Arbitration steps completed. Selection time-out occurred then disconnected

4

3

18

Selection with ATN steps fully executed

Sequence halted during command transfer due to premature phase change;

some CDB bytes may not have been sent; check FIFO flags

2

0

18

Message out completed; sent one message byte with ATN true, then released

ATN; sequence halted because Target failed to assert command phase after

message byte was sent

Arbitration and selection completed; sequence halted because Target did not

assert message out phase; ATN still driven by ESC

Initiator Select with ATN3 Steps

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

Bits 7:0 (Hex)

0

4

3

20

18

Arbitration steps completed. Selection time-out occurred then disconnected

Selection with ATN3 steps fully executed

Sequence halted during command transfer due to premature phase change;

some CDB bytes may not have been sent; check FIFO flags

2

0

18

One, two, or three message bytes sent; sequence halted because Target failed

to assert command phase after third message byte, or prematurely released

message out phase; ATN released only if third message byte was sent

Arbitration and selection completed; sequence halted because Target failed to

assert message out phase; ATN still driven by ESC

Initiator Select with ATN and Stop Steps

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

Bits 7:0 (Hex)

0

20

18

Arbitration steps completed. Selection time-out occurred then disconnected

Arbitration and selection completed; sequence halted because Target failed to

assert message out phase; ATN still asserted by ESC

1

18

Message out completed; one message byte sent; ATN on

24

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Target Select without ATN Steps

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Selected; received entire CDB; check group code valid bit

Sequence halted in command phase due to parity error; some CDB bytes may

not have been received; check FIFO flags; Initiator asserted ATN in command

phase

Bits 2:0 (Hex)

Bits 7:0 (Hex)

2

1

11

2

1

01

Selected; received entire CDB; check group code valid bit

Sequence halted in command phase because of parity error; some CDB bytes

may not have been received; check FIFO flags

0

01

Selected; loaded bus ID into FIFO; null-byte message loaded into FIFO

Target Select with ATN Steps, SCSI-2 Bit NOT SET

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

2

Bits 7:0 (Hex)

12

Selection complete; received one message byte and entire CDB; Initiator as-

serted ATN during command phase

1

0

12

Halted in command phase; parity error and ATN true

Selected with ATN; stored bus ID and one message byte; sequence halted be-

cause ATN remained true after first message byte

2

1

02

Selection completed; received one message byte and the entire CDB

Sequence halted in command phase because of parity error; some CDB bytes

not received; check group code valid bit and FIFO flags

0

02

Selected with ATN; stored bus ID and one message byte; sequence halted be-

cause of parity error or invalid ID message

Target Select with ATN Steps, SCSI-2 Bit SET

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

Bits 7:0 (Hex)

6

5

4

2

12

Selection completed; received three message bytes and entire CDB. ATN is true

Halted in command phase; parity error and ATN true

ATN remained true after third message byte

Selection completed; Initiator deasserts ATN after receipt of one message byte;

entire CDB received. ATN asserted during command phase

1

0

12

Sequence halted during command phase because of parity error; one message

byte received; some bytes of CDB not received; parity error and ATN true

Selected with ATN; stored bus ID and one message byte; sequence halted be-

cause of parity error or invalid ID message; ATN is true

6

5

02

Selection completed; received three message bytes and the entire CDB

Received three message bytes then halted in command phase because of parity

error; some CDB bytes not received; check group code valid bit and FIFO flags

4

2

02

Parity error during second or third message byte

Selection completed; Initiator deasserts ATN after receipt of one message byte;

entire CDB received

1

0

02

Sequence halted during command phase because of parity error; one message

byte received; some bytes of CDB not received; check FIFO flags and group

code valid bit

Selected with ATN; stored bus ID and one message byte; sequence halted be-

cause of parity error or invalid ID message

25

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

Target Receive Command Steps

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

Bits 7:0 (Hex)

2

1

18

Received entire CDB; Initiator asserted ATN

Sequence halted during command transfer due to parity error; ATN asserted by

Initiator

2

1

08

Received entire CDB

Sequence halted during command transfer due to parity error; check FIFO flags

Target Disconnect Steps

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

Bits 7:0 (Hex)

2

1

0

28

18

Disconnect steps fully executed; disconnected; bus is free

Two message bytes sent; sequence halted because Initiator asserted ATN

One message byte sent; sequence halted because Initiator asserted ATN

Target Terminate Steps

Internal State

Register (06H)

Interrupt Status

Register (05H)

Explanation

Bits 2:0 (Hex)

Bits 7:0 (Hex)

2

1

0

28

18

Terminate steps fully executed; disconnected; bus is free

Status and message bytes sent; sequence halted because Initiator asserted ATN

Status byte sent; sequence halted because Initiator asserted ATN

26

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Synchronous Transfer Period Register (06H) Write

Synchronous Transfer Period Register

STPREG

Address: 06H

Type: Write

7

6

5

4

3

2

1

0

RES

STP4

STP3

STP2

STP1

STP0

x

0

1

0

1

Synchronous Transfer Period 4:0

Reserved

17348B-25

The Synchronous Transfer Period Register (STPREG)

contains a 5-bit value indicating the number of clock cy-

cles each byte will take to be transferred over the SCSI

bus in synchronous mode. The minimum value allowed

is 4. The STPREG defaults to 5 clocks/byte after a hard

or soft reset.

Clocks/

STP3 STP2 STP1 STP0 Byte

STP4

0

•

0

•

1

•

0

1

0

1

•

4

5

0

1

•

6

STPREG – Bits 7:5 – RES – Reserved

7

STPREG – Bits 4:0 – STP 4:0 – Synchronous

Transfer Period 4:0

•

The STP 4:0 bits are programmed to specify the syn-

chronous transfer period or the number of clock cycles

for each byte transfer in the synchronous mode. The

minimum value for STP 4:0 is 4 clocks/byte. Missing

table entries follow the binary code.

1

0

1

0

1

0

1

0

1

0

1

0

1

31

32

33

34

35

27

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

Current FIFO/Internal State Register (07H) Read

Current FIFO/Internal State Register

CFISREG

Address: 07H

Type: Read

7

6

5

4

3

2

1

0

IS2

IS1

IS0

CF4

CF3

CF2

CF1

CF0

0

Current FIFO 4:0

Internal State 2:0

17348B-26

This register has two fields, the Current FIFO field and

the Internal State field.

transfer can continue. A zero value indicates that the

synchronous offset count has been reached and no

more data can be transferred until an acknowledge is

received.

CFISREG – Bits 7:5 – IS 2:0 – Internal State 2:0

The Internal State Register (ISREG) tracks theprogress

of a sequence-type command.

CFISREG – Bits 4:0 – CF 4:0 – Current FIFO 4:0

The CF 4:0 bits are the binary coded value of the num-

ber of bytes in the FIFO. These bits should not be read

when the device is transferring data since this count

may not be stable.

The IS 2:0 bits are duplicated from the IS 2:0 field in the

Internal State Register (ISREG) in the normal mode. If

the device is in the test mode, (see CNTLREG1, bit 3)

IS 0 is set to indicate that the offset value is non-zero.

A non-zero value indicates that synchronous data

Synchronous Offset Register (07H) Write

Synchronous Offset Register

SOFREG

Address: 07H

Type: Write

7

6

5

4

3

2

1

0

RAD1

RAD0

RAA1

RAA0

SO3

SO2

SO1

SO0

0

Synchronous Offset 3:0

REQ/ACK Assertion 1:0

REQ/ACK Deassertion 1:0

17348B-27

The Synchronous Offset Register (SOFREG) controls

REQ/ACK deassertion/assertion delay and stores a

4-bit count of the number of bytes that can be sent to

(or received from) the SCSI bus during synchronous

transfers without an ACK (or REQ). Bytes exceeding

the threshold will be sent one byte at a time

(asynchronously). That is, each byte will require an

ACK/REQ handshake. To set up an asynchronous

transfer, theSOFREGissettozero. TheSOFREGisset

to zero after a hard or soft reset.

SOFREG – Bits 7:6 – RAD 1:0

These bits may be programmed to control the deasser-

tion delay of the REQ and ACK signals during synchro-

nous transfers. Deassertion delay is expressed as input

clock cycles, and depends on the implementation of

FASTCLK. (See CNTLREG3, bit 3)

28

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Deassertion Delay

REQ/ACK

Bits 7:6 Ctrl 3, Bit 3 Input CLK Cycles

Assertion Delay

REQ/ACK

Input CLK Cycles

SOFREG FASTCLK

SOFREG

Bits 5:4

00

01

10

11

00

01

10

11

0

1

Default – 0 cycles

1/2 cycle early

1 cycle delay

1/2 cycle delay

Default – 0 cycles

1/2 cycle delay

1 cycle delay

00

01

10

11

Default – 0 cycles

1/2 cycle delay

1 cycle delay

1 1/2 cycles delay

SOFREG – Bits 3:0 – SO 3:0 – Synchronous

Offset 3:0

1 1/2 cycles delay

The SO 3:0 bits are the binary coded value of the num-

ber of bytes that can be sent to (or received from) the

SCSI bus without an ACK (or REQ) signal. A zero value

designates Asynchronous xfer, while a non-zero value

designates the number of bytes for synchronous

transfer.

SOFREG – Bits 5:4 – RAA 1:0

These bits may be programmed to control the assertion

delay of the REQ and ACK signals during synchronous

transfers. Unlike deassertion delay, assertion delay is

independent of the FASTCLK setting.

Control Register One (08H) Read/Write

Control Register One

CNTLREG1

Address: 08H

Type: Read/Write

7

6

5

4

3

2

1

0

ETM

DISR

PTE

PERE

STE

CID2

CID1

CID0

0

x

Chip ID 2:0

Self Test Enable

Parity Error Reporting Enable

Parity Test Enable

Disable Interrupt on SCSI Reset

Extended Timing Mode

17348B-28

The Control Register 1 (CNTLREG1) sets up the device

with various operating parameters.

CNTLREG1 – Bit 5 – PTE – Parity Test Enable

The PTE bit is for test use only. When the PTE bit is set

the parity on the output (SCSI or host processor) bus is

forced to the value of the MSB (bit 7) of the output data

from the internal FIFO. This allows parity errors to be

created to test the hardware and software. The PTE bit

is reset to zero by a hard or soft reset. This bit should not

be set in normal operation.

CNTLREG1 – Bit 7 – ETM – Extended Timing Mode

Enabling this feature will increase the minimum setup

time for data being transmitted on the SCSI bus. This bit

should only be set if the external cabling conditions pro-

duce SCSI timing violations. FASTCLK operation is

unaffected by this feature.

CNTLREG1 – Bit 4 – PERE – Parity Error Report-

ing Enable

CNTLREG1 – Bit 6 – DISR – Disable Interrupt on

SCSI Reset

ThePEREbitenablesthecheckingandreportingofpar-

ity errors on incoming SCSI bytes during the information

transfer phase. When the PERE bit set and bad parity is

detected, the PE bit in the STATREG is will be set but an

interrupt will not be generated. In the Initiator mode the

ATN signal will also be asserted on the SCSI bus. When

The DISR bit masks the reporting of the SCSI reset.

When the DISR bit is set and a SCSI reset is asserted,

the device will disconnect from the SCSI bus and remain

idle without interrupting the host processor. When the

DISR bit is reset and a SCSI reset is asserted the device

will respond by interrupting the host processor. The

DISR bit is reset to zero by a hard or soft reset.

29

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

the PERE bit is reset and bad parity occurs it is not de-

tected and no action is taken.

CNTLREG1 – Bit 2:0 – CID 2:0 – Chip ID 2:0

The Chip ID 2:0 bits specify the binary coded value of

the device ID on the SCSI bus. The device will arbitrate

with this ID and will respond to Selection or Reselection

to this ID. At power-up the state of these bit are unde-

fined. These bits are not affected by hard or soft reset.

CNTLREG1 – Bit 3 – STE – Self Test Enable

The STE bit is for test use only. When the STE bit is set

the device is placed in a test mode which enables the

device to access the test register at address 0AH. To re-

set this bit and to resume normal operation the device

must be issued a hard or soft reset.

Clock Factor Register (09H) Write

Clock Factor Register

CLKFREG

Address: 09H

Type: Write

7

6

5

4

3

2

1

0

RES

CLKF2

CLKF1 CLKF0

x

0

1

0

Clock Factor 2:0

Reserved

17348B-29

The Clock Factor Register (CLKFREG) must be set to

indicate the input frequency range of the device. This

valueiscrucialforcontrollingvarioustimingstomeetthe

SCSI specification. The value of bits CLKF 2:0 can be

calculated by rounding off the quotient of (Input Clock

Frequency in MHz)/(5 MHz). The device has a fre-

quency range of 10 to 40 MHz.

Input Clock

CLKF0 Frequency in MHz

CLKF2

CLKF1

0

1

0

1

0

1

0

1

0

1

0

1

0

10

10.01 to 15

15.01 to 20

20.01 to 25

25.01 to 30

30.01 to 35

35.01 to 40

CLKFREG – Bits 7:3 – RES – Reserved

CLKFREG – Bits 2:0 – CLKF 2:0 – Clock Factor 2:0

The CLKF 2:0 bits specify the binary coded value of the

clock factor. The CLKF 2:0 bits will default to a value of 2

by a hard or soft reset.

30

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Forced Test Mode Register (0AH) Write

Forced Test Mode Register

FTMREG

Address: 0AH

Type: Write

7

6

5

4

3

2

1

0

RES

FHI

FIM

FTM

x

0

Forced Target Mode

Forced Initiator Mode

Forced High Impedance Mode

Reserved

17348B-30

The Forced Test Mode Register (FTMREG) is for test

use only. The STE bit in the Control Register One

(CNTLREG1) must be set for the FTMREG to operate.

the command loaded in the Command Register). The

ESC will remain in this mode for as long as BSY is as-

serted, or until a Reset SCSI Bus or Reset Device com-

mand occurs. During normal operation this bit must not

be set.

FTMREG – Bits 7:3 – RES – Reserved

FTMREG – Bit 2 – FHI – Forced High Impedance

Mode

FTMREG – Bit 0 – FTM – Forced Target Mode

The FTM bit when set forces the ESC into the Target

mode. As a Target, the device does not assert BSY;

rather, it drives SCSI data lines, REQ, MSG, C/D or I/O

(depending on the command loaded in the Command

Register). The ESC will remain in this mode until a Dis-

connect Steps, Reset SCSI Bus, or Reset Device com-

mand occurs. During normal operation this bit must not

be set.

The FHI bit when set places all the output and bidirec-

tional pins into a high impedance state. It is zeroed by a

hardware or chip reset.

FTMREG – Bit 1 – FIM – Forced Initiator Mode

The FIM bit when set forces the ESC into the Initiator

mode. As an Initiator, the device will drive SCSI data

lines, andACKorATN(dependingonthebusphaseand

Control Register Two (0BH) Read/Write

Control Register Two

CNTLREG2

Address: 0BH

Type: Read/Write

7

6

5

4

3

2

1

0

DAE

ENF

SBO

TSDR

S2FE

ACDPE

PGRP

PGDP

0

Pass Through/Generate Data Parity

Pass Through/Generate Register Parity

Abort on Command/Data Parity Error

SCSI-2 Features Enable

Tri-State DMA Request

Select Byte Order

Enable Features

Data Alignment Enable

17348B-31

The Control Register Two (CNTLREG2) sets up the de-

vice with various operating parameters.

transferred to the memory, the upper byte being the first

byte of the first word received from the SCSI bus.

Note:

CNTLREG2 – Bit 7 – DAE – Data Alignment Enable

If an interrupt is received for a misaligned boundary on a

phase change to synchronous data the following recov-

ery procedure may be followed. The host processor

should copy the byte at the start address in the host

memory to the Data Alignment Register 0FH (DALREG)

The DAE bit is used in the Initiator Synchronous Data-In

phaseonly. WhentheDAEbitissetonebyteisreserved

at the bottom of the FIFO when the phase changes to

the Synchronous Data-In phase. The contents of this

byte will become the lower byte of the DMA word (16-bit)

31

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

and then issue an information transfer command. The

first word the device will write to the memory (via DMA)

will consists of the lower byte from the DALREG and the

upper byte from the first byte received from the

SCSI bus.

CNTLREG2 – Bit 3 – S2FE – SCSI-2 Features

Enable

The S2FE bit allows the device to recognize two SCSI-2

features: the extended message feature and the

Group 2 command recognition. (These features can

also be controlled independently by bits 6:5 in

CNTLREG3).

The DAE bit must be set before the phase changes to

theSynchronousData-In. TheDAEbitisresettozeroby

a hard or soft reset or by writing the DALREG when in-

terrupted in the Synchronous Data-In phase.

Extended Message Feature: When the S2FE bit is set

and the device is selected with attention, the device will

monitor the ATN signal at the end of the first message

byte. If the ATN signal is active, the device will request

two more message bytes before switching to the com-

mand phase. If the ATN signal is inactive the device will

switch to the Command phase. When the S2FE bit is re-

set as a Target the device will request a single message

byte. As an Initiator, the device will abort the selection

sequence if the Target does not switch to the Command

phase after receiving a single message byte.

CNTLREG2 – Bit 6 – ENF – Enable Features

A software or hardware reset will clear this bit to its de-

fault value of ‘0’; a SCSI reset will leave this bit unaf-

fected. When set to a value of ‘1’, this bit activates the

following product enhancements:

1) The Current Transfer Count Register High (0EH)

will be enabled, extending the transfer counter from

16 to 24 bits to allow for larger transfers.

Group 2 Command Recognition: When the S2FE bit is

set, the GCV (Group Code Valid) bit in the STATREG

(04H) is set, allowing the Group 2 commands to be rec-

ognized as 10 byte commands. When the S2FE bit is

reset, the GCV bit in the STATREG is not set, and the

device will interpret the Group 2 commands as reserved

commands and will request 6 byte commands.

2) Following a chip or power on reset, up until the point

where the Current Transfer Count Register High

(0EH) is loaded with a value, it is possible to read

the part-unique ID from this register.

3) The SCSI phase will be latched at the completion of

each command by bits 2:0 in the Status Register

(STATREG). When this bit is ‘0’, the Status Register

(STATREG) will reflect real-time SCSI phases.

CNTLREG2 – Bit 2 – ACDPE – Abort on Command/

Data Parity Error

4) The enable signal for the differential drivers may be

delayed to avoid bus contention on the SCSI

differential lines when the direction for I/O is

switching. When the SCSI bus changes direction

from input to output, the output drivers are not

asserted for two clock cycles to avoid bus

contention. When the bus changes from output to

input, SDC7:0 are given time to switch direction

before the SCSI drivers are asserted.

The ACDPE bit when set allows the device to abort a

command or data transfer when a parity error is de-

tected. When the ACDPE bit is reset parity error is ig-

nored.

CNTLREG2 – Bit 1 – PGRP – Pass Through/Gener-

ate Register Parity

The PGRP bit, when set, allows parity from DMAP1–0 to

pass during register writes to the FIFO. Enabling this bit

also causes parity checking as data is unloaded from

the FIFO to the SCSI bus.

CNTLREG2 – Bit 5 – SBO – Select Byte Order

The SBO bit is used only when the BUSMD 1:0 = 10 to

enable or disable the byte control on the DMA interface.

WhenSBOissetandtheBUSMD1:0=10, thebytecon-

trol inputs BHE and AS0 control the byte positions.

When SBO is reset the byte control inputs BHE and AS0

are ignored.

When this bit is reset to zero, parity is generated for reg-

ister writes to the FIFO, however no additional checking

will be done as FIFO data is unloaded to the SCSI bus

unless the PGDP bit is set.

CNTLREG2 – Bit 0 – PGDP – Pass Through/Gener-

ate Data Parity

CNTLREG2 – Bit 4 – TSDR – Tri-State DMA

Request

The PGDP bit, when set, allows parity from DMAP1–0 to

pass during DMA writes to the FIFO. Parity checking will

also be performed as data is unloaded from the FIFO to

the SCSI bus.

TheTSDRbitwhensetsendstheDREQoutputsignalto

high impedance state and the device ignores all activity

on the DMA request (DREQ) input. This is useful for

wiring-OR several devices that share a common DMA

request line. When the TSDR bit is reset the DREQ

output is driven to TTL levels.

When this bit is reset to zero, parity is generated during

DMA Writes to the FIFO, however no additional check-

ing will be done as FIFO data is unloaded, unless the

PGRP bit is set.

32

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Control Register Three (0CH) Read/Write

Control Register Three

CNTLREG3

Address: 0CH

Type: Read/Write

7

6

5

4

3

2

1

0

ADID

CHK

FAST

SCSI

FAST

CLK

QTAG

G2CB

LBTM

MDM

BS8

0

Burst Size 8

Modify DMA Mode

Last Byte Transfer Mode

FASTCLK

FASTSCSI

Group 2 Command Block

QTAG Control

Additional ID Check

17348B-32

CNTLREG3 – Bit 7 – ADIDCHK – Additional ID

Check

CNTLREG3 – Bit 4 – FASTSCSI – Fast SCSI

CNTLREG3 – Bit 3 – FASTCLK – Fast SCSI

Clocking

Enables additional check on ID message during bus-

initiated Select or Reselect with ATN. The ESC will

check bits 7, and bits 5:3 in the first byte of the ID mes-

sage during Selection of Reselection. An interrupt will

be generated if bit 7 is ‘0’, or if bits 5, 4, or 3 are ‘1’.

ThesebitsconfiguretheESC’sstatemachinetosupport

both Fast SCSI timings and SCSI-1 timings. These bits

will affect the SCSI transfer rate, and must be consid-

ered in conjunction with the ESC’s clock frequency and

mode of operation.

CNTLREG3 – Bit 6 – QTAG – QTAG Control

This bit controls the Queue Tag feature in the ESC.

When enabled, the ESC is capable of receiving 3-byte

messages during bus-initiated Select/Reselect with

ATN. (Bit 3, Control Register Two also enables this fea-

ture). The 3-byte message consists of one byte Identify

Message and two bytes of Queue Tag message. The

ESC will check the second byte for values of 20h, 21h,

and 22h. If this condition is not satisfied, the sequence

halts and the ESC generates an interrupt.

CNTLREG3 CNTLREG3 CNTLREG2

Bit 6

QTAG

Bit 5

G2CB

Bit 3

S2FE

Enabled

Features

––

1

––

0

1

0

10-byte CDB,

3-byte

message

3-byte

message

0

1

0

10-byte CDB

When the QTAG feature is not enabled, the ESC halts

the Selected with ATN sequence following the receipt of

one ID message byte if ATN is still true.

10-byte CDB,

3-byte

message

0

Features

disabled

CNTLREG3 – Bit 5 – G2CB – Group 2 Command

Block

–– = don’t care

When this bit is set, the ESC is capable of recognizing

10-byte Group 2 Commands as valid CDBs (Command

Descriptor Blocks). (This feature is also controlled by

bit 3 of CNTLREG2). When this feature is enabled, the

Target receives 10 bytes of Group 2 commands, and

sets the group code valid bit (bit 3) in Status Register

(STATREG). When this feature is disabled, the Target

receives only 6 bytes of command code, and does not

set bit 3 in register (04H).

This bit may be programmed in conjunction with bit 6

(described above) to send 1 or 3 byte messages with 6

or 10 byte CDBs. The following table illustrates the

transmission options:

33

Am53CF94/Am53CF96

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P R E L I M I N A R Y

The BS8 bit is used in conjunction with the Modify DMA

CNTLREG3 CNTLREG3

FASTSCSI

Bit 4

Mode (MDM) bit in the CNTLREG3. Both bits have to be

set for proper operation.

FASTCLK

Bit 3

Clock

Mode of

Frequency Operation

1

25–40 MHz 10 MBytes/

When the BS8 bit is set the device delays the assertion

of the DREQ signal until 8 bytes or 4 words transfer is

possible.

sec,

Fast SCSI

0

––

1

0

25–40 MHz 5 MBytes/sec,

SCSI-1

When the BS8 bit is set and the device is in a DMA write

modetheDREQsignalwillbeassertedonlywhen8byte

locations are available for writing. In the DMA read

mode the DREQ signal will go active under the following

circumstances:

< = 25 MHz 5 MBytes/sec,

SCSI-1

–– = don’t care

CNTLREG3 – Bit 2 – LBTM – Last Byte Transfer

Mode

At the end of a transfer,

■ In the Target mode,

– when the transfer is complete

or

The LBTM bit specifies how the last byte in an odd byte

transfer is handled during 16-bit DMA transfers (modes

1, 2, 3). This mode is not used if byte control is selected

via BUSMD 1:0 = 10 and SBO (Select Byte Order) bit in

the CNTLREG2is set to ‘1’. This mode has no affect dur-

ing 8-bit DMA transfers (mode 0) and on transfers on the

SCSI bus.

– when the ATN signal is active

■ In the Initiator mode,

– when the Current Transfer Register (CTCREG)

is decremented to zero

or

– after any phase change

When the LBTM bit is set the DREQ signal will not be

asserted for the last byte, instead the host will read or

write the last byte from or to the FIFO. When the LBTM

bit is reset the DREQ signal will be asserted for the last

byte and the following 16-bit DMA transfer will contain

the last byte on the lower bus. While the upper bus

(DMA 15:8/DMAP 1) will be all ones.

In the middle of a transfer

■ In the Initiator mode,

– when the last 8 bytes of the FIFO are full

– during Synchronous Data-In transfer when the

Event Transfer Count Register is greater than

7 and the last 8 bytes of the FIFO are full.

The LBTM bit is reset by hard or soft reset.

CNTLREG3 – Bit 1 – MDM – Modify DMA Mode

When the BS8 bit is reset and the device is in a DMA

read or write mode the DREQ signal will toggle every

time the data is strobed by the DMARD or DMAWR

signals.

The MDM bit is used to modify the timing of the DACK

signal with respect to the DMARD and DMAWR signals.

The MDM bit is used in conjunction with the Burst Size 8

(BS8) bit in the CNTLREG3. Both bits have to be set for

proper operation.

Using (Bit 0 (BS8) and Bit 1 (MDM) of Control

Register Three (CNTLREG3), one can enable the differ-

ent combination modes shown in the table below.

When the MDM bit is set and the device is in a DMA read

or write mode the DACK signal will remain asserted

while the data is strobed by the DMARD or DMAWR sig-

nals. In the DMA read mode when BUSMD 1:0 = 11 the

DACK signal will toggle for every DMA read.

Maximum

Synchronous

Offset

(MDM) (BS8)

Function

Bit 1

Bit 0

0

1

0

1

0

1

Normal DMA Mode

Burst Size 8 Mode

Reserved

15

7

When the MDM bit is reset and the device is in a DMA

read or write mode the DACK signal will toggle every

time the data is strobed by the DMARD or DMAWR

signals.

–

Modified DMA Mode

7

CNTLREG3 – Bit 0 – BS8 – Burst Size 8

The BS8 bit is used to modify the timing of the DREQ

signal with respect to the DMARD and DMAWR signals.

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AMD

Control Register Four (0DH)

Control Register Four

CNTLREG4

Address: 00H

7

6

5

4

3

2

1

0

RES (R)

RAE(W)

RES

GE1

GE0

PWD

RADE

RES

NU

0

X

0

X

Transfer Count Test Enable

Active Negation Ctl.

RES (R)/Active Negation Ctl (W)

Reserved

Power-Down

GLITCH EATER

17348B-33

This register is used to control several AMD proprietary

features implemented in the Am53CF94/96. At power

up, this register will show a ‘0’ value on all bits except

bit 4.

CNTLREG4 – Bit 3 (Write Only) – RAE – Active

Negation Control

CNTLREG4 – Bit 2 – RADE – Active Negation

Control

CNTLREG4 – Bit 7:6 – GE1:0 – GLITCH EATER

Bits 2 and 3 control the Active Negation Drivers which

may be enabled on REQ, ACK, or DATA lines. The fol-

lowing table shows the programming options for this

feature:

The GLITCH EATER circuitry has been implementedon

all SCSI input lines and are controlled by bits 7and 6.

The valid signal window may be adjusted by setting the

bits in the combinations listed below.

CNTLREG4

Bit 3

CNTLREG4

Bit 2

CNTLREG4 CNTLREG4

Function Selected

Bit 7

GE1

Bit 6

GE0

Single-

ended

RAE

RADE

Differential

0 ns

0

1

Active Negation

Disabled

0

1

0

1

0

1

12 ns

25 ns

35 ns

0 ns

25 ns

1

––

Active Negation on

REQ and ACK only

35 ns

Active Negation on

REQ, ACK and DATA

12 ns

–– = don’t care

CNTLREG4 – Bit 5 – PWD – Power-Down Feature

CNTLREG4 – Bit 1 – RES

Setting this bit to ‘1’ will enable AMD’s exclusive power-

down feature. This will turn off the input buffers on all the

SCSIbussignallinestoreducepowerconsumptiondur-

ing the chip’s sleep mode.

This bit is reserved for internal use.

CNTLREG4 – Bit 0 – NU – Not Used

The NCR53CF94/96 uses this bit to control back-to-

back transfers. This bit may be read or written but is not

used by the Am53CF94/96. Back-to-Back transfers are

always enabled.

CNTLREG4 – Bit 4 – RES

This bit is reserved for internal use.

CNTLREG4 – Bit 3 (Read Only) – RES

This bit is reserved for internal use.

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Am53CF94/Am53CF96

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P R E L I M I N A R Y

Data Alignment Register (0FH) Write

Part-Unique ID Register (0EH) Read Only

This register extends the transfer counter from 16 to 24

bits and is only enabled when the ENF bit is set (bit 6,

Control Register Two). The descriptions accompanying

the Start Transfer Count Registers and the Current

Count Registers should be referenced for more informa-

tion regarding the transfer counter.

Data Alignment Register

DALREG

Address: OF H

Type: Write

7

6

5

4

3

2

1 0

DA7

0

DA6

0

DA5 DA4 DA3 DA2

DA1 DA0

This register is also used to store the part-unique ID

code for the Am53CF94/96. This information may be ac-

cessed when all of the following are true:

0

17348B-34

1) A value has not been loaded into this register

2) A DMA NOP command has been issued (code 80h)

3) Bit 6 in Control Register Two is set (ENF bit)

4) A power up or chip reset has taken place

The Data Alignment Register (DALREG) is used if the

first byte of a 16-bit DMA transfer from the SCSI bus to

the host processor is misaligned. Prior to issuing an in-

formation transfer command, the host processor must

set the Data Alignment Enable (DAE) bit in Control Reg-

ister Two (CNTLREG2).

When the above conditions are satisfied, the following

bit descriptions apply:

This register may be loaded immediately following the

phase change to Synchronous Data In. This byte will

become the LSB of the first word transmitted from the

FIFO to the DMA controller. The MSB will be comprised

of the first byte received over the SCSI bus. Together,

these bytes constitute the first 16-bit word transferred to

memory.

ID

Am53CF94, 3 V

Am53CF94, 5 V

12

DALREG – Bits 7:0 – DA 7:0 – Data Alignment 7:0

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P R E L I M I N A R Y

AMD

COMMANDS

The device commands can be broadly divided into two

categories, DMA commands and non-DMA commands.

DMAcommandsarethosewhichcausedatamovement

between the host memory and the SCSI bus while non-

DMA commands are those that cause data movement

betweenthedeviceFIFOandtheSCSIbus. TheMSBof

the command byte differentiate the DMA from the non-

DMA commands.

Summary of Commands

Command Code

(Hex.)

Command Code

(Hex.)

Non-

DMA

Mode

Command

Non-

DMA

Mode

Command

DMA

Mode

DMA

Mode

Idle State Commands

Initiator Commands

Reselect Steps

40

41

42

43

44

45

46

47

C0

C1

C2

C3

C4

C5

C6

C7

Information Transfer

10

11

12

18

1A

1B

90

91

–

Select without ATN Steps

Select with ATN Steps

Initiator Command Complete Steps

Message Accepted

Transfer Pad Bytes

Set ATN

Select with ATN and Stop Steps

Enable Selection/Reselection

Disable Selection/Reselection

Select With ATN3 Steps

98

–

Reset ATN

–

Target Commands

Send Message

Reselect with ATN3 Steps

20

21

22

23

24

25

27

28

29

2A

2B

04

05

A0

A1

A2

A3

A4

A5

A7

A8

A9

AA

AB

84

Send Status

General Commands

No Operation

00

01

02

03

80

81

82

83

Send Data

Clear FIFO

Disconnect Steps

Terminate Steps

Reset Device

Reset SCSI bus

Target Command Complete Steps

Disconnect

Receive Message

Receive Command Steps

Receive Data

Receive Command Steps

DMA Stop Command

Access FIFO Command

85

37

Am53CF94/Am53CF96

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P R E L I M I N A R Y

COMMAND DESCRIPTION

Initiator Commands

Initiator commands are executed by the device when

it is in the Initiator mode. If the device is not in the Initia-

tor mode and an Initiator command is received the

device will ignore the command, generate an Invalid

Command interrupt and clear the Command Register

(CMDREG).

During synchronous data Transfers the Target may

send up to the maximum synchronous threshold num-

ber of REQpulses to the Initiator. If it is the Synchronous

Data-In phase then the Target sends the data and the

REQ pulses. These bytes are stored by the Initiator in

the FIFO as they are received.

InformationTransferCommand, whenissuedduringthe

following SCSI phases and terminated in synchronous

data phases, is handled as described below:

Should the Target disconnect from the SCSI bus by

deasserting the BSY signal line while the ESC (Initiator)

is waiting for the Target to assert REQ, a Disconnected

Interrupt will be issued 1.5 to 3.5 clock cycles following

BSY going false.

■ Message In/Status Phase – When a phase change

to Synchronous Data-In or Synchronous Data-Out is

detected by the device, the Command Register

(CMDREG) is cleared and the DMA interface is

disabledtodisallowanytransferofdataphasebytes.

If the phase change is to Synchronous Data-In and

bad parity is detected on the data bytes coming in, it

is not reported since the Status Register

(STATREG) will report the status of the command

just completed. The parity error flag and the ATN

signalwillbeassertedwhentheTransferInformation

command begins execution.

Upon receipt of the last byte during Msg In phase, ACK

will remain asserted to prevent the Target from issuing

any additional bytes, while the Initiator decides to ac-

cept/reject the message. If non-DMA commands are

used, the last byte signals the FIFO is empty. If DMA

commands are used, the transfer counter signals the

last byte.

If parity checking is enabled in the Initiator mode and an

error is detected, ATN will be asserted for the erroneous

byte before deasserting ACK. An exception to this is fol-

lowing a phase change to Synchronous Data In.

■ Message Out/Command Phase – When a phase

change to Synchronous Data-In or Synchronous

Data-Out is detected by the device, the Command

Register (CMDREG) is cleared and the DMA

interface is disabled to disallow any transfer of data

phase bytes. If the phase change is to Synchronous

Data-In and bad parity is detected on the data bytes

coming in, it is not reported since the Status Register

(STATREG) will report the status of the command

just completed. The parity error flag and the ATN

signalwillbeassertedwhentheTransferInformation

command begins execution. The FIFO Register

(FFREG) will be latched and will remain in that

condition until the next command begins execution.

The value in the FFREG indicates the number of

bytes in the FIFO when the phase changed to

Synchronous Data-In. These bytes are cleared from

the FIFO, which now contains only the incoming data

bytes.

To program Synchronous Transfer, the Synchronous

Offset Register (SOFREG) must be set to a non-zero

value. While in this mode, if the phase changes to Data

In, the DMA interface is disabled, and parity generation

is delayed. The Data In phase will latch the FIFO flags to

indicate the number of bytes in the FIFO, clear the FIFO,

load the FIFO with the first byte of Data In, generate an

interrupt, and continue to load the FIFO with incoming

bytes up to the synchronous offset.

Information Transfer Command

(Command Code 10H/90H)

The Information Transfer command is used to transfer

information bytes over the SCSI bus. This command

may be issued during any SCSI Information Transfer

phase. Synchronous data transmission requires use of

the DMA mode.

■ In the Synchronous Data-Out phase, the threshold

counter is incremented as REQ pulses are received.

The transfer is completed when the FIFO is empty

and the Current Transfer Count Register (CTCREG)

is zero. The threshold counter will not be zero.

The device will continue to transfer information until it is

terminated by any one of the following conditions:

■ The Target changes the SCSI bus phase before the

expected number of bytes are transferred. The

device clears the Command Register (CMDREG),

and generates a service interrupt when the Target

asserts REQ.

■ In the Synchronous Data-In phase, the Current

Transfer Count Register (CTCREG) is decre-

mented as bytes are read from the FIFO rather than

being decremented when the bytes are being written

to the FIFO. The transfer is completed when Current

Transfer Count Register (CTCREG) is zero but the

FIFO may not be empty.

■ Transfer is successfully complete. If the phase is

Message Out, the device deasserts ATN before

asserting ACK for the last byte of the message.

When the Target asserts REQ, a service interrupt is

generated.

■ In the Message In phase when the device receives

the last byte. The device keeps the ACK signal

asserted and generates a Successful Operation

interrupt.

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Am53CF94/Am53CF96

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AMD

Initiator Command Complete Steps

(Command Code 11H/91H)

the end of this command. The ATN signal is deasserted

before asserting the ACK signal during the last byte of

the Message Out phase.

The Initiator Command Complete Steps command is

normally issued when the SCSI bus is in the Status In

phase. One Status byte followed by one Message byte

is transferred if this command completes normally. After

receiving the message byte the device will keep the

ACK signal asserted to allow the Initiator to examine the

message and assert the ATN signal if it is unacceptable.

The command terminates early if the Target does not

switch to the Message In phase or if the Target discon-

nects from the SCSI bus.

Note:

The ATN signal is asserted by the device without this

command in the following cases:

■ If any select with ATN command is issued and the

arbitration is won.

■ An Initiator needs the Target’s attention to send a

message. The ATN signal is asserted before

deasserting the ACK signal.

Reset ATN Command (Command Code 1BH)

Message Accepted Command

(Command Code 12H)

The Reset ATN Command is used to deassert the ATN

signal on the SCSI bus. An interrupt is not generated at

the end of this command. This command is used only

when interfacing with devices that do not support the

Common Command Set (CCS). These older devices do

not deassert their ATN signal automatically on the last

byte of the Message Out phase. This device does deas-

sert its ATN signal automatically on the last byte of the

Message Out phase.

The Message Accepted Command is used to release

the ACK signal. This command is normally used to com-

plete a Message In handshake. Upon execution of this

command the device generates a service request inter-

rupt after REQ is asserted by the Target.

After the device has received the last byte of message, it

keeps the ACK signal asserted. This allows the device

to either accept or reject the message. To accept the

message, Message Accepted Command is issued. To

reject the message the ATN signal must be asserted

(with the help of the Set ATN Command) before issuing

the Message Accepted Command. In either case the

Message Accepted Command has to be issued to re-

lease the ACK signal.

Target Commands

Target commands are executed by the device when it is

in the Target mode. If the device is not in the Target

mode and a Target command is received the device will

ignore the command, generate an Invalid Command in-

terrupt and clear the Command Register (CMDREG).

Transfer Pad Bytes Command

(Command Code 18H/98H)

ASCSIbusresetduringanyTargetcommandwillcause

the device to abort the command sequence , flag a SCSI

bus reset interrupt (if the interrupt is enabled) and dis-

connect from the SCSI bus.

The Transfer Pad Bytes Command is used to recover

from an error condition. This command is similar to the

Information Transfer Command, only the information

bytes consists of null data. It is used when the Target ex-

pects more data bytes than the Initiator has to send. It is

also used when the Initiator receives more information

than expected from the Target.

Normal or successful completion of a Target command

will cause a Successful Operation interrupt to be

flagged. If the ATN signal is asserted during a Target

command sequence the Service Request bit is asserted

in the Interrupt Status Register (INSTREG). If the ATN

signal is asserted when the device is in an Idle state a

Service Request interrupt will be generated, the Suc-

cessful Operation bit in the Interrupt Status Register

(INSTREG) will be reset and the Command Register

(CMDREG) cleared.

When sending data to the SCSI bus, the FIFO is loaded

with null bytes which are sent out to the SCSI bus. Al-

though an actual DMA request is not made, DMA must

be enabled when pad bytes are transmitted since the

ESC uses Current Transfer Count Register (CTCREG)

to terminate transmission.

Send Message Command

(Command Code 20H/A0H)

When receiving data from the SCSI bus, the device will

receive the pad bytes and place them on the top of the

FIFO and unload them from the bottom of the FIFO.

The Send Message Command is used by the Target to

inform the Initiator to receive a message. The SCSI bus

phase lines are set to the Message In Phase and mes-

sage bytes are transferred from the device FIFO to the

buffer memory.

Thiscommandterminatesunderthesameconditionsas

theInformationTransferCommand, butthedevicedoes

not keep the ACK signal asserted during the last byte of

the Message In phase. Should this command terminate

prematurely due to a disconnect or a phase change,

(before the Current Transfer Count Register (CTCREG)

decrements to zero), the FIFO may contain residual pad

bytes.

Send Status Command

(Command Code 21H/A1H)

The Send Status Command is used by the Target to in-

form the Initiator to receive status information. TheSCSI

bus phase lines are set to the Status Phase and status

bytes are transferred from the Target device to the Initia-

tor device.

Set ATN Command (Command Code 1AH)

The Set ATN Command is used to drive the ATN signal

active on the SCSI bus. An interrupt is not generated at

39

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

Send Data Command (Command Code 22H/A2H)

and clock factor). Interrupt is not generated to the micro-

processor.

The Send Data Command is used by the Target to

inform the Initiator to receive data bytes. The SCSI bus

phase lines are set to the Data-In Phase and data bytes

are transferred from the Target device to the Initiator

device.

Receive Message Steps Command

(Command Code 28H/A8H)

The Receive Message Steps Command is used by the

Target to request message bytes from the Initiator. The

Target receives the message bytes from the Initiator

while the SCSI bus is in the Message Out Phase. The

Successful Operation bit is set in the Interrupt Status

Register (INSTREG) upon command completion. If

ATN signal is asserted by the Initiator then Successful

Operation and Service Request bits are set in the IN-

STREG, the Command Register (CMDREG) is cleared,

but if a parity error is detected, the device ignores the re-

ceived message bytes until ATN signal is deasserted,

the Successful Operation bit is set in the INSTREG, and

the CMDREG is cleared.

Disconnect Steps Command

(Command Code 23H/A3H)

The Disconnect Steps Command is used by the Target

to disconnect from the SCSI bus. This command is exe-

cuted in two steps. In the Message In phase, the Target

sends two bytes of the Save Data Pointers commands.

Followingtransmission, theTargetdisconnectsfromthe

SCSI bus. Successful Operation and Disconnected bits

are set in the Interrupt Status Register (INSTREG) upon

command completion. If ATN signal is asserted by the

Initiator then Successful Operation and Service Re-

questbitsaresetintheINSTREG, theCommandRegis-

ter (CMDREG) is cleared and Disconnect Steps Com-

mand terminates without disconnecting.

Receive Commands Command

(Command Code 29H/A9H)

The Receive Commands Command is used by the

Target to request command bytes from the Initiator. The

Target receives the command bytes from the Initiator

while the SCSI bus is in the Command Phase. The

Successful Operation bit is set in the Interrupt Status

Register (INSTREG) upon command completion. If

ATN signal is asserted by the Initiator then Successful

Operation and Service Request bits are set in the

INSTREG, the Command Register (CMDREG) is

cleared and the command terminates prematurely. If a

parity error is detected, the device continues to receive

command bytes until the transfer is complete. However,

if the Abort on Command Data/Parity Error (ACDPE) bit

in Control Register Two (CNTLREG2) bit is set, the

command is terminated immediately. The Parity Error

(PE) bit in the Status Register (STATREG) is set and

CMDREG is cleared.

Terminate Steps Command

(Command Code 24H/A4H)

The Terminate Steps Command is used by the Target to

disconnect from the SCSI bus. This command is exe-

cuted in three steps. While in Status phase, the Target

first sends a 1 byte status message. Following the

Status phase the Target moves to the Message In

phase and sends another 1 byte message. Lastly, the

Target disconnects from the SCSI bus. The Discon-

nected bit is set in the Interrupt Status Register

(INSTREG) upon command completion. If ATN signal is

asserted by the Initiator, then Successful Operation and

Service Request bits are set in the INSTREG, an inter-

rupt is generated and the Command Register

(CMDREG) is cleared and Terminate Steps Command

terminates without disconnecting.

Receive Data Command

(Command Code 2AH/AAH)

Target Command Complete Steps Command

(Command Code 25H/A5H)

The Receive Data Command is used by the Target to re-

quest data bytes from the Initiator. During this command

the Target receives the data bytes from the Initiator

while the SCSI bus is in the Data-Out Phase. The Suc-

cessful Operation bit is set in the Interrupt Status Regis-

ter (INSTREG) upon command completion. If ATN sig-

nal is asserted by the Initiator then Successful Opera-

tion and Service Request bits are set in the INSTREG,

the Command Register (CMDREG) is cleared and the

command terminates prematurely. If a parity error is de-

tected, the device continues to receive data bytes until

the transfer is complete (Abort on Command/Data Par-

ity Error (ACDPE) bit in Control Register Two

(CNTLREG2) is reset). If the ACDPE bit is set, the com-

mand is terminated immediately. The Parity Error (PE)

bit in the Status Register (STATREG) is set and

CMDREG is cleared.

The Target Command Complete Steps Command is

used by the Target to inform the Initiator of a linked com-

mand completion. This command consists of two steps.

In the first step, the Target sends one status byte to the

Initiator in the Status Phase. The Target then sends one

message byte to the Initiator in the Message In Phase.

The Successful Operation bit is set in the Interrupt

Status Register (INSTREG) upon command comple-

tion. If ATN signal is asserted by the Initiator then

Successful Operation and Service Request bits are set

in the INSTREG, the Command Register (CMDREG) is

cleared and Target Command Complete Steps Com-

mand terminates prematurely.

Disconnect Command

(Command Code 27H/A7H)

The Disconnect Command is used by the Target to dis-

connect from the SCSI bus. All SCSI bus signals except

RSTC are released and the device returns to the Dis-

connected state. The RSTC signal is driven active for

about 25 micro seconds (depending on clock frequency

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Am53CF94/Am53CF96

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AMD

Receive Command Steps Command

(Command Code 2BH/ABH)

Upon receipt of the DMA Stop Command, the ESC re-

sets the DMA interface and DREQ pin, then terminates

the command in progress. Ongoing SCSI sequences

are completed as follows:

The Receive Command Steps Command is used by the

Target to request command information bytes from

the Initiator. During this command the Target receives

the command information bytes from the Initiator

while the SCSI bus is in the Command Phase.

■ Synch Data Send: completes when CTZ bit in Status

Register is ‘1’.

■ Synch Data Receive: when all outstanding ACKs

received, command completes

The Target device determines the command block

length from the first byte. If an unknown length is re-

ceived, the Start Transfer Count Register (STCREG) is

loaded with five and the Group Code Valid (GCV) bit in

the Status Register (STATREG) is reset. If a valid length

is received, the STCREG is loaded with the appropriate

valueandtheGCVbitintheSTATREGisset. IfATNsig-

nal is asserted by the Initiator then the Service Request

bit is set in the Interrupt Status Register (INSTREG),

and the Command Register (CMDREG) is cleared. If a

parity error is detected, the command is terminated pre-

maturely and the CMDREG is cleared.

■ Asynchronous Data Send: immediately completes

■ Asynchronous Data Receive: immediately com-

pletes. Remaining data in FIFO should be removed

by microprocessor.

Access FIFO Command (Command Code 05H/85H)

The host may issue the Access FIFO command follow-

ing a Target Abort DMA or abort due to parity error. This

command will give the DMA controller access to the

data remaining in the FIFO. The following shall be true

depending on the status of the DAE bit in CNTRLREG2:

DMA Stop Command (Command Code 04H/84H)

DAE=1:

DREQ will be asserted if the FIFO has two or more bytes

of data, and will deassert if the FIFO contains one or

zero bytes of data.

The DMA Stop Command is used by the Target to allow

the microprocessor to discontinue data transfers due to

a lack of activity on the DMA channel. This command is

executed from the top of the command queue. If there is

a queued command waiting execution, it will be over-

written and the Illegal Operation Error (IOE) bit in the

Status Register (STATREG) will be set. This command

is cleared from the command queue once it is decoded.

DAE=0:

DREQ will be asserted if the FIFO is not empty, and will

deassert when the FIFO is empty.

While DREQ is asserted, the DMA controller may read

the data. This command is supported only in normal

DMA mode.

Caution must be exercised when using this command.

The following conditions must be true:

■ The DMA Stop Command can be used only during

DMA Target Send Data Command or DMA Target

Receive Data Command execution. In both cases

the DMA controller and the ESC must be in the idle

state.

Idle State Commands

The Idle State Commands can be issued to the device

only when the device is disconnected from the SCSI

bus. If these commands are issued to the device when it

is logically connected to the SCSI bus, the commands

are ignored, and the device will generate an Invalid

Command interrupt and clear the Command Register

(CMDREG).

■ During a DMA Target Send Data Command: the

FIFO is empty or the Current FIFO (CF 4:0) bits inthe

Current FIFO/Internal State Register (CFISREG)

are zero.

Reselect Steps Command

(Command Code 40H/C0H)

■ During a DMA Synchronous Target Receive Data

Command: the Current Transfer Count Register

(CTCREG) is zero, (indicated by the Count to Zero

(CTZ) bit of the Status Register (STATREG)), or the

Synchronous Offset Register (SOFREG) has

reached its maximum value (indicated by the

Synchronous Offset Flag (SOF) bit of the Internal

State Register (ISREG)).

The Reselect Steps Command is used by the Target de-

vice to reselect an Initiator device. When this command

is issued the device arbitrates for the control of the SCSI

bus. If the device wins arbitration, it Reselects the Initia-

tor device and transfers a single byte identify message.

Before issuing this command the SCSI Timeout Regis-

ter (STIMREG), the Control Register One (CNTLREG1)

and the SCSI Destination ID Register (SDIDREG) must

be set to the proper values. If DMA is enabled, the Start

Transfer Count Register (STCREG) must be set to one.

If DMA is not enabled, the single byte identify message

must be loaded into the FIFO before issuing this com-

mand. This command will be terminated early if the

SCSI Timeout Register times out, or if sequence termi-

nates normally, a Successful Operation interrupt will be

issued. This command also resets the Internal State

Register (ISREG).

■ During a DMA Asynchronous Target Receive Data

Command: the FIFO is full (CF 4:0 set to ‘1’ in the

Current FIFO/Internal State Register (CFISREG)),

or Current Transfer Count Register (CTCREG) is

zero (indicated by the Count to Zero (CTZ) bit of the

Status Register (STATREG)).

When conditions are satisfied, the ESC halts, asserts

DREQ, and then waits for the DMA channel. If the ESC

halted during Synchronous Transfer, the ACK pulses

not received from the SCSI bus remain outstanding.

41

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

fer counter with the number of bytes which will follow,

Select without ATN Steps Command

then issue an information transfer command. (Note: the

Target is still in the message out phase when this com-

mand is issued). ATN will remain asserted until the

transfer counter decrements to zero.

(Command Code 41H/C1H)

The Select without ATN Steps Command is used by the

Initiator to select a Target. When this command is

issued the device arbitrates for the control of the SCSI

bus. When the device wins arbitration, it selects the

Target device and transfers the Command Descriptor

Block (CDB). Before issuing this command the SCSI

Timeout Register (STIMREG), the Control Register

One (CNTLREG1) and the SCSI Destination ID Regis-

ter (SDIDREG) must be set to the proper values. If DMA

is enabled, the Start Transfer Count Register

(STCREG) must be set to the total length of the

command. If DMA is not enabled, the data must be

loaded into the FIFO before issuing this command. This

command will be terminated early if the SCSI Timeout

Register times out or if the Target does not go to the

Command Phase following the Selection Phase or if the

Target exits the Command Phase prematurely. A

Successful Operation interrupt will be generated follow-

ing normal command execution.

The SCSI Timeout Register (STIMREG), ControlRegis-

ter One (CNTLREG1), and the SCSI Destination ID

Register (SDIDREG) must be set to the proper values

before beginning the Initiator issues this command. This

command will be terminated early if the STIMREG times

out or if the Target does not go to the Message Out

Phase following the Selection Phase.

Enable Selection/Reselection Command

(Command Code 44H/C4H)

TheEnableSelection/ReselectionCommandisusedby

the Target to respond to a bus-initiated Selection or

Reselection. Upon disconnecting from the bus the Se-

lection/Reselection circuit is automatically disabled by

device. This circuit has to be enabled for the device to

respondtosubsequentreselectionattemptsandtheEn-

able Selection/Reselection Command is issued to do

that. This command is normally issued within 250 ms

(select/reselect timeout) after the device disconnects

from the bus. If DMA is enabled the device loads the re-

ceived data to the buffer memory, but if the DMA is dis-

abled, the received data stays in the FIFO.

Select with ATN Steps Command

(Command Code 42H/C2H)

The Select with ATN Steps Command is used by the In-

itiator to select a Target. When this command is issued

the device arbitrates for the control of the SCSI bus.

When the device wins arbitration, it selects the Target

device with the ATN signal asserted and transfers the

Command Descriptor Block (CDB) and a one byte mes-

sage. Before issuing this command the SCSI Timeout

Register (STIMREG), the Control Register One

(CNTLREG1) and the SCSI Destination ID Register

(SDIDREG) must be set to the proper values. If DMA is

enabled, the Start Transfer Count Register (STCREG)

must be set to the total length of the command and mes-

sage. If DMA is not enabled, the data must be loaded

into the FIFO before issuing this command. This com-

mand will be terminated early in the following situations:

Disable Selection/Reselection Command

(Command Code 45H/C5H)

The Disable Selection/Reselection Command is used

by the Target to disable response to a bus-initiated

Reselection. Whenthiscommandisissuedbeforeabus

initiated Selection or Reselection is initiated, it resets

the internal mode bits previously set by the Enable Se-

lection/Reselection Command. The device also gener-

ates a function complete interrupt to the processor. If

however, this command is issued after a bus initiated

Selection/Reselection has already begun the command

is ignored since the Command Register (CMDREG) is

held reset and all incoming commands are ignored. The

device generates a selected or reselected interrupt

when the sequence is complete.

■ The SCSI Timeout Register times out

■ The Target does not go to the Message Out Phase

following the Selection Phase

■ The Target exits the Message Phase early

Select with ATN3 Steps Command

(Command Code 46H/C6H)

■ The Target does not go to the Command Phase

following the Message Out Phase

The Select with ATN3 Steps Command is used by the

Initiator to select a Target. This command is similar to

the Select with ATN Steps Command, except that it

sends exactly three message bytes. When this com-

mand is issued the ESC arbitrates for the control of the

SCSI bus. When the device wins arbitration, it selects

the Target device with the ATN signal asserted and

transfers the Command Descriptor Block (CDB) and

three message bytes. Before issuing this command the

SCSI Timeout Register (STIMREG), the Control Regis-

ter One (CNTLREG1) and the SCSI Destination ID Reg-

ister (SDIDREG) must be set to the proper values. If

DMA is enabled, the Start Transfer Count Register

(STCREG) must be set to the total length of the com-

mand. If DMA is not enabled, the data must be loaded

■ The Target exits the Command Phase early

A Successful Operation/Service Request interrupt

isgeneratedwhenthiscommandiscompletedsuccess-

fully.

Select with ATN and Stop Steps Command

(Command Code 43H/C3H)

The Select with ATN and Stop Steps Command is used

bytheInitiatortosendmessageswithlengthsotherthan

1 or 3 bytes. When this command is issued, the device

executes the Selection process, transfers the first mes-

sage byte, then STOPS the sequence. ATN is not deas-

serted at this time, allowing the Initiator to send addi-

tional message bytes after the ID message. To send

these additional bytes, the Initiator must write the trans-

42

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

into the FIFO before issuing this command. This com-

mand will be terminated early in the following

situations:

A No Operation Command in the DMA mode may be

used to verify the contents of the Start Transfer Count

Register (STCREG). After the STCREG is loaded with

the transfer count and a DMA No Operation Command

is issued, reading the Current Transfer Count Register

(CTCREG) will give the transfer count value.

■ The SCSI Timeout Register times out

■ The Target does not go to the Message Out Phase

following the Selection Phase

Clear FIFO Command

(Command Code 01H/81H)

■ The Target removes Command Phase early

■ The Target does not go to the Command Phase

The Clear FIFO Command is used to initialize the FIFO

to the empty condition. The Current FIFO Register

(CFISREG) reflects the empty FIFO status and the bot-

tom of the FIFO is set to zero. No interrupt is generated

at the end of this command.

following the Message Out Phase

■ The Target exits the Command Out Phase early

A Successful Operation/Service Request interrupt is

generated when this command is executed success-

fully.

Reset Device Command

(Command Code 02H/82H)

Reselect with ATN3 Steps Command

(Command Code 47H/C7H)

The Reset Device Command immediately stops any de-

vice operation and resets all the functions of the device.

It returns the device to the disconnected state and it also

generatesahardreset. TheResetDeviceCommandre-

mains on the top of the Command Register FIFO hold-

ing the device in the reset state until the No Operation

Command is loaded. The No Operation command

serves to enable the Command Register.

The Queue Tag feature of the Select with ATN3 com-

mand has been implemented in the Reselection com-

mand. Therefore, a Target reselecting an Initiator can

use the QTAG feature of ATN3. Following Reselection,

one message byte and 2 bytes QTAG will be sent. The

three message bytes must be loaded into the FIFO be-

fore this command is issued if DMA is not enabled.

Reset SCSI Bus Command

(Command Code 03H/83H)

General Commands

No Operation Command

(Command Code 00H/80H)

The Reset SCSI Bus Command forces the RSTC signal

active for a period of 25 µs, and drives the chip to the

Disconnected state. An interrupt is not generated upon

command completion, however, if bit 6 is not disabled in

Control Register One (CNTLREG1), a SCSI reset inter-

rupt will be issued.

The No Operation Command administers no operation,

therefore an interrupt is not generated upon completion.

This command is issued following the Reset Device

Command to clear the Command Register (CMDREG).

43

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature . . . . . . . . . . . –65°C to +150°C

Commercial Devices

Ambient Temperature

Ambient Temperature (T_A) . . . . . . . 0°C to +70°C

Under Bias . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Supply Voltage (V_DD) . . . . . . . . . . . 4.5 V to 5.5 V

V_DD. . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +7.0 V

DC Voltage Applied

to Any Pin . . . . . . . . . . . . . . . . . –0.5 to (V_DD+ 0.5) V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

Input Static Discharge Protection . . . . 4K V pin-to-pin

(Human body model: 100 pF at 1.5K Ω)

Stresses above those listed under Absolute Maximum Rat-

ings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to absolute maxi-

mum ratings for extended periods may affect device reliability.

44

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

DC OPERATING CHARACTERISTICS

Parameter

Symbol

Parameter Description

Pin Names

Test Conditions

Min

Max

Unit

I_DDS

I_DDD

Static Supply Current

Dynamic Supply Current

Latch Up Current

Capacitance

V_{DD MAX}

_LU≤ 10 V

4.0

30

mA

pF

I_LU

All I/O

V

– 100

+100

10

C

All Pins

SCSI Pins

V_IH

Input High Voltage

All SCSI Inputs

SD 7–0, SD P

2.0

V_SS– 0.5

300

V_DD+ 0.5

0.8

V

V_IL

Input Low Voltage

V_IHST

V_OH

Input Hysterisis

4.5 V < V_DD< 5.5 V

I_OH= – 2 mA

I_OL= 4 mA

mV

V

Output High Voltage

SCSI Output Low Voltage

2.4

V_DD

0.4

0.5

V_SOL1

V_SOL2

V_SS

V

SDC 7–0, SDC P, I_OL= 48 mA

MSG, C/D, I/O,

V_SS

V

ATN, RSTC,

SELC, BSYC,

ACKC and REQC

I_IL

Input Low Leakage

0.0 V < V_IN< 2.7 V

–10

+10

µA

I_IH

I_OZ

Input High Leakage

High Impedance Leakage

2.7 V < V_IN< V_DD

0 V < V_OUT< V_DD

Bidirectional Pins

V_IH

V_IL

Input High Voltage

2.0

V_SS– 0.5

2.4

V_DD+ 0.5

0.8

V

Input Low Voltage

V_OH

Output High Voltage

DMA 15–0 and

DMAP 1–0

AD 7–0

I_OH= – 2 mA

V_DD

I_OH= – 1 mA

V_OL

Output Low Voltage

Input Low Leakage

Input High Leakage

DMA 15–0 and

DMAP 1–0

AD 7–0

I_OL= 4 mA

V_SS

– 10

–10

0.4

+10

V

I_OL= 2 mA

I_IL

DMA 15–0,

DMAP 1–0 and

AD 7–0

0 V < V_IN< V_IL

µA

I_IH

DMA 15–0,

DMAP 1–0 and

AD 7–0

V_IH< V_IN< V_DD

I_OZ

High Impedance Leakage

Output High Voltage

0 V < V_OUT< V_DD

I_OH= – 2 mA

–10

2.4

+10

V_DD

µA

Output Pins

V_OH

DREQ, ISEL,

TSEL, REQC*,

ACKC*

V

V_OL

Output Low Voltage

DREQ, ISEL,

TSEL, REQC*,

ACKC*

I_OL= 4 mA

V_SS

–10

0.4

V

I_OZ

High Impedance Leakage

0 V < V_OUT< V_DD

+10

µA

*REQC and ACKC in Differential Mode only.

45

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

DC OPERATING CHARACTERISTICS (continued)

Parameter

Symbol

Parameter Description

Pin Names

Test Conditions

Min

Max

Unit

Input Pins

V_IH

V_IL

I_IL

Input High Voltage

A 3-0, CS, RD, WR,

DMAWR, CLK,

BUSMD 1–0, DACK,

RESET, and

2.0

V_DD+ 0.5

V

DFMODE

Input Low Voltage

Input High Voltage

A 3-0, CS, RD, WR,

DMAWR, CLK,

BUSMD 1–0, DACK,

RESET, and

V_SS+0.5

0.8

+10

V

µA

DFMODE

A 3-0, CS, RD, WR,

DMAWR, CLK,

BUSMD 1–0, DACK,

RESET, and

–10

0 < V_IN< V_IL

DFMODE

I_IH

A 3-0, CS, RD, WR,

DMAWR, CLK,

BUSMD 1–0, DACK,

RESET, and

–10

V_IH< V_IN< V_DD

DFMODE

SWITCHING TEST CIRCUIT

I_OL

From Output

Under Test

V_T

C_L

0 V

I_OH

17348B-35

SWITCHING TEST WAVEFORMS

3.0 V

0.0 V

1.5 V

All Inputs

V_OH

2.0 V

V_OL

2.3 V

True Data Outputs AD 7–0, DMA 15–0, DMAP1–0

Hi-Z Outputs AD 7–0, DMA 15–0, DMAP1–0

All Open Drain Outputs and INT

0.8 V

V_OH–0.3 V

2.0 V

V_OL+0.3 V

2.0 V

0.8 V

V_OL

V_OH

2.3 V

0.8 V

SD 7–0, SD P, DREQ, ISEL, TSEL

V_OL

17348B-36

46

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Must be

Steady

Will be

Steady

May

Change

from H to L

Will be

Changing

from H to L

May

Change

from L to H

Will be

Changing

from L to H

Don’t Care,

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center

Line is High-

Impedance

“Off” State

KS000010

47

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

CLK

4

1

2

3

3A

17348B-37

Clock Input

FastClk Disabled (Control Register Three (0CH) bit 3=0)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

1

2

3

4

t_PWL

Clock Pulse Width Low

14.58

40

0.65 • t_CPns

t_CP

t_L

Clock period (1 ÷ Clock Frequency)

Synchronization latency

100

ns

54.58

14.58

t_{PWL +}t_CP

1

t_PWH

Clock Pulse Width High

0.65 • t_CPns

Note:

¹For Synchronous data transmissions, the following conditions

must be true:

2tCP + tPWL > 97.92 ns

2tCP + tPWH > 97.92 ns

Clock Frequency Range for Fast Clk disabled.

= 10 MHz to 25 MHz for Asynchronous transmission

= 12 MHz to 25 MHz for Synchronous transmission

FastClk Enabled (Control Register Three (0CH) bit 3=1)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

1

2

t_PWL

t_CP

Clock Pulse Width Low

0.4 • t_CP0.6 • t_CP

ns

Clock period (1 ÷ Clock Frequency)

Synchronization latency

25

50

3A

4

t_L

54.58

2 • t_CP

t_PWH

Clock Pulse Width High

0.4 • t_CP0.6 • t_CP

Note:

Clock Frequency Range for Fast Clk enabled.

= 20 MHz to 40 MHz for Asynchronous Transmission

= 20 MHz to 40 MHz for Synchronous Transmission

48

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

RESET

5

17348B-38

Reset Input

Parameter

Symbol

No.

Parameter Description

Reset Pulse Width High

Test Conditions

Min

Max

Unit

5

t_PWH

500

ns

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

7

INT

RD

6

8

9

17348B-39

Interrupt Output

Parameter

Symbol

No.

Parameter Description

Test Conditions

Min

Max

Unit

6

7

8

9

t_S

t_PD

t_PWL

t_PD

INT to RD

RD to INT

Set Up Time

Delay

0

ns

100

RD Pulse Width Low

RD to INT Delay

50

t_L

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

49

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

A 3–0

10

11

20

19

CS

RD

16

12

14

22

21

15

17

18

13

AD 7–0

DMA 7–0

DMAP 0

17348B-40

Register Read with Non-Multiplexed Address Data Bus

A 3–0

10

11

19

26

CS

27

23

24

28

WR

31

30

25

29

AD 7–0

DMA 7–0

DMAP 0

17348B-41

Register Write with Non-Multiplexed Address Data Bus

50

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Register Read/Write with Non-Multiplexed Address Data Bus

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

t_S

t_H

Address to CS Set Up Time

Address to CS Hold Time

CS to RD Set Up Time

CS to Data Valid Delay

RD Pulse Width Low

0

30

0

ns

t_S

t_PD

t_PWL

t_PD

t_H

65

30

0

RD to Data Valid Delay

RD to CS Hold Time

RD to Data High Impedance

RD to Data Hold Time

CS Pulse Width High

t_Z

t_H

2

30

40

2

t_PWH

t_S

RD to CS Set Up Time

CS to Data Hold Time

CS to Data High Impedance

CS to WR Set Up Time

WR Pulse Width Low

t_H

t_Z

30

t_S

0

t_PWL

t_S

30

15

0

Data to WR Set Up Time

WR to CS Hold Time

WR to CS Set Up Time

WR Pulse Width High

t_H

t_S

30

40

0

t_PWH

t_H

Data to WR Hold Time

CS to Data Hold

t_H

30

10

t_S

Data to CS Setup Time

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

51

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

32

ALE

33

34

35

AD 7–0

CS

Address

Data

40

Address

Data

36

46 47

43

38

37

39

41

42

RD

17348B-42

Register Read with Muliplexed Address Data Bus

32

ALE

33

34

51

Data

52

35

AD 7–0

Address

Data

57

Address

54

43

50

CS

48

49

53

WR

17348B-43

Register Write with Multiplexed Address Data Bus

52

Am53CF94/Am53CF96

P R E L I M I N A R Y

Register Read/Write with Multiplexed Address Data Bus

AMD

Parameter

Symbol

No.

Parameter Description

Test Conditions

Min

Max

Unit

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

t_PWH

t_S

ALE Pulse Width High

20

10

ns

Address to ALE

Set Up Time

t_H

Address to ALE Hold Time

ALE to CS Set Up Time

t_S

t_PD

t_S

CS

to Data Valid Delay

65

30

to RD Set Up Time

0

t_PD

t_PWL

t_H

RD to Data Valid Delay

RD Pulse Width Low

30

2

RD to Data Hold Time

t_H

RD to CS

RD to Data High Impedance

CS to ALE Set Up Time

Hold Time

0

t_Z

30

t_S

50

2

PARAMETER DOES NOT EXIST

t_PD

t_Z

CS

CS to Data High Impedance

CS to WR Set Up Time

to Data Hold Time

ns

t_S

0

30

15

50

0

t_PWL

t_S

WR Pulse Width Low

Data to WR Set Up Time

t_S

WR to ALE

Data to WR

Set Up Time

Hold Time

t_H

WR to CS Hold Time

CS to Data Hold Time

0

t_H

30

PARAMETER DOES NOT EXIST

Data Setup to CS

t_S

10

ns

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

53

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

DREQ

58

62

63

59

DACK

60

65

66

64

61

DMA 15–0

DMAP 1–0

17348B-44

DMA Read without Byte Control

DREQ

DACK

58

62

59

63

64

60

68

69

71

DMAWR

72

75

74

70

73

DMA 15–0

DMAP 1–0

17348B-45

DMA Write without Byte Control

54

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

DMA Read/Write without Byte Control

Parameter

No.

Symbol

Parameter Description

DACK to DREQ Valid Delay

DACK to DACK period

Test Conditions

Min

Max

Unit

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

t_PD

t_P

30

ns

95

45

t_PWL

t_PD

t_P

DACK Pulse Width Low

DACK to Data Valid Delay

DACK to DREQ Valid Delay

30

DACK to DACK

period

t_L+25

12

t_PWH

t_Z

DACK Pulse Width High

DACK to Data High Impedance

DACK to Data Hold Time

PARAMETER DOES NOT EXIST

DACK to DMAWR Set Up Time

DMAWR Pulse Width Low

25

t_H

2

t_S

t_PWL

t_S

0

ns

30

15

0

Data to DMAWR Set Up Time

DMAWR to DACK Hold Time

DMAWR Pulse Width High

t_H

t_PWH

t_H

25

0

Data to DMAWR Hold Time

Data to DACK Set Up Time

DACK to Data Hold Time

t_S

10

t_H

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

55

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

DREQ

76

87

77

88

DACK

78

89

AS 0

BHE

83

84

80

79

81

DMARD

85

86

92

93

82

91

DMA 15–0

DMAP 1–0

17348B-46

DMA Read with Byte Control

DREQ

76

87

77

88

DACK

78

89

AS 0

BHE

99

98

95

94

96

DMAWR

100

101

103

102

97

DMA 15–0

DMAP 1–0

17348B-47

DMA Write with Byte Control

56

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

DMA Read/Write with Byte Control

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

t_PD

t_P

t_PWL

t_S

DACK to DREQ Valid Delay

DACK to DACK period

DACK Pulse Width Low

30

ns

95

45

0

DACK to DMARD

Set Up Time

t_S

BHE, AS0 to DMARD Set Up Time

DMARD Pulse Width Low

20

35

t_PWL

t_PD

t_H

DMARD to Data Valid Delay

BHE, AS0 to DMARD Hold Time

DMARD to DACK Hold Time

DMARD to Data High Impedance

DMARD to Data Hold Time

DACK to DREQ Valid Delay

DACK to DACK period

35

20

0

t_H

ns

t_Z

35

30

t_H

2

t_PD

t_P

t_L+ 25

12

t_PWH

DACK Pulse Width High

PARAMETER DOES NOT EXIST

DACK to Data Valid Delay

DACK to Data Hold Time

t_PD

t_H

30

25

ns

2

t_z

DACK to Data High Impedance

DACK to DMAWR Set Up Time

BHE, AS0 to DMAWR Set Up Time

DMAWR Pulse Width Low

t_S

0

t_S

20

30

15

20

0

t_PWL

t_S

Data to DMAWR Set Up Time

BHE, AS0 to DMAWR Hold Time

t_H

DMAWR to DACK

Hold Time

t_PWH

t_H

DMAWR Pulse Width High

Data to DMAWR Hold Time

DACK to Data Hold Time

Data to DACK Set Up Time

25

0

t_H

10

t_S

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

57

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

DREQ

DACK

RD

115

116

104

105

112

109

107

106

119

118

110

113

114

108

117

DMA 15–0

DMAP 1–0

17348B-48

Burst DMA Read without Byte Control—Modes 0 and 1

DREQ

DACK

104

115

116

105

126

121

124

125

DMAWR

120

122

123

DMA 15–0

DMAP 1–0

17348B-49

Burst DMA Write without Byte Control—Modes 0 and 1

58

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Burst DMA Read/Write Mode 0, 1

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

t_PD

t_PWL

t_S

DACK to DREQ Valid Delay

DACK Pulse Width Low

30

ns

70

0

DACK

to RD Set Up Time

t_P

RD to DACK Hold Time

RD to Data Valid Delay

RD Pulse Width High

0

t_PD

55

t_PWH

t_PWL

60

70

RD Pulse Width Low

PARAMETER DOES NOT EXIST

RD to DREQ Valid Delay

RD to Data High Impedance

RD to Data Hold Time

t_PD

t_Z

90

45

ns

t_H

2

60

2

t_PD

t_PWH

t_PD

t_H

DACK to DREQ Valid Delay

DACK Pulse Width High

30

35

DACK to Data Valid Delay

DACK to Data Hold Time

DACK to Data High Impedance

DACK to DMAWR Set Up Time

DMAWR Pulse Width High

DMAWR Pulse Width Low

t_Z

25

t_S

0

t_PWH

t_PWL

t_S

60

70

15

Data to DMAWR

DMAWR to DREQ Valid Delay

Data to DMAWR Hold Time

DMAWR to DACK Hold Time

Set Up Time

t_PD

t_H

90

0

t_H

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

59

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

DREQ

138

127

128

139

140

DACK

AS 0

BHE

129

134

132

135

DMARD

130

133

136

137

144

143

131

142

DMA 15–0

DMAP 1–0

17348B-50

Burst DMA Read with Byte Control—Mode 2

DREQ

127

138

139

128

DACK

AS 0

BHE

149

146

147

150

151

153

DMAWR

145

148

152

DMA 15–0

DMAP 1–0

17348B-51

Burst DMA Write with Byte Control—Mode 2

60

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Burst DMA–Mode 2

Parameter

Symbol

No.

Parameter Description

Test Conditions

Min

Max

Unit

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

t_PD

t_PWL

t_S

DACK to DREQ Valid Delay

DACK Pulse Width Low

30

ns

70

20

0

BHE, AS0 to DMARD Set Up Time

DACK to DMARD Set Up Time

DMARD to Data Valid Delay

DMARD Pulse Width High

t_S

t_PD

t_PWH

t_PWL

t_H

55

60

70

20

DMARD Pulse Width Low

BHE, AS0 to DMARD Hold Time

DMARD to DREQ Valid Delay

DMARD to Data High Impedance

DMARD to Data Hold Time

DACK to DREQ Valid Delay

DACK Pulse Width High

t_PD

t_Z

90

45

t_H

2

t_PD

t_PWH

t_H

30

60

0

DMARD to DACK Hold Time

PARAMETER DOES NOT EXIST

DACK to Data Valid Delay

DACK to Data Hold Time

t_PD

t_H

35

25

ns

2

t_Z

DACK to Data High Impendance

DACK to DMAWR Set Up Time

BHE, AS0 to DMAWR Set Up Time

DMAWR Pulse Width High

t_S

0

t_S

20

60

70

20

t_PWH

t_PWL

t_H

DMAWR Pulse Width Low

BHE, AS0 to DMAWR Hold Time

t_PD

t_H

DMAWR to DREQ

Valid Delay

90

Data to DMAWR Hold Time

Data to DMAWR Set Up Time

0

15

0

t_S

t_H

DMAWR to DACK

Hold Time

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

61

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

DREQ

154

157

158

DACK

159

160

155

156

DMA 15–0

DMAP 1–0

17348B-52

Burst DMA Read without Byte Control—Mode 3

DREQ

DACK

154

168

158

157

155

165

162

166

DMAWR/

163

167

164

DMA 15–0

DMAP 1–0

17348B-53

Burst DMA Write without Byte Control—Mode 3

62

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

Burst DMA Mode 3

Parameter

Symbol

No.

Parameter Description

Test Conditions

Min

Max

Unit

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

t_PD

t_PWL

t_PD

t_PWH

t_Z

DACK to DREQ Valid Delay

DACK Pulse Width Low

30

ns

70

DACK to Data Valid Delay

DACK to DREQ Valid Delay

DACK Pulse Width High

35

30

60

2

DACK to Data High Impedance

DACK to Data Hold Time

25

t_H

PARAMETER DOES NOT EXIST

DACK to DMAWR Set Up Time

DMAWR Pulse Width Low

t_S

t_PWL

t_S

0

70

15

0

ns

Data to DMAWR Set Up Time

DMAWR to DACK Hold Time

DMAWR Pulse Width High

t_H

t_PWH

t_H

60

0

Data to DMAWR Hold Time

DACK to DREQ Valid Delay

t_PD

90

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

63

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

SDC 7–0

SDCP

169

170

ACKC

172

171

REQ

17348B-54

Asynchronous Initiator Send

Single Ended:

Parameter

Symbol

No.

Parameter Description

Test Conditions

Min

Max

Unit

169

170

171

172

t_S

Data to ACKC

Set Up Time

60

5

ns

t_PD

REQ to Data Delay

REQ to ACKC

Delay

50

Differential:

No.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

169

170

171

172

t_S

Data to ACKC

Set Up Time

70

5

ns

t_PD

REQ to Data Delay

REQ to ACKC

Delay

25

30

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

64

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

SD 7–0

SDP

176

ACKC

REQ

174

173

175

17348B-55

Asynchronous Initiator Receive

Single Ended:

Parameter

Symbol

No.

Parameter Description

Test Conditions

Min

Max

Unit

173

174

175

176

t_PD

t_S

REQ to ACKC

Delay

50

ns

Data to REQ Set Up Time

REQ to Data Hold Time

0

t_H

18

Differential:

No.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

173

174

175

176

t_PD

t_S

REQ to ACKC

Delay

25

30

ns

Data to REQ Set Up Time

REQ to Data Hold Time

0

t_H

18

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

65

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

SD 7–0

SDP

177

178

REQC

ACK

179

180

17348B-56

Asynchronous Target Send

Single Ended:

Parameter

Symbol

No.

Parameter Description

Data to REQC Set Up Time

to Data Hold Time

Test Conditions

Min

Max

Unit

177

178

179

180

t_S

t_H

60

5

ns

ACK

t_PD

to REQC

Delay

50

45

Differential:

Parameter

No.

Symbol

Parameter Description

Data to REQC Set Up Time

to Data Hold Time

Test Conditions

Min

Max

Unit

177

178

179

180

t_S

t_H

70

5

ns

ACK

t_PD

to REQC

Delay

30

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

66

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

SDC 7–0

SDCP

183

184

REQC

ACK

181

182

17348B-57

Asynchronous Target Receive

Single Ended:

Parameter

Symbol

No.

Parameter Description

Test Conditions

Min

Max

Unit

181

182

183

184

t_PD

t_S

ACK to REQC

Delay

50

45

ns

Data to ACK Set Up Time

ACK to Data Hold Time

0

t_H

18

Differential:

No.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

181

182

183

184

t_PD

t_S

ACK to REQC

Delay

30

ns

Data to ACK Set Up Time

ACK to Data Hold Time

0

t_H

18

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

67

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

SDC 7–0

SDCP

188

186

185

187

REQC

ACKC

17348B-58

Synchronous Initiator Target Transmit

Normal SCSI: (Single Ended)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

185

t_S

ACKC or REQC

Set Up Time

to Data

55

ns

186

187

188

t_PWL

t_PWH

t_H

REQC or ACKC Pulse Width Low

REQC or ACKC Pulse Width High

ACKC or REQC to Data Hold Time

90

ns

100

Fast SCSI: (Single Ended)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

185

t_S

ACKC or REQC

Set Up Time

to Data

25

ns

186

187

188

t_PWL

t_PWH

t_H

REQC or ACKC Pulse Width Low

REQC or ACKC Pulse Width High

ACKC or REQC to Data Hold Time

30

35

ns

Normal SCSI: (Differential)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

185

t_S

ACKC or REQC to Data

Set Up Time

65

ns

186

187

188

t_PWL

t_PWH

t_H

REQC or ACKC Pulse Width Low

REQC or ACKC Pulse Width High

ACKC or REQC to Data Hold Time

96

ns

110

Fast SCSI: (Differential)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

185

t_S

ACKC or REQC

Set Up Time

to Data

35

ns

186

187

188

t_PWL

t_PWH

t_H

REQC or ACKC Pulse Width Low

REQC or ACKC Pulse Width High

ACKC or REQC to Data Hold Time

40

45

ns

* The minimum values have a wide range since they depend on the Synchronization latency. The synchronization latency, in

turn, depends on the operating frequency of the device.

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

68

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

SDC 7–0

SDCP

192

189

191

190

REQ

ACK

17348B-59

Synchronous Initiator Target Receive

Parameter

Symbol

No.

Parameter Description

Test Conditions

Min

Max

Unit

189

190

191

192

t_PWL

t_PWH

t_S

REQ Pulse Width Low

27

20

5

ns

ACK Pulse Width Low

REQ Pulse Width High

ACK Pulse Width High

Data to REQor ACK Set Up Time

REQ or ACK to Data Hold Time

t_H

15

Note:

There is a one-to-one relationship between every AMD and Emulex Parameter (refer to Appendix B).

69

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

APPENDIX A

Pin Connection Cross Reference for Am53CF94

Pin#

AMD

Emulex

Pin#

AMD

Emulex

1

DMAP0

DBP0

43

RSTC

RSTON

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

V_SS

DB8

DB9

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

V_SS

SEL

BSY

REQ

ACK

RST

BUSMD 1

BUSMD 0

INT

RESET

WR

V_SS

DMA8

DMA9

DMA10

DMA11

DMA12

DMA13

DMA14

DMA15

DMAP1

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

SDP

SELIN

BSYIN

REQIN

ACKIN

RSTIN

MODE 1

MODE 0

INTN

DB10

DB11

DB12

DB13

DB14

DB15

DBP1

SDI0N

SDI1N

SDI2N

SDI3N

SDI4N

SDI5N

SDI6N

SDI7N

SDIPN

RESET

WRN

RDN

RD

CS

CSN

ASO [A0]

BHE [A1]

DMARD [A2]

ALE [A3]

CLK

A0/SA0

A1/BHE

A2/DBRDN

A3/ALE

CK

62

63

64

65

66

V_DD

21

V_DD

AD0

AD1

AD2

AD3

PAD0

PAD1

PAD2

PAD3

22

23

24

25

26

V_SS

SDC0

SDC1

SDC2

SDC3

SDO0N

SDO1N

SDO2N

SDO3N

67

68

69

70

71

72

73

74

V_SS

AD4

AD5

AD6

V_SS

PAD4

PAD5

PAD6

PAD7

DREQ

DACKN

DBWRN

27

28

29

30

31

32

V_SS

SDC4

SDC5

SDC6

SDC7

SDCP

SDO4N

SDO5N

SDO6N

SDO7N

SDOPN

AD7

DREQ

DACK

DMAWR

75

V_SS

33

34

35

36

37

V_SS

76

77

78

79

80

81

82

83

84

V_SS

SELC

BSYC

REQC

ACKC

SELON

BSYON

REQON

ACKON

DMA0

DMA1

DMA2

DMA3

DMA4

DMA5

DMA6

DMA7

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

38

39

40

41

42

V_SS

MSG

C/D

I/O

MSGION

CDION

IOION

ATNION

ATN

70

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

APPENDIX A

Pin Connection Cross Reference for Am53CF96

Pin#

1

2

3

4

5

6

7

8

AMD

DACK

DMAWR

NC

ISEL

V_SS

Emulex

DACKN

DBWRN

NC

IGS

V_SS

TGS

V_SS

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DBP0

V_SS

Pin#

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

AMD

SDC 7

SDC P

NC

V_SS

SELC

BSYC

REQC

ACKC

V_SS

MSG

C/D

I/O

ATN

RSTC

V_SS

SEL

BSY

REQ

ACK

Emulex

SDO7N

SDOPN

NC

V_SS

SELON

BSYON

REQON

ACKON

V_SS

TSEL

V_SS

DMA0

DMA1

DMA2

DMA3

DMA4

DMA5

DMA6

DMA7

DMAP0

V_SS

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

V_SS

MSGION

CDION

IOION

ATNION

RSTON

V_SS

DMA8

DMA9

DMA10

DMA11

DMA12

DMA13

DMA14

DMA15

DMAP1

NC

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

DB8

DB9

SELIN

BSYIN

REQIN

ACKIN

RSTIN

MODE 1

MODE 0

INTN

RESET

NC

WRN

RDN

CSN

A0/SA0

A1/BHE

A2/DBRDN

A3/ALE

CK

DIFFMN

V_DD

DB10

DB11

DB12

DB13

DB14

DB15

DBP1

NC

SDI0N

SDI1N

SDI2N

SDI3N

SDI4N

SDI5N

SDI6N

SDI7N

SDIPN

V_DD

NC

V_SS

SDO0N

SDO1N

SDO2N

SDO3N

V_SS

RST

BUSMD 1

BUSMD 0

INT

RESET

NC

WR

RD

CS

ASO [A0]

BHE [A1]

DMARD [A2]

ALE [A3]

CLK

DFMODE

V_DD

NC

AD0

AD1

AD2

AD3

V_SS

AD4

AD5

AD6

AD7

DREQ

SDP

V_DD

NC

V_SS

NC

PAD0

PAD1

PAD2

PAD3

V_SS

SDC0

SDC1

SDC2

SDC3

V_SS

PAD4

PAD5

PAD6

PAD7

DREQ

V_SS

SDC4

SDC5

SDC6

SDO4N

SDO5N

SDO6N

71

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

APPENDIX B

Emulex to AMD Timing Parameters Cross Reference

Emulex

AMD

Emulex

AMD

Emulex

AMD

Parameter #

Clock Input, Reset Input,

Interrupt Output:

DMA Interface Timing:

Alternate DMA Interface

Timing: (Continued)

1

2

3

4

5

58, 76

1

2

3

4

5

6

2

4

1

5

7

9

15

118, 143,

62, 87

64, 89

60, 78

59, 77

63, 88

80

160 (min)

119, 144,

159 (max)

16

114, 137 (min)

113, 136 (max)

6

7

17

18

19

20

21

22

23

24

25

146

149

8

83

Register Interface Timing:

9

79

120, 145, 162

122, 148, 163

126, 153, 165

124, 150, 168

121, 147, 166

123, 152, 164

125, 151, 167

1

2

10

11

10

11

12

13

14

15

81

84

None

61, 91

82

3

33

4

34

5

32

6

35

66, 92 (min)

65, 93 (max)

7

43

8

19

Asynchronous Timing:

16

86 (min)

85 (max)

9

12, 37

14, 39

16, 41

20

13, 36

15, 38

1

179, 181

10

11

12

13

14

15

2

3

4

180, 182

171, 173

172, 174

177

17

18

19

20

21

22

23

24

25

26

95

98

68, 94

69, 96

71, 99

72, 100

70, 97

73,101

74, 103

75, 102

5 (REQON)

5 (ACKON)

6 (REQIN)

6 (ACKIN)

7 (REQIN)

7 (ACKIN)

8 (REQIN)

8 (ACKIN)

169

170

178

175

183

176

184

21, 46 (min)

22, 47 (max)

16

18, 40 (min)

17, 42 (max)

17

18

19

20

21

22

23

24

25

26

23, 48

24, 49

26, 53

27

28

51

25, 50

29, 52

31, 57

30, 54

Alternate DMA Interface

Timing:

Synchronous Timing:

1

2

3

4

5

104, 127, 154

1

2

3

4

5

6

7

8

9

186

115, 138, 157

116, 139, 158

105, 128, 155

129

187

185

188

189

190

189

190

191

192

6

134

7

8

9

10

11

12

13

14

106, 130

110, 133

107, 140

112, 135

109, 132

None

10

117, 142, 156

108, 131

72

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

PHYSICAL DIMENSIONS*

PL 084

Plastic Leaded Chip Carrier (measured in inches)

.020

MIN

.050

.042

.048

REF

.042

.056

.025

.045

R

.013

.021

.026

.032

1.185 1.150

1.195 1.156

1.000 1.090

REF 1.130

.007

.013

1.150

1.156

1.185

1.195

.090

.130

09980B

CG08 PL 084

8/14/92 c dc

.165

.180

TOP VIEW

SIDE VIEW

* For reference only. BSC is an ANSI standard for Basic Space Centering.

73

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

PHYSICAL DIMENSIONS*

PQR100

Plastic Quad Flatpack Trimmed and Formed (measured in millimeters)

PQJ 100 (Plastic Quad Flat Pack; Trimmed and Formed)

(measured in millimeters)

17.10

17.30

13.90

14.10

12.35

REF

0.22

0.38

18.85

REF

19.90

20.10

23.00

23.40

0.65

REF

Pin 1 I.D.

TOP VIEW

2.60

3.00

3.35

MAX

0.70

0.90

15590D

BX 45

0.25

MIN

9/6/91 SG

SIDE VIEW

* For reference only. BSC is an ANSI standard for Basic Space Centering.

74

Am53CF94/Am53CF96

P R E L I M I N A R Y

AMD

PHYSICAL DIMENSIONS*

PQR100

Plastic Quad Flatpack with Molded Carrier Ring (measured in millimeters)

35.87

36.13

35.50

35.90

31.37

31.63

27.87

28.13

25.15

25.20

BSC

25.25

22.15

22.25

13.80

14.10

50

30

35.50 27.87 22.15

35.90 28.13 22.25

25.15

25.25

35.87 31.37

36.13 31.63

19.80

20.10

Pin 1 I.D.

100

80

0.22

0.38

.65 NOM

TOP VIEW

.45 Typ

.65 Pitch

2.00 4.80

1.80

.65 Typ

SIDE VIEW

CB 48

6/25/92 SG

* For reference only. Not drawn to scale. BSC is an ANSI standard for Basic Space Centering.

75

Am53CF94/Am53CF96

AMD

P R E L I M I N A R Y

Trademarks

AMD and Am386 are registered trademarks of Advanced Micro Devices, Inc.

GLITCH EATER is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

76

Am53CF94/Am53CF96


型号：	AM53CF94KCW
厂家：	AMD
描述：	Enhanced SCSI-2 Controller (ESC) 增强型SCSI - 2控制器（ ESC ）控制器
文件：	总76页 (文件大小：543K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM53CF94KCW [AMD]

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