AM79761_技术文档

PRELIMINARY

Am79761

Physical Layer 10-Bit Transceiver for Gigabit Ethernet

(GigaPHY™-SD)

DISTINCTIVE CHARACTERISTICS

n Gigabit Ethernet Transceiver operates at

n Low Power Operation - 700 mW typical

1.25 Gigabits per second (Gbps)

n 64-pin Standard PQFP

— 14 x 14 mm (0˚ C - 70˚ C)

— 10 x 10 mm (0˚ C - 50˚ C)

n Suitable for both Coaxial and Optical Link

applications

n 10-bit TTL Interface for Transmit and Receive

n 125 MHz TTL Reference Clock

n Loopback Diagnostic

Data

n Monolithic Clock Synthesis and Clock Recovery

requires no external components

n Single +3.3 V Supply

n Word Synchronization Function (Comma

Detect)

GENERAL DESCRIPTION

The Am79761 Gigabit Ethernet Physical Layer Serial-

izer/Deserializer (GigaPHY-SD) device is a 1.25 Gbps

Ethernet Transceiver optimized for Gigabit Ethernet/

1000BASE-X applications. It implements the Physical

Medium Attachment (PMA) layer for a single port.

When transmitting, the GigaPHY-SD device receives

10-bit 8B/10B code groups at 125 million code groups

per second. It then serializes the parallel data stream,

adding a reference clock, and transmits it through the

PECL drivers.

The GigaPHY-SD device can interface to ﬁber-optic

media to support 1000BASE-LX and 1000BASE-SX

applications and can interface to copper coax to sup-

port 1000BASE-CX applications.

When receiving, the GigaPHY-SD device receives the

PECL data stream from the network. It then recovers

the clock from the data stream, deserializes the data

stream into a 10-bit code group, and transmits it to the

Physical Coding Sublayer (PCS) logic above. Option-

ally, it detects comma characters used to align the in-

coming word.

The functions performed by the device include serializ-

ing the 8B/10B 10-bit data for transmission, deserializ-

ing received code groups, recovering the clock from the

incoming data stream, and word synchronization.

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication# 21560 Rev: A Amendment/+1

Issue Date: April 1998

P R E L I M I N A R Y

BLOCK DIAGRAM

TX+

TX-

10

Parallel

to Serial

TXD[0:9]

D Q

PLL Clock

Multiply

REFCLK

EWRAP

10

Serial to

Parallel

RXD[0:9]

Q D

Clock

Recovery

RX+

10

20

RX-

RCLK

RCLKN

Comma

Detect

Frame

Logic

COM_DET

EN_CDET

21560A-1

2

Am79761

P R E L I M I N A R Y

CONNECTION DIAGRAM

N/C

DVSS

TXD0

TXD1

TXD2

DVDD

TXD3

TXD4

TXD5

TXD6

DVDD

TXD7

TXD8

TXD9

DVSS

N/C

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

COM_DET

DVSS_T

RXD0

RXD1

RXD2

DVDD_T

RXD3

RXD4

RXD5

RXD6

DVDD_T

RXD7

RXD8

RXD9

DVSS_T

9

10

11

12

13

14

15

16

21560A-2

Note:

N/C = No Connect

LOGIC SYMBOL

DVDD

DVDD_T

DVDD_P AVDD

REFCLK

RCLK

RCLKN

TXD [0:9]

To PCS

RXD [0:9]

PHY

Control

EN_CDET

EWRAP

COM_DET

Am79761

GigaPHY-SD

TX+

TX–

TEST4

Test

Port

Transceiver

RX+

RX–

TDST [3:1]

DVSS

DVSS_D

DVSS

21560A-3

Am79761

3

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges.The order number (Valid Combination) is formed

by a combination of the elements below.

Am79761

Y

C

-10

PACKAGE SIZE OPTION

-10 = 10 x 10 mm body size

-14 = 14 x 14 mm body size

TEMPERATURE RANGE

C = Commercial (0˚C to +70˚C)

PACKAGE TYPE

Y = 64-Pin Plastic Quad Flat Pack (PDH064)

DEVICE NUMBER/DESCRIPTION

Am79761

Physical Layer 10-Bit Transceiver for Gigabit Ethernet

GigaPHY™-SD)

Valid Combinations

Valid Combinations list conﬁgurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

ofﬁce to conﬁrm availability of speciﬁc valid combinations and

to check on newly released combinations.

Am79761YC

-10

-14

4

Am79761

P R E L I M I N A R Y

RELATED PRODUCTS

Part No.

Description

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Am79C983

Am79C984A

Am79C985

Am79C987

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Am79C900

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Am79C961

Am79C961A

Am79C965

Am79C970

Am79C970A

Am79C971

CMOS Local Area Network Controller for Ethernet (C-LANCE)

Twisted Pair Ethernet Transceiver (TPEX)

Twisted Pair Ethernet Transceiver Plus (TPEX+)

Quad Fast Ethernet Transceiver for 100BASE-X Repeaters (QFEXr™)

Integrated Multiport Repeater Plus (IMR+™)

basic Integrated Multiport Repeater (bIMR™)

Integrated Multiport Repeater 2 (IMR2™)

enhanced Integrated Multiport Repeater (eIMR™)

enhanced Integrated Multiport Repeater Plus (eIMR+™)

Hardware Implemented Management Information Base (HIMIB™)

Quad Integrated Ethernet Transceiver (QuIET™)

Integrated Local Area Communications Controller (ILACC™)

Media Access Controller for Ethernet (MACE™)

PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)

PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support)

PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA

PCnet™-32 Single-Chip 32-Bit Ethernet Controller

PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)

PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)

PCnet™-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus

Am79761

5

P R E L I M I N A R Y

PIN DESIGNATION

Listed by Pin Number

Pin No.

Pin Name

DVSS

TXD0

TXD1

TXD2

DVDD

TXD3

TXD4

TXD5

TXD6

DVDD

TXD7

TXD8

TXD9

DVSS

N/C

Pin No.

17

Pin Name

N/C

Pin No.

33

Pin Name

DVSS_T

RXD9

Pin No.

49

Pin Name

N/C

1

2

18

TEST1

EWRAP

TEST2

DVSS

34

50

DVDD

DVSS

RX-

3

19

35

RXD8

51

4

20

36

RXD7

52

5

21

37

DVDD_T

RXD6

53

DVDD_P

RX+

6

22

REFCLK

TEST3

EN_CDET

DVSS

38

54

7

23

39

RXD5

55

DVDD

DVSS

AVDD

AVSS

DVDD

DVDD_P

TX-

8

24

40

RXD4

56

9

25

41

RXD3

57

10

11

12

13

14

15

16

26

TEST4

N/C

42

DVDD_T

RXD2

58

27

43

59

28

DVDD

44

RXD1

60

29

DVDD_T

RCLKN

RCLK

45

RXD0

61

30

46

DVSS_T

COM_DET

N/C

62

TX+

31

47

63

DVDD_P

N/C

32

DVSS_T

48

64

6

Am79761

P R E L I M I N A R Y

EN_CDET

PIN DESCRIPTION

TX+,TX-

Serial Transmit Data

PECL Output

Enable Comma Detect

TTL Input

These pins are the 1000BASE-X port differential driv-

ers which transmit the serial stream to the network.

These pins are connected to the copper or ﬁber optic

connectors.

This pin is used to enable the word synchronization

mode. When logic HIGH, the COM_DET output is en-

abled and word synchronization is active.

COM_DET

When EWRAP is LOW, the pins assume normal oper-

ation. When HIGH, TX+ is logic HIGH and TX- is logic

LOW.

Comma Detect Indicator

TTL Output

Comma Detect is asserted to indicate that the incoming

word on RXD[0:9] contains a Comma character

(0011111xxx). COM_DET goes HIGH for half of a RCLK

period, and can be captured when RCKLN is rising.

RX+, RX-

Serial Receive Data

PECL Input

These pins are the 1000BASE-X port differential re-

ceiver pair, receiving a serial stream of data from the

network. These pins are connected to the copper or

ﬁber optic connectors.

In order for COM_DET to provide indication, EN_CDET

must be enabled (logic HIGH).

EWRAP

Loopback Enable

TTL Input

When EWRAP is LOW, the pins assume normal oper-

ation. The pins are internally biased.

When EWRAP is asserted, the transmitted data stream

is sent back to the receiver through an internal loop-

back path. TX+ is logic HIGH, and TX- is logic LOW in

this mode.

TXD[0:9]

Transmit Data

TTL Input

The TXD[0:9] pin is a set of 10 data signals which are

driven from the Physical Coding Sublayer (PCS) above.

The 10 bits of data are clocked in parallel on the rising

edge of REFCLK. TXD0 is transmitted ﬁrst on TX±.

This pin is logic LOW for normal operation.

TEST[1:3]

Factory Test Pins

Input

RXD[0:9]

Receive Data

TTL Output

These pins should be tied to DVDD for normal operation.

TEST[4]

Factory Test Pin

Output

The RXD[0:9] pin is a set of 10 data signals which are

sent to the Physical Coding Sublayer (PCS) above.The

10 bits of data are clocked out in parallel on the rising

edges of RCLK and RCLKN. RXD0 is received ﬁrst on

RX±.

This pin should be left unconnected for normal operation.

DVDD

Power

REFCLK

These pins supply power to the digital blocks of the

Reference Clock

TTL Input

device.They must be connected to a 3.3 V ±5% source.

DVDD_T

This input is used for the 125-Mhz clock. The rising

edge of this clock latches TXD[0:9] into an input regis-

ter. This clock serves as the reference clock at 1/10th

the baud rate for the PLL.

TTL Power

These pins supply power to the TTL blocks of the de-

vice. They must be connected to a 3.3 V ±5% source.

DVDD_P

PECL Power

RCLK, RCLKN

Receive Clock

TTL Output

These pins supply power to the PECL blocks of the de-

vice.They must be connected to a 3.3 V ±5% source. It

is critical that the signal supplied to these pins are

clean to ensure good performance of the device.

These pins provide the differential receive clock sig-

nals, derived from the RX± data stream, and are at

1/20th the baud rate of the receive stream. Parallel data

on RXD[0:9] is provided at each rising transition of

RCLK and RCLKN.

Am79761

7

P R E L I M I N A R Y

AVDD

Analog Power

DVSS_T

Ground

These pins supply power to the analog blocks of the

device. They must be connected to a 3m.3 V ±5%

source and require careful decoupling to ensure

proper device performance.

These pins are the ground connections for the TTL

blocks. They must be connected to the common exter-

nal ground plane.

AVSS

DVSS

Ground

These pins are the ground connections for the

analog blocks. They must be connected to an analog

ground plane.

These pins are the ground connections for the digital

blocks. They must be connected to the common

external ground plane.

8

Am79761

P R E L I M I N A R Y

FUNCTIONAL DESCRIPTION

Overview

Clock Synthesizer

The Am79761 clock synthesizer multiplies the refer-

ence frequency provided on the REFCLK pin by 10 to

achieve a baud rate clock at nominally 1.25 GHz. The

clock synthesizer contains a fully monolithic PLL which

does not require any external components.

The GigaPHY-SD device provides the PMA functionality

for 1000BASE-X systems. The GigiaPHY-SD communi-

cates with the PCS through the 10-bit code groups and

communicates with the Physical Medium Dependent

(PMD) layer to transmit and receive data from the net-

work, through either ﬁber optic or copper coax media.

Serializer

The Am79761 device accepts TTL input data as a par-

allel 10-bit character on the TXD[0:9] bus which is

latched into the input latch on the rising edge of

REFCLK. This data will be serialized and transmitted

on the TX PECL differential outputs at a baud rate of

ten times the frequency of the REFCLK input, with bit

TXD0 transmitted ﬁrst. User data should be encoded

for transmission using the 8B/10B block code de-

scribed in the IEEE 802.3 speciﬁcation.

The GigaPHY-SD device consists of the following

functional blocks:

n 1000BASE-X Transmit block including:

— Clock Synthesizer

— Serializer and Transmission interface

n 1000BASE-X Receive block including:

— Clock Recovery

Transmission Character Interface

— Deserializer

An encoded byte is 10 bits and is referred to as a trans-

mission character. The 10-bit interface on the

Am79761 device corresponds to a transmission char-

acter. This mapping is shown in Table 20.

— Word Alignment and synchronization

Table 20. Transmission Order and Mapping of an 8B/10B Character

Parallel Data Bits

8B/10B Bit Position

Comma Character

T9

j

T8

h

T7

g

T6

f

T5

i

T4

e

T3

d

T2

c

T1

b

T0

a

X

1

0

First Data Bit

Transmitted

Last Data Bit

Transmitted

downstream controller chip.The clocks are generated by

dividing down the high-speed clock which is phase

locked to the serial data. The serial data is re-timed by

the internal high-speed clock and deserialized.

Clock Recovery

The Am79761 device accepts differential high speed

serial inputs on the RX± pins, extracts the clock and

retimes the data.The Am79761 clock recovery circuitry

is completely monolithic and requires no external com-

ponents. For proper operation, the baud rate of the

data stream to be recovered should be within 0.01% of

ten times the REFCLK frequency. For example, if the

REFCLK used is 125 MHz, then the incoming serial

baud rate must be 1.25 gigabaud ±0.01 percent.

The resulting parallel data will be captured by the

adjoining protocol logic on the rising edges of RCLK and

RCLKN. In order to maximize the setup and hold times

available at this interface, the parallel data is loaded into

the output register at a point nominally midway between

the transition edges of RCLK and RCLKN.

If serial input data is not present or does not meet the

required baud rate, the Am79761 will continue to pro-

duce a recovered clock so that downstream logic may

continue to function. The RCLK and RCLKN output

frequency under these circumstances may differ from

their expected frequency by no more than ±1 percent.

Deserializer

The re-timed serial bit stream is converted into a 10-bit

parallel output character.The Am79761 device provides

complementary TTL recovered clocks, RCLK and

RCLKN, which are at 1/20th of the serial baud rate.This

architecture is designed to simplify demultiplexing of the

10-bit data characters into a 20-bit half-word in the

Am79761

9

P R E L I M I N A R Y

properly in RXD[0:9]. This results in proper character

Word Alignment

and half-word alignment. When the parallel data

alignment changes in response to an improperly

aligned comma pattern, some data which would have

been presented on the parallel output port may be

lost. However, the synchronization character and

subsequent data will be output correctly and properly

aligned. When EN_CDET is LOW, the current align-

ment of the serial data is maintained indeﬁnitely,

regardless of data pattern.

The Am79761 device provides 7-bit comma character

recognition and data word alignment. Word synchroni-

zation is enabled by asserting EN_CDET HIGH. When

synchronization is enabled, the Am79761 device con-

stantly examines the serial data for the presence of the

Comma character.This pattern is 0011111XXX, where

the leading zero corresponds to the ﬁrst bit received.

The comma sequence is not contained in any normal

8B/10B coded data character or pair of adjacent char-

acters. It occurs only within special characters, known

as K28.1, K28.5, and K28.7, which are deﬁned speciﬁ-

cally for synchronization purposes. Improper alignment

of the comma character is deﬁned as any of the follow-

ing conditions:

When encountering a comma character, COM_DET is

driven HIGH to inform the user that realignment of the

parallel data ﬁeld may have occurred. The COM_DET

pulse is presented simultaneously with the comma char-

acter and has a duration equal to the data, or half of an

RCLK period.The COM_DET signal is timed such that it

can be captured by the adjoining protocol logic on the

rising edge of RCLKN. Functional waveforms for

synchronization are given in Figure 18 and Figure 19.

1. The comma is not aligned within the 10-bit trans-

mission character such that TXD0...TXD6 =

“0011111.”

2. The comma straddles the boundary between two

10-bit transmission characters.

Figure 18 shows the case when a comma character is

detected and no phase adjustment is necessary. It illus-

trates the position of the COM_DET pulse in relation to

the comma character on RXD[0:9]. Figure 19 shows the

case where K28.5 is detected, but it is out of phase and

a change in the output data alignment is required. Note

that up to three characters prior to the comma character

may be corrupted by the realignment process.

3. The comma is properly aligned but occurs in the re-

ceived character presented during the rising edge

of RCLK rather than RCLKN.

When EN_CDET is HIGH and an improperly aligned

comma is encountered, the internal data is shifted in

such a manner that the comma character is aligned

RCLK

RCLKN

COM_DET

RXD[0:9]

K28.5

TChar

21560A-4

Note : TChar = 10-bit Transmission Character

Figure 18. Detection of a Properly Aligned Comma Character

10

Am79761

P R E L I M I N A R Y

RCLK

RCLKN

COM_DET

RXD[0:9]

K28.5

TChar

K28.5

TChar

Potentially Corrupted

21560A-5

Figure 19. Receiving Two Consecutive K28.5 + TCharacter Transmission Words

Am79761

11

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature . . . . . . . . . . . .-65° C to +150° C

Ambient Temperature Under Bias . .-55° C to +125° C

Temperature (T ) 0° C to +70° C for 14 x 14 mm PQFP

A

. . . . . . . . . . . . . 0° C to +50° C for 10 x 10 mm PQFP

Power Supply Voltage (V ) . . . . . . . -0.5 V to +4.0 V

Power Supply Voltage (D

) . . . . . . . . . +3.3 V ±5%

DD

VDD

DC Voltage (PECL Inputs) . . . . . .-0.5 V to V +0.5 V

Operating ranges deﬁne those limits between which

functionality of the device is guaranteed.

DD

DC Voltage (TTL Inputs). . . . . . . . . . . -0.5 V to +5.5 V

Output Current (TTL Outputs) . . . . . . . . . . . . -±50 mA

Output Current (PECL Outputs). . . . . . . . . . . -±50 mA

Maximum Input ESD (Human Body Model) . . . 1500 V

Stresses above those listed under Absolute Maximum

Ratings may cause permanent device failure.

Functionality at or above these limits is not implied.

Exposure to absolute maximum ratings for extended

periods may affect device reliability.

DC CHARACTERISTICS (over recommended operating conditions)

Symbol

Parameter Description

Input HIGH voltage (TTL)

Input LOW voltage (TTL)

Input HIGH current (TTL)

Input LOW current (TTL)

Output HIGH voltage (TTL)

Output LOW voltage (TTL)

Test Conditions

Min

2.0

0

Typ

—

Max

5.5

Unit

V

IH

—

0.8

V

IL

I

V

=2.4 V

—

50

—

500

-500

—

µA

V

IH

IL

IN

=0.5 V

—

IN

V

I

= -1.0 mA

= +1.0 mA

2.4

—

OH

OL

I

—

0.5

V

OL

TX Output differential peak-to-

peak voltage swing

∆V

75 Ω to V – 2.0 V

1200

400

—

2200

3200

290

mVp-p

mA

OUT75

OUT50

IN

DD

TX Output differential peak-to-

peak voltage swing

50 Ω to V – 2.0 V

DD

Receiver differential peak-to-

peak Input Sensitivity RX

Internally biased to V /2

—

DD

Outputs open,

I

Supply Current

210

700

DD

V

= V max

DD

Outputs open,

P

Power dissipation

—

1000

mW

D

V

= V max

DD

12

Am79761

P R E L I M I N A R Y

D_VDD

INPUT

Current

Limit

INPUT

R

INPUT

All Resistors

3.3K

D_VSS

High Speed Differential Input

REFCLK and TTL Inputs

A

(RX±)

B

21560A-6

Figure 20. Input Structures

Am79761

13

P R E L I M I N A R Y

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Must be

Steady

Will be

Steady

May

Change

from H to L

Will be

Changing

from H to L

May

Change

from L to H

Will be

Changing

from L to H

Don’t Care,

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center

Line is High-

Impedance

“Off” State

KS000010-PAL

AC CHARACTERISTICS

REFCLK

T₁

T₂

TXD[0:9]

10 Bit Data

Data Valid

21560A-7

Figure 21. Transmit Timing Waveforms

Table 21. Transmit AC Characteristics

Test Conditions

Symbol

Parameter Description

Min

Max

Unit

Measured between the valid data

level of TXD[0:9] to the 1.4 V point of

REFCLK

TXD[0:9] Setup time to the rising

edge of REFCLK

T

1.5

—

ns

1

2

TXD[0:9] hold time after the rising

edge of REFCLK

T

1.0

—

ns

ps

20% to 80%, 75 Ω load toV ,Tested

on a sample basis

SS

T

,T

TX± rise and fall time

300

SDR SDF

Latency from rising edge of

REFCLK to TXD0 appearing on

TX±-

bc = Bit clocks

T

11bc - 1ns

—

LAT

ns = Nano second

14

Am79761

P R E L I M I N A R Y

AC CHARACTERISTICS (Continued)

T₄

T₃

RCLK

RCLKN

T₁

Data Valid

T₂

RXD[0:9]

Data Valid

21560A-8

Figure 22. Receive Timing Waveform

Table 22. Receive AC Characteristics

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Data or COM_DET Valid prior

to RCLK/RCLKN rise

Measured between the 1.4 V

point of RCLK or RCLKN and a

valid level of RXD[0:9]. All

outputs driving 10 pF load.

T

3.0

—

ns

1

Data or COM_DET Valid after

RCLK or RCLKN rise

2.0

—

ns

2

Deviation of RCLK rising edge

to RCLKN rising edge delay

from nominal.

Nominal delay is 10 bit times.

Tested on sample basis

T

-500

500

ps

3

4

f_baud

delay= ----------- ± T ₃

10

Deviation of RCLK, RCLKN

frequency from nominal.

Whether or not locked to serial

data

T

-1.0

1.0

%

f_REFCLK

f

_RCLK= ------------------- ± T₄

2

RXD[0:9], COM_DET, RCLK, Between V

and V

,

IL(MAX)

IH(MIN)

T , T

—

2.4

ns

—

R

F

RCLKN rise and fall time

into 10 pf load.

bc = Bit clock

R

T

Latency from RX± to RXD[0:9]

15 bc + 2 ns

34 bc + 2 ns

lat

ns = Nano second

8B/10B IDLE pattern.

Data acquisition lock time @

1.25 Gbps

—

2.0

40

µs

LOCK

Tested on a sample basis

-12

Receive Data

Jitter

Receive Data Jitter Power

dBc, RMS for 10 Bit Error

Ratio Tested on a sample basis

1

-------------------------------

2 × BitTime

ps

PhaseNoise

∫

100KHz

Am79761

15

P R E L I M I N A R Y

REFERENCE CLOCK REQUIREMENTS

T_L

T_H

V_ih(min)

V_il(max)

REFCLK

21560A-9

Figure 23. REFCLK Timing Waveform

Table 23. Reference Clock Requirements

Symbol

Parameter Description

Test Conditions

Min

Max

Units

Range over which both transmit and

receive reference clocks on any link may be

centered

FR

Frequency Range

Frequency Offset

123

127

MHz

Maximum frequency offset between

transmit and receive reference clocks on

one link

FO

DC

-200

200

ppm

REFCLK duty cycle

Measured at 1.5 V

30

—

70

%

T

,T

REFCLK rise and fall time

Between V

and V

IH(MIN)

1.0

ns

RCR RCF

IL(MAX)

16

Am79761

P R E L I M I N A R Y

MEASUREMENTS

Serial Input Rise and Fall Time

TTL Input and Output Rise and Fall Time

V_ih(min)

V_il(max)

80%

20%

T_f

T_r

T_f

T_r

Receiver Input Eye Diagram Jitter Tolerance Task Mask

Bit Time

Amplitude

Eye Width%

Parametric Test Load Circuit

Serial Output Load

TTL AC Output Load

10 pF

75Ω

Z

₀= 75W

V_DD– 2.0 V

21560A-10

Figure 24. Parametric Measurement Information

Am79761

17

P R E L I M I N A R Y

MEASUREMENTS (Continued)

Random Jitter Measurement

BERT

Pattern

Generator

DATA

125 MHz

Trigger

Digitizing

Scope

CLK = 1.25 GHz

DATA = 00000 0000011111 11111

125 MHz

Am79761

RJ

1.25 Gbps

Single-Ended Measurement

REFCLK

TXD[0:9]

TX+

TX-

-K28.7

0011111000

-K28.7

0011111000

Random jitter (RJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section

A.4.4. Measure standard deviation of all 50% crossing points. Peak to peak RJ is ±7 sigma of distribution.

Deterministic Jitter Measurement

BERT

Pattern

Generator

DATA

PAT SYNC

125 MHz

Trigger

Digitizing

Scope

CLK = 1.25 GHz

DATA = 00000 0000011111 11111

Am79761

DJ

1.25 Gbps

Single-Ended Measurement

REFCLK

TXD[0:9]

TX+

TX-

-K28.5

0011111010

K28.5

1100000101

TRIGGER

DATA

20 bit time

19 bit time

18 bit time

Deterministic jitter (DJ) measurements

performed according to Fibre Channel

4.3 Annex A, Test Methods, Section A.4.3.

Measure time of all the 50% points of

all ten transitions. DJ is the range of

the timing variation from expected.

17 bit time

12 bit time

10 bit time

9 bit time

8 bit time

7 bit time

21560A-11

2 bit time

Figure 25. Transmitter Jitter Measurement Method

Transmitter Output Jitter Allocation

Serial data output random jitter

RMS, tested on a sample basis

(refer to Figure 8)

T

—

20

ps

rj

(RMS)

Serial data output deterministic

jitter (p-p)

Peak to peak, tested on a sample

basis (refer to Figure 8)

T

100

DJ

18

Am79761

P R E L I M I N A R Y

packages use an industry-standard EIAJ footprint, but

THERMAL CONSIDERATIONS

have been enhanced to improve thermal dissipation. The

construction of the packages are as shown in Figure 26.

The Am79761 is packaged in a 14-mm or a 10-mm

conventional PQFP with an internal heat spreader.These

Plastic Molding Compound

Copper Heat Spreader

21560A-12

Lead

Die

Bond Wire

Figure 26. Package Cross Section

Table 24. Thermal Resistance

Description

Symbol

10 mm Value 14 mm Value

Units

o

θ

Thermal resistance from junction to case

10.0

50.8

9.5

29

C/W

jc

Thermal resistance from case to ambient in still air including

conduction through the leads.

o

C/W

ca

o

θ

Thermal resistance from case to ambient with 100 LFM airﬂow

Thermal resistance from case to ambient with 200 LFM airﬂow

Thermal resistance from case to ambient with 400 LFM airﬂow

41.2

36.9

31.8

27.8

26.1

23.8

20.5

17.9

C/W

ca-100

ca-200

ca-400

ca-600

o

C/W

o

C/W

o

Thermal resistance from case to ambient with 600 LFM airﬂow

o

C/W

The Am79761 is designed to operate with a junction

temperature up to 105 C. The user must guarantee

50 C, while the 14x14 PQFP can operate in still air am-

bient temperatures of 72 C. If the ambient air tempera-

o

that the temperature speciﬁcation is not violated. With

the Thermal Resistances shown above, the 10x10

PQFP can operate in still air ambient temperatures of

ture exceeds these limits then some form of cooling

through a heatsink or an increase in airﬂow must be

provided.

Notes:

o

1. 50 C=110 C-1W*(10 C/W+50.8 C/W)

o

2. 72 C=110 C-1W*(95 C/W+29 C/W)

Am79761

19

P R E L I M I N A R Y

PHYSICAL DIMENSIONS

PDH064

64-Pin (measured in millimeters)

Trademarks

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

GigaPHY is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identiﬁcation purposes only and may be trademarks of their respective companies.

20

Am79761


型号：	AM79761
厂家：	AMD
描述：	Physical Layer 10-Bit Transceiver for Gigabit Ethernet (GigaPHY⑩-SD) 物理层的10位收发器，用于千兆位以太网（ GigaPHY ™ SD）以太网
文件：	总20页 (文件大小：134K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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