AM79C983AKCW [AMD]
Integrated Multiport Repeater 2 (IMR2⑩); 集成多端口中继器2 （ IMR2 ™ ）
| 型号： | AM79C983AKCW |
| 厂家： | 
AMD |
| 描述： | Integrated Multiport Repeater 2 (IMR2⑩) |
| 文件： | 总60页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Am79C983A
Integrated Multiport Repeater 2 (IMR2™)
DISTINCTIVE CHARACTERISTICS
n Repeater functionality compliant with IEEE
n Port switching support to allow individual ports
to be switched between multiple Ethernet
backplanes under software control
802.3 Repeater Unit specifications
n Hardware implementation of Management
Information Base (MIB) with all of the counters, n Remote Monitoring (RMON) Register Bank to
attributes, actions, and notifications specified
by IEEE 802.3 Section 19 (Layer Management)
provide direct support for etherStatsEntry and
etherStatsHistory object groups of the RMON
MIB (IETF RFC1757)
n Twelve pseudo AUI (PAUI™) ports to support
multiple media types via direct connection to
external transceivers
n Packet Report Port to provide packet
information for deriving objects in the Host,
HostTopN, and Matrix groups of the RMON MIB
(IETF RFC1578)
n One IEEE-compliant AUI port
n One reversible AUI (RAUI™) port that can be
programmed as a second AUI port or used to
connect directly to a media access controller
(MAC)
n Two user-selectable expansion bus modes:
IMR/IMR+ compatible mode and asynchronous
mode
n Simple 8-bit microprocessor interface
n Direct interface with the AMD Am79C988A
QuIET™ (Quad Integrated EthernetTransceiver) n Full LED support
to support 10BASE-T repeater designs
n 132-pin PQFP CMOS device with a single 5-V
supply
GENERAL DESCRIPTION
The Am79C983A Integrated Multiport Repeater 2
(IMR2) chip is a VLSI integrated circuit that provides a
system-level solution to designing intelligent (man-
aged) multiport repeaters. When the IMR2 device is
combined with the Quad Integrated Ethernet Trans-
ceiver (QuIET) device, it provides a cost-effective
solution to designing 10BASE-T managed repeaters.
The IMR2 device integrates the repeater functions
specified by Section 9 (Repeater Unit) and Section19
(Layer Management for 10 Mb/s Baseband Repeaters)
of the IEEE 802.3 standard.
ports between IMR2 devices. This capability allows
multiple IMR2 devices to be connected to a single
set of transceivers, thus allowing straightforward
implementations of port switching applications.
The IMR2 device also provides a Hardware Imple-
mented Management Information Base (HIMIB™),
which is a super set of the functions provided by the
Am79C987 HIMIB device. All of the necessary
counters, attributes, actions, and notifications speci-
fied by Section 19 of the IEEE 802.3 standard are
included in the IMR2 device. To facilitate the design
of managed repeaters, the IMR2 device implements
a simple 8-bit microprocessor interface.
The Am79C983A IMR2 device provides 1 standard
Attachment Unit Interface (AUI) port, 12 Pseudo
Attachment Unit Interface (PAUI) ports, and 1
Reversible AUI (RAUI) port for direct connection to
a media access controller (MAC). The pseudo AUI
ports can be connected to external transceivers to
support multiple media types, including 10BASE2,
10BASE-T, and 10BASE-FL/FOIRL. The pseudo
AUI ports can be turned off individually (without ex-
ternal circuitry) to allow the switching of transceiver
Support for an RMON MIB, as specified by the Internet
Engineering Task Force (IETF) RFC 1757, is provided.
Direct support is from an RMON Register Bank. Addi-
tional support is provided by the Packet Report Port,
which supplies information that can be used in conjunc-
tion with a microprocessor to derive various RMON
MIB attributes. With systems using multiple IMR2 de-
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 19879 Rev: B Amendment/0
Issue Date: April 1997
P R E L I M I N A R Y
vices, the information is passed to a designated IMR2
device that transfers the information to a MAC.
For application examples on building fully-managed
repeaters using the IMR2 and QuIET devices, refer to
AMD’s IMR2 Technical Manual (PID 19898A).
2
Am79C983A
P R E L I M I N A R Y
BLOCK DIAGRAM
DO±
Manchester
Decoder
FIFO
AUI
Port
DI±
Preamble
Jam
CI±
FIFO
PLL
Control
RDO±
RAUI
Port
RDI±
RCI±
Manchester
Encoder
PDO
DAT
PAUI
PDI
REQ
ACK
Port 0
PCI
COL
JAM
ECLK
IMR2
Repeater
Engine
MACEN
FRAME
XMODE
PDO
PAUI
PDI
Port 11
PCI
LD[7:0]
BSEL
CRS
Attributes and
Control Registers
(HIMIB)
COLX
PART
LINK
POL
PDAT
PCLK
D[7:0]
CS
C/D
Receiver
MAC
Engine
PENAI
PENAO
PTAG
RD
WR
RDY
INT
PDRV
SDATA[3:0]
DIR[1:0]
Transceiver
Interface
MCLK
RST
XENA
19879B-1
Am79C983A
3
P R E L I M I N A R Y
RELATED AMD PRODUCTS
Part No.
Description
Am79C981
Am79C982
Am79C987
Am79C988A
Am7990
Integrated Multiport Repeater+ (IMR+™)
basic Integrated Multiport Repeater (bIMR™)
Hardware Implemented Management Information Base(HIMIB™)
Quad Integrated Ethernet Transceiver (QuIET™)
Local Area Network Controller for Ethernet (LANCE)
IEEE 802.3/Ethernet/Cheapernet Transceiver
Am7996
Am79C90
Am79C98
Am79C100
Am79C900
Am79C940
Am79C960
Am79C961
Am79C961A
Am79C965
Am79C970
Am79C970A
Am79C974
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Twisted Pair Ethernet Transceiver (TPEX)
Twisted Pair Ethernet Transceiver Plus (TPEX+)
Integrated Local Area Communications Controller (ILACC™)
Media Access Controller for Ethernet (MACE™)
PCnet™-ISA Single-Chip Ethernet Controller (for ISA bus)
PCnet™-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft® Plug n’ Play® Support)
PCnet™-ISA II Full Duplex Single-Chip Ethernet Controller for ISA
PCnet™-32 Single-Chip 32-Bit Ethernet Controller
PCnet™-PCI Single-Chip Ethernet Controller (for PCI bus)
PCnet™-PCI II Full Duplex Single-Chip Ethernet Controller (for PCI bus)
PCnet™-SCSI Combination Ethernet and SCSI Controller for PCI Systems
4
Am79C983A
P R E L I M I N A R Y
CONNECTION DIAGRAM
PQFP
RDO–
RDO+
RCI–
RCI+
DVSS
DIR[1]
DIR[0]
SDATA[3]
DVSS
SDATA[2]
SDATA[1]
SDATA[0]
VDD
XENA
RST
DVSS
MCLK
DVSS
BSEL
CRS
COLX
PART
LINK
VDD
POL
1
2
3
4
5
6
7
8
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
DO–
DO+
DI–
DI+
CI–
CI+
DVSS
MACEN
COL
ACK
XMODE
REQ
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DAT
JAM
VDD
ECLK
FRAME
DVSS
PDRV
PDAT
PTAG
PCLK
DVSS
PENAO
PENAI
DVSS
MATCHI
MATCHO
PS
Am79C983
A
LD[7]
LD[6]
DVSS
LD[5]
LD[4]
DVSS
VDD
INT
RDY
DVSS
LD[3]
LD[2]
19879B-2
Am79C983A
5
P R E L I M I N A R Y
LOGIC SYMBOL
V
DD
DO±
DAT
REQ
ACK
DI±
CI±
AUI
COL
JAM
Expansion Bus
RDO±
RDI±
RCI±
ECLK
MACEN
FRAME
RAUI
PDO
PDI
PCI
LD[7:0]
BSEL
CRS
PAUI
(12)
COLX
PART
LED Interface
PDAT
PCLK
A
Am79C983
Packet
Report
Port
LINK
POL
PENAI
PENAO
PTAG
PDRV
D[7:0]
CS
MCLK
RST
XENA
XMODE
C/D
RD
Microprocessor
Interface
WR
RDY
INT
SDATA [3:0]
DIR [1:0]
Transceiver
Interface
DV
AV
SS
SS
19879B-3
LOGIC DIAGRAM
MAC
Engine
Expansion
Bus
Packet
Report Port
RAUI
Port
Transceiver
Interface
Repeater
State
Machine
AUI
Port
Microprocessor
Interface
PAUI
LED
PAUI
Port 11
Interface
Port 0
19879B-4
6
Am79C983A
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
K
C
Am79C983A
\W
ALTERNATE PACKAGING OPTION
\W = Trimmed and formed in a tray
OPTIONAL PROCESSING
Blank = Standard processing
TEMPERATURE RANGE
C = Commercial (0˚C to +70˚C)
PACKAGE TYPE
K = Plastic Quad Flat Pack (PQB 132)
DEVICE VARIATION
Blank = Security not included.
S = Security included. (See Appendix.)
DEVICE NUMBER/DESCRIPTION
Am79C983A
Integrated Multiport Repeater 2 (IMR2)
Valid Combinations
Valid Combinations
Am79C983A KC, KC\W
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local AMD sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.
Am79C983A
7
P R E L I M I N A R Y
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS.................................................................................................... 1
GENERAL DESCRIPTION................................................................................................................... 1
BLOCK DIAGRAM ............................................................................................................................... 3
RELATED AMD PRODUCTS............................................................................................................... 4
CONNECTION DIAGRAM ....................................................................................................................5
LOGIC SYMBOL...................................................................................................................................6
LOGIC DIAGRAM ................................................................................................................................ 6
ORDERING INFORMATION.................................................................................................................7
Standard Products .......................................................................................................................... 7
PIN DESIGNATIONS..........................................................................................................................12
PIN DESCRIPTION............................................................................................................................ 13
Pseudo AUI Pins........................................................................................................................... 13
RAUI Port Pins.............................................................................................................................. 13
AUI Pins........................................................................................................................................ 13
Expansion Bus Pins...................................................................................................................... 13
Packet Report Port........................................................................................................................ 14
Microprocessor Interface .............................................................................................................. 15
LED Interface................................................................................................................................ 15
Miscellaneous Pins ....................................................................................................................... 15
Transceiver Device Interface ........................................................................................................ 15
FUNCTIONAL DESCRIPTION............................................................................................................17
Overview....................................................................................................................................... 17
Basic Repeater Functions............................................................................................................. 17
Repeater Function ..................................................................................................................17
Signal Regeneration ...............................................................................................................17
Jabber Lockup Protection .......................................................................................................17
Collision Handling ...................................................................................................................17
Fragment Extension ...............................................................................................................17
Auto Partitioning/Reconnection ..............................................................................................17
Basic Management Functions....................................................................................................... 18
Repeater Management ...........................................................................................................18
RMON ....................................................................................................................................18
Packet Reports .......................................................................................................................18
Detailed Functions ........................................................................................................................ 22
Reset ......................................................................................................................................22
Hardware Reset............................................................................................................... 22
Software Reset ................................................................................................................ 22
Expansion Bus .......................................................................................................................22
Synchronous Mode Operation ......................................................................................... 23
Asynchronous Mode Operation ....................................................................................... 24
Packet Statistics .....................................................................................................................24
Packet Report Port........................................................................................................... 24
RAUI Port......................................................................................................................... 25
Error Packet Statistics ............................................................................................................26
Transceiver Interface .................................................................................................................... 26
PAUI Ports ..............................................................................................................................26
QuIET Device Control and Status Data Interface ...................................................................26
QuIET Device Control and Status Data Interface Operation ........................................... 26
Control and Status for Non-QuIET Transceivers ............................................................. 27
Visual Status Monitoring (LED) Support ....................................................................................... 27
Using AUI/RAUI for 10BASE-T Ports .....................................................................................28
Intrusion Protection....................................................................................................................... 28
Timer Values ..........................................................................................................................29
8
Am79C983A
P R E L I M I N A R Y
Microprocessor Interface .............................................................................................................. 29
Management Functions ..........................................................................................................29
Status Register ................................................................................................................ 30
Register Bank 0: Repeater Registers .............................................................................. 30
Source Address Match Register .............................................................................. 30
Total Octets.............................................................................................................. 31
Transmit Collisions................................................................................................... 31
Configuration Register ............................................................................................. 31
Repeater Status ....................................................................................................... 31
QuIET Device Transceiver ID Register.................................................................... 31
Repeater Device and Revision Register .................................................................. 32
Device Configuration................................................................................................ 32
Register Bank 1: Interrupts .............................................................................................. 32
Port Partition Status Change Interrupt ..................................................................... 32
Runts with Good FCS Interrupt................................................................................ 32
Link Status Change Interrupt ................................................................................... 32
Loopback Error Change Interrupt............................................................................. 33
Polarity Change Interrupt ......................................................................................... 33
SQE Test Error Change Interrupt............................................................................. 33
Source Address Changed Interrupt.......................................................................... 33
Intruder Interrupt ...................................................................................................... 33
Source Address Match Interrupt .............................................................................. 33
Data Rate Mismatch Interrupt .................................................................................. 34
Transceiver Interface Status .................................................................................... 34
Transceiver Interface Change Interrupt ................................................................... 34
Jabber Interrupt........................................................................................................ 34
Register Bank 2: Interrupt Control Registers ................................................................... 34
Partition Status Change Interrupt Enable................................................................. 34
Runts with Good FCS Interrupt Enable.................................................................... 34
Link Status Change Interrupt Enable ....................................................................... 35
Loopback Error Change Interrupt Enable ................................................................ 35
Polarity Change Interrupt Enable............................................................................. 35
SQE Test Error Change Interrupt Enable ................................................................ 35
Source Address Changed Interrupt Enable ............................................................. 35
Intruder Interrupt Enable .......................................................................................... 35
Multicast Address Pass Enable................................................................................ 36
Data Rate Mismatch Interrupt Enable...................................................................... 36
Last Source Address Compare Enable.................................................................... 36
Preferred Address Compare Enable........................................................................ 36
Transceiver Interface Changed Interrupt Enable ..................................................... 36
Jabber Interrupt Enable............................................................................................ 36
Register Bank 3: Port Control Registers.......................................................................... 37
Alternative Reconnection Algorithm Enable............................................................. 37
Link Test Enable ...................................................................................................... 37
Link Pulse Transmit Enable ..................................................................................... 37
Automatic Receiver Polarity Reversal Enable.......................................................... 37
SQE Mask Enable.................................................................................................... 37
Port Enable/Disable ................................................................................................. 37
Port Switching Control.............................................................................................. 37
Extended Distance Enable....................................................................................... 38
Automatic Last Source Address Intrusion Control ................................................... 38
Automatic Preferred Source Address Intrusion Control ........................................... 38
Last Source Address Lock Control........................................................................... 38
Register Bank 4: Port Status Registers ........................................................................... 39
Partitioning Status of Ports....................................................................................... 39
Link Test Status of Ports.......................................................................................... 39
Loopback Error Status ............................................................................................. 39
Receive Polarity Status............................................................................................ 39
Am79C983A
9
P R E L I M I N A R Y
SQE Test Status ...................................................................................................... 39
Register Bank 5: RMON Registers .................................................................................. 39
etherStatsOctets ...................................................................................................... 39
etherStatsPkts.......................................................................................................... 39
etherStatsBroadcastPkts.......................................................................................... 40
etherStatsMulticastPkts.............................................................................................40
etherStatsCRCAlignErrors ........................................................................................40
etherStatsUndersizePkts.......................................................................................... 40
etherStatsOversizePkts............................................................................................ 40
etherStatsFragments................................................................................................ 40
etherStatsJabbers.................................................................................................... 40
etherStatsCollisions ................................................................................................. 40
etherStats64Octets .................................................................................................. 40
etherStats65to127Octets ......................................................................................... 40
etherStats128to255Octets ....................................................................................... 40
etherStats256to511Octets ....................................................................................... 40
etherStats512to1023Octets ..................................................................................... 40
etherStats1024to1518Octets ................................................................................... 40
Activity...................................................................................................................... 40
Register Bank 7: Management Support........................................................................... 40
Device ID.................................................................................................................. 40
Sample Error Status................................................................................................. 40
Report Packet Size .................................................................................................. 41
STATS Control......................................................................................................... 41
Register Banks 16 through 30: Port Attribute Registers .................................................. 41
Readable Frames..................................................................................................... 42
Readable Octets ...................................................................................................... 42
Frame Check Sequence (FCS) Errors..................................................................... 42
Alignment Errors ...................................................................................................... 42
Frames Too Long..................................................................................................... 42
Short Events............................................................................................................. 43
Runts........................................................................................................................ 43
Collisions.................................................................................................................. 43
Late Events .............................................................................................................. 43
Very Long Events..................................................................................................... 43
Data Rate Mismatches............................................................................................. 43
Auto Partitions.......................................................................................................... 44
Source Address Changes ........................................................................................ 44
Readable Broadcast Frames ................................................................................... 44
Last Source Address................................................................................................ 44
Readable Multicast Frames ..................................................................................... 44
Preferred Source Address........................................................................................ 44
SYSTEM APPLICATIONS..................................................................................................................45
IMR2 to QuIET Connection........................................................................................................... 45
Other Media .................................................................................................................................. 45
MAC Interface............................................................................................................................... 45
RAUI Port ...............................................................................................................................45
PR Port Configuration ............................................................................................................45
Port Switching............................................................................................................................... 48
ABSOLUTE MAXIMUM RATINGS .....................................................................................................50
OPERATING RANGES................................................................................................................. 50
DC CHARACTERISTICS over operating ranges unless otherwise specified............................... 50
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified ............... 51
KEY TO SWITCHING WAVEFORMS................................................................................................ 54
SWITCHING WAVEFORMS.............................................................................................................. 54
Master Clock (MCLK) Timing........................................................................................................ 54
10
Am79C983A
P R E L I M I N A R Y
Expansion Bus Asynchronous Clock (ECLK) Timing ...................................................................54
Expansion Bus Input Timing - Synchronous Mode....................................................................... 55
Expansion Bus Output Timing - Synchronous Mode ....................................................................55
Expansion Port Collision Timing - Synchronous Mode .................................................................56
Packet Report Port Timing............................................................................................................ 56
Expansion Port Input Timing - Asynchronous Mode..................................................................... 56
Expansion Port Output Timing - Asynchronous Mode.................................................................. 57
PAUI PDO Transmit...................................................................................................................... 57
PAUI PCI Receive......................................................................................................................... 57
PAUI Receive................................................................................................................................ 58
(R)AUI Timing ................................................................................................................................58
(R)AUI Receive .............................................................................................................................58
Microprocessor Bus Interface Timing ...........................................................................................59
PHYSICAL DIMENSIONS.................................................................................................................. 60
Am79C983A
11
P R E L I M I N A R Y
PIN DESIGNATIONS
Listed by Pin Number
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
AVSS
1
DO-
DO+
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
WR
RD
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
LD[2]
LD[3]
DVSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
2
RDI+
RDI-
3
DI-
CS
4
DI+
C/D
LD[4]
LD[5]
DVSS
VDD
5
CI-
D[7]
PDI[0]
PCI[0]
PDI[1]
PCI[1]
PDI[2]
PCI[2]
PDI[3]
PCI[3]
PDI[4]
PCI[4]
VDD
6
CI+
D[6]
7
DVSS
MACEN
COL
D[5]
LD[6]
LD[7]
POL
8
D[4]
9
DVSS
D[3]
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
ACK
VDD
XMODE
REQ
D[2]
LINK
D[1]
PART
COLX
CRS
DAT
D[0]
JAM
VDD
VDD
PDO[11]
PDO[10]
PDO[9]
PDO[8]
DVSS
PDO[7]
PDO[6]
VDD
BSEL
DVSS
ECLK
FRAME
DVSS
PDRV
PDAT
PTAG
PCLK
DVSS
PENAO
PENAI
DVSS
MATCHI
MATCHO
PS
PDI[5]
PCI[5]
AVSS
MCLK
DVSS
RST
PDI[6]
PCI[6]
PDI[7]
PCI[7]
PDI[8]
PCI[8]
AVSS
XENA
VDD
SDATA[0]
SDATA[1]
SDATA[2]
DVSS
PDO[5]
PDO[4]
DVSS
PDO[3]
PDO[2]
VDD
SDATA[3]
DIR[0]
DIR[1]
DVSS
PDI[9]
PCI[9]
AVSS
PDO[1]
PDO[0]
LD[0]
LD[1]
NC
PDI[10]
PCI[10]
PDI[11]
PCI[11]
VDD
VDD
RCI+
INT
RCI-
RDY
RDO+
RDO-
DVSS
12
Am79C983A
P R E L I M I N A R Y
CI+, CI-
PIN DESCRIPTION
Pseudo AUI Pins
AUI Collision Input
Input
PDO
AUI port collision differential receiver.
0-11
Pseudo AUI Data Output
Output/High Impedance
Expansion Bus Pins
PDO is a single-ended output driver. PDO can be
placed into a high impedance state, allowing multiple
IMR2 devices to connect to a single QuIET device (port
switching). The output data is Manchester encoded.
DAT
Data
Input/Output/High Impedance
The IMR2 device drives the DAT line with NRZ data
when both REQ and ACK pins are asserted. DAT is an
input if only the ACK signal is asserted. If REQ and ACK
are not asserted, DAT enters a high impedance state.
During collision when JAM is HIGH, DAT is used to sig-
nal a multiport (DAT=0) or single port (DAT=1) condition.
PDI
0-11
Pseudo AUI Receive Data Input
Input
The input data is Manchester encoded.
PCI
0-11
JAM
Jam
Pseudo AUI Collision Input
Input
Input/Output/High Impedance
PAUI port collision data receiver. A 10-MHz square wave
indicates a collision has been detected on that port.
This pin is an output if the device is the only active
IMR2 device. An IMR2 device is defined as active when
it has one or more ports receiving or colliding, is in the
state where it is still transmitting data from the internal
FIFO, or is extending a packet to the minimum 96-bit
times. If active, the IMR2 device drives the JAM pin
HIGH to indicate that it is in a Collision state when both
REQ and ACK pins are asserted. JAM is an input if only
the ACK signal is asserted. If REQ and ACK are not as-
serted, JAM enters a high impedance state.
RAUI Port Pins
RDO+, RDO-
Reversible AUI Data Output
Output
RDO is a differential, Manchester output driver.
RDI+, RDI-
Reversible AUI Data Input
Input
REQ
Request
RDI is a differential, Manchester receiver.
Output, Active LOW
RCI+, RCI-
Reversible AUI Collision Input
Input/Output
This pin is driven LOW when the IMR2 device senses
activity. An IMR2 device is defined as ACTIVE when it
has one or more ports receiving or colliding, is in the
state where it is still transmitting data from the internal
FIFO, or is extending a packet to the minimum 96-bit
times. The assertion of this signal signifies that the
IMR2 device requires the DAT and JAM lines to transfer
repeated data and collision status information to other
IMR2 devices.
RCI is a differential I/O. As an input, RCI receives a col-
lision indication. As an output, RCI generates a 10-MHz
square wave when a collision is sensed.
PS
Output
This pin is reserved for factory use.
AUI Pins
ACK
Acknowledge
Input, Active LOW
DO+, DO-
AUI Data Output
Output
When this signal is asserted by an external arbiter, it
signals to the requesting IMR2 device that it may drive
the DAT and JAM pins. It signals to other IMR2 devices
the presence of valid collision status on the JAM line
and valid data on the DAT line.
AUI port differential driver. Manchester encoded data.
DI+, DI-
AUI Data Input
Input
AUI port differential receiver. Manchester encoded data.
Am79C983A
13
P R E L I M I N A R Y
COL
Collision
Input, Active LOW
XENA
Port Enable
Input
When this pin is asserted by an external arbiter, it sig-
nifies that more than one IMR2 device is active and that
each IMR2 device should generate the Collision Jam
Sequence independently.
XENA sets the default mode of the ports. It is used
when RST transitions from LOW to HIGH.
XENA
Default
All ports are enabled.
1
0
ECLK
Bus Clock
Input/Output
All ports are disabled. The output drivers
are in a high impedance state.
Data transitions on the expansion bus on DAT are syn-
chronized to this clock. ECLK is a 10-MHz output clock
when DAT is transmitting and a 10-MHz input clock
when DAT is receiving. ECLK is only used when the ex-
pansion bus is operated in the asynchronous mode.
ECLK should be terminated to ground with a 1 kΩ resis-
tor. ECLK should be ignored in the synchronous mode.
Note: XENA only controls the default state. Once
reset is completed, the enabling and disabling of ports
is under software control. It is recommended that
XENA be tied either HIGH or LOW, depending on the
desired default state.
Packet Report Port
PDAT
MACEN
MAC Enable
Input, Active LOW
Packet Report
Output, High Impedance
PDAT outputs the beginning portion of a packet fol-
lowed by packet status information. The size of the be-
ginning portion is user programmable. If a second
packet arrives before PDAT finishes transmitting status
information, the second packet and corresponding sta-
tus information are not transmitted over PDAT. The
packet is aborted on collision.
When this pin is asserted, data on the expansion bus is
included in MIB statistics. This is typically used when a
MAC is driving the expansion bus.
MATCHO
This pin should be tied to +5 V through a 1 kΩ
±10% resistor.
PENAI
MATCHI
Packet Report Enable Input
Input, Active LOW
This pin should be tied to +5 V through a 1 kΩ
±10% resistor.
PENAI senses when another device is transmitting
over PDAT.
FRAME
Packet Framing Signal
Input/Output, Active LOW
PENAO
Packet Report Enable Output
Output, Active LOW, Open Drain
FRAME defines the beginning and end of a packet.
FRAME indicates valid data on the DAT pin when the ex-
pansion bus is in the asynchronous mode. FRAME is an
output on the IMR2 device when it is transmitting over the
expansion bus. It is an input on all other IMR2 devices.
PENAO is TRUE when the IMR2 device is transmitting
data over PDAT. If a second packet arrives before PDAT
is finished transmitting status information, PENAO re-
mains active for the second packet.
XMODE
Expansion Bus Mode
Input
PDRV
Packet Drive
Output, Active LOW
XMODE determines the mode of the expansion bus.
XMODE should not be changed after RST. Although
changing XMODE after RST will change the expansion
bus mode, the operation is unpredictable. Therefore, it
is recommended that XMODE be tied either HIGH or
LOW, depending on the desired expansion bus mode.
PDRV is TRUE when the IMR2 device is transmitting
data over PDAT. If a second packet arrives before PDAT
is finished transmitting status, PDRV goes FALSE after
the status is transmitted.
PCLK
Packet Report Clock
Output, High Impedance
XMODE
Mode
1
0
Asynchronous
Synchronous (IMR/IMR+)
PCLK is a 10-MHz clock. PDAT transitions are synchro-
nized to PCLK.
14
Am79C983A
P R E L I M I N A R Y
Output
PTAG
Packet Tag
Output, HIGH Impedance, Active LOW
When BSEL is LOW, LD[7:0] is transmitting the status
of the first eight PAUI ports (ports P through P ).When
7
0
PTAG indicates when the status frame is being trans-
mitted over PDAT. It is asserted when the status frame
is transmitted.
BSEL is HIGH, LD[7:0] is transmitting the status of the
rest of the PAUI ports (ports P through P ), the AUI
11
8
port, the RAUI port, and the expansion bus.
Microprocessor Interface
CRS
Carrier Sense Strobe
Output
D[7:0]
Microprocessor Data
Input/Output
When CRS is HIGH, LD [7:0] has carrier sense status.
These pins are inputs when either CS or WR are LOW.
They are outputs when CS and RD are LOW. Other-
wise, these pins are high impedance.
COLX
Collision Status
Output
When COLX is HIGH, LD [7:0] has collision status.
CS
Chip Select
Input, Active LOW
PART
Partitioning Status
Output
This pin enables the IMR2 device to read from or write
to the microprocessor data bus.
When PART is HIGH, LD [7:0] has partitioning status.
C/D
Control/Data
Input
LINK
Link Status
Output
This pin is used to select either a control register or a
data register in the IMR2 device and is normally con-
nected to the least significant bit of the address bus.
When LINK is HIGH, LD [7:0] has link status.
POL
Polarity Status
Output
RD
Read Strobe
Input, Active LOW
When POL is HIGH, LD [7:0] has polarity status.
Miscellaneous Pins
Initiates read operation.
RST
Reset
Input
WR
Write Strobe
Input, Active LOW
When RST is LOW, the IMR2 device resets to its
default state.
Initiates write operation.
RDY
Ready
MCLK
Master Clock
Input
Output, Active HIGH, Open Drain
RDY is driven LOW at the start of every READ or
WRITE cycle. RDY is released when the IMR2 device
is ready to complete the transaction.
MCLK is a 20-MHz clock input.
Transceiver Device Interface
INT
Interrupt
Output, Active LOW, Open Drain
SDATA [3:0]
Serial Data
Input/Output
The Interrupt pin is driven LOW when any of the un-
masked (enabled) interrupts occur.
SDATA carries command and status data between the
IMR2 device and the QuIET device (or other
connected transceiver).
LED Interface
Pin
Transceiver Ports
PAUI [3:0]
LD[7:0]
LED Drivers
Output
SDATA [0]
SDATA [1]
SDATA [2]
SDATA [3]
PAUI [7:4]
PAUI [11:8]
LD is the status output and is transmitted as 2 bytes.
The byte number (high or low) is determined by BSEL.
Arbitrary ports
BSEL
Byte Select
Am79C983A
15
P R E L I M I N A R Y
AVSS
DIR
Direction
Output
Analog Ground
Ground Pin
DIR sets the direction of data on SDATA[3:0] The set-
tings are as follows:
These pins provide the ground reference for the analog
portions of the IMR2 circuitry. These pins should be de-
coupled and kept separate from the digital ground plane.
DIR[1:0]
Function
Transceiver (QuIET device) drives SDATA with
status and device ID.
DVss
Digital Ground
Ground Pin
00
01
10
11
SDATA is a high impedance output.
SDATA is a high impedance output.
IMR2 device drives SDATA with commands.
These pins provide the ground reference for the digital
portions of the IMR2 circuitry. These pins should be de-
coupled and kept separate from the analog power plane.
VDD
Power Pin
These pins supply +5 V power.
16
Am79C983A
P R E L I M I N A R Y
Jabber Lockup Protection
FUNCTIONAL DESCRIPTION
Overview
The IMR2 chip implements a built-in jabber protection
scheme to ensure that the network is not disabled due
to transmission of excessively long data packets. This
protection scheme will automatically interrupt the
transmitter circuits of the IMR2 device for 96-bit times,
if the IMR2 device has been transmitting continuously
for more than 65,536 bit times. This is referred to as
MAU Jabber Lockup Protection (MJLP). The MJLP
status for the IMR2 chip can be read from the
Repeater Status Register.
The Am79C983A Integrated Multiport Repeater 2 de-
vice provides a system-level solution to designing IEEE
802.3 managed repeaters. It includes 12 pseudo AUI
(PAUI) ports for single-ended connections to external
transceivers. The IMR2 device interfaces directly with
AMD's Am79C988A Quad Integrated Ethernet Trans-
ceiver (QuIET) device for 10BASE-T implementations.
The PAUI ports can be turned off individually to enable
port switching applications. In addition, the IMR2 de-
vice has a standard AUI port and a reversible AUI
(RAUI) port for a direct connection to a MAC.
Collision Handling
The IMR2 chip will detect and respond to collision con-
ditions as specified in the IEEE 802.3 specification. A
multiple IMR2 device repeater implementation also
complies with the specification because of the inter-
IMR2 chip status communication provided by the ex-
pansion port. Specifically, a repeater based on one or
more IMR2 devices will handle correctly the transmit
collision and one-port-left collision conditions as spec-
ified in Section 9 of the IEEE 802.3 specification.
The IMR2 device provides a Hardware Implemented
Management Information Base (HIMIB) which contains
all of the necessary counters, attributes, actions, and
notifications specified by Section 19 of the IEEE 802.3
standard. Support for an RMON MIB, as specified by
the Internet Engineering Task Force (IETF) RFC 1757,
is also provided. Direct support is from an RMON Reg-
ister Bank. Additional support is provided by the Packet
Report Port, which supplies packet information that can
be used in conjunction with a microprocessor to derive
various RMON MIB attributes.
Fragment Extension
If the total packet length received by the IMR2 device is
less than 96 bits, including preamble, the IMR2 chip will
extend the repeated packet length to 96 bits by ap-
pending a Jam sequence to the original fragment. Note
that in a few cases, it is possible for the IMR2 device to
generate a sequence 97 bits in length when the expan-
sion bus is operated in the asynchronous mode.
Basic Repeater Functions
The IMR2 repeater functions are summarized below.
An overview of IMR2 management functions is
presented under Basic Management Functions.
Repeater Function
Auto Partitioning/Reconnection
If any single network port of a repeater system senses
the start of a valid packet on its receive lines, the IMR2
device will retransmit the received data to all other en-
abled network ports unless a collision is detected. The
repeated data will also be presented on the DAT line of
the expansion bus to facilitate designs utilizing multiple
IMR2 devices. The IMR2 device fully complies with
Section 9.5.1 of the IEEE 802.3 specifications.
Any of the IMR2 ports can be partitioned under exces-
sive duration or frequency of collision conditions. Once
a port is partitioned, the IMR2 device will continue to
transmit data packets to a partitioned port, but will not
respond (as a repeater) to activity on the partitioned
port’s receiver. The IMR2 chip will monitor the port and
reconnect it once certain criteria indicating port “well-
ness” are met. The criteria for reconnection are speci-
fied by the IEEE 802.3 standard. In addition to the
standard reconnection algorithm, the IMR2 device im-
plements an alternative reconnection algorithm which
provides a more robust partitioning function. Each port
is partitioned and/ or reconnected separately and inde-
pendently of other network ports.
Signal Regeneration
When retransmitting a packet, the IMR2 device en-
sures that the outgoing packet complies with the IEEE
802.3 specification in terms of preamble structure.
Data packets repeated by the IMR2 device will contain
a minimum of 56 preamble bits before the Start of
Frame Delimiter.
Either one of the following conditions occurring on any
enabled IMR2 device network port will cause the port
to partition:
The IMR2 device, by virtue of its internal Phase Lock
Loop and Manchester Encoder/Decoder, will ensure
correct regeneration of the repeated signal at its PAUI
and AUI outputs. If the outputs of the IMR2 device are
connected to QuIET device transceivers, the 10BASE-T
outputs of the QuIET devices will meet the IEEE 802.3
signal symmetry requirements. If other types of trans-
ceivers are used, the signal characteristics will depend,
in part, on the transceiver.
a. An SQE signal active for more than 2048 bit times.
b. A collision condition occurs during each of 32 con-
secutive attempts to transmit to that port.
Once a network port is partitioned, the IMR2 device will
reconnect that port if the following is met:
Am79C983A
17
P R E L I M I N A R Y
a. Standard reconnection algorithm—A data packet
longer than 512-bit times (nominal) is transmitted or re-
ceived by the partitioned port without a collision.
P4:0 represent the Register Bank or Port Number, or-
ganized as follows:
P = P P P P P
0
4
3
2
1
b. Alternate reconnection algorithm—A data packet
longer than 512-bit times (nominal) is transmitted by
the partitioned port without a collision.
P
0
1
2
3
4
5
7
Port/Register Bank
Repeater Registers
Interrupt Registers
Interrupt Control Registers
Port Control Registers
Port Status Registers
RMON Registers
Basic Management Functions
Repeater Management
The IMR2 management functions are a super-set of
the those provided by the AMD’s IMR+/HIMIB device
chipset. The IMR2 device contains the complete set of
repeater and port functions as defined in ANSI/IEEE
802.3, Repeater Management Standard, (Section 19).
All mandatory and optional capabilities are supported.
These include the Basic Control, Performance Monitor-
ing, and Address Tracking packages. Additionally,
Node Address Mapping, MAU Management specific
functions, and intrusion protection functions are in-
cluded. Support is also provided for the RMON MIB
RFC 1757.
Packet Report Registers
Port Attributes
16- 30
The register to be accessed for reading or writing is
specified by writing the following control byte to the
C register:
C Port Write
1
1
1
R4
R3
R2
R1
R0
LSB
MSB
R = R R R R R
0
4
3
2
1
All information is stored in registers which can be ac-
cessed through the Microprocessor Interface (Node
Processor Port). The register location is defined by a
register bank and an address within that register bank.
Address and data of the registers are multiplexed using
the C/D pin. The register address is selected by writing
to the Node Processor Port with C/D HIGH. The regis-
ter data is selected by writing or reading to the Node
Processor Port with C/D LOW.
Figure 1 shows the Management Register Map, and
Table 1 shows register banks and register assignments
within the register banks.
RMON
Remote monitoring (RMON) functions are designed to
give the management system the capability to remotely
monitor the hub for diagnostic purposes. The rules for
RMON are described in the RMON MIB (as of this
writing IETF RFC1578).
Many of the registers are larger than 1 byte. For these
registers, consecutive accesses to register data (equal
to the number of bytes in the register) are required.The
order is LSByte to MSByte. For a write operation, if the
address changes before all the bytes are written, the
register is not changed to the new value.
The IMR2 device provides direct support for both the
statistics and history object groups. Indirect support is
provided for the alarm, host, hostTopN, event, and ma-
trix groups. Direct support is provided via the RMON
register set and relevant attribute registers. Indirect
support is provided through the Packet Report Port.
The Status Register is accessed by reading the Node
Processor Port with the C/D pin HIGH. This reduces
the number of operations necessary to access the
Status Register.
Packet Reports
The IMR2 device generates status information on
every packet that it repeats. The data is transmitted
over the Packet Report Port. The data format consists
of the beginning of the packet followed by a packet tag
and statistical data on the packet.
All bit fields are ordered such that the left most bit is the
most significant bit. Unused register banks, ports and
register numbers are reserved and should not be ac-
cessed as this may cause device malfunction. When
specifying the register bank or port number, the follow-
ing format is used:
Port No., New
Preamble DA SA T/L Packet Data
Var. Length Tag &
Status
FCS
C Port Write
0
0
0
P4
P3
P2
P1
P0
LSB
MSB
18
Am79C983A
P R E L I M I N A R Y
C/D = 1
8
5
Bank Select
Command (C) Port
0
0 0 P4 P3 P2 P1 P0
8
Status
Register
8
4
5
7
16 * * 27, 28, 29, 30
1
2
3
0
PS RMN MSR P0 * * P11, A, AR, EP
IR
ICR PCR
RR
Register Select
0
1
1 1 R4 R3 R2 R1 R0
1
2
3
4
5
6
To
Node
5
7
Processor
Port
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A - AUI Port
AR - RAUI Port
EP - Expansion Port
ICR - Interrupt Control Registers
IR - Interrupt Registers
MSR - Management Support Registers
PCR - Port Control Registers
PS - Port Status Registers
PXX - PAUI Port
RMN - RMON Registers
RR - Repeater Registers
23
24
25
26
27
28
29
30
31
C/D = 0
Data (D) Port
To
Node
Processor
Port
19879B-5
Figure 1. Management Register Map
Am79C983A
19
P R E L I M I N A R Y
Table 1. Management Registers
RegisterBank 2
Reg.
No.
RegisterBank0
Repeater Registers
RegisterBank1
Interrupt Registers
Interrupt Control
Registers
RegisterBank3
Port Control Registers
Port Partition Status
Change Interrupt
Partition Change Interrupt
Enable
Alternative Partition
Algorithm Enable
0
1
2
3
4
5
Runts with Good FCS
Interrupt
Runts with Good FCS
Interrupt Enable
Link Status Change
Interrupt
Link Status Change
Interrupt Enable
Link Test Enable
Loopback Error Change
Interrupt
Loopback Error Change
Interrupt Enable
Link Pulse Transmit
Enable
Polarity Change Interrupt
Enable
Automatic Receiver
Polarity Reversal Enable
Polarity Change Interrupt
SQE Test Error Change
Interrupt
SQE Test Error Change
Interrupt Enable
SQE Mask Enable
Source Address Changed Source Address Changed
6
7
8
Port Enable/Disable
Port Mobility Control
Interrupt
Interrupt Enable
Intruder Interrupt
Intruder Interrupt Enable
Source Address Match
Interrupt
Extended Distance
Enable
Multicast Address Pass
Enable
Last Source Address
Automatic Intrusion Control
9
Source Address Match
Register
Data Rate Mismatch
Interrupt
Data Rate Mismatch
Interrupt Enable
Pref. Source Address
Automatic Intrusion Control
10
11
12
Last Source Address Lock
Enable
Last Source Address
Compare Enable
Total Octets
13
14
Transmit Collisions
Preferred Address
Compare Enable
15
16
Transceiver Interface Status
Transceiver Interface
Changed Interrupt
Transceiver Interface
Changed Interrupt Enable
Configuration Register
17
18
19
20
21
22
23
24
25
26
27
Jabber Interrupt
Jabber Interrupt Enable
Repeater Status
QuIET Device ID Register
Repeater Device and
Revision Register
28
29
30
31
Device Configuration
20
Am79C983A
P R E L I M I N A R Y
Table 1. Management Registers (Continued)
Register Bank 7
RegisterBank4
Port Status Registers
RegisterBank5
RMON Registers
Management Support
Registers
Register Bank 16-30
Port Attribute Registers
Reg. No.
0
1
Partitioning Status of Ports etherStatsOctets
etherStatsPkts
Device ID
Readable Frames
Readable Octets
Frame Check Sequence
Errors
2
Link Test Status of Ports
etherStatsBroadcastPkts
etherStatsMulticastPkts
Sample Error Status
Report Packet Size
3
4
Loopback Error Status
Receive Polarity Status
SQE Test Status
Alignment Errors
Frames Too Long
Short Events
etherStatsCRCAlignErrors Statistics Control
etherStatsUndersizePkts
etherStatsOversizePkts
etherStatsFragments
5
6
Runts
7
Collisions
8
etherStatsJabbers
Late Events
9
etherStatsCollisions
Very Long Events
Data Rate Mismatches
Auto Partition
10
11
etherStats64Octets
etherStats65to127Octets
etherStats128to255-
Octets
Source Address
Changes
12
13
14
15
16
etherStats256to511-
Octets
Readable Broadcast
Frames
etherStats512to1023-
Octets
Last Source Address
etherStats1024to1518-
Octets
Readable Multicast Frames
Preferred Source
Address
Activity
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Am79C983A
21
P R E L I M I N A R Y
processor interface is not reset and the ability to access
Detailed Functions
4 and 6 byte attribute registers is maintained. Bit M af-
fects only the management and intrusion protection
functions of the IMR2 device.
This section describes the detailed functional behavior
of the IMR2 device. Where necessary, the behavior is
defined in terms of state machines. Note that this is a
conceptual definition and the actual implementation
may be different.
Bit R causes the IMR2 device to go into the default
state. As with hardware reset, all analog outputs are
placed in their idle state, all bidirectional signals are not
driven, all active-HIGH signals are driven LOW, and all
active-LOW signals are driven HIGH. The only excep-
tion is POL, which defaults to HIGH on reset. Registers
are also set to their default state.
Reset
Hardware Reset
The IMR2 device enters the reset state when the RST
pin is driven LOW. The reset pin should be held LOW
for a minimum of 150 µs after power-up or 4 µs other-
wise. This allows the IMR2 device to reset the internal
logic. During reset, the registers are set to their default
values. The output signals are placed in their inactive
state. That is, all analog outputs are placed in their idle
state, all bidirectional signals are not driven, all active-
HIGH signals are driven LOW, and all active-LOW sig-
nals are driven HIGH.The only exception is POL, which
defaults to HIGH on reset. In a multiple IMR2 device re-
peater, the reset signal should be synchronized to
MCLK when the expansion bus is operated in the syn-
chronous mode.
Setting Bit R also allows write access to the MIB regis-
ters and some other read-only registers. These regis-
ters are theTotal Octets Register, theTransmit Collision
Register, the entire RMON Register Bank, and the Port
Attribute Register Banks. Note that the Last Source Ad-
dress Register and the Preferred Source Address Reg-
ister can also be written into when bit R is not set.
Setting bit R will not affect any bit of the Device Config-
uration Register. Thus, the IMR2 device does not auto-
matically exit software reset. Software reset must be
exited by setting bit R to zero.
The function of bit M is a subset of the function of bit R.
It affects the intrusion protection and MIB registers. Set-
ting bit M causes the intrusion protection registers to go
into the default state. As with bit R, the MIB registers can
be written into. 2 lists the default state of the registers. If
the M column has an M, the corresponding register is set
to its default state when bit M is set.
Reset does not affect the RMON registers (Register Bank
5) or the Port Attribute Registers (Register Banks 16-30).
These registers will power up at a random value. They
can be preset while the IMR2 is in software reset or while
the port is disabled via the microprocessor interface.
The mode of the expansion bus and the default state of
the ports are set by XMODE and XENA during RST.
XMODE sets the expansion bus mode and XENA sets
the port state. Note that XENA only controls the default
state. Once reset is completed, the enabling and dis-
abling of the ports is under software control.The settings
are as follow:
Expansion Bus
The expansion bus has two modes of operation: the
synchronous (IMR/IMR+ compatible) mode and the
asynchronous mode. The modes are differentiated by
the expansion bus clock. In the synchronous mode, the
IMR2 devices (and any IMR/IMR+ devices) are all
clocked by a single 20-MHz clock. The IMR2 device
uses MCLK as the clock source.
The expansion bus is in the asynchronous
(IMR2) mode.
1
XMODE
In the asynchronous mode, IMR2 devices can be
clocked (MCLK) by different sources. The single IMR2
device transmitting over the expansion bus provides
the clock source for data. The clock pin in this mode is
ECLK. ECLK clocks the data. All other expansion bus
signals are asynchronous. The mode of expansion bus
operation is selected during reset by XMODE.
The expansion bus is in the synchronous
(IMR/IMR+) mode.
0
1
0
All ports are enabled.
All PAUI ports are disabled. The output
drivers are placed in a high impedance
state.
XENA
Software Reset
The expansion bus can be configured for connection to
a MAC. The pin MACEN selects the MAC mode. When
MACEN is TRUE (LOW), the statistics on the data re-
ceived by DAT are recorded in the management regis-
ters. The expansion bus is considered another port in
the same sense as the PAUIs, the AUI, and the RAUI.
The IMR2 device supports software reset with two bits
on the Device Configuration Register: Repeater Reset
(R - bit 7 on the register) and Management Reset (M - bit
6 on the register). Bit R resets the registers, repeater,
and MAC engine. Setting Bit R is the functional equiva-
lent of hardware reset, with the exception that the micro-
22
Am79C983A
P R E L I M I N A R Y
Register
Synchronous Mode Operation
Default
M
While operating in the synchronous mode, the expan-
sion bus pins are Data (DAT), JAM, Request (REQ),
Acknowledge (ACK), and Collision (COL). DAT and
JAM are bidirectional signals. REQ is an output. ACK
and COL are inputs.
Source Address Changed Interrupt Masked M,R
Enable
Intruder Interrupt Enable
Masked M, R
Disabled M, R
Multicast Address Pass Enable
Data Rate Mismatch Interrupt Masked
Enable
R
Table 2. Register Reset Default States
Source Address Compare Enable Disabled M, R
Register
Default
M
Preferred
Enable
Address
Compare Disabled M, R
Configuration
M, R
Transceiver Interface Changed Masked
Interrupt Enable
R
Enable Interrupts
Source Address Match
Interrupt
Masked
Masked
Jabber Interrupt Enable
Alternative Partition
Link Test Enable
Masked
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
XENA
R
R
R
R
R
R
R
R
R
R
Repeater Status
MJLP
No Error
R
Device Configuration
Repeater Reset
Link Pulse Enable
Reverse Polarity Enable
SQE Mask Enable
Port Enable
Normal
Normal
Normal
Normal
Normal
None
Management Reset
RAUI Direction
Loopback Test Mode
Transceiver Loopback
Partition Change Interrupt
Runts with Good FCS Interrupt
Link Change Interrupt
Loopback Change Interrupt
Polarity Changed Interrupt
SQE Test No Change Interrupt
Port Mobility Control
Extended Distance Control Enable Disabled
R
Source Address Automatic Intru- Disabled
sion Enable
None
M, R
R
Preferred Address Automatic Intru- Disabled
sion Enable
R
None
None
R
Last Source Address Lock Enable Disabled M, R
None
R
Partition Status
Link Status
Connect
Link Fail
No Error
Positive
No Error
Four
R
None
R
R
Source Address Changed Interrupt None
M, R
M, R
M, R
R
Loopback Status
Polarity Status
SQE Test Status
Sample Counter Que
Packet Report Packet Size
Statistics Control
Stat Tag
R
Intruder Interrupt
None
None
R
Source Address Match Interrupt
Data Rate Mismatch Interrupt
R
No
Mismatch
M, R
M, R
07FF‘
Transceiver Interface Status
No Trans. R
Transceiver Interface Change None
Interrupt
R
Disable
Disable
M, R
M, R
Jabber Interrupt
No Jabber R
FCS Tag
Partition Change Interrupt Enable Masked
R
The IMR2 device expansion scheme allows the use of
multiple IMR2 devices in a single-board repeater or in
a modular multiport repeater with a backplane architec-
ture. Data sent on the DAT line is in NRZ format and is
synchronized to MCLK. Another bidirectional pin, JAM,
is used to communicate internal IMR2 device status
from the single active IMR2 device to other IMR2 de-
vices in the system. This signal indicates whether the
active IMR2 device is in a collision state.
Runts with Good FCS Interrupt Masked M,R
Enable
Link Changed Interrupt Enable
Masked
R
R
Loopback
Enable
Changed
Interrupt Masked
Polarity Changed Interrupts Enable Masked
R
R
SQE Test Changed Interrupt Masked
Enable
Arbitration for control of the bussed signals, DAT and
JAM, is provided by external circuitry. One output pin
(REQ) and two input pins (ACK and COL) are used as
arbitration signals. The IMR2 device asserts REQ to
Am79C983A
23
P R E L I M I N A R Y
indicate that it is active and is ready to drive the DAT
skewed in frequency. To help the IMR2 devices accom-
modate the frequency differences, the expansion bus
transmits a framing signal (FRAME). See Figure 2.
and JAM signals. The external arbiter asserts ACK if
one and only one IMR2 device has REQ asserted.This
allows the corresponding IMR2 device to drive the DAT
line with data to be repeated by all other IMR2 devices.
If there is more than one IMR2 device asserting REQ,
the external arbiter should assert COL, indicating mul-
tiple IMR2 devices are active.
Because JAM is an asynchronous signal, there is no
defined relationship between JAM and ECLK.
ECLK
FRAME
DAT
The active IMR2 device drives the JAM line HIGH in
order to signal other IMR2 devices that it has detected
a collision across one or more of its ports and is gener-
ating a Jam Sequence.The DAT line is used during sin-
gle IMR2 device collision (JAM asserted) to signal
single-port collision (DAT HIGH) or multiport collision
(DAT LOW). Other IMR2 devices synchronize their in-
ternal Collision Jam Sequence generators using JAM
and DAT pins as inputs.
JAM
ACK
19879B-6
Figure 2. Asynchronous Mode Data Transfer
If more than one IMR2 device is active (multiple REQs
asserted), the external arbiter should assert the COL
line to signal this condition. In this case, all IMR2 de-
vices in the repeater are forced into the multiport colli-
sion state and will generate Jam sequence
independently while this condition lasts. As ports on
separate IMR2 devices back off, the last IMR2 device
with an active port regains control of the DAT and JAM
signals and all other IMR2 devices will continue gener-
ating Jam sequence while the JAM signal is asserted.
Packet Statistics
Packet Report Port
For each packet, the IMR2 device can compile a set of
data about that packet.This data, which will now be re-
ferred to as the report packet, allows the system to de-
rive objects in the Host, HostTopN, and Matrix groups
of the RMON MIB (RFC 1757). The Report Packet is
delivered by the Packet Report Port (PR).
In a typical single-board application, three IMR2 de-
vices can be connected together without the use of ex-
ternal transceivers. The total number of IMR2 devices
that can be used in a more complex architecture will
depend on the drive capability, system timing limita-
tions, and system design.
The PR port transmits a portion of the packet along
with data about that packet to a MAC.The format of the
report packet is shown in 3. Sending only a portion of
the packet is referred to as packet compression.
The degree to which the original packet is compressed
is set by the Report Packet Size Register.The size is in
bytes. If the register is set to 14 or less, the size of the
packet passed is 14 bytes. If the register is set to 1536
or greater, the entire packet is passed. If the packet
size is equal to or less than the value set in the Report
Packet Size Register, the entire packet is passed.
The external arbiter is required to generate two signals
(ACK and COL). The logic function for these signals in
a three IMR2 device Repeater Unit is as follows:
ACK = REQ1 & !REQ2 & !REQ3 + !REQ1 & REQ2 &
!REQ3 + !REQ1 & !REQ2 & REQ3
If the destination address of the packet is the same as
the address of the MAC connected to the PR Port, then
it is desirable to have the entire packet transmitted to
the MAC. Therefore, packet compression is automati-
cally disabled when the destination address of the
packet is a valid address for the expansion bus. How-
ever, the report tag is appended to the end of the
packet. Note that the entire packet is also sent if the
destination address is a broadcast address.
COL = !(ACK + !REQ1 & !REQ2 & !REQ3)
Asynchronous Mode Operation
The operation of the expansion bus in the asynchro-
nous mode is similar to the operation in the synchro-
nous mode. The primary difference is that the clock
signal in the asynchronous mode is ECLK, which is
sourced by the IMR2 device transmitting DAT. The sig-
nals JAM, REQ, ACK, and COL are all asynchronous.
DAT is synchronized to ECLK, which is a 10-MHz clock
signal. When the IMR2 device asserts REQ and re-
ceives an ACK, ECLK is an output.When the IMR2 de-
vice does not assert REQ and receives an ACK, ECLK
is an input.
In the asynchronous mode, it is probable that ECLK and
the master clocks of the receiving IMR2 devices will be
24
Am79C983A
P R E L I M I N A R Y
The PR port has six signals: PCLK, PDAT, PENAO,
PENAI, PDRV, and PTAG. PCLK is a 10-MHz clock sig-
nal. PDAT transmits the packet data and is clocked by
the rising edge of PCLK. PENAO is an active-LOW sig-
nal and indicates when the PR port is active. PENAI
senses when a PR port of another IMR2 device is ac-
tive and is an active-LOW signal. PDRV is used to en-
able an external buffer for PCLK and PDAT. PTAG
indicates when the tag is being transmitted.
Preamble and SFD
Front of Original Packet
(min 14 Octets long)
Stat 1 Field
Device ID
The signal format is shown in 4. PDAT first transmits
the compressed or uncompressed packet. Then it
transmits the first status field. This field has the format
of the first statistics field shown in 4. At the end of the
first statistics field, PCLK is stopped until the end of the
packet. Then the second statistics field is transmitted
over PDAT along with a new FCS.
Port Number
(4 Bits)
Stat 2 Field
LSB Frame Size
(in Octets)
Multiple IMR2 devices can be connected to a single
MAC. If an IMR2 device becomes active while another
device is transmitting statistics, the new packet will not
be transmitted over the PR port.
MSB Frame
Size
(in Octets)
RAUI Port
The RAUI Port is a configurable AUI port. It has the
same signals that are associated with an AUI port: DO,
DI, and CI. For the RAUI Port, these are named RDO,
RDI, and RCI, respectively. The RAUI port can be con-
figured in either normal or reverse mode. When config-
ured in normal mode (default mode), the functionality is
that of an AUI port on a MAC. When configured in re-
verse mode, the RAUI port provides the functionality of
an AUI port on a MAU, with RCI acting as an output.
This reverse configuration allows the RAUI Port to be
connected directly to a MAC. However, the sense of
RDO and RDI does not change with the configuration.
Therefore, in the reverse configuration RDO should be
connected to DI of the MAC and RDI should be con-
nected to DO on the MAC.
New FCS
(4 Octets)
BROAD - Broadcast Address Match
MULT - Multicast Address Match
RES - Reserved. Set to Zero.
ROLL- Frame Size has exceeded
1535 bytes
BRE - Bit Rate Error
ALIGN - Framing Error
CRC - CRC Error
Note: The bit designation is LSB to the
left and MSB to the right. The fields are
transmitted LSB first.
19879B-7
Table 3. RAUI Port
Device Configuration
Figure 3. Detailed Report Packet
The presence of a valid destination address is deter-
mined by comparing the destination address of the
packet with the Last Source Address Register and the
Preferred Source Address Register associated with the
expansion bus. Comparison is enabled by setting the
EP bit of the Last Source Address Compare Enable
Register and/or the Preferred Source Address
Compare Enable Register. Setting the EP bit of the
Multicast Address Pass Enable Register inhibits com-
pression when the address is a multicast address.
RegisterBit 5
RAUI Port Mode
0
Normal Mode
ReverseMode
(RCI is an Output)
1
Am79C983A
25
P R E L I M I N A R Y
PDAT
Pre SFD DA SA T/L Field
Length in Bytes
Data
Stat1 Field
Stat2 Field FCS
PCLK
PENAO
PDRV
PTAG
19879B-8
Figure 4. Packet Port Signals
Error Packet Statistics
Status data is on the SDATA[3:0] pins, and serial inter-
face control is on the DIR[1:0] pins. SDATA is I/O. For
interfacing with non-QuIET devices, both DIR[1] and
DIR[0] are required. DIR[1:0] is used to select groups
of four ports. For interfacing with QuIET devices, only
DIR[1] is required.
Sample Error Status is an 8-byte 4-deep FIFO that con-
tains statistical data on each packet having errors. The
data is read in the following order:
Port Number
Status
1 byte
1byte:
DIR[1] controls the direction of data travel. Each SDATA
pin corresponds to a QuIET device connected to a set
of four specific IMR2 device ports.
FCS Error (LSB)
Non-Integral Bytes
Long
Pin
Port
Short
SDATA[0]
SDATA[1]
SDATA[2]
PAUI [3:0]
PAUI [7:4]
PAUI [11:8]
Runt
DataRateError
Very Long Event (MSB)
Source Address
6 bytes
Typically, SDATA[3] is not used for a 12-port repeater.
However, a QuIET device can be attached to the AUI
port and the RAUI port (in normal mode) to make a 14-
port repeater. The remaining two ports on the QuIET
device can be connected to two ports on another IMR2
device. SDATA[3] provides the MAU management for
all four ports on this QuIET device.
The FIFO is emptied by reading. If the FIFO is full, noth-
ing more is recorded in Sample Error Status. If the con-
trol port is accessed, the reading starts at the beginning
of the next location. If the data register is accessed after
the location has been completely read, the beginning of
the next location is automatically accessed.
QuIET Device Control and Status Data Interface
Operation
Transceiver Interface
PAUI Ports
The interface has two modes of operation: QuIET de-
vice mode and Non-QuIET device mode. The QuIET
device mode is automatically selected when a QuIET
device is attached and used, and the Non-QuIET mode
is selected when another type of transceiver is used.
Note that it is possible for different sets of ports to use
different types of transceivers.
Packets are transferred between an IMR2 device and
transceivers via twelve Pseudo AUI (PAUI) ports. The
PAUI ports have the functionality of AUI ports, except that
they are single-ended signals rather than differential.
QuIET Device Control and Status Data Interface
Control and status data are passed between the IMR2
device and QuIET devices via a serial data interface.
26
Am79C983A
P R E L I M I N A R Y
In the QuIET device mode, DIR[1] has the following values: Control and Status for Non-QuIET Transceivers
On the SDATA[n] pins that do not return the correct pre-
amble, the IMR2 device expects to see data correspond-
ing to the polarity status of the port. The corresponding
signals for each port on the transceiver should be con-
nected to a 4-to-1 multiplexer with DIR utilized as the
control lines. The multiplexer should behave as follows:
DIR[1]
0
QuIETdevicedrivesSDATAwithsta-
tus and device ID.
1
IMR2 device drives QuIET device
with commands.
DIR[1] continually cycles. The state of DIR changes
once every 50-bit times (1-bit time = 100 ns). When
DIR[1] switches from 1 to 0, the QuIET device re-
sponds in the following format:
DIR[1:0]
Action
Select Transceiver 0.
Select Transceiver 1.
Select Transceiver 2.
Select Transceiver 3.
00
01
10
11
01010A A A A B B B B C C C C D D D D S S
1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1
0
S S
2
3
01010
A A A A
1 2 3
Preamble
Device ID (0000 for QuIET)
DIR[1:0] rotates through the 10 → 00 → 01 → 11 cycle
regardless of the mode of SDATA[n].The mode of each
SDATA[n] pin can change with each cycle as transceiv-
ers are removed or inserted.
0
B B B B
1 2 3
0
1
0
1
0
1
Link Fail
0
Link Pass
C C C C
Received polarity is reversed.
Received polarity is correct.
No Jabber
0
1
2
3
Visual Status Monitoring (LED) Support
The IMR2 device has a status port which can be con-
nected to LEDs to facilitate visual monitoring of differ-
ent repeater ports. Five port status attributes can be
monitored: Carrier Sense (CRS), Collision (COLX),
Partition (PART), Link Status (LINK), and Polarity
(POL). The status of the ports is indicated on an 8-bit
bus, LD[7:0], which is time multiplexed to show all five
attributes for up to 16 ports. BSEL is the port select pin.
When the select pin (BSEL) is LOW, LD[7:0] has the
status of ports P7 through P0. When BSEL is HIGH,
LD[3:0] has the status of P11 through P8, LD[4] has the
status of the AUI port, and LD[5] has the status of the
RAUI port. LD[7:6]is used to display the port status of
a fourth QuIET device that optionally may be shared
with another IMR2 device.
D D D D
0
1 2
3
Jabber
S
Spares - Will be logic HIGH.
n
Each character corresponds to a bit. Each bit is held for 2-
bit times (200 ns). The IMR2 device uses the 01010 pre-
amble to determine if the transceiver is a QuIET device. If
any other sequence is received, the SDATA[n] pins be-
have as if a non-QuIET device transceiver is connected.
On the SDATA[n] pins that return the correct preamble,
the IMR2 device transmits the following sequence
when DIR[1] switches from 0 to 1.
0E E E E F F F F G G G G H H H H S S S S S S S
1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 4 5 6
0
CRS, COLX, PART, LINK, and POL are the attribute se-
lect pins. When an attribute select pin is HIGH, LD[7:0]
indicates the corresponding status attribute. The Status
Monitoring port continually cycles as per 5. Each strobe
is active for 64-bit times (6.4 µs). This allows a 10-per-
cent duty cycle. The following table gives the value of
LD[7:0] corresponding to the Attribute Select signal.
E E E E Extended Distance
0
1 2 3
0
1
Disabled
Enabled
F F F F
1 2 3
Link Test
0
0
1
Disabled
Enabled
G G G G Link Pulse Transmit
0
1
2
3
Signal
CRS
HIGH
LOW
No Activity
0
1
Disabled
Enabled
Activity
COLX
PART
LINK
POL
Collision
Connected
Good
No Collision
Partitioned
None
H H H H Reverse Received Polarity
0
n
1 2 3
0
1
Disabled
Enabled
Correct
Reversed
S
Spares - Will be logic HIGH.
Am79C983A
27
P R E L I M I N A R Y
LD[7:0]
LD [7:0]
BSEL
EN
EN
BSEL
CRS
COLX
PART
LINK
POL
CRS
COLX
PART
19879B-9
LINK
POL
Figure 5. Visual Monitor Signals
19879B-10
CRS and COLX are the only valid attributes for the Ex-
pansion Bus. Therefore, when BSEL is HIGH, LD[6]
has the Expansion Bus attribute for CRS and COLX.
Figure 6. Visual Monitoring Application -
Simplified Schematic
Using AUI/RAUI for 10BASE-T Ports
Intrusion Protection
The IMR2 device obtains Link and Polarity status from
the serial data interface (SDATA [3:0]). When a single
IMR2 device uses four QuIET devices, two of the ports
on the fourth QuIET device connect to the AUI and
RAUI ports of the IMR2.The two remaining ports on the
fourth QuIET device connect to a second IMR2 device.
Only the IMR2 device driving the serial interface to this
QuIET device has Link and Polarity Status. Therefore,
when BSEL is HIGH and either LINK or PART are
HIGH, LD[7:6] contains Link Status or Polarity Status,
respectively, of ports 2 and 3 of the fourth QuIET de-
vice.
The IMR2 device provides protection against intrusion,
which is defined here as the unauthorized transmitting
of packets onto the network.
Each port has two address registers associated with it:
Last Source Address Register and Preferred Source
Address Register. Unless it is locked, the Last Source
Address Register contains the source address of the
previous packet received by that port. The Preferred
Source Address Register contains the source address
that the system considers valid for that port. Both reg-
isters may be written.
If the AUI and RAUI ports are connected to a MAU
(other than a QuIET device), LINK actually reports
Loopback Error, where 1 indicates no loopback error
and 0 indicates a Loopback Error.The state of POL will
reflect the received polarity value on SDATA. The rec-
ommended implementation is shown in 6.The attribute
select pins are connected to open-collector or open-
drain inverters. The buffers connected to LD[7:0] have
high-impedance outputs. They must source enough
current to turn on the LEDs (typically 20 mA). CMOS
devices that have a rail-to-rail output are recom-
mended. Also, multiple open-collector inverters can be
used in conjunction with multiple drives to overcome
maximum current source/drain issues.
If the valid address is known by the system, it may be
written into both registers. If it is not known by the sys-
tem, the Last Source Address Register is monitored by
the system. After a packet is received by the port, the
source address may be written into the Preferred
Source Address Register by the system.
The Last Source Address Register may be locked. If
the Last Source Address Register is locked, a mis-
match between the packet's source address and the
Last Source Address Register will not result in a
change in the Last Source Address Register. The only
way the register can be changed is by accessing it
through the node processor interface. The control reg-
ister for this is the Last Source Address Lock Register.
CRS and COLX signals are stretched to enhance vi-
sual recognition, i.e., they will remain active for some
time even if the corresponding condition has expired.
Once carrier sense is active, CRS will remain active for
a minimum of 4 ms. Once a collision is detected, COLX
will remain active for at least 4 ms.
The IMR2 device provides two applicable interrupts:
Source Address Changed Interrupt and Intruder Inter-
rupt. Both interrupts can be masked on a port-by-port
basis. Source Address Changed Interrupt compares
the incoming packet's source address against two
registers: Last Source Address Register and the Pre-
ferred Source Address Register. The interrupt is set
when the source address of the incoming packet does
not match both registers. Intruder Interrupt compares
28
Am79C983A
P R E L I M I N A R Y
the incoming packet's source address with the Pre-
Write Cycle:
ferred Source Address Register. The interrupt is set
when there is a mismatch.
1. Data is to be placed on the Data (D[7:0]) pins prior
to trailing edge of WR.
If the Automatic Intrusion Control register bit is set, the
port is disabled if there is no match between the source
address and either valid source address for that port.
Valid addresses are determined from the correspond-
ing Preferred Source Address Automatic Intrusion
Control Register and Last Source Address Automatic
Intrusion Control Register. The selection of these reg-
isters as valid addresses is made by the Last Source
Address Compare Enable Register and the Preferred
Source Address Compare Enable Register. The port is
disabled after the FCS field and only if the packet is a
valid packet. Once the port is disabled, it can only be
enabled by the management software.
2. The IMR2 device releases RDY (pulled HIGH exter-
nally), indicating that it is ready to accept the data.
3. WR strobe is de-asserted (HIGH) in response to
RDY.The IMR2 device latches data internally on the
rising edge of WR.
4. The processor can stop driving Data pins after the
rising edge of the WR.
Many of the registers are two or more bytes long. In
these cases, the registers are read or written into by ac-
cessing the microprocessor port with C/D LOW the
same number of times as the byte size of the register.
Read Cycle:
Timer Values
1. The IMR2 device drives Data pins.
Descriptions and values for the various timers are
as follows:
2. The IMR2 device releases RDY (pulled HIGH), indi-
cating valid data.
3. De-assert RD (HIGH) in response to RDY HIGH.
Wait Timer for the end of
transmit recovery time
Tw1
Tw2
Tw3
10 bit times
3 bit times
4. The IMR2 device stops driving Data pins after the
trailing edge of RD.
Wait Timer for the end of
carrier recovery time
The interrupt pin (INT) is an open drain output. It is OFF
(high impedance) upon reset, when all interrupts are
disabled (masked), or when all internal sources of the
interrupts are cleared. It is ON (LOW) when any of the
enabled interrupts occur. Reading all the internal regis-
ters that caused the interrupt clears the internal source
of the interrupt, and sets INT OFF.
Wait Timer for length of
continuous output
65,536 bit times
Wait Timer for time to disable
Tw4 output for Jabber Lockup
Protection
96 bit times
WaitTimer for length of packet 452 to 523 bit
without collision
Tw5
Tw6
times
Wait Timer for excessive
length of collision
Management Functions
2048 bit times
All management functions are accessible through the
microprocessor interface. The functions are divided into
register banks which are subdivided into attribute regis-
ters. A register bank is selected by writing a byte with the
Number of consecutive
CC- collisions which must occur
Limit before a segment (port) is
partitioned
32 collisions
format 000P P P P P into the C port, where P
4
3
2
1
0
4
through P corresponds to the register bank. The de-
sired attribute register within the selected register bank
Microprocessor Interface
0
The IMR2 device implements a simple interface de-
signed to be used by a variety of available microproces-
sors. The bus interface is asynchronous and can be
easily adapted for different hardware interfaces.
is selected by writing 111R R R R R into the C port,
4
3 2 1 0
where R through R corresponds to the attribute regis-
4
0
ter. Data can then be read from or written to the D port.
For registers whose contents are cleared upon reading,
reading the first byte will clear the entire register. When
writing to registers, all bytes must be written consecu-
tively. If all register bytes are not written, the original
contents of the register are left unchanged.
The interface protocol is as follows:
1. Assert CS (LOW) and C/D (HIGH to access control
and LOW to access data).
2. Assert RD (LOW) to start a read cycle or WR (LOW)
to start a write cycle.
Most of the registers contain status or control informa-
tion on the individual ports. These registers are each
two bytes long. Each bit corresponds to an individual
port. Active statistics will be maintained on the data
received by DAT only if the EP bit of the Port Enable
Register is set and MACEN is TRUE.
3. The IMR2 device forces RDY LOW in response to
the leading edge of either of RD or WR.
Note: CS is internally gated with RD and WR, such
that CS may be permanently grounded if it is not re-
quired. A read or write cycle is started when CS and ei-
ther data strobe are asserted (LOW).
Am79C983A
29
P R E L I M I N A R Y
Unless otherwise indicated, the discussion of registers
incoming data packet.This bit remains set until the
Source Address Match Status Register is read.
that are concerned with status or control on the IMR2
device will have the following format.
B
Bit Rate Error and Partition. This bit is set if the
interrupt is caused by either a bit rate error or a
change in the partition status of a port.
IMR2 Device Registers
D Port Read/Write
M
Source Address Change.This bit is set if the inter-
rupt is caused by a change in the source address
or a mismatch between the incoming source ad-
dress and a preferred address.
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
EP/0
0
AUI P11 P10 P9 P8
P
Polarity and SQE. This bit is set if the interrupt is
caused by a change in the SQE test results or a
polarity change.
Where:
Pn refers to a PAUI port.
L
Link and Loopback.This bit is set if the interrupt is
caused by a link or loopback change.
AUI refers to the AUI port
RAUI refers to the RAUI port
EP refers to the Expansion Bus
X
Reserved. The values of reserved bits
are indeterminate.
Unless otherwise indicated, the discussion of regis-
ters that are concerned with status or control on
QuIET devices connected to the IMR2 device will
have the following format.
Register Bank 0: Repeater Registers
These registers are accessed by writing the bit pattern
0000 0000 to the C Register. The contents of all at-
tribute counters are indeterminate upon power up.
QuIET Device Registers
Source Address Match Register
Address: 1110 1010
D Port Read/Write
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Byte 0
Byte 1
TP11 TP10
SP3 SP2 SP1 SP0
TP9 TP8
D Port Read/Write
bit 7
bit 0
Byte 0
Byte 1
Where:
Byte 2
Byte 3
Byte 4
Byte 5
TPn refers to a TP port on a QuIET device.
SPn refers to a QuIET device port connected to
the AUI port or PAUI port on this device or to any
port on another IMR2 device.
bit 40
LSB
bit 47
MSB
Note: The port on the QuIET device may be connected
to a port on another IMR2 device.
This is a read/write register. The six bytes are read or
written in LOW byte to HIGH byte order. The sequence
is (re)started once the C register is programmed for ac-
cess to this register. This register may be used to track
nodes within a LAN by reporting the port that received
a packet with a specific source address.The source ad-
dress field of incoming packets is always compared
with the 48-bit quantity stored in this register.The initial
value of this register is indeterminate.
Status Register
The Status Register can be accessed at any time by
reading the Command Register.
The 8-bit quantity read has the following format:
C Port Read
E
I
S
X
B
M
P
L
I
Interrupt.Thisbitreflectsthestateofthe INToutput
pin. If this bit is set to 1, then this IMR2 device is
driving the INT pin. Note that INT is an open drain
output and that multiple devices may share the
same interrupt signal.
The IMR2 indicates a match by setting the correspond-
ing bit in the Source Address Match Interrupt Register
of the receiving port. If the Source Address Match In-
terrupt Enable bit is enabled, then the INT output pin is
driven LOW. The set bit(s) in the Source Address
Match Interrupt Registers are cleared when these reg-
isters are read.
E
S
Transceiver Interface Changed.This bit is set if the
interface to at least one SDATA input has changed
from a QuIET device to a non-QuIET device or
from a non-QuIET device to a QuIET device.
Note: Once the sequence is started, all six bytes have
to be written or the contents do not change.
Source Address Match. This bit is set if the inter-
rupt is caused by a source address match of the
30
Am79C983A
P R E L I M I N A R Y
D Port Read/Write
Total Octets
Address: 1110 1100
0
I
S
0
0
0
0
0
MSB
LSB
D Port Read/Write
bit 7
bit 0
Byte 0
I
Enable Interrupts.When this bit is set to 0 all inter-
rupts from this IMR2 device are masked (but not
cleared) and the INT output pin is forced into inac-
tive state (not driven).
Byte 1
Byte 2
bit 31
MSB
bit 24
LSB
Byte 3
S
Source Address Match Interrupt Enable.When this
bit is set, IMR2 device will generate an interrupt if
the Source Address of the received packet match-
es that which is programmed into the Source Ad-
dress Match Register.
This is a 4-byte attribute register whose contents are in-
cremented while the repeater is repeating packet data.
This counter is a truncated divide by 8 of the total num-
ber of bits transmitted by the repeated (i.e., the number
of whole bytes transmitted by the repeater). The
counter counts the bytes on all non-collision packets
with a valid Start of Frame Delimiter (SFD). The pre-
amble is included in the count.The four bytes in this at-
tribute are sequentially accessed by reading the D
register, LSB first. Note that once the C register is pro-
grammed for access to this attribute, reading the D reg-
ister port causes the value of this register to be copied
into the holding register. The data is then read off the
holding register, without affecting this attribute.This se-
quence is repeated when the last byte is read and the
D register is accessed.
Repeater Status
Address: 1111 1010
This is a read only register. Bit 0 is the only bit of inter-
est. When bit 0 is set, the IMR2 device has entered
MAU Jabber Lockup Protection (MJLP). The Repeater
Status register is cleared by reading.
D Port Read
0
0
0
0
0
0
0
E
LSB
MSB
E
0
1
Status
No Error
Error
Transmit Collisions
Address: 1110 1101
QuIET Device Transceiver ID Register
Address: 1111 1011
D Port Read/Write
bit 7
bit 0
Byte 0
This is a read-only register. It contains the transceiver
ID of the QuIET device connected to the IMR2 device.
The 16-bit quantity has the following format:
Byte 1
Byte 2
Byte 3
bit 31
MSB
bit 24
LSB
D Port Read
This is a 4-byte attribute whose contents are incre-
mented each time the repeater has entered the trans-
mit collision state from any state other than ONE PORT
LEFT. The bytes are read in LOW to HIGH order by
reading the Data (D) register consecutively. The se-
quence will be restarted once the last byte is read or
the C register is reprogrammed with this register num-
ber. This causes the current value of the counter to be
copied into a holding register, which is then read by ac-
cessing the D register.
Transceiver 1
Transceiver 0
Byte 0 M
M
M
M
M
M
M
M
M
13
12
11
10
03
02
01
00
20
Transceiver 3
Transceiver 2
M
M
M
M
M
M
M
Byte 1
33
32
31
30
23
22
21
MSB
LSB
Transceiver 0
Transceiver 1
Transceiver 2
Transceiver 3
PAUI [3:0]
PAUI [7:4]
PAUI [11:8]
AUI and RAUI ports or misc.
Configuration Register
Address: 1111 0000
This 16-bit register is divided into four sections. Each
section is labeled M to M where X refers to trans-
This is a read/write register. The value read is the
same as that written. Unused bits are read as zeros
and only zeros should be written into these bits. Do
not write non-zero values into unused bits. All bits are
cleared upon reset.
X3
X0
ceivers 0 through 3. These register bits are only valid if
the appropriate Transceiver Interface Status Register
bit indicates that a QuIET device is connected.
Am79C983A
31
P R E L I M I N A R Y
pattern 0000 0001 to the C Register. These registers
M
Transceiver
X3-X0
are read only and are cleared to 0 upon reading. When
all the interrupt registers are clear (all bits zero), the In-
terrupt bit of the Status Register and INT are cleared.
0
QuIET Device ID
Reserved
1 to 15
Repeater Device and Revision Register
Address: 1111 1100
Note that for each interrupt register there is a corre-
sponding interrupt enable register.The bits on the inter-
rupt register cannot set unless the corresponding bits
on the corresponding interrupt enable register are set.
This is a read only register. The 8-bit quantity read has
the following format:
D Port Read
D2
Port Partition Status Change Interrupt
Address: 1110 0000
D3
D1
D0
V3
V2
V1
V0
LSB
Any port changing state between partitioned and re-
connected causes the appropriate register bit to be set
to 1.
MSB
D
V
Device Type. These bits contain the IMR2
device code.
The format is as follows:
D Port Read
D3-0
0010
IMR2
Revision Number. These bits contain the revision
number.Software may interrogate these bits to de-
termine additional features that may be available
with future versions of the device.
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
0
AUI P11 P10 P9 P8
LSB
MSB
V3-0 0000
Revision 0
Pn/AUI/RAUI
0
1
Partition status of corresponding
port unchanged
Device Configuration
Address: 1111 1101
Partition status of corresponding
port changed
This is a read/write register. When this register is writ-
ten, zeros must be written into unassigned fields. The
8-bit quantity has the following format:
Runts with Good FCS Interrupt
Address: 1110 0001
D Port Read/Write
Any port receiving a packet that is less than 64 octets
(not including preamble and SFD), but is otherwise well
formed and error free, causes the appropriate bit to be
set. The format is as follows:
M
R
A
0
0
0
0
0
MSB
LSB
R
Repeater Reset. Setting Bit R resets the registers,
repeater, and MAC engine. It is the functional
equivalent of hardware reset, with the exception
that the microprocessor interface is not reset and
the ability to access RMON and port attribute reg-
isters is maintained.
D Port Read
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
MSB
Pn/AUI/RAUI/EP
0
1
No runts with valid FCS
Runt with valid FCS
M
A
Management Reset. Setting this bit causes the
MAC engine to be reset.When the M bit is set, the
IMR2 device still functions as a repeater, however
MIB tracking is disabled.Setting this bit also allows
the RMON registers and the attribute registers to
be preset by software.
Link Status Change Interrupt
Address: 1110 0010
A change in the Link Test state of a twisted pair port
associated with a repeater port (from fail to pass or pass
to fail) causes the appropriate bit to be set in this register.
This register is only valid when a QuIET device is
connected to the corresponding port(s).
This bit configures the RAUI port. The configura-
tion options are:
0
Normal Mode.The RAUI port is configured
as a standard AUI port.
1
Reverse Mode. RCI is an output, i.e., RCI
generates a 10-MHz signal during a collision.
D Port Read
Register Bank 1: Interrupts
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Byte 0
Byte 1
When a bit on an interrupt register is set, the interrupt
bit on the Status Register is set and the INT pin is
driven. These registers are accessed by writing the bit
TP10
TP11
SP2
SP3
MSB
SP1 SP0
TP9 TP8
LSB
32
Am79C983A
P R E L I M I N A R Y
TPn/SPn
0
Link Test state unchanged
Link Test state changed
Source Address Changed Interrupt
Address: 1110 0110
1
Loopback Error Change Interrupt
Address: 1110 0011
The corresponding bit in the register is set when the
source address of the incoming data packet matches
neither the Last Source Address Register nor the Pre-
ferred Source Address Register associated with the
port. The incoming packet must be an error-free packet.
If a port is connected to a MAU which does not loop-
back data from DO to DI during transmission that port
has a loopback error. For the error to be detected, the
network needs to be active and a packet transmitted
from the port. The corresponding bit is set to 1 when
the loopback error condition changes.
D Port Read
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
D Port Read
MSB
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
Pn/AUI/RAUI/EP
0
1
No change
RAUI
0
0
AUI P11 P10 P9 P8
LSB
Source address changed on
the incoming port
MSB
Intruder Interrupt
Pn/AUI/RAUI
0
No loopback error change
Loopback error change
Address: 1110 0111
1
A bit on the Intruder Interrupt Register is set when the
source address of an error-free incoming packet does not
match the corresponding Preferred Source Address Reg-
ister.The incoming packet must be an error-free packet.
Polarity Change Interrupt
Address: 1110 0100
The corresponding bit is set to 1 if the polarity of the
connected port is switched.
Note: The Preferred Address attribute is programma-
ble and can be used to store the expected Node ID for
a port. If the appropriate interrupt is also enabled, then
a Source Address Changed can be used to alert the
network manager of an unauthorized access. This is
particularly useful for segments that are supposed to
be connected to a single station.
D Port Read
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Byte 0
Byte 1
TP10
TP11
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
TPn/SPn
0
1
Polarity unchanged
Polarity changed
D Port Read
SQE Test Error Change Interrupt
Address: 1110 0101
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
of
If a port is connected to a MAU with SQE Test enabled
that port has an SQE Test Error. For the error to be de-
tected, the network needs to be active and a packet
must be transmitted from the port. The corresponding
bit on the register is set when the port changes from an
error state to a non-error state or from a non-error state
to an error state.
MSB
Pn/AUI/RAUI/EP
0
1
Intruder
status
port unchanged
Intruder
status
of
port changed
Source Address Match Interrupt
Address: 1110 1000
D Port Read
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
When the source address of an incoming packet from
any port matches the Source Address Match Register,
the appropriate bit is set. The received packet must be
an error-free packet.
RAUI
0
0
AUI P11 P10 P9 P8
LSB
MSB
Pn/AUI/RAUI
0
1
No SQE Test Error change
SQE Test Error change
D Port Read
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
MSB
Am79C983A
33
P R E L I M I N A R Y
Pn/AUI/RAUI/EP
0
1
No match
Jabber Interrupt
Source address matches the
SourceAddressMatchRegister
Address: 1111 0001
A bit on this register is set if the transceiver connected
to the corresponding port detects jabber.
Note: This function is useful for mapping stations to
ports in a network.
D Port Read
Data Rate Mismatch Interrupt
Address: 1110 1010
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Byte 0
Byte 1
TP10
TP11
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
A bit is set when the data received by the corresponding
port has caused an overflow or underflow of the FIFO.
This bit is not set unless the received packet, after SFD, is
at least 512 bits long and collision did not occur
TPn/SPn
0
1
Port does not jabber
Port in jabber
D Port Read
Register Bank 2: Interrupt Control Registers
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
These registers are accessed by writing the bit pattern
0000 0010 to the C Register. All registers can be read
from as well as written to. A set (1) control bit enables
an interrupt or function of the corresponding port. All
control registers are cleared upon reset. Also, all inter-
rupts are disabled and all status bits are cleared upon
hardware reset.
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
MSB
Pn/AUI/RAUI/EP
0
1
No error
Data rate error
Transceiver Interface Status
Address: 1110 1111
Partition Status Change Interrupt Enable
Address: 1110 0000
If a QuIET transceiver is not hardware connected, the
corresponding bit on the register is set.
This register is used to enable or mask interrupts
caused by a change in the Port Partitioning Status.
Note that if this is the only cause for the interrupt, dis-
abling an active interrupt source causes the INT output
to be placed into an inactive state. Software should be
designed to write zeros into unused bits.
D Port Read
X
X
X
X
Q3
Q2
Q1
Q0
MSB
LSB
QuIET 0 (Q0) PAUI [3:0]
QuIET 1 (Q1) PAUI [7:4]
QuIET 2 (Q2) PAUI [11:8]
D Port Read/Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
QuIET 3 (Q3) AUI and RAUI ports
RAUI
0
0
AUI P11 P10 P9 P8
LSB
Qn
0 QuIET device is connected
MSB
1 Non-QuIET transceiver is connected
Pn/AUI/RAUI
0
1
Partition Status Change Interrupt
masked (disabled)
Transceiver Interface Change Interrupt
Address: 1111 0000
Partition
Status
Change
If the device changes from a QuIET device to another type
of transceiver or from a non-QuIET device to a QuIET
device, the corresponding bit on the register is set.
Interrupt enabled
Runts with Good FCS Interrupt Enable
Address: 1110 0001
D Port Read
This register is used to enable or mask interrupts
caused by a port receiving a packet that is less than 64
octets (not including preamble and SFD), but is other-
wise well formed and error free.
X
X
X
X
Q3
Q2
Q1
Q0
MSB
LSB
QuIET 0 (Q0)PAUI [3:0]
D Port Read/Write
QuIET 1 (Q1) PAUI [7:4]
QuIET 2 (Q2) PAUI [11:8]
QuIET 3 (Q3) AUI and RAUI ports
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
Qn
0
1
No change of transceiver type
Change of transceiver type
MSB
34
Am79C983A
P R E L I M I N A R Y
Runts with Valid FCS Interrupt
Pn/AUI/RAUI/EP
0
1
Setting a bit in this register causes an interrupt to be
generated when the IMR2 device senses a change in
the SQE Test Error condition at a port. This occurs
when an attached MAU has SQE Test enabled. A new
interrupt is generated when a condition change is
sensed by the IMR2 device.
masked (disabled)
Runts with Valid FCS
Interrupt enabled
Link Status Change Interrupt Enable
Address: 1110 0010
D Port Read/Write
Setting any of the bits in this register causes the INT pin
to be driven when there is a change in the Link Test
state of the corresponding port.The corresponding sta-
tus bit in the LinkTest State Change Register is set to 1.
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
0
AUI P11 P10 P9 P8
LSB
MSB
D Port Read/Write
Pn/AUI/RAUI
0
1
SQE Test Error Change
Interrupt masked (disabled)
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Byte 0
Byte 1
TP10
TP11
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
SQE Test Error Change
Interrupt enabled
Source Address Changed Interrupt Enable
Address: 1110 0110
TPn/SPn
0
1
Link Status Change Interrupt
masked (disabled)
This register enables interrupts caused by a mismatch
between the source address of an incoming packet and
either the Last Source Address Register or the Preferred
Source Address Register. If Last Source Address Lock
is not set and the packet is a valid packet, a mismatch
between the source address and the Last Source
Address Register also causes the new source address
to be written into the Last Source Address Register.
Link Status Change Interrupt
enabled
Loopback Error Change Interrupt Enable
Address: 1110 0011
Setting a bit in this register causes an interrupt to be
generated when the IMR2 device senses a change in the
Loop Back Error condition on the corresponding port.
D Port Read/Write
D Port Read/Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
RAUI
0
0
AUI P11 P10 P9 P8
LSB
MSB
MSB
Pn/AUI/RAUI/EP
0
1
Source
Address
Changed
Interrupt masked (disabled)
Source Address Changed
Interrupt enabled
Pn/AUI/RAUI
0
Loopback Error Change Interrupt
masked (disabled)
1 Loopback
Error
Change
Interrupt enabled
Intruder Interrupt Enable
Address: 1110 0111
Polarity Change Interrupt Enable
Address: 1110 0100
This register enables interrupts to be generated when the
source address of an incoming packet does not match the
Preferred Source Address Register on the corresponding
port. The corresponding interrupt can be interpreted as
an attempt by an intruder to gain access to the network.
The management system can then take appropriate ac-
tion, such as disabling the corresponding port.
Setting a bit in this register causes an interrupt to be gener-
ated when the polarity of the connected port is changed.
D Port Read
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Byte 0
Byte 1
TP10
TP11
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
TPn/SPn
0
1
Polarity Change Interrupt
masked (disabled)
D Port Read/Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
Polarity Change Interrupt
enabled
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
MSB
SQE Test Error Change Interrupt Enable
Address: 1110 0101
Pn/AUI/RAUI
0
1
Intruder Interrupt masked (disabled)
Intruder Interrupt enabled
Am79C983A
35
P R E L I M I N A R Y
Note: Zeros should be written to all register bits except
Multicast Address Pass Enable
Address: 1110 1001
the EP bit.
Preferred Address Compare Enable
Address: 1110 1111
Setting EP disables packet compression on packets
with multicast addresses.
Setting the EP bit in this register enables a comparison
of the destination address of an incoming packet to the
Preferred Address Register for the expansion port.
Packet compression is disabled when the destination
address matches the Preferred Address Register.
D Port Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
Byte 0
Byte 1
0
0
EP
0
MSB
LSB
D Port Read/Write
EP
0
1
Packet compression on pack-
ets with multicast addresses
is enabled
0
0
0
0
0
0
0
0
0
0
0
0
0
Byte 0
Byte 1
0
EP
0
Packet compression on pack-
ets with multicast addresses
is disabled
LSB
MSB
EP
0
1
Preferred Source Address
Compare disabled
Note: Zeros should be written to all register bits ex-
cept the EP bit.
Preferred Source Address
Compare enabled
Data Rate Mismatch Interrupt Enable
Address: 1110 1010
Note: Zeros should be written to all register bits except
the EP bit.
The IMR2 device can generate an interrupt if received
data is outside the data rate tolerances. Setting a bit
enables the Data Rate Mismatch Interrupt control of
the corresponding port.
Transceiver Interface Changed Interrupt Enable
Address: 1111 0000
When a bit is set, an interrupt is generated if the device
connected to the corresponding port changes from a
QuIET device to a non-QuIET device or from a non-
QuIET device to a QuIET device.
D Port Read/Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
MSB
D Port Read/Write
Pn/AUI/RAUI/EP
0
1
Data Rate Mismatch Interrupt
masked (disabled)
X
X
X
X
Q3
Q2
Q1
Q0
MSB
LSB
Data
Rate
Mismatch
Interrupt enabled
Transceiver 0
Transceiver 1
PAUI [3:0]
PAUI [7:4]
PAUI [11:8]
Last Source Address Compare Enable
Address: 1110 1100
Transceiver 2
Transceiver 3
Setting the EP bit in this register enables a comparison
of the destination address of an incoming packet to the
Last Source Address Register for the expansion port.
Packet compression is disabled when the destination
address matches the Last Source Address Register.
AUI and RAUI ports
Qn
0
Device Connection Changed Test
masked (disabled)
1
Device Connection Changed Test enabled
Jabber Interrupt Enable
Address: 1111 0001
D Port Read/Write
When a bit in this register is set, an indication of jabber
from a port will cause an interrupt.
0
0
0
0
0
0
0
0
0
0
0
0
0
Byte 0
Byte 1
0
EP
0
D Port Read/Write
MSB
LSB
TP7
TP5 TP4 TP3 TP2 TP1 TP0
TP6
Byte 0
Byte 1
EP
0
1
Last Source Address Com-
pare masked (disabled)
TP10
TP11
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
Last
Source
Address
TPn/SPn
0 Jabber Interrupt
Compare enabled
masked (disabled)
1 Jabber Interrupt enabled
36
Am79C983A
P R E L I M I N A R Y
once after reset or link fail. On reset, this register de-
Register Bank 3: Port Control Registers
faults to Automatic Receiver Polarity Reversal disabled.
These registers are accessed by writing the bit pattern
0000 0011 into the C register. All registers can be read
from as well as written to.
D Port Read/Write
TP7
TP5 TP4 TP3 TP2 TP1 TP0
TP6
Byte 0
Byte 1
Alternative Reconnection Algorithm Enable
Address: 1110 0000
TP10
TP11
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
The AUI Partitioning/Reconnection state machine can
be programmed for the alternative reconnection algo-
rithm (transmit only). On reset, this register defaults to
the standard reconnection algorithm.
TPn/SPn
0
1
Automatic Receiver Polarity
Reversal disabled
Automatic Receiver Polarity
Reversal enabled
D Port Read/Write
SQE Mask Enable
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
Address: 1110 0101
RAUI
0
0
AUI P11 P10 P9 P8
LSB
Setting a bit in this register allows the corresponding
port to ignore activity on CI during the SQE test window
following a transmission on that port.The SQE test win-
dow is defined by ANSI/IEEE 802.3, Section 7.2.2.2.4
as 6-bit times to 31-bit times following the end of the
packet. Note that the SQE Mask does not affect report-
ing SQE tests on the SQE Status Register and the
SQE Test Change Interrupt Register. On reset, this reg-
ister defaults to SQE Test Mask disabled.
MSB
Pn/AUI/RAUI
0
Standard Reconnection Algorithm
Alternative Reconnection Algorithm
1
Link Test Enable
Address 1110 0010
Setting a bit in this register enables the Link Test func-
tion for the corresponding port. This is only in effect
when the IMR2 device is interfaced to a QuIET device.
On reset, this register defaults to Link Test Enabled.
D Port Read/Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
D Port Read/Write
RAUI
0
0
AUI P11 P10 P9 P8
LSB
TP5 TP4 TP3 TP2 TP1 TP0
TP7 TP6
Byte 0
Byte 1
MSB
TP11 TP10
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
Pn/AUI/RAUI
0
1
SQE Test Mask disabled
SQE Test Mask enabled
TPn/SPn
0 Link Test Function disabled
1 Link Test Function enabled
Port Enable/Disable
Address 1110 0110
Link Pulse Transmit Enable
Address: 1110 0011
Setting a bit in this register enables the corresponding
port. On reset, the ports default to enabled.
Setting a bit in this register enables the corresponding port
to transmit a Link Test Pulse.This is only in effect when the
IMR2 device is interfaced to a QuIET device. On reset, this
register defaults to Link Test Pulse Transmit enabled.
D Port Read/Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
MSB
D Port Read/Write
TP7
TP5 TP4 TP3 TP2 TP1 TP0
TP6
Byte 0
Byte 1
Pn/AUI/RAUI
0
1
Disable the corresponding port
Enable the corresponding port
TP11 TP10
SP3 SP2 SP1 SP0
TP9 TP8
Setting the EP bit will not disable the expansion bus.
However, if the EP bit is not set, data carried on the ex-
pansion bus that is addressed to a MAC will not be
counted in the MIB attributes.
TPn/SPn
0
1
Link Test Pulse Transmit disabled
Link Test Pulse Transmit enabled
Automatic Receiver Polarity Reversal Enable
Address 1110 0100
Port Switching Control
Address: 1110 0111
Setting a bit in this register enables the QuIET device to
automatically invert the receive signal following detec-
tion of the first packet with inverted polarity. This is done
Setting a bit in this register isolates the corresponding
port. All input signals to the corresponding port and all
information concerning port activity from the transceiver
Am79C983A
37
P R E L I M I N A R Y
are ignored. This feature is useful when implementing Pn/AUI/RAU
port switching.The IMR2 device connected to the QuIET
device serial interface will still report correct status on
the Link and Polarity LEDs. The ports default to the
XENA value on reset.
0
Automatic Intrusion Control with
Last Source Address disabled
1
Automatic Intrusion Control with
Last Source Address enabled
Automatic Preferred Source Address Intrusion Control
Address: 1110 1010
D Port Read/Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
Automatic Intrusion Control disables a port automatically
when a valid packet (no errors) is received with a source
address which is not a valid address for that port. Before
a bit on this register is set, the corresponding Preferred
Address register should contain a valid address for that
port. On reset, this register defaults to Automatic Intrusion
Control with Preferred Source Address disabled.
RAUI
0
0
AUI P11 P10 P9 P8
LSB
MSB
Pn/AUI/RAUI
0
Isolate the corresponding port
Connect the corresponding port
1
Note: If a port is isolated during an incoming or transmit-
ted packet, repeating the packet is immediately stopped.
If a port is connected during an incoming packet, the ac-
tual connection is delayed until after the end of the packet.
If a port is connected while the IMR2 device is repeating
a packet, the connection is made immediately.
D Port Read/ Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
0
AUI P11 P10 P9 P8
LSB
Automatic Intrusion Control with
MSB
Extended Distance Enable
Address: 1110 1000
Pn/AUI/RAUI
0
1
Preferred
disabled
Source
Address
Setting a bit on this register lowers the input threshold
on RXD of the corresponding QuIET transceiver. This
allows the use of a twisted pair cable longer than 100
meters. This register is only in effect if the correspond-
ing port is connected to a QuIET device. On reset, this
register defaults to Extended Distance Option disabled.
Automatic Intrusion Control with
Preferred
enabled
Source
Address
Note: The Automatic Preferred Source Address Intru-
sion Control Register and the Automatic Last Source Ad-
dress Intrusion Control Register work together. If intrusion
on a port is not enabled on either register, intrusion control
is not performed for that port. If intrusion on a port is en-
abled on only one of the intrusion control registers, intru-
sion control is based on the corresponding enabled
register. If intrusion on a port is enabled on both intrusion
control registers, the port is disabled if the source address
fails to match both the Last Source Address Register and
the Preferred Source Address Register.
D Port Read/Write
TP7
TP5 TP4 TP3 TP2 TP1 TP0
TP6
Byte 0
Byte 1
TP10
TP11
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
TPn/SPn
0
1
Extended
disabled
Distance
Distance
Option
Option
Extended
enabled
Last Source Address Lock Control
Address: 1110 1011
Automatic Last Source Address Intrusion Control
Address: 1110 1001
Whenever the source address of an incoming packet is
different from the Last Source Address Register, the
new source address is written into the Last Source Ad-
dress Register. Setting a bit on this register disables
automatic updating of the Last Source Address Regis-
ter based on the last received packet. The Last Source
Address Register can still be written into via the node
processor interface. On reset, this register defaults to
Last Source Address Lock disabled. Note that a re-
peater that uses Last Source Address Lock Control will
not comply with IETF RFC 1516.
Automatic Intrusion Control disables a port automati-
cally when a valid packet (no errors) is received with a
source address which is not a valid address for that
port. Before a bit on this register is set, the correspond-
ing Last Source Address Register should contain a
valid address for that port. On reset, this register de-
faults to Automatic Intrusion Control with Last Source
Address disabled. See note under Automatic Preferred
Source Address Intrusion Control.
D Port Read/Write
D Port Read/Write
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
0
AUI P11 P10 P9 P8
LSB
RAUI
0
EP
AUI P11 P10 P9 P8
LSB
MSB
MSB
38
Am79C983A
P R E L I M I N A R Y
Pn/AUI/RAUI/EP
0
1
Last Source Address Lock
disabled
Note: The RAUI bit is not valid when the RAUI port is
in the reverse mode.
Last Source Address Lock
enabled
Receive Polarity Status
Address: 1110 0100
Note: Setting a bit on this register invalidates the cor-
responding Source Address Changes Register.
Each register bit represents the receive polarity status
of the corresponding port. The bit setting is based on
data received from the QuIET device through the serial
interface. If another transceiver device is used, the bit
setting reflects what is on the corresponding SDATA.
Register Bank 4: Port Status Registers
These registers are accessed by writing 0000 0100 to
the C register.
D Port Read
Partitioning Status of Ports
Address: 1110 0000
TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0
Byte 0
Byte 1
TP10
TP11
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
These bits indicate the partition status of the corre-
sponding ports. Ports that are partitioned will transmit
packets. However, the IMR2 device will not repeat
packets received by a partitioned port.
TPn/SPn
0
1
Polarity correct
Polarity reversed
SQE Test Status
D Port Read
Address: 1110 0101
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
These register bits reflect the status of the last packet
received from the corresponding port. The RAUI bit is
not valid when the RAUI port is in the reverse mode.
RAUI
0
0
AUI P11 P10 P9 P8
LSB
MSB
Pn/AUI/RAUI
0
Port partitioned
Port connected
D Port Read
1
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
RAUI
0
0
Link Test Status of Ports
Address: 1110 0010
AUI P11 P10 P9 P8
LSB
MSB
The register bits indicate the Link Test Status of the cor-
responding ports. The bit setting is based on data re-
ceived by the QuIET device.Therefore, the bit setting is
invalid if a non-QuIET transceiver is used for the port.
Pn/AUI/RAUI
0
1
No SQE Test Error
SQE Test Error
Register Bank 5: RMON Registers
The RMON registers can be accessed by writing to ad-
dress 0000 0101 and then accessing the individual reg-
isters. The RMON registers are 32-bit counters and
comply with etherStatsEntry of the statistics group of
the RMON MIB (RFC 1757) or etherHistoryEntry of the
History group of RFC 1757. They are 4 bytes long and
are read low order byte to high order byte.
D Port Read
TP7
TP5 TP4 TP3 TP2 TP1 TP0
TP6
Byte 0
Byte 1
TP11 TP10
SP3 SP2 SP1 SP0
MSB
TP9 TP8
LSB
TPn/SPn
0
1
Link Test failed
Link Test passed
The RMON registers can usually only be read. How-
ever, they can be written to when the Repeater Reset
bit or the Management Reset bit on the Device Config-
uration Register is set.
Loopback Error Status
Address: 1110 0011
When a packet is transmitted, the DO signal is looped
back to the IMR2 device through the corresponding DI
pins.When a bit on this register is set, data is not being
looped back to the IMR2 device.
etherStatsOctets
Address: 1110 0000
The value in this register represents the total number of
octets received (excluding preamble bits, but including
FCS bits) by the IMR2 device.
D Port Read
P7 P6 P5 P4 P3 P2 P1 P0
Byte 0
Byte 1
etherStatsPkts
RAUI
0
0
AUI P11 P10 P9 P8
LSB
Address: 1110 0001
MSB
The value in this register represents the total number of
packets received by the IMR2 device.
Pn/AUI/RAUI
0
1
No Loopback Error
Loopback Error
Am79C983A
39
P R E L I M I N A R Y
etherStats65to127Octets
etherStatsBroadcastPkts
Address: 1110 0010
Address: 1110 1011
The value in this register represents the total number
of valid packets received that were addressed to a
broadcast address.
The value in this register represents the total number of
packets (including error packets) that were 65 octets to
127 octets long inclusive.
etherStatsMulticastPkts
Address: 1110 0011
etherStats128to255Octets
Address: 1110 1100
The value in this register represents the total number
of valid packets received that were addressed to a
multicast address.
The value in this register represents the total number of
packets (including error packets) that were 128 octets
to 255 octets long inclusive.
etherStatsCRCAlignErrors
Address: 1110 0100
etherStats256to511Octets
Address: 1110 1101
The value in this register represents the total number of
packets received that were between 64 and 1518 octets,
inclusive, and had either FCS errors or alignment errors.
The value in this register represents the total number of
packets (including error packets) that were 256 octets
to 511 octets long inclusive.
etherStatsUndersizePkts
Address: 1110 0101
etherStats512to1023Octets
Address: 1110 1110
The value in this register represents the total number of
packets received that were less than 64 octets long, but
were otherwise error free.
The value in this register represents the total number of
packets (including error packets) that were 512 octets
to 1023 octets long inclusive.
etherStatsOversizePkts
Address: 1110 0110
etherStats1024to1518Octets
Address: 1110 1111
The value in this register represents the total number of
packets received that were greater than 1518 octets
long, but were otherwise error free.
The value in this register represents the total number of
packets (including error packets) that were 1024 octets
to 1518 octets long inclusive.
etherStatsFragments
Address: 1110 0111
Activity
Address: 1111 0000
The value in this register represents the total number of
packets received that were less than 64 octets long, not
including the preamble or SFD, and had either an FCS
error or an alignment error.
The value in this register represents the total number of
octets that were active on the IMR2 device.
Register Bank 7: Management Support
These registers control packet compression and error
sampling. The Management Support Registers can be
accessed by writing 0000 0111 to the C Register and
then writing the register address to the C Register.
etherStatsJabbers
Address: 1110 1000
The value in this register represents the total number of
packets that were greater than 1518 octets long and
had either FCS errors or alignment errors.
Device ID
Address: 1110 0000
Note: This differs from the IEEE definition of Jabber.
etherStatsCollisions
The Device ID Register is a read/write register. It is an
8-bit register and contains the assigned ID number of
the IMR2 device. This number is transmitted as part of
the tag field by the Packet Report Port.
Address: 1110 1001
The value in this register represents the total number of
collisions on the IMR2 device.
Sample Error Status
Address: 1110 0010
etherStats64Octets
Sample Error Status gives statistical data on packets that
have errors. It is a 4-deep 8-byte FIFO. Each read re-
quires accessing the data register eight times. The ac-
cess can jump to the next level of the FIFO in the middle
of a read by writing any value to the node processor port
with the C/D pin HIGH. If the node processor port is ac-
cessed (with the C/D pin LOW) after the last byte is read,
Address: 1110 1010
The value in this register represents the total number of
packets (including error packets) that were 64 octets long.
40
Am79C983A
P R E L I M I N A R Y
the register jumps to the next level automatically.The data
format is as follows:
D Port Read/Write
T
0
F
0
0
0
0
0
MSB
LSB
D Port Read/Write
T
F
0 Packet tagging is disabled
1 Packet tagging is enabled
E
0
0
0
N3 N2 N1 N0
Byte 0
Byte 1
Byte 2
0
VL
DRE
RNT S
L
A
FCS
0 Appending of a new FCS during port tag-
ging is disabled
bit 23
bit 16
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
1 Appending of a new FCS during port tag-
ging is enabled
Register Banks 16 through 30: Port Attribute
Registers
bit 56
bit 63
Port Attribute registers are accessed by writing the ap-
propriate port number into the C register, followed by
the attribute number. The table below shows the corre-
sponding register bank for each port.
MSB
LSB
E
Packet 0 - Empty
1 - Valid
Register Bank Access
0001 0000
0001 0001
0001 0010
0001 0011
0001 0100
0001 0101
0001 0110
0001 0111
0001 1000
0001 1001
0001 1010
0001 1011
0001 1100
0001 1101
0001 1110
Port
0
1
2
3
4
5
6
7
8
9
10
11
AUI
RAUI
N3-0 Port Number
VL Very Long Event
DRE Data Rate Error
RNT Runt Packet
S
L
A
Short Event
Long Event
Alignment Error
FCS Error
Source Address. It is read low
order byte to high order byte.
FCS
Bytes 2-7
Note: The FIFO is emptied by reading. If the FIFO is
full, nothing more is recorded in Sample Error Status. If
the FIFO is empty (bit E = 0), there is nothing in the re-
maining 7 bytes; therefore, the next access will be the
first byte of the 8-byte register.
Expansion Bus
(activity recorded
when MACEN
is TRUE)
Report Packet Size
Address: 1110 0011
Report Packet Size is a two-byte register. The eleven
least significant bits are used. It sets the length of the
original packet (in octets) that is transmitted over the
Packet Report Port. The LS Byte is accessed first. The
limits are 14 bytes (binary 000000001110) and 1535
bytes (binary 10111111111). If the register is set at
less than 14, 14 bytes of the original packet are trans-
mitted over the Packet Reports Port. If the register is
set at greater than 1535 bytes, all of the original packet
is sent over the Packet Report Port.
Except for the Last Source Address Register and the
Preferred Source Register, all registers are four bytes
long and read only unless special conditions are met.
The Last Source Address Register and the Preferred
Source Address Register are six bytes long and their
contents can be written and read.
Once the C Register is programmed with a valid port
and attribute number, the corresponding attribute is
transferred to a holding register upon reading the first
byte. Subsequent accesses to the D register access
the value in a least significant to most significant byte
order. During a read, once the last byte is read, the at-
tribute value is re-transferred to the holding register
and the sequence can be restarted.
D Port Read/Write
bit 0
bit 8
LSB
bit 7
bit 15
Byte 0
Byte 1
MSB
When writing the Last Source Address Register and the
Preferred Source Register, if the sequence is aborted
prior to the 6th consecutive write cycle, the register value
is not altered. The sequence (read or write) may be
aborted and restarted by programming the C register.
STATS Control
Address: 1110 0100
STATS Control is a 1-byte register. It sets the operation
of the Packet Report Port and the RAUI port.
Am79C983A
41
P R E L I M I N A R Y
The contents of all attribute registers are maintained
during hardware or software reset.
Frame Check Sequence (FCS) Errors
Address: 1110 0010
These attributes and their definitions comply with the
IEEE 802.3 Repeater Management standard,
Section19 (Layer Management for 10 Mb/s Baseband
Repeaters). A brief description of attributes is included
here for reference only. For more details refer to the
IEEE document. An IMR2-based hub can be designed
that will comply with IETF RFC 1515 and RFC 1516.
D Port Read
bit 0
bit 7
Byte 0
Byte 1
Byte 2
Byte 3
bit 31
MSB
bit 24
LSB
The Port Attribute Registers can be written into if one of
two conditions are met. The first is when either the M bit
or the R bit on the Device Configuration Register is set.
The second is when the corresponding port is disabled.
FrameCheckSequence (FCS) Errors is a read-only
attribute that counts the number of frames detected on
each port with an invalid frame check sequence. This
counter is incremented on each frame of valid length
(64 bytes to 1518 bytes) that does not suffer a collision
during the frame. This counter is incremented on each
invalid frame. However, it is not incremented for frames
with both framing errors and frame check sequence
errors.This attribute is a 32-bit counter with a minimum
rollover time of 80 hours.
Readable Frames
Address: 1110 0000
D Port Read
bit 0
bit 7
Byte 0
Byte 1
Byte 2
Byte 3
Alignment Errors
bit 31
MSB
bit 24
LSB
Address: 1110 0011
D Port Read
Readable Frames is a read-only attribute that counts
the number of valid frames detected by the port. Valid
frames are from 64 bytes to 1518 bytes in length, have
a valid frame CRC, and are received without a collision.
This attribute is a 32-bit counter with a minimum roll-
over time of 80 hours.
bit 0
bit 7
Byte 0
Byte 1
Byte 2
Byte 3
bit 31
MSB
bit 24
LSB
Readable Octets
Alignment Errors is a read-only attribute that counts the
number of frames detected on each port with an FCS
error and a framing error.This counter is incremented on
each frame of valid length (64 bytes to 1518 bytes) that
does not suffer a collision during the frame. Frames that
have both framing errors and FCS errors are counted by
this attribute, but not by the Frame Check Sequence
Errors attribute. This attribute is a 32-bit counter with a
minimum rollover time of 80 hours.
Address: 1110 0001
D Port Read
bit 0
bit 7
Byte 0
Byte 1
Byte 2
Byte 3
bit 31
MSB
bit 24
LSB
Frames Too Long
Readable Octets is a read-only attribute that counts the
number of octets received on each port. This number is
determined by adding the frame length to this register at
the completion of every valid frame.This attribute is a 32-
bit counter with a minimum rollover time of 58 minutes.
Address: 1110 0100
D Port Read
bit 0
bit 7
Byte 0
Byte 1
Byte 2
Byte 3
bit 31
MSB
bit 24
LSB
Frames Too Long is a read-only attribute that counts
the number of frames that exceed the maximum valid
packet length of 1518 bytes. This attribute is a 32-bit
counter with a minimum rollover time of 61 days.
42
Am79C983A
P R E L I M I N A R Y
Short Events
Late Events
Address: 1110 0101
Address: 1110 1000
D Port Read
D Port Read
bit 7
bit 7
bit 0
bit 0
Byte 0
Byte 0
Byte 1
Byte 2
Byte 1
Byte 2
Byte 3
bit 31
bit 24
LSB
bit 31
MSB
bit 24
LSB
Byte 3
MSB
Short Events is a read-only attribute that counts the
number of instances where activity is detected with a
duration less than the ShortEventMaxTime (74-82 bit
times).This attribute is a 32-bit counter with a minimum
rollover time of 16 hours.
Late Events is a read-only attribute that counts the
number of instances where a collision is detected after
the LateEventThreshold (480-565 bit times) in the
frame. This event will be counted both by the Late
Events attribute, as well as the Collisions attribute.This
attribute is a a 32-bit counter with a minimum rollover
time of 81 hours.
Runts
Address: 1110 0110
Very Long Events
Address: 1110 1001
D Port Read
bit 0
bit 7
Byte 0
D Port Read
Byte 1
Byte 2
Byte 3
bit 0
bit 7
Byte 0
Byte 1
Byte 2
Byte 3
bit 31
MSB
bit 24
LSB
bit 31
MSB
bit 24
LSB
Runts is a read-only attribute that counts the number of
instances where activity is detected with a duration
greater than the ShortEventMaxTime (74-82 bit times,
but less than the minimum valid frame time (512-bit
times, or 64 bytes). This attribute is a 32-bit counter
with a minimum rollover time of 16 hours.
Very Long Events is a read-only attribute that counts
the number of times the transmitter is active in ex-
cess of the MAU Jabber Lockup Protection (MJLP)
Timer (4 ms - 7.5 ms). This attribute is a 32-bit
counter with a minimum rollover time of 198 days.
Note: Runts usually indicate collision fragments, a
normal network event. In certain situations associated
with large diameter networks, a percentage of runts
may exceed ValidPacketMinTime.
Data Rate Mismatches
Address: 1110 1010
Collisions
D Port Read
bit 0
Address: 1110 0111
bit 7
Byte 0
Byte 1
Byte 2
Byte 3
D Port Read
bit 0
bit 7
Byte 0
bit 31
MSB
bit 24
LSB
Byte 1
Byte 2
Byte 3
Data Rate Mismatches is a read-only attribute that
counts the number of occurrences where the frequency
or data rate of the incoming signal is detectably differ-
ent from the local transmit frequency. To be counted,
the incoming packet must be at least 512 bytes and not
in collision. The attribute is a 32-bit counter with a min-
imum rollover time of 80 hours.
bit 31
MSB
bit 24
LSB
Collisions is a read-only attribute that counts the num-
ber of instances where a carrier is detected on the port,
and a collision is detected. This attribute is a 32-bit
counter with a minimum rollover time of 16 hours.
Note: The rate at which the Data Rate Mismatches
attribute will increment will depend on the magnitude of
the difference between the received signal clock and
the local transmit frequency.
Am79C983A
43
P R E L I M I N A R Y
Last Source Address is a read/write attribute and is the
Auto Partitions
source address of the last readable frame received by
this port.
Address: 1110 1011
D Port Read
This 6-byte register may be read from or written to.This
feature allows the software to preset this attribute to the
known Node ID for a single node segment. A change in
the contents of this register would then signal an anom-
aly. This will cause the Source Address Changes at-
tribute to increment. Furthermore, setting the
respective PAUI/AUI/RAUI Port Source Address
Change Interrupt Enable bit (in the Port Control Regis-
ters) can be used to generate a hardware interrupt to
signal the software to automatically disable this port.
bit 0
bit 7
Byte 0
Byte 1
Byte 2
Byte 3
bit 31
MSB
bit 24
LSB
Auto Partitions is a read-only attribute that counts the
number of instances where the repeater has partitioned
this port from the network.This attribute is a 32-bit counter
that is incremented on each such event.The approximate
minimum time between counter rollovers is 20 days.
Readable Multicast Frames
Address: 1110 1111
Source Address Changes
Address: 1110 1100
D Port Read
bit 0
bit 7
Byte 0
D Port Read
Byte 1
Byte 2
Byte 3
bit 0
bit 7
Byte 0
bit 31
MSB
bit 24
LSB
Byte 1
Byte 2
Byte 3
bit 31
MSB
bit 24
LSB
The counter is incremented by one each time this port
receives an error-free multicast frame. Broadcast
frames are not counted.
Source Address Changes is a read-only attribute that
counts the number of times the source address field of
valid frames received on a port changes. This attribute
is a 32-bit counter with a minimum rollover of 81 hours.
Preferred Source Address
Address: 1111 0000
Note: This may indicate whether a link is connected to
D Port Read/Write
a single DTE or another multi-user segment.
bit 7
bit 0
Byte 0
Readable Broadcast Frames
Address: 1110 1101
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
D Port Read
bit 0
bit 7
Byte 0
bit 40
LSB
bit 47
MSB
Byte 1
Byte 2
Byte 3
The address programmed into this register is compared
with the incoming source address to generate a Source
Address Changed Interrupt. This is a 6-byte word. The
operation will abort if all 6 bytes are not written.
bit 31
MSB
bit 24
LSB
The counter is incremented by one each time this port
receives an error-free broadcast frame.
Last Source Address
Address: 1110 1110
D Port Read/Write
bit 7
bit 0
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
bit 40
LSB
bit 47
MSB
44
Am79C983A
P R E L I M I N A R Y
RAUI Port
SYSTEM APPLICATIONS
IMR2 to QuIET Connection
When the RAUI port is to be connected to a MAC, it
should be configured in reverse mode and connected
as shown in 9 (a). Notice that RDI is connected to DO
of the MAC and RDO is connected to DI. This is be-
cause the reverse configuration only affects RCI. 9 (b)
shows the normal AUI configuration for reference.
The IMR2 device provides a system solution to design-
ing repeaters. It can be used with the QuIET
transceivers to design 10BASE-T hubs or with other
types of MAUs for 10BASE2 or 10BASE-FL hubs. The
MAU types can be mixed to design a hub that supports
multiple media types. The IMR2 device connects di-
rectly to the QuIET device transceivers. 7 shows the
simplified connection. Three QuIET devices may be
connected to a single IMR2 device for 12 ports. Only
one connection is shown for simplicity.
PR Port Configuration
The PR port may be connected to the GPSI port of a
MAC. Communication with the MAC involves both the
PR port and the Expansion Bus.The PR port connects
to the receive side of the MAC and the expansion bus
connects to the transmit side.
Other Media
An example of the MAC connection is shown in 10.
Here the IMR2 device is connected to the SIA interface
of the Am79C90 (C-LANCE). MACEN, DAT, and ECLK
are bus signals. Therefore, the AND gates and buffers
to these signals must be open-collector or open-drain.
The OR gate for RENA satisfies the loopback require-
ments for the C-LANCE.
The IMR2 device, with some supporting circuitry, can be
connected to the AUI port of any MAU device. Thus, it
can support 10BASE2 and 10BASE-FL.The example in
8 shows a PAUI port connected to a 10BASE-FL trans-
ceiver (ml4663). For the ml4663, signals TX, RX, and
COL are equivalent to the AUI signals DO, DI, and CI.
The 360−Ω resistors are required by the ml4663 drivers.
MAC Interface
The IMR2 device can be connected to a MAC using either
the RAUI port or the PR port. The RAUI port supports a
direct connection.The PR port requires some glue logic.
Am79C983A
45
P R E L I M I N A R Y
IMR2
QuIET
TP Connector
TP Connector
TP Connector
TP Connector
TXD0+
110 Ω
100 Ω
PDO0
PDI0
PCI0
PDO0
PDI0
PCI0
TXD0-
RXD0+
RXD0-
TXD1+
TXD1-
110 Ω
100 Ω
PDO1
PDI1
PCI1
PDO1
PDI1
PCI1
RXD1+
RXD1-
TXD2+
TXD2-
110 Ω
100 Ω
PDO2
PDI2
PCI2
PDO2
PDI2
PCI2
RXD2+
RXD2-
TXD3+
TXD3-
110 Ω
100 Ω
PDO3
PDI3
PCI3
PDO3
PDI3
PCI3
RXD3+
RXD3-
AVDD
REXT
MCLK
RST
RST
CLK
13K Ω
Typical
19879B-11
Note: Common mode chokes may be required.
Figure 7. Simplified 10BASE-T Connection
46
Am79C983A
P R E L I M I N A R Y
Am79C983
ML4663
0.1 µF
PDO
TX+
TX–
16 KΩ
330 Ω
100 Ω
100 Ω
10K
10K
0.1 µF
PDI
RX+
RX–
78 Ω
360 Ω
360 Ω
10K
10K
0.1 µF
COL+
COL–
PCI
78 Ω
360 Ω
360 Ω
19879B-12
Figure 8. PAUI Interface to non-QuIET Device Transceiver
Am7996
Am79C940
Am79C983
Am79C983
DO+
DO–
RDI+
RDI–
RDI+
RDI–
DI+
DI–
40 Ω
40 Ω
40 Ω
40 Ω
DI+
DI–
RDO+
RDO–
RDO+
RDO–
DO+
DO–
0.1 µF
40 Ω
40 Ω
40 Ω
40 Ω
CI+
CI–
RCI+
RCI–
RCI+
RCI–
CI+
CI–
40 Ω
40 Ω
40 Ω
40 Ω
0.1 µF
39 Ω – 150 Ω
0.1 µF
0.1 µF 0.1 µF
0.1 µF
+9 V
b) Normal Mode (with MAU)
a) Reverse Mode (with MAC)
19879B-13
Figure 9. RAUI Port Interconnections
Am79C983A
47
P R E L I M I N A R Y
Am79C90 (C-LANCE)
CLSN
COL
JAM
RCLK
RX
PCLK
PDRV
PDAT
PENAI
PENAO
RENA
4.9 kΩ
+5 V
TENA
TX
MACEN
DAT
ECLK
TCL
Clock
Generator
19879B-14
Figure 10. PR Port Connection to an Am79C90 C-Lance
The other two IMR2 devices will have PAUI[0]
disabled with PDO[0] in a high impedance state. To
move port 0 to another backplane, the software will
disable PAUI[0] on the active IMR2 device and enable
PAUI[0] on the targeted IMR2 device that represents
the desired backplane. Pseudo AUI ports can be
disabled or enabled by setting the appropriate bit in
the Port Switching Control Register.
Port Switching
Port switching allows the movement of individual ports
between multiple Ethernet collision domains via soft-
ware. This capability enables the network manager to
optimize network performance by dynamically balanc-
ing the loads on a network. As an example, a port ex-
hibiting a high level of activity can be moved to a less
congested collision domain.
Although there are multiple IMR2 devices, only one has
management control of the QuIET devices. 11 shows
IMR2 device 0 having management control. The other
two devices do not have any control over the configura-
tion of the QuIET devices.
The method of implementing port switching with the
IMR2/QuIET chip set is to connect a single transceiver
port to multiple IMR2 devices.The number of IMR2 de-
vices will equal the number of backplanes supported in
the hub. 11 is a simplified schematic showing a hub
with three separate backplanes. Only one QuIET de-
vice is shown for simplicity, although it is expected that
most applications will use three QuIET devices to en-
able 12 port multiples.
The number of IMR2 devices that can be connected to-
gether is limited by the load on the PAUI drivers. The
PAUI will operate reliably with a load up to 100 pF. On
a system that uses sockets for the IMR2 devices, the
maximum number of devices is six.This number can in-
crease as long as the total load capacitance is kept
below 100 pF.
The following discussion of port switching will con-
sider only port 0; although, it is equally applicable to
all of the ports. At any time, PAUI[0] is enabled on one,
and only one, IMR2 device. As a result, port 0 is trans-
ferred to whichever IMR2 device has PAUI[0] enabled.
48
Am79C983A
P R E L I M I N A R Y
Backplane 0
PDO
PDI
PCI
PDO
PDI
PCI
TX
RX
Port 0
Port 1
Port 2
A
m
7
PDO
PDI
PCI
PDO
PDI
PCI
TX
RX
Am79C983
IMR2 0
PDO
PDI
PCI
PDO
PDI
PCI
TX
RX
9
PDO
PDI
PCI
PDO
PDI
PCI
TX
RX
Port 3
C
9
SDATA[0]
DIR[1]
SDATA
DIR
8
Backplane 1
8
PDO
PDI
PCI
PDO
PDI
PCI
Am79C983
IMR2 1
PDO
PDI
PCI
PDO
PDI
PCI
Backplane 2
PDO
PDI
PCI
PDO
PDI
PCI
Am79C983
IMR2 2
PDO
PDI
PCI
PDO
PDI
PCI
19879B-15
Figure 11. Port Switching Configuration
Am79C983A
49
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . .. –65°C to +150°C
Ambient Temperature Under Bias. . . . . . . . . 0 to 70°C
Supply Voltage referenced to
Commercial (C) Devices
Temperature (TA) . . . . . . . . . . . . . .0°C to + 70° C
Supply Voltages (VDD) . . . . . . . . . . . . . +5 V ±5%
Operating ranges define those limits between which the
functionality of the device is guaranteed.
AV or DV (AV , DV ) . . . . . . . . . . . . .–0.3 to +6V
SS
SS
DD
DD
Stresses above those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent device failure.
Functionality at or above these limits is not implied. Expo-
sure to Absolute Maximum Ratings for extended periods
may affect reliability. Programming conditions may differ.
DC CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Input LOW Voltage
Test Conditions
Min
Max
Unit
Digital I/O
V
-
-
-0.5
2.0
-
0.8
0.5+V
0.4
V
V
IL
IH
V
Input HIGH Voltage
DD
V
Output LOW Voltage
I
=4.0 mA
=-0.4 mA
V
OL
OH
OL
V
Output HIGH Voltage
Input Leakage Current
Open Drain Output LOW Voltage
I
2.4
-
-
V
OH
I
0<V <V
DD
10
µA
V
IL
IN
V
I
= 12 mA
-
0.4
OLOD
OLOD
(R)AUI Ports
I
Input Current at DI± and CI ±
V
<V <V
DD
-500
500
-1
µA
V
AIXD
SS
IN
V
DI±, CI± Open Circuit Input Voltage Range
Differential Mode Input Voltage Range
DI, CI Squelch Threshold
I
= 0
V
-3
V
AICM
IN
DD
DD
V
V
= 5.0V
-
-2
+2
V
AIDV
DD
V
-350
620
620
-160
1100
1100
mV
mV
mV
ASQ
V
Differential Output Voltage (DO+) -(DO)
R = 78Ω
L
AOD
V
Differential Output Voltage (RCI+)-(RCI-)
(Reverse Mode)
R = 39Ω
L
AOC
V
DO Differential Output Voltage Imbalance
R = 78Ω
-25
-40
+25
+40
mV
mV
µA
V
AODI
L
V
OFF DO Differential Idle Output Voltage
R = 78Ω
L
AOD
I
OFF DO Differential Idle Output Current
R = 78Ω (Note 1)
-525
2.5
+525
AOD
L
V
DO+, DO- Output Voltage
R = 78Ω
V
DD
AOCM
L
PAUI Ports
V
V
Idle Voltage
-
V
/2-10%
V /2+10%
DD
mV
mV
mV
mV
V
IDLE
POH
DD
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
-
V
+ 0.45
IDLE
V
-
V
-0.45
POL
IDLE
V
(Note 1)
(Note 1)
V
+ 0.45
- 0.45
PIH
IDLE
V
V
IDLE
PIL
PIL
I
V
= MAX
-
10
µA
mV
DD
v
PDI & PCI Squelch (the value PDI & PCI must
go to before internal PDI & PCI carrier sense
can be turned on) (Note 11)
V
-550
V
-350
PASQ
IDLE
IDLE
Power Supply Current
I
Power Supply Current (Idle)
MCLK = 20 MHz
= +5.25V
-
-
300
mA
mA
DD
V
DD
Power Supply Current (Transmitting)
MCLK = 20 MHz
= +5.25V
450
V
DD
50
Am79C983A
P R E L I M I N A R Y
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
Clock and Reset Timing
tMCLK
tMCLKH
tMCLKL
tMCLKR
tMCLKF
tECLKH
tECLKL
tECRR
tECRF
tECTR
tECTF
MCLK Clock Period
49.995
50.005
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
MCLK Clock HIGH
20
30
MCLK Clock LOW
20
30
MCLK Rise Time
-
10
MCLK Fall Time
-
10
ECLK HIGH
(Note 2)
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
0.4 tECLK
0.6 tECLK
ECLK LOW
0.4 tECLK
0.6 tECLK
ECLK Rise Time (When Receiving DAT)
ECLK Fall Time (When Receiving DAT)
ECLK Rise Time (When Transmitting DAT)
ECLK Fall Time (When Transmitting DAT)
Reset Pulse Width
-
-
10
10
10
10
-
-
-
tRST
4
tRSTP
Reset Pulse Width on Power-Up
150
20
0
-
tRSTSET Reset Input SetupTime with respect to MCLK
tRSTHLD Reset Input Hold Time with respect to MCLK
(R)AUI Port Timing
-
-
tDOTD
tDOTR
MCLK HIGH to DO Toggle
DO Rise Time
-
-
30
7.0
7.0
1.0
375
45
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
tDOTF
tDORM
tDOETD
tPWODI
DO Fall Time
-
DO+, DO- Rise and Fall Time Mismatch
DO End Of Transmission
DI Pulse Width Accept/Reject
-
275
15
|V |>|V
|
|
|
|
IN
ASQ
ASQ
ASQ
ASQ
(Note 3)
tPWKDI
tPWOCI
tPWKCI
DI PulseWidth Not toTurn Off Internal Carrier
Sense
|V |>|V
136
8
220
26
ns
ns
ns
IN
(Note 4)
CI Pulse Width Accept/Reject Threshold
|V |>|V
IN
(Note 5)
CI Pulse Width Not to Turn Off Threshold
|V |>|V
80
160
IN
(Note 6)
tCITR
tCITF
tCIRM
RCI Rise Time (in Reverse Mode)
RCI Fall Time (In Reverse Mode)
(Note 1)
(Note 1)
-
-
-
7.0
7.0
1.0
ns
ns
ns
RCI+, RCI- Rise and Fall Time Mismatch
(RAUI in Reverse Mode)
PAUI Port Timing
tPDOTD
MCLK HIGH to DO Toggle
-
30
375
45
ns
ns
ns
ns
tPDOETD PDO End of Transmission
tPWOPDI PDI Pulse Width Accept/Reject (Note 7)
(Note 1)
275
15
|V |>|V
|
|
IN
ASQ
tPWKPDI DI PulseWidth Not toTurn Off Internal Carrier
Sense (Note 8)
|V |>|V
136
220
IN
ASQ
tPWOPCI CI Pulse Width Accept/Reject Threshold
(Note 9)
|V |>|V
|
|
8
26
ns
ns
IN
ASQ
ASQ
tPWKPCI CI Pulse Width Not to Turn Off Threshold
(Note 10)
|V |>|V
80
160
IN
Expansion Bus Timing
tMHRL
tMHRH
MCLK HIGH to REQ Driven LOW
MCLK HIGH TO REQ Driven HIGH
C =100pF
10
10
40
40
ns
ns
L
C =100pF
L
Am79C983A
51
P R E L I M I N A R Y
Test Conditions
Parameter
Symbol
Parameter Description
MCLK HIGH to DAT/JAM Driven
MCLK HIGH TO DAT/JAM Not Driven
DAT/JAM Setup Time to MCLK
Min
10
14
10
10
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tMHDR
tMHDZ
C =100pF
40
40
-
L
C =100pF
L
tMDSET
tMDHOLD DAT/JAM Hold Time from MCLK
-
tMASET
tMAHLD
tELDR
COL/ACK Setup Time to MCLK
COL/ACK Hold Time to MCLK
ECLK LOW to DAT Switching
DAT Setup to ECLK
-
14
-
-
C =100pF
20
-
L
tEDSET
10
14
tEDHOLD DAT Hold Time from ECLK
-
Microprocessor Interface Timing
tCDS
tCDH
tCSS
C/D Setup Time with Respect to RD/WR
Leading Edge
10
0
-
-
-
ns
ns
ns
C/DHoldTimewithRespecttoRD/WRRising
Edge
CS Setup Time with Respect to RD/WR Fall-
ing Edge
10
tCSH
tRDYD
tRDYH
tDOUT
tDOH
tDIS
CS Hold Time with Respect to RD/WR Rising
RDY Leading Edge Delay
0
-
-
25
-
ns
ns
ns
ns
ns
ns
C =100pF
L
RDY HIGH to RD/WR Rising
Data Out to RDY HIGH
0
C =100pF
50
10
25
-
L
Data Out HOLD after RD HIGH
C =100pF
50
-
L
Data In Setup Time with Respect to WR Ris-
ing Edge
tREST
Rest Period between MPI Operations (Time
betweentheEarliestCS/RD/WRGoingHIGH
to the Next CS/RD/WR Going LOW, whichev-
er is the Latest
150
-
ns
tDIH
Data In HOLD after WR HIGH
0
-
ns
Management Port Timing
tMSSO
tMSDO
MCLK to SDATA
MCLK to DIR[1:0]
SDATA Setup Time
SDATA Hold Time
10
10
10
10
40
40
-
ns
ns
ns
ns
tMSSSU
tMSSHD
-
Packet Report Port Timing
tPRV PCLK LOW to PDAT Switching
-
20
ns
Notes:
1. Parameter is not tested.
2. ECLK is dependent on the frequency of the data on the active port.
3. (R)DI pulses narrower than tPWODI (min) will be rejected; (R)DI pulses wider than tPWODI (max) will turn internal (R)DI car-
rier sense on.
4. (R)DI pulses narrower than tPWKDI (min) will maintain internal (R)DI carrier sense on; (R)DI pulses wider than tPWKDI(max)
will turn internal (R)DI carrier sense off.
5. (R)CI pulses narrower than tPWOCI (min) will be rejected; (R)CI pulses wider than tPWOCI (max) will turn internal (R)CI car-
rier sense on.
6. (R)CI pulses narrower than tPWKCI (min) will maintain internal (R)CI carrier sense; (R)CI pulses longer than tPWKCI (max)
will turn internal (R)CI carrier sense off.
7. PDI pulses narrower than tPWOPDI (min) will be rejected; PDI pulses wider than tPWOPDI (max) will turn internal PDI carrier
sense on.
52
Am79C983A
P R E L I M I N A R Y
8. PDI pulses narrower than tPWKPDI (min) will maintain internal PDI carrier sense on; PDI pulses wider than tPWKPDI (max)
will turn internal PDI carrier sense off.
9. PCI pulses narrower than tPWOPCI (min) will be rejected; PCI pulses wider than tPWOPCI (max) will turn internal PCI carrier
sense on.
10. PCI pulses narrower than tPWKPCI (min) will maintain internal PCI carrier sense on; PCI pulses wider than tPWKPCI (max)
will turn internal PCI carrier sense off.
11. Squelch thresholds change proportionately with V
.
DD
Am79C983A
53
P R E L I M I N A R Y
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS00010
SWITCHING WAVEFORMS
tMCLK
tMCLKH
tMCLKL
19879B-16
Figure 12. Master Clock (MCLK) Timing
tECLK
tECLKH
tECLKL
Figure 13. Expansion Bus Asynchronous Clock (ECLK) Timing
19879B-17
54
Am79C983A
P R E L I M I N A R Y
SWITCHING WAVEFORMS
MCLK
TCLK*
REQ
ACK
COL
tMDSET
tMDHOLD
IN
DAT/JAM
19879B-18
*TCLK illustrates internal IMR2 chip clock phase relationships
Figure 14. Expansion Bus Input Timing - Synchronous Mode
MCLK
TCLK*
tMHRH
tMHRL
REQ
ACK
COL
REQ
tMASET
tMASET
ACK
COL
tMAHLD
tMHDZ
tMHDR
DAT/JAM
OUT
*TCLK illustrates internal IMR2 chip clock phrase relationships
Figure 15. Expansion Bus Output Timing - Synchronous Mode
19879B-19
Am79C983A
55
P R E L I M I N A R Y
SWITCHING WAVEFORMS
MCLK
TCLK*
tMHRH
REQ
tMASET
tMHRL
ACK
COL
tMASET
tMAHLD
DAT/JAM
*TCLK illustrates internal IMR2 chip clock phrase relationships
19879B-20
Figure 16. Expansion Port Collision Timing - Synchronous Mode
PCLK
tDPRV
PDAT
PENAO
19879B-21
Figure 17. Packet Report Port Timing
ECLK
REQ
ACK
COL
tEDSET
tEDHOLD
IN
DAT
19879B-22
Figure 18. Expansion Port Input Timing - Asynchronous Mode
Am79C983A
56
P R E L I M I N A R Y
SWITCHING WAVEFORMS
ECLK
REQ
ACK
COL
DAT
tELDR
19879B-23
Figure 19. Expansion Port Output Timing - Asynchronous Mode
MCLK
PDO
tPDOTD
19879B-24
Figure 20. PAUI PDO Transmit
tPWKPCI
PCI
VASQ
tPWKPCI
tPWOPCI
19879B-25
Figure 21. PAUI PCI Receive
Am79C983A
57
P R E L I M I N A R Y
SWITCHING WAVEFORMS
tPWKPDI
PDI
VASQ
tPWKPDI
tPWOPDI
19879B-26
Figure 22. PAUI Receive
MCLK
DO+
tDOETD
tDOTD
tDOTR
tDOTF
DO–
19879B-27
Figure 23. (R)AUI Timing
tPWKDI
DI±
or
RDI±
VASQ
tPWKDI
tPWODI
19879B-28
Figure 24. (R)AUI Receive
58
Am79C983A
P R E L I M I N A R Y
SWITCHING WAVEFORMS
C/D
tCDS
tCDH
CS
tREST
tCSH
tCSS
RD, WR
tRDYD
tREST
tRDYH
RDY
tDOH
tDOUT
D7–0
D7–0
Read Data
tDIS
tDIH
Write Data
19879B-29
Figure 25. Microprocessor Bus Interface Timing
Am79C983A
59
P R E L I M I N A R Y
PHYSICAL DIMENSIONS*
PQB 132
132-Pin Plastic Quad Flat Pack (Measured in inches)
1.097
1.103
1.075
1.085
0.947
0.953
Pin 132
Pin 99
Pin 1 I.D.
0.947
0.953
1.075
1.085
1.097
1.103
Pin 33
Pin 66
0.008
0.012
TOP VIEW
0.025 BASIC
0.130
0.150
0.160
0.180
SEATING
PLANE
0.80 REF
BOTTOM VIEW
0.020
0.040
16-038-PQB
PQB132
DB87
7-26-94 ae
REVISION SUMMARY
This revision (B) reflects changes to Figures 4, 7, and
8. Changes have also been made to the Ordering
Information page, DC Characteristics and Switching
Characteristics tables. Also, the Table of Contents has
been moved to page 7. No other technical changes
have been made.
Trademarks
Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof, and IMR2, QuIET, HIMIB, PAUI, and RAUI are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
60
Am79C983A
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