AMD27C64-255DC [AMD]
64 Kilobit (8,192 x 8-Bit) CMOS EPROM; 64千位（ 8,192 ×8位） CMOS EPROM
| 型号： | AMD27C64-255DC |
| 厂家： | 
AMD |
| 描述： | 64 Kilobit (8,192 x 8-Bit) CMOS EPROM |
| 文件： | 总11页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Advanced
Micro
Am27C64
64 Kilobit (8,192 x 8-Bit) CMOS EPROM
Devices
DISTINCTIVE CHARACTERISTICS
■ Fast access time
■ Latch-up protected to 100 mA from –1 V to
VCC + 1 V
— 45 ns
■ High noise immunity
■ Low power consumption
— 20 µA typical CMOS standby current
■ JEDEC-approved pinout
■ Versatile features for simple interfacing
— Both CMOS and TTL input/output
compatibility
■ Single +5 V power supply
■ ±10% power supply tolerance available
■ 100% FlashriteTM programming
— Typical programming time of 1 second
— Two line control functions
■ Standard 28-pin DIP, PDIP, and 32-pin PLCC
packages
GENERAL DESCRIPTION
The Am27C64 is a 64-Kbit ultraviolet erasable program-
mable read-only memory. It is organized as 8K words by
8 bits per word, operates from a single +5 V supply, has
a static standby mode, and features fast single address
location programming. Products are available in win-
dowed ceramic DIP packages as well as plastic one
time programmable (OTP) PDIP, and PLCC packages.
controls, thus eliminating bus contention in a multiple
bus microprocessor system.
AMD’s CMOS process technology provides high speed,
low power, and high noise immunity. Typical power con-
sumption is only 80 mW in active mode, and 100 µW in
standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in blocks,
or at random. The Am27C64 supports AMD’s Flashrite
programming algorithm (100 µs pulses) resulting in a
typical programming time of 1 second.
Typically, any byte can be accessed in less than 45 ns,
allowing operation with high-performance microproces-
sors without any WAIT states. The Am27C64 offers
separate Output Enable (OE) and Chip Enable (CE)
BLOCK DIAGRAM
Data Outputs
DQ0–DQ7
VCC
VSS
VPP
OE
CE
Output Enable
Chip Enable
and
Output
Buffers
Prog Logic
PGM
Y
Y
Decoder
Gating
A0–A12
Address
Inputs
65,538
Bit Cell
Matrix
X
Decoder
11419D-1
Publication# 11419 Rev. D Amendment/0
Issue Date: May 1995
2-10
AMD
PRODUCT SELECTOR GUIDE
Family Part No.
Am27C64
Ordering Part No:
VCC ± 5%
-255
V
CC ± 10%
-45
45
45
30
-55
55
55
35
-70
70
70
40
-90
90
90
40
-120
-150
150
150
50
-200
200
200
50
Max Access Time (ns)
CE (E) Access Time (ns)
OE (G) Access Time (ns)
120
120
50
250
250
50
CONNECTION DIAGRAMS
Top View
DIP
PLCC
1
2
3
4
5
6
28
27
26
25
24
23
VPP
A12
A7
VCC
PGM (P)
NC
4
3 2 1 32 31 30
A6
A5
A4
A3
A8
A6
A5
A4
A3
A2
A1
A0
NC
A8
A9
5
29
28
A9
6
A11
7
27 A11
NC
7
8
22
21
OE (G)
A10
8
26
A2
A1
9
25 OE (G)
9
20
19
18
17
16
15
CE (E)
DQ7
24 A10
10
11
12
13
10
11
12
13
14
A0
DQ0
DQ1
DQ2
23
22
21
CE (E)
DQ7
DQ6
DQ5
DQ4
DQ3
DQ6
DQ0
14 15 16 17 18 19 20
VSS
11419D-2
11419D-3
Notes:
1. JEDEC nomenclature is in parentheses.
LOGIC SYMBOL
PIN DESIGNATIONS
A0–A12
CE (E)
DQ0–DQ7
OE (G)
PGM (P)
VCC
=
=
=
=
=
=
=
Address Inputs
13
Chip Enable
A0–A12
Data Inputs/Outputs
Output Enable Input
Program Enable Input
VCC Supply Voltage
Program Voltage Input
Ground
8
DQ0–DQ7
CE (E)
VPP
PGM (P)
OE (G)
VSS
=
=
=
NC
No Internal Connection
DU
No External Connection (Don’t Use)
11419D-4
2-11
Am27C64
AMD
ORDERING INFORMATION
UV EPROM Products
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM27C64
-45
D
C
B
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I
= Industrial (–40°C to +85°C)
E = Extended Commercial (–55°C to +125°C)
PACKAGE TYPE
D = 28-Pin Ceramic DIP (CDV028)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER
Am27C64
64 Kilobit (8,192 x 8-Bit) CMOS UV EPROM
Valid Combinations
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
AM27C64-45
DC, DCB, DI, DIB
AM27C64-55
AM27C64-70
AM27C64-90
AM27C64-120
AM27C64-150
AM27C64-200
AM27C64-255
DC, DCB, DI,
DIB, DE, DEB
DC, DCB, DI, DIB
2-12
Am27C64
AMD
ORDERING INFORMATION
OTP Products
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM27C64
-55
P
C
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I
= Industrial (–40°C to + 85°C)
E = Extended Commercial (–55°C to +125°C)
PACKAGE TYPE
P = 28-Pin Plastic DIP (PD 028)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER
Am27C64
64 Kilobit (8,192 x 8-Bit) CMOS OTP EPROM
Valid Combinations
Valid Combinations
AM27C64-55
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combination.
AM27C64-70
AM27C64-90
AM27C64-120
AM27C64-150
AM27C64-200
AM27C64-255
JC, PC,
JI, PI
2-13
Am27C64
AMD
FUNCTIONAL DESCRIPTION
Erasing the Am27C64
PGM input with VPP = 12.75 V ± 0.25 V and CE Low will
program that Am27C64. A high-level CE input inhibits
the other Am27C64 devices from being programmed.
In order to clear all locations of their programmed con-
tents, it is necessary to expose the Am27C64 to an
ultravioletlightsource. Adosageof15Wseconds/cm2is
required to completely erase an Am27C64. This dosage
can be obtained by exposure to an ultraviolet lamp—
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with OE and CE at VIL , PGM
at VIH, and VPP between 12.5 V and 13.0 V.
2
°
A
wavelength of 2537 —with intensity of 12,000 µW/cm
for 15 to 20 minutes. The Am27C64 should be directly
under and about one inch from the source and all filters
should be removed from the UV light source prior
to erasure.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
andtype. Thismodeisintendedforusebyprogramming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25°C ± 5°C ambient temperature range that is required
when programming the Am27C64.
It is important to note that the Am27C64 and similar
deviceswillerasewithlightsourceshavingwavelengths
°
A
shorter than 4000 . Although erasure times will be
°
A
much longer than with UV sources at 2537 , exposure
to fluorescent light and sunlight will eventually erase the
Am27C64 and exposure to them should be prevented to
realize maximum system reliability. If used in such an
environment, the package window should be covered
by an opaque label or substance.
To activate this mode, the programming equipment
must force 12.0 V ± 0.5 V on address line A9 of the
Am27C64. Two identifier bytes may then be sequenced
from the device outputs by toggling address line A0 from
VIL to VIH. All other address lines must be held at VIL dur-
ing auto select mode.
Programming the Am27C64
Upon delivery or after each erasure the Am27C64
has all 65,536 bits in the “ONE” or HIGH state. “ZEROs”
are loaded into the Am27C64 through the procedure
of programming.
Byte 0 (A0 = VIL) represents the manufacturer code, and
byte 1 (A0 = VIH), the device code. For the Am27C64,
these two identifier bytes are given in the Mode Select
Table. All identifiers for manufacturer and device codes
will possess odd parity, with the MSB (DQ7) defined as
the parity bit.
The programming mode is entered when 12.75 V ±
0.25 V is applied to the VPP pin, CE is at VIL and PGM is
at VIL.
For programming, the data to be programmed is applied
8 bits in parallel to the data output pins.
Read Mode
The Flashrite algorithm reduces programming time by
using 100 µs programming pulses and by giving each
address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to
a given address, the data in that address is verified. If
the data does not verify, additional pulses are given until
it verifies or the maximum is reached. This process is
repeated while sequencing through each address of the
Am27C64. This part of the algorithm is done at
VCC = 6.25 V to assure that each EPROM bit is pro-
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem-
ory is verified at VCC = VPP = 5.25 V.
The Am27C64 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
shouldbeusedfordeviceselection. OutputEnable(OE)
is the output control and should be used to gate data to
the output pins, independent of device selection. As-
suming that addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data
is available at the outputs tOE after the falling edge of
OE, assuming that CE has been LOW and addresses
have been stable for at least tACC–tOE.
Standby Mode
Please refer to Section 6 for programming flow chart
and characteristics.
The Am27C64 has a CMOS standby mode which re-
duces the maximum VCC current to 100µA. It is placed in
CMOS-standby when CE is at VCC ± 0.3 V. The
Am27C64 also has a TTL-standby mode which reduces
the maximum VCC current to 1.0 mA. It is placed in
TTL-standby when CE is at VIH. When in standby mode,
the outputs are in a high-impedance state, independent
of the OE input.
Program Inhibit
Programming of multiple Am27C64 in parallel with dif-
ferent data is also easily accomplished. Except for CE,
all like inputs of the parallel Am27C64 may be common.
A TTL low-level program pulse applied to an Am27C64
2-14
Am27C64
AMD
Output OR-Tieing
System Applications
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1-µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive ef-
fects of the printed circuit board traces on EPROM ar-
rays, a 4.7-µF bulk electrolytic capacitor should be used
between VCC and VSS for each eight devices. The loca-
tion of the capacitor should be close to where the power
supply is connected to the array.
■ Low memory power dissipation
■ Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and con-
nected to the READ line from the system control bus.
This assures that all deselected memory devices are in
low-power standby mode and that the output pins are
only active when data is desired from a particular
memory device.
MODE SELECT TABLE
Pins
CE
VIL
OE
PGM
X
A0
X
A9
X
VPP
X
Outputs
DOUT
Mode
Read
VIL
VIH
X
Output Disable
Standby (TTL)
Standby (CMOS)
Program
X
X
X
X
X
High-Z
High-Z
High-Z
DIN
VIH
X
X
X
X
V
CC ± 0.3 V
X
X
X
X
X
VIL
X
VIL
VIH
X
X
X
VPP
VPP
VPP
Program Verify
Program Inhibit
VIL
VIL
X
X
X
DOUT
VIH
X
X
High-Z
Manufacturer
Code
Auto Select
(Note 3)
VIL
VIL
VIL
VIL
X
X
VIL
VIH
VH
VH
X
X
01H
15H
Device Code
Notes:
1. VH = 12.0 V ± 0.5 V
2. X = Either VIH or VIL
3. A1–A8 = A10–A12 = VIL
4. See DC Programming Characteristics for VPP voltage during programming.
2-15
Am27C64
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
OTP Products . . . . . . . . . . . . . . . –65°C to +125°C
All Other Products . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (TA) . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Ambient Temperature (TA) . . . . . –40°C to +85°C
Extended Commercial (E) Devices
Voltage with Respect To VSS
Ambient Temperature (TA) . . . . –55°C to +125°C
All pins except A9,VPP,VCC . –0.6 V to VCC + 0.5 V
Supply Read Voltages
A9 and VPP . . . . . . . . . . . . . . . . –0.6 V to +13.5 V
VCC . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to +7.0 V
VCC for Am27C64-XX5 . . . . . . +4.75 V to +5.25 V
VCC for Am27C64-XX0 . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
transitions, the inputs may overshoot VSS to –2.0 V for pe-
riods of up to 20 ns. Maximum DC voltage on input and I/O
pins is VCC + 0.5 V which may overshoot to VCC + 2.0 V for
periods up to 20ns.
2. For A9 and VPP the minimum DC input is –0.5 V. During
transitions, A9 and VPP may overshoot VSS to –2.0 V for
periods of up to 20 ns. A9 and VPPmust not exceed 13.5 V
for any period of time.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2-16
Am27C64
AMD
DC CHARACTERISTICS over operating range unless otherwise specified.
(Notes 1, 2, 3 and 4)
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –400 µA
2.4
V
V
VOL
VIH
VIL
ILI
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
IOL = 2.1 mA
0.45
VCC + 0.5
+0.8
2.0
V
–0.5
V
VIN = 0 V to VCC
1.0
µA
ILO
VOUT = 0 V to VCC
C/I Devices
E Devices
1.0
5.0
µA
ICC1
VCC Active Current
(Note 3)
CE = VIL, f = 10 MHz,
25
mA
I
OUT = 0 mA
ICC2
ICC3
IPP1
VCC TTL Standby Current
CE = VIH
1
mA
µA
µA
VCC CMOS Standby Current CE = VCC ± 0.3 V
VPP Current During Read CE = OE = VIL, VPP = VCC
100
100
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. Caution: The Am27C64 must not be removed from (or inserted into) a socket when VCC or VPP is applied.
3. ICC1 is tested with OE = VIH to simulate open outputs.
4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.
30
25
20
15
10
30
25
20
15
10
1
2
3
4
5
6
7
8
9
10
–75 –50 –25
0
25 50 75 100 125 150
Frequency in MHz
Temperature in °C
Figure 1. Typical Supply Current
vs. Frequency
Figure 2. Typical Supply Current
vs. Temperature
VCC = 5.5 V, T = 25°C
VCC = 5.5 V, f = 10 MHz
11419D-5
11419D-6
2-17
Am27C64
AMD
CAPACITANCE
Parameter
CDV028
PL 032
PD 028
Test
Symbol
Parameter Description
Conditions
Typ Max Typ Max Typ Max
Unit
pF
CIN
Input Capacitance
Output Capacitance
VIN = 0
8
10
14
6
8
10
12
5
8
10
10
COUT
VOUT = 0
11
pF
Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25°C, f = 1 MHz.
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
(Notes 1, 3 and 4)
Parameter
Symbols
Am27C64
Parameter
Test
JEDEC Standard Description
Conditions
-45 -55
-70
-90 -120 -150 -200 -255 Unit
tAVQV
tACC
Address to
CE = OE = Min
–
–
–
–
–
–
–
–
Output Delay
VIL
Max 45
Min
Max 45
Min
Max 30
Min
Max 25
55
70
90 120 150 200 250
ns
ns
ns
tELQV
tGLQV
tCE
tOE
Chip Enable to
Output Delay
OE = VIL
–
–
55
–
70
–
–
–
–
–
90 120 150 200 250
Output Enable to
Output Delay
CE = VIL
–
–
35
–
40
–
–
–
–
–
40
50
50
50
50
tEHQZ
tGHQZ
tDF
–
–
–
–
–
–
–
–
Chip Enable HIGH or
Output Enable HIGH,
whichever comes
(Note 2)
25
25
25
30
30
30
30
ns
first, to Output Float
tAXQX
tOH
Output Hold from
Addresses, CE, orOE,
whicheveroccurredfirst
Min
Max
0
–
0
–
0
–
0
–
0
–
0
–
0
–
0
–
ns
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is only sampled and not 100% tested.
3. Caution: The Am27C64 must not be removed from (or inserted into) a socket or board when VPP or VCC is applied.
4. For the -45, -55 and -70:
Output Load: 1 TTL gate and CL = 30 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level: 1.5 V for inputs and outputs
For all other versions:
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs
2-18
Am27C64
AMD
SWITCHING TEST CIRCUIT
2.7 kΩ
Device
Under
Test
+5.0 V
Diodes = IN3064
or Equivalent
CL
6.2 kΩ
CL = 100 pF including jig capacitance (30 pF for -45, -55, -70)
11419D-7
SWITCHING TEST WAVEFORM
2.4 V
3 V
0 V
2.0 V
0.8 V
2.0 V
0.8 V
Test Points
Test Points
1.5 V
Input
1.5 V
Output
0.45 V
Input
Output
11419D-8
AC Testing: Inputs are driven at 2.4 V for a logic “1”
and 0.45 V for a logic “0”. Input pulse
rise and fall times are ≤ 20 ns.
AC Testing: Inputs are driven at 3.0 V for a logic “1”
and 0 V for a logic “0”. Input pulse rise and
fall times are ≤ 20 ns for -45, -55 and -70.
2-19
Am27C64
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center
Line is High
Impedence
“Off” State
KS000010
SWITCHING WAVEFORMS
2.4
Addresses
0.45
2.0
0.8
2.0
0.8
Addresses Valid
CE
OE
tCE
tDF
(Note 2)
tOE
tACC
(Note 1)
tOH
High Z
Output
High Z
Valid Output
Notes:
11419D-9
1. OE may be delayed up to tACC–tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE or CE, whichever occurs first.
2-20
Am27C64
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