L256MH123RF_技术文档

Am29LV256M

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not available for designs. For new and current designs,

S29GL256N supersedes Am29LV256M and is the factory-recommended migration path. Please refer

to the S29GL256N datasheet for specifications and ordering information. Availability of this docu-

ment is retained for reference and historical purposes only.

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 25263 Revision C Amendment +6 Issue Date December 16, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29LV256M

256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBit^TM3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O^TMControl

This product has been retired and is not available for designs. For new and current designs, S29GL256N supersedes Am29LV256M and is the factory-recommended

migration path. Please refer to the S29GL256N datasheet for specifications and ordering information. Availability of this document is retained for reference and his-

torical purposes only.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

— 4-word/8-byte page read buffer

— 16-word/32-byte write buffer

Single power supply operation

— 3 volt read, erase, and program operations

Low power consumption (typical values at 3.0 V, 5

VersatileI/O^TMcontrol

MHz)

— 13 mA typical active read current

— 50 mA typical erase/program current

— 1 µA typical standby mode current

— Device generates data output voltages and tolerates

data input voltages on the CE# and DQ inputs/outputs

as determined by the voltage on the V_IOpin; operates

from 1.65 to 3.6 V

Package options

— 56-pin TSOP

Manufactured on 0.23 µm MirrorBit process

technology

SecSi^TM(Secured Silicon) Sector region

— 64-ball Fortified BGA

SOFTWARE & HARDWARE FEATURES

— 128-word/256-byte sector for permanent, secure

identification through an 8-word/16-byte random

Electronic Serial Number, accessible through a

command sequence

Software features

— Program Suspend & Resume: read other sectors

before programming operation is completed

— May be programmed and locked at the factory or by

the customer

— Erase Suspend & Resume: read/program other

sectors before an erase operation is completed

— Data# polling & toggle bits provide status

Flexible sector architecture

— Unlock Bypass Program command reduces overall

multiple-word or byte programming time

— Five hundred twelve 32 Kword (64 Kbyte) sectors

Compatibility with JEDEC standards

— CFI (Common Flash Interface) compliant: allows host

system to identify and accommodate multiple flash

devices

— Provides pinout and software compatibility for

single-power supply flash, and superior inadvertent

write protection

Hardware features

Minimum 100,000 erase cycle guarantee per sector

20-year data retention at 125°C

— Sector Group Protection: hardware-level method of

preventing write operations within a sector group

— Temporary Sector Group Unprotect: V_ID-level method

of changing code in locked sector groups

PERFORMANCE CHARACTERISTICS

High performance

— WP#/ACC input accelerates programming time

(when high voltage is applied) for greater throughput

during system production. Protects first or last sector

regardless of sector protection settings

— 100 ns access time

— 30 ns page read times

— 0.5 s typical sector erase time

— 15 µs typical effective write buffer word programming

time: 16-word/32-byte write buffer reduces overall

programming time for multiple-word updates

— Hardware reset input (RESET#) resets device

— Ready/Busy# output (RY/BY#) detects program or

erase cycle completion

Publication# 25263 Rev: C Amendment/+6

Issue Date: December 16, 2005

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

D A T A S H E E T

GENERAL DESCRIPTION

The Am29LV256M is a 256 Mbit, 3.0 volt single power

supply flash memory devices organized as 16,777,216

words or 33,554,432 bytes. The device has a 16-bit

wide data bus that can also function as an 8-bit wide

data bus by using the BYTE# input. The device can be

programmed either in the host system or in standard

EPROM programmers.

and tolerates on the CE# control input and DQ I/Os to

the same voltage level that is asserted on the V_IOpin.

Refer to the Ordering Information section for valid V_IO

options.

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

group protection feature disables both program and

erase operations in any combination of sector groups

of memory. This can be achieved in-system or via pro-

gramming equipment.

An access time of 100, 110, or 120 ns is available.

Note that each access time has a specific operating

voltage range (V_CC) and an I/O voltage range (V_IO), as

specified in the Product Selector Guide and the Order-

ing Information sections. The device is offered in a

56-pin TSOP or Fortified BGA package. Each device

has separate chip enable (CE#), write enable (WE#)

and output enable (OE#) controls.

The Erase Suspend/Erase Resume feature allows

the host system to pause an erase operation in a given

sector to read or program any other sector and then

complete the erase operation. The Program Sus-

pend/Program Resume feature enables the host sys-

tem to pause a program operation in a given sector to

read any other sector and then complete the program

operation.

Each device requires only a single 3.0 volt power

supply for both read and write functions. In addition to

a V_CCinput, a high-voltage accelerated program

(WP#/ACC) input provides shorter programming times

through increased current. This feature is intended to

facilitate factory throughput during system production,

but may also be used in the field if desired.

The hardware RESET# pin terminates any operation

in progress and resets the device, after which it is then

ready for a new operation. The RESET# pin may be

tied to the system reset circuitry. A system reset would

thus also reset the device, enabling the host system to

read boot-up firmware from the Flash memory device.

The device is entirely command set compatible with

the JEDEC single-power-supply Flash standard.

Commands are written to the device using standard

microprocessor write timing. Write cycles also inter-

nally latch addresses and data needed for the pro-

gramming and erase operations.

The device reduces power consumption in the

standby mode when it detects specific voltage levels

on CE# and RESET#, or when addresses have been

stable for a specified period of time.

The SecSi^TM(Secured Silicon) Sector provides a

128-word/256-byte area for code or data that can be

permanently protected. Once this sector is protected,

no further changes within the sector can occur.

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Device programming and erasure are initiated through

command sequences. Once a program or erase oper-

ation has begun, the host system need only poll the

DQ7 (Data# Polling) or DQ6 (toggle) status bits or

monitor the Ready/Busy# (RY/BY#) output to deter-

mine whether the operation is complete. To facilitate

programming, an Unlock Bypass mode reduces com-

mand sequence overhead by requiring only two write

cycles to program data instead of four.

The Write Protect (WP#/ACC) feature protects the

first or last sector by asserting a logic low on the WP#

pin.

AMD MirrorBit flash technology combines years of

Flash memory manufacturing experience to produce

the highest levels of quality, reliability and cost effec-

tiveness. The device electrically erases all bits within a

sector simultaneously via hot-hole assisted erase. The

data is programmed using hot electron injection.

The VersatileI/O™ (V_IO) control allows the host sys-

tem to set the voltage levels that the device generates

RELATED DOCUMENTS

For a comprehensive information on MirrorBit prod-

ucts, including migration information, data sheets, ap-

plication notes, and software drivers, please see

www.amd.com→Flash Memory→Product Informa-

tion→MirrorBit→Flash Information→Technical Docu-

mentation. The following is a partial list of documents

closely related to this product:

MirrorBit™ Flash Memory Write Buffer Programming

and Page Buffer Read

Implementing a Common Layout for AMD MirrorBit

and Intel StrataFlash Memory Devices

Migrating from Single-byte to Three-byte Device IDs

2

Am29LV256M

December 16, 2005

D A T A S H E E T

TABLE OF CONTENTS

Table 10. Erase Operation............................................................. 39

Erase Suspend/Erase Resume Commands ........................... 39

Command Definitions ............................................................. 40

Table 11. Command Definitions (x16 Mode, BYTE# = V_IH) ........... 40

Table 12. Command Definitions (x8 Mode, BYTE# = V_IL).............. 41

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 42

DQ7: Data# Polling ................................................................. 42

Figure 7. Data# Polling Algorithm .................................................. 42

RY/BY#: Ready/Busy# ............................................................ 43

DQ6: Toggle Bit I .................................................................... 43

Figure 8. Toggle Bit Algorithm ........................................................ 44

DQ2: Toggle Bit II ................................................................... 44

Reading Toggle Bits DQ6/DQ2 ............................................... 44

DQ5: Exceeded Timing Limits ................................................ 45

DQ3: Sector Erase Timer ....................................................... 45

DQ1: Write-to-Buffer Abort ..................................................... 45

Table 13. Write Operation Status................................................... 45

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 46

Figure 9. Maximum Negative Overshoot Waveform ..................... 46

Figure 10. Maximum Positive Overshoot Waveform ..................... 46

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 46

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 11. Test Setup ..................................................................... 48

Table 14. Test Specifications......................................................... 48

Key to Switching Waveforms. . . . . . . . . . . . . . . . 48

Figure 12. Input Waveforms and

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations ....................................................... 9

Word/Byte Configuration .......................................................... 9

VersatileIO^TM(V_IO) Control ........................................................ 9

Requirements for Reading Array Data ................................... 10

Page Mode Read ............................................................................10

Writing Commands/Command Sequences ............................ 10

Write Buffer .....................................................................................10

Accelerated Program Operation ......................................................10

Autoselect Functions .......................................................................10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Pin ............................................... 11

Output Disable Mode .............................................................. 11

Table 2. Sector Address Table........................................................ 12

Autoselect Mode ..................................................................... 23

Table 3. Autoselect Codes, (High Voltage Method) ....................... 23

Sector Group Protection and Unprotection ............................. 24

Table 4. Sector Group Protection/Unprotection Address Table ..... 24

Write Protect (WP#) ................................................................ 26

Temporary Sector Group Unprotect ....................................... 26

Figure 1. Temporary Sector Group Unprotect Operation ................26

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...27

SecSi (Secured Silicon) Sector Flash Memory Region .......... 28

Table 5. SecSi Sector Contents...................................................... 28

................................................................................................ 29

Figure 3. SecSi Sector Protect Verify ..............................................29

Hardware Data Protection ...................................................... 29

Low VCC Write Inhibit .....................................................................29

Write Pulse “Glitch” Protection ........................................................29

Logical Inhibit ..................................................................................29

Power-Up Write Inhibit ....................................................................29

Common Flash Memory Interface (CFI). . . . . . . 29

Table 6. CFI Query Identification String ..........................................30

Table 7. System Interface String..................................................... 30

Table 8. Device Geometry Definition ..............................................31

Table 9. Primary Vendor-Specific Extended Query ........................32

Command Definitions . . . . . . . . . . . . . . . . . . . . . 32

Reading Array Data ................................................................ 32

Reset Command ..................................................................... 33

Autoselect Command Sequence ............................................ 33

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 33

Word/Byte Program Command Sequence ............................. 33

Unlock Bypass Command Sequence ..............................................34

Write Buffer Programming ...............................................................34

Accelerated Program ......................................................................35

Figure 4. Write Buffer Programming Operation ...............................36

Figure 5. Program Operation ..........................................................37

Program Suspend/Program Resume Command Sequence ... 37

Figure 6. Program Suspend/Program Resume ...............................38

Chip Erase Command Sequence ........................................... 38

Sector Erase Command Sequence ........................................ 38

Measurement Levels ...................................................................... 48

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 49

Read-Only Operations ........................................................... 49

Figure 13. Read Operation Timings ............................................... 49

Figure 14. Page Read Timings ...................................................... 50

Hardware Reset (RESET#) .................................................... 51

Figure 15. Reset Timings ............................................................... 51

Erase and Program Operations .............................................. 52

Figure 16. Program Operation Timings .......................................... 53

Figure 17. Accelerated Program Timing Diagram .......................... 53

Figure 18. Chip/Sector Erase Operation Timings .......................... 54

Figure 19. Data# Polling Timings (During Embedded Algorithms) . 55

Figure 20. Toggle Bit Timings (During Embedded Algorithms) ...... 56

Figure 21. DQ2 vs. DQ6 ................................................................. 56

Temporary Sector Unprotect .................................................. 57

Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 57

Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 58

Alternate CE# Controlled Erase and Program Operations ..... 59

Figure 24. Alternate CE# Controlled Write (Erase/Program)

Operation Timings .......................................................................... 60

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 60

Erase And Programming Performance. . . . . . . . 61

TSOP Pin and BGA Package Capacitance . . . . . 61

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline

Package (TSOP) ..................................................................... 63

LAC064—64-Ball Fortified Ball Grid Array

18 x 12 mm Package .............................................................. 64

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 65

December 16, 2005

Am29LV256M

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Part Number

Am29LV256M

103R

(Note 2)

(V_IO= 2.7–3.6)

113R

(V_IO= 1.65–3.6)

123R

(V_IO= 1.65–3.6)

Regulated Voltage Range

V_CC= 3.0–3.6 V

Speed/

Voltage

Option

103

(Note 2)

(V_IO= 2.7–3.6)

113

(Note 2)

(V_IO= 1.65–3.6)

123

(Note 2)

(V_IO= 1.65–3.6)

Full Voltage Range

V_CC= 2.7–3.6 V

Max. Access Time (ns)

100

30

110

120

Max. CE# Access Time (ns)

Max. Page access time (t_PACC

Max. OE# Access Time (ns)

)

30

40

30

40

30

Notes:

1. See “AC Characteristics” for full specifications.

2. Contact factory for availability and ordering information.

BLOCK DIAGRAM

DQ0–DQ15 (A-1)

RY/BY#

V_CC

Sector Switches

V_SS

Erase Voltage

Generator

Input/Output

Buffers

V_IO

RESET#

WE#

State

WP#/ACC

Control

BYTE#

Command

Register

PGM Voltage

Generator

Data

Latch

Chip Enable

Output Enable

Logic

STB

CE#

OE#

Y-Decoder

X-Decoder

Y-Gating

STB

V_CCDetector

Timer

Cell Matrix

A23–A0

4

Am29LV256M

December 16, 2005

D A T A S H E E T

CONNECTION DIAGRAMS

A23

A22

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

9

56 NC

55 NC

54 A16

53 BYTE#

52 V_SS

51 DQ15/A-1

50 DQ7

49 DQ14

48 DQ6

47 DQ13

46 DQ5

45 DQ12

44 DQ4

43 V_CC

42 DQ11

41 DQ3

40 DQ10

39 DQ2

38 DQ9

37 DQ1

36 DQ8

35 DQ0

34 OE#

33 V_SS

56-Pin Standard TSOP

A8 10

A19 11

A20 12

WE# 13

RESET# 14

A21 15

WP#/ACC 16

RY/BY# 17

A18 18

A17 19

A7 20

A6 21

A5 22

A4 23

A3 24

A2 25

32 CE#

31 A0

30 NC

29 V_IO

A1 26

NC 27

NC 28

NC

1

2

3

4

5

6

7

8

9

56 A23

55 A22

54 A15

53 A14

52 A13

51 A12

50 A11

49 A10

48 A9

A16

BYTE#

V_SS

DQ15/A-1

DQ7

56-Pin Reverse TSOP

DQ14

DQ6

DQ13 10

DQ5 11

DQ12 12

DQ4 13

V_CC14

DQ11 15

DQ3 16

DQ10 17

DQ2 18

DQ9 19

DQ1 20

DQ8 21

DQ0 22

OE# 23

V_SS24

47 A8

46 A19

45 A20

44 WE#

43 RESET#

42 A21

41 WP#/ACC

40 RY/BY#

39 A18

38 A17

37 A7

36 A6

35 A5

34 A4

33 A3

CE# 25

A0 26

NC 27

V_IO28

32 A2

31 A1

30 NC

29 NC

December 16, 2005

Am29LV256M

5

D A T A S H E E T

CONNECTION DIAGRAMS

Fortified BGA

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

NC

H8

A22²

A23³

V_IO

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

V_SS

A13

A12

A14

A15

A16

BYTE# DQ15/A-1

A6

A9

B6

A8

C6

D6

E6

F6

G6

H6

A10

A11

DQ7

DQ14

DQ13

DQ6

A5

B5

C5

D5

E5

F5

G5

H5

WE# RESET# A21¹

A19

DQ5

DQ12

DQ4

V_CC

A4

B4

C4

D4

E4

F4

G4

H4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A3

A7

B3

C3

A6

D3

A5

E3

F3

G3

H3

A17

DQ0

DQ8

DQ9

DQ1

A2

A3

B2

A4

C2

A2

D2

A1

E2

A0

F2

G2

H2

V_SS

CE#

OE#

A1

B1

C1

D1

E1

F1

G1

NC

H1

NC

V_IO

and/or data integrity may be compromised if the

package body is exposed to temperatures above

150°C for prolonged periods of time.

SPECIAL PACKAGE HANDLING

INSTRUCTIONS

Special handling is required for Flash Memory products

in molded packages (TSOP and BGA). The package

6

Am29LV256M

December 16, 2005

D A T A S H E E T

PIN DESCRIPTION

LOGIC SYMBOL

A23–A0

= 24 Address inputs

24

DQ14–DQ0 = 15 Data inputs/outputs

A23–A0

16 or 8

DQ15/A-1

= DQ15 (Data input/output, word mode),

DQ15–DQ0

(A-1)

CE#

A-1 (LSB Address input, byte mode)

OE#

CE#

OE#

WE#

= Chip Enable input

WE#

= Output Enable input

WP#/ACC

RESET#

V_IO

= Write Enable input

WP#/ACC = Hardware Write Protect input;

Acceleration input

RY/BY#

RESET#

BYTE#

RY/BY#

V_CC

= Hardware Reset Pin input

= Selects 8-bit or 16-bit mode

= Ready/Busy output

BYTE#

= 3.0 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

V_IO

V_SS

NC

= Output Buffer power

= Device Ground

= Pin Not Connected Internally

December 16, 2005

Am29LV256M

7

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29LV256M

H

123R

PG

I

TEMPERATURE RANGE

I

F

=

Industrial (–40°C to +85°C)

Industrial (–40°C to +85°C) with Lead (Pb)-free package

PACKAGE TYPE

E

F

PG

=

56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056)

56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056)

64-Ball Fortified Ball Grid Array,

1.0 mm pitch, 18 x 12 mm package (LAC064)

SPEED OPTION

See Product Selector Guide and Valid Combinations

SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = V_IL)

H

L

=

Uniform sector device, highest address sector protected

Uniform sector device, lowest address sector protected

DEVICE NUMBER/DESCRIPTION

Am29LV256MH/L

256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO^TMControl

3.0 Volt-only Read, Program, and Erase

Valid Combinations for

Fortified BGA Package

Valid Combinations for

TSOP Package

Speed

(ns)

V_IO

Range

V_CC

Range

Speed

(ns)

V_IO

V_CC

Range Range

Order Number

Package Marking

Am29LV256MH113R

Am29LV256ML113R

110

120

1.65–3.6 V

EI,

FI,

EF

Am29LV256MH113R

Am29LV256ML113R

L256MH113R

L256ML113R

1.65–

3.6 V

3.0–3.6 V

110

120

Am29LV256MH123R

Am29LV256ML123R

PGI,

PGF

I,

F

3.0–

3.6 V

Am29LV256MH123R

Am29LV256ML123R

L256MH123R

L256ML123R

1.65–

3.6 V

Valid Combinations

Valid Combinations list configurations planned to be supported in volume for

this device. Consult the local AMD sales office to confirm availability of specific

valid combinations and to check on newly released combinations.

Note:For 103, 103R, 110, and 120 speed option shown in product selector

guide, contact AMD for availability and ordering information.

Notes:

1. To select the product with ESN factory-locked into the SecSi Sector: 1) select the order number from the valid combinations

given above, 2)add designator “N” at the end of the order number, and 3) modify the speed option indicator as follows

[113R = 11R; 123R = 12R; 113, 123 = no change] Example: Am29LV256MH12RPGIN. For fortified BGA packages, the

designator “N” will also appear at the end of the package marking. Example: L256MH12RIN.

8

Am29LV256M

December 16, 2005

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Device Bus Operations

DQ8–DQ15

DQ0–

DQ7

BYTE#

= V_IH

BYTE#

= V_IL

Addresses

(Note 2)

Operation

CE#

OE# WE# RESET#

WP#

X

ACC

X

Read

L

H

L

H

A_IN

D_OUT

DQ8–DQ14

= High-Z,

DQ15 = A-1

Write (Program/Erase)

Accelerated Program

(Note 3)

X

(Note 4) (Note 4)

(Note 3) V_HH

V_CC

0.3 V

V_CC

0.3 V

Standby

X

H

X

High-Z High-Z

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z High-Z

High-Z

X

SA, A6 =L,

A3=L, A2=L, (Note 4)

A1=H, A0=L

Sector Group Protect

(Note 2)

L

H

L

V_ID

H

X

SA, A6=H,

A3=L, A2=L, (Note 4)

A1=H, A0=L

Sector Group Unprotect

(Note 2)

L

H

X

L

V_ID

H

X

Temporary Sector Group

Unprotect

X

A_IN

(Note 4) (Note 4)

High-Z

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 11.5–12.5V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A23:A0 in word mode; A23:A-1 in byte mode. Sector addresses are A23:A15 in both modes.

2. The sector group protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Group Protection and Unprotection” section.

3. If WP# = V_IL, the first or last sector group remains protected. If WP# = V_IH, the first or last sector will be protected or unprotected as

determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The

SecSi Sector may be factory protected depending on version ordered.)

4. D_INor D_OUTas required by command sequence, data polling, or sector protect algorithm (see Figure 2).

pins DQ8–DQ14 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins operate in the byte or word configuration. If the

VersatileIO^TM(V_IO) Control

BYTE# pin is set at logic ‘1’, the device is in word con-

figuration, DQ0–DQ15 are active and controlled by

The VersatileIO^TM(V_IO) control allows the host system

to set the voltage levels that the device generates and

tolerates on CE# and DQ I/Os to the same voltage

level that is asserted on V_IO. See Ordering Information

for V_IOoptions on this device.

CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are

active and controlled by CE# and OE#. The data I/O

December 16, 2005

Am29LV256M

9

D A T A S H E E T

For example, a V_I/Oof 1.65–3.6 volts allows for I/O at

Unlock Bypass mode, only two write cycles are re-

quired to program a word, instead of four. The

“Word/Byte Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command se-

quences.

the 1.8 or 3 volt levels, driving and receiving signals to

and from other 1.8 or 3 V devices on the same data

bus.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies.

Refer to the DC Characteristics table for the active

current specification for the write mode. The AC Char-

acteristics section contains timing specification tables

and timing diagrams for write operations.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

Write Buffer

Write Buffer Programming allows the system write to a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. See

“Write Buffer” for more information.

Accelerated Program Operation

See “Reading Array Data” for more information. Refer

to the AC Read-Only Operations table for timing speci-

fications and to Figure 13 for the timing diagram. Refer

to the DC Characteristics table for the active current

specification on reading array data.

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

Page Mode Read

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sector

groups, and uses the higher voltage on the pin to re-

duce the time required for program operations. The

system would use a two-cycle program command se-

quence as required by the Unlock Bypass mode. Re-

moving V_HHfrom the WP#/ACC pin returns the device

to normal operation. Note that the WP#/ACC pin must

not be at V_HHfor operations other than accelerated

programming, or device damage may result. WP# has

an internal pullup; when unconnected, WP# is at V_IH.

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for random locations within a page. The page size of

the device is 4 words/8 bytes. The appropriate page is

selected by the higher address bits A(max)–A2. Ad-

dress bits A1–A0 in word mode (A1–A-1 in byte mode)

determine the specific word within a page. This is an

asynchronous operation; the microprocessor supplies

the specific word location.

The random or initial page access is equal to t_ACCor

t_CEand subsequent page read accesses (as long as

the locations specified by the microprocessor falls

within that page) is equivalent to t_PACC. When CE# is

deasserted and reasserted for a subsequent access,

the access time is t_ACCor t_CE. Fast page mode ac-

cesses are obtained by keeping the “read-page ad-

dresses” constant and changing the “intra-read page”

addresses.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

10

Am29LV256M

December 16, 2005

D A T A S H E E T

and the outputs are placed in the high impedance

state, independent of the OE# input.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_IO0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_IO0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current will

be greater.

Refer to the DC Characteristics table for the standby

current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

this mode when addresses remain stable for t_ACC

+

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Refer to the DC Characteristics table for the automatic

sleep mode current specification.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 15 for the timing diagram.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

December 16, 2005

Am29LV256M

11

D A T A S H E E T

Table 2. Sector Address Table

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA0

A23–A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

0000000–000FFFF

0010000–001FFFF

0020000–002FFFF

0030000–003FFFF

0040000–004FFFF

0050000–005FFFF

0060000–006FFFF

0070000–007FFFF

0080000–008FFFF

0090000–009FFFF

00A0000–00AFFFF

00B0000–00BFFFF

00C0000–00CFFFF

00D0000–00DFFFF

00E0000–00EFFFF

00F0000–00FFFFF

0100000–010FFFF

0110000–011FFFF

0120000–012FFFF

0130000–013FFFF

0140000–014FFFF

0150000–015FFFF

0160000–016FFFF

0170000–017FFFF

0180000–018FFFF

0190000–019FFFF

01A0000–01AFFFF

01B0000–01BFFFF

01C0000–01CFFFF

01D0000–01DFFFF

01E0000–01EFFFF

01F0000–01FFFFF

0200000–020FFFF

0210000–021FFFF

0220000–022FFFF

0230000–023FFFF

0240000–024FFFF

0250000–025FFFF

0260000–026FFFF

0270000–027FFFF

0280000–028FFFF

0290000–029FFFF

02A0000–02AFFFF

02B0000–02BFFFF

02C0000–02CFFFF

02D0000–02DFFFF

02E0000–02EFFFF

000000–007FFF

008000–00FFFF

010000–017FFF

018000–01FFFF

020000–027FFF

028000–02FFFF

030000–037FFF

038000–03FFFF

040000–047FFF

048000–04FFFF

050000–057FFF

058000–05FFFF

060000–067FFF

068000–06FFFF

070000–077FFF

078000–07FFFF

080000–087FFF

088000–08FFFF

090000–097FFF

098000–09FFFF

0A0000–0A7FFF

0A8000–0AFFFF

0B0000–0B7FFF

0B8000–0BFFFF

0C0000–0C7FFF

0C8000–0CFFFF

0D0000–0D7FFF

0D8000–0DFFFF

0E0000–0E7FFF

0E8000–0EFFFF

0F0000–0F7FFF

0F8000–0FFFFF

100000–107FFF

108000–10FFFF

110000–117FFF

118000–11FFFF

120000–127FFF

128000–12FFFF

130000–137FFF

138000–13FFFF

140000–147FFF

148000–14FFFF

150000–157FFF

158000–15FFFF

160000–167FFF

168000–16FFFF

170000–177FFF

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

12

Am29LV256M

December 16, 2005

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

A23–A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

02F0000–02FFFFF

0300000–030FFFF

0310000–031FFFF

0320000–032FFFF

0330000–033FFFF

0340000–034FFFF

0350000–035FFFF

0360000–036FFFF

0370000–037FFFF

0380000–038FFFF

0390000–039FFFF

03A0000–03AFFFF

03B0000–03BFFFF

03C0000–03CFFFF

03D0000–03DFFFF

03E0000–03EFFFF

03F0000–03FFFFF

0400000–040FFFF

0410000–041FFFF

0420000–042FFFF

0430000–043FFFF

0440000–044FFFF

0450000–045FFFF

0460000–046FFFF

0470000–047FFFF

0480000–048FFFF

0490000–049FFFF

04A0000–04AFFFF

04B0000–04BFFFF

04C0000–04CFFFF

04D0000–04DFFFF

04E0000–04EFFFF

04F0000–04FFFFF

0500000–050FFFF

0510000–051FFFF

0520000–052FFFF

0530000–053FFFF

0540000–054FFFF

0550000–055FFFF

0560000–056FFFF

0570000–057FFFF

0580000–058FFFF

0590000–059FFFF

05A0000–05AFFFF

05B0000–05BFFFF

05C0000–05CFFFF

05D0000–05DFFFF

05E0000–05EFFFF

178000–17FFFF

180000–187FFF

188000–18FFFF

190000–197FFF

198000–19FFFF

1A0000–1A7FFF

1A8000–1AFFFF

1B0000–1B7FFF

1B8000–1BFFFF

1C0000–1C7FFF

1C8000–1CFFFF

1D0000–1D7FFF

1D8000–1DFFFF

1E0000–1E7FFF

1E8000–1EFFFF

1F0000–1F7FFF

1F8000–1FFFFF

200000–207FFF

208000–20FFFF

210000–217FFF

218000–21FFFF

220000–227FFF

228000–22FFFF

230000–237FFF

238000–23FFFF

240000–247FFF

248000–24FFFF

250000–257FFF

258000–25FFFF

260000–267FFF

268000–26FFFF

270000–277FFF

278000–27FFFF

280000–287FFF

288000–28FFFF

290000–297FFF

298000–29FFFF

2A0000–2A7FFF

2A8000–2AFFFF

2B0000–2B7FFF

2B8000–2BFFFF

2C0000–2C7FFF

2C8000–2CFFFF

2D0000–2D7FFF

2D8000–2DFFFF

2E0000–2E7FFF

2E8000–2EFFFF

2F0000–2F7FFF

December 16, 2005

Am29LV256M

13

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA95

A23–A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

05F0000–05FFFFF

0600000–060FFFF

0610000–061FFFF

0620000–062FFFF

0630000–063FFFF

0640000–064FFFF

0650000–065FFFF

0660000–066FFFF

0670000–067FFFF

0680000–068FFFF

0690000–069FFFF

06A0000–06AFFFF

06B0000–06BFFFF

06C0000–06CFFFF

06D0000–06DFFFF

06E0000–06EFFFF

06F0000–06FFFFF

0700000–070FFFF

0710000–071FFFF

0720000–072FFFF

0730000–073FFFF

0740000–074FFFF

0750000–075FFFF

0760000–076FFFF

0770000–077FFFF

0780000–078FFFF

0790000–079FFFF

07A0000–07AFFFF

07B0000–07BFFFF

07C0000–07CFFFF

07D0000–07DFFFF

07E0000–07EFFFF

07F0000–07FFFFF

0800000–080FFFF

0810000–081FFFF

0820000–082FFFF

0830000–083FFFF

0840000–084FFFF

0850000–085FFFF

0860000–086FFFF

0870000–087FFFF

0880000–088FFFF

0890000–089FFFF

08A0000–08AFFFF

08B0000–08BFFFF

08C0000–08CFFFF

08D0000–08DFFFF

08E0000–08EFFFF

2F8000–2FFFFF

300000–307FFF

308000–30FFFF

310000–317FFF

318000–31FFFF

320000–327FFF

328000–32FFFF

330000–337FFF

338000–33FFFF

340000–347FFF

348000–34FFFF

350000–357FFF

358000–35FFFF

360000–367FFF

368000–36FFFF

370000–377FFF

378000–37FFFF

380000–387FFF

388000–38FFFF

390000–397FFF

398000–39FFFF

3A0000–3A7FFF

3A8000–3AFFFF

3B0000–3B7FFF

3B8000–3BFFFF

3C0000–3C7FFF

3C8000–3CFFFF

3D0000–3D7FFF

3D8000–3DFFFF

3E0000–3E7FFF

3E8000–3EFFFF

3F0000–3F7FFF

3F8000–3FFFFF

400000–407FFF

408000–40FFFF

410000–417FFF

418000–41FFFF

420000–427FFF

428000–42FFFF

430000–437FFF

438000–43FFFF

440000–447FFF

448000–44FFFF

450000–457FFF

458000–45FFFF

460000–467FFF

468000–46FFFF

470000–477FFF

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

14

Am29LV256M

December 16, 2005

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

A23–A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

08F0000–08FFFFF

0900000–090FFFF

0910000–091FFFF

0920000–092FFFF

0930000–093FFFF

0940000–094FFFF

0950000–095FFFF

0960000–096FFFF

0970000–097FFFF

0980000–098FFFF

0990000–099FFFF

09A0000–09AFFFF

09B0000–09BFFFF

09C0000–09CFFFF

09D0000–09DFFFF

09E0000–09EFFFF

09F0000–09FFFFF

0A00000–0A0FFFF

0A10000–0A1FFFF

0A20000–0A2FFFF

0A30000–0A3FFFF

0A40000–0A4FFFF

0A50000–0A5FFFF

0A60000–0A6FFFF

0A70000–0A7FFFF

0A80000–0A8FFFF

0A90000–0A9FFFF

0AA0000–0AAFFFF

0AB0000–0ABFFFF

0AC0000–0ACFFFF

0AD0000–0ADFFFF

0AE0000–0AEFFFF

0AF0000–0AFFFFF

0B00000–0B0FFFF

0B10000–0B1FFFF

0B20000–0B2FFFF

0B30000–0B3FFFF

0B40000–0B4FFFF

0B50000–0B5FFFF

0B60000–0B6FFFF

0B70000–0B7FFFF

0B80000–0B8FFFF

0B90000–0B9FFFF

0BA0000–0BAFFFF

0BB0000–0BBFFFF

0BC0000–0BCFFFF

0BD0000–0BDFFFF

0BE0000–0BEFFFF

478000–47FFFF

480000–487FFF

488000–48FFFF

490000–497FFF

498000–49FFFF

4A0000–4A7FFF

4A8000–4AFFFF

4B0000–4B7FFF

4B8000–4BFFFF

4C0000–4C7FFF

4C8000–4CFFFF

4D0000–4D7FFF

4D8000–4DFFFF

4E0000–4E7FFF

4E8000–4EFFFF

4F0000–4F7FFF

4F8000–4FFFFF

500000–507FFF

508000–50FFFF

510000–517FFF

518000–51FFFF

520000–527FFF

528000–52FFFF

530000–537FFF

538000–53FFFF

540000–547FFF

548000–54FFFF

550000–557FFF

558000–55FFFF

560000–567FFF

568000–56FFFF

570000–577FFF

578000–57FFFF

580000–587FFF

588000–58FFFF

590000–597FFF

598000–59FFFF

5A0000–5A7FFF

5A8000–5AFFFF

5B0000–5B7FFF

5B8000–5BFFFF

5C0000–5C7FFF

5C8000–5CFFFF

5D0000–5D7FFF

5D8000–5DFFFF

5E0000–5E7FFF

5E8000–5EFFFF

5F0000–5F7FFF

December 16, 2005

Am29LV256M

15

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

SA199

SA200

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

A23–A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

0BF0000–0BFFFFF

0C00000–0C0FFFF

0C10000–0C1FFFF

0C20000–0C2FFFF

0C30000–0C3FFFF

0C40000–0C4FFFF

0C50000–0C5FFFF

0C60000–0C6FFFF

0C70000–0C7FFFF

0C80000–0C8FFFF

0C90000–0C9FFFF

0CA0000–0CAFFFF

0CB0000–0CBFFFF

0CC0000–0CCFFFF

0CD0000–0CDFFFF

0CE0000–0CEFFFF

0CF0000–0CFFFFF

0D00000–0D0FFFF

0D10000–0D1FFFF

0D20000–0D2FFFF

0D30000–0D3FFFF

0D40000–0D4FFFF

0D50000–0D5FFFF

0D60000–0D6FFFF

0D70000–0D7FFFF

0D80000–0D8FFFF

0D90000–0D9FFFF

0DA0000–0DAFFFF

0DB0000–0DBFFFF

0DC0000–0DCFFFF

0DD0000–0DDFFFF

0DE0000–0DEFFFF

0DF0000–0DFFFFF

0E00000–0E0FFFF

0E10000–0E1FFFF

0E20000–0E2FFFF

0E30000–0E3FFFF

0E40000–0E4FFFF

0E50000–0E5FFFF

0E60000–0E6FFFF

0E70000–0E7FFFF

0E80000–0E8FFFF

0E90000–0E9FFFF

0EA0000–0EAFFFF

0EB0000–0EBFFFF

0EC0000–0ECFFFF

0ED0000–0EDFFFF

0EE0000–0EEFFFF

5F8000–5FFFFF

600000–607FFF

608000–60FFFF

610000–617FFF

618000–61FFFF

620000–627FFF

628000–62FFFF

630000–637FFF

638000–63FFFF

640000–647FFF

648000–64FFFF

650000–657FFF

658000–65FFFF

660000–667FFF

668000–66FFFF

670000–677FFF

678000–67FFFF

680000–687FFF

688000–68FFFF

690000–697FFF

698000–69FFFF

6A0000–6A7FFF

6A8000–6AFFFF

6B0000–6B7FFF

6B8000–6BFFFF

6C0000–6C7FFF

6C8000–6CFFFF

6D0000–6D7FFF

6D8000–6DFFFF

6E0000–6E7FFF

6E8000–6EFFFF

6F0000–6F7FFF

6F8000–6FFFFF

700000–707FFF

708000–70FFFF

710000–717FFF

718000–71FFFF

720000–727FFF

728000–72FFFF

730000–737FFF

738000–73FFFF

740000–747FFF

748000–74FFFF

750000–757FFF

758000–75FFFF

760000–767FFF

768000–76FFFF

770000–777FFF

16

Am29LV256M

December 16, 2005

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA239

SA240

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

SA256

SA257

SA258

SA259

SA260

SA261

SA262

SA263

SA264

SA265

SA266

SA267

SA268

SA269

SA270

SA271

SA272

SA273

SA274

SA275

SA276

SA277

SA278

SA279

SA280

SA281

SA282

SA283

SA284

SA285

SA286

A23–A15

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

0EF0000–0EFFFFF

0F00000–0F0FFFF

0F10000–0F1FFFF

0F20000–0F2FFFF

0F30000–0F3FFFF

0F40000–0F4FFFF

0F50000–0F5FFFF

0F60000–0F6FFFF

0F70000–0F7FFFF

0F80000–0F8FFFF

0F90000–0F9FFFF

0FA0000–0FAFFFF

0FB0000–0FBFFFF

0FC0000–0FCFFFF

0FD0000–0FDFFFF

0FE0000–0FEFFFF

0FF0000–0FFFFFF

1000000–100FFFF

1010000–101FFFF

1020000–102FFFF

1030000–103FFFF

1040000–104FFFF

1050000–105FFFF

1060000–106FFFF

1070000–107FFFF

1080000–108FFFF

1090000–109FFFF

10A0000–10AFFFF

10B0000–10BFFFF

10C0000–10CFFFF

10D0000–10DFFFF

10E0000–10EFFFF

10F0000–10FFFFF

1100000–110FFFF

1110000–111FFFF

1120000–112FFFF

1130000–113FFFF

1140000–114FFFF

1150000–115FFFF

1160000–116FFFF

1170000–117FFFF

1180000–118FFFF

1190000–119FFFF

11A0000–11AFFFF

11B0000–11BFFFF

11C0000–11CFFFF

11D0000–11DFFFF

11E0000–11EFFFF

778000–77FFFF

780000–787FFF

788000–78FFFF

790000–797FFF

798000–79FFFF

7A0000–7A7FFF

7A8000–7AFFFF

7B0000–7B7FFF

7B8000–7BFFFF

7C0000–7C7FFF

7C8000–7CFFFF

7D0000–7D7FFF

7D8000–7DFFFF

7E0000–7E7FFF

7E8000–7EFFFF

7F0000–7F7FFF

7F8000–7FFFFF

800000–807FFF

808000–80FFFF

810000–817FFF

818000–81FFFF

820000–827FFF

828000–82FFFF

830000–837FFF

838000–83FFFF

840000–847FFF

848000–84FFFF

850000–857FFF

858000–85FFFF

860000–867FFF

868000–86FFFF

870000–877FFF

878000–87FFFF

880000–887FFF

888000–88FFFF

890000–897FFF

898000–89FFFF

8A0000–8A7FFF

8A8000–8AFFFF

8B0000–8B7FFF

8B8000–8BFFFF

8C0000–8C7FFF

8C8000–8CFFFF

8D0000–8D7FFF

8D8000–8DFFFF

8E0000–8E7FFF

8E8000–8EFFFF

8F0000–8F7FFF

December 16, 2005

Am29LV256M

17

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA287

SA288

SA289

SA290

SA291

SA292

SA293

SA294

SA295

SA296

SA297

SA298

SA299

SA300

SA301

SA302

SA303

SA304

SA305

SA306

SA307

SA308

SA309

SA310

SA311

SA312

SA313

SA314

SA315

SA316

SA317

SA318

SA319

SA320

SA321

SA322

SA323

SA324

SA325

SA326

SA327

SA328

SA329

SA330

SA331

SA332

SA333

SA334

A23–A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

11F0000–11FFFFF

1200000–120FFFF

1210000–121FFFF

1220000–122FFFF

1230000–123FFFF

1240000–124FFFF

1250000–125FFFF

1260000–126FFFF

1270000–127FFFF

1280000–128FFFF

1290000–129FFFF

12A0000–12AFFFF

12B0000–12BFFFF

12C0000–12CFFFF

12D0000–12DFFFF

12E0000–12EFFFF

12F0000–12FFFFF

1300000–130FFFF

1310000–131FFFF

1320000–132FFFF

1330000–133FFFF

1340000–134FFFF

1350000–135FFFF

1360000–136FFFF

1370000–137FFFF

1380000–138FFFF

1390000–139FFFF

13A0000–13AFFFF

13B0000–13BFFFF

13C0000–13CFFFF

13D0000–13DFFFF

13E0000–13EFFFF

13F0000–13FFFFF

1400000–140FFFF

1410000–141FFFF

1420000–142FFFF

1430000–143FFFF

1440000–144FFFF

1450000–145FFFF

1460000–146FFFF

1470000–147FFFF

1480000–148FFFF

1490000–149FFFF

14A0000–14AFFFF

14B0000–14BFFFF

14C0000–14CFFFF

14D0000–14DFFFF

14E0000–14EFFFF

8F8000–8FFFFF

900000–907FFF

908000–90FFFF

910000–917FFF

918000–91FFFF

920000–927FFF

928000–92FFFF

930000–937FFF

938000–93FFFF

940000–947FFF

948000–94FFFF

950000–957FFF

958000–95FFFF

960000–967FFF

968000–96FFFF

970000–977FFF

978000–97FFFF

980000–987FFF

988000–98FFFF

990000–997FFF

998000–99FFFF

9A0000–9A7FFF

9A8000–9AFFFF

9B0000–9B7FFF

9B8000–9BFFFF

9C0000–9C7FFF

9C8000–9CFFFF

9D0000–9D7FFF

9D8000–9DFFFF

9E0000–9E7FFF

9E8000–9EFFFF

9F0000–9F7FFF

9F8000–9FFFFF

A00000–A07FFF

A08000–A0FFFF

A10000–A17FFF

A18000–A1FFFF

A20000–A27FFF

A28000–A2FFFF

A30000–A37FFF

A38000–A3FFFF

A40000–A47FFF

A48000–A4FFFF

A50000–A57FFF

A58000–A5FFFF

A60000–A67FFF

A68000–A6FFFF

A70000–A77FFF

18

Am29LV256M

December 16, 2005

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA335

SA336

SA337

SA338

SA339

SA340

SA341

SA342

SA343

SA344

SA345

SA346

SA347

SA348

SA349

SA350

SA351

SA352

SA353

SA354

SA355

SA356

SA357

SA358

SA359

SA360

SA361

SA362

SA363

SA364

SA365

SA366

SA367

SA368

SA369

SA370

SA371

SA372

SA373

SA374

SA375

SA376

SA377

SA378

SA379

SA380

SA381

SA382

A23–A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

14F0000–14FFFFF

1500000–150FFFF

1510000–151FFFF

1520000–152FFFF

1530000–153FFFF

1540000–154FFFF

1550000–155FFFF

1560000–156FFFF

1570000–157FFFF

1580000–158FFFF

1590000–159FFFF

15A0000–15AFFFF

15B0000–15BFFFF

15C0000–15CFFFF

15D0000–15DFFFF

15E0000–15EFFFF

15F0000–15FFFFF

1600000–160FFFF

1610000–161FFFF

1620000–162FFFF

1630000–163FFFF

1640000–164FFFF

1650000–165FFFF

1660000–166FFFF

1670000–167FFFF

1680000–168FFFF

1690000–169FFFF

16A0000–16AFFFF

16B0000–16BFFFF

16C0000–16CFFFF

16D0000–16DFFFF

16E0000–16EFFFF

16F0000–16FFFFF

1700000–170FFFF

1710000–171FFFF

1720000–172FFFF

1730000–173FFFF

1740000–174FFFF

1750000–175FFFF

1760000–176FFFF

1770000–177FFFF

1780000–178FFFF

1790000–179FFFF

17A0000–17AFFFF

17B0000–17BFFFF

17C0000–17CFFFF

17D0000–17DFFFF

17E0000–17EFFFF

A78000–A7FFFF

A80000–A87FFF

A88000–A8FFFF

A90000–A97FFF

A98000–A9FFFF

AA0000–AA7FFF

AA8000–AAFFFF

AB0000–AB7FFF

AB8000–ABFFFF

AC0000–AC7FFF

AC8000–ACFFFF

AD0000–AD7FFF

AD8000–ADFFFF

AE0000–AE7FFF

AE8000–AEFFFF

AF0000–AF7FFF

AF8000–AFFFFF

B00000–B07FFF

B08000–B0FFFF

B10000–B17FFF

B18000–B1FFFF

B20000–B27FFF

B28000–B2FFFF

B30000–B37FFF

B38000–B3FFFF

B40000–B47FFF

B48000–B4FFFF

B50000–B57FFF

B58000–B5FFFF

B60000–B67FFF

B68000–B6FFFF

B70000–B77FFF

B78000–B7FFFF

B80000–B87FFF

B88000–B8FFFF

B90000–B97FFF

B98000–B9FFFF

BA0000–BA7FFF

BA8000–BAFFFF

BB0000–BB7FFF

BB8000–BBFFFF

BC0000–BC7FFF

BC8000–BCFFFF

BD0000–BD7FFF

BD8000–BDFFFF

BE0000–BE7FFF

BE8000–BEFFFF

BF0000–BF7FFF

December 16, 2005

Am29LV256M

19

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA383

SA384

SA385

SA386

SA387

SA388

SA389

SA390

SA391

SA392

SA393

SA394

SA395

SA396

SA397

SA398

SA399

SA400

SA401

SA402

SA403

SA404

SA405

SA406

SA407

SA408

SA409

SA410

SA411

SA412

SA413

SA414

SA415

SA416

SA417

SA418

SA419

SA420

SA421

SA422

SA423

SA424

SA425

SA426

SA427

SA428

SA429

SA430

A23–A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

17F0000–17FFFFF

1800000–180FFFF

1810000–181FFFF

1820000–182FFFF

1830000–183FFFF

1840000–184FFFF

1850000–185FFFF

1860000–186FFFF

1870000–187FFFF

1880000–188FFFF

1890000–189FFFF

18A0000–18AFFFF

18B0000–18BFFFF

18C0000–18CFFFF

18D0000–18DFFFF

18E0000–18EFFFF

18F0000–18FFFFF

1900000–190FFFF

1910000–191FFFF

1920000–192FFFF

1930000–193FFFF

1940000–194FFFF

1950000–195FFFF

1960000–196FFFF

1970000–197FFFF

1980000–198FFFF

1990000–199FFFF

19A0000–19AFFFF

19B0000–19BFFFF

19C0000–19CFFFF

19D0000–19DFFFF

19E0000–19EFFFF

19F0000–19FFFFF

1A00000–1A0FFFF

1A10000–1A1FFFF

1A20000–1A2FFFF

1A30000–1A3FFFF

1A40000–1A4FFFF

1A50000–1A5FFFF

1A60000–1A6FFFF

1A70000–1A7FFFF

1A80000–1A8FFFF

1A90000–1A9FFFF

1AA0000–1AAFFFF

1AB0000–1ABFFFF

1AC0000–1ACFFFF

1AD0000–1ADFFFF

1AE0000–1AEFFFF

BF8000–BFFFFF

C00000–C07FFF

C08000–C0FFFF

C10000–C17FFF

C18000–C1FFFF

C20000–C27FFF

C28000–C2FFFF

C30000–C37FFF

C38000–C3FFFF

C40000–C47FFF

C48000–C4FFFF

C50000–C57FFF

C58000–C5FFFF

C60000–C67FFF

C68000–C6FFFF

C70000–C77FFF

C78000–C7FFFF

C80000–C87FFF

C88000–C8FFFF

C90000–C97FFF

C98000–C9FFFF

CA0000–CA7FFF

CA8000–CAFFFF

CB0000–CB7FFF

CB8000–CBFFFF

CC0000–CC7FFF

CC8000–CCFFFF

CD0000–CD7FFF

CD8000–CDFFFF

CE0000–CE7FFF

CE8000–CEFFFF

CF0000–CF7FFF

CF8000–CFFFFF

D00000–D07FFF

D08000–D0FFFF

D10000–D17FFF

D18000–D1FFFF

D20000–D27FFF

D28000–D2FFFF

D30000–D37FFF

D38000–D3FFFF

D40000–D47FFF

D48000–D4FFFF

D50000–D57FFF

D58000–D5FFFF

D60000–D67FFF

D68000–D6FFFF

D70000–D77FFF

20

Am29LV256M

December 16, 2005

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA431

SA432

SA433

SA434

SA435

SA436

SA437

SA438

SA439

SA440

SA441

SA442

SA443

SA444

SA445

SA446

SA447

SA448

SA449

SA450

SA451

SA452

SA453

SA454

SA455

SA456

SA457

SA458

SA459

SA460

SA461

SA462

SA463

SA464

SA465

SA466

SA467

SA468

SA469

SA470

SA471

SA472

SA473

SA474

SA475

SA476

SA477

SA478

A23–A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

64/32

1AF0000–1AFFFFF

1B00000–1B0FFFF

1B10000–1B1FFFF

1B20000–1B2FFFF

1B30000–1B3FFFF

1B40000–1B4FFFF

1B50000–1B5FFFF

1B60000–1B6FFFF

1B70000–1B7FFFF

1B80000–1B8FFFF

1B90000–1B9FFFF

1BA0000–1BAFFFF

1BB0000–1BBFFFF

1BC0000–1BCFFFF

1BD0000–1BDFFFF

1BE0000–1BEFFFF

1BF0000–1BFFFFF

1C00000–1C0FFFF

1C10000–1C1FFFF

1C20000–1C2FFFF

1C30000–1C3FFFF

1C40000–1C4FFFF

1C50000–1C5FFFF

1C60000–1C6FFFF

1C70000–1C7FFFF

1C80000–1C8FFFF

1C90000–1C9FFFF

1CA0000–1CAFFFF

1CB0000–1CBFFFF

1CC0000–1CCFFFF

1CD0000–1CDFFFF

1CE0000–1CEFFFF

1CF0000–1CFFFFF

1D00000–1D0FFFF

1D10000–1D1FFFF

1D20000–1D2FFFF

1D30000–1D3FFFF

1D40000–1D4FFFF

1D50000–1D5FFFF

1D60000–1D6FFFF

1D70000–1D7FFFF

1D80000–1D8FFFF

1D90000–1D9FFFF

1DA0000–1DAFFFF

1DB0000–1DBFFFF

1DC0000–1DCFFFF

1DD0000–1DDFFFF

1DE0000–1DEFFFF

D78000–D7FFFF

D80000–D87FFF

D88000–D8FFFF

D90000–D97FFF

D98000–D9FFFF

DA0000–DA7FFF

DA8000–DAFFFF

DB0000–DB7FFF

DB8000–DBFFFF

DC0000–DC7FFF

DC8000–DCFFFF

DD0000–DD7FFF

DD8000–DDFFFF

DE0000–DE7FFF

DE8000–DEFFFF

DF0000–DF7FFF

DF8000–DFFFFF

E00000–E07FFF

E08000–E0FFFF

E10000–E17FFF

E18000–E1FFFF

E20000–E27FFF

E28000–E2FFFF

E30000–E37FFF

E38000–E3FFFF

E40000–E47FFF

E48000–E4FFFF

E50000–E57FFF

E58000–E5FFFF

E60000–E67FFF

E68000–E6FFFF

E70000–E77FFF

E78000–E7FFFF

E80000–E87FFF

E88000–E8FFFF

E90000–E97FFF

E98000–E9FFFF

EA0000–EA7FFF

EA8000–EAFFFF

EB0000–EB7FFF

EB8000–EBFFFF

EC0000–EC7FFF

EC8000–ECFFFF

ED0000–ED7FFF

ED8000–EDFFFF

EE0000–EE7FFF

EE8000–EEFFFF

EF0000–EF7FFF

December 16, 2005

Am29LV256M

21

D A T A S H E E T

Table 2. Sector Address Table (Continued)

8-bit

Address Range

(in hexadecimal)

16-bit

Address Range

(in hexadecimal)

Sector Size

(Kbytes/Kwords)

Sector

SA479

SA480

SA481

SA482

SA483

SA484

SA485

SA486

SA487

SA488

SA489

SA490

SA491

SA492

SA493

SA494

SA495

SA496

SA497

SA498

SA499

SA500

SA501

SA502

SA503

SA504

SA505

SA506

SA507

SA508

SA509

SA510

SA511

A23–A15

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

64/32

1DF0000–1DFFFFF

1E00000–1E0FFFF

1E10000–1E1FFFF

1E20000–1E2FFFF

1E30000–1E3FFFF

1E40000–1E4FFFF

1E50000–1E5FFFF

1E60000–1E6FFFF

1E70000–1E7FFFF

1E80000–1E8FFFF

1E90000–1E9FFFF

1EA0000–1EAFFFF

1EB0000–1EBFFFF

1EC0000–1ECFFFF

1ED0000–1EDFFFF

1EE0000–1EEFFFF

1EF0000–1EFFFFF

1F00000–1F0FFFF

1F10000–1F1FFFF

1F20000–1F2FFFF

1F30000–1F3FFFF

1F40000–1F4FFFF

1F50000–1F5FFFF

1F60000–1F6FFFF

1F70000–1F7FFFF

1F80000–1F8FFFF

1F90000–1F9FFFF

1FA0000–1FAFFFF

1FB0000–1FBFFFF

1FC0000–1FCFFFF

1FD0000–1FDFFFF

1FE0000–1FEFFFF

1FF0000–1FFFFFF

EF8000–EFFFFF

F00000–F07FFF

F08000–F0FFFF

F10000–F17FFF

F18000–F1FFFF

F20000–F27FFF

F28000–F2FFFF

F30000–F37FFF

F38000–F3FFFF

F40000–F47FFF

F48000–F4FFFF

F50000–F57FFF

F58000–F5FFFF

F60000–F67FFF

F68000–F6FFFF

F70000–F77FFF

F78000–F7FFFF

F80000–F87FFF

F88000–F8FFFF

F90000–F97FFF

F98000–F9FFFF

FA0000–FA7FFF

FA8000–FAFFFF

FB0000–FB7FFF

FB8000–FBFFFF

FC0000–FC7FFF

FC8000–FCFFFF

FD0000–FD7FFF

FD8000–FDFFFF

FE0000–FE7FFF

FE8000–FEFFFF

FF0000–FF7FFF

FF8000–FFFFFF

22

Am29LV256M

December 16, 2005

D A T A S H E E T

In addition, when verifying sector protection, the sector

Autoselect Mode

address must appear on the appropriate highest order

address bits (see Table 2). Table 3 shows the remain-

ing address bits that are don’t care. When all neces-

sary bits have been set as required, the programming

equipment may then read the corresponding identifier

code on DQ7–DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector group protection verifica-

tion, through identifier codes output on DQ7–DQ0.

This mode is primarily intended for programming

equipment to automatically match a device to be pro-

grammed with its corresponding programming algo-

rithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Tables 11 and 12. This

method does not require V_ID. Refer to the Autoselect

Command Sequence section for more information.

When using programming equipment, the autoselect

mode requires V_IDon address pin A9. Address pins

A6, A3, A2, A1, and A0 must be as shown in Table 3.

Table 3. Autoselect Codes, (High Voltage Method)

DQ8 to DQ15

A22 A14

A8

A9 to A6

A7

A5 A3

to to

A4 A2

Description

CE# OE# WE# to

to

A1 A0

DQ7 to DQ0

BYTE# BYTE#

A15 A10

= V_IH

= V_IL

V_ID

Manufacturer ID: AMD

Cycle 1

L

H

X

L

X

L

H

L

00

X

01h

7Eh

12h

01h

22

X

V_ID

Cycle 2

X

L

X

H

22

X

Cycle 3

H

22

X

Sector Group

Protection Verification

01h (protected),

00h (unprotected)

V_ID

L

H

SA

X

L

X

L

H

L

X

SecSi Sector Indicator

Bit (DQ7), WP#

protects highest

address sector

98h (factory locked),

18h (not factory locked)

V_ID

L

H

X

SecSi Sector Indicator

Bit (DQ7), WP#

protects lowest

88h (factory locked),

08h (not factory locked)

V_ID

L

H

X

L

X

L

H

X

address sector

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

December 16, 2005

Am29LV256M

23

D A T A S H E E T

Sector Group Protection and Unprotection

Sector Group

SA68–SA71

A23–A15

0010001xx

0010010xx

0010011xx

0010100xx

0010101xx

0010110xx

0010111xx

0011000xx

0011001xx

0011010xx

0011011xx

0011100xx

0011101xx

0011110xx

0011111xx

0100000xx

0100001xx

0100010xx

0100011xx

0100100xx

0100101xx

0100110xx

0100111xx

0101000xx

0101001xx

0101010xx

0101011xx

0101100xx

0101101xx

0101110xx

0101111xx

0110000xx

0110001xx

0110010xx

0110011xx

0110100xx

0110101xx

0110110xx

0110111xx

0111000xx

0111001xx

0111010xx

0111011xx

0111100xx

0111101xx

The hardware sector group protection feature disables

both program and erase operations in any sector

group. The hardware sector group unprotection fea-

ture re-enables both program and erase operations in

previously protected sector groups. Sector group pro-

tection/unprotection can be implemented via two

methods.

SA72–SA75

SA76–SA79

SA80–SA83

SA84–SA87

SA88–SA91

Sector group protection/unprotection requires V_IDon

the RESET# pin only, and can be implemented either

in-system or via programming equipment. Figure 2

shows the algorithms and Figure 23 shows the timing

diagram. For sector group unprotect, all unprotected

sector groups must first be protected prior to the first

sector group unprotect write cycle. Note that the sec-

tor group unprotect algorithm unprotects all sector

groups in parallel. All previously protected sector

groups must be individually re-protected.

SA92–SA95

SA96–SA99

SA100–SA103

SA104–SA107

SA108–SA111

SA112–SA115

SA116–SA119

SA120–SA123

SA124–SA127

SA128–SA131

SA132–SA135

SA136–SA139

SA140–SA143

SA144–SA147

SA148–SA151

SA152–SA155

SA156–SA159

SA160–SA163

SA164–SA167

SA168–SA171

SA172–SA175

SA176–SA179

SA180–SA183

SA184–SA187

SA188–SA191

SA192–SA195

SA196–SA199

SA200–SA203

SA204–SA207

SA208–SA211

SA212–SA215

SA216–SA219

SA220–SA223

SA224–SA227

SA228–SA231

SA232–SA235

SA236–SA239

SA240–SA243

SA244–SA247

The device is shipped with all sector groups unpro-

tected. AMD offers the option of programming and pro-

tecting sector groups at its factory prior to shipping the

device through AMD’s ExpressFlash™ Service. Con-

tact an AMD representative for details.

It is possible to determine whether a sector group is

protected or unprotected. See the Autoselect Mode

section for details.

Table 4. Sector Group Protection/Unprotection

Address Table

Sector Group

SA0

A23–A15

000000000

000000001

000000010

000000011

0000001xx

0000010xx

0000011xx

0000100xx

0000101xx

0000110xx

0000111xx

0001000xx

0001001xx

0001010xx

0001011xx

0001100xx

0001101xx

0001110xx

0001111xx

0010000xx

SA1

SA2

SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA63

SA64–SA67

24

Am29LV256M

December 16, 2005

D A T A S H E E T

A23–A15

Sector Group

SA248–SA251

SA252–SA255

SA256–SA259

SA260–SA263

SA264–SA267

SA268–SA271

SA272–SA275

SA276–SA279

SA280–SA283

SA284–SA287

SA288–SA291

SA292–SA295

SA296–SA299

SA300–SA303

SA304–SA307

SA308–SA311

SA312–SA315

SA316–SA319

SA320–SA323

SA324–SA327

SA328–SA331

SA332–SA335

SA336–SA339

SA340–SA343

SA344–SA347

SA348–SA351

SA352–SA355

SA356–SA359

SA360–SA363

SA364–SA367

SA368–SA371

SA372–SA375

SA376–SA379

SA380–SA383

SA384–SA387

SA388–SA391

SA392–SA395

SA396–SA399

SA400–SA403

SA404–SA407

SA408–SA411

SA412–SA415

SA416–SA419

SA420–SA423

SA424–SA427

Sector Group

SA428–SA431

SA432–SA435

SA436–SA439

SA440–SA443

SA444–SA447

SA448–SA451

SA452–SA455

SA456–SA459

SA460–SA463

SA464–SA467

SA468–SA471

SA472–SA475

SA476–SA479

SA480–SA483

SA484–SA487

SA488–SA491

SA492–SA495

SA496–SA499

SA500–SA503

SA504–SA507

SA508

A23–A15

1101011xx

1101100xx

1101101xx

1101110xx

1101111xx

1110000xx

1110001xx

1110010xx

1110011xx

1110100xx

1110101xx

1110110xx

1110111xx

1111000xx

1111001xx

1111010xx

1111011xx

1111100xx

1111101xx

1111110xx

111111100

111111101

111111110

111111111

0111110xx

0111111xx

1000000xx

1000001xx

1000010xx

1000011xx

1000100xx

1000101xx

1000110xx

1000111xx

1001000xx

1001001xx

1001010xx

1001011xx

1001100xx

1001101xx

1001110xx

1001111xx

1010000xx

1010001xx

1010010xx

1010011xx

1010100xx

1010101xx

1010110xx

1010111xx

1011000xx

1011001xx

1011010xx

1011011xx

1011100xx

1011101xx

1011110xx

1011111xx

1100000xx

1100001xx

1100010xx

1100011xx

1100100xx

1100101xx

1100110xx

1100111xx

1101000xx

1101001xx

1101010xx

SA509

SA510

SA511

December 16, 2005

Am29LV256M

25

D A T A S H E E T

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting the first or last sector without

using V_ID. Write Protect is one of two functions pro-

vided by the WP#/ACC input.

START

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in the first

or last sector independently of whether those sectors

were protected or unprotected using the method de-

scribed in “Sector Group Protection and Unprotection”.

Note that if WP#/ACC is at V_ILwhen the device is in

the standby mode, the maximum input load current is

increased. See the table in “DC Characteristics”.

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether the first or last sector was pre-

viously set to be protected or unprotected using the

method described in “Sector Group Protection and

Unprotection”. Note that WP# has an internal pullup;

when unconnected, WP# is at V_IH.

Temporary Sector Group

Unprotect Completed

(Note 2)

Temporary Sector Group Unprotect

Notes:

This feature allows temporary unprotection of previ-

ously protected sector groups to change data in-sys-

tem. The Sector Group Unprotect mode is activated by

setting the RESET# pin to V_ID. During this mode, for-

merly protected sector groups can be programmed or

erased by selecting the sector addresses. Once V_IDis

removed from the RESET# pin, all the previously pro-

tected sector groups are protected again. Figure 1

shows the algorithm, and Figure 22 shows the timing

diagrams, for this feature.

1. All protected sector groups unprotected (If WP# = V_IL,

the first or last sector will remain protected).

2. All previously protected sector groups are protected

once again.

Figure 1. Temporary Sector

Group Unprotect Operation

26

Am29LV256M

December 16, 2005

D A T A S H E E T

START

PLSCNT = 1

RESET# = V_ID

Protect all sector

groups: The indicated

portion of the sector

group protect algorithm

must be performed for all

unprotected sector

groups prior to issuing

the first sector group

unprotect address

RESET# = V_ID

Wait 1 μs

Temporary Sector

Group Unprotect

Mode

Temporary Sector

Group Unprotect

Mode

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Yes

Set up sector

group address

All sector

groups

No

protected?

Sector Group Protect:

Write 60h to sector

group address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

group address

Sector Group

Unprotect:

Wait 150 µs

Write 60h to sector

group address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector Group

Protect: Write 40h

to sector group

address twith A6 = 0,

A1 = 1, A0 = 0

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

Verify Sector Group

Unprotect: Write

40h to sector group

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector group address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector group

address with A6 = 1,

A1 = 1, A0 = 0

Data = 01h?

Yes

No

Yes

Set up

next sector group

address

Protect

another

sector group?

Yes

No

PLSCNT

= 1000?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

Last sector

group

verified?

No

Device failed

Write reset

command

Yes

Remove V_ID

from RESET#

Sector Group

Unprotect

Sector Group

Protect

Sector Group

Protect complete

Write reset

command

Algorithm

Sector Group

Unprotect complete

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

Am29LV256M

December 16, 2005

27

D A T A S H E E T

Customer Lockable: SecSi Sector NOT

SecSi (Secured Silicon) Sector Flash

Memory Region

Programmed or Protected At the Factory

Unless otherwise specified, the device is shipped such

that the customer may program and protect the

256-byte SecSi sector.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 256 bytes in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

The system may program the SecSi Sector using the

write-buffer, accelerated and/or unlock bypass meth-

ods, in addition to the standard programming com-

mand sequence. See Command Definitions.

Programming and protecting the SecSi Sector must be

used with caution since, once protected, there is no

procedure available for unprotecting the SecSi Sector

area and none of the bits in the SecSi Sector memory

space can be modified in any way.

AMD offers the device with the SecSi Sector either

customer lockable (standard shipping option) or fac-

tory locked (contact an AMD sales representative for

ordering information). The customer-lockable version

is shipped with the SecSi Sector unprotected, allowing

customers to program the sector after receiving the

device. The customer-lockable version also has the

SecSi Sector Indicator Bit permanently set to a “0.”

The factory-locked version is always protected when

shipped from the factory, and has the SecSi (Secured

Silicon) Sector Indicator Bit permanently set to a “1.”

Thus, the SecSi Sector Indicator Bit prevents cus-

tomer-lockable devices from being used to replace de-

vices that are factory locked. Note that the ACC

function and unlock bypass modes are not available

when the SecSi Sector is enabled.

The SecSi Sector area can be protected using one of

the following procedures:

Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is programmed, locked and

verified, the system must write the Exit SecSi Sector

Region command sequence to return to reading and

writing within the remainder of the array.

The SecSi sector address space in this device is allo-

cated as follows:

Table 5. SecSi Sector Contents

SecSi Sector

Address Range

Customer

Lockable

ESN Factory

Locked

ExpressFlash

Factory Locked

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

ESN or

determined by

customer

000000h–000007h

000008h–00007Fh

ESN

Determined by

customer

In devices with an ESN, the SecSi Sector is protected

when the device is shipped from the factory. The SecSi

Sector cannot be modified in any way. An ESN Factory

Locked device has an 16-byte random ESN at ad-

dresses 000000h–000007h. Please contact your local

AMD sales representative for details on ordering ESN

Factory Locked devices.

Determined by

customer

Unavailable

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the first sector (SA0).

This mode of operation continues until the system is-

sues the Exit SecSi Sector command sequence, or

until power is removed from the device. On power-up,

or following a hardware reset, the device reverts to

sending commands to sector SA0.

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service (Express

Flash Factory Locked). The devices are then shipped

from AMD’s factory with the SecSi Sector permanently

locked. Contact an AMD representative for details on

using AMD’s ExpressFlash service.

28

Am29LV256M

December 16, 2005

D A T A S H E E T

for command definitions). In addition, the following

hardware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system

noise.

START

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

RESET# =

V_IHor V_ID

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

Wait 1 μs

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

with A6 = 0,

Write reset

command

greater than V_LKO

.

A1 = 1, A0 = 0

Write Pulse “Glitch” Protection

SecSi Sector

Protect Verify

complete

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

Logical Inhibit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Figure 3. SecSi Sector Protect Verify

Power-Up Write Inhibit

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Tables 11 and 12

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 6–9. The

system must write the reset command to return the

device to reading array data.

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 6–9. To terminate reading CFI data,

the system must write the reset command.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

December 16, 2005

Am29LV256M

29

D A T A S H E E T

Table 6. CFI Query Identification String

Addresses (x16)

Data

Description

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

Table 7. System Interface String

Description

Addresses (x16)

Data

V

_CCMin. (write/erase)

1Bh

0027h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0036h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0007h

000Ah

0000h

0001h

0005h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

30

Am29LV256M

December 16, 2005

D A T A S H E E T

Table 8. Device Geometry Definition

Addresses (x16)

Data

Description

27h

0019h

Device Size = 2^Nbyte

28h

29h

0002h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0005h

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

Number of Erase Block Regions within device (01h = uniform device, 02h = boot

device)

2Ch

0001h

2Dh

2Eh

2Fh

30h

00FFh

0001h

0000h

0001h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

0000h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

35h

36h

37h

38h

0000h

39h

3Ah

3Bh

3Ch

0000h

December 16, 2005

Am29LV256M

31

D A T A S H E E T

Table 9. Primary Vendor-Specific Extended Query

Addresses (x16)

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII

Minor version number, ASCII

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

0008h

Process Technology (Bits 7-2) 0010b = 0.23 µm MirrorBit

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0004h

0000h

0001h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors in Bank

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

00B5h

00C5h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

0004h/

0005h

00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top

Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top

WP# protect

4Fh

50h

Program Suspend

0001h

00h = Not Supported, 01h = Supported

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Tables 11 and 12 define the valid register

command sequences. Writing incorrect address and

data values or writing them in the improper sequence

may place the device in an unknown state. A reset

command is then required to return the device to read-

ing array data.

first. Refer to the AC Characteristics section for timing

diagrams.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

After the device accepts an Erase Suspend command,

the device enters the erase-suspend-read mode, after

which the system can read data from any

32

Am29LV256M

December 16, 2005

D A T A S H E E T

non-erase-suspended sector. After completing a pro-

Table 12 shows the address and data requirements.

This method is an alternative to that shown in Table 3,

which is intended for PROM programmers and re-

quires V_IDon address pin A9. The autoselect com-

mand sequence may be written to an address that is

either in the read or erase-suspend-read mode. The

autoselect command may not be written while the de-

vice is actively programming or erasing.

gramming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See the Erase Suspend/Erase Resume

Commands section for more information.

The system must issue the reset command to return

the device to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase op-

eration, or if the device is in the autoselect mode. See

the next section, Reset Command, for more informa-

tion.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the autoselect command. The

device then enters the autoselect mode. The system

may read at any address any number of times without

initiating another autoselect command sequence:

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The Read-Only Operations table provides the read pa-

rameters, and Figure 13 shows the timing diagram.

A read cycle at address XX00h returns the manu-

facturer code.

Reset Command

Three read cycles at addresses 01h, 0Eh, and 0Fh

Writing the reset command resets the device to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

return the device code.

A read cycle to an address containing a sector ad-

dress (SA), and the address 02h on A7–A0 in word

mode returns 01h if the sector is protected, or 00h if

it is unprotected.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to the read

mode. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the de-

vice was previously in Erase Suspend).

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

the read mode. If the program command sequence is

written while the device is in the Erase Suspend mode,

writing the reset command returns the device to the

erase-suspend-read mode. Once programming be-

gins, however, the device ignores reset commands

until the operation is complete.

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area

containing an 8-word/16-byte random Electronic Serial

Number (ESN). The system can access the SecSi

Sector region by issuing the three-cycle Enter SecSi

Sector command sequence. The device continues to

access the SecSi Sector region until the system is-

sues the four-cycle Exit SecSi Sector command se-

quence. The Exit SecSi Sector command sequence

returns the device to normal operation. Tables 11 and

12 show the address and data requirements for both

command sequences. See also “SecSi (Secured Sili-

con) Sector Flash Memory Region” for further informa-

tion. Note that the ACC function and unlock bypass

modes are not available when the SecSi Sector is en-

abled.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If the de-

vice entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns the

device to the erase-suspend-read mode.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to the

read mode (or erase-suspend-read mode if the device

was in Erase Suspend).

Word/Byte Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Tables 11 and 12 show the

Note that if DQ1 goes high during a Write Buffer Pro-

gramming operation, the system must write the

Write-to-Buffer-Abort Reset command sequence to

reset the device for the next operation.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

December 16, 2005

Am29LV256M

33

D A T A S H E E T

address and data requirements for the word program

ated by first writing two unlock cycles. This is followed

by a third write cycle containing the Write Buffer Load

command written at the Sector Address in which pro-

gramming will occur. The fourth cycle writes the sector

address and the number of word locations, minus one,

to be programmed. For example, if the system will pro-

gram 6 unique address locations, then 05h should be

written to the device. This tells the device how many

write buffer addresses will be loaded with data and

therefore when to expect the Program Buffer to Flash

command. The number of locations to program cannot

exceed the size of the write buffer or the operation will

abort.

command sequence.

When the Embedded Program algorithm is complete,

the device then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7 or DQ6. Refer to the Write Operation Status sec-

tion for information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that the

SecSi Sector, autoselect, and CFI functions are un-

available when a program operation is in progress.

Note that a hardware reset immediately terminates

the program operation. The program command se-

quence should be reinitiated once the device has re-

turned to the read mode, to ensure data integrity.

The fifth cycle writes the first address location and

data to be programmed. The write-buffer-page is se-

lected by address bits A_MAX–A₄. All subsequent ad-

dress/data pairs must fall within the

selected-write-buffer-page. The system then writes the

remaining address/data pairs into the write buffer.

Write buffer locations may be loaded in any order.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

The write-buffer-page address must be the same for

all address/data pairs loaded into the write buffer.

(This means Write Buffer Programming cannot be per-

formed across multiple write-buffer pages. This also

means that Write Buffer Programming cannot be per-

formed across multiple sectors. If the system attempts

to load programming data outside of the selected

write-buffer page, the operation will abort.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Tables 11 and 12 show the requirements

for the command sequence.

Note that if a Write Buffer address location is loaded

multiple times, the address/data pair counter will be

decremented for every data load operation. The host

system must therefore account for loading a

write-buffer location more than once. The counter dec-

rements for each data load operation, not for each

unique write-buffer-address location. Note also that if

an address location is loaded more than once into the

buffer, the final data loaded for that address will be

programmed.

Once the specified number of write buffer locations

have been loaded, the system must then write the Pro-

gram Buffer to Flash command at the sector address.

Any other address and data combination aborts the

Write Buffer Programming operation. The device then

begins programming. Data polling should be used

while monitoring the last address location loaded into

the write buffer. DQ7, DQ6, DQ5, and DQ1 should be

monitored to determine the device status during Write

Buffer Programming.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. (See Table 9).

The write-buffer programming operation can be sus-

pended using the standard program suspend/resume

commands. Upon successful completion of the Write

Buffer Programming operation, the device is ready to

execute the next command.

Write Buffer Programming

Write Buffer Programming allows the system write to a

maximum of 16 words/32 bytes in one programming

operation. This results in faster effective programming

time than the standard programming algorithms. The

Write Buffer Programming command sequence is initi-

The Write Buffer Programming Sequence can be

aborted in the following ways:

34

Am29LV256M

December 16, 2005

D A T A S H E E T

Load a value that is greater than the page buffer

from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

size during the Number of Locations to Program

step.

Write to an address in a sector different than the

one specified during the Write-Buffer-Load com-

mand.

Write an Address/Data pair to

a

different

Accelerated Program

write-buffer-page than the one selected by the

Starting Address during the write buffer data load-

ing stage of the operation.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V

_HHon the WP#/ACC pin, the device automatically en-

Write data other than the Confirm Command after

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHfor operations

other than accelerated programming, or device dam-

age may result. WP# has an internal pullup; when un-

connected, WP# is at V_IH.

the specified number of data load cycles.

The abort condition is indicated by DQ1 = 1, DQ7 =

DATA# (for the last address location loaded), DQ6 =

toggle, and DQ5=0. A Write-to-Buffer-Abort Reset

command sequence must be written to reset the de-

vice for the next operation. Note that the full 3-cycle

Write-to-Buffer-Abort Reset command sequence is re-

quired when using Write-Buffer-Programming features

in Unlock Bypass mode.

Figure 5 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 16 for timing diagrams.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

December 16, 2005

Am29LV256M

35

D A T A S H E E T

Write “Write to Buffer”

command and

Sector Address

Part of “Write to Buffer”

Command Sequence

Write number of addresses

to program minus 1(WC)

and Sector Address

Write first address/data

Yes

WC = 0 ?

No

Write to a different

sector address

Abort Write to

Yes

Buffer Operation?

Write to buffer ABORTED.

Must write “Write-to-buffer

Abort Reset” command

sequence to return

No

Write next address/data pair

(Note 1)

to read mode.

WC = WC - 1

Write program buffer to

flash sector address

Notes:

1. When Sector Address is specified, any address in

the selected sector is acceptable. However, when

loading Write-Buffer address locations with data, all

addresses must fall within the selected Write-Buffer

Page.

Read DQ15 - DQ0 at

Last Loaded Address

2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

3. If this flowchart location was reached because

DQ5= “1”, then the device FAILED. If this flowchart

location was reached because DQ1= “1”, then the

Write to Buffer operation was ABORTED. In either

case, the proper reset command must be written

before the device can begin another operation. If

DQ1=1, write the

Yes

DQ7 and DQ15 = Data?

No

Write-Buffer-Programming-Abort-Reset

command. if DQ5=1, write the Reset command.

No

DQ1 = 1?

Yes

DQ5 and DQ13 = 1?

Yes

4. See Tables 11 and 12 for command sequences

required for write buffer programming.

Read DQ15 - DQ0 with

address = Last Loaded

Address

Yes

DQ7 and DQ15 = Data?

(Note 2)

No

FAIL or ABORT

PASS

(Note 3)

Figure 4. Write Buffer Programming Operation

Am29LV256M

36

December 16, 2005

D A T A S H E E T

Program Suspend/Program Resume

Command Sequence

The Program Suspend command allows the system to

interrupt a programming operation or a Write to Buffer

programming operation so that data can be read from

any non-suspended sector. When the Program Sus-

pend command is written during a programming pro-

cess, the device halts the program operation within 15

μs maximum (5μs typical) and updates the status bits.

Addresses are not required when writing the Program

Suspend command.

START

Write Program

Command Sequence

Data Poll

from System

Embedded

Program

After the programming operation has been sus-

pended, the system can read array data from any

non-suspended sector. The Program Suspend com-

mand may also be issued during a programming oper-

ation while an erase is suspended. In this case, data

may be read from any addresses not in Erase Sus-

pend or Program Suspend. If a read is needed from

the SecSi Sector area (One-time Program area), then

user must use the proper command sequences to

enter and exit this region.

algorithm

in progress

Verify Data?

Yes

No

Increment Address

Last Address?

Yes

The system may also write the autoselect command

sequence when the device is in the Program Suspend

mode. The system can read as many autoselect codes

as required. When the device exits the autoselect

mode, the device reverts to the Program Suspend

mode, and is ready for another valid operation. See

Autoselect Command Sequence for more information.

Programming

Completed

Note: See Tables 11 and 12 for program command

sequence.

After the Program Resume command is written, the

device reverts to programming. The system can deter-

mine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard pro-

gram operation. See Write Operation Status for more

information.

Figure 5. Program Operation

The system must write the Program Resume com-

mand to exit the Program Suspend mode and continue

the programming operation. Further writes of the Re-

sume command are ignored. Another Program Sus-

pend command can be written after the device has

resume programming.

December 16, 2005

Am29LV256M

37

D A T A S H E E T

When the Embedded Erase algorithm is complete, the

device returns to the read mode and addresses are no

longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, or DQ2.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Write address/data

XXXh/B0B0h

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once the device has returned to reading

array data, to ensure data integrity.

Command is also valid for

Erase-suspended-program

operations

Wait 15 ms

Autoselect and SecSi Sector

Read data as

required

read operations are also allowed

Figure 10 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 18 section for timing diagrams.

Data cannot be read from erase- or

program-suspended sectors

Done

No

reading?

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 12 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Yes

Write Program Resume

Command Sequence

Write address/data

XXXh/3030h

Device reverts to

operation prior to

Program Suspend

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Figure 6. Program Suspend/Program Resume

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Tables 11 and

12 show the address and data requirements for the

chip erase command sequence.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

the device to the read mode. The system must re-

write the command sequence and any additional ad-

dresses and commands. Note that the SecSi Sector,

autoselect, and CFI functions are unavailable when an

erase operation in is progress.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

38

Am29LV256M

December 16, 2005

D A T A S H E E T

ing edge of the final WE# pulse in the command

for erasure. This command is valid only during the sec-

tor erase operation, including the 50 µs time-out pe-

riod during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program

algorithm.

sequence.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. The system can determine the

status of the erase operation by reading DQ7, DQ6, or

DQ2 in the erasing sector. Refer to the Write Opera-

tion Status section for information on these status bits.

When the Erase Suspend command is written during

the sector erase operation, the device requires a typi-

cal of 5 μs (maximum of 20 μs) to suspend the erase

operation. However, when the Erase Suspend com-

mand is written during the sector erase time-out, the

device immediately terminates the time-out period and

suspends the erase operation.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

After the erase operation has been suspended, the

device enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Figure 10 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 18 section for timing diagrams.

START

After an erase-suspended program operation is com-

plete, the device returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard word program operation.

Refer to the Write Operation Status section for more

information.

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

Autoselect Mode and Autoselect Command Sequence

sections for details.

Erase

algorithm

in progress

No

Data = FFh?

To resume the sector erase operation, the system

must write the Erase Resume command. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the chip

has resumed erasing.

Yes

Erasure Completed

Note: During an erase operation, this flash device per-

forms multiple internal operations which are invisible

to the system. When an erase operation is suspended,

any of the internal operations that were not fully com-

pleted must be restarted. As such, if this flash device

is continually issued suspend/resume commands in

rapid succession, erase progress will be impeded as a

function of the number of suspends. The result will be

a longer cumulative erase time than without suspends.

Note that the additional suspends do not affect device

reliability or future performance. In most systems rapid

erase/suspend activity occurs only briefly. In such

cases, erase performance will not be significantly im-

pacted.

Notes:

1. See Tables 11 and 12 for program command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Table 10. Erase Operation

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

December 16, 2005

Am29LV256M

39

D A T A S H E E T

Command Definitions

Table 11. Command Definitions (x16 Mode, BYTE# = V_IH)

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

Manufacturer ID

1

4

RA

XXX

555

RD

F0

AA

2AA

55

555

90

X00

X01

0001

227E

Device ID (Note 9)

X0E 2212 X0F 2201

SecSi^TMSector Factory Protect

(Note 10)

4

555

AA

2AA

55

555

90

X03

(Note 10)

00/01

Sector Group Protect Verify

(Note 12)

(SA)X02

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

1

3

2

6

1

555

SA

AA

29

2AA

55

555

SA

88

90

A0

25

XXX

PA

00

PD

WC

Write to Buffer (Note 11)

Program Buffer to Flash

Write to Buffer Abort Reset (Note 13)

Unlock Bypass

SA

PA

PD

WBL

PD

555

XXX

555

XXX

55

AA

A0

90

2AA

PA

55

PD

00

55

555

F0

20

Unlock Bypass Program (Note 14)

Unlock Bypass Reset (Note 15)

Chip Erase

XXX

2AA

AA

B0

30

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Program/Erase Suspend (Note 16)

Program/Erase Resume (Note 17)

CFI Query (Note 18)

98

Legend:

X = Don’t care

RA = Read Address of the memory location to be read.

RD = Read Data read from location RA during read operation.

PA = Program Address. Addresses latch on the falling edge of the WE#

or CE# pulse, whichever happens later.

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A23–A15 uniquely select any sector.

WBL = Write Buffer Location. Address must be within the same write

buffer page as PA.

WC = Word Count. Number of write buffer locations to load minus 1.

PD = Program Data for location PA. Data latches on the rising edge of

WE# or CE# pulse, whichever happens first.

Notes:

1. See Table 1 for description of bus operations.

lowest address sector, the data is 88h for factory locked and 08h

for not factor locked.

2. All values are in hexadecimal.

11. The total number of cycles in the command sequence is

determined by the number of words written to the write buffer. The

maximum number of cycles in the command sequence is 21.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD, PD and WC.

12. The data is 00h for an unprotected sector and 01h for a protected

sector.

5. Unless otherwise noted, address bits A23–A11 are don’t cares.

13. Command sequence resets device for next command after

aborted write-to-buffer operation.

6. No unlock or command cycles required when device is in read

mode.

14. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when the device is in the autoselect mode, or if DQ5 goes high

while the device is providing status information.

15. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

16. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

8. The fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect

Command Sequence section for more information.

9. The device ID must be read in three cycles.

17. The Erase Resume command is valid only during the Erase

Suspend mode.

10. If WP# protects the highest address sector, the data is 98h for

factory locked and 18h for not factory locked. If WP# protects the

18. Command is valid when device is ready to read array data or when

device is in autoselect mode.

40

Am29LV256M

December 16, 2005

D A T A S H E E T

Table 12. Command Definitions (x8 Mode, BYTE# = V_IL)

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Fourth

Fifth

Sixth

Addr Data Addr Data

Addr

Data

Addr

Data

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

Manufacturer ID

1

4

RA

RD

F0

XXX

AAA

AA

555

55

AAA

90

X00

X02

01

7E

Device ID (Note 9)

X1C

12

X1E

01

SecSi^TMSector Factory Protect

(Note 10)

4

AAA

AA

555

55

AAA

90

X06

(Note 10)

00/01

Sector Group Protect Verify

(Note 12)

(SA)X04

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

1

3

2

6

1

AAA

SA

AA

29

555

55

AAA

SA

88

90

A0

25

XXX

PA

00

PD

BC

Write to Buffer (Note 11)

Program Buffer to Flash

Write to Buffer Abort Reset (Note 13)

Unlock Bypass

SA

PA

PD

WBL

PD

AAA

XXX

AAA

XXX

AA

A0

90

555

PA

55

PD

00

55

AAA

F0

20

Unlock Bypass Program (Note 14)

Unlock Bypass Reset (Note 15)

Chip Erase

XXX

555

AA

B0

30

AAA

80

AAA

AA

555

55

AAA

SA

10

30

Sector Erase

Program/Erase Suspend (Note 16)

Program/Erase Resume (Note 17)

CFI Query (Note 18)

98

Legend:

X = Don’t care

RA = Read Address of the memory location to be read.

RD = Read Data read from location RA during read operation.

PA = Program Address. Addresses latch on the falling edge of the WE#

or CE# pulse, whichever happens later.

SA = Sector Address of sector to be verified (in autoselect mode) or

erased. Address bits A23–A15 uniquely select any sector.

WBL = Write Buffer Location. Address must be within the same write

buffer page as PA.

BC = Byte Count. Number of write buffer locations to load minus 1.

PD = Program Data for location PA. Data latches on the rising edge of

WE# or CE# pulse, whichever happens first.

Notes:

1. See Table 1 for description of bus operations.

lowest address sector, the data is 88h for factory locked and 08h

for not factor locked.

2. All values are in hexadecimal.

11. The total number of cycles in the command sequence is

determined by the number of bytes written to the write buffer. The

maximum number of cycles in the command sequence is 37.

3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

4. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

12. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

5. Unless otherwise noted, address bits A22–A11 are don’t cares.

13. Command sequence resets device for next command after

aborted write-to-buffer operation.

6. No unlock or command cycles required when device is in read

mode.

14. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when the device is in the autoselect mode, or if DQ5 goes high

while the device is providing status information.

15. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

16. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation.

8. The fourth cycle of the autoselect command sequence is a read

cycle. Data bits DQ15–DQ8 are don’t care. See the Autoselect

Command Sequence section for more information.

9. The device ID must be read in three cycles.

17. The Erase Resume command is valid only during the Erase

Suspend mode.

10. If WP# protects the highest address sector, the data is 98h for

factory locked and 18h for not factory locked. If WP# protects the

18. Command is valid when device is ready to read array data or when

device is in autoselect mode.

December 16, 2005

Am29LV256M

41

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 13 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine

whether an Embedded Program or Erase operation is

in progress or has been completed.

valid data, the data outputs on DQ0–DQ6 may be still

invalid. Valid data on DQ0–DQ7 will appear on suc-

cessive read cycles.

Table 13 shows the outputs for Data# Polling on DQ7.

Figure 7 shows the Data# Polling algorithm. Figure 19

in the AC Characteristics section shows the Data#

Polling timing diagram.

DQ7: Data# Polling

START

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether the device is in Erase

Suspend. Data# Polling is valid after the rising edge of the

final WE# pulse in the command sequence.

Read DQ15–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then the device returns to the

read mode.

Yes

DQ7 and DQ15

= Data?

No

DQ5 and DQ13

= 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ15–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

device returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 and DQ15

= Data?

No

PASS

FAIL

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 7. Data# Polling Algorithm

42

Am29LV256M

December 16, 2005

D A T A S H E E T

After an erase command sequence is written, if all sectors

RY/BY#: Ready/Busy#

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling).

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or in the erase-suspend-read mode. Table 13

shows the outputs for RY/BY#.

DQ6: Toggle Bit I

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Table 13 shows the outputs for Toggle Bit I on DQ6.

Figure 8 shows the toggle bit algorithm. Figure 20 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 21 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

December 16, 2005

Am29LV256M

43

D A T A S H E E T

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

START

Read DQ7–DQ0

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 13 to compare out-

puts for DQ2 and DQ6.

Read DQ7–DQ0

No

Toggle Bit

= Toggle?

Yes

Figure 8 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the RY/BY#: Ready/Busy# sub-

section. Figure 20 shows the toggle bit timing diagram.

Figure 21 shows the differences between DQ2 and

DQ6 in graphical form.

No

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

Reading Toggle Bits DQ6/DQ2

Refer to Figure 8 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Program/Erase

Operation Complete

Complete, Write

Reset Command

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Note: The system should recheck the toggle bit even if

DQ5 = “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

Figure 8. Toggle Bit Algorithm

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

44

Am29LV256M

December 16, 2005

D A T A S H E E T

other system tasks. In this case, the system must start

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 8).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program, erase, or

write-to-buffer time has exceeded a specified internal

pulse count limit. Under these conditions DQ5 produces a

“1,” indicating that the program or erase cycle was not suc-

cessfully completed.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

In all these cases, the system must write the reset

command to return the device to the reading the array

(or to erase-suspend-read if the device was previously

in the erase-suspend-program mode).

Table 13 shows the status of DQ3 relative to the other

status bits.

DQ3: Sector Erase Timer

DQ1: Write-to-Buffer Abort

DQ1 indicates whether a Write-to-Buffer operation

was aborted. Under these conditions DQ1 produces a

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

“1”.

The

system

must

issue

the

Write-to-Buffer-Abort-Reset command sequence to re-

turn the device to reading array data. See Write Buffer

Table 13. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

DQ1 RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Program-Suspended

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

N/A

Invalid (not allowed)

Data

1

0

Program

Suspend

Mode

Program-

Sector

Suspend

Non-Program

Read

Suspended Sector

Erase-Suspended

1

No toggle

Toggle

0

N/A

Toggle

N/A

Erase-

Sector

Suspend

Erase

Suspend

Mode

Non-EraseSuspended

Read

Data

Sector

Erase-Suspend-Program

(Embedded Program)

DQ7#

0

N/A

Busy (Note 3)

Abort (Note 4)

DQ7#

Toggle

0

N/A

0

1

0

Write-to-

Buffer

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

December 16, 2005

Am29LV256M

45

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

+0.8 V

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

–0.5 V

–2.0 V

Voltage with Respect to Ground

V

_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

V_IO. . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

20 ns

A9, OE#, ACC, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

Figure 9. Maximum Negative

Overshoot Waveform

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 9. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 10.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2. Minimum DC input voltage on pins A9, OE#, ACC, and

RESET# is –0.5 V. During voltage transitions, A9, OE#,

ACC, and RESET# may overshoot V_SSto –2.0 V for

periods of up to 20 ns. See Figure 9. Maximum DC input

voltage on pin A9, OE#, ACC, and RESET# is +12.5 V

which may overshoot to +14.0 V for periods up to 20 ns.

2.0 V

20 ns

Figure 10. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Supply Voltages

V

_CC(regulated voltage range) . . . . . . . . . . . 3.0–3.6 V

_CC(full voltage range) . . . . . . . . . . . . . . . . 2.7–3.6 V

_IO(Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1.65–3.6 V

Notes:

1. Operating ranges define those limits between which the

functionality of the device is guaranteed.

2. See Ordering Information section for valid V_CC/V_IOrange

combinations. The I/Os will not operate at 3 V when

V_IO=1.8 V.

46

Am29LV256M

December 16, 2005

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

(Notes)

Input Load Current (1)

A9, ACC Input Load Current

Output Leakage Current

Reset Leakage Current

V

_IN= V_SSto V_CC

,

I_LI

I_LIT

I_LO

I_LR

1.0

35

µA

_CC= V_{CC max}

V_CC= V_{CC max}; A9 = 12.5 V

V

_OUT= V_SSto V_CC

,

1.0

_CC= V_{CC max}

V_CC= V_{CC max}; RESET# = 12.5 V

CE# = V_IL,OE# = V_IH,

35

34

43

50

80

20

40

60

5

1 MHz

5 MHz

3

13

4

V_CCActive Read Current

(2, 3)

I_CC1

I_CC2

I_CC3

mA

1 MHz

V_CCInitial Page Read Current (2, 3) CE# = V_IL,OE# = V_IH

V_CCIntra-Page Read Current (2, 3) CE# = V_IL,OE# = V_IH

10 MHz

33 MHz

40

3

6

I_CC4

I_CC5

I_CC6

V_CCActive Write Current (3, 4)

V_CCStandby Current (3)

V_CCReset Current (3)

CE# = V_IL,OE# = V_IH

50

1

mA

µA

CE#, RESET# = V_CC0.3 V, WP# = V_IH

RESET# = V_SS0.3 V, WP# = V_IH

1

5

V

_IH= V_CC0.3 V; V_IL= V_SS0.3 V,

I_CC7

Automatic Sleep Mode (3, 5)

1

5

µA

WP# = V_IH

V_IL1

V_IH1

V_IL2

V_IH2

V_HH

Input Low Voltage 1(6, 7)

–0.5

1.9

0.8

V

Input High Voltage 1 (6, 7)

Input Low Voltage 2 (6, 8)

V_CC+ 0.5

0.3 x V_IO

V_IO+ 0.5

12.5

–0.5

1.9

Input High Voltage 2 (6, 8)

Voltage for ACC Program Acceleration

V_CC= 2.7 –3.6 V

11.5

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V

_CC= 2.7 –3.6 V

11.5

12.5

V

V_OL

V_OH1

V_OH2

V_LKO

Output Low Voltage (10)

I_OL= 4.0 mA, V_CC= V_{CC min}= V_IO

I_OH= –2.0 mA, V_CC= V_{CC min}= V_IO

I_OH= –100 µA, V_CC= V_{CC min}= V_IO

0.15 x V_IO

V

0.85 V_IO

V_IO–0.4

2.3

Output High Voltage

Low V_CCLock-Out Voltage (9)

2.5

Notes:

1. On the WP#/ACC pin only, the maximum input load current when

5. Automatic sleep mode enables the low power mode when

addresses remain stable for t_ACC+ 30 ns.

WP# = V_ILis 5.0 µA.

2. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at

V_IH.

6. If V_IO< V_CC, maximum V_ILfor CE# and DQ I/Os is 0.3 V_IO.

Maximum V_IHfor these connections is V_IO+ 0.3 V

3. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

7. V_CCvoltage requirements.

8. V_IOvoltage requirements.

9. Not 100% tested

4. I_CCactive while Embedded Erase or Embedded Program is in

progress.

10. Includes RY/BY#

December 16, 2005

Am29LV256M

47

D A T A S H E E T

TEST CONDITIONS

Table 14. Test Specifications

Test Condition All Speeds

Output Load 1 TTL gate

3.3 V

Unit

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

pF

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

C

L

6.2 kΩ

0.0–3.0

Input timing measurement

reference levels (See Note)

1.5

V

Output timing measurement

reference levels

0.5 V_IO

Note: Diodes are IN3064 or equivalent.

Note: If V_IO< V_CC, the reference level is 0.5 V_IO.

Figure 11. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Changing, State Unknown

Don’t Care, Any Change Permitted

Does Not Apply

Center Line is High Impedance State (High Z)

3.0 V

1.5 V

0.5 V_IOV

Input

Measurement Level

Output

0.0 V

Note: If V_IO< V_CC, the input measurement reference level is 0.5 V_IO.

Figure 12. Input Waveforms and

Measurement Levels

48

Am29LV256M

December 16, 2005

D A T A S H E E T

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

JEDEC Std. Description

Test Setup

103, 103R

113R

113

123R

123

Unit

t_AVAV

t_AVQV

t_ELQV

t_RCRead Cycle Time (Note 1)

t_ACCAddress to Output Delay

Min

100

110

120

ns

CE#,

OE# = V_IL

Max

100

110

ns

t_CEChip Enable to Output Delay

t_PACCPage Access Time

OE# = V_ILMax

100

30

110

40

ns

Max

30

40

t_GLQV

t_EHQZ

t_OEOutput Enable to Output Delay

30

40

Chip Enable to Output High Z

(Note 1)

t_DF

Max

16

ns

Output Enable to Output High Z

(Note 1)

t_GHQZ

t_DF

Output Hold Time From Addresses,

t_OHCE# or OE#, Whichever Occurs

First

t_AXQX

Min

0

ns

Read

Min

0

ns

Output Enable

t_OEHHold Time

Toggle and

Data# Polling

10

(Note 1)

Notes:

1. Not 100% tested.

2. See Figure 11 and Table 14 for test specifications.

3. AC specifications listed are tested with V_IO= V_CC. Contact AMD for information on AC operation with V_IO≠ V_CC

t_RC

Addresses Stable

t_ACC

Addresses

CE#

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 13. Read Operation Timings

December 16, 2005

Am29LV256M

49

D A T A S H E E T

AC CHARACTERISTICS

Same Page

AMax-A3

A2-A0*

Ad

Aa

t_ACC

Ab

t_PACC

Ac

t_PACC

Data Bus

Qa

Qb

Qc

Qd

CE#

OE#

* Figure shows word mode. Addresses are A1–A-1 for byte mode.

Figure 14. Page Read Timings

50

Am29LV256M

December 16, 2005

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std.

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note:

1. Not 100% tested.

2. AC specifications listed are tested with V_IO= V_CC. Contact AMD for information on AC operation with V_IO≠ V_CC.

RY/BY#

CE#, OE#

t_RH

RESET#

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 15. Reset Timings

December 16, 2005

Am29LV256M

51

D A T A S H E E T

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

103, 103R 113, 113R 123, 123R

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

100

110

0

120

t_AVWL

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

45

ns

t_WLAX

ns

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

45

0

ns

Data Hold Time

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

µs

sec

ns

µs

ns

µs

CE# Hold Time

t_WP

Write Pulse Width

35

t_WPH

Write Pulse Width High

Write Buffer Program Operation (Notes 2, 3)

30

240

7.5

15

Per Byte

Effective Write Buffer Program Operation

(Notes 2, 4)

Per Word

Per Byte

6.25

12.5

60

Accelerated Effective Write Buffer Program

Operation (Notes 2, 4)

t_WHWH1

Per Word

Byte

Single Byte/Word

Program Operation (Note 2, 5)

Word

60

Byte

54

Accelerated Single Byte/Word

Programming Operation (Note 2, 5)

Word

54

t_WHWH2

t_WHWH2Sector Erase Operation (Note 2)

0.5

250

50

t_VHH

t_VCS

t_BUSY

V_HHRise and Fall Time (Note 1)

V_CCSetup Time (Note 1)

Erase/Program Valid to RY/BY# Delay

Program Valid Before Status Polling (Note 7)

100

110

4

120

t_POLL

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. Byte/Word programming specification is based upon a single word/byte programming operation not utilizing the write buffer.

6. AC specifications listed are tested with V_IO= V_CC. Contact AMD for information on AC operation with V_IO≠ V_CC.

7. When using the program suspend/resume feature, if the suspend command is issued within t_POLL, t_POLLmust be fully

re-applied upon resuming the programming operation. If the suspend command is issued after t_POLL, t_POLLis not required

again prior to reading the status bits upon resuming.

52

Am29LV256M

December 16, 2005

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_POLL

t_WP

WE#

Data

t_WPH

t_WHWH1

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

2. Illustration shows device in word mode.

Figure 16. Program Operation Timings

V_HH

V_ILor V_IH

ACC

t_VHH

Figure 17. Accelerated Program Timing Diagram

December 16, 2005

Am29LV256M

53

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

2. These waveforms are for the word mode.

Figure 18. Chip/Sector Erase Operation Timings

54

Am29LV256M

December 16, 2005

D A T A S H E E T

AC CHARACTERISTICS

t_RC

VA

Addresses

VA

t_POLL

t_ACC

t_CE

CE#

t_CH

t_OE

OE#

t_OEH

t_DF

WE#

t_OH

High Z

DQ15 and DQ7

Valid Data

Complement

True

DQ14–DQ8, DQ6–DQ0

RY/BY#

Status Data

True

Valid Data

Status Data

t_BUSY

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

December 16, 2005

Am29LV256M

55

D A T A S H E E T

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_CEPH

t_OEH

WE#

t_OEPH

OE#

t_DH

t_OE

Valid

Status

Valid

Status

Valid

Status

Valid Data

DQ6 & DQ14/

DQ2 & DQ10

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 21. DQ2 vs. DQ6

56

Am29LV256M

December 16, 2005

D A T A S H E E T

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

Description

All Speed Options

Unit

t_VIDR

V_IDRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

4

µs

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 22. Temporary Sector Group Unprotect Timing Diagram

December 16, 2005

Am29LV256M

57

D A T A S H E E T

AC CHARACTERISTICS

V

ID

IH

V

RESET#

SA, A6,

A1, A0

Valid*

Sector Group Protect or Unprotect

6060h 6060h

Valid*

Status

Verify

4040h

Data

Sector Group Protect: 150 µs,

Sector Group Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Group Protect and Unprotect Timing Diagram

58

Am29LV256M

December 16, 2005

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

103, 103R 113, 113R 123, 123R Unit

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

100

110

0

120

ns

t_AVWL

t_ELAX

t_DVEH

t_EHDX

t_AH

45

0

t_DS

t_DH

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

Min

Typ

0

ns

µs

WE# Hold Time

CE# Pulse Width

45

t_CPH

CE# Pulse Width High

Write Buffer Program Operation (Notes 2, 3)

30

240

7.5

15

Per Byte

Per Word

Per Byte

Per Word

Byte

Effective Write Buffer Program Operation

(Notes 2, 4)

6.25

12.5

60

Effective Accelerated Write Buffer

Program Operation (Notes 2, 4)

t_WHWH1

Single Byte/Word

Program Operation (Note 2, 5)

Word

60

Accelerated Single Byte/Word

Programming Operation

(Note 2, 5)

Byte

54

Word

Typ

54

µs

t_WHWH2Sector Erase Operation (Note 2)

Typ

0.5

4

sec

µs

t_WHWH2

t_POLLProgram Valid before Status Polling (Note 7)

Max

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

3. For 1–16 words/1–32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.

6. AC listed are tested with V_IO= V_CC. Contact AMD for information on AC operation with V_IO≠ V_CC.

7. When using the program suspend/resume feature, if the suspend command is issued within t_POLL, t_POLLmust be fully re-applied

upon resuming the programming operation. If the suspend command is issued after t_POLL, t_POLLis not required again prior to

reading the status bits upon resuming.

December 16, 2005

Am29LV256M

59

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_AS

t_AH

t_WH

WE#

OE#

t_POLL

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#,

DQ15

D_OUT

Data

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 24. Alternate CE# Controlled Write (Erase/Program)

Operation Timings

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

60

Am29LV256M

December 16, 2005

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1)

Max (Note 2)

Unit

sec

µs

Comments

Sector Erase Time

Chip Erase Time

0.5

256

60

3.5

512

600

540

Excludes 00h programming

prior to erasure (Note 6)

Byte

Word

Byte

Single Byte/Word

Program Time (Note 3)

60

µs

Accelerated Single Byte/Word

Program Time

(Note 3)

54

µs

Word

54

540

µs

Total Write Buffer Program

Time (Note 4)

240

1200

Excludes system level

overhead (Note 7)

Per Byte

Per Word

7.5

15

38

75

µs

Effective Write Buffer Program

Time (Note 5)

Total Accelerated Write Buffer

Program Time (Note 4)

200

1040

µs

Effective Accelerated Write

Buffer Program Time

(Note 5)

Per Byte

Per Word

6.25

12.5

252

33

65

µs

Chip Program Time

584

sec

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC. Programming specifications assume that

all bits are programmed to 00h.

2. Maximum values are measured at VCC = 3.0, worst case temperature. Maximum values are valid up to and including 100,000

program/erase cycles.

3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer.

4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.

5. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

7. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

11 for further information on command definitions.

8. The device has a minimum erase and program cycle endurance of 100,000 cycles.

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Setup

Typ

6

Max

7.5

5

Unit

pF

TSOP

BGA

C_IN

Input Capacitance

V_IN= 0

4.2

8.5

5.4

7.5

3.9

TSOP

BGA

12

6.5

9

C_OUT

Output Capacitance

V_OUT= 0

V_IN= 0

TSOP

BGA

C_IN2

Control Pin Capacitance

4.7

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

December 16, 2005

Am29LV256M

61

D A T A S H E E T

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

62

Am29LV256M

December 16, 2005

D A T A S H E E T

PHYSICAL DIMENSIONS

TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP)

NOTES:

PACKAGE

TS/TSR 56

JEDEC

MO-142 (B) EC

1

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.)

SYMBOL

MIN.

---

NOM.

---

MAX.

1.20

0.15

1.05

0.23

0.27

0.16

0.21

2

3

4

PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).

A

A1

A2

b1

b

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

0.05

0.95

0.17

0.10

---

1.00

0.20

0.22

---

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS

DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE

LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.

5

6

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE

MOLD PROTUSION IS 0.15 mm PER SIDE.

c1

c

---

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE

DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b

DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN

PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

D

19.90

18.30

20.00

18.40

20.20

18.50

D1

E

e

13.90

14.00

14.10

7

THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP.

0.50 BASIC

L

0.50

0˚

0.60

3˚

0.70

5˚

8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE

SEATING PLANE.

O

R

N

0.08

---

0.20

9

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

56

3160\38.10A

December 16, 2005

Am29LV256M

63

D A T A S H E E T

PHYSICAL DIMENSIONS

LAC064—64-Ball Fortified Ball Grid Array

18 x 12 mm Package

D1

D

A

0.20 C

2X

eD

H

G

F

E

D

C

B

A

8

7

6

5

4

3

2

1

7

SE

eE

E

E1

A1 CORNER ID.

(INK OR LASER)

A1

CORNER

1.00 0.5

B

6

SD

0.20

2X

C

NXφb

φ 0.25 M C A

7

TOP VIEW

B

A1

φ 0.10 M

C

CORNER

BOTTOM VIEW

0.25

C

A

A2

A1

SEATING PLANE

C

0.15 C

SIDE VIEW

NOTES:

PACKAGE

JEDEC

LAC 064

N/A

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

18.00 mm x 12.00 mm

PACKAGE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT

AS NOTED).

SYMBOL

MIN

NOM

---

MAX

NOTE

PROFILE HEIGHT

STANDOFF

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

---

1.40

---

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE

"D" DIRECTION.

0.40

0.60

---

SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE

"E" DIRECTION.

A2

---

BODY THICKNESS

BODY SIZE

D

18.00 BSC.

12.00 BSC.

7.00 BSC.

8

N IS THE TOTAL NUMBER OF SOLDER BALLS.

E

BODY SIZE

6

7

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

D1

E1

MATRIX FOOTPRINT

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER

SOLDER BALL IN THE OUTER ROW.

MD

ME

N

MATRIX SIZE D DIRECTION

MATRIX SIZE E DIRECTION

BALL COUNT

8

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN

THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,

RESPECTIVELY, SD OR SE = 0.000.

64

φb

0.50

0.60

0.70

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN

THE OUTER ROW, SD OR SE = e/2

eD

eE

1.00 BSC.

0.50 BSC.

NONE

BALL PITCH - D DIRECTION

BALL PITCH - E DIRECTION

SOLDER BALL PLACEMENT

8. NOT USED.

SD / SE

9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED

BALLS.

DEPOPULATED SOLDER BALLS

3243 \ 16-038.12d

64

Am29LV256M

December 16, 2005

D A T A S H E E T

REVISION SUMMARY

Revision A (August 3, 2001)

Revision B+2 (September 9, 2002)

Initial release as abbreviated Advance Information

data sheet.

Product Selector Guide, Ordering Information,

Read-Only Operations, Erase and Program

Operations, and Alternate CE# Controlled Erase

and Program Operations

Revision A+1 (September 12, 2001)

Ordering Information

Added regulated OPNs.

Changed package part number designation from WH

to PC.

Changed all OPNs that end with 4 or 9 to end with 3 or

8.

Physical Dimensions

Changed all package markings that contain combina-

tions that end with 4 or 9 to end with 3 or 8.

Added the TS056 and LAA064 packages.

Revision A+2 (October 3, 2001)

CFI

Global

Modified wording of last paragraph to read: “reading

array data.”

Corrected title from 64 Mbit to 256 Mbit. Added 120 ns

speed option.

Program Suspend/Program Resume Command

Sequence

Distinctive Characteristics

SecSi^TM(Secured Silicon) Sector region: Corrected

64-byte to 256-byte.

Changed 15 µs typical to maximum and added 5 µs

typical.

Erase Suspend/Erase Resume Commands

Connection Diagram

Changed typical from 20 µs to 5 µs and added a maxi-

mum of 20 µs.

Modified Fortified BGA ball grid to an 8 x 8 ball matrix.

Changed RFU (reserved for future use) balls to NC

(No Connection).

LAC064—64-Ball Fortified Ball Grid Array

Ordering Information

Added final package drawing.

Changed operating voltage range on 90 ns speed op-

tion to 3.0–3.6 V.

Revision B+3 (October 23, 2002)

SecSi (Secured Silicon) Sector Flash

Memory Region

Pin Description

Added A-1 description.

Added x8 address range.

Revision A+3 (March 25, 2002)

Physical Dimensions

Distinctive Characteristics

Modified drawing to show the actual number of balls

on device package.

Clarified description of Enhanced VersatileIO control.

Physical Dimensions

Revision B+4 (November 6, 2002)

Added drawing that shows both TS056 and TSR056

specifications.

Global

Removed the Enhanced VI/O option and changed it to

VI/O only.

Revision B (July 1, 2002)

Expanded data sheet to full specification version.

Product Selector Guide

Revision B+1 (July 10, 2002)

Removed the 98R, 108, 108R, 118, 118R, 128, and

128R Speed Options.

Ordering Information, Physical Dimensions

Modified Note #2.

Corrected package description to LAC064, 18 x 12

mm Fortified BGA.

Moved V_IOfrom far left side of the block diagram and

moved it to Input/Output Buffers.

DC Characteristics table

Deleted I_ACCspecification.

Ordering Information

Modified Order numbers and package markings to re-

flect the removal of speed options.

December 16, 2005

Am29LV256M

65

D A T A S H E E T

Figure 6. Program Suspend/Program Resume

Table 4. SecSi Sector Contents

Added x8 and x16

Change wait time to 15 μs.

Operating Ranges

Changed the V_IOsupply range to 1.65–3.6 V.

Corrected typos in V_IOranges.

Removed full voltage range.

Erase and Programming Performance

Changed the typicals and/or maximums of Chip Erase

Time, Effective Write Buffer Program Time, and Pro-

gram Time to TBD.

CMOS Compatible

Changed V_IH1and V_IH2minimum to 1.9.

Removed typos in notes.

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the factory.

Read-Only Characteristics

Added second bullet, SecSi sector-protect verify text

and figure 3.

Added note #3.

Hardware Reset, Erase and Program Operations,

Temporary Sector Unprotect, and Alternate CE#

Controlled Erase and Program Operations

Table 7. Device Geometry Definition

Changed the x16 data for 2Dh to 00FFh.

SecSi Sector Flash Memory Region, and Enter

SecSi Sector/Exit SecSi Sector Command

Sequence

Added Note.

Revision C (February 14, 2003)

Noted that the ACC function and unlock bypass modes

are not available when the SecSi sector is enabled.

Distinctive Characteristics

Corrected performance characteristics.

Byte/Word Program Command Sequence, Sector

Erase Command Sequence, and Chip Erase Com-

mand Sequence

Product Selector Guide

Removed 93R speed option.

Noted that the SecSi Sector, autoselect, and CFI

functions are unavailable when a program or erase

operation is in progress.

Added note 2.

Ordering Information

Corrected Valid Combination to reflect speed option

changes.

Common Flash Memory Interface (CFI)

Changed CFI website address.

Added Note.

Revision B+5 (November 11, 2002)

AC Characteristics

Product Selector Guide and Read Only Operations

Removed 93, 93R speed option.

Added a 30 ns Page Access time and Output Enable

Access time to the 113R and 123R Speed Options.

Added Note

Input values in the t_WHWH1 and t_WHWH2 parameters in

the Erase and Program Options table that were previ-

ously TBD. Also added notes 5 and 6.

Revision B+6 (December 2, 2002)

Global

Input values in the t_WHWH1 and t_WHWH2 parameters in

the Alternate CE# Controlled Erase and Program Op-

tions table that were previously TBD. Also added notes

5.

Added Sector Group Protection and added Table 4.

Product Selector Guide

Added V_IOs to table and removed Note #2

Erase and Programming Performance

Input values into table that were previously TBD.

Ordering Information

Added note 4.

Corrected typos in V_IOranges.

Removed Note.

66

Am29LV256M

December 16, 2005

D A T A S H E E T

Customer Lockable: SecSi Sector NOT

Revision C+1 (May 28, 2003)

Programmed or Protected at the Factory

Global

Removed second paragraph.

Converted to full datasheet version.

Enter SecSi Sector/Exit SecSi Sector Command

Sequence

Modified SecSi Sector Flash Memory Region section

to include ESN references.

Added (write buffer) to last sentence of first paragraph.

Erase and Programming Performance

Write Buffer Programming

Input values into table that were previously TBD.

Removed last paragraph.

Modified notes.

Table 10 & Table 12: Command Definitions

CMOS Compatible

Replaced the Addr information Program/Erase Sus-

pend and Program/Erase Resume from BA to XXX.

Corrected typos in table.

Erase Suspend/Erase Resume Commands

Erase and Program Operations and Alternate CE#

Controlled Erase and Program Operations

Added note on flash device performance during

suspend/erase mode.

Changed the typical for the Accelerated Effective Write

Buffer Program Operation for Byte and Word to 6.25

and 12.5.

AC Characteristics - Erase and Program

Operations

Added t_POLLinformation.

Revision C+2 (June 11, 2003)

AC Characteristics - Operation Timings Figures

Global

Updated Figure 16: Program Operation Timings,

Figure 19: Data# Polling Timings (During Embedded

Algorithms, and Figure 24: Alternate CE# Controlled

Write (Erase/Program) Operation Timings.

Modified speed grades available.

Revision C+3 (September 15, 2003)

Ordering Information

Trademarks

Added OPN note for ESN feature.

Updated information.

Tables 11 & 12 Command Definitions

Cover page and Title sheet

Changed definition BA to XXX for Program/Erase Sus-

pend (Note 16) and for Program/Erase Resume (Note

17).

Added notation referencing superseding documenta-

tion.

Revision C + 5 (October 27, 2004)

Program Suspend/Program Resume Command

Sequence

Ordering Information Table

Removed - program suspended sector is required

when writing this command.

Added Pb-free ordering option

Revision C + 6 (December 16, 2005)

AC Characteristics - Hardware Reset

This product has been retired and is not available for

designs. For new and current designs, S29GL256N

supersedes Am29LV256M and is the factory-recom-

mended migration path. Please refer to the

S29GL256N datasheet for specifications and ordering

information. Availability of this document is retained for

reference and historical purposes only.

Added information for t_RB.

AC Characteristics - Erase and Program

Operations

Added information for t_BUSY

.

Revision C + 4 (February 9, 2004)

Table 1 Device Bus Operations

Modified ACC column to replace instances of X to L/H.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

December 16, 2005

Am29LV256M

67


型号：	L256MH123RF
厂家：	AMD
描述：	256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBitTM 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/OTM Control 256兆位（ 16一M× 16位/ 32 ×8位） MirrorBitTM 3.0伏只统一部门快闪记忆体与VersatileI / OTM控制
文件：	总69页 (文件大小：1571K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

L256MH123RF [AMD]

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