P322DT10UI_技术文档

Am29PDS322D

Data Sheet

The following document contains information on Spansion memory products. Although the document

is marked with the name of the company that originally developed the specification, Spansion will

continue to offer these products to existing customers.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these

products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number 23569 Revision A Amendment 5 Issue Date December 4, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29PDS322D

32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V)

Simultaneous Read/Write Page-Mode Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

— 1 mA active read current at 20 MHz for intra-page

read

■

Simultaneous Read/Write operations

— 200 nA in standby or automatic sleep mode

— Data can be continuously read from one bank while

executing erase/program functions in other bank.

■

Minimum 1 million write cycles guaranteed per

sector

20 year data retention at 125°C

— Reliable operation for the life of the system

— Zero latency between read and write operations

■

Page Mode Operation

— 4 word page allows fast asynchronous reads

SOFTWARE FEATURES

Dual Bank architecture

■

Data Management Software (DMS)

— AMD-supplied software manages data programming,

enabling EEPROM emulation

— One 4 Mbit bank and one 28 Mbit bank

SecSi (Secured Silicon) Sector: Extra 64 KByte

sector

— Eases historical sector erase flash limitations

— Factory locked and identifiable: 16 byte Electronic

Serial Number available for factory secure, random

ID; verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

— Customer lockable: Can be read, programmed, or

erased just like other sectors. Once locked, data

cannot be changed

■

Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

■

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero.

HARDWARE FEATURES

■

Any combination of sectors can be erased

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

Package options

— 48-ball FBGA

■

Top or bottom boot block

Manufactured on 0.23 µm process technology

Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

■

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect

status

PERFORMANCE CHARACTERISTICS

■

High performance

— Access time as fast 40 ns (100 ns random access

time) at 1.8 V to 2.2 V V_CC

— Acceleration (ACC) function accelerates program

timing

— ACC voltage is 8.5 V to 12.5 V

Sector protection

— Random access time of 100 ns at 1.8 V to 2.2 V V_CC

will be required as customers migrate downward in

voltage

■

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

■

Ultra low power consumption (typical values)

— 2.5 mA active read current at 1 MHz for initial page

read

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

— 24 mA active read current at 10 MHz for initial page

read

— 0.5 mA active read current at 10 MHz for intra-page

read

Publication# 23569 Rev: A Amendment/5

Issue Date: December 4, 2006

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

D A T A S H E E T

GENERAL DESCRIPTION

The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash

memory organized as 2,097,152 words of 16 bits

each. This device is offered in a 48-ball FBGA pack-

age. The device is designed to be programmed in sys-

tem with standard system 1.8 V V_CCsupply. This

device can also be reprogrammed in standard

EPROM programmers.

other flash sector, or may permanently lock their own

code there.

DMS (Data Management Software) allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

is an advantage compared to systems where

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and soft-

ware integration efforts.

The Am29PDS322D offers fast page access time of

40 ns with random access time of 100 ns (at 1.8 V to

2.2 V V_CC), allowing operation of high-speed micropro-

cessors without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE), write

enable (WE), and output enable (OE) controls. The

page size is 4 words.

The device requires only a single 1.8 volt power sup-

ply for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation by dividing the memory

space into two banks. The device can improve overall

system performance by allowing a host system to pro-

gram or erase in one bank, then immediately and si-

multaneously read from the other bank, with zero

latency. This releases the system from waiting for the

completion of program or erase operations.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard. Commands are written to the command

register using standard microprocessor write timings.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or

erase operation is complete by using the device sta-

tus bits: RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The device is divided as shown in the following table:

Bank 1 Sectors

Quantity Size

Bank 2 Sectors

Quantity

Size

8

7

4 Kwords

56

32 Kwords

The sector erase architecture allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

32 Kwords

4 Mbits total

28 Mbits total

Am29PDS322D Features

Hardware data protection measures include a low

V_CCdetector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The SecSi (Secured Silicon) Sector is an extra 64

KByte sector capable of being permanently locked by

AMD or customers. The SecSi Indicator Bit (DQ7) is

permanently set to a 1 if the part is factory locked,

and set to a 0 if customer lockable. This way, cus-

tomer lockable parts can never be used to replace a

factory locked part.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the

standby mode. Power consumption is greatly re-

duced in both modes.

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both. Customer Lockable parts may utilize the SecSi

Sector as bonus space, reading and writing like any

2

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

TABLE OF CONTENTS

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Special Handling Instructions for FBGA Package .................... 5

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29PDS322D Device Bus Operations .............................8

Requirements for Reading Array Data ..................................... 8

Read Mode ............................................................................... 8

Random Read (Non-Page Mode Read) ............................................8

Page Mode Read ...................................................................... 9

Table 2. Page Word Mode ................................................................9

Writing Commands/Command Sequences .............................. 9

Accelerated Program Operation ........................................................9

Autoselect Functions .........................................................................9

Simultaneous Read/Write Operations with Zero Latency ......... 9

Standby Mode .......................................................................... 9

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode .............................................................. 10

Table 3. Am29PDS322DT Top Boot Sector Addresses ..................11

Table 4. Am29PDS322DT Top Boot SecSi Sector Address ...........12

Table 5. Am29PDS322DB Bottom Boot Sector Addresses ............12

Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address . . .14

Autoselect Mode..................................................................... 15

Table 7. Autoselect Codes (High Voltage Method) ........................15

Sector/Sector Block Protection and Unprotection .................. 16

Table 8. Top Boot Sector/Sector Block Addresses for

Sector Erase Command Sequence ........................................ 24

Erase Suspend/Erase Resume Commands ........................... 24

Figure 6. Erase Operation.............................................................. 25

Am29PDS322D Command Definitions . . . . . . . . 26

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 27

DQ7: Data# Polling ................................................................. 27

Figure 7. Data# Polling Algorithm .................................................. 27

RY/BY#: Ready/Busy#............................................................ 28

DQ6: Toggle Bit I .................................................................... 28

Figure 8. Toggle Bit Algorithm........................................................ 28

DQ2: Toggle Bit II ................................................................... 29

Reading Toggle Bits DQ6/DQ2 ............................................... 29

DQ5: Exceeded Timing Limits ................................................ 29

DQ3: Sector Erase Timer ....................................................... 29

Table 11. Write Operation Status ................................................... 30

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 31

Figure 9. Maximum Negative Overshoot Waveform ...................... 31

Figure 10. Maximum Positive Overshoot Waveform...................... 31

Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 31

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 11. I_CC1Current vs. Time (Showing Active and Automatic

Sleep Currents).............................................................................. 33

Figure 12. Typical I_CC1vs. Frequency............................................ 33

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13. Test Setup.................................................................... 34

Table 12. Test Specifications ......................................................... 34

Key to Switching Waveforms. . . . . . . . . . . . . . . . 34

Figure 14. Input Waveforms and Measurement Levels ................. 34

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 15. Conventional Read Operation Timings......................... 35

Figure 16. Page Mode Read Timings ............................................ 36

Hardware Reset (RESET#) .................................................... 37

Figure 17. Reset Timings............................................................... 37

Erase and Program Operations .............................................. 38

Figure 18. Program Operation Timings.......................................... 39

Figure 19. Accelerated Program Timing Diagram.......................... 39

Figure 20. Chip/Sector Erase Operation Timings .......................... 40

Figure 21. Back-to-back Read/Write Cycle Timings ...................... 41

Figure 22. Data# Polling Timings (During Embedded Algorithms). 41

Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 42

Figure 24. DQ2 vs. DQ6................................................................. 42

Temporary Sector Unprotect .................................................. 43

Figure 25. Temporary Sector Group Unprotect Timing Diagram ... 43

Figure 26. Sector Group Protect and Unprotect Timing Diagram .. 44

Alternate CE# Controlled Erase and Program Operations ..... 45

Figure 27. Alternate CE# Controlled Write (Erase/Program)

Protection/Unprotection ...................................................................16

Table 9. Bottom Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................................16

Write Protect (WP#) ................................................................ 17

Temporary Sector/Sector Block Unprotect ............................. 17

Figure 1. Temporary Sector Unprotect Operation........................... 17

Figure 2. Temporary Sector Group Unprotect Operation................ 18

Figure 3. In-System Sector Group Protect/Unprotect Algorithms ... 19

SecSi (Secured Silicon) Sector Flash Memory Region .......... 20

Factory Locked: SecSi Sector Programmed and Protected

at the Factory ..................................................................................20

Hardware Data Protection ...................................................... 20

Low V_CCWrite Inhibit .......................................................................20

Write Pulse “Glitch” Protection ........................................................21

Logical Inhibit ..................................................................................21

Power-Up Write Inhibit ....................................................................21

Command Definitions . . . . . . . . . . . . . . . . . . . . . 21

Reading Array Data ................................................................ 21

Reset Command ..................................................................... 21

Autoselect Command Sequence ............................................ 21

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 22

Word Program Command Sequence ..................................... 22

Unlock Bypass Command Sequence ..............................................22

Chip Erase Command Sequence ........................................... 22

Figure 4. Unlock Bypass Algorithm................................................. 23

Figure 5. Program Operation .......................................................... 23

Operation Timings.......................................................................... 46

Erase And Programming Performance. . . . . . . . 47

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 47

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48

FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

6 x 12 mm package ................................................................ 48

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49

December 4, 2006 23569A5

Am29PDS322D

3

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Part Number

Am29PDS322D

Speed Options

Standard Voltage Range: V_CC= 1.8–2.2 V

10

100

40

12

120

45

Max Random Address Access Time (ns)

Max Page Address Access Time (ns)

CE# Access Time (ns)

100

35

120

40

OE# Access Time (ns)

Note: See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

OE#

V

CC

SS

Mux

Upper Bank Address

A0–A20

Upper Bank

X-Decoder

RY/BY#

A0–A20

RESET#

STATE

CONTROL

&

COMMAND

REGISTER

Status

WE#

CE#

DQ0–DQ15

WP#/ACC

Mux

Control

DQ0–DQ15

X-Decoder

Lower Bank

A0–A20

Lower Bank Address

Mux

4

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

CONNECTION DIAGRAMS

48-Ball FBGA

Top View, Balls Facing Down

A6

B6

C6

D6

E6

F6

G6

H6

V_SS

A13

A12

A14

A15

A16

NC

DQ15

A5

A9

B5

A8

C5

D5

E5

F5

G5

H5

A10

A11

DQ7

DQ14

DQ13

DQ6

A4

B4

C4

D4

E4

F4

G4

H4

V_CC

WE# RESET#

NC

A19

DQ5

DQ12

DQ4

A3 B3

C3

D3

E3

F3

G3

H3

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

A2

A7

B2

C2

A6

D2

A5

E2

F2

G2

H2

A17

DQ0

DQ8

DQ9

DQ1

A1

A3

B1

A4

C1

A2

D1

A1

E1

A0

F1

G1

H1

V_SS

CE#

OE#

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compromised

if the package body is exposed to temperatures above

150°C for prolonged periods of time.

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory products

in FBGA packages.

December 4, 2006 23569A5

Am29PDS322D

5

D A T A S H E E T

PIN DESCRIPTION

LOGIC SYMBOL

A0–A20

= 21 Addresses inputs

21

DQ0–DQ15 = 16 Data inputs/outputs

A0–A20

16

CE#

OE#

WE#

= Chip Enable input

= Output Enable input

= Write Enable input

DQ0–DQ15

CE#

OE#

WE#

WP#/ACC = Hardware Write Protect/

Acceleration Input

WP#/ACC

RESET#

RY/BY#

RESET#

RY/BY#

V_CC

= Hardware Reset Pin input

= Ready/Busy output

= 1.8 volt-only single power supply

(see Product Selector Guide for

speed options and voltage

supply tolerances)

V_SS

NC

= Device Ground

= Pin Not Connected Internally

6

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29PDS322D

B

10

WM

I

N

OPTIONAL PROCESSING

Blank = Standard Processing

N

=

16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

PACKAGE TYPE

WM

=

48-Ball Fine-Pitch Ball Grid Array (FBGA)

0.80 mm pitch, 6 x 12 mm package (FBD048)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T

B

=

Top sector

Bottom sector

DEVICE NUMBER/DESCRIPTION

Am29PDS322D

32 Megabit (2 M x 16-Bit) CMOS Boot Sector Page Mode Flash Memory

1.8 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations for FBGA Package

Order Number Package Marking

Am29PDS322DT10,

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

P322DT10U,

P322DB10U

WMI

I

Am29PDS322DB10

Am29PDS322DT12,

Am29PDS322DB12

P322DT12U,

P322DB12U

WMI

I

December 4, 2006 23569A5

Am29PDS322D

7

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29PDS322D Device Bus Operations

Addresses

(Note 1)

Operation

Read

CE#

OE#

L

WE#

H

RESET# WP#/ACC

DQ0–DQ15

D_OUT

L

H

L/H

(Note 2)

H

A_IN

X

Write

L

H

L

H

D_IN

Standby

Output Disable

Reset

V_CC± 0.3 V

X

V_CC± 0.3 V

High-Z

L

H

L

L/H

X

L/H

X

SA, A6 = L,

A1 = H, A0 = L

Sector Protect (Note 1)

L

H

L

V_ID

L/H

D_IN

SA, A6 = H,

A1 = H, A0 = L

Sector Unprotect (Note 1)

Temporary Sector Unprotect

L

H

X

L

V_ID

(Note 2)

D_IN

X

A_IN

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 9.0–11.0 V, V_HH= 9.0 0.ꢀ V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

2. If WP#/ACC = V_IL, the two outermost boot sectors remain protected. If WP#/ACC = V_IH, the two outermost boot sector

protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block

Protection and Unprotection”. If WP#/ACC = V_HH,all sectors will be unprotected.

timing diagram. I_CC1in the DC Characteristics table

represents the active current specification for reading

To read array data from the outputs, the system must

array data.

Requirements for Reading Array Data

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

Read Mode

Random Read (Non-Page Mode Read)

should remain at V_IH.

The device has two control functions which must be

satisfied in order to obtain data at the outputs. CE# is

the power control and should be used for device selec-

tion. OE# is the output control and should be used to

gate data to the output pins if the device is selected.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. The device remains

enabled for read access until the command register

contents are altered.

Address access time (t_ACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (t_CE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output

pins. The output enable access time is the delay from

the falling edge of OE# to valid data at the output pins

(assuming the addresses have been stable for at least

See “Requirements for Reading Array Data” for more

information. Refer to the AC Read-Only Operations

table for timing specifications and to Figure 15 for the

t_ACC–t_OEtime).

8

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

Accelerated Program Operation

Page Mode Read

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

The device is capable of fast Page mode read and is

compatible with the Page mode Mask ROM read oper-

ation. This mode provides faster read access speed for

random locations within a page. The Page size of the

device is 4 words. The appropriate Page is selected by

the higher address bits A20–A2 and the LSB bits

A1–A0 determine the specific word within that page.

This is an asynchronous operation with the micropro-

cessor supplying the specific word location.

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

The random or initial page access is equal to t_ACCor

t_CEand subsequent Page read accesses (as long as

the locations specified by the microprocessor falls

within that Page) are equivalent to t_PACC. When CE# is

deasserted and reasserted for a subsequent access,

the access time is t_ACCor t_CE. Here again, CE# selects

the device and OE# is the output control and should be

used to gate data to the output pins if the device is se-

lected. Fast Page mode accesses are obtained by

keeping A2–A20 constant and changing A0 to A1 to

select the specific word within that page. See Figure

16 for timing specifications.

V

_HHfrom the ACC pin returns the device to normal op-

eration.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

The following table determines the specific word within

the selected page:

Simultaneous Read/Write Operations with

Zero Latency

Table 2. Page Word Mode

Word

A1

0

A0

0

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same bank (except the sector being

erased). Figure 21 shows how read and write cycles

may be initiated for simultaneous operation with zero

latency. I_CC6and I_CC7in the DC Characteristics table

represent the current specifications for read-while-pro-

gram and read-while-erase, respectively.

Word 0

Word 1

Word 2

Word 3

0

1

0

1

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are re-

quired to program a word, instead of four. The “Word

Program Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V_CC0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_CC0.3 V, the device will be in the standby mode,

but the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 2 indicates the address

space that each sector occupies.

I

_CC2in the DC Characteristics table represents the ac-

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

December 4, 2006 23569A5

Am29PDS322D

9

D A T A S H E E T

If the device is deselected during erasure or program-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

ming, the device draws active current until the

operation is completed.

I_CC3in the DC Characteristics table represents the

standby current specification.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC3). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current

will be greater.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

this mode when addresses remain stable for t_ACC

+

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

Automatic sleep mode current is drawn when CE# =

V_SS0.3 V and all inputs are held at V_CC0.3 V. If

CE# and RESET# voltages are not held within these

tolerances, the automatic sleep mode current will be

greater.

I_CC5in the DC Characteristics table represents the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 17 for the timing diagram.

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins are placed in the high

impedance state.

10

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

Table 3. Am29PDS322DT Top Boot Sector Addresses

Sector Address

A20–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA0

000000xxx

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

32

000000h–07FFFh

008000h–0FFFFh

010000h–17FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

December 4, 2006 23569A5

Am29PDS322D

11

D A T A S H E E T

Table 3. Am29PDS322DT Top Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

101100xxx

101101xxx

101110xxx

101111xxx

110000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

32

4

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1F8FFFh

1F9000h–1F9FFFh

1FA000h–1FAFFFh

1FB000h–1FBFFFh

1FC000h–1FCFFFh

1FD000h–1FDFFFh

1FE000h–1FEFFFh

1FF000h–1FFFFFh

4

Table 4. Am29PDS322DT Top Boot SecSi Sector Address

Sector Address A20–A12

111111xxx

Sector Size

(x16) Address Range

32

1F8000h–1FFFFh

Table 5. Am29PDS322DB Bottom Boot Sector Addresses

Sector Address

A20–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA0

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

4

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

008000h–00FFFFh

010000h–017FFFh

018000h–01FFFFh

020000h–027FFFh

028000h–02FFFFh

030000h–037FFFh

038000h–03FFFFh

SA1

SA2

4

SA3

4

SA4

4

SA5

4

SA6

4

SA7

4

SA8

32

SA9

SA10

SA11

SA12

SA13

SA14

12

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

Table 5. Am29PDS322DB Bottom Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

111000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

32

040000h–047FFFh

048000h–04FFFFh

050000h–057FFFh

058000h–05FFFFh

060000h–067FFFh

068000h–06FFFFh

070000h–077FFFh

078000h–07FFFFh

080000h–087FFFh

088000h–08FFFFh

090000h–097FFFh

098000h–09FFFFh

0A0000h–0A7FFFh

0A8000h–0AFFFFh

0B0000h–0B7FFFh

0B8000h–0BFFFFh

0C0000h–0C7FFFh

0C8000h–0CFFFFh

0D0000h–0D7FFFh

0D8000h–0DFFFFh

0E0000h–0E7FFFh

0E8000h–0EFFFFh

0F0000h–0F7FFFh

0F8000h–0FFFFFh

100000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

December 4, 2006 23569A5

Am29PDS322D

13

D A T A S H E E T

Table 5. Am29PDS322DB Bottom Boot Sector Addresses (Continued)

Sector Address

A20–A12

Sector Size

(Kwords)

(x16)

Address Range

Bank

Sector

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111xxx

32

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address

Sector Address

(x16)

A20–A12

Sector Size

Address Range

000000xxx

32

00000h-07FFFh

.

14

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

Table 7. In addition, when verifying sector protection,

Autoselect Mode

the sector address must appear on the appropriate

highest order address bits (see Tables 3 through 6).

Table 7 shows the remaining address bits that are

don’t care. When all necessary bits have been set as

required, the programming equipment may then read

the corresponding identifier code on DQ15–DQ0.

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ15–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 10. This method

does not require V_ID. Refer to the Autoselect Com-

mand Sequence section for more information.

When using programming equipment, the autoselect

mode requires V_ID(8.5 V to 12.5 V) on address pin A9.

Address pins A6, A1, and A0 must be as shown in

Table 7. Autoselect Codes (High Voltage Method)

A20 A11

to to

A8

to

A5

to

Description

CE# OE# WE# A12 A10 A9 A7 A6 A4 A3 A2 A1 A0

DQ15 to DQ0

Manufacturer ID:

AMD

L

H

X

V_ID

X

L

X

L

0001h

Device ID Word 1

Device ID Word 2

L

H

X

V_ID

X

L

X

L

H

L

227Eh

2206h

H

Device ID Word 3:

Top or Bottom Boot

2201h (Top Boot),

2200h (Bottom Boot)

L

H

X

V_ID

X

L

X

H

X

H

X

H

L

Sector Protection

Verification

XX01h (protected),

XX00h (unprotected)

SA

SecSi Indicator Bit

(DQ7),

WP# protects

highest address

sector

80h (factory locked),

00h (not factory locked)

L

H

X

V_ID

X

L

X

H

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, SA = Sector Address, X = Don’t care.

December 4, 2006 23569A5

Am29PDS322D

15

D A T A S H E E T

Table 9. Bottom Boot Sector/Sector Block

Addresses for Protection/Unprotection

Sector/Sector Block Protection and

Unprotection

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Tables

8 and 9).

Sector

Sector/Sector

Group

Sectors

SA70

A20–A12

111111XXX

11110XXXX

1110XXXXX

1101XXXXX

1100XXXXX

1011XXXXX

1010XXXXX

1001XXXXX

1000XXXXX

0111XXXXX

0110XXXXX

0101XXXXX

0100XXXXX

0011XXXXX

0010XXXXX

0001XXXXX

000011XXX

000000111

000000110

000000101

000000100

000000011

000000010

000000001

000000000

Block Size

64 (1x64) Kbytes

192 (3x64) Kbytes

256 (4x64) Kbytes

192 (3x64) Kbytes

8 Kbytes

SGA0

SGA1

SA69–SA67

SA66–SA63

SA62–SA59

SA58–SA55

SA54–SA51

SA50–SA47

SA46–SA43

SA42–SA39

SA38–SA35

SA34–SA31

SA30–SA27

SA26–SA23

SA22–SA19

SA18–SA15

SA14–SA11

SA10–SA8

SA7

SGA2

SGA3

SGA4

SGA5

Table 8. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection

SGA6

SGA7

Sector

Group

Sector/

Sector Block Size

SGA8

Sectors

SA0

A20–A12

000000XXX

00001XXXX

0001XXXXX

0010XXXXX

0011XXXXX

0100XXXXX

0101XXXXX

0110XXXXX

0111XXXXX

1000XXXXX

1001XXXXX

1010XXXXX

1011XXXXX

1100XXXXX

1101XXXXX

1110XXXXX

111100XXX

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

SGA9

SGA0

SGA1

64 (1x64) Kbytes

192 (3x64) Kbytes

256 (4x64) Kbytes

192 (3x64) Kbytes

8 Kbytes

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SA1–SA3

SA4–SA7

SA8–SA11

SA12–SA15

SA16–SA19

SA20–SA23

SA24–SA27

SA28–SA31

SA32–SA35

SA36–SA39

SA40–SA43

SA44–SA47

SA48–SA51

SA52–SA55

SA56–SA59

SA60–SA62

SA63

SGA2

SGA3

SGA4

SGA5

SGA6

SGA7

SGA8

SA6

8 Kbytes

SGA9

SA5

8 Kbytes

SGA10

SGA11

SGA12

SGA13

SGA14

SGA15

SGA16

SGA17

SGA18

SGA19

SGA20

SGA21

SGA22

SGA23

SGA24

SA4

8 Kbytes

SA3

8 Kbytes

SA2

8 Kbytes

SA1

8 Kbytes

SA0

8 Kbytes

The hardware sector protection feature disables both

program and erase operations in any sector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors. Sector protection and unprotection can be im-

plemented via two methods.

SA64

8 Kbytes

SA65

8 Kbytes

SA66

8 Kbytes

SA67

8 Kbytes

SA68

8 Kbytes

The primary method requires V_IDon the RESET# pin

only, and can be implemented either in-system or via

programming equipment. Figure 3 shows the algo-

rithms and Figure 26 shows the timing diagram. This

method uses standard microprocessor bus cycle tim-

ing. For sector unprotect, all unprotected sectors must

first be protected prior to the first sector unprotect

write cycle.

SA69

8 Kbytes

SA70

8 Kbytes

16

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

The alternate method intended only for programming

block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Tables

8 and 9).

equipment requires V_IDon address pin A9 and OE#.

This method is compatible with programmer routines

written for earlier AMD flash devices. Contact an AMD

representative for further details.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID(9.0 V – 11.0 V). During this mode,

formerly protected sectors can be programmed or

erased by selecting the sector addresses. Once V_IDis

removed from the RESET# pin, all the previously pro-

tected sectors are protected again. Figure 1 shows the

algorithm, and Figure 25 shows the timing diagrams,

for this feature.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is pro-

tected or unprotected. See the Autoselect Mode

section for details.

Write Protect (WP#)

The Write Protect function provides a hardware

method of protecting certain boot sectors without

using V_ID. This function is one of two provided by the

WP#/ACC pin.

START

RESET# = V_ID

(Note 1)

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in the two

“outermost” 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected

using the method described in “Sector/Sector Block

Protection and Unprotection”. The two outermost 8

Kbyte boot sectors are the two sectors containing the

lowest addresses in a bottom-boot-configured device,

or the two sectors containing the highest addresses in

a top-boot-configured device.

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Unprotect Completed

(Note 2)

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether the two outermost 8 Kbyte boot

sectors were last set to be protected or unprotected.

That is, sector protection or unprotection for these two

sectors depends on whether they were last protected

or unprotected using the method described in “Sec-

tor/Sector Block Protection and Unprotection”.

Notes:

1. All protected sectors unprotected (If WP#/ACC = V_IL,

outermost boot sectors will remain protected).

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

2. All previously protected sectors are protected once

again.

Temporary Sector/Sector Block Unprotect

(Note: For the following discussion, the term “sector”

applies to both sectors and sector blocks. A sector

Figure 1. Temporary Sector Unprotect Operation

December 4, 2006 23569A5

Am29PDS322D

17

D A T A S H E E T

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Temporary Sector

Group Unprotect

Completed (Note 2)

Notes:

1. All protected sector groups unprotected (If WP# = V_IL,

the first or last sector will remain protected).

2. All previously protected sector groups are protected

once again.

Figure 2. Temporary Sector Group Unprotect

Operation

18

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 1 μs

unprotect address

No

First Write

Cycle = 60h?

No

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Yes

Set up first sector

address

Sector Unprotect:

Wait 150 µs

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 15 ms

A1 = 1, A0 = 0

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

Increment

PLSCNT

No

PLSCNT

= 25?

Read from

sector address

with A6 = 1,

Data = 01h?

Yes

A1 = 1, A0 = 0

No

Yes

Set up

next sector

address

Yes

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

Device failed

No

Yes

Remove V_ID

from RESET#

No

Last sector

verified?

Device failed

Write reset

command

Yes

Remove V_ID

Sector Unprotect

Algorithm

from RESET#

Sector Protect

Algorithm

Sector Protect

complete

Write reset

command

Sector Unprotect

complete

Figure 3. In-System Sector Group Protect/Unprotect Algorithms

December 4, 2006 23569A5

Am29PDS322D

19

D A T A S H E E T

Customers may opt to have their code programmed by

SecSi (Secured Silicon) Sector Flash

Memory Region

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the permanently locked. Contact an AMD

representative for details on using AMD’s Express-

Flash service.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is 64 KBytes in length, and

uses a SecSi Sector Indicator Bit (DQ7) to indicate

whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional Flash memory space,

expanding the size of the available Flash array by 64

Kbytes. The SecSi Sector can be read, programmed,

and erased as often as required. The SecSi Sector area

can be protected using one of the following procedures:

AMD offers the device with the SecSi Sector either

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to utilize that

sector in any manner they choose. The customer-lock-

able version also has the SecSi Sector Indicator Bit

permanently set to a “0.” Thus, the SecSi Sector Indi-

cator Bit prevents customer-lockable devices from

being used to replace devices that are factory locked.

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 3, ex-

cept that RESET# may be at either V_IHor V_ID. This

allows in-system protection of the SecSi Sector

without raising any device pin to a high voltage.

Note that this method is only applicable to the SecSi

Sector.

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then use the alternate

method of sector protection described in the “Sec-

tor/Sector Block Protection and Unprotection” sec-

tion.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the first sector (SA0).

This mode of operation continues until the system is-

sues the Exit SecSi Sector command sequence, or

until power is removed from the device. On power-up,

or following a hardware reset, the device reverts to

sending commands to the boot sectors instead of the

SecSi sector

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region

command sequence to return to reading and writing

the remainder of the array.

The SecSi Sector protection must be used with cau-

tion since, once protected, there is no procedure

available for unprotecting the SecSi Sector area and

none of the bits in the SecSi Sector memory space

can be modified in any way.

Factory Locked: SecSi Sector Programmed and

Protected at the Factory

Hardware Data Protection

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is available preprogrammed with one of the

following:

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 10 for com-

mand definitions). In addition, the following hardware

data protection measures prevent accidental erasure

or programming, which might otherwise be caused by

spurious system level signals during V_CCpower-up

and power-down transitions, or from system noise.

■ A random, secure ESN only

■ Customer code through the ExpressFlash service

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

Low V_CCWrite Inhibit

In devices that have an ESN, a Bottom Boot device will

have the 16-byte ESN in the lowest addressable mem-

ory area at addresses 000000h–000007h. In the Top

Boot device the starting address of the ESN will be at

the bottom of the lowest 8 Kbyte boot sector at ad-

dresses 1F8000h–1F8007h.

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

20

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

writes are ignored until V_CCis greater than V_LKO. The

Logical Inhibit

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

greater than V_LKO

.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 10 defines the valid register command

sequences. Writing incorrect address and data val-

ues or writing them in the improper sequence resets

the device to reading array data.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to the read

mode. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the device to

the read mode. If the program command sequence is

written while the device is in the Erase Suspend mode,

writing the reset command returns the device to the

erase-suspend-read mode. Once programming be-

gins, however, the device ignores reset commands

until the operation is complete.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If the de-

vice entered the autoselect mode while in the Erase

Suspend mode, writing the reset command returns the

device to the erase-suspend-read mode.

After the device accepts an Erase Suspend command,

the device enters the erase-suspend-read mode, after

which the system can read data from any

non-erase-suspended sector. After completing a pro-

gramming operation in the Erase Suspend mode, the

system may once again read array data with the same

exception. See the Erase Suspend/Erase Resume

Commands section for more information.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to the

read mode (or erase-suspend-read mode if the device

was in Erase Suspend).

Autoselect Command Sequence

The system must issue the reset command to return

the device to the read (or erase-suspend-read) mode if

DQ5 goes high during an active program or erase op-

eration, or if the device is in the autoselect mode. See

the next section, Reset Command, for more informa-

tion.

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

Table 10 shows the address and data requirements.

This method is an alternative to that shown in Table 7,

which is intended for PROM programmers and re-

quires V_IDon address pin A9. The autoselect com-

mand sequence may be written to an address that is

either in the read or erase-suspend-read mode. The

autoselect command may not be written while the de-

vice is actively programming or erasing.

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The Read-Only Operations table provides the read pa-

rameters, and Figure 15 shows the timing diagram.

Reset Command

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect mode,

Writing the reset command resets the device to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

December 4, 2006 23569A5

Am29PDS322D

21

D A T A S H E E T

and the system may read any number of autoselect

from “0” back to a “1.” Attempting to do so may

cause the device to set DQ5 = 1, or cause the DQ7

and DQ6 status bits to indicate the operation was suc-

cessful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

codes without reinitiating the command sequence.

Table 10 shows the address and data requirements for

the command sequence. To determine sector protec-

tion information, the system must write to the appropri-

ate sector group address (SGA). Tables 3 and 5 show

the address range associated with each sector.

Unlock Bypass Command Sequence

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the de-

vice was previously in Erase Suspend).

The unlock bypass feature allows the system to pro-

gram words to the device faster than using the stan-

dard program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. The device

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 10 shows the requirements for the

command sequence.

Enter SecSi Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area

containing an 16-byte random Electronic Serial Num-

ber (ESN). The system can access the SecSi Sector

region by issuing the three-cycle Enter SecSi Sector

command sequence. The device continues to access

the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The

Exit SecSi Sector command sequence returns the de-

vice to normal operation. Table 10 shows the address

and data requirements for both command sequences.

See also “SecSi (Secured Silicon) Sector Flash Mem-

ory Region” for further information. Note that a hard-

ware reset (RESET#=V_IL) will reset the device to

reading array data.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h. The second cycle must contain the data 00h. The

device then returns to reading array data. See Figure

4 for the unlock bypass algorithm.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 10 shows the address

and data requirements for the program command se-

quence.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V

_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

When the Embedded Program algorithm is complete,

the device then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refer to the Write Operation

Status section for information on these status bits.

Figure 5 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 18 for timing diagrams.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once the device has returned to the read

mode, to ensure data integrity.

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

22

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

Start

555h/AAh

START

Set

Write Program

Command Sequence

Unlock

Bypass

Mode

2AAh/55h

Data Poll

from System

555h/20h

Embedded

Program

algorithm

in progress

XXXh/A0h

Verify Data?

Yes

No

Program Address/Program Data

Data#Polling Device

No

Increment Address

Last Address?

Yes

No

In

Verify Byte?

Yes

Unlock

Bypass

Program

Programming

Completed

No

Increment

Address

Last Address

?

Yes

Note: See Table 10 for program command sequence.

Programming Completed

Figure 5. Program Operation

(BA)XXXh/90h

Reset

Unlock

Bypass

Mode

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 10

shows the address and data requirements for the chip

erase command sequence.

XXXh/F0h

Figure 4. Unlock Bypass Algorithm

December 4, 2006 23569A5

Am29PDS322D

23

D A T A S H E E T

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses

are no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

data from the non-erasing sector. The system can de-

termine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing sector.

Refer to the Write Operation Status section for infor-

mation on these status bits.

device returns to the read mode and addresses are no

longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, DQ2, or

RY/BY#. Refer to the Write Operation Status section

for information on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once the device has returned to reading

array data, to ensure data integrity.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once the device has returned to

reading array data, to ensure data integrity.

Figure 6 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 20 section for timing diagrams.

Figure 6 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 20 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 10 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. This command is valid only during the sec-

tor erase operation, including the 50 µs time-out pe-

riod during the sector erase command sequence. The

Erase Suspend command is ignored if written during

the chip erase operation or Embedded Program

algorithm.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

After the command sequence is written, a sector erase

time-out of 50 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

the device to the read mode. The system must re-

write the command sequence and any additional ad-

dresses and commands.

After the erase operation has been suspended, the

device enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Note that un-

lock bypass programming is not allowed when the

device is erase-suspended.

Reading at any address within erase-suspended sec-

tors produces status information on DQ7–DQ0. The

system can use DQ7, or DQ6 and DQ2 together, to

determine if a sector is actively erasing or is

erase-suspended. Refer to the Write Operation Status

section for information on these status bits.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

After an erase-suspended program operation is com-

plete, the device returns to the erase-suspend-read

24

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard word program operation.

Refer to the Write Operation Status section for more

information.

START

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. Refer to the

Autoselect Mode and Autoselect Command Sequence

sections for details.

Write Erase

Command Sequence

(Notes 1, 2)

To resume the sector erase operation, the system

must write the Erase Resume command. The address

of the erase-suspended sector is required when writ-

ing this command. Further writes of the Resume com-

mand are ignored. Another Erase Suspend command

can be written after the chip has resumed erasing.

Data Poll to Erasing

Bank from System

Embedded

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

Notes:

1. See Table 10 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 6. Erase Operation

December 4, 2006 23569A5

Am29PDS322D

25

D A T A S H E E T

Table 10. Am29PDS322D Command Definitions

Bus Cycles (Notes 2–5)

Command

Sequence

(Note 1)

First

Second

Third

Addr

Fourth

Fifth

Sixth

Addr Data Addr Data

Data

Addr

Data

Addr Data Addr Data

Read (Note 6)

Reset (Note 7)

Manufacturer ID

1

4

RA

XXX

555

RD

F0

AA

2AA

55

555

90

X00

X01

0001

227E

2201/

X0E 2206 X0F

2200

Device ID (Note 9)

6

4

555

AA

SecSi Sector Factory

Protect (Note 10)

2AA

55

555

90

X03

80/00

Sector Group Protect Verify

(Note 11)

(SGA)

X02

XX00/

XX01

Enter SecSi Sector Region

Exit SecSi Sector Region

Program

3

4

3

555

AA

2AA

55

555

88

90

A0

20

XXX

PA

00

PD

Unlock Bypass

Unlock Bypass Program (Note 12)

XXX

A0

PA

PD

2

Unlock Bypass Reset (Note 13)

Chip Erase

XXX

555

BA

90

AA

B0

30

XXX

2AA

00

55

2

6

1

555

80

555

AA

2AA

55

555

SA

10

30

Sector Erase

Erase Suspend (Note 14)

Erase Resume (Note 15)

BA

Legend:

X = Don’t care

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

SGA = Address of the sector group to be verified (in autoselect mode)

or erased. Address bits A20–A12 uniquely select any sector.

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses

latch on the falling edge of the WE# or CE# pulse, whichever happens

later.

Notes:

1. See Table 1 for description of bus operations.

9. The device ID must be read across the fourth, fifth and sixth

cycles. The sixth cycle specifies 2201h for top boot or 2200h for

bottom boot.

2. All values are in hexadecimal.

3. Except for the read cycle and the fourth and fifth cycle of the

autoselect command sequence, all bus cycles are write cycles.

10. The data is 80h for factory locked and 00h for not factory locked.

11. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

4. Data bits DQ1ꢀ–DQ8 are don’t care in command sequences,

except for RD and PD.

12. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

ꢀ. Unless otherwise noted, address bits A20–A12 are don’t cares in

unlock sequence.

13. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

6. No unlock or command cycles required when device is in read

mode.

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when the device is in the autoselect mode, or if DQꢀ goes high

(while the device is providing status information).

1ꢀ. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

8. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or SecSi Sector factory protect

information. Data bits DQ1ꢀ–DQ8 are don’t care. See the

Autoselect Command Sequence section for more information.

26

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 11 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

invalid. Valid data on DQ0–DQ7 will appear on suc-

cessive read cycles.

Table 11 shows the outputs for Data# Polling on DQ7.

Figure 7 shows the Data# Polling algorithm. Figure 22

in the AC Characteristics section shows the Data#

Polling timing diagram.

START

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether the device is in Erase

Suspend. Data# Polling is valid after the rising edge of the

final WE# pulse in the command sequence.

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then the device returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

device returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ0–DQ6 may be still

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQꢀ = “1” because

DQ7 may change simultaneously with DQꢀ.

Figure 7. Data# Polling Algorithm

December 4, 2006 23569A5

Am29PDS322D

27

D A T A S H E E T

Table 11 shows the outputs for Toggle Bit I on DQ6.

RY/BY#: Ready/Busy#

Figure 8 shows the toggle bit algorithm. Figure 23 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 24 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or the device is in the erase-suspend-read

mode.

START

Read DQ7–DQ0

Table 11 shows the outputs for RY/BY#.

Read DQ7–DQ0

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

No

Toggle Bit

= Toggle?

Yes

No

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

DQ5 = 1?

Yes

Read DQ7–DQ0

Twice

After an erase command sequence is written, if all sectors

selected for erasing are protected, DQ6 toggles for approxi-

mately 100 µs, then returns to reading array data. If not all

selected sectors are protected, the Embedded Erase algo-

rithm erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

Toggle Bit

= Toggle?

No

The system can use DQ6 and DQ2 together to determine

whether a sector is actively erasing or is erase-suspended.

When the device is actively erasing (that is, the Embedded

Erase algorithm is in progress), DQ6 toggles. When the de-

vice enters the Erase Suspend mode, DQ6 stops toggling.

However, the system must also use DQ2 to determine

which sectors are erasing or erase-suspended. Alterna-

tively, the system can use DQ7 (see the subsection on

DQ7: Data# Polling).

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if

DQꢀ = “1” because the toggle bit may stop toggling as DQꢀ

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 μs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

Figure 8. Toggle Bit Algorithm

28

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

the toggle bit and DQ5 through successive read cy-

DQ2: Toggle Bit II

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 8).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 11 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if the device was previ-

ously in the erase-suspend-program mode).

Figure 8 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 23 shows the toggle bit timing diagram. Figure

24 shows the differences between DQ2 and DQ6 in

graphical form.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 8 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 11 shows the status of DQ3 relative to the other

status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

December 4, 2006 23569A5

Am29PDS322D

29

D A T A S H E E T

Table 11. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQꢀ switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQꢀ for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

30

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

20 ns

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

+0.8 V

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

–0.5 V

–2.0 V

Voltage with Respect to Ground

V

_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V

20 ns

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . . . –0.5 V to +11 V

WP#/ACC . . . . . . . . . . . . . . . . . .–0.5 V to +12.6 V

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 100 mA

Figure 9. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.ꢀ V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.ꢀ V.

See Figure 9. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 10.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.ꢀ V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 9. Maximum

DC input voltage on pin A9 is +12.ꢀ V which may

overshoot to +14.0 V for periods up to 20 ns. Maximum

DC input voltage on WP#/ACC is +12.6 V which may

overshoot to +12.0 V for periods up to 20 ns.

2.0 V

20 ns

Figure 10. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

OPERATING RANGES

Industrial (I) Devices

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

V

_CCSupply Voltages

V

_CCfor standard voltage range . . . . . . .1.8 V to 2.2 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

December 4, 2006 23569A5

Am29PDS322D

31

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Symbol

Parameter Description

Test Conditions

Min

Typ

Max

Unit

I_LI

Input Load Current

V_IN= V_SSto V_CC, V_CC= V_{CC max}

±1.0

µA

V_CC= V_{CC max}

A9, OE#, RESET# = 11 V

;

I_LIT

I_LO

A9 Input Load Current

Output Leakage Current

35

µA

V_OUT= V_SSto V_CC, V_CC= V_{CC max}

±1.0

3

1 MHz

CE# = V_IL, OE# = V_IH,

10 MHz

2.5

24

V_CCActive Inter-Page Read Current

(Notes 1, 2)

I_CC1

mA

28

30

5

I_CC2

I_CC3

V_CCActive Write Current (Notes 2, 3) CE# = V_IL,OE# = V_IH

15

mA

µA

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE#, RESET# = V_CC± 0.3 V

0.2

WP#/ACC = V_CC± 0.3 V,

RESET# = V_SS± 0.3 V

I_CC4

0.1

0.2

5

µA

CE# = V_SS± 0.3 V;

RESET# = V_CC± 0.3 V,

V_IN= V_CC± 0.3 V or V_SS± 0.3 V

V_CCAutomatic Sleep Mode Current

(Notes 2, 4)

I_CC5

V_CCActive Read-While-Program

Current (Notes 1, 2, 5)

I_CC6

I_CC7

CE# = V_IL, OE# = V_IH

30

55

mA

V_CCActive Read-While-Erase

Current (Notes 1, 2, 5)

V_CCActive

I_CC8

Program-While-Erase-Suspended

Current (Note 2)

CE# = V_IL, OE# = V_IH

17

35

mA

10 MHz

20 MHz

0.5

1

2

I_CC9

V_CCActive Intra-Page Read Current CE# = V_IL, OE# = V_IH

WP#/ACC Accelerated Program

mA

I_ACC

V

_CC= V_CCMax, WP#/ACC = V_ACCMax

12

20

Current

V_IL

V_IH

Input Low Voltage

Input High Voltage

–0.5

V_CCx 0.2

V_CC+ 0.3

V

0.8 x V_CC

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration

V_ACC

V_CC= 1.8–2.2 V

8.5

9

12.5

V

Voltage for Autoselect and Temporary

Sector Unprotect

V_ID

V_CC= 1.8–2.2 V

11

V_OL

V_OH

V_LKO

Output Low Voltage

I_OL= 100 µA, V_CC= V_{CC min}

I_OH= –100 µA

0.1

V

Output High Voltage

Low V_CCLock-Out Voltage

V_CC– 0.1

1.2

1.5

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at V_IH.

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax.

3. I_CCactive while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for 1ꢀ0 ns.

ꢀ. Embedded algorithm (program or erase) is in progress (at 8 MHz).

32

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

DC CHARACTERISTICS

Zero-Power Flash

25

20

15

10

5

0

500

1000

1500

2000

2500

3000

3500

4000

Time in ns

Note: Addresses are switching at 1 MHz

Figure 11. I_CC1Current vs. Time (Showing Active and Automatic Sleep Currents)

18

15

12

9

2.0 V

6

3

0

1

2

3

4

5

6

7

8

Frequency in MHz

Note: T = 2ꢀ °C

Figure 12. Typical I_CC1vs. Frequency

Am29PDS322D

December 4, 2006 23569A5

33

D A T A S H E E T

TEST CONDITIONS

Table 12. Test Specifications

Test Condition

10

12

100

Unit

Device

Under

Test

Output Load Capacitance, C_L

30

pF

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

C

L

0.0–2.0 V

1.0

Input timing measurement

reference levels

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

1.0

Figure 13. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

KS000010-PAL

V_CC

1.0 V

Input

Measurement Level

Output

0.5 V_CC

0.0 V

Figure 14. Input Waveforms and Measurement Levels

34

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Option

JEDEC

t_AVAV

Std

t_RC

Description

Test Setup

10

100

40

12

120

50

Unit

ns

Read Cycle Time (Note 1)

Address to Output Delay

Page Read Cycle

Min

Max

Min

t_AVQV

t_ACC

t_PRC

CE#, OE# = V_IL

t_PACCPage Address to Output Delay

CE#, OE# = V_IL

OE# = V_IL

Max

40

50

t_ELQV

t_GLQV

t_EHQZ

t_GHQZ

t_CE

t_OE

t_DF

Chip Enable to Output Delay

100

35

120

50

Output Enable to Output Delay

Chip Enable to Output High Z (Notes 1, 3)

Output Enable to Output High Z (Notes 1, 3)

16

Output Hold Time From Addresses, CE# or OE#,

Whichever Occurs First

t_AXQX

t_OH

Min

0

ns

Read

Output Enable Hold

Time (Note 1)

t_OEH

Toggle and

10

Data# Polling

Notes:

1. Not 100% tested.

2. See Figure 13 and Table 12 for test specifications.

3. Measurements performed by placing a ꢀ0Ω termination on the data pin with a bias of V_CC/2. The time from OE# high to the

data bus driven to V_CC/2 is taken as t_DF

.

t_RC

Addresses Stable

Addresses

t_ACC

CE#

t_RH

t_DF

t_OE

OE#

WE#

t_OEH

t_CE

t_OH

HIGH Z

Output Valid

Outputs

RESET#

RY/BY#

0 V

Figure 15. Conventional Read Operation Timings

December 4, 2006 23569A5

Am29PDS322D

35

D A T A S H E E T

AC CHARACTERISTICS

Same page Addresses

A20 to A2

Aa

Ab

Ac

Ad

A1 to A0

t_RC

t_PRC

t_ACC

t_CE

CE#

t_OE

OE#

WE#

t_OEH

t_DF

t_PACC

t_OH

t_PACC

t_OH

t_PACC

t_OH

Dd

High-Z

Da

Db

Dc

Output

Figure 16. Page Mode Read Timings

36

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

μs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

200

20

ns

μs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

0

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 17. Reset Timings

December 4, 2006 23569A5

Am29PDS322D

37

D A T A S H E E T

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Option

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

10

12

Unit

ns

Write Cycle Time (Note 1)

Min

100

120

t_AVWL

Address Setup Time

0

ns

t_ASO

t_AH

Address Setup Time to OE# low during toggle bit polling

Address Hold Time

15

60

ns

t_WLAX

ns

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

Min

0

ns

t_DVWH

t_WHDX

t_DS

t_DH

t_CEPH

t_OEPH

Data Setup Time

Min

60

0

ns

Data Hold Time

Chip Enable High during toggle bit polling

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

µs

sec

µs

ns

CE# Hold Time

t_WP

Write Pulse Width

60

0

t_WPH

t_SR/W

t_WHWH1

t_WHWH2

t_VCS

Write Pulse Width High

Latency Between Read and Write Operations

Programming Operation (Note 2)

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

V_CCSetup Time (Note 1)

t_WHWH1

t_WHWH2

11

5

1

50

0

t_RB

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

t_BUSY

90

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

38

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Note: PA = program address, PD = program data, D_OUTis the true data at the program address.

Figure 18. Program Operation Timings

V_HH

V_ILor V_IH

ACC

t_VHH

Figure 19. Accelerated Program Timing Diagram

December 4, 2006 23569A5

Am29PDS322D

39

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

In

Data

Complete

55h

30h

Progress

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

Figure 20. Chip/Sector Erase Operation Timings

40

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_CPH

t_ACC

t_CE

CE#

t_CP

t_OE

OE#

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 21. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

CE#

VA

t_ACC

t_CE

VA

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ0–DQ6

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 22. Data# Polling Timings (During Embedded Algorithms)

December 4, 2006 23569A5

Am29PDS322D

41

D A T A S H E E T

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 24. DQ2 vs. DQ6

42

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

ns

RESET# Setup Time for Temporary

Sector/Sector Block Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector/Sector Block Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_SS, V_IL,

or V_IH

V_SS, V_IL,

or V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 25. Temporary Sector Group Unprotect Timing Diagram

December 4, 2006 23569A5

Am29PDS322D

43

D A T A S H E E T

AC CHARACTERISTICS

V_ID

V_IH

RESET#

SA, A6,

A1, A0

Valid*

Sector/Sector Block Protect or Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

Sector/Sector Block Protect: 150 µs,

Sector/Sector Block Unprotect: 15 ms

1 µs

CE#

WE#

OE#

* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 26. Sector Group Protect and Unprotect Timing Diagram

44

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Option

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

10

12

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

100

120

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

60

0

ns

t_AH

t_DS

t_DH

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_WS

t_WH

WE# Setup Time

Min

Typ

0

ns

WE# Hold Time

0

t_CP

CE# Pulse Width

60

16

t_EHEL

t_CPH

CE# Pulse Width High

ns

t_WHWH1

t_WHWH2

t_WHWH1

t_WHWH2

Programming Operation (Note 2)

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

µs

5

µs

1

sec

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

December 4, 2006 23569A5

Am29PDS322D

45

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings

46

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

Comments

Sector Erase Time

Chip Erase Time

1

10

Excludes 00h programming

prior to erasure (Note 4)

93

Excludes system level

overhead (Note 5)

Word Program Time

16

360

100

µs

Accelerated Word Program Time

Chip Program Time (Note 3)

Notes:

5

µs

20

sec

1. Typical program and erase times assume the following conditions: 2ꢀ°C, 2.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 1.8 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

ꢀ. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table

10 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

12.5 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 1.8 V, one pin at a time.

DATA RETENTION

Parameter Description

Test Conditions

Min

10

Unit

Years

150°C

125°C

Minimum Pattern Data Retention Time

20

December 4, 2006 23569A5

Am29PDS322D

47

D A T A S H E E T

PHYSICAL DIMENSIONS

FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 12 mm package

Dwg rev AF; 1/2000

xFBD 048

6.00 mm x 12.00 mm

PACKAGE

1.20

0.94

0.20

0.84

12.00 BSC

6.00 BSC

5.60 BSC

4.00 BSC

8

6

48

0.25 0.30

0.35

0.80 BSC

0.40 BSC

* For reference only. BSC is an ANSI standard for Basic Space Centering.

48

Am29PDS322D

23569A5 December 4, 2006

D A T A S H E E T

REVISION SUMMARY

Revision A (December 4, 2000)

Initial release.

Erase Suspend/Erase Resume Commands

Noted in the third paragraph that unlock bypass pro-

gramming is not allowed when the device is erase sus-

pended.

Revision A+1 (February 16, 2001)

Revision A+4 (August 7, 2002)

Ordering Information

Added “U” designator to package marking. Deleted

burn-in option.

Distinctive Characteristics

Removed “Supports Common Flash Memory Interface

(CFI))

Revision A+2 (August 31, 2001)

Autoselect Command Sequence

Table 10. Am29PDS322D Command Definitions

Modified section to point to appropriate tables for au-

toselect functions.

Changed the Command Cycle Device ID cycle from 6

to 4.

Revision A+3 (February 18, 2002)

Revision A5 (December 4, 2006)

Global

Removed “Advance Information” designation from

data sheet.

Removed Advance Information designation from docu-

ment (inadvertently restored in Revision A+4).

AC Characteristics

Erase and Program Operations table: Changed t_BUSY

to a maximum specification.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita-

tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con-

templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the

public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,

aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for

any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable

to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor

devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design

measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating

conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign

Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au-

thorization by the respective government entity will be required for export of those products.

Trademarks

marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are

for identification purposes only and may be trademarks of their respective companies.

trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.

December 4, 2006 23569A5

Am29PDS322D

49


型号：	P322DT10UI
厂家：	AMD
描述：	32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V) Simultaneous Read/Write Page-Mode Boot Sector Flash Memory 32兆位（2M ×16位） CMOS 1.8伏只（ 1.8 V至2.2 V）同步读/写分页模式引导扇区闪存闪存
文件：	总51页 (文件大小：844K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

P322DT10UI [AMD]

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