PALCE16V8Q-10SI4 [AMD]
EE CMOS 20-Pin Universal Programmable Array Logic; EE CMOS 20引脚通用可编程阵列逻辑
| 型号： | PALCE16V8Q-10SI4 |
| 厂家： | 
AMD |
| 描述： | EE CMOS 20-Pin Universal Programmable Array Logic |
| 文件： | 总26页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-10/15/25, Q-20/25
PALCE16V8 Family
EE CMOS 20-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
■ Pin and function compatible with all 20-pin
■ Programmable output polarity
GAL devices
■ Programmable enable/disable control
■ Preloadable output registers for testability
■ Automatic register reset on power up
■ Electrically erasable CMOS technology
provides reconfigurable logic and full
testability
■ Cost-effective 20-pin plastic DIP, PLCC, and
■ High-speed CMOS technology
SOIC packages
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
■ Extensive third-party software and programmer
support through FusionPLD partners
■ Direct plug-in replacement for the PAL16R8
■ Fully tested for 100% programming and
series and most of the PAL10H8 series
functional yields and high reliability
■ Outputs programmable as registered or
■ 5 ns version utilizes a split leadframe for
combinatorial in any combination
improved performance
■ Peripheral Component Interconnect (PCI)
compliant
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. It is functionally compatible with all 20-pin
GALdevices. Themacrocellsprovideauniversaldevice
architecture. The PALCE16V8 will directly replace the
PAL16R8 and PAL10H8 series devices, with the excep-
tion of the PAL16C1.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial with an active-
high or active-low output. The output configuration is
determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
The PALCE16V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
AMD’s FusionPLD program allows PALCE16V8 de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provideaccurate, qualitysupport. Byensuringthatthird-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
Publication# 16493 Rev. D Amendment/0
Issue Date: February 1996
2-36
AMD
BLOCK DIAGRAM
I
– I
8
1
CLK/I
0
8
Programmable AND Array
32 x 64
MACRO
MC
MACRO
MC
MACRO
MC
MACRO
MC
MACRO
MC
MACRO
MC
MACRO
MC
MACRO
MC
0
1
2
3
4
5
6
7
OE/I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
9
0
1
2
3
4
5
6
16493D-1
CONNECTION DIAGRAMS
Top View
DIP/SOIC
PLCC/LCC
1
20
19
18
17
16
VCC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE/I9
CLK/I0
I1
I2
I3
2
3
3
2
1
20
19
4
5
6
I4
I5
I6
I/O6
I/O5
I/O4
I/O3
18
17
16
15
4
5
6
7
I3
I4
15
14
13
7
I5
I6
I7
8
I7
I8
9
12
11
14
I/O2
8
10
GND
16493D-2
9
10 11 12 13
Note: Pin 1 is marked for orientation.
PIN DESIGNATIONS
16493D-3
CLK
GND
I
I/O
OE
VCC
=
=
=
=
=
=
Clock
Ground
Input
Input/Output
Output Enable
Supply Voltage
PALCE16V8 Family
2-37
AMD
ORDERING INFORMATION
Commercial and Industrial Products
AMD programmable logic products for commercial and industrial applications are available with several ordering options. The
order number (Valid Combination) is formed by a combination of:
PAL CE 16 V 8 H -5 P C /5
OPTIONAL PROCESSING
Blank = Standard Processing
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/4 = First Revision
NUMBER OF
ARRAY INPUTS
/5 = Second Revision
(Same Algorithm as /4)
OUTPUT TYPE
V = Versatile
NUMBER OF OUTPUTS
OPERATING CONDITIONS
C = Commercial (0°C to +75°C)
POWER
H = Half Power (90 – 125 mA ICC
Q = Quarter Power (55 mA ICC
)
I
= Industrial (–40°C to +85°C)
)
SPEED
PACKAGE TYPE
P = 20-Pin Plastic DIP (PD 020)
J = 20-Pin Plastic Leaded Chip
Carrier (PL 020)
S = 20-Pin Plastic Gull-Wing
Small Outline Package (SO 020)
-5 = 5 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-15 = 15 ns tPD
-20 = 20 ns tPD
-25 = 25 ns tPD
Valid Combinations
Valid Combinations
JC
PALCE16V8H-5
PALCE16V8H-7
PALCE16V8H-10
PALCE16V8Q-10
PALCE16V8H-15
PALCE16V8Q-15
PALCE16V8Q-20
PALCE16V8H-25
PALCE16V8Q-25
Valid Combinations lists configurations planned
to be supported in volume for this device. Consult
the local AMD sales office to confirm availability of
specific valid combinations and to check on newly
released combinations.
/5
PC, JC
PC, JC, SC, PI, JI
PC, JC, SC
PC, JC, SC, PI, JI
PC, JC
/4
/5
PI, JI
Blank,
/4
PC, JC, SC, PI, JI
PC, JC, PI, JI
PALCE16V8H-5/7/10/15/25, Q-10/15/25 (Com’l)
H-10/15/25, Q-20/25 (Ind)
2-38
AMD
specification. The design specification is processed by
development software to verify the design and create a
programming file (JEDEC). This file, once downloaded
to a programmer, configures the device according to the
user’s desired function.
FUNCTIONAL DESCRIPTION
The PALCE16V8 is a universal PAL device. It has eight
independently configurable macrocells (MC0–MC7).
Each macrocell can be configured as registered output,
combinatorial output, combinatorial I/O or dedicated in-
put. The programming matrix implements a program-
mable AND logic array, which drives a fixed OR logic
array. Buffers for device inputs have complementary
outputs to provide user-programmable input signal po-
larity. Pins 1 and 11 serve either as array inputs or as
clock (CLK) and output enable (OE), respectively, for all
flip-flops.
The user is given two design options with the
PALCE16V8. First, it can be programmed as a standard
PAL device from the PAL16R8 and PAL10H8 series.
The PAL programmer manufacturer will supply device
codes for the standard PAL device architectures to be
used with the PALCE16V8. The programmer will pro-
gram the PALCE16V8 in the corresponding architec-
ture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed as
aPALCE16V8. HeretheusermustusethePALCE16V8
device code. This option allows full utilization of the
macrocell.
Unused input pins should be tied directly to VCC or GND.
Product terms with all bits unprogrammed (discon-
nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALCE16V8 are
automatically configured from the user’s design
To
Adjacent
Macrocell
1 1
OE
1 0
0 0
0 1
1 1
VCC
0 X
1 0
SL0
X
SG1
1 1
0 X
I/OX
D
Q
1 0
SL1X
CLK
Q
1 0
1 1
0 X
From
Adjacent
Pin
*
SG1
SL0X
16493D-4
*In macrocells MC0 and MC7, SG1 is replaced by SG0 on the feedback multiplexer.
PALCE16V8 Macrocell
PALCE16V8 Family
2-39
AMD
use the feedback path of MC7 and pin 11 will use the
feedback path of MC0.
Configuration Options
Each macrocell can be configured as one of the follow-
ing: registered output, combinatorial output, combinato-
rial I/O, or dedicated input. In the registered output
configuration, theoutputbufferisenabledbytheOE pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, it is always disabled. With
the exception of MC0 and MC7, a macrocell configured
as a dedicated input derives the input signal from an ad-
jacent I/O. MC0 derives its input from pin 11 (OE) and
MC7 from pin 1 (CLK).
Combinatorial I/O in a Non-Registered
Device
ThecontrolbitsettingsareSG0=1, SG1=1, andSL0x =
1. Only seven product terms are available to the OR
gate. The eighth product term is used to enable the out-
put buffer. The signal at the I/O pin is fed back to the
AND array via the feedback multiplexer. This allows the
pin to be used as an input.
Because CLK and OE are not used in a non-registered
device, pins 1 and 11 are available as inputs. Pin 1 will
use the feedback path of MC7 and pin 11 will use the
feedback path of MC0.
The macrocell configurations are controlled by the con-
figuration control word. It contains 2 global bits (SG0
and SG1) and 16 local bits (SL00 through SL07 and SL10
through SL17). SG0 determines whether registers will
be allowed. SG1 determines whether the PALCE16V8
will emulate a PAL16R8 family or a PAL10H8 family de-
vice. Within each macrocell, SL0x, in conjunction with
SG1, selects the configuration of the macrocell, and
SL1x sets the output as either active low or active high
for the individual macrocell.
Combinatorial I/O in a Registered Device
The control bit settings are SG0 = 0, SG1 = 1 and SL0x =
1. Only seven product terms are available to the OR
gate. The eighth product term is used as the output
enable. The feedback signal is the corresponding I/O
signal.
Dedicated Input Configuration
The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul-
tiplexers: a product term input, an enable select, an out-
put select, and a feedback select multiplexer. SG1 and
SL0x are the control signals for all four multiplexers. In
MC0 and MC7, SG0 replaces SG1 on the feedback mul-
tiplexer. This accommodates CLK being the adjacent
pin for MC7 and OE the adjacent pin for MC0.
The control bit settings are SG0 = 1, SG1 = 0 and SL0x =
1. Theoutputbufferisdisabled. ExceptforMC0 andMC7
thefeedbacksignalisanadjacentI/O. ForMC0 and MC7
the feedback signals are pins 1 and 11. These configu-
rations are summarized in Table 1 and illustrated in
Figure 2.
Table 1. Macrocell Configuration
Registered Output Configuration
SG0 SG1 SL0X Cell Configuration Devices Emulated
Device Uses Registers
The control bit settings are SG0 = 0, SG1 = 1 and SL0x =
0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1x. The flip-flop is
loaded on the LOW-to-HIGH transition of CLK. The
feedback path is from Q on the register. The output
buffer is enabled by OE.
0
1
0
Registered Output PAL16R8, 16R6,
16R4
Combinatorial I/O PAL16R6, 16R4
0
1
1
Device Uses No Registers
1
1
1
0
0
1
0
1
1
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8,
12L6, 14L4, 16L2
PAL12H6, 14H4,
16H2, 12L6, 14L4,
16L2
Input
Combinatorial Configurations
Combinatorial I/O PAL16L8
The PALCE16V8 has three combinatorial output con-
figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.
Programmable Output Polarity
The polarity of each macrocell can be active-high or ac-
tive-low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Dedicated Output in a Non-Registered
Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x =
0. All eight product terms are available to the OR gate.
Although the macrocell is a dedicated output, the feed-
back is used, with the exception of pins 15 and 16. Pins
15 and 16 do not use feedback in this mode. Because
CLK and OE are not used in a non-registered device,
pins 1 and 11 are available as input signals. Pin 1 will
Selection is through a programmable bit SL1x which
controls an exclusive-OR gate at the output of the AND/
OR logic. The output is active high if SL1x is 1 and active
low if SL1x is 0.
2-40
PALCE16V8 Family
AMD
OE
OE
D
Q
D
Q
Q
Q
CLK
CLK
Registered Active Low
Registered Active High
Combinatorial I/O Active Low
Combinatorial I/O Active High
VCC
VCC
Note 1
Note 1
Combinatorial Output Active Low
Combinatorial Output Active High
Notes:
1. Feedback is not available on pins 15
and 16 in the combinatorial output mode.
Adjacent I/O pin
Note 2
2. This configuration is not available on pins 15 and 16.
Dedicated Input
16493D-5
Figure 2. Macrocell Configurations
PALCE16V8 Family
2-41
AMD
Power-Up Reset
Programming and Erasing
All flip-flops power up to a logic LOW for predictable sys-
tem initialization. Outputs of the PALCE16V8 will de-
pend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
HIGH. If combinatorial is selected, the output will be a
function of the logic.
The PALCE16V8 can be programmed on standard logic
programmers. It also may be erased to reset a previ-
ously configured device back to its virgin state. Erasure
is automatically performed by the programming hard-
ware. No special erase operation is required.
Quality and Testability
Register Preload
The PALCE16V8 offers a very high level of built-in qual-
ity. The erasability of the device provides a direct means
of verifying performance of all AC and DC parameters.
In addition, this verifies complete programmability and
functionality of the device to provide the highest pro-
gramming yields and post-programming functional
yields in the industry.
The register on the PALCE16V8 can be preloaded from
the output pins to facilitate functional testing of complex
state machine designs. This feature allows direct load-
ing of arbitrary states, making it unnecessary to cycle
through long test vector sequences to reach a desired
state. In addition, transitions from illegal states can be
verified by loading illegal states and observing proper
recovery.
Technology
The high-speed PALCE16V8 is fabricated with AMD’s
advanced electrically erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
Security Bit
A security bit is provided on the PALCE16V8 as a deter-
rent to unauthorized copying of the array configuration
patterns. Once programmed, this bit defeats readback
and verification of the programmed pattern by a device
programmer, securing proprietary designs from com-
petitors. The bit can only be erased in conjunction with
the array during an erase cycle.
PCI Compliance
The PALCE22V10H-7/10 is fully compliant with the PCI
Local Bus Specification published by the PCI Special In-
terest Group. The PALCE22V10H-7/10’s predictable
timing ensures compliance with the PCI AC specifica-
tions independent of the design.
Electronic Signature Word
An electronic signature word is provided in the
PALCE16V8 device. It consists of 64 bits of programm-
able memory that can contain user-defined data. The
signature data is always available to the user independ-
ent of the security bit.
2-42
PALCE16V8 Family
AMD
LOGIC DIAGRAM
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
CLK/I
1
2
3
4
0
20
19
1 1
1 0
0 0
0 1
V
CC
1 1
V
CC
0 X
1 0
SL07
0
7
SG1
1 1
0 X
I/O
7
D
Q
Q
1 0
SL17
1 0
1 1
0 X
I
1
SG0
SL07
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL06
8
SG1
1 1
0 X
18 I/O
6
D
Q
1 0
Q
15
SL16
1 0
1 1
0 X
I
2
SG1
SL06
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL05
16
23
SG1
1 1
0 X
17 I/O
5
D
Q
Q
1 0
SL15
1 0
1 1
0 X
I
3
SG1
SL05
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL04
24
31
SG1
1 1
0 X
16
I/O
4
D
Q
Q
1 0
SL14
1 0
1 1
0 X
5
I
4
SG1
SL04
CLK OE
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
16493D-6
PALCE16V8 Family
2-43
AMD
LOGIC DIAGRAM (continued)
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
CLK OE
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL03
32
39
SG1
1 1
0 X
15
14
13
I/O
3
D
Q
Q
1 0
SL13
1 0
1 1
0 X
6
7
8
I
5
SG1
SL03
SL02
SL01
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL02
40
47
SG1
1 1
0 X
I/O
2
D
Q
Q
1 0
SL12
1 0
1 1
0 X
I
6
SG1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL01
48
55
SG1
1 1
0 X
I/O
1
D
Q
Q
1 0
SL11
1 0
1 1
0 X
I
7
SG1
1 1
1 0
0 0
0 1
1 1
V
CC
0 X
1 0
SL00
56
63
SG1
1 1
0 X
12 I/O
0
D
Q
Q
1 0
SL10
1 0
1 1
0 X
9
I
8
SL00
SG0
11
OE/I
9
0
3
4
7
8
11 12 15 16 19 20 23 24 27 28 31
GND 10
16493D-6
(concluded)
2-44
PALCE16V8 Family
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Commercial (C) Devices
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage (VCC) with
Supply Voltage with
Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to 75°C) . . . . . . . . . . . . . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VCC = Min
VIN = VIH or VIL
VIN = VIH or VIL
2.4
V
VOL
Output LOW Voltage
IOL = 24 mA
VCC = Min
0.5
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
V
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current
Input LOW Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
10
–100
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–150
125
mA
mA
ICC
Outputs Open (IOUT = 0 mA), VIN = 0 V
VCC = Max
(Static)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
PALCE16V8H-5 (Com’l)
2-45
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Descriptions
Test Conditions
VIN = 2.0 V
Typ
5
Unit
pF
CIN
Input Capacitance
Output Capacitance
VCC = 5.0 V, TA = 25°C,
COUT
VOUT = 2.0 V
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Min
(Note 5)
Parameter Description
Max
Unit
tPD
tS
Input or Feedback to Combinatorial Output
1
3
0
1
5
ns
Setup Time from Input or Feedback to Clock
Hold Time
ns
ns
tH
tCO
Clock to Output
4
1
ns
ns
tSKEWR
Skew Between Registered Outputs (Note 4)
tWL
tWH
LOW
3
3
ns
ns
Clock Width
HIGH
External Feedback
Maximum
1/(tS+tCO
1/(tS+tCF) (Note 6)
1/(tWH+tWL
)
142.8
166
166
1
MHz
MHz
MHz
ns
Frequency
(Note 3)
fMAX
Internal Feedback (fCNT),
No Feedback
)
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
6
5
6
5
1
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
2
ns
tER
2
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
5. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improve-
ments may alter these values therefore, minimum values are recommended for simulation purposes only.
6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-46
PALCE16V8H-5 (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Commercial (C) Devices
Temperature (TA)
Storage Temperature . . . . . . . . . . –65°C to +150°C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . –55°C to +125°C
Operating in Free Air . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . –0.5 V to + 7.0 V
Supply Voltage (VCC
with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
)
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 1.0 V
Operating Ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 1.0 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to +75°C) . . . . . . . . . . . . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VCC = Min
VIN = VIH or VIL
VIN = VIH or VIL
2.4
V
VOL
Output LOW Voltage
IOL = 24 mA
VCC = Min
0.5
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
V
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current
Input LOW Leakage Current
VIN = 5.5 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
10
–100
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.5 V, VCC = Max,
VIN = VIL or VIH (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
–100
µA
VIN = VIL or VIH (Note 2)
ISC
Output Short-Circuit Current
Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–150
115
mA
mA
ICC
Outputs Open, (IOUT = 0 mA),
(Dynamic)
VCC = Max, f = 25 MHz
Notes:
1. These are absolute values with respect to the device ground and all overshoots due to system and tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
PALCE16V8H-7 (Com’l)
2-47
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Descriptions
Test Conditions
VIN = 2.0 V
Typ
5
Unit
pF
CIN
Input Capacitance
Output Capacitance
VCC = 5.0 V, TA = 25°C,
COUT
VOUT = 2.0 V
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Min
(Note 5)
Parameter Description
Max
Unit
tPD
Input or Feedback to Combinatorial Output
8 Outputs Switching
1 Output Switching
3
3
7.5
7
ns
ns
tS
tH
Setup Time from Input or Feedback
5
0
1
ns
ns
Hold Time
tCO
Clock to Output
5
1
ns
tSKEWR
tWL
Skew Between Registered Outputs (Note 4)
ns
LOW
4
4
ns
Clock Width
HIGH
tWH
ns
External Feedback
Maximum
1/(tS + tCO
1/(tS + tCF) (Note 6)
1/(tWH + tWL
)
100
125
125
1
MHz
MHz
MHz
ns
Frequency
(Note 3)
fMAX
Internal Feedback (fCNT
)
No Feedback
)
tPZX
tPXA
tEA
OE to Output Enable
OE to Output Disable
6
6
9
9
1
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
3
ns
tER
3
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
5. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values therefore, minimum values are recommended for simulation purposes only.
6. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-48
PALCE16V8H-7 (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) Operating
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . –0.5 V to + 7.0 V
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Industrial (I) Devices
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V
Latchup Current
(TA = –40°C to +85°C) . . . . . . . . . . . . . . . . . . 100 mA
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VCC = Min
VIN = VIH or VIL
VIN = VIH or VIL
2.4
V
VOL
Output LOW Voltage
IOL = 24 mA
VCC = Min
0.5
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
V
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current
Input LOW Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
10
–100
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
Output Short-Circuit Current
Commercial Supply Current
VOUT = 0.5 V
VCC = Max (Note 3)
–30
–150
115
mA
mA
ICC
Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
(Dynamic)
Industrial Supply Current
130
mA
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
PALCE16V8H-10 (Com’l, Ind)
2-49
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Descriptions
Test Conditions
VIN = 2.0 V
Typ
5
Unit
pF
CIN
Input Capacitance
Output Capacitance
VCC = 5.0 V, TA = 25°C,
COUT
VOUT = 2.0 V
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
Parameter
Symbol
Min
(Note 4)
Parameter Description
Max
Unit
tPD
tS
Input or Feedback to Combinatorial Output
3
7.5
0
10
ns
Setup Time from Input or Feedback to Clock
ns
ns
tH
Hold Time
Clock to Output
LOW
tCO
tWL
tWH
3
7.5
ns
6
ns
Clock Width
HIGH
6
ns
External Feedback
Maximum
1/(tS + tCO
1/(tS + tCF) (Note 5)
1/(tWH + tWL
)
66.7
71.4
83.3
2
MHz
MHz
MHz
ns
fMAX
Internal Feedback (fCNT
)
Frequency
(Note 3)
No Feedback
)
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
10
10
10
10
2
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
3
ns
tER
3
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improve-
ments may alter these values therefore, minimum values are recommended for simulation purposes only.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-50
PALCE16V8H-10 (Com’l, Ind)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Commercial (C) Devices
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Supply Voltage (VCC) with
Supply Voltage with
Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
Respect to Ground . . . . . . . . . . . . . –0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current
(TA = 0°C to 75°C) . . . . . . . . . . . . . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VCC = Min
VIN = VIH or VIL
VIN = VIH or VIL
2.4
V
VOL
Output LOW Voltage
IOL = 24 mA
VCC = Min
0.5
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
V
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current
Input LOW Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
10
–100
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
ICC
Output Short-Circuit Current
Supply Current (Dynamic)
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–150
55
mA
mA
Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
PALCE16V8Q-10 (Com’l)
2-51
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Descriptions
Test Conditions
VIN = 2.0 V
Typ
5
Unit
pF
CIN
Input Capacitance
Output Capacitance
VCC = 5.0 V, TA = 25°C,
COUT
VOUT = 2.0 V
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Min
(Note 4)
Parameter Description
Max
Unit
tPD
tS
Input or Feedback to Combinatorial Output
3
7.5
0
10
ns
Setup Time from Input or Feedback to Clock
Hold Time
ns
ns
tH
tCO
tWL
tWH
Clock to Output
3
7.5
ns
LOW
Clock Width
6
ns
HIGH
6
ns
External Feedback
Maximum
1/(tS + tCO
1/(tS + tCF) (Note 5)
1/(tWH + tWL
)
66.7
71.4
83.3
2
MHz
MHz
MHz
ns
fMAX
Frequency
(Note 3)
Internal Feedback (fCNT
)
No Feedback
)
tPZX
tPXZ
tEA
OE to Output Enable
OE to Output Disable
10
10
10
10
2
ns
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
3
ns
tER
3
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improve-
ments may alter these values therefore, minimum values are recommended for simulation purposes only.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-52
PALCE16V8Q-10 (Com’l)
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Commercial (C) Devices
Temperature (TA) Operating
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
in Free Air . . . . . . . . . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . –0.5 V to + 7.0 V
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . +4.75 V to +5.25 V
DC Input Voltage . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Industrial (I) Devices
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Temperature (TA) Operating
in Free Air . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Supply Voltage (VCC) with
Respect to Ground . . . . . . . . . . . . . . +4.5 V to +5.5 V
Latchup Current
(TA = –40°C to +85°C) . . . . . . . . . . . . . . . . . . 100 mA
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
Parameter
Symbol
Parameter Description
Test Conditions
Min
Max
Unit
VOH
Output HIGH Voltage
IOH = –3.2 mA
VCC = Min
VIN = VIH or VIL
VIN = VIH or VIL
2.4
V
VOL
Output LOW Voltage
IOL = 24 mA
VCC = Min
0.5
V
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
Guaranteed Input Logical HIGH
Voltage for all Inputs (Note 1)
2.0
V
V
Guaranteed Input Logical LOW
Voltage for all Inputs (Note 1)
0.8
IIH
IIL
Input HIGH Leakage Current
Input LOW Leakage Current
VIN = 5.25 V, VCC = Max (Note 2)
VIN = 0 V, VCC = Max (Note 2)
10
–100
10
µA
µA
µA
IOZH
Off-State Output Leakage
Current HIGH
VOUT = 5.25 V, VCC = Max
VIN = VIH or VIL (Note 2)
IOZL
Off-State Output Leakage
Current LOW
VOUT = 0 V, VCC = Max
VIN = VIH or VIL (Note 2)
–100
µA
ISC
Output Short-Circuit Current
Commercial Supply Current
VOUT = 0.5 V, VCC = Max (Note 3)
–30
–150
mA
mA
ICC
Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
H
Q
90
55
(Dynamic)
ICC
Industrial Supply Current
Outputs Open (IOUT = 0 mA)
VCC = Max, f = 15 MHz
H
Q
130
65
mA
(Dynamic)
Notes:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
PALCE16V8H-15/25, Q-15/25 (Com’l, Ind), Q-20 (Ind)
2-53
AMD
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Descriptions
Test Conditions
VIN = 2.0 V
Typ
5
Unit
pF
CIN
Input Capacitance
Output Capacitance
VCC = 5.0 V, TA = 25°C,
COUT
VOUT = 2.0 V
f = 1 MHz
8
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where capacitance may be affected.
SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges
(Note 2)
-15
-20
-25
Parameter
Symbol
Parameter Description
Min Max Min Max
Min Max Unit
tPD
tS
Input or Feedback to Combinatorial Output
Setup Time from Input or Feedback to Clock
Hold Time
15
10
20
11
25
ns
ns
12
0
13
0
15
0
tH
ns
tCO
tWL
tWH
Clock to Output
12
ns
LOW
8
8
10
10
12
12
37
40
ns
Clock Width
HIGH
ns
External Feedback
1/(tS + tCO
)
45.5
50
41.6
45.4
MHz
MHz
Maximum
Frequency
(Note 3)
fMAX
Internal Feedback
1/(tS + tCO
(Note 4)
)
(fCNT
)
No Feedback
1/(tWH + tWL
)
62.5
50.0
41.6
MHz
ns
tPZX
tPXZ
OE to Output Enable
OE to Output Disable
15
15
15
15
18
18
18
18
20
20
20
20
ns
tEA
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
ns
tER
ns
Notes:
2. See Switching Test Circuit for test conditions.
3. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified
where frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
2-54
PALCE16V8H-15/25, Q-15/25 (Com’l, Ind), Q-20 (Ind)
AMD
SWITCHING WAVEFORMS
Input or
Feedback
VT
Input or
Feedback
VT
tS
tH
tPD
VT
tCO
Combinatorial
Output
VT
Clock
16493D-7
Registered
Output
VT
16493D-8
Combinatorial Output
Registered Output
VT
Input
tWH
tER
tEA
VT
VOH - 0.5V
VOL + 0.5V
Clock
VT
Output
tWL
16493D-9
16493D-10
Clock Width
Input to Output Disable/Enable
VT
OE
tPXZ
tPZX
VT
VOH - 0.5V
VOL + 0.5V
Output
16493D-11
OE to Output Disable/Enable
Notes:
1. VT = 1.5 V
2. Input pulse amplitude 0 V to 3.0 V.
3. Input rise and fall times 2 ns – 5 ns typical.
PALCE16V8 Family
2-55
AMD
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
5 V
S1
R1
Output
Test Point
R2
CL
16493D-12
Commercial
Measured
Specification
PD, tCO
tEA
S1
CL
R1
R2
Output Value
t
Closed
1.5 V
1.5 V
Z → H: Open
Z → L: Closed
50 pF
5 pF
200 Ω
390 Ω
tER
H → Z: Open
L → Z: Closed
H-5:
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
200 Ω
2-56
PALCE16V8 Family
AMD
TYPICAL ICC CHARACTERISTICS
VCC = 5 V, TA = 25°C
150
125
100
16V8H-5
16V8H-7
ICC (mA)
75
50
25
0
16V8H-10
16V8H-15/25
16V8Q-10/15/25
0
10
20
30
40
50
16493D-13
Frequency (MHz)
ICC vs. Frequency
The selected “typical” pattern utilized 50% of the device resources. Half of the macrocells were programmed as registered, and
the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any
vector, half of the outputs were switching.
By utilizing 50% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to
estimate the ICC requirements for a particular design.
PALCE16V8 Family
2-57
AMD
ENDURANCE CHARACTERISTICS
The PALCE16V8 is manufactured using AMD’s ad-
vanced Electrically Erasable process. This technology
uses an EE cell to replace the fuse link used in bipolar
parts. As a result, the device can be erased and
reprogrammed—a feature which allows 100% testing at
the factory.
Symbol Parameter
tDR Min Pattern Data Retention Time
Test Conditions
Min
Unit
Max Storage Temperature
10
20
Years
Years
Cycles
Max Operating Temperature
Normal Programming Conditions
N
Min Reprogramming Cycles
100
2-58
PALCE16V8 Family
AMD
clocking caused by subsequent ringing. A special noise
filtermakestheprogrammingcircuitrycompletelyinsen-
sitive to any positive overshoot that has a pulse width of
less than about 100 ns for the /5 versions. Selected /4
devices are also being retrofitted with these robustness
features. See chart below for device listings.
ROBUSTNESS FEATURES
PALCE16V8X-X/5 devices have some unique features
that make them extremely robust, especially when oper-
ating in high-speed design environments. Pull-up resis-
tors on inputs and I/O pins cause unconnected pins to
default to a known state. Input clamping circuitry limits
negative overshoot, eliminating the possibility of false
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR /5 VERSIONS AND SELECTED /4
VERSIONS*
VCC
VCC
> 50 kΩ
ESD
Protection
and
Programming
Pins only
Programming
Voltage
Detection
Positive
Overshoot
Filter
Programming
Circuitry
Clamping
Typical Input
VCC
VCC
> 50 kΩ
Provides ESD
Protection and
Clamping
Preload Feedback
Circuitry
Input
16493D-14
Typical Output
*
Rev Letter
Topside Marking:
Device
PALCE16V8H-10
PALCE16V8H-15 D, E, F, G, I, J, K
Filter Only
Filter and Pullups
AMD CMOS PLD’s are marked on the top of the package in the
following manner:
E, F, K
L
L, M
M
PALCEXXXX
Date Code (3 numbers) Lot ID (4 characters)– –(Rev. Letter)
PALCE16V8Q-15
PALCE16V8H-25
PALCE16V8Q-25
D, G, J
D, G, J
D, G, J
The Lot ID and Rev Letter are separated by two spaces.
M
M
PALCE16V8 Family
2-59
AMD
and the wide range of ways VCC can rise to its steady
state, two conditions are required to insure a valid
power-up reset. These conditions are:
POWER-UP RESET
The PALCE16V8 has been designed with the capability
to reset during system power-up. Following power-up,
all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature pro-
vides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset
The VCC rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Parameter
Symbol
Parameter Descriptions
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
Min
Max
Unit
tPR
1000
ns
tS
See Switching Characteristics
tWL
VCC
4 V
Power
tPR
Registered
Output
tS
Clock
tWL
16493D-15
Power-Up Reset Waveform
2-60
PALCE16V8 Family
AMD
TYPICAL THERMAL CHARACTERISTICS
/4 Devices (PALCE16V8H-10/4)
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
PDIP
25
PLCC
22
Unit
θjc
Thermal Impedance, Junction to Case
Thermal Impedance, Junction to Ambient
Thermal Impedance, Junction to Ambient with Air Flow
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θja
71
64
θjma
200 Ifpm air
400 Ifpm air
600 Ifpm air
800 Ifpm air
61
55
55
51
51
47
47
45
/5 Devices (PALCE16V8H-7/5)
Measured at 25°C ambient. These parameters are not tested.
Typ
Parameter
Symbol
Parameter Description
PDIP
29
70
64
58
53
X
PLCC
23
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θjc
Thermal Impedance, Junction to Case
Thermal Impedance, Junction to Ambient
Thermal Impedance, Junction to Ambient with Air Flow
θja
61
θjma
200 Ifpm air
400 Ifpm air
600 Ifpm air
800 Ifpm air
53
47
44
X
Plastic θjc Considerations
The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The
heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the
package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the
package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a
constant temperature. Therefore, the measurements can only be used in a similar environment.
PALCE16V8 Family
2-61
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