PD640G98UI_技术文档

Am29PDL640G

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not available for designs. For new and current designs,

S29PL064J supersedes Am29PDL640G and is the factory-recommended migration path. Please refer

to the S29PL064J datasheet for specifications and ordering information. Availability of this document

is retained for reference and historical purposes only.

April 2005

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number 26573 Revision B Amendment +2 Issue Date December 13, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29PDL640G

64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only,

Simultaneous Read/Write Flash Memory with Enhanced

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ARCHITECTURAL ADVANTAGES

SOFTWARE FEATURES

Software command-set compatible with JEDEC 42.4

standard

64 Mbit Page Mode device

— Page size of 8 words: Fast page read access from

random locations within the page

— Backward compatible with Am29F and Am29LV

families

Single power supply operation

CFI (Common Flash Interface) complaint

— Full Voltage range: 2.7 to 3.1 volt read, erase, and

program operations for battery-powered applications

— Provides device-specific information to the system,

allowing host software to easily reconfigure for

different Flash devices

Simultaneous Read/Write Operation

— Data can be continuously read from one bank while

executing erase/program functions in another bank

Erase Suspend / Erase Resume

— Suspends an erase operation to allow read or

program operations in other sectors of same bank

— Zero latency switching from write to read operations

Unlock Bypass Program command

FlexBank Architecture

— Reduces overall programming time when issuing

multiple program command sequences

— 4 separate banks, with up to two simultaneous

operations per device

— Bank A: 8 Mbit (4 Kw x 8 and 32Kw x 15)

— Bank B: 24 Mbit (32 Kw x 48)

— Bank C: 24 Mbit (32 Kw x 48)

HARDWARE FEATURES

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting program or

erase cycle completion

— Bank D: 8 Mbit (4 Kw x 8 and 32 Kw x 15)

Enhanced VersatileI/O^TM(V_IO) Control

Hardware reset pin (RESET#)

— Output voltage generated and input voltages tolerated

on all control inputs and I/Os is determined by the

voltage on the V_IOpin

SecSi^TM(Secured Silicon) Sector region

— Hardware method to reset the device to reading array

data

WP#/ACC (Write Protect/Accelerate) input

— At V_IL, protects the first and last two 4K word sectors,

regardless of sector protect/unprotect status

— Up to 128 words accessible through a command

sequence

— At V_IH, allows removal of sector protection

Both top and bottom boot blocks in one device

Manufactured on 0.17 µm process technology

20-year data retention at 125°C

— At V_HH, provides faster programming times in a factory

setting

Persistent Sector Protection

Minimum 1 million erase cycle guarantee per sector

— A command sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector

PERFORMANCE CHARACTERISTICS

High Performance

— Sectors can be locked and unlocked in-system at V_CC

level

— Page access times as fast as 25 ns

— Random access times as fast as 65 ns

Password Sector Protection

Power consumption (typical values at 10 MHz)

— A sophisticated sector protection method to lock

combinations of individual sectors and sector groups

to prevent program or erase operations within that

sector using a user-defined 64-bit password

— 25 mA active read current

— 15 mA program/erase current

— 0.2 µA typical standby mode current

Package options

— 63-ball Fine-pitch BGA

— 80-ball Fine-pitch BGA

Publication# 26573

Issue Date: December 13, 2005

Rev: B Amendment/+2

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Refer to AMD’s Website (www.amd.com) for the latest information.

D A T A S H E E T

GENERAL DESCRIPTION

The Am29PDL640G is a 64 Mbit, 3.0 volt-only Page Mode

and Simultaneous Read/Write Flash memory device orga-

nized as 4 Mwords. The device is offered in 63- or 80-ball

Fine-pitch BGA packages. The word-wide data (x16) ap-

pears on DQ15-DQ0. This device can be programmed

in-system or in standard EPROM programmers. A 12.0 V

V_PPis not required for write or erase operations.

The device is entirely command set compatible with the

JEDEC 42.4 single-power-supply Flash standard. Com-

mands are written to the command register using standard

microprocessor write timing. Register contents serve as in-

puts to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch ad-

dresses and data needed for the programming and erase

operations. Reading data out of the device is similar to read-

ing from other Flash or EPROM devices.

The device offers fast page access times of 25, 30, and 45

ns, with corresponding random access times of 65, 70, 85,

and 90 ns, respectively, allowing high speed microproces-

sors to operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

Device programming occurs by executing the program com-

mand sequence. The Unlock Bypass mode facilitates faster

programming times by requiring only two write cycles to pro-

gram data instead of four. Device erasure occurs by execut-

ing the erase command sequence.

Simultaneous Read/Write Operation with

Zero Latency

The host system can detect whether a program or erase op-

eration is complete by reading the DQ7 (Data# Polling) and

DQ6 (toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or ac-

cept another command.

The Simultaneous Read/Write architecture provides simul-

taneous operation by dividing the memory space into 4

banks, which can be considered to be four separate memory

arrays as far as certain operations are concerned. The de-

vice can improve overall system performance by allowing a

host system to program or erase in one bank, then immedi-

ately and simultaneously read from another bank with zero

latency (with two simultaneous operations operating at any

one time). This releases the system from waiting for the

completion of a program or erase operation, greatly improv-

ing system performance.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

Hardware data protection measures include a low V_CCde-

tector that automatically inhibits write operations during

power transitions. The hardware sector protection feature

disables both program and erase operations in any combina-

tion of sectors of memory. This can be achieved in-system or

via programming equipment.

The device can be organized in both top and bottom sector

configurations. The banks are organized as follows:

Bank

Sectors

8 Mbit (4 Kw x 8 and 32 Kw x 15)

The Erase Suspend/Erase Resume feature enables the

user to put erase on hold for any period of time to read data

from, or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved. If a

read is needed from the SecSi Sector area (One Time Pro-

gram area) after an erase suspend, then the user must use

the proper command sequence to enter and exit this region.

A

B

C

D

24 Mbit (32 Kw x 48)

8 Mbit (4 Kw x 8 and 32 Kw x 15)

Page Mode Features

The device is AC timing, input/output, and package compat-

ible with 4 Mbit x16 page mode mask ROM. The page size

is 8 words.

The device offers two power-saving features. When ad-

dresses have been stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both these modes.

After initial page access is accomplished, the page mode op-

eration provides fast read access speed of random locations

within that page.

AMD’s Flash technology combined years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via

Fowler-Nordheim tunneling. The data is programmed using

hot electron injection.

Standard Flash Memory Features

The device requires a single 3.0 volt power supply (2.7 V

to 3.1 V) for both read and write functions. Internally gener-

ated and regulated voltages are provided for the program

and erase operations.

2

Am29PDL640G

December 13, 2005

D A T A S H E E T

TABLE OF CONTENTS

Table 11. System Interface String................................................... 25

Table 12. Device Geometry Definition................................. 26

Table 13. Primary Vendor-Specific Extended Query........... 27

Command Definitions. . . . . . . . . . . . . . . . . . . . . . 28

Reading Array Data ................................................................ 28

Reset Command ..................................................................... 28

Autoselect Command Sequence ............................................ 28

Enter SecSi™ Sector/Exit SecSi Sector

Product Selector Guide. . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Simultaneous READ/Write Block Diagram . . . . . 6

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ordering Information. . . . . . . . . . . . . . . . . . . . . . 10

Device Bus Operations . . . . . . . . . . . . . . . . . . . . 11

Table 1. Am29PDL640G Device Bus Operations ...........................11

Requirements for Reading Array Data ................................... 11

Random Read (Non-Page Read) ........................................... 11

Page Mode Read .................................................................... 11

Table 2. Page Select .......................................................................12

Simultaneous Operation ......................................................... 12

Table 3. Bank Select .......................................................................12

Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation ............................................. 12

Autoselect Functions .............................................................. 12

Standby Mode ........................................................................ 12

Automatic Sleep Mode ........................................................... 13

RESET#: Hardware Reset Pin ............................................... 13

Output Disable Mode .............................................................. 13

Table 4. Am29PDL640G Sector Architecture .................................13

Table 5. Bank Address ....................................................................15

Table 6. SecSi^TMSector Addresses ...............................................15

Autoselect Mode..................................................................... 15

Table 7. Autoselect Codes (High Voltage Method) ........................16

Table 8. Am29PDL640G Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................................16

Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . 17

Persistent Sector Protection ................................................... 17

Persistent Protection Bit (PPB) ............................................... 17

Persistent Protection Bit Lock (PPB Lock) ............................. 17

Dynamic Protection Bit (DYB) ................................................ 17

Table 9. Sector Protection Schemes ...............................................18

Persistent Sector Protection Mode Locking Bit ...................... 18

Password Protection Mode ..................................................... 18

Password and Password Mode Locking Bit ........................... 19

64-bit Password ...................................................................... 19

Write Protect (WP#) ................................................................ 19

Persistent Protection Bit Lock ................................................. 19

High Voltage Sector Protection .............................................. 20

Figure 1. In-System Sector Protection/

Command Sequence .............................................................. 29

Word Program Command Sequence ...................................... 29

Unlock Bypass Command Sequence ..................................... 29

Figure 4. Program Operation ......................................................... 30

Chip Erase Command Sequence ........................................... 30

Sector Erase Command Sequence ........................................ 30

Erase Suspend/Erase Resume Commands ........................... 31

Figure 5. Erase Operation.............................................................. 31

Password Program Command ................................................ 31

Password Verify Command .................................................... 32

Password Protection Mode Locking Bit Program Command .. 32

Persistent Sector Protection Mode Locking Bit Program

Command ............................................................................... 32

SecSi Sector Protection Bit Program Command ....................32

PPB Lock Bit Set Command ................................................... 32

DYB Write Command ............................................................. 32

Password Unlock Command .................................................. 33

PPB Program Command ........................................................ 33

All PPB Erase Command ........................................................ 33

DYB Write Command ............................................................. 33

PPB Lock Bit Set Command ................................................... 33

PPB Status Command ............................................................ 33

PPB Lock Bit Status Command .............................................. 33

Sector Protection Status Command ....................................... 33

Command Definitions Tables.................................................. 34

Table 14. Memory Array Command Definitions ............................. 34

Table 15. Sector Protection Command Definitions ........................ 35

Write Operation Status. . . . . . . . . . . . . . . . . . . . . 36

DQ7: Data# Polling ................................................................. 36

Figure 6. Data# Polling Algorithm .................................................. 36

RY/BY#: Ready/Busy#............................................................ 37

DQ6: Toggle Bit I .................................................................... 37

Figure 7. Toggle Bit Algorithm........................................................ 37

DQ2: Toggle Bit II ................................................................... 38

Reading Toggle Bits DQ6/DQ2 ............................................... 38

DQ5: Exceeded Timing Limits ................................................ 38

DQ3: Sector Erase Timer ....................................................... 38

Table 16. Write Operation Status ................................................... 39

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 40

Figure 8. Maximum Negative Overshoot Waveform ...................... 40

Figure 9. Maximum Positive Overshoot Waveform........................ 40

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 10. Test Setup.................................................................... 42

Figure 11. Input Waveforms and Measurement Levels ................. 42

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43

Read-Only Operations ........................................................... 43

Figure 12. Read Operation Timings............................................... 43

Figure 13. Page Read Operation Timings...................................... 44

Sector Unprotection Algorithms ...................................................... 21

Temporary Sector Unprotect .................................................. 22

Figure 2. Temporary Sector Unprotect Operation........................... 22

SecSi™ (Secured Silicon) Sector

Flash Memory Region ............................................................ 22

SecSi Sector Protection Bit .................................................... 23

Figure 3. SecSi Sector Protect Verify.............................................. 23

Hardware Data Protection ...................................................... 23

Low VCC Write Inhibit ............................................................ 23

Write Pulse “Glitch” Protection ............................................... 23

Logical Inhibit .......................................................................... 23

Power-Up Write Inhibit ............................................................ 23

Common Flash Memory Interface (CFI). . . . . . . 23

Table 10. CFI Query Identification String ............................ 25

December 13, 2005

Am29PDL640G

3

D A T A S H E E T

Figure 24. Alternate CE# Controlled Write (Erase/Program)

Hardware Reset (RESET#) .................................................... 45

Figure 14. Reset Timings................................................................ 45

Erase and Program Operations .............................................. 46

Figure 15. Program Operation Timings........................................... 47

Figure 16. Accelerated Program Timing Diagram........................... 47

Figure 17. Chip/Sector Erase Operation Timings ........................... 48

Figure 18. Back-to-back Read/Write Cycle Timings ....................... 49

Figure 19. Data# Polling Timings (During Embedded Algorithms).. 49

Figure 20. Toggle Bit Timings (During Embedded Algorithms)....... 50

Figure 21. DQ2 vs. DQ6.................................................................. 50

Temporary Sector Unprotect .................................................. 51

Figure 22. Temporary Sector Unprotect Timing Diagram ............... 51

Figure 23. Sector/Sector Block Protect and

Operation Timings.......................................................................... 54

Erase And Programming Performance. . . . . . . . 55

Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 55

BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 55

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56

FBE080—80-Ball Fine-pitch Ball Grid Array

12 x 11 mm package .............................................................. 56

FBE063—63-Ball Fine-pitch Ball Grid Array

12 x 11 mm package .............................................................. 57

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 58

Unprotect Timing Diagram .............................................................. 52

Alternate CE# Controlled Erase and Program Operations ..... 53

4

Am29PDL640G

December 13, 2005

D A T A S H E E T

PRODUCT SELECTOR GUIDE

Part Number

Am29PDL640G

V

_CC, V_IO= 2.7–3.1 V

V_CC= 2.7–3.1 V, V_IO= 1.65–1.95 V

Max Access Time, ns (t_ACC

Max CE# Access, ns (t_CE

Max Page Access, ns (t_PACC

Max OE# Access, ns (t_OE

63

73

83

Speed Option

98

90

45

)

65

25

70

25

85

30

)

BLOCK DIAGRAM

DQ15–DQ0

RY/BY# (See Note)

V

CC

V

SS

Sector

Switches

V

IO

Input/Output

Buffers

RESET#

WE#

Erase Voltage

Generator

State

Control

Command

Register

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

CE#

OE#

STB

Data Latch

Y-Gating

Y-Decoder

X-Decoder

STB

V

CC

Detector

Timer

A21–A3

Cell Matrix

A2–A0

Note:RY/BY# is an open drain output.

December 13, 2005

Am29PDL640G

5

D A T A S H E E T

SIMULTANEOUS READ/WRITE BLOCK DIAGRAM

V

CC

OE#

SS

Mux

Bank A

Bank A Address

A21–A0

X-Decoder

Bank B Address

RY/BY#

Bank B

X-Decoder

A21–A0

RESET#

STATE

CONTROL

&

COMMAND

REGISTER

Status

WE#

DQ15–DQ0

CE#

WP#/ACC

Control

Mux

X-Decoder

Bank C

DQ0–DQ15

Bank C Address

Bank D Address

X-Decoder

Bank D

A21–A0

Mux

6

Am29PDL640G

December 13, 2005

D A T A S H E E T

CONNECTION DIAGRAMS

80-Ball Fine-pitch BGA

Top View, Balls Facing Down

A8

B8

C8

D8

E8

F8

G8

H8

J8

K8

L8

M8

NC

V_IO

V_SS

NC

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

NC

A13

A12

A14

A15

A16

NC

DQ15

V_SS

NC

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

WE# RESET#

A21

A19

DQ5

DQ12

V_CC

DQ4

C4 D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

A2

B2

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

NC

CE#

OE#

V_SS

NC

A1

B1

C1

D1

E1

F1

G1

NC

H1

J1

K1

L1

M1

NC

V_IO

NC

December 13, 2005

Am29PDL640G

7

D A T A S H E E T

CONNECTION DIAGRAMS

63-Ball Fine-pitch BGA

Top View, Balls Facing Down

L8

M8

A8

B8

NC

NC*

A7

B7

C7

D7

E7

F7

G7

H7

J7

K7

L7

M7

V_SS

NC

NC*

A13

A12

A14

A15

A16

NC

DQ15

C6

A9

D6

A8

E6

F6

G6

H6

J6

K6

A10

A11

DQ7

DQ14

DQ13

DQ6

C5

D5

E5

F5

G5

H5

J5

K5

V_CC

WE# RESET#

A21

A19

DQ5

DQ12

DQ4

C4 D4

E4

F4

G4

H4

J4

K4

RY/BY# WP#/ACC A18

A20

DQ2

DQ10

DQ11

DQ3

C3

A7

D3

E3

A6

F3

A5

G3

H3

J3

K3

A17

DQ0

DQ8

DQ9

DQ1

C2

A3

D2

A4

E2

A2

F2

A1

G2

A0

H2

J2

K2

L2

M2

A2

V_SS

CE#

OE#

NC*

A1

B1

L1

M1

* Balls are shorted together via the substrate but not connected to the die.

NC*

Notes:V_IO= V_CCfor 63-Ball Fine-pitch BGA package.

8

Am29PDL640G

December 13, 2005

D A T A S H E E T

PIN DESCRIPTION

LOGIC SYMBOL

A21–A0

= 22 Addresses

22

DQ15–DQ0 = 16 Data Inputs/Outputs

A21–A0

16

CE#

OE#

WE#

= Chip Enable

= Output Enable

= Write Enable

DQ15–DQ0

CE#

OE#

WP#/ACC = Hardware Write Protect/Program Ac-

celeration Input

WE#

RESET#

RY/BY#

V_CC

= Hardware Reset Pin, Active Low

= Ready/Busy Output

WP#/ACC

RESET#

RY/BY#

= 3.0 Volt-only Single Power Supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

V_IO(N/A 63-ball FBGA)

V_IO

= Output Buffer Power Supply (not avail-

able in 63-ball FBGA package)

V_SS

NC

= Device Ground

= Pin Not Connected Internally

December 13, 2005

Am29PDL640G

9

D A T A S H E E T

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combination of the following:

Am29PDL640G

63

WS

I

OPTIONAL PROCESSING

Blank = Standard Processing

N

=

16-byte ESN devices

(Contact an AMD representative for more information)

TEMPERATURE RANGE

I

=

Industrial (–40°C to +85°C)

PACKAGE TYPE

WH

WS

=

63-ball Fine-pitch Ball Grid Array

0.8 mm pitch, 12 x 11 mm package (FBE063)

80-Ball Fine-pitch Ball Grid Array

0.8 mm pitch, 12 x 11 mm package (FBE080)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29PDL640G

64 Megabit (4 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations

Valid Combinations for BGA Packages

Valid Combinations list configurations planned to be supported in

volume for this device. Consult the local AMD sales office to con-

firm availability of specific valid combinations and to check on

newly released combinations.

Speed

(ns)

V_IO

Range

Order Number

Package Marking

Am29PDL640G63

Am29PDL640G73

Am29PDL640G83

WHI PD640G63V

65

WSI PD640G63U

WHI PD640G73V

WSI PD640G73U

WHI PD640G83V

WSI PD640G83U

2.7–

3.1 V

Note: For the Am29PDL640G, the last digit of the speed indicator

specifies V range. Speed grades ending in 3 (such as 73,83) indicate

a 3 Volt V_IOrange; speed grades ending in 8 (such as 98) indicate a

1.8V V_IOrange.

70

IO

I

85

90

1.65–

1.95 V

Am29PDL640G98

WSI PD640G98U

10

Am29PDL640G

December 13, 2005

D A T A S H E E T

DEVICE BUS OPERATIONS

This section describes the requirements and use of

the device bus operations, which are initiated through

the internal command register. The command register

itself does not occupy any addressable memory loca-

tion. The register is a latch used to store the com-

mands, along with the address and data information

needed to execute the command. The contents of the

register serve as inputs to the internal state machine.

The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the in-

puts and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29PDL640G Device Bus Operations

Addresses

(Note 1)

DQ15–

DQ0

Operation

CE#

L

OE#

L

WE#

H

RESET#

WP#/ACC

Read

Write

H

X

A_IN

D_OUT

D_IN

L

H

L

V_IO±

0.3 V

V_IO±

0.3 V

Standby

X

High-Z

Output Disable

Reset

L

H

X

H

X

H

L

X

High-Z

X

Temporary Sector Unprotect (High

Voltage)

X

V_ID

X

A_IN

D_IN

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, V_ID= 11.5–12.5 V, V_HH= 8.5–9.5 V, X = Don’t Care, SA = Sector Address,

A_IN= Address In, D_IN= Data In, D_OUT= Data Out

Notes:

1. Addresses are A21–A0.

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High Voltage

Sector Protection section.

Random Read (Non-Page Read)

Requirements for Reading Array Data

Address access time (t_ACC) is equal to the delay from

stable addresses to valid output data. The chip enable

access time (t_CE) is the delay from the stable ad-

dresses and stable CE# to valid data at the output in-

puts. The output enable access time is the delay from

the falling edge of the OE# to valid data at the output

inputs (assuming the addresses have been stable for

at least t_ACC–t_OEtime).

To read array data from the outputs, the system must

drive the CE# and OE# pins to V_IL. CE# is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V_IH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

Page Mode Read

The device is capable of fast page mode read and is

compatible with the page mode Mask ROM read oper-

ation. This mode provides faster read access speed

for random locations within a page. The page size of

the device is 8 words, with the appropriate page being

selected by the higher address bits A21–A3 and the

LSB bits A2–A0 determining the specific word within

that page. This is an asynchronous operation with the

microprocessor supplying the specific word location.

Refer to the AC Read-Only Operations table for timing

specifications and to Figure 12 for the timing diagram.

I_CC1in the DC Characteristics table represents the ac-

tive current specification for reading array data.

The random or initial page access is equal to t_ACCor

t_CEand subsequent page read accesses (as long as

the locations specified by the microprocessor falls

within that page) is equivalent to t_PACC. When CE# is

December 13, 2005

Am29PDL640G

11

D A T A S H E E T

deasserted and reasserted for a subsequent access,

gram Command Sequence” section has details on

programming data to the device using both standard

and Unlock Bypass command sequences.

the access time is t_ACCor t_CE. Here again, CE# selects

the device and OE# is the output control and should

be used to gate data to the output inputs if the device

is selected. Fast page mode accesses are obtained by

keeping A21–A3 constant and changing A2 to A0 to

select the specific word within that page.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 4 indicates the address

space that each sector occupies. A “bank address” is

the address bits required to uniquely select a bank.

Similarly, a “sector address” refers to the address bits

required to uniquely select a sector. The “Command

Definitions” section has details on erasing a sector or

the entire chip, or suspending/resuming the erase op-

eration.

Table 2. Page Select

Word

A2

0

A1

0

A0

0

Word 0

Word 1

Word 2

Word 3

Word 4

Word 5

Word 6

Word 7

I_CC2in the DC Characteristics table represents the ac-

0

1

tive current specification for the write mode. The AC

Characteristics section contains timing specification

tables and timing diagrams for write operations.

0

1

0

1

Accelerated Program Operation

1

0

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput at the

factory.

1

0

1

0

1

If the system asserts V_HHon this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

Simultaneous Operation

The device is capable of reading data from one bank

of memory while a program or erase operation is in

progress in another bank of memory (simultaneous

operation), in addition to the conventional features

(read, program, erase-suspend read, and erase-sus-

pend program). The bank selected can be selected by

bank addresses (A21–A19) with zero latency.

V

_HHfrom the WP#/ACC pin returns the device to nor-

mal operation. Note that V_HHmust not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin should be raised to V_CCwhen not in

use. That is, the WP#/ACC pin should not be left float-

ing or unconnected; inconsistent behavior of the de-

vice may result.

The simultaneous operation can execute multi-func-

tion mode in the same bank.

Table 3. Bank Select

Bank

A21–A19

000

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Bank A

Bank B

Bank C

Bank D

001, 010, 011

100, 101, 110

111

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V_IL, and OE# to V_IH.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word, instead of four. The “Word Pro-

12

Am29PDL640G

December 13, 2005

D A T A S H E E T

The device enters the CMOS standby mode when the

tem can thus monitor RY/BY# to determine whether

the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing

(RY/BY# pin is “1”), the reset operation is completed

within a time of t_READY(not during Embedded Algo-

rithms). The system can read data t_RHafter the RE-

SET# pin returns to V_IH.

CE# and RESET# pins are both held at V_IO0.3 V.

(Note that this is a more restricted voltage range than

V_IH.) If CE# and RESET# are held at V_IH, but not within

V_IO0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device re-

quires standard access time (t_CE) for read access

when the device is in either of these standby modes,

before it is ready to read data.

Refer to the AC Characteristics tables for RESET# pa-

rameters and to Figure 14 for the timing diagram.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

Output Disable Mode

When the OE# input is at V_IH, output from the device is

disabled. The output pins (except for RY/BY#) are

placed in the high impedance state.

I_CC3in the DC Characteristics table represents the

CMOS standby current specification.

Table 4. Am29PDL640G Sector Architecture

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables

Sector

Address

A21–A12

Sector

Size

(Kwords)

Bank Sector

Address Range

this mode when addresses remain stable for t_ACC

+

SA0

SA1

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

0000001xxx

0000010xxx

0000011xxx

0000100xxx

0000101xxx

0000110xxx

0000111xxx

0001000xxx

0001001xxx

0001010xxx

0001011xxx

0001100xxx

0001101xxx

0001111xxx

4

00000h–00FFFh

01000h–01FFFh

02000h–02FFFh

03000h–03FFFh

04000h–04FFFh

05000h–05FFFh

06000h–06FFFh

07000h–07FFFh

08000h–0FFFFh

10000h–17FFFh

18000h–1FFFFh

20000h–27FFFh

28000h–2FFFFh

30000h–37FFFh

38000h–3FFFFh

40000h–47FFFh

48000h–4FFFFh

50000h–57FFFh

58000h–5FFFFh

60000h–67FFFh

68000h–6FFFFh

70000h–77FFFh

78000h–7FFFFh

30 ns. The automatic sleep mode is independent of

the CE#, WE#, and OE# control signals. Standard ad-

dress access timings provide new data when ad-

dresses are changed. While in sleep mode, output

data is latched and always available to the system.

Note that during automatic sleep mode, OE# must be

at V_IHbefore the device reduces current to the stated

sleep mode specification. I_CC5in the DC Characteris-

tics table represents the automatic sleep mode current

specification.

4

SA2

4

SA3

4

SA4

4

SA5

4

SA6

4

SA7

4

SA8

32

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of re-

setting the device to reading array data. When the RE-

SET# pin is driven low for at least a period of t_RP, the

device immediately terminates any operation in

progress, tristates all output pins, and ignores all

read/write commands for the duration of the RESET#

pulse. The device also resets the internal state ma-

chine to reading array data. The operation that was in-

terrupted should be reinitiated once the device is

ready to accept another command sequence, to en-

sure data integrity.

Current is reduced for the duration of the RESET#

pulse. When RESET# is held at V_SS0.3 V, the device

draws CMOS standby current (I_CC4). If RESET# is held

at V_ILbut not within V_SS0.3 V, the standby current will

be greater.

The RESET# pin may be tied to the system reset cir-

cuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firm-

ware from the Flash memory.

If RESET# is asserted during a program or erase op-

eration, the RY/BY# pin remains a “0” (busy) until the

internal reset operation is complete, which requires a

time of t_READY(during Embedded Algorithms). The sys-

December 13, 2005

Am29PDL640G

13

D A T A S H E E T

Table 4. Am29PDL640G Sector Architecture Table 4. Am29PDL640G Sector Architecture

Sector

Address

A21–A12

Sector

Size

(Kwords)

Sector

Address

A21–A12

Sector

Size

(Kwords)

Bank Sector

Address Range

Bank Sector

Address Range

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

0010000xxx

0010001xxx

0010010xxx

0010011xxx

0010100xxx

0010101xxx

0010110xxx

0010111xxx

0011000xxx

0011001xxx

0011010xxx

0011011xxx

0011000xxx

0011101xxx

0011110xxx

0011111xxx

0100000xxx

0100001xxx

0100010xxx

0101011xxx

0100100xxx

0100101xxx

0100110xxx

0100111xxx

0101000xxx

0101001xxx

0101010xxx

0101011xxx

0101100xxx

0101101xxx

0101110xxx

0101111xxx

0110000xxx

0110001xxx

0110010xxx

0110011xxx

0100100xxx

0110101xxx

0110110xxx

0110111xxx

0111000xxx

0111001xxx

0111010xxx

0111011xxx

0111100xxx

0111101xxx

0111110xxx

0111111xxx

32

80000h–87FFFh

88000h–8FFFFh

SA71

SA72

SA73

SA74

SA75

SA76

SA77

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

SA118

1000000xxx

1000001xxx

1000010xxx

1000011xxx

1000100xxx

1000101xxx

1000110xxx

1000111xxx

1001000xxx

1001001xxx

1001010xxx

1001011xxx

1001100xxx

1001101xxx

1001110xxx

1001111xxx

1010000xxx

1010001xxx

1010010xxx

1010011xxx

1010100xxx

1010101xxx

1010110xxx

1010111xxx

1011000xxx

1011001xxx

1011010xxx

1011011xxx

1011100xxx

1011101xxx

1011110xxx

1011111xxx

1100000xxx

1100001xxx

1100010xxx

1100011xxx

1100100xxx

1100101xxx

1100110xxx

1100111xxx

1101000xxx

1101001xxx

1101010xxx

1101011xxx

1101100xxx

1101101xxx

1101110xxx

1101111xxx

32

200000h–207FFFh

208000h–20FFFFh

210000h–217FFFh

218000h–21FFFFh

220000h–227FFFh

228000h–22FFFFh

230000h–237FFFh

238000h–23FFFFh

240000h–247FFFh

248000h–24FFFFh

250000h–257FFFh

258000h–25FFFFh

260000h–267FFFh

268000h–26FFFFh

270000h–277FFFh

278000h–27FFFFh

280000h–28FFFFh

288000h–28FFFFh

290000h–297FFFh

298000h–29FFFFh

2A0000h–2A7FFFh

2A8000h–2AFFFFh

2B0000h–2B7FFFh

2B8000h–2BFFFFh

2C0000h–2C7FFFh

2C8000h–2CFFFFh

2D0000h–2D7FFFh

2D8000h–2DFFFFh

2E0000h–2E7FFFh

2E8000h–2EFFFFh

2F0000h–2FFFFFh

2F8000h–2FFFFFh

300000h–307FFFh

308000h–30FFFFh

310000h–317FFFh

318000h–31FFFFh

320000h–327FFFh

328000h–32FFFFh

330000h–337FFFh

338000h–33FFFFh

340000h–347FFFh

348000h–34FFFFh

350000h–357FFFh

358000h–35FFFFh

360000h–367FFFh

368000h–36FFFFh

370000h–377FFFh

378000h–37FFFFh

90000h–97FFFh

98000h–9FFFFh

A0000h–A7FFFh

A8000h–AFFFFh

B0000h–B7FFFh

B8000h–BFFFFh

C0000h–C7FFFh

C8000h–CFFFFh

D0000h–D7FFFh

D8000h–DFFFFh

E0000h–E7FFFh

E8000h–EFFFFh

F0000h–F7FFFh

F8000h–FFFFFh

F9000h–107FFFh

108000h–10FFFFh

110000h–117FFFh

118000h–11FFFFh

120000h–127FFFh

128000h–12FFFFh

130000h–137FFFh

138000h–13FFFFh

140000h–147FFFh

148000h–14FFFFh

150000h–157FFFh

158000h–15FFFFh

160000h–167FFFh

168000h–16FFFFh

170000h–177FFFh

178000h–17FFFFh

180000h–187FFFh

188000h–18FFFFh

190000h–197FFFh

198000h–19FFFFh

1A0000h–1A7FFFh

1A8000h–1AFFFFh

1B0000h–1B7FFFh

1B8000h–1BFFFFh

1C0000h–1C7FFFh

1C8000h–1CFFFFh

1D0000h–1D7FFFh

1D8000h–1DFFFFh

1E0000h–1E7FFFh

1E8000h–1EFFFFh

1F0000h–1F7FFFh

1F8000h–1FFFFFh

14

Am29PDL640G

December 13, 2005

D A T A S H E E T

Table 4. Am29PDL640G Sector Architecture

Autoselect Mode

Sector

Address

A21–A12

Sector

Size

(Kwords)

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended for programming equip-

ment to automatically match a device to be pro-

grammed with its corresponding programming

algorithm. However, the autoselect codes can also be

accessed in-system through the command register.

Bank Sector

Address Range

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

1110000xxx

1110001xxx

1110010xxx

1110011xxx

1110100xxx

1110101xxx

1110110xxx

1110111xxx

1111000xxx

1111001xxx

1111010xxx

1111011xxx

1111100xxx

1111101xxx

1111110xxx

32

4

380000h–387FFFh

388000h–38FFFFh

390000h–397FFFh

398000h–39FFFFh

3A0000h–3A7FFFh

3A8000h–3AFFFFh

3B0000h–3B7FFFh

3B8000h–3BFFFFh

3C0000h–3C7FFFh

3C8000h–3CFFFFh

3D0000h–3D7FFFh

3D8000h–3DFFFFh

3E0000h–3E7FFFh

3E8000h–3EFFFFh

3F0000h–3F7FFFh

3F8000h–3F8FFFh

3F9000h–3F9FFFh

3FA000h–3FAFFFh

3FB000h–3FBFFFh

3FC000h–3FCFFFh

3FD000h–3FDFFFh

3FE000h–3FEFFFh

3FF000h–3FFFFFh

When using programming equipment, the autoselect

mode requires V_IDon address pin A9. Address pins

must be as shown in Table 7. In addition, when verify-

ing sector protection, the sector address must appear

on the appropriate highest order address bits (see

Table 4). Table 7 shows the remaining address bits

that are don’t care. When all necessary bits have been

set as required, the programming equipment may then

read the corresponding identifier code on DQ7–DQ0.

However, the autoselect codes can also be accessed

in-system through the command register, for instances

when the device is erased or programmed in a system

without access to high voltage on the A9 pin. The com-

mand sequence is illustrated in Table 14. Note that if a

Bank Address (BA) on address bits A21, A20, and A19

is asserted during the third write cycle of the autose-

lect command, the host system can read autoselect

data that bank and then immediately read array data

from the other bank, without exiting the autoselect

mode.

SA134 1111111000

SA135 1111111001

SA136 1111111010

SA137 1111111011

SA138 1111111100

SA139 1111111101

SA140 1111111110

SA141 1111111111

4

Table 5. Bank Address

Bank

A21–A19

000

A

B

C

D

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in Table 14. This method

does not require V_ID. Refer to the Autoselect Com-

mand Sequence section for more information.

001, 010, 011

100, 101, 110

111

Table 6. SecSi^TMSector Addresses

Device

Sector Size

Address Range

Am29PDL640G

128 words

00000h–0007Fh

December 13, 2005

Am29PDL640G

15

D A T A S H E E T

Table 7. Autoselect Codes (High Voltage Method)

A21

to

A5

to

DQ15

Description

CE# OE# WE#

A12

A10

A9

A8

A7

A6

A4

A3

A2

A1

A0

to DQ0

Manufacturer ID:

AMD

V_ID

L

H

X

L

X

L

0001h

227Eh

2215h

2201h

Read

Cycle 1

L

H

L

H

L

H

L

Read

Cycle 2

V_ID

L

X

L

Read

Cycle 3

H

L

Sector Protection

Verification

0001h (protected),

0000h (unprotected)

V_ID

L

H

SA

X

L

H

X

0080h

(factory locked),

0000h (not factory

locked)

SecSi Indicator Bit

(DQ7)

V_ID

X

L

H

Legend: L = Logic Low = V_IL, H = Logic High = V_IH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Note: The autoselect codes may also be accessed in-system via command sequences.

Table 8. Am29PDL640G Boot Sector/Sector Block

Sector/

Addresses for Protection/Unprotection

Sector

A21–A12

Sector Block Size

SA67–SA70

SA71–SA74

SA75–SA78

SA79–SA82

SA83–SA86

SA87–SA90

SA91–SA94

SA95–SA98

SA99–SA102

SA103–SA106

SA107–SA110

SA111–SA114

SA115–SA118

SA119–SA122

SA123–SA126

SA127–SA130

01111XXXXX

10000XXXXX

10001XXXXX

10010XXXXX

10011XXXXX

10100XXXXX

10101XXXXX

10110XXXXX

10111XXXXX

11000XXXXX

11001XXXXX

11010XXXXX

11011XXXXX

11100XXXXX

11101XXXXX

11110XXXXX

128 (4x32) Kwords

Sector/

Sector Block Size

Sector

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

A21–A12

0000000000

0000000001

0000000010

0000000011

0000000100

0000000101

0000000110

0000000111

4 Kwords

0000001XXX,

0000010XXX,

0000011XXX

SA8–SA10

96 (3x32) Kwords

SA11–SA14

SA15–SA18

SA19–SA22

SA23–SA26

SA27-SA30

SA31-SA34

SA35-SA38

SA39-SA42

SA43-SA46

SA47-SA50

SA51-SA54

SA55–SA58

SA59–SA62

SA63–SA66

00001XXXXX

00010XXXXX

00011XXXXX

00100XXXXX

00101XXXXX

00110XXXXX

00111XXXXX

01000XXXXX

01001XXXXX

01010XXXXX

01011XXXXX

01100XXXXX

01101XXXXX

01110XXXXX

128 (4x32) Kwords

1111100XXX,

1111101XXX,

1111110XXX

SA131–SA133

96 (3x32) Kwords

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

1111111000

1111111001

1111111010

1111111011

1111111100

1111111101

1111111111

4 Kwords

16

Am29PDL640G

December 13, 2005

D A T A S H E E T

SECTOR PROTECTION

The Am29PDL640G features several levels of sector

protection, which can disable both the program and

erase operations in certain sectors or sector groups:

■ Persistently Locked—The sector is protected and

cannot be changed.

■ Dynamically Locked—The sector is protected and

can be changed by a simple command.

Persistent Sector Protection

■ Unlocked—The sector is unprotected and can be

A command sector protection method that replaces

the old 12 V controlled protection method.

changed by a simple command.

To achieve these states, three types of “bits” are used:

Password Sector Protection

A highly sophisticated protection method that requires

a password before changes to certain sectors or sec-

tor groups are permitted

Persistent Protection Bit (PPB)

A single Persistent (non-volatile) Protection Bit is as-

signed to a maximum four sectors (see the sector ad-

dress tables for specific sector protection groupings).

All 4 Kword boot-block sectors have individual sector

Persistent Protection Bits (PPBs) for greater flexibility.

Each PPB is individually modifiable through the PPB

Write Command.

WP# Hardware Protection

A write protect pin that can prevent program or erase

operations in sectors 0, 1, 140, and 141.

All parts default to operate in the Persistent Sector

Protection mode. The customer must then choose if

the Persistent or Password Protection method is most

desirable. There are two one-time programmable

non-volatile bits that define which sector protection

method will be used. If the Persistent Sector Protec-

tion method is desired, programming the Persistent

Sector Protection Mode Locking Bit permanently

sets the device to the Persistent Sector Protection

mode. If the Password Sector Protection method is de-

sired, programming the Password Mode Locking Bit

permanently sets the device to the Password Sector

Protection mode. It is not possible to switch between

the two protection modes once a locking bit has been

set. One of the two modes must be selected when

the device is first programmed. This prevents a pro-

gram or virus from later setting the Password Mode

Locking Bit, which would cause an unexpected shift

from the default Persistent Sector Protection Mode

into the Password Protection Mode.

The device erases all PPBs in parallel. If any PPB re-

quires erasure, the device must be instructed to pre-

program all of the sector PPBs prior to PPB erasure.

Otherwise, a previously erased sector PPBs can po-

tentially be over-erased. The flash device does not

have a built-in means of preventing sector PPBs

over-erasure.

Persistent Protection Bit Lock (PPB Lock)

The Persistent Protection Bit Lock (PPB Lock) is a glo-

bal volatile bit. When set to “1”, the PPBs cannot be

changed. When cleared (“0”), the PPBs are change-

able. There is only one PPB Lock bit per device. The

PPB Lock is cleared after power-up or hardware reset.

There is no command sequence to unlock the PPB

Lock.

Dynamic Protection Bit (DYB)

A volatile protection bit is assigned for each sector.

After power-up or hardware reset, the contents of all

DYBs is “0”. Each DYB is individually modifiable

through the DYB Write Command.

The WP# Hardware Protection feature is always avail-

able, independent of the software managed protection

method chosen.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at the factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

When the parts are first shipped, the PPBs are

cleared, the DYBs are cleared, and PPB Lock is de-

faulted to power up in the cleared state – meaning the

PPBs are changeable.

When the device is first powered on the DYBs power

up cleared (sectors not protected). The Protection

State for each sector is determined by the logical OR

of the PPB and the DYB related to that sector. For the

sectors that have the PPBs cleared, the DYBs control

whether or not the sector is protected or unprotected.

By issuing the DYB Write command sequences, the

DYBs will be set or cleared, thus placing each sector in

the protected or unprotected state. These are the

so-called Dynamic Locked or Unlocked states. They

are called dynamic states because it is very easy to

It is possible to determine whether a sector is pro-

tected or unprotected. See Autoselect Mode for de-

tails.

Persistent Sector Protection

The Persistent Sector Protection method replaces the

12 V controlled protection method in previous AMD

flash devices. This new method provides three differ-

ent sector protection states:

December 13, 2005

Am29PDL640G

17

D A T A S H E E T

switch back and forth between the protected and un-

Table 9. Sector Protection Schemes

protected conditions. This allows software to easily

protect sectors against inadvertent changes yet does

not prevent the easy removal of protection when

changes are needed. The DYBs maybe set or cleared

as often as needed.

PPB

Lock

DYB

PPB

Sector State

Unprotected—PPB and DYB are

changeable

0

The PPBs allow for a more static, and difficult to

change, level of protection. The PPBs retain their state

across power cycles because they are non-volatile. In-

dividual PPBs are set with a command but must all be

cleared as a group through a complex sequence of

program and erasing commands. The PPBs are also

limited to 100 erase cycles.

Unprotected—PPB not

changeable, DYB is changeable

0

1

0

1

0

1

0

1

0

1

0

1

Protected—PPB and DYB are

changeable

The PPB Lock bit adds an additional level of protec-

tion. Once all PPBs are programmed to the desired

settings, the PPB Lock may be set to “1”. Setting the

PPB Lock disables all program and erase commands

to the non-volatile PPBs. In effect, the PPB Lock Bit

locks the PPBs into their current state. The only way to

clear the PPB Lock is to go through a power cycle.

System boot code can determine if any changes to the

PPB are needed; for example, to allow new system

code to be downloaded. If no changes are needed

then the boot code can set the PPB Lock to disable

any further changes to the PPBs during system opera-

tion.

Protected—PPB not

changeable, DYB is changeable

Table 9 contains all possible combinations of the DYB,

PPB, and PPB lock relating to the status of the sector.

In summary, if the PPB is set, and the PPB lock is set,

the sector is protected and the protection can not be

removed until the next power cycle clears the PPB

lock. If the PPB is cleared, the sector can be dynami-

cally locked or unlocked. The DYB then controls

whether or not the sector is protected or unprotected.

The WP#/ACC write protect pin adds a final level of

hardware protection to sectors 0, 1, 140, and 141.

When this pin is low it is not possible to change the

contents of these sectors. These sectors generally

hold system boot code. The WP#/ACC pin can prevent

any changes to the boot code that could override the

choices made while setting up sector protection during

system initialization.

If the user attempts to program or erase a protected

sector, the device ignores the command and returns to

read mode. A program command to a protected sector

enables status polling for approximately 1 µs before

the device returns to read mode without having modi-

fied the contents of the protected sector. An erase

command to a protected sector enables status polling

for approximately 50 µs after which the device returns

to read mode without having erased the protected sec-

tor.

It is possible to have sectors that have been persis-

tently locked, and sectors that are left in the dynamic

state. The sectors in the dynamic state are all unpro-

tected. If there is a need to protect some of them, a

simple DYB Write command sequence is all that is

necessary. The DYB write command for the dynamic

sectors switch the DYBs to signify protected and un-

protected, respectively. If there is a need to change the

status of the persistently locked sectors, a few more

steps are required. First, the PPB Lock bit must be dis-

abled by either putting the device through a power-cy-

cle, or hardware reset. The PPBs can then be

changed to reflect the desired settings. Setting the

PPB lock bit once again will lock the PPBs, and the de-

vice operates normally again.

The programming of the DYB, PPB, and PPB lock for a

given sector can be verified by writing a

DYB/PPB/PPB lock verify command to the device.

Persistent Sector Protection Mode Locking Bit

Like the password mode locking bit, a Persistent Sec-

tor Protection mode locking bit exists to guarantee that

the device remain in software sector protection. Once

set, the Persistent Sector Protection locking bit pre-

vents programming of the password protection mode

locking bit. This guarantees that a hacker could not

place the device in password protection mode.

The best protection is achieved by executing the PPB

lock bit set command early in the boot code, and pro-

tect the boot code by holding WP#/ACC = V_IL.

Password Protection Mode

The Password Sector Protection Mode method allows

an even higher level of security than the Persistent

Sector Protection Mode. There are two main differ-

ences between the Persistent Sector Protection and

the Password Sector Protection Mode:

18

Am29PDL640G

December 13, 2005

D A T A S H E E T

■ When the device is first powered on, or comes out

The Password Mode Locking Bit, once set, prevents

reading the 64-bit password on the DQ bus and further

password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit

is programmed, the Persistent Sector Protection Lock-

ing Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

of a reset cycle, the PPB Lock bit set to the locked

state, rather than cleared to the unlocked state.

■ The only means to clear the PPB Lock bit is by writ-

ing a unique 64-bit Password to the device.

The Password Sector Protection method is otherwise

identical to the Persistent Sector Protection method.

64-bit Password

A 64-bit password is the only additional tool utilized in

this method.

The 64-bit Password is located in its own memory

space and is accessible through the use of the Pass-

word Program and Verify commands (see “Password

Verify Command”). The password function works in

conjunction with the Password Mode Locking Bit,

which when set, prevents the Password Verify com-

mand from reading the contents of the password on

the pins of the device.

The password is stored in a one-time programmable

(OTP) region of the flash memory. Once the Password

Mode Locking Bit is set, the password is permanently

set with no means to read, program, or erase it. The

password is used to clear the PPB Lock bit. The Pass-

word Unlock command must be written to the flash,

along with a password. The flash device internally

compares the given password with the pre-pro-

grammed password. If they match, the PPB Lock bit is

cleared, and the PPBs can be altered. If they do not

match, the flash device does nothing. There is a

built-in 2 µs delay for each “password check.” This

delay is intended to thwart any efforts to run a program

that tries all possible combinations in order to crack

the password.

Write Protect (WP#)

The Write Protect feature provides a hardware method

of protecting sectors 0, 1, 140, and 141 without using

V_ID. This function is provided by the WP# pin and over-

rides the previously discussed High Voltage Sector

Protection method.

If the system asserts V_ILon the WP#/ACC pin, the de-

vice disables program and erase functions in the two

outermost 4 Kword sectors on both ends of the flash

array independent of whether it was previously pro-

tected or unprotected.

Password and Password Mode Locking Bit

In order to select the Password sector protection

scheme, the customer must first program the pass-

word. The password may be correlated to the unique

Electronic Serial Number (ESN) of the particular flash

device. Each ESN is different for every flash device;

therefore each password should be different for every

flash device. While programming in the password re-

gion, the customer may perform Password Verify oper-

ations.

If the system asserts V_IHon the WP#/ACC pin, the de-

vice reverts to whether sectors 0, 1, 140, and 141

were last set to be protected or unprotected. That is,

sector protection or unprotection for these sectors de-

pends on whether they were last protected or unpro-

tected using the method described in High Voltage

Sector Protection.

Once the desired password is programmed in, the

customer must then set the Password Mode Locking

Bit. This operation achieves two objectives:

Note that the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

1. Permanently sets the device to operate using the

Password Protection Mode. It is not possible to re-

verse this function.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile

bit that reflects the state of the Password Mode Lock-

ing Bit after power-up reset. If the Password Mode

Lock Bit is also set after a hardware reset (RESET#

asserted) or a power-up reset, the ONLY means for

clearing the PPB Lock Bit in Password Protection

Mode is to issue the Password Unlock command. Suc-

cessful execution of the Password Unlock command

clears the PPB Lock Bit, allowing for sector PPBs

modifications. Asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit to a “1” when the

Password Mode Lock Bit is not set.

2. Disables all further commands to the password re-

gion. All program, and read operations are ignored.

Both of these objectives are important, and if not care-

fully considered, may lead to unrecoverable errors.

The user must be sure that the Password Protection

method is desired when setting the Password Mode

Locking Bit. More importantly, the user must be sure

that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations

are disabled, there is no means to verify what the

password is afterwards. If the password is lost after

setting the Password Mode Locking Bit, there will be

no way to clear the PPB Lock bit.

December 13, 2005

Am29PDL640G

19

D A T A S H E E T

If the Password Mode Locking Bit is not set, including

High Voltage Sector Protection

Persistent Protection Mode, the PPB Lock Bit is

cleared after power-up or hardware reset. The PPB

Lock Bit is set by issuing the PPB Lock Bit Set com-

mand. Once set the only means for clearing the PPB

Lock Bit is by issuing a hardware or power-up reset.

The Password Unlock command is ignored in Persis-

tent Protection Mode.

Sector protection and unprotection may also be imple-

mented using programming equipment. The proce-

dure requires high voltage (V_ID) to be placed on the

RESET# pin. Refer to Figure Note: for details on this

procedure. Note that for sector unprotect, all unpro-

tected sectors must first be protected prior to the first

sector write cycle.

20

Am29PDL640G

December 13, 2005

D A T A S H E E T

START

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

PLSCNT = 1

RESET# = V_ID

unprotected sectors

prior to issuing the

first sector

Wait 4 μs

unprotect address

No

First Write

Cycle = 60h?

First Write

Cycle = 60h?

Temporary Sector

Unprotect Mode

Temporary Sector

Unprotect Mode

Yes

Set up sector

address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6-A0 =

Yes

Set up first sector

address

0111010

Sector Unprotect:

Wait 100 µs

Write 60h to sector

address with

A6-A0 =

Verify Sector

Protect: Write 40h

to sector address

with A6-A0 =

1111010

Reset

PLSCNT = 1

Increment

PLSCNT

Wait 1.2 ms

0000010

Verify Sector

Unprotect: Write

40h to sector

address with

A6-A0 =

Read from

sector address

with A6-A0 =

0000010

Increment

PLSCNT

No

0000010

No

PLSCNT

= 25?

Read from

sector address

with A6-A0 =

0000010

Data = 01h?

Yes

No

Yes

Set up

next sector

address

Yes

Remove V_ID

from RESET#

No

PLSCNT

= 1000?

Protect another

sector?

Data = 00h?

Yes

No

Write reset

command

Yes

Remove V_ID

from RESET#

Remove V_ID

from RESET#

No

Last sector

verified?

Sector Protect

complete

Write reset

command

Yes

Write reset

command

Remove V_ID

from RESET#

Device failed

Sector Protect

complete

Sector Unprotect

complete

Write reset

command

Sector Protect

Algorithm

Device failed

Sector Unprotect

complete

Sector Unprotect

Algorithm

Note:These algorithms are valid only in Persistent Sector Protection Mode. They are not valid in Password Protection Mode.

Figure 1. In-System Sector Protection/

Sector Unprotection Algorithms

December 13, 2005

Am29PDL640G

21

D A T A S H E E T

AMD offers the device with the SecSi Sector either

Temporary Sector Unprotect

factory locked or customer lockable. The fac-

tory-locked version is always protected when shipped

from the factory, and has the SecSi (Secured Silicon)

Sector Indicator Bit permanently set to a “1.” The cus-

tomer-lockable version is shipped with the SecSi Sec-

tor unprotected, allowing customers to utilize the

sector in any manner they choose. The customer-lock-

able version has the SecSi (Secured Silicon) Sector

Indicator Bit permanently set to a “0.” Thus, the SecSi

Sector Indicator Bit prevents customer-lockable de-

vices from being used to replace devices that are fac-

tory locked.

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system. The

Sector Unprotect mode is activated by setting the RE-

SET# pin to V_ID. During this mode, formerly protected

sectors can be programmed or erased by selecting the

sector addresses. Once V_IDis removed from the RE-

SET# pin, all the previously protected sectors are

protected again. Figure 2 shows the algorithm, and

Figure 22 shows the timing diagrams, for this feature.

The system accesses the SecSi Sector through a

command sequence (see “Enter SecSi™ Sector/Exit

SecSi Sector Command Sequence”). After the system

has written the Enter SecSi Sector command se-

quence, it may read the SecSi Sector by using the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues

the Exit SecSi Sector command sequence, or until

power is removed from the device. On power-up, or

following a hardware reset, the device reverts to send-

ing commands to the normal address space. Note that

the ACC function and unlock bypass modes are not

available when the SecSi Sector is enabled.

START

RESET# = V_ID

(Note 1)

Perform Erase or

Program Operations

RESET# = V_IH

Factory Locked: SecSi Sector Programmed and

Protected At the Factory

Temporary Sector

Unprotect Completed

(Note 2)

In a factory locked device, the SecSi Sector is pro-

tected when the device is shipped from the factory.

The SecSi Sector cannot be modified in any way. The

device is preprogrammed with both a random number

and a secure ESN. The SecSi Sector is located at ad-

dresses 000000h–00007Fh in Persistent Protection

mode, and at addresses 000005h–00007Fh in Pass-

word Protection mode. The device is available prepro-

grammed with one of the following:

Notes:

1. All protected sectors unprotected (If WP#/ACC = V_IL,

sectors 0, 1, 140, 141 will remain protected).

2. All previously protected sectors are protected once

again.

■ A random, secure ESN only

■ Customer code through the ExpressFlash service

Figure 2. Temporary Sector Unprotect Operation

■ Both a random, secure ESN and customer code

through the ExpressFlash service.

SecSi™ (Secured Silicon) Sector

Flash Memory Region

Customers may opt to have their code programmed by

AMD through the AMD ExpressFlash service. AMD

programs the customer’s code, with or without the ran-

dom ESN. The devices are then shipped from AMD’s

factory with the SecSi Sector permanently locked.

Contact an AMD representative for details on using

AMD’s ExpressFlash service.

The SecSi (Secured Silicon) Sector feature provides a

Flash memory region that enables permanent part

identification through an Electronic Serial Number

(ESN). The SecSi Sector is up to 128 words in length,

and uses a SecSi Sector Indicator Bit (DQ7) to indi-

cate whether or not the SecSi Sector is locked when

shipped from the factory. This bit is permanently set at

the factory and cannot be changed, which prevents

cloning of a factory locked part. This ensures the secu-

rity of the ESN once the product is shipped to the field.

Customer Lockable: SecSi Sector NOT

Programmed or Protected At the Factory

If the security feature is not required, the SecSi Sector

can be treated as an additional Flash memory space.

The SecSi Sector can be read any number of times,

but can be programmed and locked only once. Note

22

Am29PDL640G

December 13, 2005

D A T A S H E E T

that the accelerated programming (ACC) and unlock

bypass functions are not available when programming

the SecSi Sector.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes. In addition, the following

hardware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during V_CC

power-up and power-down transitions, or from system

noise.

The SecSi Sector area can be protected using one of

the following procedures:

■ Write the three-cycle Enter SecSi Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure Note:,

except that RESET# may be at either V_IHor V_ID.

This allows in-system protection of the SecSi Sector

Region without raising any device pin to a high volt-

age. Note that this method is only applicable to the

SecSi Sector.

Low V_CCWrite Inhibit

When V_CCis less than V_LKO, the device does not ac-

cept any write cycles. This protects data during V_CC

power-up and power-down. The command register

and all internal program/erase circuits are disabled,

and the device resets to the read mode. Subsequent

writes are ignored until V_CCis greater than V_LKO. The

system must provide the proper signals to the control

pins to prevent unintentional writes when V_CCis

■ To verify the protect/unprotect status of the SecSi

Sector, follow the algorithm shown in Figure 3.

Once the SecSi Sector is locked and verified, the sys-

tem must write the Exit SecSi Sector Region com-

mand sequence to return to reading and writing the

remainder of the array.

greater than V_LKO

.

The SecSi Sector lock must be used with caution

since, once locked, there is no procedure available for

unlocking the SecSi Sector area and none of the bits

in the SecSi Sector memory space can be modified in

any way.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE#

or WE# do not initiate a write cycle.

Logical Inhibit

SecSi Sector Protection Bit

Write cycles are inhibited by holding any one of OE# =

V_IL, CE# = V_IHor WE# = V_IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

The SecSi Sector Protection Bit prevents program-

ming of the SecSi Sector memory area. Once set, the

SecSi Sector memory area contents are non-modifi-

able.

Power-Up Write Inhibit

If WE# = CE# = V_ILand OE# = V_IHduring power up,

the device does not accept commands on the rising

edge of WE#. The internal state machine is automati-

cally reset to the read mode on power-up.

START

If data = 00h,

RESET# =

SecSi Sector is

V_IHor V_ID

COMMON FLASH MEMORY INTERFACE

(CFI)

unprotected.

If data = 01h,

SecSi Sector is

protected.

Wait 1 μs

The Common Flash Interface (CFI) specification out-

lines device and host system software interrogation

handshake, which allows specific vendor-specified

software algorithms to be used for entire families of

devices. Software support can then be device-inde-

pendent, JEDEC ID-independent, and forward- and

backward-compatible for the specified flash device

families. Flash vendors can standardize their existing

interfaces for long-term compatibility.

Write 60h to

any address

Remove V_IHor V_ID

from RESET#

Write 40h to SecSi

Sector address

Write reset

with A6 = 0,

command

A1 = 1, A0 = 0

SecSi Sector

Read from SecSi

Protect Verify

This device enters the CFI Query mode when the sys-

tem writes the CFI Query command, 98h, to address

55h, any time the device is ready to read array data.

The system can read CFI information at the addresses

given in Tables 10–13. To terminate reading CFI data,

the system must write the reset command. The CFI

Query mode is not accessible when the device is exe-

Sector address

complete

with A6 = 0,

A1 = 1, A0 = 0

Figure 3. SecSi Sector Protect Verify

December 13, 2005

Am29PDL640G

23

D A T A S H E E T

cuting an Embedded Program or embedded Erase al-

For further information, please refer to the CFI Specifi-

cation and CFI Publication 100, available via the World

Wide Web at http://www.amd.com/flash/cfi. Alterna-

tively, contact an AMD representative for copies of

these documents.

gorithm.

The system can also write the CFI query command

when the device is in the autoselect mode. The device

enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 10–13. The

system must write the reset command to return the

device to reading array data.

24

Am29PDL640G

December 13, 2005

D A T A S H E E T

Table 10. CFI Query Identification String

Description

Addresses

Data

10h

11h

12h

0051h

0052h

0059h

Query Unique ASCII string “QRY”

13h

14h

0002h

0000h

Primary OEM Command Set

15h

16h

0040h

0000h

Address for Primary Extended Table

17h

18h

0000h

Alternate OEM Command Set (00h = none exists)

Address for Alternate OEM Extended Table (00h = none exists)

19h

1Ah

0000h

Table 11. System Interface String

Description

Addresses

Data

V

_CCMin. (write/erase)

1Bh

0027h

D7–D4: volt, D3–D0: 100 millivolt

V_CCMax. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch

0031h

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

0000h

0004h

0000h

0009h

0000h

0005h

0000h

0004h

0000h

V_PPMin. voltage (00h = no V_PPpin present)

V_PPMax. voltage (00h = no V_PPpin present)

Typical timeout per single byte/word write 2^Nµs

Typical timeout for Min. size buffer write 2^Nµs (00h = not supported)

Typical timeout per individual block erase 2^Nms

Typical timeout for full chip erase 2^Nms (00h = not supported)

Max. timeout for byte/word write 2^Ntimes typical

Max. timeout for buffer write 2^Ntimes typical

Max. timeout per individual block erase 2^Ntimes typical

Max. timeout for full chip erase 2^Ntimes typical (00h = not supported)

December 13, 2005

Am29PDL640G

25

D A T A S H E E T

Table 12. Device Geometry Definition

Addresses

Data

Description

27h

0017h

Device Size = 2^Nbyte

28h

29h

0001h

0000h

Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh

0000h

Max. number of byte in multi-byte write = 2^N

(00h = not supported)

2Ch

0003h

Number of Erase Block Regions within device

2Dh

2Eh

2Fh

30h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

007Dh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

35h

36h

37h

38h

0007h

0000h

0020h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

26

Am29PDL640G

December 13, 2005

D A T A S H E E T

Table 13. Primary Vendor-Specific Extended Query

Addresses

Data

Description

40h

41h

42h

0050h

0052h

0049h

Query-unique ASCII string “PRI”

43h

44h

0031h

0033h

Major version number, ASCII (reflects modifications to the silicon)

Minor version number, ASCII (reflects modifications to the CFI table)

Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not Required

45h

0004h

Silicon Revision Number (Bits 7-2)

Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

46h

47h

48h

49h

4Ah

4Bh

4Ch

0002h

0001h

0007h

0077h

0000h

0002h

Sector Protect

0 = Not Supported, X = Number of sectors in per group

Sector Temporary Unprotect

00 = Not Supported, 01 = Supported

Sector Protect/Unprotect scheme

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode

Simultaneous Operation

00 = Not Supported, X = Number of Sectors excluding Bank 1

Burst Mode Type

00 = Not Supported, 01 = Supported

Page Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

ACC (Acceleration) Supply Minimum

4Dh

4Eh

0085h

0095h

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

ACC (Acceleration) Supply Maximum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

Top/Bottom Boot Sector Flag

4Fh

0001h

00h = Uniform device, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both

Top and Bottom

Program Suspend

50h

57h

58h

59h

5Ah

5Bh

0001h

0004h

0017h

0030h

0017h

0 = Not supported, 1 = Supported

Bank Organization

00 = Data at 4Ah is zero, X = Number of Banks

Bank 1 Region Information

X = Number of Sectors in Bank 1

Bank 2 Region Information

X = Number of Sectors in Bank 2

Bank 3 Region Information

X = Number of Sectors in Bank 3

Bank 4 Region Information

X = Number of Sectors in Bank 4

December 13, 2005

Am29PDL640G

27

D A T A S H E E T

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 14 defines the valid register command

sequences. Writing incorrect address and data values

or writing them in the improper sequence may place

the device in an unknown state. A reset command is

then required to return the device to reading array

data.

erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure be-

gins, however, the device ignores reset commands

until the operation is complete.

The reset command may be written between the

sequence cycles in a program command sequence

before programming begins. This resets the bank to

which the system was writing to the read mode. If the

program command sequence is written to a bank that

is in the Erase Suspend mode, writing the reset

command returns that bank to the erase-sus-

pend-read mode. Once programming begins, however,

the device ignores reset commands until the operation

is complete.

All addresses are latched on the falling edge of WE#

or CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the AC Characteristics section for timing

diagrams.

Reading Array Data

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must be written to return to the read mode. If a bank

entered the autoselect mode while in the Erase Sus-

pend mode, writing the reset command returns that

bank to the erase-suspend-read mode.

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. Each bank is ready to read array data

after completing an Embedded Program or Embedded

Erase algorithm.

After the device accepts an Erase Suspend command,

the corresponding bank enters the erase-sus-

pend-read mode, after which the system can read

data from any non-erase-suspended sector within the

same bank. The system can read array data using the

standard read timing, except that if it reads at an ad-

dress within erase-suspended sectors, the device out-

puts status data. After completing a programming

operation in the Erase Suspend mode, the system

may once again read array data with the same excep-

tion. See the Erase Suspend/Erase Resume Com-

mands section for more information.

If DQ5 goes high during a program or erase operation,

writing the reset command returns the banks to the

read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and device codes,

and determine whether or not a sector is protected.

The autoselect command sequence may be written to

an address within a bank that is either in the read or

erase-suspend-read mode. The autoselect command

may not be written while the device is actively pro-

gramming or erasing in the other bank.

The system must issue the reset command to return a

bank to the read (or erase-suspend-read) mode if DQ5

goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the

next section, Reset Command, for more information.

Note that the ACC function and unlock bypass modes

are not available when the SecSi Sector is enabled.

The autoselect command sequence is initiated by first

writing two unlock cycles. This is followed by a third

write cycle that contains the bank address and the au-

toselect command. The bank then enters the autose-

lect mode. The system may read any number of

autoselect codes without reinitiating the command se-

quence.

See also Requirements for Reading Array Data in the

Device Bus Operations section for more information.

The Read-Only Operations table provides the read pa-

rameters, and Figure 12 shows the timing diagram.

Table 14 shows the address and data requirements.

To determine sector protection information, the system

must write to the appropriate bank address (BA) and

sector address (SA). Table 4 shows the address range

and bank number associated with each sector.

Reset Command

Writing the reset command resets the banks to the

read or erase-suspend-read mode. Address bits are

don’t cares for this command.

The system must write the reset command to return to

the read mode (or erase-suspend-read mode if the

bank was previously in Erase Suspend).

The reset command may be written between the se-

quence cycles in an erase command sequence before

28

Am29PDL640G

December 13, 2005

D A T A S H E E T

from “0” back to a “1.” Attempting to do so may

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence

cause that bank to set DQ5 = 1, or cause the DQ7 and

DQ6 status bits to indicate the operation was success-

ful. However, a succeeding read will show that the

data is still “0.” Only erase operations can convert a “0”

to a “1.”

The SecSi Sector region provides a secured data area

containing a random, eight word electronic serial num-

ber (ESN). The system can access the SecSi Sector

region by issuing the three-cycle Enter SecSi Sector

command sequence. The device continues to access

the SecSi Sector region until the system issues the

four-cycle Exit SecSi Sector command sequence. The

Exit SecSi Sector command sequence returns the de-

vice to normal operation. The SecSi Sector is not ac-

cessible when the device is executing an Embedded

Program or embedded Erase algorithm. Table 14

shows the address and data requirements for both

command sequences. See also “SecSi™ (Secured Sili-

con) Sector Flash Memory Region” for further informa-

tion. Note that the ACC function and unlock bypass

modes are not available when the SecSi Sector is en-

abled.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram data to a bank faster than using the standard

program command sequence. The unlock bypass

command sequence is initiated by first writing two un-

lock cycles. This is followed by a third write cycle con-

taining the unlock bypass command, 20h. That bank

then enters the unlock bypass mode. A two-cycle un-

lock bypass program command sequence is all that is

required to program in this mode. The first cycle in this

sequence contains the unlock bypass program com-

mand, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. Table 14 shows the requirements for the

command sequence.

Word Program Command Sequence

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically provides

internally generated program pulses and verifies the

programmed cell margin. Table 14 shows the address

and data requirements for the program command se-

quence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the bank

address and the data 90h. The second cycle need

only contain the data 00h. The bank then returns to

the read mode.

When the Embedded Program algorithm is complete,

that bank then returns to the read mode and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. Refer to the Write Operation

Status section for information on these status bits.

The device offers accelerated program operations

through the WP#/ACC pin. When the system asserts

V

_HHon the WP#/ACC pin, the device automatically en-

ters the Unlock Bypass mode. The system may then

write the two-cycle Unlock Bypass program command

sequence. The device uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that

the WP#/ACC pin must not be at V_HHany operation

other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not

be left floating or unconnected; inconsistent behavior

of the device may result.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program

operation. The program command sequence should

be reinitiated once that bank has returned to the read

mode, to ensure data integrity. Note that the SecSi

Sector, autoselect, and CFI functions are unavailable

when a program operation is in progress.

Figure 4 illustrates the algorithm for the program oper-

ation. Refer to the Erase and Program Operations

table in the AC Characteristics section for parameters,

and Figure 15 for timing diagrams.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

December 13, 2005

Am29PDL640G

29

D A T A S H E E T

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that oc-

curs, the chip erase command sequence should be

reinitiated once that bank has returned to reading

array data, to ensure data integrity.

START

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 17 section for timing diagrams.

Write Program

Command Sequence

Data Poll

from System

Sector Erase Command Sequence

Embedded

Program

algorithm

in progress

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two ad-

ditional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command.Table 14 shows the ad-

dress and data requirements for the sector erase com-

mand sequence.

Verify Data?

Yes

No

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

Increment Address

Last Address?

Yes

Programming

Completed

After the command sequence is written, a sector erase

time-out of 80 µs occurs. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 80

µs, otherwise erasure may begin. Any sector erase ad-

dress and command following the exceeded time-out

may or may not be accepted. It is recommended that

processor interrupts be disabled during this time to en-

sure all commands are accepted. The interrupts can

be re-enabled after the last Sector Erase command is

written. Any command other than Sector Erase or

Erase Suspend during the time-out period resets

that bank to the read mode. The system must rewrite

the command sequence and any additional addresses

and commands. Note that the SecSi Sector, autose-

lect, and CFI functions are unavailable when an erase

operation is in progress.

Note: See Table 14 for program command sequence.

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 14

shows the address and data requirements for the chip

erase command sequence.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7, DQ6, DQ2,

or RY/BY#. Refer to the Write Operation Status sec-

tion for information on these status bits. Note that the

SecSi Sector, autoselect, and CFI functions are un-

available when an erase operation is in progress.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded

Erase operation is in progress, the system can read

30

Am29PDL640G

December 13, 2005

D A T A S H E E T

data from the non-erasing bank. The system can de-

In the erase-suspend-read mode, the system can also

issue the autoselect command sequence. The device

allows reading autoselect codes even at addresses

within erasing sectors, since the codes are not stored

in the memory array. When the device exits the au-

toselect mode, the device reverts to the Erase Sus-

pend mode, and is ready for another valid operation.

Refer to the Autoselect Mode and Autoselect Com-

mand Sequence sections for details.

termine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer

to the Write Operation Status section for information

on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

To resume the sector erase operation, the system

must write the Erase Resume command (address bits

are don’t care). The bank address of the erase-sus-

pended bank is required when writing this command.

Further writes of the Resume command are ignored.

Another Erase Suspend command can be written after

the chip has resumed erasing.

Figure 5 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations ta-

bles in the AC Characteristics section for parameters,

and Figure 17 section for timing diagrams.

Erase Suspend/Erase Resume

Commands

START

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the 80 µs time-out

period during the sector erase command sequence.

The Erase Suspend command is ignored if written dur-

ing the chip erase operation or Embedded Program

algorithm.

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Embedded

When the Erase Suspend command is written during

the sector erase operation, the device requires a max-

imum of 20 µs to suspend the erase operation. How-

ever, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation. Addresses are “don’t-cares” when

writing the Erase suspend command.

Erase

algorithm

in progress

No

Data = FFh?

Yes

Erasure Completed

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The sys-

tem can read data from or program data to any sector

not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at

any address within erase-suspended sectors pro-

duces status information on DQ7–DQ0. The system

can use DQ7, or DQ6 and DQ2 together, to determine

if a sector is actively erasing or is erase-suspended.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Notes:

1. See Table 14 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

Figure 5. Erase Operation

Password Program Command

After an erase-suspended program operation is com-

plete, the bank returns to the erase-suspend-read

mode. The system can determine the status of the

program operation using the DQ7 or DQ6 status bits,

just as in the standard Word Program operation.

Refer to the Write Operation Status section for more

information.

The Password Program Command permits program-

ming the password that is used as part of the hard-

ware protection scheme. The actual password is

64-bits long. Four Password Program commands are

required to program the password. The system must

enter the unlock cycle, password program command

(38h) and the program address/data for each portion

December 13, 2005

Am29PDL640G

31

D A T A S H E E T

of the password when programming. There are no pro-

Persistent Sector Protection Mode

Locking Bit Program Command

visions for entering the 2-cycle unlock cycle, the pass-

word program command, and all the password data.

There is no special addressing order required for pro-

gramming the password. Also, when the password is

undergoing programming, Simultaneous Operation is

disabled. Read operations to any memory location will

return the programming status. Once programming is

complete, the user must issue a Read/Reset com-

mand to return the device to normal operation. Once

the Password is written and verified, the Password

Mode Locking Bit must be set in order to prevent verifi-

cation. The Password Program Command is only ca-

pable of programming “0”s. Programming a “1” after a

cell is programmed as a “0” results in a time-out by the

Embedded Program Algorithm™ with the cell remain-

ing as a “0”. The password is all ones when shipped

from the factory. All 64-bit password combinations are

valid as a password.

The Persistent Sector Protection Mode Locking Bit

Program Command programs the Persistent Sector

Protection Mode Locking Bit, which prevents the Pass-

word Mode Locking Bit from ever being programmed.

If the Persistent Sector Protection Mode Locking Bit is

verified as programmed without margin, the Persistent

Sector Protection Mode Locking Bit Program Com-

mand should be reissued to improve program margin.

By disabling the program circuitry of the Password

Mode Locking Bit, the device is forced to remain in the

Persistent Sector Protection mode of operation, once

this bit is set. Exiting the Persistent Protection Mode

Locking Bit Program command is accomplished by

writing the Read/Reset command.

SecSi Sector Protection Bit Program

Command

Password Verify Command

The SecSi Sector Protection Bit Program Command

programs the SecSi Sector Protection Bit, which pre-

vents the SecSi sector memory from being cleared. If

the SecSi Sector Protection Bit is verified as pro-

grammed without margin, the SecSi Sector Protection

Bit Program Command should be reissued to improve

program margin. Exiting the V_CC-level SecSi Sector

Protection Bit Program Command is accomplished by

writing the Read/Reset command.

The Password Verify Command is used to verify the

Password. The Password is verifiable only when the

Password Mode Locking Bit is not programmed. If the

Password Mode Locking Bit is programmed and the

user attempts to verify the Password, the device will al-

ways drive all F’s onto the DQ data bus.

The Password Verify command is permitted if the

SecSi sector is enabled. Also, the device will not oper-

ate in Simultaneous Operation when the Password

Verify command is executed. Only the password is re-

turned regardless of the bank address. The lower two

address bits (A1-A0) are valid during the Password

Verify. Writing the Read/Reset command returns the

device back to normal operation.

PPB Lock Bit Set Command

The PPB Lock Bit Set command is used to set the

PPB Lock bit if it is cleared either at reset or if the

Password Unlock command was successfully exe-

cuted. There is no PPB Lock Bit Clear command.

Once the PPB Lock Bit is set, it cannot be cleared un-

less the device is taken through a power-on clear or

the Password Unlock command is executed. Upon set-

ting the PPB Lock Bit, the PPBs are latched into the

DYBs. If the Password Mode Locking Bit is set, the

PPB Lock Bit status is reflected as set, even after a

power-on reset cycle. Exiting the PPB Lock Bit Set

command is accomplished by writing the Read/Reset

command (only in the Persistent Protection Mode).

Password Protection Mode Locking Bit

Program Command

The Password Protection Mode Locking Bit Program

Command programs the Password Protection Mode

Locking Bit, which prevents further verifies or updates

to the Password. Once programmed, the Password

Protection Mode Locking Bit cannot be erased! If the

Password Protection Mode Locking Bit is verified as

program without margin, the Password Protection

Mode Locking Bit Program command can be executed

to improve the program margin. Once the Password

Protection Mode Locking Bit is programmed, the Per-

sistent Sector Protection Locking Bit program circuitry

is disabled, thereby forcing the device to remain in the

Password Protection mode. Exiting the Mode Locking

Bit Program command is accomplished by writing the

Read/Reset command.

DYB Write Command

The DYB Write command is used to set or clear a DYB

for a given sector. The high order address bits

(A21–A12) are issued at the same time as the code

01h or 00h on DQ7-DQ0. All other DQ data bus pins

are ignored during the data write cycle. The DYBs are

modifiable at any time, regardless of the state of the

PPB or PPB Lock Bit. The DYBs are cleared at

power-up or hardware reset.Exiting the DYB Write

command is accomplished by writing the Read/Reset

command.

32

Am29PDL640G

December 13, 2005

D A T A S H E E T

erasing the PPBs, two additional cycles are needed to

Password Unlock Command

determine whether the PPB has been erased with

margin. If the PPBs has been erased without margin,

the erase command should be reissued to improve the

program margin.

The Password Unlock command is used to clear the

PPB Lock Bit so that the PPBs can be unlocked for

modification, thereby allowing the PPBs to become ac-

cessible for modification. The exact password must be

entered in order for the unlocking function to occur.

This command cannot be issued any faster than 2 µs

at a time to prevent a hacker from running through all

64-bit combinations in an attempt to correctly match a

password. If the command is issued before the 2 µs

execution window for each portion of the unlock, the

command will be ignored.

It is the responsibility of the user to preprogram all

PPBs prior to issuing the All PPB Erase command. If

the user attempts to erase a cleared PPB, over-era-

sure may occur making it difficult to program the PPB

at a later time. Also note that the total number of PPB

program/erase cycles is limited to 100 cycles. Cycling

the PPBs beyond 100 cycles is not guaranteed.

Once the Password Unlock command is entered, the

RY/BY# indicates that the device is busy. Approxi-

mately 2 µs is required for each portion of the unlock.

Once the first portion of the password unlock com-

pletes (RY/BY# is not low or DQ6 does not toggle

when read), the Password Unlock command and next

part of the password are written. The system must

thus monitor RY/BY# or the status bits to confirm

when to write the next portion of the password.

DYB Write Command

The DYB Write command is used for setting the DYB,

which is a volatile bit that is cleared at reset. There is

one DYB per sector. If the PPB is set, the sector is pro-

tected regardless of the value of the DYB. If the PPB is

cleared, setting the DYB to a 1 protects the sector from

programs or erases. Since this is a volatile bit, remov-

ing power or resetting the device will clear the DYBs.

The bank address is latched when the command is

written.

Note that immediately following successful unlock,

write the SecSi Sector exit command before attempt-

ing to verify, program, or erase the PPBs.

PPB Lock Bit Set Command

The PPB Lock Bit set command is used for setting the

DYB, which is a volatile bit that is cleared at reset.

There is one DYB per sector. If the PPB is set, the sec-

tor is protected regardless of the value of the DYB. If

the PPB is cleared, setting the DYB to a 1 protects the

sector from programs or erases. Since this is a volatile

bit, removing power or resetting the device will clear

the DYBs. The bank address is latched when the com-

mand is written.

PPB Program Command

The PPB Program command is used to program, or

set, a given PPB. Each PPB is individually pro-

grammed (but is bulk erased with the other PPBs).

The specific sector address (A21–A12) are written at

the same time as the program command 60h with A6

= 0. If the PPB Lock Bit is set and the corresponding

PPB is set for the sector, the PPB Program command

will not execute and the command will time-out without

programming the PPB.

PPB Status Command

After programming a PPB, two additional cycles are

needed to determine whether the PPB has been pro-

grammed with margin. If the PPB has been pro-

grammed without margin, the program command

should be reissued to improve the program margin.

Also note that the total number of PPB program/erase

cycles is limited to 100 cycles. Cycling the PPBs be-

yond 100 cycles is not guaranteed.

The programming of the PPB for a given sector can be

verified by writing a PPB status verify command to the

device.

PPB Lock Bit Status Command

The programming of the PPB Lock Bit for a given sec-

tor can be verified by writing a PPB Lock Bit status ver-

ify command to the device.

The PPB Program command does not follow the Em-

bedded Program algorithm.

Note that immediately following the PPB Lock Status

Command write the SecSi Sector Exit command be-

fore attempting to verify, program, or erase the PPBs.

All PPB Erase Command

The All PPB Erase command is used to erase all

PPBs in bulk. There is no means for individually eras-

ing a specific PPB. Unlike the PPB program, no spe-

cific sector address is required. However, when the

PPB erase command is written all Sector PPBs are

erased in parallel. If the PPB Lock Bit is set the ALL

PPB Erase command will not execute and the com-

mand will time-out without erasing the PPBs. After

Sector Protection Status Command

The programming of either the PPB or DYB for a given

sector or sector group can be verified by writing a Sec-

tor Protection Status command to the device.

Note that there is no single command to independently

verify the programming of a DYB for a given sector

group.

December 13, 2005

Am29PDL640G

33

D A T A S H E E T

Command Definitions Tables

Table 14. Memory Array Command Definitions

Bus Cycles (Notes 1–4)

Command (Notes)

Addr Data Addr Data

RA RD

XXX F0

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read (5)

Reset (6)

1

4

6

Manufacturer ID

555

AA 2AA

55 (BA) 555 90 (BA)X00

55 (BA) 555 90 (BA)X01

01

7E

Device ID (10)

AA 2AA

(BA)X0E 15 (BA)X0F

01

Autoselect

(Note 7)

SecSi Sector Factory

Protect (8)

(see

note 8)

4

555

AA 2AA

55 (BA) 555 90

X03

Sector Group Protect

Verify (9)

XX00/

XX01

AA 2AA

55 (BA) 555 90 (SA)X02

Program

4

6

1

2

3

2

1

2

555

BA

55

AA 2AA

B0

55

555

A0

80

PA

PD

AA

Chip Erase

Sector Erase

555

2AA

55

555

SA

10

30

Program/Erase Suspend (11)

Program/Erase Resume (12)

CFI Query (13)

30

98

Accelerated Program (14)

Unlock Bypass Entry (15)

Unlock Bypass Program (15)

Unlock Bypass Erase (15)

Unlock Bypass CFI (13, 15)

Unlock Bypass Reset (15)

XX

555

XX

A0

PA

PD

55

AA 2AA

555

20

A0

80

98

90

PA

PD

10

XX

00

Legend:

BA = Address of bank switching to autoselect mode, bypass mode, or

erase operation. Determined by A21:A19, see Tables 4 and 5 for more

detail.

PA = Program Address (A21:A0). Addresses latch on falling edge of

WE# or CE# pulse, whichever happens later.

RA = Read Address (A21:A0).

RD = Read Data (DQ15:DQ0) from location RA.

SA = Sector Address (A21:A12) for verifying (in autoselect mode) or

erasing.

WD = Write Data. See “Configuration Register” definition for specific

write data. Data latched on rising edge of WE#.

X = Don’t care

PD = Program Data (DQ15:DQ0) written to location PA. Data latches

on rising edge of WE# or CE# pulse, whichever happens first.

Notes:

1. See Table 1 for description of bus operations.

8. The data is 80h for factory locked and 00h for not factory locked.

2. All values are in hexadecimal.

9. The data is 00h for an unprotected sector group and 01h for a

protected sector group.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

10. Device ID must be read across cycles 4, 5, and 6.

4. During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

11. System may read and program in non-erasing sectors, or enter

autoselect mode, when in Program/Erase Suspend mode.

Program/Erase Suspend command is valid only during a sector

erase operation, and requires bank address.

5. No unlock or command cycles required when bank is reading

array data.

12. Program/Erase Resume command is valid only during Erase

Suspend mode, and requires bank address.

6. The Reset command is required to return to reading array (or to

erase-suspend-read mode if previously in Erase Suspend) when

bank is in autoselect mode, or if DQ5 goes high (while bank is

providing status information).

13. Command is valid when device is ready to read array data or

when device is in autoselect mode.

14. WP#/ACC must be at V_IDduring the entire operation of command.

15. Unlock Bypass Entry command is required prior to any Unlock

Bypass operation. Unlock Bypass Reset command is required to

return to the reading array.

7. Fourth cycle of autoselect command sequence is a read cycle.

System must provide bank address to obtain manufacturer ID or

device ID information. See Autoselect Command Sequence

section for more information.

34

Am29PDL640G

December 13, 2005

D A T A S H E E T

Table 15. Sector Protection Command Definitions

Bus Cycles (Notes 1-4)

Command (Notes)

Addr Data Addr Data Addr Data

Addr

Data

Addr

Data

Addr Data

Reset

1

3

4

6

4

6

3

4

6

4

6

4

XXX F0

SecSi Sector Entry

555

AA 2AA

55

555

88

90

60

38

SecSi Sector Exit

XX

OW

00

68

SecSi Protection Bit Program (5, 6)

SecSi Protection Bit Status

Password Program (5, 7, 8)

Password Verify (8, 9)

Password Unlock (7, 10, 11, 17)

PPB Program (5, 6, 12)

All PPB Erase (5, 13, 14)

PPB Lock Bit Set

OW

48

OW

RD(0)

OW

RD(0)

PD[0-3]

XX[0-3]

C8 PWA[0-3] PWD[0-3]

28 PWA[0-3] PWD[0-3]

60

78

58

48

58

60

(SA)WP

EP

68

60

(SA)WP

(SA)EP

48

40

(SA)WP RD(0)

PPB Lock Bit Status (15, 18)

DYB Write (7)

SA

PL

SL

RD(1)

X1

DYB Erase (7)

X0

DYB Status

RD(0)

68

PPMLB Program (5, 6, 12)

PPMLB Status (5)

PL

SL

48

PL

SL

RD(0)

68

SPMLB Program (5, 6, 12)

SPMLB Status (5)

RD(0)

Legend:

DYB = Dynamic Protection Bit

OW = Address (A6:A0) is (0011010)

PD[3:0] = Password Data (1 of 4 portions)

PPB = Persistent Protection Bit

PWA = Password Address. A1:A0 selects portion of password.

PWD = Password Data being verified.

RD(1) = Read Data DQ1 for PPB Lock status.

SA = Sector Address where security command applies. Address bits

A21:A12 uniquely select any sector.

SL = Persistent Protection Mode Lock Address (A5:A0) is (010010)

WP = PPB Address (A6:A0) is (0111010) (Note 16)

EP = PPB Erase Address (A6:A0) is (1111010) (Note 16)

X = Don’t care

PPMLB = Password Protection Mode Locking Bit

SPMLB = Persistent Protection Mode Locking Bit

PL = Password Protection Mode Lock Address (A5:A0) is (001010)

RD(0) = Read Data DQ0 for protection indicator bit.

1. See Table 1 for description of bus operations.

2. All values are in hexadecimal.

11. A 2 µs timeout is required between any two portions of password.

12. A 100 µs timeout is required between cycles 4 and 5.

13. A 1.2 ms timeout is required between cycles 4 and 5.

3. Shaded cells in table denote read cycles. All other cycles are

write operations.

14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been

fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command

must be issued and verified again. Before issuing erase

command, all PPBs should be programmed to prevent PPB

overerasure.

4. During unlock and command cycles, when lower address bits are

555 or 2AAh as shown in table, address bits higher than A11

(except where BA is required) and data bits higher than DQ7 are

don’t cares.

5. The reset command returns device to reading array.

15. DQ1 = 1 if PPB locked, 0 if unlocked.

6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6

validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0

in cycle 6, program command must be issued and verified again.

16. For all other parts that use the Persistent Protection Bit (excluding

PDL128G), the WP and EP addresses are 00000010.

17. Immediately following successful unlock, write the SecSi Sector

Exit command before attempting to verify, program, or erase the

PPBs.

7. Data is latched on the rising edge of WE#.

8. Entire command sequence must be entered for each portion of

password.

18. Immediately following the PPB Lock Status command write the

SecSi Sector Exit command before attempting to verify, program,

or erase the PPBs.

9. Command sequence returns FFh if PPMLB is set.

10. The password is written over four consecutive cycles, at

addresses 0-3.

December 13, 2005

Am29PDL640G

35

D A T A S H E E T

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 16 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method for

determining whether a program or erase operation is com-

plete or in progress. The device also provides a hard-

ware-based output signal, RY/BY#, to determine whether

an Embedded Program or Erase operation is in progress or

has been completed.

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ15–DQ0 may be still

invalid. Valid data on DQ15–DQ0 will appear on suc-

cessive read cycles.

Table 16 shows the outputs for Data# Polling on DQ7.

Figure 6 shows the Data# Polling algorithm. Figure 19

in the AC Characteristics section shows the Data#

Polling timing diagram.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Program or Erase algorithm is in

progress or completed, or whether a bank is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the final

WE# pulse in the command sequence.

START

Read DQ7–DQ0

Addr = VA

During the Embedded Program algorithm, the device out-

puts on DQ7 the complement of the datum programmed to

DQ7. This DQ7 status also applies to programming during

Erase Suspend. When the Embedded Program algorithm is

complete, the device outputs the datum programmed to

DQ7. The system must provide the program address to

read valid status information on DQ7. If a program address

falls within a protected sector, Data# Polling on DQ7 is ac-

tive for approximately 1 µs, then that bank returns to the

read mode.

Yes

DQ7 = Data?

No

DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7.

Yes

Read DQ7–DQ0

Addr = VA

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data# Poll-

ing on DQ7 is active for approximately 100 µs, then the

bank returns to the read mode. If not all selected sec-

tors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected. However, if the sys-

tem reads DQ7 at an address within a protected

sector, the status may not be valid.

Yes

DQ7 = Data?

No

PASS

FAIL

Notes:

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ15–DQ0 on the following read cycles. Just prior to

the completion of an Embedded Program or Erase op-

eration, DQ7 may change asynchronously with

DQ15–DQ0 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a

valid address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 6. Data# Polling Algorithm

36

Am29PDL640G

December 13, 2005

D A T A S H E E T

DQ6 also toggles during the erase-suspend-program

RY/BY#: Ready/Busy#

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The RY/BY# is a dedicated, open-drain output pin

which indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open-drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

Table 16 shows the outputs for Toggle Bit I on DQ6.

Figure 7 shows the toggle bit algorithm. Figure 20 in

the “AC Characteristics” section shows the toggle bit

timing diagrams. Figure 21 shows the differences be-

tween DQ2 and DQ6 in graphical form. See also the

subsection on DQ2: Toggle Bit II.

pull-up resistor to V_CC

.

If the output is low (Busy), the device is actively eras-

ing or programming. (This includes programming in

the Erase Suspend mode.) If the output is high

(Ready), the device is in the read mode, the standby

mode, or one of the banks is in the erase-sus-

pend-read mode.

START

Read Byte

(DQ7–DQ0)

Address =VA

Table 16 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or com-

plete, or whether the device has entered the Erase

Suspend mode. Toggle Bit I may be read at any ad-

dress, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

Read Byte

(DQ7–DQ0)

Address =VA

No

Toggle Bit

= Toggle?

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. The system may use either OE# or

CE# to control the read cycles. When the operation is

complete, DQ6 stops toggling.

Yes

No

DQ5 = 1?

Yes

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the

Embedded Erase algorithm erases the unprotected

sectors, and ignores the selected sectors that are pro-

tected.

Read Byte Twice

(DQ7–DQ0)

Address = VA

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase Sus-

pend mode, DQ6 stops toggling. However, the system

must also use DQ2 to determine which sectors are

erasing or erase-suspended. Alternatively, the system

can use DQ7 (see the subsection on DQ7: Data# Poll-

ing).

Toggle Bit

= Toggle?

No

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

If a program address falls within a protected sector,

DQ6 toggles for approximately 1 µs after the program

command sequence is written, then returns to reading

array data.

Figure 7. Toggle Bit Algorithm

December 13, 2005

Am29PDL640G

37

D A T A S H E E T

the toggle bit and DQ5 through successive read cy-

DQ2: Toggle Bit II

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 7).

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ5: Exceeded Timing Limits

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# to con-

trol the read cycles.) But DQ2 cannot distinguish

whether the sector is actively erasing or is erase-sus-

pended. DQ6, by comparison, indicates whether the

device is actively erasing, or is in Erase Suspend, but

cannot distinguish which sectors are selected for era-

sure. Thus, both status bits are required for sector and

mode information. Refer to Table 16 to compare out-

puts for DQ2 and DQ6.

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit

has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if a bank was previ-

ously in the erase-suspend-program mode).

Figure 7 shows the toggle bit algorithm in flowchart

form, and the section “DQ2: Toggle Bit II” explains the

algorithm. See also the DQ6: Toggle Bit I subsection.

Figure 20 shows the toggle bit timing diagram. Figure

21 shows the differences between DQ2 and DQ6 in

graphical form.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure has begun. (The sector erase timer does not

apply to the chip erase command.) If additional

sectors are selected for erasure, the entire time-out

also applies after each additional sector erase com-

mand. When the time-out period is complete, DQ3

switches from a “0” to a “1.” If the time between addi-

tional sector erase commands from the system can be

assumed to be less than 50 µs, the system need not

monitor DQ3. See also the Sector Erase Command

Sequence section.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 7 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ15–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically,

the system would note and store the value of the tog-

gle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ15–DQ0 on the fol-

lowing read cycle.

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device will accept additional sector erase commands.

To ensure the command has been accepted, the sys-

tem software should check the status of DQ3 prior to

and following each subsequent sector erase com-

mand. If DQ3 is high on the second status check, the

last command might not have been accepted.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

Table 16 shows the status of DQ3 relative to the other

status bits.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

38

Am29PDL640G

December 13, 2005

D A T A S H E E T

Table 16. Write Operation Status

DQ7

DQ5

DQ2

Status

(Note 2)

DQ6

(Note 1)

DQ3

N/A

1

(Note 2)

RY/BY#

Embedded Program Algorithm

Embedded Erase Algorithm

Erase

Erase-Suspend-

Read

DQ7#

0

Toggle

0

No toggle

Toggle

0

Standard

Mode

1

No toggle

0

N/A

Toggle

1

Suspended Sector

Erase

Suspend

Mode

Non-Erase

Suspended Sector

Data

0

Data

N/A

Data

N/A

1

0

Erase-Suspend-Program

DQ7#

Toggle

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

December 13, 2005

Am29PDL640G

39

D A T A S H E E T

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

20 ns

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –65°C to +125°C

+0.8 V

Voltage with Respect to Ground

–0.5 V

–2.0 V

V

_CC(Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V

20 ns

WP#/ACC (Note 2) . . . . . . . . . . .–0.5 V to +10.5 V

All other pins (Note 1). . . . . . –0.5 V to V_CC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Figure 8. Maximum Negative

Overshoot Waveform

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V.

During voltage transitions, input or I/O pins may

overshoot V_SSto –2.0 V for periods of up to 20 ns.

Maximum DC voltage on input or I/O pins is V_CC+0.5 V.

See Figure 8. During voltage transitions, input or I/O pins

may overshoot to V_CC+2.0 V for periods up to 20 ns. See

Figure 9.

20 ns

V_CC

+2.0 V

V_CC

+0.5 V

2. Minimum DC input voltage on pins A9, OE#, RESET#,

and WP#/ACC is –0.5 V. During voltage transitions, A9,

OE#, WP#/ACC, and RESET# may overshoot V_SSto

–2.0 V for periods of up to 20 ns. See Figure 8. Maximum

DC input voltage on pin A9, OE#, and RESET# is +12.5

V which may overshoot to +14.0 V for periods up to 20

ns. Maximum DC input voltage on WP#/ACC is +9.5 V

which may overshoot to +12.0 V for periods up to 20 ns.

2.0 V

20 ns

Figure 9. Maximum Positive

Overshoot Waveform

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditions for extended periods may affect device reliability.

Supply Voltages

OPERATING RANGES

V_CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7–3.1 V

Industrial (I) Devices

V

_IO(see Note) . . . . . . . . . . . 1.65–1.95 V or 2.7–3.1 V

Ambient Temperature (T_A) . . . . . . . . . –40°C to +85°C

Note: For all AC and DC specifications, V_IO= V_CC; contact

AMD for other V_IOoptions.

Operating ranges define those limits between which the

functionality of the device is guaranteed.

40

Am29PDL640G

December 13, 2005

D A T A S H E E T

DC CHARACTERISTICS

CMOS Compatible

Parameter

Parameter Description

Test Conditions

Min

Typ

Max

Unit

Symbol

V

_IN= V_SSto V_CC

_CC= V_{CC max}

,

I_LI

Input Load Current

±1.0

35

µA

I_LIT

I_LO

A9, OE#, RESET# Input Load Current

Output Leakage Current

V_CC= V_{CC max}; V_ID= 12.5 V

_OUT= V_SSto V_CC, OE# = V_IH

V

±1.0

V_CC= V_{CC max}

5 MHz

10

25

15

20

45

30

CE# = V_IL, OE# = V_IH, V_CC

= V_{CC max}

I_CC1

V_CCActive Read Current (Notes 1, 2)

mA

10 MHz

I_CC2

I_CC3

I_CC4

V_CCActive Write Current (Notes 2, 3)

V_CCStandby Current (Note 2)

V_CCReset Current (Note 2)

CE# = V_IL, OE# = V_IH, WE# = V_IL

mA

µA

CE#, RESET#, WP#/ACC = V_IO± 0.3 V

RESET# = V_SS± 0.3 V

1

5

V

_IH= V_IO± 0.3 V;

_IL= V_SS± 0.3 V

I_CC5

I_CC6

I_CC7

I_CC8

Automatic Sleep Mode (Notes 2, 4)

1

5

µA

mA

V_CCActive Read-While-Program Current

(Notes 1, 2)

CE# = V_IL, OE# = V_IH

Word

21

17

45

35

V_CCActive Read-While-Erase Current

(Notes 1, 2)

V_CCActive Program-While-Erase-

Suspended Current (Notes 2, 5)

CE# = V_IL, OE# = V_IH

V_IO= 1.65–1.95 V

–0.4

0.4

0.8

V

V_IL

V_IH

Input Low Voltage

–0.5

V

_IO= 2.7–3.1 V

V_IO= 1.65–1.95 V

_IO= 2.7–3.1 V

V_CC= 3.0 V 10ꢀ

V

_IO–0.4

V_IO+0.4

V_CC+0.3

Input High Voltage

V

2

V

V_HH

V_ID

Voltage for ACC Program Acceleration

8.5

9.5

Voltage for Autoselect and Temporary

Sector Unprotect

V

_CC= 3.0 V ± 10ꢀ

11.5

12.5

V

I_OL= 100 µA, V_CC= V_{CC min}, V_IO= 1.65–1.95 V

0.1

0.4

V

V_OL

Output Low Voltage

I

_OL= 4.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.1 V

_OH= –100 µA, V_CC= V_{CC min}

_IO= 1.65–1.95 V

I_OH= –2.0 mA, V_CC= V_{CC min}, V_IO= 2.7–3.1 V

I

,

V

_IO–0.1

V

V_OH

Output High Voltage

2.4

2.3

V

V_LKO

Low V_CCLock-Out Voltage (Note 5)

2.5

Notes:

1. The I_CCcurrent listed is typically less than 2 mA/MHz, with OE# at

V_IH

2. Maximum I_CCspecifications are tested with V_CC= V_CCmax

4. Automatic sleep mode enables the low power mode when

.

addresses remain stable for t_ACC+ 30 ns. Typical sleep mode

current is 200 nA.

.

5. Not 100% tested.

3. I_CCactive while Embedded Erase or Embedded Program is in

progress.

December 13, 2005

Am29PDL640G

41

D A T A S H E E T

TEST CONDITIONS

Table 17. Test Specifications

3.0 V

Test Condition

Output Load

63, 98

73, 83

Unit

1 TTL gate

2.7 kΩ

Device

Under

Test

Output Load Capacitance, C_L

(including jig capacitance)

30

70

pF

Input Rise and Fall Times

Input Pulse Levels

5

0.0–3.0

ns

V

C

L

6.2 kΩ

Input timing measurement

reference levels

1.5

V

Output timing measurement

reference levels

Note: Diodes are IN3064 or equivalent

Figure 10. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

3.0 V

0.0 V

1.5 V

Input

Measurement Level

Output

Figure 11. Input Waveforms and Measurement Levels

42

Am29PDL640G

December 13, 2005

D A T A S H E E T

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

JEDEC Std. Description

Test Setup

63

73

70

83

98

90

45

Unit

ns

t_AVAV

t_AVQV

t_ELQV

t_RCRead Cycle Time (Note 1)

Min

CE#, OE# = V_ILMax

65

85

30

t_ACCAddress to Output Delay

ns

t_CEChip Enable to Output Delay

t_PACCPage Access Time

OE# = V_IL

Max

ns

25

ns

t_GLQV

t_EHQZ

t_GHQZ

t_OEOutput Enable to Output Delay

t_DFChip Enable to Output High Z (Notes 1, 3)

t_DFOutput Enable to Output High Z (Notes 1, 3)

ns

Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First

t_AXQX

t_OH

Min

4

5

ns

Read

0

Output Enable Hold

t_OEH

Toggle and

Data# Polling

Time (Note 1)

10

Notes:

1. Not 100% tested.

2. See Figure 10 and Table 17 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of V_CC/2. The time from OE# high to

the data bus driven to V_CC/2 is taken as t_DF.

.

t_RC

Addresses Stable

t_ACC

Addresses

CE#f

t_RH

t_DF

t_OE

OE#

t_OEH

WE#

Data

t_CE

t_OH

HIGH Z

Valid Data

RESET#

RY/BY#

0 V

Figure 12. Read Operation Timings

December 13, 2005

Am29PDL640G

43

D A T A S H E E T

AC CHARACTERISTICS

Same Page

A21

-

A3

A0

A2

Ad

Aa

Ab

Ac

t_PACC

t_ACC

Data

Qa

Qb

Qc

Qd

CE#

OE#

Figure 13. Page Read Operation Timings

44

Am29PDL640G

December 13, 2005

D A T A S H E E T

AC CHARACTERISTICS

Hardware Reset (RESET#)

Parameter

JEDEC

Std

Description

All Speed Options

Unit

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note)

t_Ready

Max

20

µs

RESET# Pin Low (NOT During Embedded

Algorithms) to Read Mode (See Note)

t_Ready

500

ns

t_RP

t_RH

t_RPD

t_RB

RESET# Pulse Width

Min

500

50

20

0

ns

µs

ns

Reset High Time Before Read (See Note)

RESET# Low to Standby Mode

RY/BY# Recovery Time

Note: Not 100% tested.

RY/BY#

CE#, OE#

RESET#

t_RH

t_RP

t_Ready

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

t_Ready

RY/BY#

t_RB

CE#, OE#

RESET#

t_RP

Figure 14. Reset Timings

December 13, 2005

Am29PDL640G

45

D A T A S H E E T

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std

t_WC

t_AS

Description

63

73

83

98

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Min

65

70

85

90

t_AVWL

0

15

45

0

ns

Address Setup Time to OE# low during toggle bit

polling

t_ASO

t_AH

Min

ns

t_WLAX

Address Hold Time

Address Hold Time From CE# or OE# high

during toggle bit polling

t_AHT

t_DVWH

t_WHDX

t_DS

t_DH

Data Setup Time

Min

35

0

ns

Data Hold Time

t_OEPH

Output Enable High during toggle bit polling

20

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHWL

Min

0

ns

t_ELWL

t_WHEH

t_WLWH

t_WHDL

t_CS

t_CH

CE# Setup Time

Min

Typ

Min

Max

0

ns

µs

sec

µs

ns

CE# Hold Time

t_WP

Write Pulse Width

35

30

0

t_WPH

t_SR/W

Write Pulse Width High

Latency Between Read and Write Operations

t_WHWH1

t_WHWH2

t_WHWH1Programming Operation (Note 2)

t_WHWH1Accelerated Programming Operation (Note 2)

t_WHWH2Sector Erase Operation (Note 2)

6

4

0.2

50

0

t_VCS

t_RB

V_CCSetup Time (Note 1)

Write Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

t_BUSY

90

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

46

Am29PDL640G

December 13, 2005

D A T A S H E E T

AC CHARACTERISTICS

Program Command Sequence (last two cycles)

Read Status Data (last two cycles)

t_AS

PA

t_WC

Addresses

555h

PA

t_AH

CE#

OE#

t_CH

t_WHWH1

t_WP

WE#

Data

t_WPH

t_CS

t_DS

t_DH

PD

D_OUT

A0h

Status

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Notes:

1. PA = program address, PD = program data, D_OUTis the true data at the program address.

Figure 15. Program Operation Timings

V_HH

V_ILor V_IH

WP#/ACC

V_ILor V_IH

t_VHH

Figure 16. Accelerated Program Timing Diagram

December 13, 2005

Am29PDL640G

47

D A T A S H E E T

AC CHARACTERISTICS

Erase Command Sequence (last two cycles)

Read Status Data

VA

t_AS

SA

t_WC

VA

Addresses

CE#

2AAh

555h for chip erase

t_AH

t_CH

OE#

t_WP

WE#

t_WPH

t_WHWH2

t_CS

t_DS

t_DH

Data

Status

D

OUT

55h

30h

10 for Chip Erase

t_BUSY

t_RB

RY/BY#

V_CC

t_VCS

Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”

Figure 17. Chip/Sector Erase Operation Timings

48

Am29PDL640G

December 13, 2005

D A T A S H E E T

AC CHARACTERISTICS

t_WC

Valid PA

t_WC

t_RC

t_WC

Valid PA

Valid RA

Valid PA

Addresses

t_AH

t_AS

t_CPH

t_AS

t_AH

t_ACC

t_CE

CE#

OE#

t_CP

t_OE

t_OEH

t_GHWL

t_WP

WE#

t_DF

t_WPH

t_DS

t_OH

t_DH

Valid

Out

Valid

In

Valid

In

Valid

In

Data

t_SR/W

WE# Controlled Write Cycle

Read Cycle

CE# Controlled Write Cycles

Figure 18. Back-to-back Read/Write Cycle Timings

t_RC

Addresses

VA

t_ACC

t_CE

VA

CE#

t_CH

t_OE

OE#

WE#

t_OEH

t_DF

t_OH

High Z

DQ7

Valid Data

Complement

True

DQ6–DQ0

Valid Data

Status Data

True

Status Data

t_BUSY

RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 19. Data# Polling Timings (During Embedded Algorithms)

December 13, 2005

Am29PDL640G

49

D A T A S H E E T

AC CHARACTERISTICS

t_AHT

t_AS

Addresses

t_AHT

t_ASO

CE#

t_OEH

WE#

t_CEPH

t_OEPH

OE#

t_DH

Valid Data

t_OE

Valid

Status

Valid

Status

Valid

Status

DQ6/DQ2

Valid Data

(first read)

(second read)

(stops toggling)

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle

Figure 20. Toggle Bit Timings (During Embedded Algorithms)

Enter

Embedded

Erasing

Erase

Suspend

Enter Erase

Suspend Program

Erase

Resume

Erase

Erase Suspend

Read

Erase

Suspend

Program

Erase

Complete

WE#

Erase

Erase Suspend

Read

DQ6

DQ2

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle

DQ2 and DQ6.

Figure 21. DQ2 vs. DQ6

50

Am29PDL640G

December 13, 2005

D A T A S H E E T

AC CHARACTERISTICS

Temporary Sector Unprotect

Parameter

JEDEC

Std

t_VIDR

t_VHH

Description

All Speed Options

Unit

ns

V_IDRise and Fall Time (See Note)

V_HHRise and Fall Time (See Note)

Min

500

250

ns

RESET# Setup Time for Temporary Sector

Unprotect

t_RSP

Min

4

µs

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect

t_RRB

Note: Not 100% tested.

V_ID

RESET#

V_ILor V_IH

t_VIDR

Program or Erase Command Sequence

CE#

WE#

t_RRB

t_RSP

RY/BY#

Figure 22. Temporary Sector Unprotect Timing Diagram

December 13, 2005

Am29PDL640G

51

D A T A S H E E T

AC CHARACTERISTICS

V

ID

V

IH

RESET#

SA, A6,

A1, A0

Valid*

Sector Group Protect/Unprotect

60h 60h

Valid*

Status

Verify

40h

Data

1 µs

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

CE#

WE#

OE#

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector/Sector Block Protect and

Unprotect Timing Diagram

52

Am29PDL640G

December 13, 2005

D A T A S H E E T

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

JEDEC

t_AVAV

Std.

t_WC

t_AS

Description

63

73

83

98

Unit

ns

Write Cycle Time (Note 1)

Address Setup Time

Address Hold Time

Data Setup Time

Data Hold Time

Min

65

70

85

90

t_AVWL

t_ELAX

t_DVEH

t_EHDX

0

45

35

0

ns

t_AH

ns

t_DS

ns

t_DH

ns

Read Recovery Time Before Write

(OE# High to WE# Low)

t_GHEL

Min

0

ns

t_WLEL

t_EHWH

t_ELEH

t_EHEL

t_WS

t_WH

t_CP

WE# Setup Time

WE# Hold Time

Min

0

ns

CE# Pulse Width

CE# Pulse Width High

35

30

t_CPH

Programming Operation

(Note 2)

t_WHWH1

Typ

6

µs

t_WHWH1

t_WHWH2

Notes:

t_WHWH1

t_WHWH2

Accelerated Programming Operation (Note 2)

Sector Erase Operation (Note 2)

Typ

4

µs

0.2

sec

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

December 13, 2005

Am29PDL640G

53

D A T A S H E E T

AC CHARACTERISTICS

555 for program

PA for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Addresses

PA

t_WC

t_WH

t_AS

t_AH

WE#

OE#

t_GHEL

t_{WHWH1 or 2}

t_CP

CE#

Data

t_WS

t_CPH

t_DS

t_BUSY

t_DH

DQ7#

D_OUT

t_RH

A0 for program

55 for erase

PD for program

30 for sector erase

10 for chip erase

RESET#

RY/BY#

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. D_OUTis the data written to the device.

4. Waveforms are for the word mode.

Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings

54

Am29PDL640G

December 13, 2005

D A T A S H E E T

ERASE AND PROGRAMMING PERFORMANCE

Parameter

Typ (Note 1) Max (Note 2)

Unit

sec

Comments

Sector Erase Time

Chip Erase Time

0.4

56

5

Excludes 00h programming

prior to erasure (Note 4)

Excludes system level

overhead (Note 5)

Word Program Time

7

210

µs

Accelerated Word Program Time

Chip Program Time (Note 3)

Notes:

4

120

84

µs

28

sec

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V_CC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, V_CC= 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables

Table 14 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Description

Min

Max

Input voltage with respect to V_SSon all pins except I/O pins

(including A9, OE#, and RESET#)

–1.0 V

13 V

Input voltage with respect to V_SSon all I/O pins

V_CCCurrent

–1.0 V

V_CC+ 1.0 V

+100 mA

–100 mA

Note: Includes all pins except V_CC. Test conditions: V_CC= 3.0 V, one pin at a time.

BGA BALL CAPACITANCE

Parameter

Symbol

Parameter Description

Input Capacitance

Test Setup

V_IN= 0

Typ

4.2

5.4

3.9

Max

5.0

6.5

4.7

Unit

pF

C_IN

C_OUT

C_IN2

Output Capacitance

Control Pin Capacitance

V_OUT= 0

V_IN= 0

pF

Notes:

1. Sampled, not 100% tested.

2. Test conditions T_A= 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Description

Test Conditions

150°C

Min

10

Unit

Years

Minimum Pattern Data Retention Time

125°C

20

December 13, 2005

Am29PDL640G

55

D A T A S H E E T

PHYSICAL DIMENSIONS

FBE080—80-Ball Fine-pitch Ball Grid Array 12 x 11 mm package

0.20

(4X)

D1

A

D

eD

8

eE

7

6

SE

5

4

E1

E

3

2

1

M

L

K

J

H

G

F

E

D

C

B

A

A1 CORNER

7

B

A1 CORNER INDEX MARK

10

6

NXOb

SD

M

φ0.08

φ0.15 M

Z

TOP VIEW

Z A B

BOTTOM VIEW

0.25 Z

0.08 Z

A2

A

A1

Z

SEATING PLANE

SIDE VIEW

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS.

PACKAGE

JEDEC

FBE 080

N/A

10.95 mm x 11.95 mm

PACKAGE

NOTE

3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.

SYMBOL

MIN. NOM. MAX.

4.

e REPRESENTS THE SOLDER BALL GRID PITCH.

A

A1

A2

D

---

1.20

---

OVERALL THICKNESS

BALL HEIGHT

5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D"

DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE

IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER

BALLS.

0.20

0.84

---

0.94

BODY THICKNESS

BODY SIZE

11.95 BSC.

E

10.95 BSC.

8.80 BSC.

BODY SIZE

6

DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM Z.

D1

E1

MD

ME

BALL FOOTPRINT

5.60 BSC.

12

BALL FOOTPRINT

7

SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER

BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER

OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D

OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000.

ROW MATRIX SIZE D DIRECTION

8

ROW MATRIX SIZE E DIRECTION

TOTAL BALL COUNT

N

b

80

0.25

0.30

0.35

BALL DIAMETER

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE

OUTER ROW, SD OR SE = e/2

e

0.80 BSC.

BALL PITCH

SD / SE

0.40 BSC.

A3-A6, B3-B6,

L3-L6, M3-M6

SOLDER BALL PLACEMENT

DEPOPULATED SOLDER BALLS

8. "+" IN THE PACKAGE DRAWING INDICATES THE THEORETICAL

CENTER OF DEPOPULATED BALLS.

E

PACKAGE OUTLINE TYPE

9

FOR PACKAGE THICKNESS, "A" IS THE CONTROLLING DIMENSION.

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, INK MARK,

METALLIZED MARKINGS INDENTION OR OTHER MEANS.

3150\38.9G

56

Am29PDL640G

December 13, 2005

D A T A S H E E T

PHYSICAL DIMENSIONS

FBE063—63-Ball Fine-pitch Ball Grid Array 12 x 11 mm package

Dwg rev AF; 10/99

December 13, 2005

Am29PDL640G

57

D A T A S H E E T

REVISION SUMMARY

Connection Diagram

July 12, 2002

Added Note.

Initial release.

Removed the 64-ball Fortified BGA connection dia-

gram.

Revision A+1 (July 29, 2002)

Global

Ordering Information

Changed all references to DPB to DYB

Removed the Extended temperature range.

Table 7. Autoselect Codes (High Voltage Method)

Removed the PC package type.

Changed the A5 to A4 and A3 Sector Protection Verifi-

cation fields from L to H.

Table 1. Am29PDL640G Device Bus Operations and

Standby Mode

Table 9. Sector Protection Schemes

Changed V_CC± 0.3 V to V_IO± 0.3 V.

Added field: Unprotected-PPB not changeable, DYB is

changeable.

Table 14. Memory Array Command Definitions

Deleted Configuration Register Verify and Write from

table.

Figure 1. In-System Sector Protection/Sector

Unprotection Algorithms

Deleted Note #15.

Added Note

Table 15. Sector Protection Command Definitions

Table 14. Memory Array Command Definitions (x32

Mode)

Changed All PPB Erase address from WP to EP.

Added SecSi Sector Factory Protect and Sector Group

Protect Verify fields to tables.

Added “EP = PPB Erase Address (A6:A0) is (1111010)

(Note 16)” to legend.

Added Notes 8 and 9

Added “the EP address is 01000010” to note #16.

Table 15. Sector Protection Command Definitions

(x32 mode)

Operating Ranges

Removed the Extended temperature range.

Changed variables in Cycle field for Password Pro-

gram (from 5 to 4), PPMLB Status (from 6 to 4), and

SPMLB Status (from 6 to 4).

CMOS Compatible

Changed V_CCto V_IOin I_CC3and I_CC5Test Conditions.

Changed Typical from 0.2 to 1 in I_CC3, I_CC4, and I_CC5

Parameters.

DC Characteristics

Removed I_ACCparameter from CMOS Compatable ta-

ble.

Added Min and/or Max to V_IL, V_IH, V_OL, and V_OH

.

Changed specific references from ACC to WP#/ACC.

Revision B (January 14, 2003)

FBGA Ball Capacitance

Distinctive Characteristics, Product Selector

Guide, and Ordering Information

Changed table from TSOP Pin Capacitance to FBGA

Ball Capacitance and modified values within table to

reflect change.

Added 65 ns speed grade.

Customer Lockable: SecSi Sector NOT

Programmed or Protected at the factory.

CFI

Modified end of last paragraph to “reading array data”

Added second bullet, SecSi sector-protect verify text

and figure 3.

Special Package Handling Instructions

Modified wording to include molded packages (TSOP,

BGA, PLCC, PDIP, SSOP).

Command Definitions

Modified last sentence of the first paragraph to state

that writing a wrong address will return the device to

an unknown state and that a reset command is re-

quired to return the device to reading array data.

Revision A+2 (September 30, 2002)

Distinctive Characteristics and General

Description

Removed the 64-ball Fortified BGA from Package op-

tions.

58

Am29PDL640G

December 13, 2005

D A T A S H E E T

SecSi Sector Flash Memory Region, and Enter

Table 15. Sector Protection Command Definitions

SecSi Sector/Exit SecSi Sector Command

Sequence

Added Note # 17 and 18.

Table 17. Test Specifications, Read-Only

Operations, and Erase and Programing Operations

Noted that the ACC function and unlock bypass modes

are not available when the SecSi sector is enabled.

Added 63 option to tables.

Byte/Word Program Command Sequence, Sector

Erase Command Sequence, and Chip Erase Com-

mand Sequence

Revision B+1 (February 26, 2003)

Table 17. Test Specification

Noted that the SecSi Sector, autoselect, and CFI

functions are unavailable when a program or erase

operation is in progress.

Updated output load capacitance.

Revision B+2 (December 13, 2005)

Common Flash Memory Interface (CFI)

Global

Changed CFI website address.

This product has been retired and is not available for

designs. For new and current designs, S29PL064J su-

persedes Am29PDL640G and is the factory-recom-

mended migration path. Please refer to the

S29PL064J datasheet for specifications and ordering

information. Availability of this document is retained for

reference and historical purposes only.

Test Conditions

Modified speed grade option rows to state “All

Speeds”.

Table 17. Test Specifications, Read-Only

Operations, and Erase and Programing Operations

Noted that one must write SecSi Sector reset before

PPB program/erase.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

December 13, 2005

Am29PDL640G

59


型号：	PD640G98UI
厂家：	AMD
描述：	64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control 64兆位（4M ×16位） CMOS 3.0伏只，同步读/写闪存增强型VersatileIOTM控制闪存 IOT
文件：	总61页 (文件大小：1041K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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