A29800TV-70IF [AMICC]
Flash, 512KX16, 70ns, PDSO48, ROHS COMPLIANT, TSOP1-48;
| 型号： | A29800TV-70IF |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | Flash, 512KX16, 70ns, PDSO48, ROHS COMPLIANT, TSOP1-48 光电二极管 内存集成电路 |
| 文件： | 总37页 (文件大小：572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A29800 Series
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Document Title
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
Initial issue
May 4, 2001
Preliminary
Error Correction:
December 24, 2002
October 7, 2003
July 15, 2004
P.10: Autoselect Command Sequence (line 15), XX11h → XX03h
Final version release
1.0
1.1
1.2
1.3
1.4
Final
Add Pb-Free package type for -70 grade
Add -70I series products
January 24, 2007
November 13, 2007
February 26, 2009
Modify symbol “L” outline dimensions in TSOP 48L package
Update -70I series product working temperature range: read -40°C
to +85°C, erase & program 0°C to +85°C
1.5
1.6
Error correction: Modify Figure 3. Erase Operation
April 28, 2009
Modify the latency time of erase suspend from 20μs to 30μs
Error correction: Modify the way to check write operation status by
December 01, 2009
either
or
to by
and
OE CE
OE
CE
1.7
1.8
Error correction: Delete tWPH Max. 50μs
Page 1: Change from typical 100,000 cycles to minimum 100,000
Cycles
December 21, 2009
December 31, 2010
1.9
Replace all non Pb-Free parts with Pb-Free ones
October 21, 2011
(October, 2011, Version 1.9)
AMIC Technology, Corp.
A29800 Series
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
Minimum 100,000 program/erase cycles per sector
20-year data retention at 125°C
- Reliable operation for the life of the system
Compatible with JEDEC-standards
5.0V ± 10% for read and write operations
Access times:
- 55/70/90 (max.)
Current:
- 28mA read current (word mode)
- Pinout and software compatible with single-power-supply
- 20 mA typical active read current (byte mode)
- 30 mA typical program/erase current
Flash memory standard
- Superior inadvertent write protection
- 1 μA typical CMOS standby
Polling and toggle bits
- Provides a software method of detecting completion of
program or erase operations
Data
Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
- Any combination of sectors can be erased
- Supports full chip erase
Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
- Sector protection:
A hardware method of protecting sectors to prevent any
inadvertent program or erase operations within that sector
Extended read operating temperature range: -40°C ~ +85°C
for – I series
Extended erase and program temperature range: 0°C ~
+85°C for – I series
Hardware reset pin (
)
RESET
- Hardware method to reset the device to reading array
data
Package options
- 44-pin SOP or 48-pin TSOP (I)
- All Pb-free (Lead-free) products are RoHS compliant
Top or bottom boot block configurations available
Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies bytes at specified addresses
General Description
The device requires only a single 5.0 volt power supply for
both read and write functions.
The A29800 is a 5.0 volt only Flash memory organized as
1048,576 bytes of 8 bits or 524,288 words of 16 bits each. The
Internally generated and regulated voltages are provided for
the program and erase operations.
A29800 offers the
function. The 1024 Kbytes of data
RESET
are further divided into nineteen sectors for flexible sector
erase capability. The 8 bits of data appear on I/O0 - I/O7 while
the addresses are input on A1 to A18; the 16 bits of data
appear on I/O0~I/O15. The A29800 is offered in 44-pin SOP
and 48-Pin TSOP packages. This device is designed to be
programmed in-system with the standard system 5.0 volt VCC
supply. Additional 12.0 volt VPP is not required for in-system
write or erase operations. However, the A29800 can also be
programmed in standard EPROM programmers.
The A29800 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it is
in the Erase Suspend. Besides the I/O6 toggle bit, the A29800
has a second toggle bit, I/O2, to indicate whether the
addressed sector is being selected for erase. The A29800 also
offers the ability to program in the Erase Suspend mode. The
standard A29800 offers access times of 55, 70 and 90 ns,
allowing high-speed microprocessors to operate without wait
states. To eliminate bus contention the device has separate
The A29800 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard
microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and
programming circuitry.
Write cycles also internally latch addresses and data needed
for the programming and erase operations. Reading data out
of the device is similar to reading from other Flash or EPROM
devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
-
an internal algorithm that automatically
preprograms the array (if it is not already programmed) before
executing the erase operation.
During erase, the device automatically times the erase pulse
widths and verifies proper erase margin.
chip enable (
), write enable (
) and output enable
WE
CE
(
) controls.
OE
(October, 2011, Version 1.9)
1
AMIC Technology, Corp.
A29800 Series
The host system can detect whether a program or erase
operation is complete by reading the I/O7 ( Polling) and
I/O6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The A29800 is fully erased when shipped
from the factory.
The Erase Suspend feature enables the user to put erase on
hold for any period of time to read data from, or program data
to, any other sector that is not selected for erasure. True
background erase can thus be achieved.
Power consumption is greatly reduced when the device is
placed in the standby mode.
Data
The hardware
pin terminates any operation in
RESET
progress and resets the internal state machine to reading
array data.
The hardware sector protection feature disables operations for
both program and erase in any combination of the sectors
of memory. This can be achieved via programming equipment.
Pin Configurations
SOP
TSOP (I)
RY/BY
1
RESET
WE
44
43
42
A18
A17
A7
2
3
4
A8
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
A18
A17
A7
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
A16
BYTE
VSS
I/O15 (A-1)
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
A9
41
40
39
38
A10
A11
A6
5
6
A5
A4
A3
A2
A1
A0
A12
A13
7
8
37
36
35
34
9
10
11
12
13
14
15
16
17
18
19
A14
A15
9
10
11
12
13
14
15
16
17
18
19
20
21
A29800V
A16
CE
33
32
31
30
29
28
27
26
25
24
BYTE
VSS
VSS
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O15 (A-1)
I/O7
A6
A5
A4
A3
A2
A1
20
21
22
23
24
29
28
27
26
25
I/O0
OE
I/O14
I/O6
VSS
CE
A0
I/O13
I/O5
I/O12
I/O4
I/O10
I/O3
VCC
I/O11
23
22
(October, 2011, Version 1.9)
2
AMIC Technology, Corp.
A29800 Series
Block Diagram
RY/BY
I/O0 - I/O15 (A-1)
VCC
VSS
Sector Switches
Input/Output
Buffers
Erase Voltage
Generator
RESET
State
Control
WE
BYTE
PGM Voltage
Generator
Command
Register
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
VCC Detector
Timer
A0-A18
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 - A18
I/O0 - I/O14
Description
Address Inputs
Data Inputs/Outputs
Data Input/Output, Word Mode
I/O15
I/O15 (A-1)
A-1
LSB Address Input, Byte Mode
Chip Enable
CE
WE
Write Enable
Output Enable
OE
Hardware Reset
RESET
BYTE
Selects Byte Mode or Word Mode
Ready/
- Output
BUSY
RY/
BY
VSS
VCC
Ground
Power Supply
(October, 2011, Version 1.9)
3
AMIC Technology, Corp.
A29800 Series
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. These
are stress ratings only. Functional operation of this device at
these or any other conditions above those indicated in the
operational sections of these specification is not implied or
intended. Exposure to the absolute maximum rating
conditions for extended periods may affect device reliability.
Ambient Operating Temperature . . . . ….. -55°C to + 125°C
Storage Temperature . . . . . . . . . . . . . . …. -65°C to + 125°C
Ground to VCC . . . . . . . . . . . . . . . . . . . . . ….. -2.0V to 7.0V
Output Voltage (Note 1) . . . . . . . . . . . . . . …... -2.0V to 7.0V
A9,
&
(Note 2) . . . . . . . . . . ….. -2.0V to 12.5V
RESET
OE
All other pins (Note 1) . . . . . . . . . . . . . . . . ….. -2.0V to 7.0V
Output Short Circuit Current (Note 3) . . . . . . ….. . . . 200mA
Operating Ranges
Notes:
Commercial (C) Devices
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, inputs may undershoot VSS to -2.0V
for periods of up to 20ns. Maximum DC voltage on output
and I/O pins is VCC +0.5V. During voltage transitions,
outputs may overshoot to VCC +2.0V for periods up to
20ns.
Ambient Temperature (TA) . . . . . . . . …. .. . . . . 0°C to +70°C
Extended Range Devices
Ambient Temperature (TA)
For – I series (read) . . . . . . . . . . . . . . . . . . -40°C to + 85°C
For – I series (erase, program) . . . . . . . . . . . . 0°C to + 85°C
2. Minimum DC input voltage on A9 pins is -0.5V. During
voltage transitions, A9,
and
may overshoot
RESET
OE
VSS to -2.0V for periods of up to 20ns. Maximum DC input
voltage on A9 and is +12.5V which may overshoot to
OE
VCC Supply Voltages
13.5V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
VCC for ± 10% devices . . . . . . . . . . . …... . . +4.5V to +5.5V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29800 Device Bus Operations
Operation
A0 - A18
I/O0 - I/O7
I/O8 - I/O15
=VIH
WE
CE
OE
RESET
=VIL
BYTE
BYTE
Read
Write
L
L
H
X
X
H
X
X
H
L
H
AIN
AIN
X
DOUT
DIN
DOUT
DIN
High-Z
L
H
High-Z
High-Z
High-Z
High-Z
High-Z
X
CMOS Standby
TTL Standby
X
X
H
X
X
High-Z
High-Z
High-Z
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
DIN
VCC ± 0.5 V
VCC ± 0.5 V
H
L
H
H
X
Output Disable
Hardware Reset
X
X
X
L
X
Temporary Sector Unprotect
(See Note)
VID
AIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note:
See the "Sector Protection/Unprotection" section and Temporary Sector Unprotect for more information.
(October, 2011, Version 1.9)
4
AMIC Technology, Corp.
A29800 Series
Word/Byte Configuration
Program and Erase Operation Status
During an erase or program operation, the system may check
the status of the operation by reading the status bits on I/O7 -
I/O0. Standard read cycle timings and ICC read specifications
apply. Refer to "Write Operation Status" for more information,
and to each AC Characteristics section for timing diagrams.
The
pin determines whether the I/O pins I/O15 - I/O0
BYTE
operate in the byte or word configuration. If the
pin is
BYTE
set at logic “1”, the device is in word configuration, I/O15 - I/O0
are active and controlled by and
.
OE
CE
If the
pin is set at logic “0”, the device is in byte
BYTE
configuration, and only I/O0 - I/O7 are active and controlled by
and . I/O8- I/O14 are tri-stated, and I/O15 pin is used as
Standby Mode
When the system is not reading or writing to the device, it can
place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
CE
OE
an input for the LSB(A-1) address function.
Requirements for Reading Array Data
the high impedance state, independent of the
input.
OE
To read array data from the outputs, the system must drive
The device enters the CMOS standby mode when the
&
CE
the
and
pins to VIL.
is the power control and
CE
OE
CE
pins are both held at VCC ± 0.5V. (Note that this is a
RESET
more restricted voltage range than VIH.) The device enters the
TTL standby mode when is held at VIH, while is
selects the device.
OE
data to the output pins.
is the output control and gates array
CE
RESET
should remain at VIH all the time
WE
held at VCC±0.5V. The device requires the standard access
time (tCE) before it is ready to read data.
during read operation. The internal state machine is set for
reading array data upon device power-up, or after a hardware
reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses on the
device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the
command register contents are altered.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
When the
input is at VIH, output from the device is
OE
disabled. The output pins are placed in the high impedance
state.
: Hardware Reset Pin
RESET
Writing Commands/Command Sequences
The
pin provides a hardware method of resetting the
RESET
device to reading array data. When the system drives the
pin low for at least a period of tRP, the device
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
RESET
memory), the system must drive
and
to VIL, and
CE
immediately terminates any operation in progress, tristates all
data output pins, and ignores all read/write attempts for the
WE
to VIH. An erase operation can erase one sector, multiple
OE
duration of the
pulse. The device also resets the
RESET
sectors, or the entire device. The Sector Address Tables
indicate the address range that each sector occupies. A
"sector address" consists of the address inputs required to
uniquely select a sector. See the "Command Definitions"
section for details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
The
pin may be tied to the system reset circuitry. A
RESET
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard read
cycle timings apply in this mode. Refer to the "Autoselect
Mode" and "Autoselect Command Sequence" sections for
more information.
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
Refer to the AC Characteristics tables for
and diagram.
parameters
RESET
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
(October, 2011, Version 1.9)
5
AMIC Technology, Corp.
A29800 Series
Table 2. A29800 Top Boot Block Sector Address Table
Sector A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
(x16)
(x8)
Address Range
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
00000h - 07FFFh 00000h - 0FFFFh
08000h - 0FFFFh 10000h - 1FFFFh
10000h - 17FFFh 20000h - 2FFFFh
18000h - 1FFFFh 30000h - 3FFFFh
20000h - 27FFFh 40000h - 4FFFFh
28000h - 2FFFFh 50000h - 5FFFFh
30000h - 37FFFh 60000h - 6FFFFh
SA2
SA3
SA4
SA5
SA6
SA7
38000h -3FFFFh
40000h -47FFFh
48000h -4FFFFh
70000h -7FFFFh
80000h -8FFFFh
90000h -9FFFFh
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
50000h - 57FFFh A0000h - AFFFFh
58000h - 5FFFFh B0000h - BFFFFh
60000h - 67FFFh C0000h - CFFFFh
68000h - 6FFFFh D0000h - DFFFFh
70000h - 77FFFh E0000h - EFFFFh
78000h - 7BFFFh F0000h - F7FFFh
7C000h - 7CFFFh F8000h - F9FFFh
7D000h - 7DFFFh FA000h - FBFFFh
7E000h - 7FFFFh FC000h - FFFFFh
1
1
0
1
8/4
1
1
X
16/8
Note:
Address range is A18: A-1 in byte mod and A18: A0 in word mode. See the “Word/Byte Configuration” section for more
information.
(October, 2011, Version 1.9)
6
AMIC Technology, Corp.
A29800 Series
Table 3. A29800 Bottom Boot Block Sector Address Table
Sector A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes /
Kwords)
Address Range
(x 16)
(x 8)
Address Range
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
16/8
8/4
00000h - 01FFFh
02000h - 02FFFh
03000h - 03FFFh
04000h - 07FFFh
08000h - 0FFFFh
10000h - 17FFFh
18000h - 1FFFFh
20000h - 27FFFh
28000h - 2FFFFh
30000h - 37FFFh
38000h - 3FFFFh
40000h - 47FFFh
48000h - 4FFFFh
50000h - 57FFFh
58000h - 5FFFFh
60000h - 67FFFh
00000h - 03FFFh
04000h - 05FFFh
06000h - 07FFFh
08000h - 0FFFFh
10000h - 1FFFFh
20000h - 2FFFFh
30000h - 3FFFFh
40000h - 4FFFFh
50000h - 5FFFFh
60000h - 6FFFFh
70000h - 7FFFFh
80000h - 8FFFFh
90000h - 9FFFFh
A0000h - AFFFFh
B0000h - BFFFFh
C0000h - CFFFFh
SA2
0
1
1
8/4
SA3
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
68000h - 6FFFFh D0000h - DFFFFh
70000h - 77FFFh
78000h - 7FFFFh
E0000h - EFFFFh
F0000h - FFFFFh
Note:
Address range is A18: A-1 in byte mode and A18: A0 in word mode. See the “Word/Byte Configuration” section for more
information
(October, 2011, Version 1.9)
7
AMIC Technology, Corp.
A29800 Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register,
as shown in the Command Definitions table. This method
does not require VID. See "Command Definitions" for details
on using the autoselect mode.
a
device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Autoselect Codes
(High Voltage Method) table. In addition, when verifying
sector protection, the sector address must appear on the
Table 4. A29800 Autoselect Codes (High Voltage Method)
A18
to
A11
to
A9
A8
to
A6
A5
to
A1
A0
I/O8
to
I/O7
to
Description
Mode
CE OE WE
A12
A10
A7
A2
I/O15
I/O0
Manufacturer ID: AMIC
Device ID: A29800
(Top Boot Block)
L
L
L
L
H
H
X
X
VID
X
X
L
L
X
X
L
L
L
X
B3h
X
37h
0Eh
0Eh
8Fh
8Fh
7Fh
Word
Byte
Word
Byte
X
X
VID
H
Device ID: A29800
(Bottom Boot Block)
B3h
X
L
L
L
L
H
H
X
X
X
X
VID
X
X
L
L
X
X
L
H
H
Continuation ID
VID
H
X
01h
(protected)
X
X
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
00h
(unprotected)
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Don’t Care.
(October, 2011, Version 1.9)
8
AMIC Technology, Corp.
A29800 Series
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
START
Sector protection/unprotection must be implemented using
programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected.
RESET = VID
(Note 1)
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
Hardware Data Protection
Perform Erase or
Program Operations
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device is
powered up to read array data to avoid accidentally writing
data to the array.
RESET = VIH
Write Pulse "Glitch" Protection
Temporary Sector
Unprotect
Completed (Note 2)
Noise pulses of less than 5ns (typical) on
do not initiate a write cycle.
,
or
OE CE
WE
Logical Inhibit
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Write cycles are inhibited by holding any one of
=VIL,
OE
CE
CE
= VIH or
= VIH. To initiate a write cycle,
and
WE
WE
Figure 1. Temporary Sector Unprotect Operation
must be a logical zero while
is a logical one.
OE
Power-Up Write Inhibit
If
=
= VIL and
= VIH during power up, the
OE
WE
device does not accept commands on the rising edge of
. The internal state machine is automatically reset to
CE
WE
reading array data on the initial power-up.
Temporary Sector Unprotect
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the
pin to VID.
RESET
During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the
pin, all the previously
RESET
protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
(October, 2011, Version 1.9)
9
AMIC Technology, Corp.
A29800 Series
Command Definitions
Autoselect Command Sequence
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not
a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
All addresses are latched on the falling edge of
or
,
CE
WE
whichever happens later. All data is latched on the rising
edge of or , whichever happens first. Refer to the
WE
CE
appropriate timing diagrams in the "AC Characteristics"
section.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h in word
mode (or 02h in byte mode) returns the device code. A read
cycle containing a sector address (SA) and the address 02h
in returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to the Sector Address tables for valid
sector addresses.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing
an Embedded Program or Embedded Erase algorithm. After
the device accepts an Erase Suspend command, the device
enters the Erase Suspend mode. The system can read array
data using the standard read timings, except that if it reads at
an address within erase-suspended sectors, the device
The system must write the reset command to exit the
autoselect mode and return to reading array data.
outputs status data. After completing
a programming
Word/Byte Program Command Sequence
operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See "Erase
Suspend/Erase Resume Commands" for more information on
this mode.
The system may program the device by word or byte,
depending on the state of the
pin. Programming is a
BYTE
four-bus-cycle operation. The program command sequence is
initiated by writing two unlock write cycles, followed by the
program set-up command. The program address and data
are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verify the
programmed cell margin. Table 5 shows the address and
data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also
applies to programming in Erase Suspend mode). Once
programming begins, however, the device ignores reset
commands until the operation is complete.
program operation by using I/O7, I/O6, or RY/
. See “White
BY
Operation Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Not that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data
integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
to “1”, or cause the
Polling algorithm to indicate the
Data
operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
(October, 2011, Version 1.9)
10
AMIC Technology, Corp.
A29800 Series
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O7, I/O6, or I/O2. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 3 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
START
Write Program
Command
Sequence
Data Poll
from System
Sector Erase Command Sequence
Embedded
Program
algorithm in
progress
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50μs begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50μs, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional sector
erase commands can be assumed to be less than 50μs, the
system need not monitor I/O3. Any command other than
Sector Erase or Erase Suspend during the time-out period
resets the device to reading array data. The system must
rewrite the command sequence and any additional sector
addresses and commands.
Verify Data ?
Yes
No
Increment Address
Last Address ?
Yes
Programming
Completed
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
The system can monitor I/O3 to determine if the sector erase
timer has timed out. (See the " I/O3: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
preprograms and verifies the entire memory for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations. The Command Definitions table shows the
address and data requirements for the chip erase command
sequence.
pulse in the command sequence.
WE
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, or I/O2. Refer to "Write
Operation Status" for information on these status bits.
Figure 3 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
(October, 2011, Version 1.9)
11
AMIC Technology, Corp.
A29800 Series
Erase Suspend/Erase Resume Commands
START
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or program
data to, any sector not selected for erasure. This command is
valid only during the sector erase operation, including the
50μs time-out period during the sector erase command
sequence. The Erase Suspend command is ignored if written
during the chip erase operation or Embedded Program
algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are
"don't cares" when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector
erase operation, the device requires a maximum of 30μs to
suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period
and suspends the erase operation.
Write Erase
Command
Sequence
Data Poll
from System
Embedded
Erase
algorithm in
progress
No
Data = FFh ?
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O7
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erase-
suspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete, the
system can once again read array data within non-suspended
sectors. The system can determine the status of the program
operation using the I/O7 or I/O6 status bits, just as in the
standard program operation. See "Write Operation Status" for
more information.
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O3 : Sector Erase Timer" for more information.
Figure 3. Erase Operation
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further writes
of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
(October, 2011, Version 1.9)
12
AMIC Technology, Corp.
A29800 Series
Table 5. A29800 Command Definitions
Bus Cycles (Notes 2 - 5)
Third Fourth
Command
Sequence
(Note 1)
First
Addr Data Addr Data
RA RD
Second
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data
Read (Note 6)
Reset (Note 7)
1
1
XXX F0
555
Word
Byte
Word
Byte
2AA
555
2AA
555
Manufacturer ID
4
4
AA
55
55
90 X00
37
AAA
AAA
555
B30E
0E
555
AA
AAA
X01
90
Device ID,
Top Boot Block
555
2AA
555
AAA
555
X02
Word
Byte
B38F
8F
555
90
X01
X02
X03
Device ID,
Bottom Boot Block
AA
AA
55
4
4
AAA
AAA
Word
Byte
555
AAA
555
2AA
555
2AA
555
AAA
555
Continuation ID
55
55
90
7F
X06
XX00
(SA)
X02
Word
Sector Protect Verify
(Note 9)
XX01
00
4
AA
90
(SA)
X04
Byte
AAA
555
AAA
01
Word
Byte
Word
Byte
Word
Byte
555
2AA
555
2AA
555
2AA
555
555
AAA
555
Program
4
6
6
AA
AA
AA
55
55
55
A0
80
80
PA
PD
AA
AA
AAA
555
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
55
55
10
30
AAA
555
AAA
555
AAA
Sector Erase
SA
AAA
AAA
AAA
Erase Suspend (Note 9)
Erase Resume (Note 10)
1
1
XXX B0
XXX 30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the
whichever happens later.
or
pulse,
CE
WE
PD = Data to be programmed at location PA. Data latches on the rising edge of
or
pulse, whichever happens first.
CE
WE
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A18 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
(October, 2011, Version 1.9)
13
AMIC Technology, Corp.
A29800 Series
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, I/O7, RY/
the A29800 to determine the status of a write operation.
Table 6 and the following subsections describe the functions
are provided in
BY
START
of these status bits. I/O7, I/O6 and RY/
each offer a
BY
method for determining whether
a program or erase
operation is complete or in progress. These three bits are
discussed first.
Read I/O
Address = VA
7-I/O0
I/O7:
Polling
Data
The
Polling bit, I/O7, indicates to the host system
Data
whether an Embedded Algorithm is in progress or completed,
Yes
I/O
7
= Data ?
No
or whether the device is in Erase Suspend. Polling is
Data
pulse in the
valid after the rising edge of the final
program or erase command sequence.
WE
During the Embedded Program algorithm, the device outputs
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
No
I/O5 = 1?
Yes
protected sector,
Polling on I/O7 is active for
Data
approximately 2μs, then the device returns to reading array
data.
Read I/O
7
- I/O0
During the Embedded Erase algorithm,
Polling
Address = VA
Data
produces a "0" on I/O7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Polling produces a "1" on I/O7.This is analogous to the
Data
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in
a sector to "1"; prior to this, the device outputs the
"complement," or "0." The system must provide an address
within any of the sectors selected for erasure to read valid
status information on I/O7.
Yes
I/O7
= Data ?
No
After an erase command sequence is written, if all sectors
selected for erasing are protected,
Polling on I/O7 is
Data
active for approximately 100μs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
(
) is asserted low. The
Polling Timings (During
Data
OE
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 6 shows the outputs for
2. I/O
7
should be rechecked even if I/O
may change simultaneously with I/O
5 = "1" because
I/O7
5
.
Data
Polling algorithm.
Polling on I/O7. Figure 4 shows the
Data
Figure 4. Data Polling Algorithm
(October, 2011, Version 1.9)
14
AMIC Technology, Corp.
A29800 Series
I/O2: Toggle Bit II
RY/
: Read/
Busy
BY
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
The RY/
is a dedicated, open-drain output pin that
BY
indicates whether an Embedded algorithm is in progress or
complete. The RY/ status is valid after the rising edge of
BY
pulse in the command sequence. Since
the final
WE
rising edge of the final
I/O2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
pulse in the command sequence.
WE
RY/
is an open-drain output, several RY/
pins can be
BY
BY
tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
system may use
and
to control the read cycles.) But
CE
OE
I/O2 cannot distinguish whether the sector is actively erasing
or is erase-suspended. I/O6, by comparison, indicates
whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 to compare outputs for
I/O2 and I/O6.
Figure 5 shows the toggle bit algorithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The I/O2
vs. I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form.
Table 6 shows the outputs for RY/
. Refer to “
RESET
BY
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Program
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge
Reading Toggle Bits I/O6, I/O2
of the final
pulse in the command sequence (prior to the
WE
Refer to Figure 5 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7 - I/O0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and
store the value of the toggle bit after the first read. After the
second read, the system would compare the new value of the
toggle bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation. The
system can read array data on I/O7 - I/O0 on the following
read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
5).
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
(The system may use
and
to control the read
CE
OE
cycles.) When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100μs, then returns to reading array data. If
not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O6 toggles. When the
device enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 :
Polling").
Data
If a program address falls within a protected sector, I/O6
toggles for approximately 2μs after the program command
sequence is written, then returns to reading array data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O6. Refer to Figure 5 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O2 vs.
I/O6 figure shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on " I/O2: Toggle Bit
II".
(October, 2011, Version 1.9)
15
AMIC Technology, Corp.
A29800 Series
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
START
The I/O5 failure condition may appear if the system tries to
program a "1 "to a location that is previously programmed to
"0." Only an erase operation can change a "0" back to a "1."
Under this condition, the device halts the operation, and
when the operation has exceeded the timing limits, I/O5
produces a "1."
Read I/O
7
-I/O
0
Read I/O7-I/O
0
(Note 1)
No
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
I/O3: Sector Erase Timer
Toggle Bit
= Toggle ?
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. When the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time between
additional sector erase commands will always be less than
50μs. See also the "Sector Erase Command Sequence"
section.
Yes
No
I/O5 = 1?
Yes
- I/O
After the sector erase command sequence is written, the
Read I/O
7
0
(Notes 1,2)
system should read the status on I/O7 (
Polling) or I/O6
Data
Twice
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (other than Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted. Table 6 shows the outputs for I/O3.
No
Toggle Bit
= Toggle ?
Yes
Program/Erase
Operation Not
Program/Erase
Commplete, Write
Reset Command
Operation Complete
Notes :
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as I/O
5
changes to "1". See text.
Figure 5. Toggle Bit Algorithm
(October, 2011, Version 1.9)
16
AMIC Technology, Corp.
A29800 Series
Table 6. Write Operation Status
I/O7
I/O6
I/O5
(Note 2)
0
I/O3
I/O2
RY/
BY
Operation
(Note 1)
(Note 1)
Standard
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Toggle
Toggle
N/A
1
No toggle
0
I/O7
0
0
0
Toggle
Toggle
0
1
Erase
Reading within Erase
Suspended Sector
1
No toggle
N/A
Suspend
Mode
Reading within Non-Erase
Suspend Sector
Data
I/O7
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend-Program
Toggle
Notes:
1. I/O7 and I/O2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. I/O5 switches to “1” when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “I/O5: Exceeded Timing Limits” for more information.
Maximum Negative Input Overshoot
20ns
20ns
+0.8V
-0.5V
-2.0V
20ns
Maximum Positive Input Overshoot
20ns
VCC+2.0V
VCC+0.5V
2.0V
20ns
20ns
(October, 2011, Version 1.9)
17
AMIC Technology, Corp.
A29800 Series
DC Characteristics
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
A9, Input Load Current
Test Description
Min.
Typ.
Max.
Unit
μA
ILI
VIN = VSS to VCC. VCC = VCC Max
VCC = VCC Max,
±1.0
ILIT
100
&
μA
OE RESET
A9,
&
=12.5V
OE RESET
ILO
Output Leakage Current
VOUT = VSS to VCC. VCC = VCC Max
±1.0
μA
ICC1
VCC Active Read Current
(Notes 1, 2)
20
30
30
mA
= VIL,
= VIH
=VIH
CE
OE
OE
VCC Active Write (Program/Erase)
Current (Notes 2, 3, 4)
ICC2
ICC3
40
mA
mA
= VIL,
= VIH,
CE
CE
VCC Standby Current (Note 2)
0.4
1.0
= VCC ± 0.5V
RESET
VIL
VIH
Input Low Level
Input High Level
-0.5
2.0
0.8
V
V
VCC+0.5
Voltage for Autoselect and
Temporary Unprotect Sector
Output Low Voltage
VID
VCC = 5.25 V
10.5
V
12.5
0.45
VOL
VOH
IOL = 12mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
V
V
Output High Voltage
2.4
CMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
A9,
Test Description
Min.
Typ.
Max.
Unit
μA
ILI
VIN = VSS to VCC, VCC = VCC Max
VCC = VCC Max,
±1.0
ILIT
50
&
Input Load Current
μA
OE RESET
A9,
&
= 12.5V
OE RESET
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max
±1.0
μA
VCC Active Read Current
(Notes 1,2)
ICC1
20
30
mA
= VIL,
= VIL,
= VIH
CE
CE
OE
OE
VCC Active Program/Erase Current
(Notes 2,3,4)
ICC2
ICC3
30
1
40
5
mA
= VIH
VCC Standby Current (Notes 2, 5)
μA
=
= VCC ± 0.5 V
CE RESET
VIL
VIH
Input Low Level
Input High Level
-0.5
V
V
0.8
0.7 x VCC
VCC+0.3
Voltage for Autoselect and
Temporary Sector Unprotect
Output Low Voltage
VID
VCC = 5.25 V
10.5
12.5
0.45
V
VOL
VOH1
VOH2
IOL = 12.0 mA, VCC = VCC Min
IOH = -2.5 mA, VCC = VCC Min
IOH = -100 μA. VCC = VCC Min
V
V
V
0.85 x VCC
VCC-0.4
Output High Voltage
Notes for DC characteristics (both tables):
1. The ICC current listed includes both the DC operation current and the frequency dependent component (at 6 MHz).
The frequency component typically is less than 2 mA/MHz, with
2. Maximum ICC specifications are tested with VCC = VCC max.
at VIH.
OE
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = 20μA max at extended temperatures (> +85°C).
(October, 2011, Version 1.9)
18
AMIC Technology, Corp.
A29800 Series
AC Characteristics
Read Only Operations
Parameter Symbols
Description
Test Setup
Speed
Unit
JEDEC
tAVAV
Std
tRC
-55
55
55
-70
70
70
-90
Read Cycle Time (Note 2)
Address to Output Delay
Min.
90
90
ns
ns
tAVQV
tACC
Max.
= VIL
= VIL
CE
OE
tELQV
tGLQV
tCE
Chip Enable to Output Delay
Output Enable to Output Delay
Output Enable Hold Read
Max.
Max.
Min.
Min.
55
30
0
70
30
0
90
35
0
ns
ns
ns
ns
= VIL
OE
tOE
tOEH
Time (Note 2)
Toggle and
Polling
10
10
10
Data
tEHQZ
tGHQZ
tDF
tDF
Chip Enable to Output High Z
Max.
Min.
18
18
20
20
20
20
ns
ns
Output Enable to Output High Z
(Notes 1,2)
tAXQX
tOH
Output Hold Time from Addresses,
0
0
0
ns
or
CE OE
, Whichever Occurs First
Notes:
1. Output driver disable time.
2. Not 100% tested.
(October, 2011, Version 1.9)
19
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Read Only Operation
tRC
Addresses
CE
Addresses Stable
t
ACC
tDF
t
OE
OE
tOEH
WE
tCE
tOH
High-Z
High-Z
Output
Output Valid
RESET
RY/BY
0V
AC Characteristics
Hardware Reset (
Parameter
)
RESET
Description
Test Setup
All Speed Options
Unit
JEDEC
Std
Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
RESET
tREADY
Max
20
μs
Pin Low (Not During Embedded
RESET
Algorithms) to Read or Write (See Note)
tREADY
Max
500
ns
tRP
tRH
tRB
Min
Min
Min
500
50
0
ns
ns
ns
Pulse Width
RESET
RESET
High Time Before Read (See Note)
Recovery Time
RY/
BY
Note: Not 100% tested.
(October, 2011, Version 1.9)
20
AMIC Technology, Corp.
A29800 Series
Timings
RESET
RY/BY
CE, OE
RESET
t
RH
t
RP
t
Ready
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
t
Ready
RY/BY
t
RB
CE, OE
RESET
t
RP
(October, 2011, Version 1.9)
21
AMIC Technology, Corp.
A29800 Series
Temporary Sector Unprotect
Parameter
Description
All Speed Options
Unit
JEDEC
Std
tVIDR
VID Rise and Fall Time (See Note)
Min
Min
500
4
ns
Setup Time for Temporary Sector
RESET
tRSP
μs
Unprotect
Note: Not 100% tested.
Temporary Sector Unprotect Timing Diagram
12V
0 or 5V
RESET
0 or 5V
t
VIDR
tVIDR
Program or Erase Command Sequence
CE
WE
t
RSP
RY/BY
AC Characteristics
Word/Byte Configuration (
Parameter
)
BYTE
Description
All Speed Options
Unit
JEDEC
Std
-55
-70
-90
tELFL/tELFH
Max
Max
Min
5
ns
ns
ns
to
Switching Low or High
BYTE
CE
tFLQZ
tFHQV
20
55
20
70
20
90
Switching Low to Output High-Z
Switching High to Output Active
BYTE
BYTE
(October, 2011, Version 1.9)
22
AMIC Technology, Corp.
A29800 Series
Timings for Read Operations
BYTE
CE
OE
BYTE
t
ELFL
Data Output
(I/O -I/O14
Data Output
(I/O -I/O
BYTE
Switching
I/O -I/O14
0
0
)
0
7)
from word to
byte mode
I/O15
Output
Address Input
I/O15 (A-1)
t
FLQZ
t
ELFH
BYTE
Data Output
(I/O -I/O
Data Output
(I/O0-I/O14)
I/O -I/O14
0
0
7
)
BYTE
Switching
from byte to
word mode
I/O15
Output
Address Input
I/O15 (A-1)
t
FHQV
Timings for Write Operations
BYTE
CE
The falling edge of the last WE signal
WE
BYTE
t
SET
(tAS
)
t
HOLD(tAH)
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
(October, 2011, Version 1.9)
23
AMIC Technology, Corp.
A29800 Series
AC Characteristics
Erase and Program Operations
Parameter
Description
Speed
Unit
JEDEC
tAVAV
Std
tWC
tAS
-55
-70
70
0
-90
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
55
90
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
tAVWL
tWLAX
tDVWH
tWHDX
tAH
45
25
45
30
0
45
45
Data Setup Time
tDS
Data Hold Time
tDH
Output Enable Setup Time
Read Recover Time Before Write
tOES
0
tGHWL
tGHWL
Min.
0
ns
(
high to
low)
WE
OE
tELWL
tWHEH
tCS
Min.
Min.
0
0
ns
ns
Setup Time
Hold Time
CE
CE
tCH
tWLWH
tWHWL
tWP
Write Pulse Width
Min.
Min.
Typ.
30
35
20
7
45
ns
ns
tWPH
Write Pulse Width High
Byte
Byte Programming Operation
(Note 2)
tWHWH1
tWHWH2
tWHWH1
μs
Word
Typ.
12
tWHWH2
tvcs
Sector Erase Operation (Note 2)
VCC Set Up Time (Note 1)
Typ.
Min.
Min
Min
1
50
0
sec
μs
ns
ns
tRB
Recovery Time from RY/
BY
tBUSY
30
30
35
Program/Erase Valid to RY/
Delay
BY
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(October, 2011, Version 1.9)
24
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Program Operation
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC
tAS
Addresses
CE
PA
PA
555h
PA
t
AH
t
CH
tGHWL
OE
tWP
tWHWH1
WE
tCS
tWPH
tDS
tDH
Data
A0h
PD
DOUT
Status
tRB
tBUSY
RY/BY
VCC
t
VCS
Note :
1. PA = program addrss, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
(October, 2011, Version 1.9)
25
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Chip/Sector Erase Operation
Erase Command Sequence (last two cycles)
Read Status Data
t
AS
tWC
SA
555h for chip erase
VA
Addresses
CE
2AAh
VA
tAH
tGHWL
t
CH
OE
tWP
WE
tWPH
t
WHWH2
tCS
tDS
tDH
In
Progress
Data
55h
30h
10h for chip erase
Complete
t
RB
tBUSY
RY/BY
t
VCS
VCC
Note :
1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Illustratin shows device in word mode.
(October, 2011, Version 1.9)
26
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for
Polling (During Embedded Algorithms)
Data
tRC
Addresses
CE
VA
VA
VA
t
ACC
CE
t
tCH
tOE
OE
tDF
tOEH
WE
t
OH
High-Z
Valid Data
I/O
7
Complement
Complement
Status Data
True
True
High-Z
I/O0
- I/O
6
Valid Data
Status Data
tBUSY
RY/BY
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
(October, 2011, Version 1.9)
27
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
tRC
Addresses
CE
VA
VA
VA
VA
t
ACC
t
CE
t
CH
tOE
OE
tDF
tOEH
WE
tOH
I/O6 , I/O2
Valid Status
(first read)
Valid Status
Valid Status
Valid Data
tBUSY
(second read)
(stop togging)
RY/BY
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
(October, 2011, Version 1.9)
28
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for I/O2 vs. I/O6
Enter
Erase
Enter Erase
Suspend Program
Erase
Resume
Embedded
Suspend
Erasing
WE
Erase
Suspend
Program
Erase
Erase
Erase Suspend
Read
Erase Suspend
Read
Erase
Complete
I/O6
I/O2
I/O2
and I/O
6
toggle with OE and CE
Note : Both I/O
6
and I/O
2
toggle with OE or CE. See the text on I/O
6
and I/O
2
in the section "Write Operation Statue" for
more information.
AC Characteristics
Erase and Program Operations
Alternate Controlled Writes
CE
Parameter
Description
Speed
Unit
JEDEC
Std
tWC
tAS
-55
-70
70
0
-90
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
Write Cycle Time (Note 1)
Min.
Min.
Min.
Min.
Min.
Min.
55
90
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
tAH
40
25
45
30
0
45
45
tDS
Data Setup Time
tDH
Data Hold Time
tOES
Output Enable Setup Time
Read Recover Time Before Write
0
tGHEL
tGHEL
Min.
0
ns
(
High to
Low)
WE
OE
tWLEL
tEHWH
tWS
tWH
Min.
Min.
0
0
ns
ns
Setup Time
WE
Hold Time
WE
CE
CE
tELEH
tEHEL
tCP
Min.
Min.
30
20
35
20
45
20
ns
ns
Pulse Width
tCPH
Pulse Width High
Byte
Typ.
Typ.
7
Programming Operation
(Note 2)
tWHWH1
tWHWH1
μs
Word
12
tWHWH2
tWHWH2
sec
Sector Erase Operation (Note 2)
Typ.
1
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
(October, 2011, Version 1.9)
29
AMIC Technology, Corp.
A29800 Series
Timing Waveforms for Alternate
Controlled Write Operation (
=VIH on A29800)
RESET
CE
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
Data Polling
PA
Addresses
tWC
tAS
tAH
tWH
WE
tGHEL
OE
tWHWH1 or 2
tCP
tBUSY
tCPH
tDH
CE
tWS
tDS
Data
DOUT
I/O7
tRH
A0 for program
55 for erase
PD for program
30 for sector erase
10 for chip erase
RESET
RY/BY
Note :
1. PA = Program Address, PD = Program Data, SA = Sector Address, I/O7 = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Erase and Programming Performance
Parameter
Sector Erase Time
Typ. (Note 1)
Max. (Note 2)
Unit
sec
sec
μs
Comments
1.0
11
7
8
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time (Note 3)
Byte Programming Time
Word Programming Time
300
500
Excludes system-level
overhead (Note 5)
12
7.2
6.3
μs
Chip Programming Time
(Note 3)
Byte Mode
Word Mode
21.6
18.6
sec
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 10,000 cycles. Additionally, programming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V (4.75V for -55), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set I/O5 = 1. See the section on I/O5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.
(October, 2011, Version 1.9)
30
AMIC Technology, Corp.
A29800 Series
Latch-up Characteristics
Description
Min.
-1.0V
Max.
VCC+1.0V
+100 mA
12.5V
Input Voltage with respect to VSS on all I/O pins
VCC Current
-100 mA
-1.0V
Input voltage with respect to VSS on all pins except I/O pins
(including A9,
and
)
RESET
OE
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time.
TSOP and SOP Pin Capacitance
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
VIN=0
Typ.
6
Max.
Unit
pF
CIN
COUT
CIN2
7.5
12
9
Output Capacitance
VOUT=0
VIN=0
8.5
7.5
pF
Control Pin Capacitance
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
Data Retention
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Minimum Pattern Data Retention Time
20
125°C
(October, 2011, Version 1.9)
31
AMIC Technology, Corp.
A29800 Series
Test Conditions
Test Specifications
Test Condition
-55
All others
Unit
Output Load
1 TTL gate
100
Output Load Capacitance, CL(including jig capacitance)
Input Rise and Fall Times
30
5
pF
ns
V
20
Input Pulse Levels
0.0 - 3.0
1.5
0.45 - 2.4
0.8, 2.0
0.8, 2.0
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
V
Test Setup
5.0 V
2.7 KΩ
Device
Under
Test
Diodes = IN3064 or Equivalent
CL
6.2 KΩ
(October, 2011, Version 1.9)
32
AMIC Technology, Corp.
A29800 Series
Ordering Information
Top Boot Sector Flash
Active Read
Current
Typ. (mA)
Program/Erase
Current
Access Time
Standby Current
Part No.
Package
(ns)
Typ. (μA)
Typ. (mA)
A29800TM-55F
A29800TM-55IF
A29800TV-55F
A29800TV-55IF
A29800TM-70F
A29800TM-70IF
A29800TV-70F
A29800TV-70IF
A29800TM-90F
A29800TM-90IF
A29800TV-90F
A29800TV-90IF
44Pin Pb-Free SOP
44Pin Pb-Free SOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
44Pin Pb-Free SOP
44Pin Pb-Free SOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
44Pin Pb-Free SOP
44Pin Pb-Free SOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
55
20
20
20
30
30
30
1
1
1
70
90
Note: -I is for industrial operating temperature range: -40°C to +85°C
(October, 2011, Version 1.9)
33
AMIC Technology, Corp.
A29800 Series
Bottom Boot Sector Flash
Active Read
Current
Typ. (mA)
Program/Erase
Current
Access Time
Standby Current
Part No.
Package
(ns)
Typ. (μA)
Typ. (mA)
A29800UM-55F
A29800UM-55IF
A29800UV-55F
A29800UV-55IF
A29800UM-70F
A29800UM-70IF
A29800UV-70F
A29800UV-70IF
A29800UM-90F
A29800UM-90IF
A29800UV-90F
A29800UV-90IF
44Pin Pb-Free SOP
44Pin Pb-Free SOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
44Pin Pb-Free SOP
44Pin Pb-Free SOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
44Pin Pb-Free SOP
44Pin Pb-Free SOP
48Pin Pb-Free TSOP
48Pin Pb-Free TSOP
55
20
20
20
30
30
30
1
1
1
70
90
Note: -I is for industrial operating temperature range: -40°C to +85°C
(October, 2011, Version 1.9)
34
AMIC Technology, Corp.
A29800 Series
Package Information
SOP 44L Outline Dimensions
unit: inches/mm
23
44
Gauge Plane
0.010"
θ
L
1
22
b
Detail F
D
L
1
S
e
y
Seating Plane
See Detail F
Dimensions in inches
Dimensions in mm
Symbol
Min
Nom
-
Max
0.118
-
Min
Nom
-
Max
3.00
-
A
A1
A2
b
-
-
0.10
2.62
0.33
0.18
-
0.004
-
-
0.103
0.106
0.016
0.008
1.122
0.496
0.050
0.631
0.032
0.0675
-
0.109
0.020
0.010
1.130
0.500
-
2.69
0.40
0.20
28.50
12.60
1.27
16.03
0.80
1.71
-
2.77
0.50
0.25
28.70
12.70
-
0.013
C
D
E
0.007
-
0.490
12.45
-
e
-
HE
L
0.620
0.643
0.040
-
15.75
0.61
-
16.33
1.02
-
0.024
L1
S
-
-
0.045
0.004
8°
-
1.14
0.10
8°
y
-
-
-
-
-
-
θ
0°
0°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(October, 2011, Version 1.9)
35
AMIC Technology, Corp.
A29800 Series
Package Information
TSOP 48L (Type I) Outline Dimensions
unit: inches/mm
D
D1
1
48
D
24
25
θ
L
Detail "A"
Detail "A"
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
Nom
Max
A
A1
A2
b
-
-
0.047
0.006
0.042
0.011
0.008
0.795
0.728
0.476
-
-
1.20
0.15
0.002
0.037
0.007
0.004
0.779
0.720
-
0.05
0.94
0.18
0.12
19.80
18.30
-
-
1.00
0.039
0.009
-
1.06
0.22
0.27
c
-
0.20
D
D1
E
e
0.787
0.724
0.472
0.020 BASIC
20.00
18.40
12.00
0.50 BASIC
0.60
20.20
18.50
12.10
L
0.020
0.024 0.0275
0.011 Typ.
0.50
0.70
S
y
0.28 Typ.
-
-
-
-
0.004
8°
-
0.10
8°
0°
0°
-
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(October, 2011, Version 1.9)
36
AMIC Technology, Corp.
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