A43E2632V-95I [AMICC]
1M X 16 Bit X 4 Banks Synchronous DRAM; 1M ×16位×4银行同步DRAM
| 型号： | A43E2632V-95I |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | 1M X 16 Bit X 4 Banks Synchronous DRAM |
| 文件： | 总42页 (文件大小：502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A43L2616B
1M X 16 Bit X 4 Banks Synchronous DRAM
Document Title
1M X 16 Bit X 4 Banks Synchronous DRAM
Revision History
Rev. No. History
Issue Date
Remark
0.0
0.1
Initial issue
August 24, 2006
February 14, 2007
Preliminary
Change ICC1 to 70mA
Change ICC6 to 1.5mA
Add 54B Pb-Free CSP package type
Final version release
0.2
1.0
1.1
1.2
1.3
March 15, 2007
April 3, 2007
Final
Change BS0 to BA0, BS1 to BA1
August 15, 2007
February 15, 2008
December 16, 2009
Add part numbering scheme
Erase 54B CSP package type
(December, 2009, Version 1.3)
AMIC Technology, Corp.
A43L2616B
1M X 16 Bit X 4 Banks Synchronous DRAM
Feature
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
Four banks / Pulse RAS
64ms refresh period (4K cycle)
Commercial Temperature Operation : 0°C~70°C
Industrial Temperature Operation : -40°C~85°C for –U
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
grade
All inputs are sampled at the positive going edge of the
system clock
Clock Frequency: 166MHz @ CL=3
143MHz @ CL=3
Available in 54-pin TSOP(II) package
Package is available to lead free (-F series)
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A43L2616B is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 X 1,048,576 words by
16 bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock.
I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth,
high
performance
memory
system
applications.
Pin Configuration
TSOP (II)
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
A43L2616BV
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
(December, 2009, Version 1.3)
1
AMIC Technology, Corp.
A43L2616B
Block Diagram
LWE
Data Input Register
Bank Select
DQM
1M X 16
1M X 16
1M X 16
1M X 16
CLK
ADD
DQi
Column Decoder
Latency & Burst Length
LRAS
Programming Register
LWCBR
LCAS
DQM
LRAS LCBR LWE
Timing Register
DQM
CLK
CKE
CS
RAS
CAS
WE
(December, 2009, Version 1.3)
2
AMIC Technology, Corp.
A43L2616B
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Row / Column addresses are multiplexed on the same pins.
Row address : RA0~RA11, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
A0~A11
Address
BA0, BA1
Bank Select Address
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
RAS
CAS
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Column Address
Strobe
Write Enable
Enables write operation and Row precharge.
WE
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data Input/Output
Mask
L(U)DQM
DQ0-15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
Power
Supply/Ground
VDD/VSS
Power Supply: +3.3V±0.3V/Ground
Data Output
Power/Ground
VDDQ/VSSQ
NC/RFU
Provide isolated Power/Ground to DQs for improved noise immunity.
No Connection
(December, 2009, Version 1.3)
3
AMIC Technology, Corp.
A43L2616B
Absolute Maximum Ratings*
*Comments
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V
Storage Temperature (TSTG) . . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . .1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for extended
periods of time could affect device reliability.
Capacitance (TA=25°C, f=1MHz)
Parameter
Input Capacitance
Symbol
CI1
Condition
A0 to A11, BA0, BA1
Min
2.5
2.5
Typ
Max
3.8
Unit
pF
CI2
CLK, CKE,
DQM
,
,
, WE ,
3.8
pF
CS RAS CAS
Data Input/Output Capacitance
CI/O
DQ0 to DQ15
4
6.5
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V, TA = 0ºC to +70ºC or TA = -40ºC to +85ºC)
Parameter
Supply Voltage
Symbol
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
VDD,VDDQ
3.3
3.6
Input High Voltage
VIH
VIL
VOH
VOL
IIL
3.0
VDD+0.3
V
Input Low Voltage
0
-
0.8
-
V
Note 1
IOH = -2mA
IOL = 2mA
Note 2
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Output Loading Condition
V
-
0.4
5
V
-5
-
μA
μA
IOL
-5
-
5
Note 3
See Figure 1
Note: 1. VIL (min) = -1.5V AC (pulse width ≤ 5ns).
2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V ≤ Vout ≤ VDD
(December, 2009, Version 1.3)
4
AMIC Technology, Corp.
A43L2616B
Decoupling Capacitance Guide Line
Recommended decoupling capacitance added to power line at board.
Parameter
Symbol
Value
Unit
μF
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
CDC1
CDC2
0.1 + 0.01
0.1 + 0.01
μF
Note: 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
DC Electrical Characteristics
(Recommended operating condition unless otherwise noted, TA = 0°C to 70°C TA = -40ºC to +85ºC)
Speed
Symbol
Parameter
Test Conditions
Unit Notes
-6
-7
Operating Current
(One Bank Active)
Burst Length = 1
Icc1
70
70
mA
mA
1
tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA
Icc2 P
CKE ≤ VIL(max), tCC = 15ns
2
1
Precharge Standby Current
in power-down mode
Icc2 PS
CKE ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
ICC2N
20
15
Precharge Standby Current
in non power-down mode
Input signals are changed one time during 30ns
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable.
ICC2NS
Active Standby current in
non power-down mode
(One Bank Active)
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3N
ICC4
30
mA
mA
Operating Current
(Burst Mode)
IOL = 0mA, Page Burst
All bank Activated, tCCD = tCCD (min)
100
130
100
130
1
2
ICC5
ICC6
Refresh Current
mA
mA
tRC ≥ tRC (min)
CKE ≤ 0.2V
Self Refresh Current
1.5
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).
2. Refresh period is 64ms. Addresses are changed only one time during tCC(min).
(December, 2009, Version 1.3)
5
AMIC Technology, Corp.
A43L2616B
AC Operating Test Conditions
(VDD = 3.3V ±0.3V, TA = 0°C to +70°C or TA = -40ºC to +85ºC)
Parameter
Value
AC input levels
VIH/VIL = 2.4V/0.4V
1.4V
Input timing measurement reference level
Input rise and all time (See note3)
Output timing measurement reference level
Output load condition
tr/tf = 1ns/1ns
1.4V
See Fig.2
3.3V
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
VTT =1.4V
1200Ω
50Ω
Output
ZO=50Ω
OUTPUT
50pF
870Ω
50pF
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
AC Characteristics
(AC operating conditions unless otherwise noted)
-6
-7
Unit
Note
Symbol
tCC
Parameter
CAS Latency
Min
6
Max
Min
7
Max
3
2
3
2
3
2
CLK cycle time
1000
1000
ns
ns
1
10
-
10
-
5
6
6
6
tSAC
CLK to valid Output delay
1,2
-
-
2.5
3
3
tOH
tCH
Output data hold time
CLK high pulse width
-
-
-
-
ns
ns
2
3
3
2.5
3
tCL
tSS
CLK low pulse width
Input setup time
2.5
1.5
1
-
-
-
3
2
1
-
-
-
ns
ns
ns
ns
3
3
3
2
tSH
tSLZ
Input hold time
CLK to output in Low-Z
1
-
-
1
-
-
3
2
5
6
6
6
tSHZ
CLK to output In Hi-Z
ns
-
-
*All AC parameters are measured from half to half.
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
(December, 2009, Version 1.3)
6
AMIC Technology, Corp.
A43L2616B
Operating AC Parameter
(AC operating conditions unless otherwise noted)
Version
Symbol
Parameter
Unit
Note
-6
12
18
-7
14
20
tRRD(min)
tRCD(min)
Row active to row active delay
ns
ns
1
1
RAS to
delay
CAS
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
Row precharge time
Row active time
18
42
20
42
ns
ns
μs
ns
1
1
100
Row cycle time
60
63
1
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
Last data in new col. Address delay
Last data in row precharge
6
12
6
7
14
7
ns
ns
ns
ns
2
2
2
Last data in to burst stop
Col. Address to col. Address delay
6
7
CAS Latency = 3
CAS Latency = 2
2
1
Number of valid output data
ea
3
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. In case of row precharge interrupt, auto precharge and read burst stop.
(December, 2009, Version 1.3)
7
AMIC Technology, Corp.
A43L2616B
Simplified Truth Table
Command
CKEn-1 CKEn CS RAS
DQM BA0 A10 A9~A0, Notes
CAS
L
WE
L
BA1 /AP
A11
Register
Mode Register Set
Auto Refresh
1,2
H
H
X
L
L
X
X
OP CODE
3
3
3
Refresh
H
L
L
L
L
L
H
H
X
Entry
Self
H
H
Refresh
Exit
L
H
X
X
X
X
H
L
X
L
X
H
X
H
3
4
Bank Active & Row Addr.
H
V
V
Row Addr.
Read &
Column Addr.
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
Column
Addr.
4
H
X
L
H
L
H
X
H
L
4,5
4
Write &
Column
Addr.
H
H
X
X
L
L
H
H
L
L
L
X
X
V
Column Addr.
H
4,5
Burst Stop
Precharge
H
X
Bank Selection
Both Banks
V
X
L
H
X
L
L
H
L
X
X
H
L
H
X
L
H
X
X
H
X
V
X
X
H
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
Entry
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
Exit
Entry
H
H
L
Precharge Power Down Mode
Exit
L
H
H
H
X
X
V
X
H
DQM
X
X
6
L
H
X
H
X
No Operation Command
H
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note : 1. OP Code: Operand Code
A0~A11, BA0, BA1: Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
4. BA0, BA1 : Bank select address.
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read write command cannot be issued.
Another bank read write command can be issued at every burst length.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) but
masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
(December, 2009, Version 1.3)
8
AMIC Technology, Corp.
A43L2616B
Mode Register Filed Table to Program Modes
Register Programmed with MRS
Address
BA0, BA1
A11, A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
RFU
RFU
W.B.L
TM
CAS Latency
BT
Burst Length
(Note 1)
(Note 2)
Test Mode
Type
CAS Latency
A6 A5 A4 Latency
Burst Type
Burst Length
A8 A7
A3
Type
A2 A1 A0
BT=0
BT=1
0
0
1
1
0
1
0
1
Mode Register Set
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
-
0
1
Sequential
Interleave
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Vendor
Use
2
Only
3
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
256(Full) Reserved
Write Burst Length
Length
A9
0
Burst
1
Single Bit
Power Up Sequence
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200μs.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.
(December, 2009, Version 1.3)
9
AMIC Technology, Corp.
A43L2616B
Burst Sequence (Burst Length = 4)
Initial address
Sequential
Interleave
A1
0
A0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
Burst Sequence (Burst Length = 8)
Initial address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
7
1
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
6
7
0
1
2
3
4
0
1
2
3
4
5
6
0
3
2
5
4
7
6
(December, 2009, Version 1.3)
10
AMIC Technology, Corp.
A43L2616B
Device Operations
Clock (CLK)
Power-Up
The following sequence is recommended for POWER UP
1. Power must be applied to either CKE and DQM inputs to
pull them high and other pins are NOP condition at the
inputs before or along with VDD (and VDDQ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum
pause of 200 microseconds is required with inputs in
NOP condition.
The clock input is used as the reference for all SDRAM
operations. All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high)
for the duration of set up and hold time around positive
edge of the clock for proper functionality and ICC
specifications.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize
the internal circuitry.
Clock Enable (CKE)
5. Perform a MODE REGISTER SET cycle to program the
CAS latency, burst length and burst type as the default
value of mode register is undefined.
The clock enable (CKE) gates the clock onto SDRAM. If
CKE goes low synchronously with clock (set-up and hold
time same as other inputs), the internal clock is suspended
form the next clock cycle and the state of output and burst
address is frozen as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes
low. When both banks are in the idle state and CKE goes
low synchronously with clock, the SDRAM enters the power
down mode form the next clock cycle. The SDRAM
remains in the power down mode ignoring the other inputs
as long as CKE remains low. The power down exit is
synchronous as the internal clock is suspended. When
CKE goes high at least “tSS + 1 CLOCK” before the high
going edge of the clock, then the SDRAM becomes active
from the same clock edge accepting all the input
commands.
At the end of one clock cycle from the mode register set
cycle, the device is ready for operation.
When the above sequence is used for Power-up, all the
out-puts will be in high impedance state. The high
impedance of outputs is not guaranteed in any other
power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
Mode Register Set (MRS)
The mode register stores the data for controlling the
various operation modes of SDRAM. It programs the CAS
latency, addressing mode, burst length, test mode and
various vendor specific options to make SDRAM useful for
variety of different applications. The default value of the
mode register is not defined, therefore the mode register
must be written after power up to operate the SDRAM. The
Bank Select (BA0, BA1)
This SDRAM is organized as 4 independent banks of
1,048,576 words X 16 bits memory arrays. The BA0, BA1
mode register is written by asserting low on
,
,
CS RAS
, (The SDRAM should be in active mode with
WE
inputs is latched at the time of assertion of
and
CAS
RAS
CAS
to select the bank to be used for the operation. The bank
select BA0, BA1 is latched at bank activate, read, write
mode register set and precharge operations.
CKE already high prior to writing the mode register). The
state of address pins A0~A11, BA0 and BA1 in the same
cycle as
,
,
,
going low is the data
WE
CS RAS CAS
written in the mode register. One clock cycle is required to
complete the write in the mode register. The mode register
contents can be changed using the same command and
clock cycle requirements during operation as long as both
banks are in the idle state. The mode register is divided
into various fields depending on functionality. The burst
length field uses A0~A2, burst type uses A3, addressing
mode uses A4~A6, A7~A8, A11, BA0 and BA1 are used for
vendor specific options or test mode. And the write burst
length is programmed using A9. A7~A8, A11, BA0 and BA1
must be set to low for normal SDRAM operation.
Address Input (A0 ~ A11)
The 20 address bits required to decode the 262,144 word
locations are multiplexed into 12 address input pins
(A0~A11). The 12 bit row address is latched along with
, BA0 and BA1 during bank activate command. The 8
RAS
bit column address is latched along with
and BA1during read or write command.
,
, BA0
WE
CAS
NOP and Device Deselect
Refer to table for specific codes for various burst length,
addressing modes and CAS latencies.
When
,
and
are high, the SDRAM
WE
CAS
RAS
performs no operation (NOP). NOP does not initiate any
new operation, but is needed to complete operations which
require more than single clock like bank activate, burst
read, auto refresh, etc. The device deselect is also a NOP
and is entered by asserting
high.
high disables
CS
CS
the command decoder so that
,
and
, and
WE
CAS
RAS
all the address inputs are ignored.
(December, 2009, Version 1.3)
11
AMIC Technology, Corp.
A43L2616B
Device Operations (continued)
Bank Activate
Burst Write
The burst write command is similar to burst read
command, and is used to write data into the SDRAM
consecutive clock cycles in adjacent addresses depending
on burst length and burst sequence. By asserting low on
The bank activate command is used to select a random
row in an idle bank. By asserting low on
and
RAS
with desired row and bank addresses, a row access is
CS
initiated. The read or write operation can occur after a time
delay of tRCD(min) from the time of bank activation.
tRCD(min) is an internal timing parameter of SDRAM,
therefore it is dependent on operating clock frequency. The
minimum number of clock cycles required between bank
activate and read or write command should be calculated
by dividing tRCD(min) with cycle time of the clock and then
rounding off the result to the next higher integer. The
SDRAM has two internal banks on the same chip and
shares part of the internal circuitry to reduce chip area,
therefore it restricts the activation of both banks
immediately. Also the noise generated during sensing of
each bank of SDRAM is high requiring some time for
power supplies recover before the other bank can be
sensed reliably. tRRD(min) specifies the minimum time
required between activating different banks. The number of
clock cycles required between different bank activation
must be calculated similar to tRCD specification. The
minimum time required for the bank to be active to initiate
sensing and restoring the complete row of dynamic cells is
determined by tRAS(min) specification before a precharge
command to that active bank can be asserted. The
maximum time any bank can be in the active state is
determined by tRAS(max). The number of cycles for both
tRAS(min) and tRAS(max) can be calculated similar to tRCD
specification.
,
and
with valid column address, a write
WE
CS CAS
burst is initiated. The data inputs are provided for the initial
address in the same clock cycle as the burst write
command. The input buffer is deselected at the end of the
burst length, even though the internal writing may not have
been completed yet. The writing can not complete to burst
length. The burst write can be terminated by issuing a burst
read and DQM for blocking data inputs or burst write in the
same or the other active bank. The burst stop command is
valid only at full page burst length where the writing
continues at the end of burst and the burst is wrap around.
The write burst can also be terminated by using DQM for
blocking data and precharging the bank “tRDL” after the last
data input to be written into the active row. See DQM
OPERATION also.
DQM Operation
The DQM is used to mask input and output operation. It
works similar to
during read operation and inhibits
OE
writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in the read cycle and
occurs in the same cycle during write cycle. DQM
operation is synchronous with the clock, therefore the
masking occurs for a complete cycle. The DQM signal is
important during burst interrupts of write with read or
precharge in the SDRAM. Due to asynchronous nature of
the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst
write is not required.
Burst Read
The burst read command is used to access burst of data
on consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low
on
and
with
being high on the positive
WE
CS
CAS
Precharge
edge of the clock. The bank must be active for at least
tRCD(min) before the burst read command is issued. The
first output appears CAS latency number of clock cycles
after the issue of burst read command. The burst length,
burst sequence and latency from the burst read command
is determined by the mode register which is already
programmed. The burst read can be initiated on any
column address of the active row. The address wraps
around if the initial address does not start from a boundary
such that number of outputs from each I/O are equal to the
burst length programmed in the mode register. The output
goes into high-impedance at the end of the burst, unless a
new burst read was initiated to keep the data output
gapless. The burst read can be terminated by issuing
another burst read or burst write in the same bank or the
other active bank or a precharge command to the same
bank. The burst stop command is valid at every page burst
length.
The precharge operation is performed on an active bank by
asserting low on
,
,
and A10/AP with valid
WE
CS RAS
BA of the bank to be precharged. The precharge command
can be asserted anytime after tRAS(min) is satisfied from
the bank activate command in the desired bank. “tRP” is
defined as the minimum time required to precharge a bank.
The minimum number of clock cycles required to complete
row precharge is calculated by dividing “tRP” with clock
cycle time and rounding up to the next higher integer. Care
should be taken to make sure that burst write is completed
or DQM is used to inhibit writing before precharge
command is asserted. The maximum time any bank can be
active is specified by tRAS(max). Therefore, each bank has
to be precharged within tRAS(max) from the bank activate
command. At the end of precharge, the bank enters the
idle state and is ready to be activated again.
Entry to Power Down, Auto refresh, Self refresh and Mode
register Set etc, is possible only when both banks are in
idle state.
(December, 2009, Version 1.3)
12
AMIC Technology, Corp.
A43L2616B
cycle). The time required to complete the auto refresh
operation is specified by “tRC(min)”. The minimum number
of clock cycles required can be calculated by driving “tRC”
with clock cycle time and then rounding up to the next
higher integer. The auto refresh command must be
followed by NOP’s until the auto refresh operation is
completed. Both banks will be in the idle state at the end of
auto refresh operation. The auto refresh is the preferred
refresh mode when the SDRAM is being used for normal
data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 4096 auto refresh cycles once
in 64ms.
Device Operations (continued)
Auto Precharge
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the
timing to satisfy tRAS(min) and “tRP” for the programmed
burst length and CAS latency. The auto precharge
command is issued at the same time as burst read or burst
write by asserting high on A10/AP. If burst read or burst
write command is issued with low on A10/AP, the bank is
left active until a new command is asserted. Once auto
precharge command is given, no new commands are
possible to that particular bank until the bank achieves idle
state.
Self Refresh
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
Four Banks Precharge
Both banks can be precharged at the same time by using
Precharge all command. Asserting low on
,
and
CS RAS
with high on A10/AP after both banks have satisfied
WE
tRAS(min) requirement, performs precharge on both banks.
At the end of tRP after performing precharge all, both
banks are in idle state.
The self refresh mode is entered from all banks idle state
by asserting low on
,
,
and CKE with high
CS RAS CAS
on
. Once the self refresh mode is entered, only CKE
WE
Auto Refresh
state being low matters, all the other inputs including clock
are ignored to remain in the self refresh.
The storage cells of SDRAM need to be refreshed every
64ms to maintain data. An auto refresh cycle accomplishes
refresh of a single row of storage cells. The internal
counter increments automatically on every auto refresh
cycle to refresh all the rows. An auto refresh command is
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of “tRC” before the SDRAM
reaches idle state to begin normal operation. If the system
uses burst auto refresh during normal operation, it is
recommended to used burst 4096 auto refresh cycles
immediately after exiting self refresh.
issued by asserting low on
,
and
with high
CS RAS
CAS
on CKE and
. The auto refresh command can only be
WE
asserted with both banks being in idle state and the device
is not in power down mode (CKE is high in the previous
(December, 2009, Version 1.3)
13
AMIC Technology, Corp.
A43L2616B
Basic feature And Function Descriptions
1. CLOCK Suspend
1) Click Suspended During Write (BL=4)
2) Clock Suspended During Read (BL=4)
CLK
CMD
CKE
WR
RD
Masked by CKE
Masked by CKE
Internal
CLK
DQ(CL2)
DQ(CL3)
D0
D0
D1
D1
D2
D2
D3
D3
Q0
Q1
Q0
Q2
Q1
Q3
Q2
Q3
Not Written
Suspended Dout
Note: CLK to CLK disable/enable=1 clock
2. DQM Operation
2) Read Mask (BL=4)
1) Write Mask (BL=4)
CLK
CMD
WR
RD
DQM
Masked by CKE
D3
Masked by CKE
Q2
Hi-Z
Hi-Z
DQ(CL2)
DQ(CL3)
D0
D0
D1
D1
Q0
Q3
Q2
D3
Q1
Q3
DQM to Data-in Mask = 0CLK
DQM to Data-out Mask = 2
2) Read Mask (BL=4)
CLK
CMD
CKE
RD
DQM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Q0
Q2
Q1
Q4
Q3
Q6
Q5
Q7
Q6
Q8
Q7
DQ(CL2)
DQ(CL3)
Hi-Z
* Note : 1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.
2. DQM masks both data-in and data-out.
(December, 2009, Version 1.3)
14
AMIC Technology, Corp.
A43L2616B
3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4)Note 1
CLK
CMD
RD
A
RD
B
ADD
DQ(CL2)
DQ(CL3)
QA0 QB0 QB1 QB2 QB3
QA0 QB0 QB1 QB2 QB3
t
CCD
Note2
2) Write interrupted by Write (BL =2)
3) Write interrupted by Read (BL =2)
CLK
WR WR
WR
RD
CMD
t
CCD
tCCD
Note2
Note2
ADD
DQ
A
B
A
B
DA0 DB0 DB1
DQ(CL2)
DQ(CL3)
DA0
QB0 QB1
t
CDL
Note3
DA0
QB0 QB1
t
CDL
Note3
Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.
By “ Interrupt”, to stop burst read/write by access; read, write and block write.
CAS
2. tCCD :
CAS
to
delay. (=1CLK)
CAS
CAS
3. tCDL : Last data in to new column address delay. (= 1CLK).
(December, 2009, Version 1.3)
15
AMIC Technology, Corp.
A43L2616B
4. CAS Interrupt (II) : Read Interrupted Write & DQM
(1) CL=2, BL=4
CLK
i) CMD
RD
RD
WR
D0
DQM
DQ
ii) CMD
D1
D2
D3
D2
WR
DQM
DQ
Hi-Z
D0
D1
D3
D2
D1
RD
RD
WR
iii) CMD
DQM
DQ
Hi-Z
D0
D1
D3
D2
iv) CMD
WR
DQM
DQ
Hi-Z
Note 1
Q0
D0
D3
(2) CL=3, BL=4
CLK
i) CMD
DQM
RD
RD
RD
RD
WR
D0
DQ
D1
D2
D3
D2
ii) CMD
WR
DQM
DQ
D0
D1
D3
D2
iii) CMD
WR
DQM
DQ
D0
D1
D3
D2
D1
iv) CMD
WR
DQM
DQ
Hi-Z
D0
D1
D3
D2
v) CMD
RD
WR
DQM
DQ
Hi-Z
Q0
D0
D3
Note 2
* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.
(December, 2009, Version 1.3)
16
AMIC Technology, Corp.
A43L2616B
5. Write Interrupted by Precharge & DQM
CLK
Note 2
CMD
WR
D0
PRE
Note 1
DQM
DQ
D1
D2 D3
Masked by DQM
Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
6. Precharge
1 ) N o rm a l W rite (B L = 4 )
C L K
C M D
D Q
W R
D 0
P R E
D 1
D 2
D 3
tR D L
2 ) R e a d (B L = 4 )
C L K
C M D
R D
P R E
Q 2
D Q (C L 2 )
Q 0
Q 1
Q 0
Q 3
Q 2
D Q (C L 3 )
Q 1
Q 3
7. Auto Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
WR
D0
D1
D2
D3
Note 1
Auto Precharge Starts
2) Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
Q0
Q1
Q0
Q2
Q1
Q3
Q2
Q3
Note 1
Auto Precharge Starts
* Note : 1. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other active bank can be issued from this point.
At burst read/write with auto precharge,
interrupt of the same/another bank is illegal.
CAS
(December, 2009, Version 1.3)
17
AMIC Technology, Corp.
A43L2616B
8. Burst Stop & Interrupted by Precharge
1) Normal Write (BL=4)
CLK
2) Write Burst Stop (BL=8)
CLK
CMD
CMD
WR
PRE
WR
STOP
DQM
DQ
DQM
DQ
D0
D1
D2
D3
D0
D1
D2
D3
D4
D5
tRDL Note 1
t
BDL Note 2
1) Read Interrupted by Precharge (BL=4)
CLK
4) Read Burst Stop (BL=4)
CLK
CMD
CMD
RD
PRE
Q0
RD
STOP
Q0
Note 3
1
1
DQ(CL2)
DQ(CL3)
Q1
Q0
DQ(CL2)
DQ(CL3)
Q1
Q0
2
2
Q1
Q1
9. MRS
Mode Register Set
CLK
Note 1
PRE
MRS
ACT
CMD
t
RP
2CLK
Note : 1. tRDL: 1CLK
2. tBDL: 1CLK; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.
4. PRE: All banks precharge if necessary.
MRS can be issued only when all banks are in precharged state.
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
2) Power Down (=Precharge Power Down) Exit
CLK
CKE
CLK
CKE
t
SS
t
SS
Note 2
Note 1
Internal
CLK
Internal
CLK
NOP
ACT
RD
CMD
CMD
(December, 2009, Version 1.3)
18
AMIC Technology, Corp.
A43L2616B
11. Auto Refresh & Self Refresh
Note 3
1) Auto Refresh
CLK
Note 4
Note 5
CMD
PRE
AR
CMD
CKE
tRP
tRC
Note 6
2) Self Refresh
CLK
Note 4
CMD
CKE
PRE
SR
CMD
tRP
tRC
* Note : 1. Active power down : one or more bank active state.
2. Precharge power down : both bank precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after Auto Refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is LOW.
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
During tRC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.
(December, 2009, Version 1.3)
19
AMIC Technology, Corp.
A43L2616B
12. About Burst Type Control
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=1,2,4,8 and full page wrap around.
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting
Sequential counting
Basic
MODE
Interleave counting
Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of convention DRAM.
Random
MODE
Random column Access
tCCD = 1 CLK
13. About Burst Length Control
At MRS A2,1,0 = “000”.
At auto precharge, tRAS should not be violated.
1
Basic
MODE
At MRS A2,1,0 = “001”.
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = “010”
2
4
8
At MRS A2,1,0 = “011”.
At MRS A9=”1”.
Read burst = 1,2,4,8, full page/write Burst =1
At auto precharge of write, tRAS should not be violated.
Before the end of burst, Row precharge command of the same bank
Stops read/write burst with Row precharge.
Special
BRSW
MODE
Interrupt
RAS
(Interrupted by Precharge)
tRDL=1 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively
Interrupt
MODE
During read/write burst with auto precharge,
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst or block write.
interrupt cannot be issued.
RAS
Interrupt
CAS
During read/write burst with auto precharge,
interrupt can not be issued.
CAS
(December, 2009, Version 1.3)
20
AMIC Technology, Corp.
A43L2616B
Power On Sequence & Auto Refresh
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
High level is necessary
tRP
tRC
RAS
CAS
ADDR
KEY
Ra
BA0, BA1
A10/AP
BA
Ra
WE
DQM
DQ
High level is necessary
High-Z
Precharge
(All Banks)
Auto Refresh
Auto Refresh
Mode Regiser Set
Row Active
(A-Bank)
: Don't care
(December, 2009, Version 1.3)
21
AMIC Technology, Corp.
A43L2616B
Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1
tCH
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
tCL
tCC
High
tRAS
tRC
tSH
*Note 1
CS
tSS
tRCD
tRP
tSH
RAS
tSS
tCCD
tSH
CAS
ADDR
tSS
tSH
tSS
Ra
Ca
Cb
Cc
Rb
tSS
tSH
*Note 2,3
*Note 2,3
*Note 2,3 *Note 4
*Note 2
*Note 2
BA0, BA1
A10/AP
BA
BA
BA
BA
BA
BA
*Note 3
*Note 3
*Note 3 *Note 4
Ra
Rb
tSH
WE
tSS
tSS
tSH
tSH
DQM
DQ
tRAC
tSAC
tSLZ
Qa
Db
Qc
tSS
tOH
tSHZ
Read
Write
Row Active
Read
Row Active
Precharge
: Don't care
(December, 2009, Version 1.3)
22
AMIC Technology, Corp.
A43L2616B
* Note : 1. All inputs can be don’t care when
is high at the CLK high going edge.
CS
2. Bank active & read/write are controlled by BA0, BA1.
BA1
BA0
Active & Read/Write
Bank A
0
0
1
1
0
1
0
1
Bank B
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP BA1
BA0
0
Operation
0
0
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Disable auto precharge, leave bank C active at end of burst.
Disable auto precharge, leave bank D active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
Enable auto precharge, precharge bank C at end of burst.
Enable auto precharge, precharge bank D at end of burst.
1
0
1
0
1
0
0
1
0
1
1
1
0
1
1
4. A10/AP and BA0, BA1 control bank precharge when precharge command is asserted.
A10/AP
BA1
0
BA0
0
Precharge
Bank A
0
0
0
0
1
0
1
Bank B
1
0
Bank C
1
1
Bank D
X
X
All Banks
(December, 2009, Version 1.3)
23
AMIC Technology, Corp.
A43L2616B
Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
*Note 1
tRC
CS
tRCD
RAS
CAS
*Note 2
ADDR
Ra
Ca0
Rb
Cb0
BA0
BA1
A10/AP
WE
Ra
Rb
DQM
tOH
Qa0
DQ
(CL = 2)
Qa1
Qa2
Qa3
Db0
Db0
Db1
Db2
Db3
tRAC
*Note 4
tRDL
tSAC
tSHZ
*Note 3
tOH
DQ
(CL = 3)
Qa0
Qa1
Qa2
Qa3
Db1
Db2
Db3
tRAC
*Note 4
tRDL
tSHZ
tSAC
*Note 3
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row enters precharge.
Last valid output will be Hi-Z after tSHZ from the clock.
3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)
(December, 2009, Version 1.3)
24
AMIC Technology, Corp.
A43L2616B
Page Read & Write Cycle at Same Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
tRCD
RAS
CAS
*Note 2
ADDR
BA0
Ra
Ca
Cb
Cc
Cd
BA1
A10/AP
WE
Ra
tRDL
tCDL
*Note 2
*Note1
*Note3
DQM
DQ
(CL=2)
Qb2
Qb1
Qa0
Qa1
Qb0
Qa1
Qb1
Qb0
Dc0
Dc0
Dc1
Dd0
Dd0
Dd1
DQ
(CL=3)
Qa0
Dc1
Dd1
Row Active
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
(December, 2009, Version 1.3)
25
AMIC Technology, Corp.
A43L2616B
Page Read Cycle at Different Bank @Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
*Note 1
CS
*Note 2
RAS
CAS
RAa
RBb
CAa
CBb
RCc
RDd
CCc
CDd
ADDR
BA0
BA1
A10/AP
WE
RAa
RBb
RCc
RDd
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
DQ
(CL=3)
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
Read
(C-Bank)
Row Active
(D-Bank)
Read
(D-Bank)
Precharge
(D-Bank)
Read
(B-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Precharge
(B-Bank)
Precharge
(C-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
: Don't care
* Note : 1.
can be don’t care when
,
CAS
RAS
and
are high at the clock high going edge.
WE
CS
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.
(December, 2009, Version 1.3)
26
AMIC Technology, Corp.
A43L2616B
Page Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
*Note 2
CCc
CDd
RAa
RBb
CAa
CBb
RCc
RDd
ADDR
BA0
BA1
A10/AP
RAa
RBb
RCc
RDd
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 CDd2
DQ
tRDL
tCDL
WE
*Note 1
DQM
Precharge
(All Banks)
Write
(A-Bank)
Write
(B-Bank)
Row Active
(D-Bank)
Write
(D-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(C-Bank)
Write
(C-Bank)
: Don't care
* Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.
(December, 2009, Version 1.3)
27
AMIC Technology, Corp.
A43L2616B
Read & Write Cycle at Different Bank @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
RAa
CAa
RDb
CDb
RBc
CBc
ADDR
BA0
BA1
A10/AP
RAa
RDb
RBC
tCDL
*Note 1
WE
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1 QBc2
QBc0 QBc1
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Write
(D-Bank)
Read
(B-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: Don't care
* Note : tCDL should be met to complete write.
(December, 2009, Version 1.3)
28
AMIC Technology, Corp.
A43L2616B
Read & Write Cycle with Auto Precharge @Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
RAa
RBb
CAa
CBb
ADDR
BA0
BA1
RAa
RBb
A10/AP
WE
DQM
DQ
(CL=2)
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
DDb0 DDb1 DDb2 DDb3
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
Auto Precharge
Start Point
(A-Bank/CL=3)
Auto Precharge
Start Point
(D-Bank)
Read with
Auto Precharge
(A-Bank)
Write with
Auto Precharge
(D-Bank)
Auto Precharge
Start Point
(A-Bank/CL=2)
Row Active
(D-Bank)
: Don't care
*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode)
(December, 2009, Version 1.3)
29
AMIC Technology, Corp.
A43L2616B
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
CS
RAS
CAS
Ra
Ca
Cb
Cc
ADDR
BA0
BA1
A10/AP
Ra
WE
* Note 1
DQM
DQ
Qa0
Qa1
Qb0
Qb1
Dc0
Dc2
Qa2
Qa3
tSHZ
tSHZ
Clock
Suspension
Write
DQM
Row Active
Read
Read
Read DQM
Clock
Suspension
Write
: Don't care
* Note : DQM needed to prevent bus contention.
(December, 2009, Version 1.3)
30
AMIC Technology, Corp.
A43L2616B
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full Page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
RAa
CAa
CAb
ADDR
BA0
BA1
RAa
A10/AP
WE
DQM
1
1
DQ
(CL=2)
QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAa0
2
2
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
Read
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Burst Stop
: Don't care
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQ’s after burst stop, it is same as the case of
interrupt.
RAS
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and interrupt should be compared carefully.
RAS
Refer the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at every burst length.
(December, 2009, Version 1.3)
31
AMIC Technology, Corp.
A43L2616B
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full Page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
High
CS
RAS
CAS
RAa
CAa
CAb
ADDR
BA0
BA1
A10/AP
RAa
tRDL
tBDL
* Note 2
WE
DQM
DQ
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Burst Stop
: Don't care
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.
It is defined by AC parameter of tRDL(=2CLK).
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
(December, 2009, Version 1.3)
32
AMIC Technology, Corp.
A43L2616B
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
* Note 2
tSS
tSS
tSS
tSS
* Note 1
*Note 3
CS
RAS
CAS
Ra
Ca
ADDR
BA0
BA1
Ra
A10/AP
WE
DQM
DQ
t
Qa0
Qa1
Qa2
Precharge
Power-down
Exit
Precharge
Power-
down
Read
Precharge
Row Active
Entry
Active
Active
Power-down
Entry
Power-
down
Exit
: Don't care
* Note : 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least “1CLK + tSS” prior to Row active command.
3. Cannot violate minimum refresh specification. (64ms)
(December, 2009, Version 1.3)
33
AMIC Technology, Corp.
A43L2616B
Self Refresh Entry & Exit Cycle
* Note : TO ENTER SELF REFRESH MODE
1. with CKE should be low at the same clock cycle.
CAS
,
&
CS RAS
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5.
starts from high.
CS
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.
If the system uses burst refresh.
(December, 2009, Version 1.3)
34
AMIC Technology, Corp.
A43L2616B
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
CLOCK
CKE
High
High
*Note 2
CS
tRC
RAS
CAS
* Note 1
* Note 3
Key
Ra
ADDR
WE
DQM
DQ
Hi-Z
Hi-Z
MRS
Auto Refresh
New Command
: Don't care
New
Command
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
* Note : 1.
,
,
&
activation at the same clock cycle with address key will set internal mode register.
WE
CS RAS CAS
2. Minimum 2 clock cycles should be met before new
3. Please refer to Mode Register Set table.
activation.
RAS
(December, 2009, Version 1.3)
35
AMIC Technology, Corp.
A43L2616B
Function Truth Table (Table 1)
Current
CS RAS
BA
Address
Action
Note
CAS
WE
State
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP
NOP
X
ILLEGAL
2
2
X
H
L
BA
BA
BA
X
CA, A10/AP ILLEGAL
IDLE
H
H
L
RA
Row Active; Latch Row Address
L
PA
NOP
4
5
5
L
H
L
X
Auto Refresh or Self Refresh
L
L
OP Code
Mode Register Access
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP
NOP
Row
X
ILLEGAL
2
2
Active
H
L
BA
BA
BA
BA
X
CA,A10/AP Begin Read; Latch CA; Determine AP
CA,A10/AP Begin Write; Latch CA; Determine AP
L
H
H
L
H
L
RA
PA
X
ILLEGAL
Precharge
ILLEGAL
L
L
X
X
H
L
X
H
H
H
H
L
X
H
H
L
X
X
NOP(Continue Burst to End →Row Active)
NOP(Continue Burst to End →Row Active)
Term burst →Row Active
X
X
X
X
H
L
BA
BA
BA
BA
X
CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
3
3
2
3
Read
L
CA,AP
Term burst; Begin Write; Latch CA; Determine AP
ILLEGAL
H
H
L
H
L
RA
PA
X
L
Term Burst; Precharge timing for Reads
ILLEGAL
L
X
X
H
L
X
H
H
H
H
L
X
H
H
L
X
X
NOP(Continue Burst to End→Row Active)
NOP(Continue Burst to End→Row Active)
Term burst →Row Active
X
X
X
X
H
L
BA
BA
BA
BA
X
CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP
3
3
2
3
Write
L
H
H
L
H
L
RA
ILLEGAL
L
A10/AP
Term Burst; Precharge timing for Writes
ILLEGAL
L
X
X
H
L
X
X
X
X
X
H
H
H
H
L
X
H
H
L
X
NOP(Continue Burst to End→Precharge)
NOP(Continue Burst to End→Precharge)
ILLEGAL
X
Read with
Auto
Precharge
X
H
L
BA
BA
BA
X
CA,A10/AP ILLEGAL
CA,A10/AP ILLEGAL
2
2
L
H
L
X
X
RA, PA
X
ILLEGAL
ILLEGAL
L
2
(December, 2009, Version 1.3)
36
AMIC Technology, Corp.
A43L2616B
Function Truth Table (Table 1, Continued)
Current
CS RAS
BA
Address
Action
Note
CAS
WE
State
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP(Continue Burst to End→Precharge)
NOP(Continue Burst to End→Precharge)
ILLEGAL
Write with
Auto
X
H
L
BA
BA
BA
X
CA,A10/AP ILLEGAL
CA,A10/AP ILLEGAL
2
2
Precharge
L
H
L
X
X
X
H
L
RA, PA
ILLEGAL
L
X
X
X
X
ILLEGAL
2
X
H
H
H
L
X
H
H
L
X
NOP→Idle after tRP
NOP→Idle after tRP
ILLEGAL
X
X
Precharge
X
H
L
BA
BA
BA
X
CA,A10/AP ILLEGAL
2
2
2
4
H
H
L
RA
ILLEGAL
L
A10/PA
NOP→Idle after tRP
ILLEGAL
L
X
X
H
L
X
X
X
X
X
H
H
H
L
X
H
H
L
X
NOP→Row Active after tRCD
NOP→Row Active after tRCD
ILLEGAL
X
X
Row
Activating
X
H
L
BA
BA
BA
X
CA,A10/AP ILLEGAL
2
2
2
2
H
H
L
RA
ILLEGAL
L
A10/PA
ILLEGAL
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
X
H
H
L
X
H
L
X
NOP→Idle after tRC
NOP→Idle after tRC
ILLEGAL
X
Refreshing
X
H
L
X
ILLEGAL
L
X
ILLEGAL
X
X
X
NOP→Idle after 2 clocks
Mode
Register
Accessing
L
H
H
H
H
X
NOP→Idle after 2 clocks
L
L
L
H
H
L
H
L
L
X
X
X
X
X
X
X
X
ILLEGAL
ILLEGAL
ILLEGAL
X
Abbreviations
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
PA = Precharge All
Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.
2. Illegal to bank in specified state : Function may be legal in the bank indicated by BA, depending on the state of that
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).
5. Illegal if any banks is not idle.
(December, 2009, Version 1.3)
37
AMIC Technology, Corp.
A43L2616B
Function Truth Table for CKE (Table 2)
Current
State
CKE CKE
CS
RAS
Address
Action
Note
CAS
WE
n-1
n
H
X
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
L
L
H
H
H
H
H
L
6
6
Exit Self Refresh→ABI after tRC
Exit Self Refresh→ABI after tRC
ILLEGAL
Self
L
L
Refresh
L
L
X
X
X
X
X
H
L
ILLEGAL
L
L
X
X
X
X
H
H
L
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
NOP(Maintain Self Refresh)
INVALID
H
L
X
H
H
H
H
H
L
7
7
Exit Power Down→ABI
Exit Power Down→ABI
ILLEGAL
Both
Bank
Precharge
Power
L
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL
Down
L
L
X
X
X
X
H
H
L
ILLEGAL
L
X
X
H
L
X
X
X
H
H
H
L
NOP(Maintain Power Down Mode)
Refer to Table 1
H
H
H
H
H
H
H
H
L
H
L
Enter Power Down
Enter Power Down
ILLEGAL
8
8
L
All
Banks
Idle
L
L
L
L
X
X
H
L
ILLEGAL
L
L
H
L
ILLEGAL
L
L
L
Enter Self Refresh
ILLEGAL
8
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP
H
H
L
H
L
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain clock Suspend
Any State
Other than
Listed
9
9
H
L
Above
L
Abbreviations : ABI = All Banks Idle
Note: 6. After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low
to high transition to issue a new command.
7. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time “tSS + one clock” must be satisfied before any command other than exit.
8. Power-down and self refresh can be entered only from the all banks idle state.
9. Must be a legal command.
(December, 2009, Version 1.3)
38
AMIC Technology, Corp.
A43L2616B
Part Numbering Scheme
X
X XX X X X X X
XX
A43
Package Material
Blank: normal
F: PB free
Temperature
Blank :0°C ~ 70°C
I:-25°C ~ 85°C
U:-40°C ~ 85°C
Speed
95: 105 MHz
75: 133 MHz
7: 143 MHz
6: 166 MHz
55: 183 MHz
5: 200 MHz
Package Type
V: TSOP
G: CSP
Device Version*
Mobile Function*
I/O Width
16: 16 I/O
32: 32 I/O
Device Density
06: 1M
16: 2M
26: 4M
36: 8M
46: 16M
83: 256K
Operating Vcc
L: 3V~3.6V
P: 2.3V~2.7V
E: 1.7V~1.95V
Device Type
A43: AMIC SDRAM
* Optional
(December, 2009, Version 1.3)
39
AMIC Technology, Corp.
A43L2616B
Ordering Information
Part No.
Cycle Time (ns)
Clock Frequency (MHz)
Access Time
Package
A43L2616BV-6F
A43L2616BV-6UF
A43L2616BV-7F
54 Pb-Free TSOP (II)
54 Pb-Free TSOP (II)
54 Pb-Free TSOP (II)
54 Pb-Free TSOP (II)
6
166 @ CL = 3
5.0 ns
7
143 @ CL = 3
6.0 ns
A43L2616BV-7UF
1. Pb-free for “-F” grade
2. Industrial for “-U” grade
(December, 2009, Version 1.3)
40
AMIC Technology, Corp.
A43L2616B
Package Information
TSOP 54 (Type II) Outline Dimensions
unit: inches/mm
Detail "A"
R1
54
28
0.21 REF
R2
0.665 REF
θ
L
L
1
1
27
D
Detail "A"
S
-C-
e
b
0.1
Seating Plane
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
Max
Min
-
Nom
Max
1.20
0.15
1.05
0.45
0.21
A
-
0.047
0.006
0.041
0.018
0.008
-
A1
A2
b
0.002
0.037
0.012
0.005
0.004
0.05
0.95
0.30
0.12
-
0.039
1.00
-
-
c
-
-
D
0.875 BSC
0.028 REF
0.463 BSC
0.400 BSC
0.031 BSC
0.020
22.22 BSC
0.71 REF
11.76 BSC
10.16 BSC
0.80 BSC
0.50
S
E
E1
e
L
0.016
0.024
0.40
0.60
L1
R1
R2
θ
0.031 REF
-
0.80 REF
-
0.005
0.005
0°
-
0.12
0.12
0°
-
-
0.010
8°
-
0.25
8°
-
-
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(December, 2009, Version 1.3)
41
AMIC Technology, Corp.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明