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A45L9332AF-8F [AMICC]

Synchronous Graphics RAM, 512KX32, 6.5ns, CMOS, PQFP100, QFP-100;
A45L9332AF-8F
型号： A45L9332AF-8F
厂家： AMIC TECHNOLOGY    AMIC TECHNOLOGY
描述：

Synchronous Graphics RAM, 512KX32, 6.5ns, CMOS, PQFP100, QFP-100

时钟 动态存储器 内存集成电路
文件： 总55页 (文件大小：1658K)
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A45L9332A Series  
256K X 32 Bit X 2 Banks Synchronous Graphic RAM  
Document Title  
256K X 32Bit X 2 Banks Synchronous Graphic RAM  
Revision History  
Rev. No. History  
Issue Date  
Remark  
0.0  
0.1  
1.0  
1.1  
Initial issue  
August 21, 2001  
October 22, 2001  
September 29, 2003  
August 19, 2004  
Preliminary  
Update AC and DC data specification  
Final version release  
Final  
Add Pb-Free package type  
(August, 2004, Version 1.1)  
AMIC Technology, Corp.  
A45L9332A Series  
256K X 32 Bit X 2 Banks Synchronous Graphic RAM  
Features  
ꢀJEDEC standard 3.3V power supply  
ꢀ100 Pin QFP, LQFP (14 X 20 mm)  
ꢀLVTTL compatible with multiplexed address  
ꢀDual banks / Pulse RAS  
ꢀMRS cycle with address key programs  
- CAS Latency (2,3)  
Graphics Features  
ꢀSMRS cycle  
- Burst Length (1,2,4,8 & full page)  
- Burst Type (Sequential & Interleave)  
ꢀ All inputs are sampled at the positive going edge of the  
system clock  
- Load mask register  
- Load color register  
ꢀWrite Per Bit (Old Mask)  
ꢀBlock Write (8 Columns)  
ꢀBurst Read Single-bit Write operation  
ꢀDQM 0-3 for byte masking  
ꢀAuto & self refresh  
ꢀ32ms refresh period (2K cycle)  
General Description  
The A45L9332A is 16,777,216 bits synchronous high data  
rate Dynamic RAM organized as 2 X 262,144 words by 32  
bits, fabricated with AMIC’s high performance CMOS  
technology. Synchronous design allows precise cycle control  
with the use of system clock. I/O transactions are possible on  
every clock cycle. Range of operating frequencies,  
programmable latencies allow the same device to be useful  
for a variety of high bandwidth, high performance memory  
system applications.  
Write per bit and  
8 columns block write improves  
performance in graphics system.  
(August, 2004, Version 1.1)  
1
AMIC Technology, Corp.  
A45L9332A Series  
Pin Configuration  
DQ  
3
1
80  
DQ28  
VDDQ  
DQ27  
DQ26  
VSSQ  
DQ25  
DQ24  
VDDQ  
DQ15  
DQ14  
VSSQ  
DQ13  
VDDQ  
2
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
DQ  
DQ  
4
5
3
4
VSSQ  
5
DQ  
DQ  
6
7
6
7
8
VDDQ  
DQ16  
9
DQ17  
10  
11  
VSSQ  
DQ18  
12  
13  
14  
15  
16  
DQ19  
VDDQ  
VDD  
DQ12  
A45L9332AE  
A45L9332AF  
VDDQ  
VSS  
VDD  
DQ11  
DQ10  
VSSQ  
VSS  
DQ20  
64  
63  
62  
61  
60  
17  
18  
DQ 21  
VSSQ  
DQ22  
DQ 23  
VDDQ  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
DQ  
DQ  
9
8
59  
58  
57  
56  
55  
VDDQ  
NC  
DQM  
DQM  
0
2
DQM  
DQM  
CLK  
3
1
WE  
CAS  
RAS  
54  
53  
52  
51  
CKE  
DSF  
NC  
CS  
BA(A10)  
A8  
A9  
(August, 2004, Version 1.1)  
2
AMIC Technology, Corp.  
A45L9332A Series  
Block Diagram  
DQMi  
MASK  
REGISTER  
BLOCK  
WRITE  
CONTROL  
LOGIC  
CLOCK  
REGISTER  
WRITE  
CONTROL  
LOGIC  
MUX  
CLK  
CKE  
CS  
DQi  
(i=0~31)  
COLUMN  
MASK  
DQMi  
RAS  
CAS  
256K x 32  
CELL  
256K x 32  
CELL  
ARRAY  
ARRAY  
WE  
DSF  
ROW DECORDER  
BANK SELECTION  
DQMi  
ROW  
ADDRESS  
BUFFER  
SERIAL  
COUNTER  
COLUMN ADDRESS  
BUFFER  
REFRESH  
COUNTER  
ADDRESS REGISTER  
CLOCK  
ADDRESS (A0~A10)  
(August, 2004, Version 1.1)  
3
AMIC Technology, Corp.  
A45L9332A Series  
Pin Descriptions  
Symbol  
Name  
Description  
CLK  
CS  
System Clock  
Chip Select  
Active on the positive going edge to sample all inputs.  
Disables or Enables device operation by masking or enabling all inputs except CLK,  
CKE and DQMi  
Masks system clock to freeze operation from the next clock cycle.  
CKE should be enabled at least one clock + t ss prior to new command.  
Disable input buffers for power down in standby.  
CKE  
Clock Enable  
Row / Column addresses are multiplexed on the same pins.  
Row address : RA0~RA9, Column address: CA0~CA7  
A0~A9  
Address  
Selects bank to be activated during row address latch time.  
Selects band for read/write during column address latch time.  
A10(BA)  
Bank Select Address  
Row Address Strobe  
Latches row addresses on the positive going edge of the CLK with RAS low.  
Enables row access & precharge.  
RAS  
CAS  
Latches column addresses on the positive going edge of the CLK with CAS low.  
Enables column access.  
Column Address Strobe  
Write Enable  
Enables write operation and Row precharge.  
WE  
Makes data output Hi-Z, t SHZ after the clock and masks the output.  
Blocks data input when DQM active. (Byte Masking)  
DQMi  
Data Input/Output Mask  
DQi  
Data Input/Output  
Data inputs/outputs are multiplexed on the same pins.  
DSF  
Define Special Function  
Power Supply/Ground  
Enables write per bit, block write and special mode register set.  
VDD/VSS  
Power Supply: +3.3V±0.3V/Ground  
VDDQ/VS Data Output  
Provide isolated Power/Ground to DQs for improved noise immunity.  
SQ  
Power/Ground  
NC  
No Connection  
(August, 2004, Version 1.1)  
4
AMIC Technology, Corp.  
A45L9332A Series  
Absolute Maximum Ratings*  
*Comments  
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V  
Voltage on VDD supply relative to VSS (VDD, VDDQ )  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V  
Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C  
Soldering Temperature X Time (TSLODER) . . . . . . . . . . . . . .  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec  
Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W  
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . 50mA  
Permanent device damage may occur if “Absolute Maximum  
Ratings” are exceeded.  
Functional operation should be restricted to recommended  
operating condition.  
Exposure to higher than recommended voltage for extended  
periods of time could affect device reliability.  
Capacitance (TA=25°C, f=1MHz)  
Parameter  
Input Capacitance  
Symbol  
CI1  
Condition  
Min  
2
Typ  
Max  
4
Unit  
pF  
A0 to A9, BA  
CI2  
2
4
pF  
CLK, CKE,  
DQMi, DSF  
,
,
,
,
WE  
CS RAS CAS  
Data Input/Output Capacitance  
CI/O  
DQ0 to DQ15  
2
6
pF  
DC Electrical Characteristics  
Recommend operating conditions (Voltage referenced to VSS = 0V)  
Parameter  
Supply Voltage  
Symbol  
Min  
3.0  
2.0  
-0.3  
2.4  
-
Typ  
Max  
Unit  
V
Note  
VDD,VDDQ  
3.3  
3.6  
Input High Voltage  
VIH  
VIL  
VOH  
VOL  
IIL  
3.0  
VDD+0.3  
V
Input Low Voltage  
0
-
0.8  
-
V
Note 1  
Output High Voltage  
Output Low Voltage  
Input Leakage Current  
Output Leakage Current  
Output Loading Condition  
V
IOH = -2mA  
IOL = 2mA  
Note 2  
-
0.4  
5
V
-5  
-
µA  
µA  
IOL  
-5  
-
5
Note 3  
See Figure 1  
Note: 1. VIL (min) = -1.5V AC (pulse width ≤ 5ns).  
2. Any input 0V ≤ VIN ≤ VDD + 0.3V, all other pins are not under test = 0V  
3. Dout is disabled, 0V ≤ Vout ≤ VDD  
Decoupling Capacitance Guide Line  
Recommended decoupling capacitance added to power line at board.  
Parameter  
Symbol  
CDC1  
Value  
Unit  
µF  
Decoupling Capacitance between VDD and VSS  
Decoupling Capacitance between VDDQ and VSSQ  
0.1 + 0.01  
0.1 + 0.01  
CDC2  
µF  
Note: 1. VDD and VDDQ pins are separated each other.  
All VDD pins are connected in chip. All VDDQ pins are connected in chip.  
2. VSS and VSSQ pins are separated each other  
All VSS pins are connected in chip. All VSSQ pins are connected in chip.  
(August, 2004, Version 1.1)  
5
AMIC Technology, Corp.  
A45L9332A Series  
DC Electrical Characteristics  
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)  
Speed  
-7  
CAS  
Symbol  
Parameter  
Test Conditions  
Unit  
Notes  
Latency  
-6  
-8  
Operating Current  
(One Bank Active)  
Burst Length = 1  
3
2
230 210  
170  
160  
Icc1  
mA  
mA  
1
tRC ≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA  
CKE ≤ VIL(max), tCC = 15ns  
-
260  
4
Icc2 P  
Precharge Standby  
Current in power-  
down mode  
Icc2 PS  
CKE ≤ VIL(max), CKL ≤ VIL(max), tCC = ∞  
4
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns  
ICC2N  
35  
Precharge Standby  
Current in non  
Input signals are changed one time during 30ns  
mA  
power-down mode  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞  
ICC2NS  
15  
Input signals are stable.  
ICC3 P  
Active Standby  
Current in power-  
down mode  
CKE ≤ VIL(max), tCC = 15ns  
6
6
mA  
mA  
ICC3 PS  
CKE ≤ VIL(max), CKE ≤ VIL(max) tCC = ∞  
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns  
ICC3N  
Active Standby  
current in non  
power-down mode  
(One Bank Active)  
60  
40  
Input signals are changed one time during 30ns  
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞  
ICC3NS  
Input signals are stable.  
3
310 280 250  
230 210  
Operating Current  
(Burst Mode)  
IOL = 0mA, Page Burst  
ICC4  
ICC5  
mA  
mA  
1
2
2
All bank Activated, tCCD = tCCD (min)  
-
3
2
150 120  
120  
120  
Refresh Current  
tRC ≥ tRC (min)  
-
180  
4
ICC6  
ICC7  
Self Refresh Current  
Operating Current  
mA  
mA  
CKE ≤ 0.2V  
240 220  
190  
tCC ≥ tCC (min), IOL=0mA, tBWC(min)  
(One Bank Block  
Write)  
Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).  
2. Refresh period is 32ms. Addresses are changed only one time during tCC(min).  
(August, 2004, Version 1.1)  
6
AMIC Technology, Corp.  
A45L9332A Series  
AC Operating Test Conditions  
(VDD = 3.3V ±0.3V, TA = 0°C to +70°C)  
Parameter  
Value  
AC input levels  
VIH/VIL = 2.4V/0.4V  
1.4V  
Input timing measurement reference level  
Input rise and all time (See note3)  
Output timing measurement reference level  
Output load condition  
tr/tf = 1ns/1ns  
1.4V  
See Fig.2  
3.3V  
VTT =1.4V  
VOH(DC) = 2.4V, IOH = -2mA  
VOL(DC) = 0.4V, IOL = 2mA  
1200Ω  
50Ω  
ZO=50Ω  
OUTPUT  
Output  
30pF  
870Ω  
3pF  
(Fig. 2) AC Output Load Circuit  
(Fig. 1) DC Output Load Circuit  
(August, 2004, Version 1.1)  
7
AMIC Technology, Corp.  
A45L9332A Series  
AC Characteristics  
(AC operating conditions unless otherwise noted)  
-6  
-7  
-8  
Symbol  
Parameter  
CAS  
Unit  
Note  
Latency  
Min  
Max  
Min  
Max  
Min  
Max  
3
2
3
2
6
7
8
8
10  
-
tCC  
CLK cycle time  
1000  
1000  
1000  
ns  
ns  
1
-
-
CLK to valid  
Output delay  
5.5  
-
-
6
6.5  
7
tSAC  
1,2  
-
-
7.5  
-
tOH  
tCH  
Output data hold time  
CLK high pulse width  
2.5  
2.5  
-
2.5  
2.5  
3
2.5  
3
ns  
ns  
2
3
3
2
3
2
3
2
3
2
3
2
3
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
2.5  
-
2.5  
3
tCL  
tSS  
tSH  
CLK low pulse width  
Input setup time  
3
2.5  
1
ns  
ns  
ns  
3
3
3
2
2
2
-
2.5  
Input hold time  
1
1
1
1
tSLZ  
tSHZ  
CLK to output in Low-Z  
1
ns  
ns  
CLK to output  
In Hi-Z  
-
-
5.5  
-
-
-
6
-
-
6.5  
7
7.5  
*All AC parameters are measured from half to half.  
Note : 1. Parameters depend on programmed CAS latency.  
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.  
3. Assumed input rise and fall time (tr & tf) = 1ns.  
If tr & tf is longer than 1ns, transient time compensation should be considered,  
i.e., [(tr + tf)/2-1]ns should be added to the parameter.  
(August, 2004, Version 1.1)  
8
AMIC Technology, Corp.  
A45L9332A Series  
Operating AC Parameter  
(AC operating conditions unless otherwise noted)  
Symbol  
Parameter  
CAS  
Latency  
Version  
-7  
Unit  
Note  
-6  
-8  
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
3
2
tRRD(min)  
tRCD(min)  
tRP(min)  
Row active to row active delay  
2
2
2
CLK  
CLK  
CLK  
CLK  
µs  
1
1
1
1
3
-
3
2
3
3
7
5
2
2
2
2
6
5
RAS to  
delay  
CAS  
3
-
Row precharge time  
8
-
tRAS(min)  
tRAS(max)  
tRC(min)  
Row active time  
100  
11  
-
10  
7
9
7
Row cycle time  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
1
2
2
2
3
tCDL(min)  
tRDL(min)  
tBDL(min)  
tCCD(min)  
tBPL(min)  
tBWC(min)  
Last data in new col. Address delay  
Last data in row precharge  
Last data in to burst stop  
1
2
-
2
2
2
2
1
1
2
1
Col. Address to col. Address delay  
Block write data-in to PRE command  
Block write cycle time  
1,3  
4
2
1
CLK  
CLK  
Number of valid output data  
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and  
then rounding off to the next higher integer.  
2. Minimum delay is required to complete write.  
3. This parameter means minimum  
to  
delay at block write cycle only.  
CAS  
CAS  
4. In case of row precharge interrupt, auto precharge and read burst stop.  
(August, 2004, Version 1.1)  
9
AMIC Technology, Corp.  
A45L9332A Series  
Simplified Truth Table  
Command  
CKEn-1 CKEn CS RAS  
DSF DQM A10 A9 A8~A0 Notes  
CAS  
L
WE  
L
Register  
Mode Register Set  
H
H
L
X
L
L
L
L
L
H
L
X
X
X
OP CODE  
1,2  
Special Mode Register Set  
Auto Refresh  
1,2,7  
3
Refresh  
H
L
L
L
H
X
X
Self  
Entry  
Exit  
3
3
Refresh  
H
H
H
H
X
H
L
X
L
X
H
X
H
3
4,5  
Bank Active Write Per Bite Disable  
H
H
H
H
X
X
X
X
L
H
L
X
X
X
X
V
V
V
V
Row Addr.  
& Row Addr.  
Write Per Bit Enable  
4,5,9  
4
Read &  
Column Addr.  
Auto Precharge Disable  
Auto Precharge Enable  
Auto Precharge Disable  
Auto Precharge Enable  
L
L
L
H
H
H
L
L
L
H
L
L
L
H
L
Column  
Addr.  
4,6  
Write &  
L
Column  
Addr.  
4,5  
Column Addr.  
H
L
4,5,6,9  
4,5  
Block Write & Auto Precharge Disable  
H
Column  
Addr.  
Column Addr.  
Burst Stop  
Precharge  
Auto Precharge Enable  
H
4,5,6,9  
7
H
H
X
X
L
L
H
L
H
H
L
L
L
L
X
X
X
Bank Selection  
Both Banks  
V
X
L
X
H
Clock Suspend or  
Active Power Down  
Entry  
H
L
L
H
X
L
H
X
X
H
X
V
X
H
X
X
H
X
V
X
H
X
X
H
X
V
X
X
X
X
Exit  
L
H
L
X
X
X
X
Precharge Power Down Mode  
Entry  
H
X
H
L
Exit  
L
H
X
V
X
X
H
DQM  
H
H
X
V
X
X
X
8
No Operation Command  
L
H
X
H
X
H
X
X
H
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)  
Note : 1. OP Code : Operand Code  
A0~A10 : Program keys. (@MRS)  
Color register exists only one per DQi which both banks share.  
So dose Mask Register.  
Color or mask is loaded into chip through DQ pin.  
2. MRS can be issued only at both banks precharge state.  
SMRS can be issued only if DQ’s are idle.  
A new command can be issued at the next clock of MRS/SMRS.  
3. Auto refresh functions as same as CBR refresh of DRAM.  
The automatical precharge without Row precharge command is meant by “Auto”.  
Auto/Self refresh can be issued only at both precharge state.  
4. A10 : Bank select address.  
If “Low” at read, (block) write, Row active and precharge, bank A is selected.  
If “High” at read, (block) write, Row active and precharge, bank B is selected.  
If A9 is “High” at Row precharge, A10 is ignored and both banks are selected.  
5. It is determined at Row active cycle.  
whether Normal/Block write operates in write per bit mode or not.  
For A bank write, at A bank Row active, for B bank write, at B bank Row active.  
Terminology : Write per bit = I/O mask  
(Block) Write with write per bit mode = Masked (Block ) Write  
(August, 2004, Version 1.1)  
10  
AMIC Technology, Corp.  
A45L9332A Series  
Simplified Truth Table  
6. During burst read or write with auto precharge, new read/ (block) write command cannot be issued.  
Another bank read/(block) write command can be issued at tPR after the end of burst.  
7. Burst stop command is valid only t full page burst length.  
8. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),  
but makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)  
9. Graphic features added to SDRAM’s original features.  
If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ’s.  
SGRAM vs SDRAM  
Function  
MRS  
Bank Active  
Write  
DSF  
L
H
L
H
L
H
Bank Active  
with  
Bank Active  
with  
SGRAM  
Function  
Normal  
Write  
Block  
Write  
MRS  
SMRS  
Write per bit  
Disable  
Write per bit  
Enable  
IF DSF is low, SGRAM functionality is identical to SDRAM functionality.  
SGRAM can be used as an unified memory by the appropriate DSF control  
→SDRAM = Graphic Memory + main Memory  
Mode Register Filed Table to Program Modes  
Register Programmed with MRS  
Address  
A10  
A9  
A8  
A7  
A6  
A5  
CAS Latency  
A4  
A3  
A2  
A1  
Burst Length  
A0  
Function  
RFU  
W.B.L  
TM  
BT  
(Note 1)  
(Note 2)  
Test Mode  
Type  
CAS Latency  
Burst Type  
Burst Length  
A8 A7  
A6 A5 A4  
Latency  
Reserved  
-
A3  
0
Type  
A2 A1 A0  
BT=0  
BT=1  
Reserved  
Reserved  
4
0
0
1
1
0
1
0
1
Mode Register Set  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Sequential  
Interleave  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
Vendor  
Use  
1
2
4
Only  
3
8
8
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
256(Full)  
Reserved  
Reserved  
Reserved  
Reserved  
Write Burst Length  
Length  
A9  
0
Burst  
1
Single Bit  
(Note 3)  
(August, 2004, Version 1.1)  
11  
AMIC Technology, Corp.  
A45L9332A Series  
Special Mode Register Programmed with SMRS  
Address  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
Function  
X
LC  
LM  
X
Load Color  
Load Mask  
A6 Function A5 Function  
0
1
Disable  
Enable  
0
1
Disable  
Enable  
(Note 4)  
Power Up Sequence  
1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.  
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200µs.  
3. Issue precharge commands for all banks of the devices.  
4. Issue 2 or more auto-refresh commands.  
5. Issue a mode register set command to initialize the mode register.  
cf.) Sequence of 4 & 5 may be changed.  
The device is now ready for normal operation.  
Note : 1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.  
2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.  
3. The full column burst (256bit) is available only at Sequential mode of burst type.  
4. If LC and LM both high (1), data of mask and color register will be unknown.  
Burst Sequence (Burst Length = 4)  
Initial address  
Sequential  
Interleave  
A1  
0
A0  
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
2
1
0
0
1
3
0
1
1
0
1
1
(August, 2004, Version 1.1)  
12  
AMIC Technology, Corp.  
A45L9332A Series  
Burst Sequence (Burst Length = 8)  
Initial address  
Sequential  
Interleave  
A2  
A1  
A0  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
2
3
0
1
6
7
4
5
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
Pixel to DQ Mapping (at BLOCK WRITE)  
Column address  
3 Byte  
I/O31 – I/O24  
DQ24  
2 Byte  
1 Byte  
0 Byte  
A2  
0
A1  
0
A0  
0
I/O23 – I/O16  
DQ16  
I/O15 – I/O8  
DQ8  
I/O7 – I/O0  
DQ0  
0
0
1
DQ25  
DQ17  
DQ9  
DQ1  
0
1
0
DQ26  
DQ18  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQ2  
0
1
1
DQ27  
DQ19  
DQ3  
1
0
0
DQ28  
DQ20  
DQ4  
1
0
1
DQ29  
DQ21  
DQ5  
1
1
0
DQ30  
DQ22  
DQ6  
1
1
1
DQ31  
DQ23  
DQ7  
(August, 2004, Version 1.1)  
13  
AMIC Technology, Corp.  
A45L9332A Series  
Device Operations  
Clock (CLK)  
Power-Up  
The clock input is used as the reference for all SGRAM  
operations. All operations are synchronized to the positive  
going edge of the clock. The clock transitions must be  
monotonic between VIL and VIH. During operation with CKE  
high all inputs are assumed to be in valid state (low or high)  
for the duration of set up and hold time around positive edge  
of the clock for proper functionality and ICC specifications.  
The following sequence is recommended for POWER UP  
1. Power must be applied to either CKE and DQM inputs to  
pull them high and other pins are NOP condition at the  
inputs before or along with VDD (and VDDQ) supply.  
The clock signal must also be asserted at the same time.  
2. After VDD reaches the desired voltage, a minimum pause  
of 200 microseconds is required with inputs in NOP  
condition.  
Clock Enable (CLK)  
3. Both banks must be precharged now.  
4. Perform a minimum of 2 Auto refresh cycles to stabilize  
the internal circuitry.  
5. Perform a MODE REGISTER SET cycle to program the  
CAS latency, burst length and burst type as the default  
value of mode register is undefined.  
The clock enable (CKE) gates the clock onto SGRAM. If  
CKE goes low synchronously with clock (set-up and hold  
time same as other inputs), the internal clock is suspended  
form the next clock cycle and the state of output and burst  
address is frozen as long as the CKE remains low. All other  
inputs are ignored from the next clock cycle after CKE goes  
low. When both banks are in the idle state and CKE goes low  
synchronously with clock, the SGRAM enters the power  
down mode form the next clock cycle. The SGRAM remains  
in the power down mode ignoring the other inputs as long as  
CKE remains low. The power down exit is synchronous as  
the internal clock is suspended. When CKE goes high at  
least “tSS + 1 CLOCK” before the high going edge of the  
clock, then the SGRAM becomes active from the same clock  
edge accepting all the input commands.  
At the end of one clock cycle from the mode register set  
cycle, the device is ready for operation.  
When the above sequence is used for Power-up, all the  
outputs will be in high impedance state. The high  
impedance of outputs is not guaranteed in any other  
power-up sequence.  
Cf.) Sequence of 4 & 5 may be charged.  
Mode Register Set (MRS)  
The mode register stores the data for controlling the various  
operation modes of SGRAM. It programs the CAS latency,  
addressing mode, burst length, test mode and various  
vendor specific options to make SGRAM useful for variety of  
different applications. The default value of the mode register  
is not defined, therefore the mode register must be written  
after power up to operate the SGRAM. The mode register is  
Bank Select (A10)  
This SGRAM is organized as two independent banks of  
262,144 words X 32 bits memory arrays. The A10 input is  
latched at the time of assertion of  
and  
to select  
CAS  
RAS  
the bank to be used for the operation. When A10 is asserted  
low, bank A is selected. When A10 is asserted high, bank B  
is selected. The bank select A10 is latched at bank activate,  
read, write mode register set and precharge operations.  
written by asserting low on  
,
,
,
and  
WE  
CS RAS CAS  
DSF (The SGRAM should be in active mode with CKE  
already high prior to writing the mode register). The state of  
address pins A0~A9 and A10 in the same cycle as  
Address Input (A0 ~ A9)  
,
,
,
and DSF going low is the data  
WE  
CS RAS CAS  
The 18 address bits required to decode the 262,144 word  
locations are multiplexed into 10 address input pins (A0~A9).  
The 10 bit row address is latched along with  
RAS  
during bank activate command. The 8 bit column address is  
written in the mode register. One clock cycle is required to  
complete the write in the mode register. The mode register  
contents can be changed using the same command and  
clock cycle requirements during operation as long as both  
banks are in the idle state. The mode register is divided into  
various fields depending on functionality. The burst length  
field uses A0~A2, burst type uses A3, addressing mode uses  
A4~A6, A7~A8 and A10 are used for vendor specific options  
or test mode. And the write burst length is programmed using  
A9. A7~A8 and A10 must be set to low for normal SGRAM  
operation.  
and A10  
latched along with  
command.  
,
and A10 during read or write  
WE  
CAS  
NOP and Device Deselect  
When and  
,
are high, the SGRAM  
WE  
RAS  
CAS  
performs no operation (NOP). NOP does not initiate any new  
operation, but is needed to complete operations which  
require more than single clock like bank activate, burst read,  
auto refresh, etc. The device deselect is also a NOP and is  
Refer to table for specific codes for various burst length,  
addressing odes and CAS latencies.  
entered by asserting  
high.  
high disables the  
CS  
CS  
command decoder so that  
,
and , DSF and  
WE  
RAS CAS  
all the address inputs are ignored.  
(August, 2004, Version 1.1)  
14  
AMIC Technology, Corp.  
A45L9332A Series  
Device Operations (continued)  
burst sequence. By asserting low on  
,
and  
WE  
CS CAS  
Bank Activate  
with valid column address, a write burst is initiated. The data  
inputs are provided for the initial address in the same clock  
cycle as the burst write command. The input buffer is  
deselected at the end of the burst length, even though the  
internal writing may not have been completed yet. The writing  
can not complete to burst length. The burst write can be  
terminated by issuing a burst read and DQM for blocking  
data inputs or burst write in the same or the other active  
bank. The burst stop command is valid only at full page burst  
length where the writing continues at the end of burst and the  
burst is wrap around. The write burst can also be terminated  
by using DQM for blocking data and precharging the bank  
“tRDL” after the last data input to be written into the active row.  
See DQM OPERATION also.  
The bank activate command is used to select a random row  
in an idle bank. By asserting low on  
and  
with  
CS  
RAS  
desired row and bank addresses, a row access is initiated.  
The read or write operation can occur after a time delay of  
tRCD(min) from the time of bank activation. tRCD(min) is an  
internal timing parameter of SGRAM, therefore it is  
dependent on operating clock frequency. The minimum  
number of clock cycles required between bank activate and  
read or write command should be calculated by dividing  
tRCD(min) with cycle time of the clock and then rounding off  
the result to the next higher integer. The SGRAM has two  
internal banks on the same chip and shares part of the  
internal circuitry to reduce chip area, therefore it restricts the  
activation of both banks immediately. Also the noise  
generated during sensing of each bank of SGRAM is high  
requiring some time for power supplies recover before the  
other bank can be sensed reliably. tRRD(min) specifies the  
minimum time required between activating different banks.  
The number of clock cycles required between different bank  
activation must be calculated similar to tRCD specification. The  
minimum time required for the bank to be active to initiate  
sensing and restoring the complete row of dynamic cells is  
determined by tRAS(min) specification before a precharge  
command to that active bank can be asserted. The maximum  
time any bank can be in the active state is determined by  
tRAS(max). The number of cycles for both tRAS(min) and  
tRAS(max) can be calculated similar to tRCD specification.  
DQM Operation  
The DQM is used to mask input and output operation. It  
works similar to  
during read operation and inhibits  
OE  
writing during write operation. The read latency is two cycles  
from DQM and zero cycle for write, which means DQM  
masking occurs two cycles later in the read cycle and occurs  
in the same cycle during write cycle. DQM operation is  
synchronous with the clock, therefore the masking occurs for  
a complete cycle. The DQM signal is important during burst  
interrupts of write with read or precharge in the SGRAM. Due  
to asynchronous nature of the internal write, the DQM  
operation is critical to avoid unwanted or incomplete writes  
when the complete burst write is not required. DQM is also  
used for device selection, byte selection and bus control in a  
memory system. DQM0 controls DQ0 to DQ7, DQM1  
controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23,  
DQM3 controls DQ24 to DQ31. DQM masks the DQ’s by a  
byte regardless that the corresponding DQ’s are in a state of  
WPB masking or Pixel masking. Please refer to DQM timing  
diagram also.  
Burst Read  
The burst read command is used to access burst of data on  
consecutive clock cycles from an active row in an active  
bank. The burst read command is issued by asserting low on  
and  
with  
being high on the positive edge of  
WE  
CS  
CAS  
the clock. The bank must be active for at least tRCD(min)  
before the burst read command is issued. The first output  
appears CAS latency number of clock cycles after the issue  
of burst read command. The burst length, burst sequence  
and latency from the burst read command is determined by  
the mode register which is already programmed. The burst  
read can be initiated on any column address of the active  
row. The address wraps around if the initial address does not  
start from a boundary such that number of outputs from each  
I/O are equal to the burst length programmed in the mode  
register. The output goes into high-impedance at the end of  
the burst, unless a new burst read was initiated to keep the  
data output gapless. The burst read can be terminated by  
issuing another burst read or burst write in the same bank or  
the other active bank or a precharge command to the same  
bank. The burst stop command is valid only at full page burst  
length where the output dose not go into high impedance at  
the end of burst and the burst is wrap around.  
Precharge  
The precharge operation is performed on an active bank by  
asserting low on  
,
,
and A9 with valid A10 of  
WE  
CS RAS  
the bank to be precharged. The precharge command can be  
asserted anytime after tRAS(min) is satisfied from the bank  
activate command in the desired bank. “tRP” is defined as the  
minimum time required to precharge a bank.  
The minimum number of clock cycles required to complete  
row precharge is calculated by dividing “tRP” with clock cycle  
time and rounding up to the next higher integer. Care should  
be taken to make sure that burst write is completed or DQM  
is used to inhibit writing before precharge command is  
asserted. The maximum time any bank can be active is  
specified by tRAS(max). Therefore, each bank has to be  
precharged within tRAS(max) from the bank activate  
command. At the end of precharge, the bank enters the idle  
state and is ready to be activated again.  
Burst Write  
Entry to Power Down, Auto refresh, Self refresh and Mode  
register Set etc, is possible only when both banks are in idle  
state.  
The burst write command is similar to burst read command,  
and is used to write data into the SGRAM consecutive clock  
cycles in adjacent addresses depending on burst length and  
(August, 2004, Version 1.1)  
15  
AMIC Technology, Corp.  
A45L9332A Series  
Device Operations (continued)  
Auto Precharge  
state to begin normal operation. If the system uses burst auto  
refresh during normal operation, it is recommended to used  
burst 2048 auto refresh cycles immediately after exiting self  
refresh.  
The precharge operation can also be performed by using  
auto precharge. The SGRAM internally generates the timing  
to satisfy tRAS(min) and “tRP” for the programmed burst length  
and CAS latency. The auto precharge command is issued at  
the same time as burst read or burst write by asserting high  
on A9. If burst read or burst write command is issued with low  
on A9, the bank is left active until a new command is  
asserted. Once auto precharge command is given, no new  
commands are possible to that particular bank until the bank  
achieves idle state.  
Define Special Function (DSF)  
The DSF controls the graphic applications of SGRAM. If DSF  
is tied to low, SGRAM function is 256K X 32 X 2 Bank  
SDRAM. SDRAM can be used as an unified memory by the  
appropriate DSF command. All the graphic function mode  
can be entered only by setting DSF high when issuing  
commands which otherwise would be normal SDRAM  
commands.  
Both Banks Precharge  
SDRAM functions such as  
Active, Write, and WCBR  
RAS  
Both banks can be precharged at the same time by using  
change to SGRAM functions such as  
Active with WPB,  
RAS  
Precharge all command. Asserting low on  
,
and  
CS RAS  
Block Write and SWCBR respectively. See the sessions  
below for the graphic functions that DSF controls.  
with high on A9 after both banks have satisfied  
WE  
tRAS(min) requirement, performs precharge on both banks. At  
the end of tRP after performing precharge all, both banks are  
in idle state.  
Special Mode Register Set (SMRS)  
There are two kinds of special mode registers in SGRAM.  
One is color register and the other is mask register. Those  
usage will be explained at “WRITE PER BIT” and ”BLOCK  
WRITE” session. When A5 and DSF goes high in the same  
Auto Refresh  
The storage cells of SGRAM need to be refreshed every  
32ms to maintain data. An auto refresh cycle accomplishes  
refresh of a single row of storage cells. The internal counter  
increments automatically on every auto refresh cycle to  
refresh all the rows. An auto refresh command is issued by  
cycle as  
,
,
and  
going low, load mask  
WE  
CS RAS CAS  
register (LMR) process is executed and the mask registers  
are filled with the masks for associated DQ’s through DQ  
pins. And when A6 and DSF goes high in the same cycle as  
asserting low on  
,
and  
with high on CKE and  
CAS  
CS RAS  
,
,
and  
going low, load color register  
WE  
CS RAS CAS  
. The auto refresh command can only be asserted with  
(LCR) process is executed and the color register is filled with  
color data for associated DQ’s through the DQ pins. If both  
A5 and A6 are high at SMRS, data of mask and color cycle is  
required to complete the write in the mask register and the  
color register at LMR and LCR respectively. The next clock of  
LMR or LCR, a new commands can be issued. SMRS,  
compared with MRS, can be issued at the active state under  
the condition that DQ’s are idle. As in write operation, SMRS  
accepts the data needed through DQ pins. Therefore it  
should be attended not to induce bus contention. The more  
detailed materials can obtained by referring corresponding  
timing diagram.  
WE  
both banks being in idle state and the device is not in power  
down mode (CKE is high in the previous cycle). The time  
required to complete the auto refresh operation is specified  
by “tRC(min)”. The minimum number of clock cycles required  
can be calculated by driving “tRC” with clock cycle time and  
then rounding up to the next higher integer. The auto refresh  
command must be followed by NOP’s until the auto refresh  
operation is completed. Both banks will be in the idle state at  
the end of auto refresh operation. The auto refresh is the  
preferred refresh mode when the SGRAM is being used for  
normal data transactions. The auto refresh cycle can be  
performed once in 15.6us or a burst of 2048 auto refresh  
cycles once in 32ms.  
Write Per Bit  
Write per bit (i.e. I/O mask mode) for SGRAM is a function  
that selectively masks bits of data being written to the  
devices. The mask is stored in an internal register and  
applied to each bit of data written when enabled. Bank active  
command with DSF = High enabled write per bit operations is  
stored in the mask register accessed by SWCBR (Special  
Mode Register Set Command). When a mask bit = 1, the  
associated data bit is written when a write command is  
executed and write per bit has been enabled for the bank  
being written. When a mask bit = 0, the associated data bit is  
unaltered when a write command is executed and the write  
per bit has been enabled for the bank being written. No  
additional timing conditions are required for write per bit  
operations. Write per bit writes can be either single write,  
burst writes or block writes. DQM masking is the same for  
write per bit and non-WPB write.  
Self Refresh  
The self refresh is another refresh mode available in the  
SGRAM. The self refresh is the preferred refresh mode for  
data retention and low power operation of SGRAM. In self  
refresh mode, the SGRAM disables the internal clock and all  
the input buffers except CKE. The refresh addressing and  
timing is internally generated to reduce power consumption.  
The self refresh mode is entered from all banks idle state by  
asserting low on  
,
,
and CKE with high on  
CS RAS CAS  
. Once the self refresh mode is entered, only CKE state  
being low matters, all the other inputs including clock are  
ignored to remain in the self refresh.  
WE  
The self refresh is exited by restarting the external clock and  
then asserting high on CKE. This must be followed by NOP’s  
for a minimum time of “tRC” before the SGRAM reaches idle  
(August, 2004, Version 1.1)  
16  
AMIC Technology, Corp.  
A45L9332A Series  
Device Operations (continued)  
Block Write  
Timing Diagram to Illustrate tBWC  
Block write is a feature allowing the simultaneous writing of  
consecutive 8 columns of data within a RAM device during a  
single access cycle. During block write the data to be written  
comes from an internal “color” register and DQ I/O pins are  
used for independent column selection. The block of column  
to be written is aligned on 8 column boundaries and is  
defined by the column address with the 3 LSB’s ignored.  
Write command with DSF = 1enables block write for the  
associated bank. A write command with DSF = 0 enables  
normal write for the associated bank. The block width is 8  
column where column = “n” bits for by “n” part. The color  
register is the same width as the data port of the chip. It is  
written via a SWCBR where data present on the DQ pin is to  
be coupled into the internal color register. The color register  
provides the data masked by the DQ column select, WPB  
mask (If enabled), and DQM byte mask. Column data  
masking (Pixel masking) is provided on an individual column  
basis for each byte of data. The column mask is driven on  
the DQ pins during a block write command. The DQ column  
mask function is segmented on a per bit basis (i.e. DQ[0:7]  
provides the column mask for data bits[0:7], DQ[8:15]  
provides the column mask for data bits[8:15], DQ0 masks  
column[0] for data bits[0:7], DQ9 masks column [1] for data  
its [8:15], etc). Block writes are always non-burst,  
independent of the burst length that has been programmed  
into the mode register. Back to back block writes are allowed  
provided that the specified block write cycle time (tBWC) is  
satisfied. If write per bit was enabled by the bank active  
command with DSF = 1, then write per bit masking of the  
color register data is enabled.  
0
1
2
Clock  
CKE  
CS  
High  
RAS  
CAS  
WE  
DSF  
1 CLK BW  
If write per bit was disabled by a bank active command with  
DSF = 0, the write per bit masking of the color register data is  
disabled. DQM masking provides independent data byte  
masking during block write exactly the same as it does during  
normal write operations, except that the control is extended  
to the consecutive 8 columns of the block write.  
(August, 2004, Version 1.1)  
17  
AMIC Technology, Corp.  
A45L9332A Series  
Summary of 2M Byte SGRAM Basic Features and Benefits  
Features  
256K X 32 X 2 SGRAM  
Benefits  
Better interaction between memory and system without wait-state of  
asynchronous DRAM.  
Interface  
Synchronous  
High speed vertical and horizontal drawing.  
High operation frequency allows performance gain for SCROLL, FILL,  
and BitBLT.  
Pseudo-infinite row length by on-chip interleaving operation.  
Hidden row activation and precharge.  
Bank  
2 ea  
Page Depth / 1 Row  
Total Page Depth  
256 bit  
High speed vertical and horizontal drawing.  
High speed vertical and horizontal drawing  
2048 bytes  
Programmable burst of 1,2,4,8 and full page transfer per column  
addresses.  
Burst Length (Read)  
Burst Length (Write)  
1,2,4,8 Full Page  
Programmable burst of 1,2,4,8 and full page transfer per column  
addresses.  
1,2,4,8 Full Page  
BRSW  
Switch to burst length of 1 at write without MRS  
Burst Type  
Sequential & Interleave Compatible with Intel and Motorola CPU based system.  
CAS Latency  
2,3  
Programmable CAS latency.  
High speed FILL, CLEAR, Text with color registers.  
Block Write  
8 Columns  
Maximum 32 byte data transfers (e.g. for 8bpp : 32 pixels) with plane  
and byte masking functions.  
Color Register  
Mask Register  
1 ea.  
1 ea.  
A and B bank share.  
Write-per-bit capability (bit plane masking). A and B banks share.  
Byte masking (pixel masking for 8bpp system) for data-out/in  
Each bit of the mask register directly controls a corresponding bit plane.  
DQM0-3  
Mask function  
Write per bit  
Pixel Mask at Block Write Byte masking (pixel masking for 8bpp system) for color by DQi  
Basic feature And Function Descriptions  
1. CLOCK Suspend  
1) Click Suspended During Write (BL=4)  
2) Clock Suspended During Read (BL=4)  
CLK  
CMD  
CKE  
WR  
RD  
Masked by CKE  
Masked by CKE  
Internal  
CLK  
DQ(CL2)  
DQ(CL3)  
D0  
D0  
D1  
D1  
D2  
D2  
D3  
D3  
Q0  
Q1  
Q0  
Q2  
Q1  
Q3  
Q2  
Q3  
Not Written  
Suspended Dout  
Note: CLK to CLK disable/enable=1 clock  
(August, 2004, Version 1.1)  
18  
AMIC Technology, Corp.  
A45L9332A Series  
2. DQM Operation  
2) Read Mask (BL=4)  
1) Write Mask (BL=4)  
CLK  
CMD  
WR  
RD  
DQMi  
Masked by CKE  
D3  
Masked by CKE  
Q1  
Hi-Z  
Hi-Z  
DQ(CL2)  
DQ(CL3)  
D0  
D0  
D1  
D1  
Q0  
Q3  
Q2  
D3  
Q1  
Q3  
DQM to Data-in Mask = 0CLK  
DQM to Data-out Mask = 2  
2) Read Mask (BL=4)  
CLK  
CMD  
CKE  
RD  
DQM  
Hi-Z  
Hi-Z  
Hi-Z  
Q4  
Hi-Z  
Hi-Z  
Q0  
Q2  
Q1  
Q6  
Q5  
Q7  
Q6  
Q8  
Q7  
DQ(CL2)  
DQ(CL3)  
Hi-Z  
Q3  
* Note : 1. There are 4 DQMi (I=0~3).  
Each DQMi masks 8 DQi’s. (1 Byte, 1 Pixel for 8bbp).  
2. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.  
(August, 2004, Version 1.1)  
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AMIC Technology, Corp.  
A45L9332A Series  
3. CAS Interrupt (I)  
1) Read intreupted by Read (BL=4)Note 1  
CKL  
CMD  
RD  
A
RD  
B
ADD  
DQ(CL2)  
DQ(CL3)  
QA0 QB0 QB1 QB2 QB3  
QA0 QB0 QB1 QB2 QB3  
t
CCD  
Note2  
2) Write interrupted by (Block) Write (BL =2)  
3) Write interrupted by Read (BL =2)  
CKL  
WR WR  
WR  
RD  
CMD  
WR  
BW  
t
CCD  
t
CCD  
tCCD  
Note2  
Note2  
Note2  
ADD  
DQ  
A
B
C
D
A
B
Note4  
DA0 DB0 DB1  
DC0  
t
DQ(CL2)  
DQ(CL3)  
DA0  
QB0 Pixel  
QB0 QB1  
Pixel  
t
CDL  
Note3  
CDL  
Note3  
DA0  
t
CDL  
Note3  
2) Block Write to Block Write  
CKL  
CMD  
ADD  
DQ  
BW  
BW  
B
A
Note4  
Pixel  
Pixel  
t
BWC  
Note5  
Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.  
By “ Interrupt”, to stop burst read/write by access; read, write and block write.  
CAS  
2. tCCD :  
CAS  
to  
delay. (=1CLK)  
CAS  
CAS  
3. tCDL : Last data in to new column address delay. ( = 1CLK).  
4. Pixel : Pixel mask.  
5. tBWC : Block write minimum cycle time.  
(August, 2004, Version 1.1)  
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AMIC Technology, Corp.  
A45L9332A Series  
4. CAS Interrupt (II) : Read Interrupted Write & DQM  
(1) CL=2, BL=4  
CLK  
i) CMD  
RD  
RD  
WR  
D0  
DQM  
DQ  
ii) CMD  
D1  
D2  
D3  
D2  
WR  
DQM  
DQ  
Hi-Z  
D0  
D1  
D3  
D2  
D1  
RD  
RD  
WR  
iii) CMD  
DQM  
DQ  
Hi-Z  
D0  
D1  
D3  
D2  
iv) CMD  
WR  
DQM  
DQ  
Hi-Z  
Note 1  
Q0  
D0  
D3  
(2) CL=3, BL=4  
CLK  
i) CMD  
DQM  
RD  
RD  
RD  
RD  
WR  
D0  
DQ  
D1  
D2  
D3  
D2  
ii) CMD  
WR  
DQM  
DQ  
D0  
D1  
D3  
D2  
iii) CMD  
WR  
DQM  
DQ  
D0  
D1  
D3  
D2  
D1  
iv) CMD  
WR  
DQM  
DQ  
Hi-Z  
D0  
D1  
D3  
D2  
v) CMD  
RD  
WR  
DQM  
DQ  
Hi-Z  
Q0  
D0  
D3  
Note 2  
* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.  
2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.  
(August, 2004, Version 1.1)  
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AMIC Technology, Corp.  
A45L9332A Series  
5. Write Interrupted by Precharge & DQM  
CLK  
Note 2  
CMD  
WR  
D0  
PRE  
Note 1  
DQM  
DQ  
D1  
D2  
D3  
Masked by DQM  
Note : 1. To inhibit invalid write, DQM should be issued.  
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge  
interrupt but only another bank precharge of dual banks operation.  
6. Precharge  
1) Normal Write (BL=4)  
2) Block Write  
CLK  
CLK  
CMD  
DQ  
CMD  
DQ  
WR  
D0  
PRE  
BW  
PRE  
D1  
D2  
D3  
Pixel  
tRDL  
Note 1  
tBPL  
Note 1  
3) Read (BL=4)  
CLK  
Note 2  
CMD  
RD  
PRE  
Q2  
1
DQ(CL2)  
Q0  
Q1  
Q0  
Q3  
Q2  
2
DQ(CL3)  
Q1  
Q3  
7. Auto Precharge  
1) Normal Write (BL=4)  
CLK  
2) Block Write  
CLK  
CMD  
DQ  
CMD  
DQ  
WR  
D0  
BW  
Pixel  
D1  
D2  
D3  
(CL 2,3)  
Note 3  
Auto Precharge Starts  
t
RP  
t
BPL  
Note 3  
Auto Precharge Starts  
3) Read (BL=4)  
CLK  
CMD  
RD  
DQ(CL2)  
DQ(CL3)  
Q0  
Q1  
Q0  
Q2  
Q1  
Q3  
Q2  
Q3  
Note 3  
Auto Precharge Starts  
* Note : 1. tBPL : Block write data-in to PRE command delay.  
2. Number of valid output data after Row Precharge : 1,2 for CAS Latency = 2,3 respectively.  
3. The row active command of the precharge bank can be issued after tRP from this point.  
The new read/write command of other active bank can be issued from this point.  
At burst read/write with auto precharge,  
interrupt of the same/another bank is illegal.  
CAS  
(August, 2004, Version 1.1)  
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AMIC Technology, Corp.  
A45L9332A Series  
8. Burst Stop & Precharge Interrupt  
1) Write Interrupted by Precharge (BL=4)  
CLK  
2) Write Burst Stop (Full Page Only)  
CLK  
CMD  
CMD  
WR  
PRE  
WR  
D0  
STOP  
DQM  
DQ  
D0  
D1  
D2  
D3  
DQ  
D1  
D2  
Note 1  
t
RDL  
t
BDL  
3) Read Interrupted by Precharge (BL=4)  
CLK  
4) Read Burst Stop (Full Page Only)  
CLK  
CMD  
CMD  
DQ(CL2)  
DQ(CL3)  
RD  
RD  
PRE  
Q0  
STOP  
Q0  
Note 3  
1
Note 3  
1
DQ(CL2)  
DQ(CL3)  
Q1  
Q0  
Q1  
Q0  
2
2
Q1  
Q1  
9. MRS & SMRS  
2) Mode Register Set  
CLK  
2) Special Mode Register Set  
CLK  
Note 4  
CMD  
SMRS  
SMRS ACT  
SMRS BW  
PRE  
MRS ACT  
1CLK  
CMD  
1CLK 1CLK 1CLK 1CLK  
t
RP  
Note : 1.tRDL : 2CLK, Last Data in to Row Precharge.  
2. tBDL : 1CLK, Last Data in to Burst Stop Delay.  
3. Number of valid output data after Row precharge or burst stop : 1,2 for CAS latency=2,3 respectively.  
4. PRE : Both banks precharge if necessary.  
MRS can be issued only at all bank precharge state.  
(August, 2004, Version 1.1)  
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AMIC Technology, Corp.  
A45L9332A Series  
10. Clock Suspend Exit & Power Down Exit  
1) Clock Suspend (=Active Power Down) Exit  
CLK  
2) Power Down (=Precharge Power Down) Exit  
CLK  
CKE  
CKE  
t
SS  
t
SS  
Note 2  
Note 1  
Internal  
CLK  
Internal  
CLK  
NOP  
ACT  
RD  
CMD  
CMD  
11. Auto Refresh & Self Refresh  
Note 3  
1) Auto Refresh  
CLK  
Note 4  
Note 5  
CKE  
PRE  
Internal  
CLK  
AR  
CMD  
CMD  
t
RP  
tRC  
Note 6  
2) Self Refresh  
CLK  
Note 4  
CMD  
CKE  
PRE  
SR  
CMD  
t
RP  
tRC  
* Note : 1. Active power down : one or more bank active state.  
2. Precharge power down : both bank precharge state.  
3. The auto refresh is the same as CBR refresh of conventional DRAM.  
No precharge commands are required after Auto Refresh command.  
During tRC from auto refresh command, any other command can not be accepted.  
4. Before executing auto/self refresh command, both banks must be idle state.  
5. (S)MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.  
6. During self refresh mode, refresh interval and refresh operation are performed internally.  
After self refresh entry, self refresh mode is kept while CKE is LOW.  
During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.  
During tRC from self refresh exit command, any other command can not be accepted.  
Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended.  
(August, 2004, Version 1.1)  
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AMIC Technology, Corp.  
A45L9332A Series  
12. About Burst Type Control  
At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)  
BL=1,2,4,8 and full page wrap around.  
Sequential counting  
Basic  
MODE  
At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)  
BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting  
At MRS A3 = “1”. (See to Interleave Counting Mode)  
Starting Address LSB 3 bits A0-2 should be “000” or “111”.@BL=8.  
--if LSB = “000” : Increment Counting.  
Interleave counting  
--if LSB= “111” : Decrement Counting.  
Pseudo-  
Decrement Sequential  
Counting  
For Example, (Assume Addresses except LSB 3 bits are all 0, BL=8)  
--@ write, LSB=”000”, Accessed Column in order 0-1-2-3-4-5-6-7  
--@ read, LSB=”111”, Accessed Column in order 7-6-5-4-3-2-1-0  
At BL=4, same applications are possible. As above example, at Interleave Counting  
mode, by confining starting address to some values, Pseudo-Decrement Counting  
Mode can be realized. See the BURST SEQUENCE TABLE carefully.  
At MRS A3 = “0”. (See to Sequential Counting Mode)  
A0-2 = “111”. (See to Full Page Mode)  
Pseudo-  
MODE  
Using Full Page Mode and Burst Stop Command, Binary Counting Mode can be  
realized.  
Pseudo-Binary Counting --@ Sequential Counting Accessed Column in order 3-4-5-6-7-1-2-3 (BL=8)  
--@ Pseudo-Binary Counting,  
Accessed Column in order 3-4-5-6-7-8-9-10 (Burst Stop command)  
Note. The next column address of 256 is 0  
Every cycle Read/Write Command with random column address can realize  
Random  
MODE  
Random column Access  
Random Column Access.  
tCCD = 1 CLK  
That is similar to Extended Data Out (EDO) Operation of convention DRAM.  
13. About Burst Length Control  
At MRS A2,1,0 = “000”.  
At auto precharge, tRAS should not be violated.  
1
At MRS A2,1,0 = “001”.  
At auto precharge, tRAS should not be violated.  
At MRS A2,1,0 = “010”  
2
Basic  
MODE  
4
8
At MRS A2,1,0 = “011”.  
At MRS A2,1,0 = “111”.  
Full Page  
Wrap around mode (Infinite burst length) should be stopped by burst stop,  
interrupt or  
interrupt.  
CAS  
RAS  
At MRS A9=”1”.  
BRSW  
Read burst = 1,2,4,8, full page/write Burst =1  
Special  
MODE  
At auto precharge of write, tRAS should not be violated.  
8 Column Block Write. LSB A0-2 are ignored. Burst length=1.  
tBWC should not be violated.  
Block Write  
Burst Stop  
At auto precharge, tRAS should not be violated.  
Random  
MODE  
tBDL=1, Valid DQ after burst stop is 1,2 for CL=2,3 respectively  
Using burst stop command, it is possible only at full page burst length.  
Before the end of burst, Row precharge command of the same bank  
Stops read/write burst with Row precharge.  
Interrupt  
RAS  
(Interrupted by Precharge)  
tRDL=2 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively  
Interrupt  
MODE  
During read/write burst with auto precharge,  
Before the end of burst, new read/write stops read/write burst and starts new  
read/write burst or block write.  
interrupt cannot be issued.  
RAS  
Interrupt  
CAS  
During read/write burst with auto precharge,  
interrupt can not be issued.  
CAS  
(August, 2004, Version 1.1)  
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AMIC Technology, Corp.  
A45L9332A Series  
14. Mask Functions  
1) Normal Write  
I/O masking : By Mask at Write per Bit Mode, the selected bit planes keep the original data.  
If bit plane 0,3,7,9,15,22,24, and 31 keep the original value.  
i) STEP  
•• SMRS (LMR) : Load mask [31-0]=”0111,1110,1011,1111,0111,1101,0111,0110”  
•• Row Active with DSF “H” : Writ Per Bit Mode Enable  
•• Perform Normal Write  
ii) ILLUSTRATION  
I/O(=DQ)  
External Data-in  
DQMi  
31  
24  
23  
16  
15  
8
7
0
1 1 1 1 1 1 1 1  
DQM3=0  
1 1 1 1 1 1 1 1  
DQM2=0  
0 0 0 0 0 0 0  
DQM1=0  
0 0 0 0 0 0 0 0  
DQM0=1  
Mask Register  
Before Write  
After Write  
0 1 1 1 1 1 1 0  
0 0 0 0 0 0 0 0  
0 1 1 1 1 1 1 0  
1 0 1 1 1 1 1 1  
0 0 0 0 0 0 0 0  
1 0 1 1 1 1 1 1  
0 1 1 1 1 0 1  
1 1 1 1 1 1 1  
1 0 0 0 0 1 0  
0 1 1 1 0 1 1 0  
1 1 1 1 1 1 1 1  
1 1 1 1 1 1 1 1  
Note 1  
2) Block Write  
Pixel masking : By Pixel Data issued through DQ pin, the selected pixels keep the original data.  
See PIXEL TO DQ MAPPING TABLE.  
If Pixel 0,4,9,13,18, 22, 27 and 31 keep the original white color.  
Assume 8bpp,  
White = “0000,0000”, Red = “1010,0011”, Green = “1110,0001”, Yellow = “0000,1111”, Blue = “1100,0011”  
i)STEP  
•• SMRS(LCR) : Load color (for 8bbp, through X32 DQ color 0-3 are loaded into color registers)  
Load(color3, color2, color1, color0) = (Blue, Green, Yellow, Red)  
= “1100,0011,1110,0001,0000,1111,1010,0011”  
•• Row Active with DSF “L” : I/O Mask by Write Per Bit Mode Disable  
•• Block write with DQ[31-0] = “0111,0111,1011,1011,1101,1101,1110,1110”  
ii) ILLUSTRATION  
I/O(=DQ)  
DQMi  
31  
24  
23  
16  
15  
8
7
0
DQM3=0  
DQM2=0  
DQM1=0  
DQM0=1  
Color Register  
Color3=Blue  
White DQ24=H  
White DQ25=H  
White DQ26=H  
White DQ27=L  
White DQ28=H  
White DQ29=H  
White DQ30=H  
White DQ31=L  
Blue  
Color2=Green  
White DQ16=H  
White DQ17=H  
White DQ18=L  
White DQ19=H  
White DQ20=H  
White DQ21=H  
White DQ22=L  
White DQ23=H  
Green  
Color1=Yellow  
White DQ8=H  
White DQ9=L  
White DQ10=H  
White DQ11=H  
White DQ12=H  
White DQ13=L  
White DQ14=H  
White DQ15=H  
Yellow  
Color0=Red  
White DQ0=L  
White DQ1=H  
White DQ2=H  
White DQ3=H  
White DQ4=L  
White DQ5=H  
White DQ6=H  
White DQ7=H  
White  
000  
Before  
Block  
Write  
&
001  
010  
011  
100  
101  
110  
111  
000  
001  
010  
011  
100  
101  
110  
111  
DQ  
(Pixel  
data)  
Blue  
Blue  
White  
Blue  
Blue  
Blue  
White  
Green  
White  
Green  
Green  
Green  
White  
Green  
White  
Yellow  
Yellow  
Yellow  
White  
Yellow  
Yellow  
White  
White  
White  
White  
White  
White  
White  
After  
Block  
Write  
Note 2  
* Note : 1. DQM byte masking.  
2. At normal write, One column is selected among columns decoded by A2-0 (000-111)  
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.  
(August, 2004, Version 1.1)  
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AMIC Technology, Corp.  
A45L9332A Series  
(Continued)  
Pixel and I/O masking : By Mask at Write Per Bit Mode, the selected bit planes keep the original data.  
By Pixel Data issued through DQ pin, the selected pixels keep the original data.  
See PIXEL TO DQ MAPPING TANLE.  
Assume 8bpp,  
White = “0000,0000”, Red = “1010,0011”, Green = “1110,0001”, Yellow = “0000,1111”, Blue = “1100,0011”  
i) STEP  
•• SMRS (LCR) : Load color (for 8bpp, through X 32 DQ color0-3 are loaded into color registers)  
Load (color3, color2, color1, color0) = (Blue, Green, Yellow, Red)  
= “1100,0011,1110,0001,0000,1111,1010,0011”  
••SMRS (LMR) : Load mask, Mask[31-0] = “1111,1111,1101,1101,0100,0010,0111,0110”  
→ Byte 3:No I/O Masking; Byte 2:I/O Masking; Byte 1:I/O and Pixel Masking; Byte 0:DQM Byte Masking  
•• Row Active with DSF “H” : I/O Mask by Write Per Bit Mode Enable  
•• Block Write with DQ[31-0] = “0111,0111,1111,1111,0101,0101,1110,1110”  
(Pixel Mask)  
ii) ILLUSTRATUON  
I/O(=DQ)  
31  
24  
23  
16  
15  
8
7
0
Color Register  
Blue  
Green  
Yellow  
Red  
1 1 0 0 0 0 1 1  
DQM3=0  
1 1 1 0 0 0 0 1  
DQM2=0  
0 0 0 0 1 1 1 1  
DQM1=0  
1 0 1 0 0 0 1 1  
DQM0=1  
DQMi  
Mask Register  
Before Write  
1 1 1 1 1 1 1 1  
1 1 0 1 1 1 0 1  
0 1 0 0 0 0 1 0  
0 1 1 1 0 1 1 0  
Yellow  
Yellow  
Green  
White  
0 0 0 0 1 1 1 1  
Blue  
0 0 0 0 1 1 1 1  
Blue  
1 1 1 0 0 0 0 1  
Red  
0 0 0 0 0 0 0 0  
White  
After Write  
1 1 0 0 0 0 1 1  
1 1 0 0 0 0 1 1  
1 0 1 0 0 0 1 1  
0 0 0 0 0 0 0 0  
Note 1  
I/O(=DQ)  
DQMi  
31  
24  
23  
16  
15  
8
7
0
DQM3=0  
DQM2=0  
DQM1=0  
DQM0=1  
Color Register  
Color3=Blue  
Yellow DQ24=H  
Yellow DQ25=H  
Yellow DQ26=H  
Yellow DQ27=L  
Yellow DQ28=H  
Yellow DQ29=H  
Yellow DQ30=H  
Yellow DQ31=L  
Blue  
Color2=Green  
Yellow DQ16=H  
Yellow DQ17=H  
Yellow DQ18=H  
Yellow DQ19=H  
Yellow DQ20=H  
Yellow DQ21=H  
Yellow DQ22=H  
Yellow DQ23=H  
Blue  
Color1=Yellow  
Green DQ8=H  
Green DQ9=L  
Green DQ10=H  
Green DQ11=H  
Green DQ12=H  
Green DQ13=L  
Green DQ14=H  
Green DQ15=L  
Red  
Color0=Red  
White DQ0=L  
White DQ1=H  
White DQ2=H  
White DQ3=H  
White DQ4=L  
White DQ5=H  
White DQ6=H  
White DQ7=H  
White  
000  
Before  
Block  
Write  
&
001  
010  
011  
100  
101  
110  
111  
000  
001  
010  
011  
100  
101  
110  
111  
DQ  
(Pixel  
data)  
Blue  
Blue  
Yellow  
Blue  
Blue  
Blue  
Yellow  
Green  
Red  
Green  
Red  
Green  
Red  
Green  
White  
White  
White  
White  
White  
White  
White  
Blue  
Blue  
Blue  
Blue  
Blue  
Blue  
Blue  
After  
Block  
Write  
Note 2  
Note 1  
PIXEL MASK  
* Note : 1. DQM byte masking.  
I/O MASK  
PIXEL & I/O MASK  
BYTE MASK  
2. At normal write, One column is selected among columns decoded by A2-0 (000-111)  
At block write, instead of ignored address A2-0, DQ0-31 control each pixel.  
(August, 2004, Version 1.1)  
27  
AMIC Technology, Corp.  
A45L9332A Series  
Power On Sequence & Auto Refresh  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
CS  
High level is necessary  
tRP  
tRC  
RAS  
CAS  
ADDR  
KEY  
Ra  
A
10/BA  
KEY  
KEY  
BS  
Ra  
A9/AP  
WE  
DSF  
DQM  
DQ  
High level is necessary  
High-Z  
Precharge  
(All Banks)  
Auto Refresh  
Auto Refresh  
Mode Regiser Set  
Row Active  
(Write per Bit  
Enable or Disable)  
: Don't care  
(August, 2004, Version 1.1)  
28  
AMIC Technology, Corp.  
A45L9332A Series  
Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1  
t
CH  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
t
CL  
t
CC  
High  
t
RAS  
t
RC  
t
SH  
*Note 1  
CS  
t
SS  
t
RCD  
t
RP  
t
SH  
RAS  
t
SS  
t
CCD  
t
SH  
CAS  
t
SS  
t
SH  
tSS  
ADDR  
Ra  
Ca  
Cb  
Cc  
Rb  
t
SS  
t
SH  
*Note 2,3  
*Note 2,3  
*Note 2,3 *Note 4  
*Note 2  
*Note 2  
A10  
BS  
BS  
BS  
BS  
BS  
BS  
*Note 3  
*Note 3  
*Note 3 *Note 4  
A9  
Ra  
Rb  
t
SH  
WE  
t
SS  
*Note 5  
*Note 6  
*Note 3  
*Note 5  
DSF  
t
SS  
tSH  
t
t
SS  
t
t
SH  
SH  
DQM  
DQ  
t
RAC  
t
SAC  
Qa  
Db  
Qc  
t
SLZ  
SS  
t
OH  
t
SHZ  
Row Active  
(Write per Bit  
Enable or  
Disable)  
Row Active  
(Write per Bit  
Enable or  
Disable  
Write  
or  
Block Write  
Read  
Read  
Precharge  
: Don't care  
(August, 2004, Version 1.1)  
29  
AMIC Technology, Corp.  
A45L9332A Series  
* Note : 1. All inputs can be don’t care when  
is high at the CLK high going edge.  
CS  
2. Bank active & read/write are controlled by A10.  
A10  
0
Active & Read/Write  
Bank A  
1
Bank B  
3. Enable and disable auto precharge function are controlled by A9 in read/write command.  
A9  
A10  
0
Operation  
Disable auto precharge, leave bank A active at end of burst.  
Disable auto precharge, leave bank B active at end of burst.  
Enable auto precharge, precharge bank A at end of burst.  
Enable auto precharge, precharge bank B at end of burst.  
0
1
0
1
1
4. A9 and A10 control bank precharge when precharge command is asserted.  
A9  
0
A10  
0
Precharge  
Bank A  
0
1
Bank B  
1
X
Both Bank  
5. Enable and disable Write-per Bit function are controlled by DSF in Row Active command.  
A10  
DSF  
L
Operation  
Bank A row active, disable write per bit function for bank A  
Bank A row active, enable write per bit function for bank A  
Bank B row active, disable write per bit function for bank B  
Bank B row active, enable write per bit function for bank B  
0
H
L
1
H
6. Block write/normal write is controlled by DSF  
DSF  
L
Operation  
Normal write  
Block write  
Minimum cycle time  
tCCD  
tBWC  
H
(August, 2004, Version 1.1)  
30  
AMIC Technology, Corp.  
A45L9332A Series  
Read & Write Cycle at Same Bank @Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
*Note 1  
RC  
t
CS  
t
RCD  
RAS  
CAS  
*Note 2  
ADDR  
A10  
A9  
Ra  
Ra  
Ca0  
Rb  
Rb  
Cb0  
WE  
DSF  
DQM  
t
OH  
DQ  
(CL = 2)  
Qa0  
Qa1  
Qa2  
Qa3  
Db0  
Db0  
Db1  
Db2  
Db3  
t
RAC  
*Note 4  
t
RDL  
t
SAC  
tSHZ  
*Note 3  
t
OH  
DQ  
(CL = 3)  
Qa0  
Qa1  
Qa2  
Qa3  
Db1  
Db2  
Db3  
t
RAC  
*Note 4  
t
RDL  
t
SHZ  
t
SAC  
*Note 3  
Row Active  
(A-Bank)  
Precharge  
(A-Bank)  
Row Active  
(A-Bank)  
Write  
(A-Bank)  
Read  
(A-Bank)  
Precharge  
(A-Bank)  
: Don't care  
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.  
2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row  
enters precharge. Last valid output will be Hi-Z after tSHZ from the clock.  
3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC  
4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)  
At Full page bit burst, burst is wrap-around.  
(August, 2004, Version 1.1)  
31  
AMIC Technology, Corp.  
A45L9332A Series  
Page Read & Write Cycle at Same Bank @Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
t
RCD  
RAS  
CAS  
*Note 2  
ADDR  
A10  
A9  
Ra  
Ra  
Ca0  
Cb0  
Cc0  
Cd0  
t
RDL  
t
CDL  
WE  
*Note 2  
DSF  
*Note1  
*Note3  
DQM  
DQ  
(CL=2)  
Qa0  
Qa1  
Qb0  
Qa1  
Qb1  
Qb0  
Dc0  
Dc1  
Dc1  
Dd0  
Dd1  
DQ  
(CL=3)  
Qa0  
Dc0  
Dd0  
Dd1  
Row Active  
(A-Bank)  
Write  
(A-Bank)  
Write  
(A-Bank)  
Read  
(A-Bank)  
Read  
(A-Bank)  
Precharge  
(A-Bank)  
: Don't care  
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write  
command to avoid bus contention.  
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.  
3. DQM should mask invalid input data on precharge command cycle when asserting precharge  
before end of burst. Input data after Row precharge cycle will be masked internally.  
(August, 2004, Version 1.1)  
32  
AMIC Technology, Corp.  
A45L9332A Series  
Block Write Cycle (with Auto Precharge)  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
*Note 2  
ADDR  
RAa  
CAa  
CAb  
RBa  
RBa  
CBa  
CBb  
A10  
A9  
RAa  
WE  
DSF  
t
BWC  
DQM  
*Note 1  
Pixel  
Mask  
Pixel  
Mask  
Pixel  
Mask  
Pixel  
Mask  
DQ  
Row Active  
(B-Bank)  
Block Write with  
Auto Precharge  
(B-Bank)  
Masked  
Block Write  
(A-Bank)  
Row Active with  
Write-per-Bit  
Enable  
(A-Bank)  
Masked  
Block Write  
(B-Bank)  
Block Write with  
Auto Precharge  
(A-Bank)  
: Don't care  
*Note : 1. Column Mask (DQi=L : Mask, DQi=H : Non Mask)  
2. At Block Write, CA0-2 are ignored.  
(August, 2004, Version 1.1)  
33  
AMIC Technology, Corp.  
A45L9332A Series  
SMRS and Block/Normal Write @ Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
*Note1  
RAa  
RBa  
CBa  
A0-2  
A3,4,7,8  
A5  
RAa  
CAa  
RBa  
CBa  
RAa  
RAa  
CAa  
CAa  
CBa  
CBa  
RBa  
RBa  
CAa  
A6  
A9  
RAa  
A10  
WE  
DSF  
DQM  
I/O  
Mask  
Pixel  
Mask  
I/O  
Mask  
Color  
Color  
DQ  
DBa0 DBa1 DBa2 DBa3  
Row Active  
with WPB*  
Enable  
Load Color  
Register  
Load Color  
Register  
Load Color  
Register  
WPB* : Write-Per-Bit  
Masked Write  
with Auto  
Precharge  
(B-Bank)  
(B-Bank)  
Row Active  
with WPB*  
Enable  
Masked  
Bolck Write  
(A-Bank)  
Load Mask Register  
(A-Bank)  
: Don't care  
* Note : 1. At the next clock of special mode set command, new command is possible.  
(August, 2004, Version 1.1)  
34  
AMIC Technology, Corp.  
A45L9332A Series  
Page Read Cycle at Different Bank @Burst Length = 4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
*Note 1  
CS  
RAS  
CAS  
*Note 2  
RAa  
RAa  
CAa  
RBb  
RBb  
CBb  
CAc  
CBd  
CAe  
ADDR  
A10  
A9  
WE  
DSF  
Low  
DQM  
DQ  
(CL=2)  
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1  
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1  
DQ  
(CL=3)  
Read  
(A-Bank)  
Read  
(B-Bank)  
Read  
(A-Bank)  
Precharge  
(A-Bank)  
Row Active  
(B-Bank)  
Read  
(B-Bank)  
Row Active  
(A-Bank)  
Read  
(A-Bank)  
: Don't care  
* Note : 1.  
can be don’t care when  
, and  
RAS CAS  
are high at the clock high going edge.  
WE  
CS  
2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.  
(August, 2004, Version 1.1)  
35  
AMIC Technology, Corp.  
A45L9332A Series  
Page Write Cycle at Different Bank @Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
RAa  
Key  
CAa  
RBb  
RBb  
CBb  
CAc  
CBd  
ADDR  
A10  
A9  
RAa  
t
CDL  
WE  
DSF  
DQM  
DQ  
Mask  
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DAc2 DAc3 DBd0 DBd1 DBd2 DBd3  
Row Active  
(B-Bank)  
Write  
(B-Bank)  
Masked Write  
with auto  
precharge  
(A-Bank)  
Write with auto  
Precharge  
(B-Bank)  
Load Mask  
Register  
Row Active with  
Write-Per-Bit  
enable  
Masked Write  
(A-Bank)  
(A-Bank)  
: Don't care  
(August, 2004, Version 1.1)  
36  
AMIC Technology, Corp.  
A45L9332A Series  
Read & Write Cycle at Different Bank @Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
RAa  
CAa  
RBb  
CBb  
RAc  
CAc  
ADDR  
A10  
A9  
RAa  
RBb  
RAc  
t
CDL  
*Note 1  
WE  
DSF  
DQM  
DQ  
(CL=2)  
QAa0 QAa1 QAa2 QAa3  
DBb0 DBb1 DBb2 DBb3  
DBb0 DBb1 DBb2 DBb3  
QAc0 QAc1 QAc2  
QAc0 QAc1  
DQ  
(CL=3)  
QAa0 QAa1 QAa2 QAa3  
Row Active  
(A-Bank)  
Read  
(A-Bank)  
Precharge  
(A-Bank)  
Write  
(B-Bank)  
Read  
(A-Bank)  
Row Active  
(B-Bank)  
Row Active  
(A-Bank)  
: Don't care  
* Note : 1. tCDL should be met to complete write.  
(August, 2004, Version 1.1)  
37  
AMIC Technology, Corp.  
A45L9332A Series  
Read & Write Cycle with Auto Precharge I @Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
RAa  
RAa  
RBb  
RBb  
CAa  
CBb  
ADDR  
A10  
A9  
WE  
DSF  
DQMi  
DQ  
(CL=2)  
QAa0 QAa1 QAa2 QAa3  
DBb0 DBb1 DBb2 DBb3  
DBb0 DBb1 DBb2 DBb3  
DQ  
(CL=3)  
QAa0 QAa1 QAa2 QAa3  
Row Active  
(A-Bank)  
Read with  
Auto Precharge  
(A-Bank)  
Auto Precharge  
Start Point  
(A-Bank)  
Write with  
Auto Precharge  
(B-Bank)  
Auto Precharge  
Start Point  
(B-Bank)  
Row Active  
(B-Bank)  
: Don't care  
*Note : 1. tRCD should be controlled to meet minimum tRAS before internal precharge start.  
(In the case of Burst Length=1 & 2, BRSW mode and Block write)  
(August, 2004, Version 1.1)  
38  
AMIC Technology, Corp.  
A45L9332A Series  
Read & Write Cycle with Auto Precharge II @Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
Ra  
Rb  
Ca  
Cb  
Ra  
Ca  
ADDR  
A10  
Ra  
Rb  
Ra  
A9  
WE  
DSF  
DQM  
Qa0  
Qa1  
Qa0  
Qb0 Qb1  
Qa1 Qb0  
Qb2  
Qb3  
Da0  
Da0  
Da1  
Da1  
DQ  
(CL=2)  
Qb1  
Qb2  
Qb3  
DQ  
(CL=3)  
Read without  
Auto Precharge  
(B-Bank)  
Auto Precharge  
Strart Point  
Row Active  
(A-Bank)  
Read with  
Auto Pre  
Charge  
Precharge  
(B-Bank)  
Row Active  
(A-Bank)  
Write with  
Auto Precharge  
(A-Bank)  
(A-Bank)  
(A-Bank) *Note 1  
Row Active  
(B-Bank)  
: Don't care  
* Note : 1. When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.  
- if read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank  
auto precharge will start at B Bank read command input point.  
- Any command can not be issued at A Bank during tRP after A Bank auto precharge starts.  
(August, 2004, Version 1.1)  
39  
AMIC Technology, Corp.  
A45L9332A Series  
Read & Write Cycle with Auto Precharge III @Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
Ra  
Ca  
Rb  
Cb  
ADDR  
A10  
A9  
Ra  
Rb  
WE  
DSF  
DQM  
DQ  
(CL=2)  
Qa0  
Qa1  
Qa0  
Qa2 Qa3  
Qa1 Qa2  
Qb0  
Qb1  
Qb2  
Qb3  
DQ  
(CL=3)  
Qa3  
Qb0  
Qb1  
Db2  
Db3  
* Note 1  
Row Active  
(A-Bank)  
Read with  
Auto Preharge  
(A-Bank)  
Read with  
Auto Precharge  
(B-Bank)  
Auto Precharge  
Start Point  
(B-Bank)  
Auto Precharge  
Start Point  
(A-Bank)  
Row Active  
(B-Bank)  
: Don't care  
* Note : 1. Any command to A-bank is not allowed in this period.  
tRP is determined from at auto precharge start point  
(August, 2004, Version 1.1)  
40  
AMIC Technology, Corp.  
A45L9332A Series  
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full Page Only)  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
ADDR  
A10  
RAa  
RAa  
CAa  
CAb  
* Note 1  
* Note 1  
A9  
WE  
DSF  
DQM  
* Note 2  
1
1
DQ  
(CL=2)  
QAa1 QAa2 QAa3 QAa4  
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5  
QAa0  
2
2
DQ  
(CL=3)  
QAa0 QAa1 QAa2 QAa3 QAa4  
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5  
Read  
(A-Bank)  
Read  
(A-Bank)  
Precharge  
(A-Bank)  
Row Active  
(A-Bank)  
Burst Stop  
: Don't care  
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.  
2. About the valid DQ’s after burst stop, it is same as the case of  
interrupt.  
RAS  
Both cases are illustrated above timing diagram. See the label 1,2 on them.  
But at burst write, burst stop and interrupt should be compared carefully.  
RAS  
Refer the timing diagram of “Full page write burst stop cycle”.  
(August, 2004, Version 1.1)  
41  
AMIC Technology, Corp.  
A45L9332A Series  
Write Interrupted by Precharge Command & Write Burst Stop Cycle (@ Full Page Only)  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
RAa  
RAa  
CAa  
CAb  
ADDR  
A10  
A9  
* Note 1  
* Note 1  
t
BDL  
tRDL  
WE  
DSF  
* Note 3  
DQM  
* Note 2  
DAa0 DAa1 DAa2 DAa3 DAa4  
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5  
DQ  
Write  
(A-Bank)  
Write  
(A-Bank)  
Precharge  
(A-Bank)  
Row Active  
(A-Bank)  
Burst Stop  
: Don't care  
* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.  
2. Data-in at the cycle of burst stop command cannot be written into corresponding memory cell.  
It is defined by AC parameter of tBDL(=1CLK).  
3. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.  
It is defined by AC parameter of tRDL(2=CLK).  
DQM at write interrupted by precharge command is needed to ensure tRDL of 2CLK.  
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.  
Input data after Row precharge cycle will be masked internally.  
4. Burst stop is valid only at full page burst length.  
(August, 2004, Version 1.1)  
42  
AMIC Technology, Corp.  
A45L9332A Series  
Burst Read Single Bit Write Cycle @Burst Length=2, BRSW  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
High  
CS  
RAS  
CAS  
* Note 2  
RAa  
RAa  
CAa  
RAc  
CBc  
CAd  
RBb  
RBb  
CAb  
ADDR  
A10  
A9  
RAc  
WE  
DSF  
DQM  
DQ  
(CL=2)  
QAb0 QAb1  
DBc0  
DBc0  
QAd0 QAd1  
DAa0  
DAa0  
DQ  
(CL=3)  
QAb0 QAb1  
QAd0 QAd1  
Row Active  
(A-Bank)  
Read  
(A-Bank)  
Precharge  
(A-Bank)  
Row Active  
(A-Bank)  
Row Active  
(B-Bank)  
Write with  
Auto Precharge  
(B-Bank)  
Read with  
Auto Precharge  
(A-Bank)  
Write  
(A-Bank)  
: Don't care  
* Note : 1. BRSW mode is enabled by setting A9 “High” at MRS (Mode Register Set).  
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programed burst length.  
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.  
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,  
The next cycle starts the precharge.  
3. WPB function is also possible at BRSW mode.  
(August, 2004, Version 1.1)  
43  
AMIC Technology, Corp.  
A45L9332A Series  
Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
CS  
RAS  
CAS  
Ra  
Ca  
Cb  
Cc  
ADDR  
A10  
A9  
Ra  
WE  
DSF  
* Note 1  
DQM  
Qa0  
Qa1  
Qb0  
Qb1  
Dc0  
Dc2  
DQ  
Qa2  
Qa3  
t
SHZ  
tSHZ  
Clock  
Suspension  
Write  
DQM  
Row Active  
Read  
Read  
Read DQM  
Clock  
Suspension  
Write  
: Don't care  
* Note : 1. DQM needed to prevent bus contention.  
(August, 2004, Version 1.1)  
44  
AMIC Technology, Corp.  
A45L9332A Series  
Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
* Note 2  
SS  
t
SS  
t
t
SS  
tSS  
* Note 1  
*Note 3  
CS  
RAS  
CAS  
Ra  
Ca  
ADDR  
A10  
Ra  
A9  
WE  
DSF  
DQM  
DQ  
Qa0  
Qa1  
Qa2  
Precharge  
Power-down  
Exit  
Precharge  
Power-down  
Entry  
Read  
Precharge  
Row Active  
Active  
Power-down  
Exit  
Active  
Power-down  
Entry  
: Don't care  
* Note : 1. All banks should be in idle state prior to entering precharge power down mode.  
2. CKE should be set high at least “1CLK + tSS” prior to Row active command.  
3. Cannot violate minimum refresh specification. (32ms)  
(August, 2004, Version 1.1)  
45  
AMIC Technology, Corp.  
A45L9332A Series  
Self Refresh Entry & Exit Cycle  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
CLOCK  
CKE  
* Note 4  
* Note 2  
t
RC min.  
t
SS  
* Note 6  
* Note 1  
* Note 3  
t
SS  
* Note 5  
CS  
RAS  
CAS  
* Note 7  
* Note 7  
ADDR  
A10  
A9  
WE  
DSF  
DQM  
DQ  
Hi-Z  
Hi-Z  
Self Refresh Exit  
Auto Refresh  
Self Refresh Entry  
: Don't care  
* Note : TO ENTER SELF REFRESH MODE  
1. with CKE should be low at the same clock cycle.  
CS RAS CAS  
,
&
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.  
3. The device remains in self refresh mode as long as CKE stays “Low”.  
(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.  
TO EXIT SELF REFRESH MODE  
4. System clock restart and be stable before returning CKE high.  
5.  
starts from high.  
CS  
6. Minimum tRC is required after CKE going high to complete self refresh exit.  
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.  
If the system uses burst refresh.  
(August, 2004, Version 1.1)  
46  
AMIC Technology, Corp.  
A45L9332A Series  
Mode Register Set Cycle  
Auto Refresh Cycle  
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10  
CLOCK  
CKE  
High  
High  
*Note 2  
CS  
tRC  
RAS  
CAS  
* Note 1  
* Note 3  
Key  
Ra  
ADDR  
WE  
DSF  
DQM  
DQ  
Hi-Z  
Hi-Z  
Auto Refresh  
New Command  
: Don't care  
MRS  
New  
Command  
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.  
MODE REGISTER SET CYCLE  
* Note : 1.  
,
,
&
activation and DSF of low at the same clock cycle with address key will set internal mode  
WE  
CS RAS CAS  
register.  
2. Minimum 1 clock cycles should be met before new  
3. Please refer to Mode Register Set table.  
activation.  
RAS  
(August, 2004, Version 1.1)  
47  
AMIC Technology, Corp.  
A45L9332A Series  
Function Truth Table (Table 1)  
Current  
BA  
CS RAS  
DSF  
Address  
Action  
Note  
CAS  
WE  
State  
(A10)  
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
L
X
X
X
X
NOP  
NOP  
X
X
ILLEGAL  
ILLEGAL  
2
2
X
H
H
L
BA  
BA  
BA  
BA  
X
CA  
RA  
RA  
PA  
X
H
H
H
H
L
Row Active; Latch Row Address; Non-IO Mask  
L
H
L
Row Active; latch Row Address; IO Mask  
IDLE  
L
NOP  
4
5
L
L
H
L
ILLEGAL  
L
H
H
L
X
X
Auto Refresh or Self Refresh  
L
L
H
L
X
X
ILLEGAL  
L
L
OP Code  
Mode Register Access  
5
6
L
L
L
H
X
X
X
L
OP Code  
Special Mode Register Access  
X
H
H
H
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
NOP  
NOP  
X
ILLEGAL  
2
2
6
H
H
L
BA  
X
CA,AP Begin Read; Latch CA; Determine AP  
ILLEGAL  
L
H
L
X
L
BA  
BA  
BA  
BA  
X
CA,AP Begin Write; Latch CA; Determine AP  
CA,AP Block Write; Latch CA; Determine AP  
Row  
L
L
H
X
L
Active  
H
H
H
L
H
L
RA  
PA  
X
ILLEGAL  
L
Precharge  
L
L
H
X
L
ILLEGAL  
L
H
L
X
X
ILLEGAL  
L
L
X
X
ILLEGAL  
L
L
L
H
X
X
L
OP Code  
Special Mode Register Access  
NOP(Continue Burst to End →Row Active)  
NOP(Continue Burst to End →Row Active)  
Term burst →Row Active  
ILLEGAL  
X
H
H
H
H
H
H
H
L
X
H
H
H
L
X
H
L
X
X
X
X
X
X
X
L
H
L
X
H
H
L
BA  
X
CA,AP Term burst; Begin Read; Latch CA; Determine AP  
ILLEGAL  
3
L
H
L
X
Read  
L
BA  
BA  
BA  
BA  
X
CA,AP Term burst; Begin Write; Latch CA; Determine AP  
CA,AP Term burst; Block Write; Latch CA; Determine AP  
3
3
2
3
L
L
H
X
L
H
H
H
L
H
L
RA  
PA  
X
ILLEGAL  
L
Term Burst; Precharge timing for Reads  
L
L
H
X
ILLEGAL  
ILLEGAL  
L
X
X
X
(August, 2004, Version 1.1)  
48  
AMIC Technology, Corp.  
A45L9332A Series  
Function Truth Table (Table 1, Continued)  
Current  
BA  
CS RAS  
DSF  
Address  
Action  
Note  
CAS  
WE  
State  
(A10)  
H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
H
H
H
H
L
X
H
H
H
L
X
H
L
X
X
L
X
X
X
X
X
X
NOP(Continue Burst to End→Row Active)  
NOP(Continue Burst to End→Row Active)  
Term burst →Row Active)  
X
L
H
L
X
ILLEGAL  
H
H
L
BA  
X
CA,AP Term burst; Begin Read; Latch CA; Determine AP  
ILLEGAL  
3
Write  
L
H
L
X
L
BA  
BA  
BA  
BA  
X
CA,AP Term burst; Begin Write; Latch CA; Determine AP  
CA,AP Term burst; Block Write; Latch CA; Determine AP  
3
3
2
3
L
L
H
X
L
H
H
H
L
H
L
RA  
PA  
X
ILLEGAL  
L
Term Burst; Precharge timing for Writes  
ILLEGAL  
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
H
L
X
X
ILLEGAL  
X
H
H
H
H
L
X
H
H
L
X
X
NOP(Continue Burst to End→Precharge)  
NOP(Continue Burst to End→Precharge)  
ILLEGAL  
X
X
Read with  
Auto  
X
X
H
L
BA  
BA  
BA  
X
CA,AP ILLEGAL  
CA,AP ILLEGAL  
RA,PA ILLEGAL  
2
2
Precharge  
L
H
L
X
X
X
H
L
L
X
X
X
X
ILLEGAL  
2
X
H
H
H
H
L
X
H
H
L
X
NOP(Continue Burst to End→Precharge)  
NOP(Continue Burst to End→Precharge)  
ILLEGAL  
X
Write with  
Auto  
X
H
L
BA  
BA  
BA  
X
CA,AP ILLEGAL  
CA,AP ILLEGAL  
RA,PA ILLEGAL  
2
2
Precharge  
L
H
L
X
X
X
H
L
L
X
X
X
X
ILLEGAL  
2
X
H
H
H
L
X
H
H
L
X
NOP→Idle after tRP  
NOP→Idle after tRP  
ILLEGAL  
X
X
Precharge  
X
H
L
BA  
BA  
BA  
X
CA,AP ILLEGAL  
2
2
2
4
H
H
L
RA  
PA  
X
ILLEGAL  
L
NOP→Idle after tRP  
ILLEGAL  
L
X
X
H
L
X
H
H
H
L
X
H
H
L
X
X
NOP→Row Active after tBWC  
NOP→Row Active after tBWC  
ILLEGAL  
X
X
Block  
Write  
Recovering  
X
X
X
H
L
BA  
BA  
BA  
X
CA,AP ILLEGAL  
2
2
2
2
H
H
L
RA  
PA  
X
ILLEGAL  
L
Term Block Write: Precharge timing for Block Write  
ILLEGAL  
L
X
(August, 2004, Version 1.1)  
49  
AMIC Technology, Corp.  
A45L9332A Series  
Function Truth Table (Table 1, Continued)  
Current  
BA  
CS RAS  
DSF  
Address  
Action  
Note  
CAS  
WE  
State  
(A10)  
H
L
L
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP→Row Active after tRCD  
NOP→Row Active after tRCD  
ILLEGAL  
X
Row  
Activating  
X
H
L
BA  
BA  
BA  
X
CA,AP ILLEGAL  
2
2
2
2
H
H
L
RA  
PA  
X
ILLEGAL  
L
ILLEGAL  
L
X
X
X
X
X
X
ILLEGAL  
X
H
H
L
X
H
L
X
X
NOP→Idle after tRC  
NOP→Idle after tRC  
ILLEGAL  
X
X
Refreshing  
X
X
H
L
X
X
ILLEGAL  
L
X
X
ILLEGAL  
Abbreviations  
RA = Row Address (A0~A9)  
NOP = No Operation Command  
BA = Bank Address (A10)  
PA = Precharge All (A9)  
AP = Auto Precharge (A9)  
CA = Column Address (A0~A7)  
Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.  
2. Illegal to bank in specified state : Function may be legal in the bank indicated by BA, depending on the state of that  
bank.  
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.  
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).  
5. Illegal if any bank is not idle.  
6. Legal only if all banks are in idle or row active state.  
(August, 2004, Version 1.1)  
50  
AMIC Technology, Corp.  
A45L9332A Series  
Function Truth Table for CKE (Table 2)  
Current  
State  
CKE CKE  
CS  
RAS  
DSF Address  
Action  
Note  
CAS  
WE  
n-1  
n
H
X
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID  
L
L
H
H
H
H
H
L
7
7
Exit Self Refresh→ABI after tRC  
Exit Self Refresh→ABI after tRC  
ILLEGAL  
Self  
L
L
Refresh  
L
L
X
X
X
X
X
H
L
ILLEGAL  
L
L
X
X
X
X
H
H
L
ILLEGAL  
L
X
X
H
L
X
X
X
H
H
H
L
NOP (Maintain Self Refresh)  
INVALID  
H
L
X
H
H
H
H
H
L
8
8
Exit Power Down→ABI  
Exit Power Down→ABI  
ILLEGAL  
Both  
Bank  
L
Precharge  
Power  
L
L
L
L
X
X
X
X
X
H
L
ILLEGAL  
Down  
L
L
X
X
X
X
H
H
L
ILLEGAL  
L
X
X
H
L
X
X
X
H
H
H
L
NOP(Maintain Power Down Mode)  
Refer to Table 1  
H
H
H
H
H
H
H
H
L
H
L
Enter Power Down  
Enter Power Down  
ILLEGAL  
9
9
L
All  
Banks  
Idle  
L
L
L
L
X
X
H
L
ILLEGAL  
L
L
H
L
ILLEGAL  
L
L
L
Enter Self Refresh  
ILLEGAL  
9
L
L
L
L
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOP  
Any State  
Other than  
Listed  
H
H
L
H
L
Refer to Operations in Table 1  
Begin Clock Suspend next cycle  
Exit Clock Suspend next cycle  
Maintain clock Suspend  
10  
10  
H
L
Above  
L
Abbreviations : ABI = All Banks Idle  
Note: 7. After CKE’s low to high transition to exit self refresh mode. And a time of tRC(min) has to be elapse after CKE’s low to  
high transition to issue a new command.  
8. CKE low to high transition is asynchronous as if restarts internal clock.  
A minimum setup time “tSS + one clock” must be satisfied before any command other than exit.  
9. Power-down and self refresh can be entered only from the all banks idle state.  
10. Must be a legal command.  
(August, 2004, Version 1.1)  
51  
AMIC Technology, Corp.  
A45L9332A Series  
Ordering Information  
Part No.  
Cycle Time (ns)  
Clock Frequency (MHz)  
Access Time  
5.5 ns @ CL = 3  
5.5 ns @ CL = 3  
5.5 ns @ CL = 3  
5.5 ns @ CL = 3  
6.0 ns @ CL = 3  
6.0 ns @ CL = 3  
6.0 ns @ CL = 3  
6.0 ns @ CL = 3  
6.5 ns @ CL = 3  
6.5 ns @ CL = 3  
6.5 ns @ CL = 3  
6.5 ns @ CL = 3  
Package  
100 QFP  
A45L9332AF-6  
A45L9332AF-6F  
A45L9332AE-6  
A45L9332AE-6F  
A45L9332AF-7  
A45L9332AF-7F  
A45L9332AE-7  
A45L9332AE-7F  
A45L9332AF-8  
A45L9332AF-8F  
A45L9332AE-8  
A45L9332AE-8F  
166  
166  
166  
166  
143  
143  
143  
143  
125  
125  
125  
125  
100 Pb-Free QFP  
100 LQFP  
6
100 Pb-Free LQFP  
100 QFP  
100 Pb-Free QFP  
100 LQFP  
7
100 Pb-Free LQFP  
100 QFP  
100 Pb-Free QFP  
100 LQFP  
8
100 Pb-Free LQFP  
* QFP (Height = 3.0mm Max)  
LQFP (Height = 1.4mm Max)  
(August, 2004, Version 1.1)  
52  
AMIC Technology, Corp.  
A45L9332A Series  
Package Information  
QFP 100L Outline Dimensions  
unit: inches/mm  
H
E
A
2
A1  
E
y
80  
51  
81  
50  
31  
100  
1
30  
b
c
e
θ
Dimensions in inches  
Dimensions in mm  
Symbol  
Min.  
0.004  
0.107  
0.010  
Nom.  
Max.  
-
Min.  
Nom.  
Max.  
A1  
A2  
b
-
0.112  
-
0.100  
2.723  
0.26  
-
2.85  
-
-
0.117  
0.014  
2.977  
0.36  
0.158  
c
0.0057 0.006 0.0063 0.142  
0.150  
HE  
E
0.905  
0.783  
0.669  
0.547  
0.020  
0.025  
0.057  
-
0.913  
0.787  
0.677  
0.551  
0.026  
0.031  
0.063  
-
0.921 22.950 23.200 23.450  
0.791 19.900 20.000 20.100  
0.685 16.950 17.200 17.450  
0.555 13.900 14.000 14.100  
HD  
D
e
0.032  
0.037  
0.069  
0.004  
8°  
0.500  
0.650  
1.450  
-
0.650  
0.800  
0.950  
1.750  
0.100  
8°  
L
0.800  
L1  
y
1.600  
-
-
-
θ
0°  
0°  
Notes:  
1. Dimensions D and E do not include mold protrusion.  
2. Dimensions b does not include dambar protrusion.  
Total in excess of the b dimension at maximum material condition.  
Dambar cannot be located on the lower radius of the foot.  
(August, 2004, Version 1.1)  
53  
AMIC Technology, Corp.  
A45L9332A Series  
Package Information  
LQFP 100L Outline Dimensions  
unit: inches/mm  
HE  
A
2
A1  
E
y
80  
51  
81  
50  
31  
100  
1
30  
b
c
e
θ
Dimensions in inches  
Dimensions in mm  
Symbol  
Min.  
0.002  
0.053  
0.011  
0.005  
0.860  
0.783  
0.624  
0.547  
Nom.  
-
Max.  
-
Min.  
Nom.  
-
Max.  
A1  
A2  
b
0.05  
1.35  
-
0.055  
0.013  
-
0.057  
0.015  
0.008  
0.872  
0.791  
0.636  
0.555  
1.40  
1.45  
0.27  
0.32  
0.37  
c
0.12  
-
0.20  
HE  
E
0.866  
0.787  
0.630  
0.551  
0.026 BSC  
0.024  
0.039 REF  
-
21.85  
19.90  
15.85  
13.90  
22.00  
20.00  
16.00  
14.00  
0.65 BSC  
0.60  
22.15  
20.10  
16.15  
14.10  
HD  
D
e
L
0.018  
0.030  
0.45  
0.75  
L1  
y
1.00 REF  
-
-
0.004  
-
0.1  
θ
0°  
3.5°  
7°  
0°  
3.5°  
7°  
Notes:  
1. Dimensions D and E do not include mold protrusion.  
2. Dimensions b does not include dambar protrusion.  
Total in excess of the b dimension at maximum material condition.  
Dambar cannot be located on the lower radius of the foot.  
(August, 2004, Version 1.1)  
54  
AMIC Technology, Corp.  

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