LP61L1024X-12F [AMICC]
Standard SRAM, 128KX8, 12ns, CMOS, PDSO32;
| 型号： | LP61L1024X-12F |
| 厂家： | 
AMIC TECHNOLOGY |
| 描述： | Standard SRAM, 128KX8, 12ns, CMOS, PDSO32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Document Title
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Revision History
Rev. No. History
Issue Date
Remark
2.0
2.1
2.2
Add product family and 32-pin TSSOP package
Add 36 ball BGA package type
May 9, 2002
Final
August 22, 2002
August 9, 2004
Add Pb-Free package type
(August, 2004, Version 2.2)
AMIC Technology, Corp.
LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Features
General Description
Single +3.3V power supply
Access times: 12/15 ns (max.)
The LP61L1024 is a low operating current 1,048,576-bit static
random access memory organized as 131,072 words by 8 bits
Current: Operating: 170mA (max.)
Standby: 10mA (max.)
and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention is guaranteed at a power supply voltage as low
as 2.0V.
Data retention voltage: 2.0V (min.)
Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32-pin
TSSOP and 36-pin CSP packages
Product Family
Package
Type
Power Dissipation
Operating
Temperature
VCC
Range
Product
Family
Speed
Data Retention
Standby
Operating
(ICC1, Typ.)
(ICCDR, Typ.)
(ISB1, Typ.)
32L SOJ
32L TSOP
32L TSSOP
36B µBGA
LP61L1024
3V ~ 3.6V
12/15 ns
0.4mA
0.5mA
130mA
0°C ~ 70°C
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
(August, 2004, Version 2.2)
1
AMIC Technology, Corp.
LP61L1024
Pin Configurations
SOJ
TSOP / TSSOP
CSP (Chip Size Package)
36-pin Top View
1
VCC
A15
CE2
32
31
30
NC
16
1
A16
2
1
2
3
4
5
6
A14
3
4
5
6
A8
WE
A13
A8
A0
A1
A2
NC
WE
A3
A4
A6
A7
A12
A7
A6
A5
A4
A3
A2
29
28
27
A
B
I/O
I/O
4
I/O
I/O
0
C
D
E
F
5
NC
A5
1
A9
7
26
GND
VCC
VCC
GND
8
A11
OE
25
24
23
22
9
A10
10
11
12
13
14
15
16
I/O
I/O
6
NC
CE1
A11
NC
A16
A12
I/O
I/O
2
CE1
A1
A0
3
G
H
7
OE
A15
A13
I/O
8
21
20
19
18
17
I/O
I/O
I/O
1
2
3
I/O
I/O
I/O
I/O
7
6
5
4
A9
A10
A14
32
17
GND
Pin No.
1
2
3
4
5
6
7
8
9
10
A16
26
11
A14
27
12
A12
28
13
A7
29
14
A6
15
16
A4
32
Pin
Name
A11
17
A9
18
A2
A8
19
A1
A13
20
WE
CE2
22
A15
23
VCC
24
NC
25
A5
31
Pin No.
21
30
Pin
Name
I/O
3
I/O8
A3
A0
I/O
1
I/O
2
GND I/O
4
I/O5
I/O6
I/O7
CE1
A10
OE
Block Diagram
Pin Description
Pin No.
Symbol
Description
VCC
GND
2 - 12, 23,
25 - 28, 31
A0 - A16
Address Inputs
A0
256 X 4096
MEMORY ARRAY
29
24
22
Write Enable
Output Enable
Chip Enable
WE
OE
DECODER
A14
A15
A16
CE1
CE2
I/O
I/O
1
30
Chip Enable
INPUT
DATA
COLUMN I/O
1
NC
No Connection
Data Input/Outputs
Power Supply
Ground
CIRCUIT
8
13 - 15, 17 - 21
I/O1 - I/O8
VCC
32
16
GND
CE2
CE1
OE
CONTROL
CIRCUIT
WE
(August, 2004, Version 2.2)
2
AMIC Technology, Corp.
LP61L1024
Recommended DC Operating Conditions
(TA = 0°C to + 70°C)
Symbol
VCC
GND
VIH
Parameter
Supply Voltage
Ground
Min.
3.0
0
Typ.
Max.
Unit
V
3.3
0
-
3.6
0
V
Input High Voltage
Input Low Voltage
Output Load
2.2
-0.3
-
VCC + 0.3
V
VIL
0
-
+0.8
30
1
V
CL
pF
-
TTL
Output Load
-
-
Absolute Maximum Ratings*
*Comments
VCC to GND ...............................................-0.5V to +7.0V
IN, IN/OUT Volt to GND..................... -0.5V to VCC +0.5V
Operating Temperature, Topr .......................0°C to +70°C
Storage Temperature, Tstg..................... -55°C to +125°C
Temperature Under Bias, Tbias................ -10°C to +85°C
Power Dissipation, Pt................................................ 1.0W
Soldering Temp. & Time ............................. 260°C, 10 sec
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C, VCC = 3.3V + 10%, GND = 0V)
LP61L1024-12/15
Symbol
Parameter
Unit
Conditions
Min.
Max.
Input Leakage Current
Output Leakage Current
-
-
2
2
VIN = GND to VCC
⏐ILI⏐
µA
µA
⏐ILO⏐
CE1 = VIH or CE2 = VIL or
OE = VIH or WE = VIL
VI/O = GND to VCC
ICC1 (1)
Dynamic Operating Current
-
170
mA
CE1 = VIL, CE2 = VIH
II/O = 0 mA
ISB
-
-
30
10
mA
mA
CE1 = VIH or CE2 = VIL
ISB1
CE1 ≥ VCC - 0.2V,
CE2 ≥ VCC - 0.2V,
VIN ≤ 0.2V or VIN ≥ VCC - 0.2V
Standby Power
Supply Current
ISB2
-
10
mA
CE1 ≤ 0.2V, CE2 ≤ 0.2V
VIN ≤ 0.2V or VIN ≥ VCC - 0.2V
VOL
VOH
Output Low Voltage
Output High Voltage
-
0.4
-
V
V
IOL = 8 mA
IOH = -4 mA
2.4
Note: 1. ICC1 is dependent on output loading, cycle rates, and Read/Write patterns
(August, 2004, Version 2.2)
3
AMIC Technology, Corp.
LP61L1024
Truth Table
Mode
CE2
I/O Operation
Supply Current
CE1
H
OE
X
WE
X
X
L
High Z
High Z
High Z
DOUT
ISB, ISB1
ISB, ISB2
ICC1
Standby
X
X
X
Output Disable
Read
L
H
H
H
H
L
H
L
H
ICC1
Write
L
X
L
DIN
ICC1
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
CIN*
Parameter
Min.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
8
CI/O*
Input/Output Capacitance
10
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0°C to +70°C, VCC = 3.3V + 10, GND = 0V)
LP61L1024-12
Min. Max.
LP61L1024-15
Symbol
Parameter
Unit
Min.
Max.
Read Cycle
tRC
tAA
Read Cycle Time
Address Access Time
12
-
15
-
-
ns
ns
ns
-
-
12
12
15
15
tACE1
Chip Enable Access Time
-
CE1
CE2
tACE2
tOE
-
-
12
7
-
-
15
9
ns
ns
ns
Output Enable to Output Valid
Chip Enable to Output in Low Z
tCLZ1
3
-
5
-
CE1
CE2
tCLZ2
tOLZ
3
2
-
-
-
5
2
-
-
-
ns
ns
ns
Output Enable to Output in Low Z
Chip Disable to Output in High Z
tCHZ1
7
10
CE1
CE2
tCHZ2
tOHZ
tOH
-
7
7
-
-
10
9
ns
ns
ns
Output Disable to Output in High Z
Output Hold from Address Change
2
3
2
5
-
(August, 2004, Version 2.2)
4
AMIC Technology, Corp.
LP61L1024
AC Characteristics (continued)
LP61L1024-12
Min. Max.
LP61L1024-15
Min. Max.
Unit
Symbol
Parameter
Write Cycle
tWC
tCW
tAS
Write Cycle Time
12
-
15
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End of Write
Address Setup Time of Write
Address Valid to End of Write
Write Pulse Width
10
0
-
-
12
0
-
-
tAW
tWP
tWR
tWHZ
tDW
tDH
10
8
-
12
10
0
-
-
-
Write Recovery Time
0
-
-
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
7
-
0
8
-
8
10
0
0
-
-
tOW
5
-
5
-
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
Timing Waveforms
Read Cycle 1(1, 2, 4)
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
(August, 2004, Version 2.2)
5
AMIC Technology, Corp.
LP61L1024
Read Cycle 2 (1, 3, 4, 6)
CE1
tACE1
5
tCLZ1
5
tCHZ1
DOUT
Read Cycle 3 (1, 4, 7, 8)
CE2
tACE2
5
tCHZ2
5
tCLZ2
DOUT
Read Cycle 4 (1)
tRC
Address
tAA
OE
tOE
tOH
5
tOLZ
CE1
tACE1
5
tCHZ1
5
tCLZ2
CE2
5
tACE2
tOHZ
5
5
tCLZ2
tCHZ2
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
(August, 2004, Version 2.2)
6
AMIC Technology, Corp.
LP61L1024
Timing Waveforms (continued)
Write Cycle 1(6)
(Write Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
CE1
CE2
(4)
(4)
1
2
tAS
tWP
WE
DIN
tDH
tDW
tWHZ
tOW
DOUT
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
CE1
CE2
(4)
(4)
1
tAS
5
tCW
2
tWP
WE
DIN
tDW
tDH
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
(August, 2004, Version 2.2)
7
AMIC Technology, Corp.
LP61L1024
AC Test Conditions
Input Pulse Levels
0V to 3.0V
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
3 ns
1.5V
See Figures 1 and 2
+3.3V
+3.3V
320Ω
320Ω
I/O
I/O
30pF*
5pF*
350Ω
350Ω
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Data Retention Characteristics (TA = 0°C to 70°C)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V or
CE2 ≤ 0.2V
VDR1
2
3.6
V
VCC for Data Retention
CE2 ≤ 0.2V
CE1 ≥ VCC - 0.2V or
CE1 ≤ 0.2V
VDR2
2
3.6
5
V
VCC = 3.0V
CE1 ≥ VCC - 0.2V
CE2 ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
ICCDR1
mA
-
-
Data Retention Current
VCC = 3.0V
CE2 ≤ 0.2V
CE1 ≤ 0.2V
ICCDR2
5
mA
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
tCDR
tR
Chip Disable to Data Retention Time
Operation Recovery Time
0
5
-
-
ns
See Retention Waveform
ms
(August, 2004, Version 2.2)
8
AMIC Technology, Corp.
LP61L1024
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
DATA RETENTION MODE
VCC
CE1
3.0V
3.0V
t
CDR
t
R
VDR ≥ 2V
VIH
VIH
CE1
≥ VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
DATA RETENTION MODE
VCC
CE2
3.0V
3.0V
t
CDR
t
R
VDR ≥ 2V
VIL
VIL
CE2
≤ 0.2V
Ordering Information
Part No.
Operating Current
Max. (mA)
Standby Current
Max. (mA)
Access Time (ns)
Package
LP61L1024S-12
LP61L1024S-12F
LP61L1024V-12
LP61L1024V-12F
LP61L1024X-12
LP61L1024X-12F
LP61L1024U-12
LP61L1024U-12F
LP61L1024S-15
LP61L1024S-15F
LP61L1024V-15
LP61L1024V-15F
LP61L1024X-15
LP61L1024X-15F
LP61L1024U-15
LP61L1024U-15F
32L SOJ (300 mil)
32L Pb-Free SOJ (300 mil)
32L TSOP
32L Pb-Free TSOP
32L TSSOP
12
170
10
32L Pb-Free TSSOP
36L CSP
36L Pb-Free CSP
32L SOJ (300 mil)
32L Pb-Free SOJ (300 mil)
32L TSOP
32L Pb-Free TSOP
32L TSSOP
15
170
10
32L Pb-Free TSSOP
36L CSP
36L Pb-Free CSP
(August, 2004, Version 2.2)
9
AMIC Technology, Corp.
LP61L1024
Package Information
SOJ 32/32LD (300mil BODY) Outline Dimensions
unit: inches/mm
b
D
32
17
F
F
BASE METAL
WITH PLATING
DETAIL "A"
SECTION F-F
1
16
DETAIL "A"
H
E
b
1
y
y
s
e
b
e
1
SEATING PLANE
0.004
y
Dimensions in inches
Dimensions in mm
Symbol
Min.
0128
0.052
0.095
0.016
0.026
0.006
0.820
0.330
0.295
0.260
-
Nom.
0.132
-
Max.
0.140
-
Min.
3.25
2.08
2.41
0.41
0.66
0.15
Nom.
3.35
-
Max.
3.56
-
A
A1
A2
b
0.100
0.018
0.028
0.008
0.825
0.335
0.300
0.267
0.050
-
0.105
0.020
0.032
0.012
0.830
0.340
0.305
0.274
-
2.54
0.46
0.71
0.20
20.96
8.51
7.62
6.78
1.27
-
2.67
0.51
0.81
0.30
21.08
8.63
7.75
6.96
-
b1
c
D
20.83
HE
E
8.39
7.49
e
1
6.61
e
s
y
-
-
-
-
0.048
0.004
1.22
0.10
-
-
-
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E doesn't include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 2.2)
10
AMIC Technology, Corp.
LP61L1024
Package Information
TSOP 32L TYPE I (8 X 20mm) Outline Dimensions
unit: inches/mm
D
12.0°
GAUGE PLANE
θ
L
L
E
H
D
Detail "A"
Detail "A"
y
S
b
0.10(0.004)
M
Symbol
Dimensions in inches
Dimensions in mm
1.20 Max.
0.10±0.05
1.00±0.05
0.20±0.03
0.15±0.02
18.40±0.10
8.00±0.10
0.50 TYP.
20.00±0.20
0.50±0.10
0.80 TYP.
0.425 TYP.
0.10 Max.
0° ~ 6°
A
A1
A2
b
0.047 Max.
0.004±0.002
0.039±0.002
0.008±0.001
0.006±0.001
0.724±0.004
0.315±0.004
0.020 TYP.
0.787±0.007
0.020±0.004
0.031 TYP.
0.0167 TYP.
0.004 Max.
0° ~ 6°
c
D
E
e
HD
L
LE
S
Y
θ
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not include resin fins.
3. Dimension e is for PC Board surface mount pad pitch design
1
reference only.
4. Dimension S includes end flash.
(August, 2004, Version 2.2)
11
AMIC Technology, Corp.
LP61L1024
Package Information
TSSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
θ
L
L
E
D
1
D
Detail "A"
Detail "A"
0.076MM
S
b
SEATING PLANE
Dimensions in inches
Dimensions in mm
Symbol
Min
-
Nom
-
Max
Min
Nom
-
Max
-
A
A1
A2
b
0.049
-
1.25
-
-
-
0.002
0.037
0.007
0.05
0.95
0.17
0.039
0.008
0.041
0.009
1.00
0.20
0.150
8.00
0.50 TYP
1.05
0.23
0.158
8.10
c
0.0056 0.0059 0.0062 0.142
E
0.311
0.315
0.020 TYP
0.528
0.319
7.90
e
D
D1
L
0.520
0.461
0.012
0.535
0.469
0.028
13.20
11.70
0.30
13.40
11.80
0.50
13.60
11.90
0.70
0.465
0.020
LE
S
0.0275 0.0315 0.0355 0.700
0.0109 TYP
0.800
0.278 TYP
3°
0.900
θ
0°
3°
5°
0°
5°
Notes:
1. The maximum value of dimension D1 includes end flash.
2. Dimension E does not include resin fins.
3. Dimension S includes end flash.
(August, 2004, Version 2.2)
12
AMIC Technology, Corp.
LP61L1024
Package Information
36LD CSP (6 x 8 mm) Outline Dimensions
unit: mm
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
S
S
0.10
0.25
C
C A B
Ball*A1 CORNER
b (36X)
6
5 4 3 2 1
1
2 3 4 5 6
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D1
A
SIDE VIEW
D
0.20(4X)
C
SEATING PLANE
Dimensions in mm
Symbol
MIN. NOM. MAX.
A
A1
A2
D
1.00
0.16
0.48
5.80
7.80
---
1.10
0.21
0.53
6.00
8.00
3.75
5.25
0.75
0.30
1.20
0.26
0.58
6.20
8.20
---
E
D1
E1
e
---
---
---
---
b
0.25
0.35
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS
OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
4. THEERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE
SOLDER BALL AND THE BODY EDGE.
(August, 2004, Version 2.2)
13
AMIC Technology, Corp.
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