FS6054(28SOIC)_技术文档

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

1.0 Features

2.0 Description

The FS6050 family of CMOS clock fanout buffer ICs are

designed for high-speed motherboard applications, such

as Intel Pentium^®II PC100-based systems with 100MHz

SDRAM.

•

Generates up to eighteen low-skew, non-inverting

clocks from one clock input

•

Supports up to four SDRAM DIMMs

2

ä

Uses either I C -bus or SMBus serial interface with

Read and Write capability for individual clock output

control

Up to eighteen buffered, non-inverting clock outputs are

fanned-out from one clock input. Individual clocks are

skew matched to less than 250ps at 100MHz. Multiple

power and ground supplies reduce the effects of supply

noise on device performance.

•

Output enable pin tristates all clock outputs to facili-

tate board testing

Under I²C-bus control, individual clock outputs may be

turned on or off. An active-low output enable is available

to force all the clock outputs to a tristate level for system

testing.

•

Clock outputs skew-matched to less than 250ps

Less than 5ns propagation delay

Output impedance: 17Ω at 0.5V_DD

Serial interface I/O meet I²C specifications; all other

I/O are LVTTL/LVCMOS-compatible

•

Five differerent pin configurations available:

Figure 2: Pin Configuration (FS6050)

•

FS6050: 18 clock outputs in a 48-pin SSOP

FS6051: 10 clock outputs in a 28-pin SOIC, SSOP

FS6053: 13 clock outputs in a 28-pin SOIC

FS6054: 14 clock outputs in a 28-pin SOIC

FS6050

Figure 1: Block Diagram (FS6050)

VDD

SDRAM_(0:1)

VSS

VDD

VDD_I²C

SDRAM_(2:3)

VSS

VDD

SDA

Serial

18

48-pin SSOP

Interface

SDRAM_(4:5)

SCL

VSS

VSS_I²C

VDD

Figure 3: Pin Configuration (FS6051)

SDRAM_(6:7)

VSS

VDD

CLK_IN

SDRAM_(8:9)

VSS

VDD

SDRAM_(10:11)

VSS

VDD

SDRAM_(12:13)

VSS

VDD

FS6051

SDRAM_(14:15)

VSS

VDD

SDRAM_16

VSS

VDD

OE

SDRAM_17

VSS

28-pin SOIC, SSOP

FS6050

Additional pin configurations are noted on Page 2.

Intel and Pentium are registered trademarks of Intel Corporation. I²C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifica-

tions as may be required to permit improvements in the design of its products.

3.4.02

ISO9001

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

Table 1: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI^U= Input with Internal Pull-Up; DI_D= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN (FS6050) PIN (FS6051) PIN (FS6053) PIN (FS6054)

TYPE

NAME

DESCRIPTION

11

25

24

4

5

8

9

15

14

2

3

6

7

-

9

15

14

2

3

6

7

-

10

11

18

19

-

9

15

14

2

3

6

7

-

10

11

18

19

-

DI

DI^U

DI^UO

DO

DI^U

CLK_IN

SCL

SDA

Clock input for SDRAM clock outputs

Serial clock input

Serial data input/output

SDRAM_0

SDRAM_1

SDRAM_2

SDRAM_3

SDRAM_4

SDRAM_5

SDRAM_6

SDRAM_7

SDRAM_8

SDRAM_9

SDRAM_10

SDRAM_11

SDRAM_12

SDRAM_13

SDRAM_14

SDRAM_15

SDRAM_16

SDRAM_17

OE

9

SDRAM clock outputs (Byte 0)

SDRAM clock outputs (Byte 1)

13

14

17

18

31

32

35

36

40

41

44

45

21

28

38

-

22

23

26

27

11

18

20

22

23

26

27

12

-

22

23

26

27

12

17

20

SDRAM feedback clock outputs (Byte 2)

-

Output enable tristates all clock outputs when low

3, 7, 12, 16,

20, 29, 33, 37,

42, 46

1, 5, 10, 19,

24, 28

1, 5, 20, 24,

28

1, 5, 24, 28

13

P

VDD

VDD_I²C

VSS

3.3V ± 5% power supply for SDRAM clock buffers

3.3V ± 5% power supply for serial communications

Ground for SDRAM clock buffers

23

13

6, 10, 15, 19,

22, 27, 30, 34,

39, 43

4, 8, 12, 17,

21, 25

4, 8, 17, 21,

25

4, 8, 21, 25

26

16

-

16

-

16

-

P

-

VSS_I²C

(reserved)

Ground for serial communications

Reserved

1, 2, 47, 48

Figure 4: Pin Configuration (FS6053)

Figure 5: Pin Configuration (FS6054)

FS6054

FS6053

3.4.02

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Low-Skew Clock Fanout Buffer ICs

3.2

Register Programming

3.0 Programming Information

A logic-one written to a valid bit location turns on the as-

signed output clock. Likewise, a logic-zero written to a

valid bit location turns off the assigned output clock.

Table 2: Clock Enable

CONTROL INPUTS

CLOCK OUTPUTS (MHz)

Any unused or reserved register bits should be cleared to

zero.

OE

SDRAM_0:17

Serial bits are written to this device in the order shown in

Table 3.

0

1

tristate

CLK_IN

Table 3: Register Summary

3.1

Power-Up Initialization

SERIAL BIT

DATA BYTE

CLOCK OUTPUT

All outputs are enabled and active upon power-up, and all

0

1

2

3

4

5

6

7

8

(MSB)

SDRAM_7

SDRAM_6

SDRAM_5

SDRAM_4

SDRAM_3

SDRAM_2

SDRAM_1

SDRAM_0

SDRAM_15

SDRAM_14

SDRAM_13

SDRAM_12

SDRAM_11

SDRAM_10

SDRAM_9

SDRAM_8

SDRAM_17

SDRAM_16

Reserved

output control register bits are initialized to one.

The outputs must be configured at power-up and are not

expected to be configured during normal operation. Inac-

tive outputs are held low and are disabled from switching.

Byte 0

SDRAM Control Register 0

3.1.1 Unused Outputs

Outputs that are not used in versions of this device with a

reduced pinout are still operational internally. To reduce

power dissipation and crosstalk effects from the unloaded

outputs, it is recommended that these outputs be shut off

via the Control Registers.

(LSB)

(MSB)

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

Byte 1

SDRAM Control Register 1

(LSB)

(MSB)

Byte 2

Reserved

SDRAM Control Register 2

(LSB)

Reserved

3.4.02

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FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

Table 4: Byte 0 - SDRAM Control Register 0

REGISTER

BIT

CLOCK

OUTPUT

OUTPUT PIN

(FS6050)

OUTPUT PIN

(FS6051)

OUTPUT PIN

(FS6053)

OUTPUT PIN

(FS6054)

DESCRIPTION

7

6

5

4

3

2

1

0

SDRAM_7

SDRAM_6

SDRAM_5

SDRAM_4

SDRAM_3

SDRAM_2

SDRAM_1

SDRAM_0

On (1) / Off (0)

Pin 18

Pin 17

Pin 14

Pin 13

Pin 9

Pin 8

Pin 5

Pin 4

-

Pin 11

Pin 10

-

Pin 11

Pin 10

-

Pin 7

Pin 6

Pin 3

Pin 2

Pin 7

Pin 6

Pin 3

Pin 2

Pin 7

Pin 6

Pin 3

Pin 2

Table 5: Byte 1 - SDRAM Control Register 1

REGISTER

BIT

CLOCK

OUTPUT

OUTPUT PIN

(FS6050)

OUTPUT PIN

(FS6051)

OUTPUT PIN

(FS6053)

OUTPUT PIN

(FS6054)

DESCRIPTION

15

14

13

12

11

10

9

SDRAM_15

SDRAM_14

SDRAM_13

SDRAM_12

SDRAM_11

SDRAM_10

SDRAM_9

SDRAM_8

On (1) / Off (0)

Pin 45

Pin 44

Pin 41

Pin 40

Pin 36

Pin 35

Pin 32

Pin 31

Pin 27

Pin 26

Pin 23

Pin 22

Pin 27

Pin 26

Pin 23

Pin 22

-

Pin 27

Pin 26

Pin 23

Pin 22

-

Pin 19

Pin 18

Pin 19

Pin 18

8

Table 6: Byte 2 - SDRAM Control Register 2

REGISTER

BIT

CLOCK

OUTPUT

OUTPUT PIN

(FS6050)

OUTPUT PIN

(FS6051)

OUTPUT PIN

(FS6053)

OUTPUT PIN

(FS6054)

DESCRIPTION

23

22

21

20

19

18

17

16

SDRAM_17

SDRAM_16

On (1) / Off (0)

Pin 28

Pin 21

Pin 18

Pin 11

-

Pin 17

Pin 12

Reserved (set to 0)

-

Reserved (set to 0)

3.4.02

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Low-Skew Clock Fanout Buffer ICs

4.1.4 Data Valid

4.0 Dual Serial Interface Control

The state of the SDA line represents valid data if the SDA

This integrated circuit is a read/write slave device that

supports both the Inter IC Bus (I²C-bus) and the System

Management Bus (SMBus) two-wire serial interface pro-

tocols. The unique device address that is written to the

device determines whether the part expects to receive

SMBus commands or I²C commands. Since SMBus is

derived from the I²C-bus, the protocol for both bus types

is very similar.

In general, the bus has to be controlled by a master de-

vice that generates the serial clock SCL, controls bus

access, and generates the START and STOP conditions

while the device works as a slave. Both master and slave

can operate as a transmitter or receiver, but the master

device determines which mode is activated. A device that

sends data onto the bus is defined as the transmitter, and

a device receiving data as the receiver.

line is stable for the duration of the high period of the SCL

line after a START condition occurs. The data on the

SDA line must be changed only during the low period of

the SCL signal. There is one clock pulse per data bit.

Each data transfer is initiated by a START condition and

terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions

is determined by the master device, and can continue

indefinitely. However, data that is overwritten to the de-

vice after the data registers are filled will overflow from

the last register into the first register, then the second,

and so on, in a first-in, first-overwritten fashion.

4.1.5 Acknowledge

When addressed, the receiving device is required to gen-

erate an Acknowledge after each byte is received. The

master device must generate an extra clock pulse to co-

incide with the Acknowledge bit. The acknowledging de-

vice must pull the SDA line low during the high period of

the master acknowledge clock pulse. Setup and hold

times must be taken into account.

Bus logic levels and timing parameters noted herein fol-

low I²C-bus convention. Logic levels are based on a per-

centage of VDD. A logic-one corresponds to a nominal

voltage of VDD, while a logic-zero corresponds to ground

(VSS).

The master must signal an end of data to the slave by not

generating an acknowledge bit on the last byte that has

been read (clocked) out of the slave. In this case, the

slave must leave the SDA line high to allow the master to

generate a STOP condition.

4.1

Bus Conditions

Data transfer on the bus can only be initiated when the

bus is not busy. During the data transfer, the data line

(SDA) must remain stable whenever the clock line (SCL)

is high. Changes in the data line when the clock line is

high is interpreted by the device as a START or STOP

condition. Both I²C-bus and SMBus protocols define the

following conditions on the bus. Refer to Figure 12: Bus

Timing Data for more information.

4.2

Bus Operation and Commands

All programmable registers can be accessed via the bi-

directional two wire digital interface. The device accepts

the Random Register Read/Write and the Sequential

Register Read/Write I²C commands. The device also

supports the Block Read/Write SMBus commands.

4.1.1 Not Busy

Both the data (SDA) and clock (SCL) lines remain high to

indicate the bus is not busy.

4.2.1 I²C-bus and SMBus Device Addressing

After generating a START condition, the bus master

broadcasts a seven-bit device address followed by a R/W

bit. Note that every device on an I²C-bus or SMBus must

have a unique address to avoid bus conflicts.

4.1.2 START Data Transfer

A high to low transition of the SDA line while the SCL in-

put is high indicates a START condition. All commands to

the device must be preceded by a START condition.

For an SMBus interface, the address of the device is:

A6

A5

A4

A3

A2

A1

A0

4.1.3 STOP Data Transfer

1

0

1

0

1

A low to high transition of the SDA line while SCL is held

high indicates a STOP condition. All commands to the

device must be followed by a STOP condition.

3.4.02

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Low-Skew Clock Fanout Buffer ICs

For an I²C-bus interface, the device can support two de-

vice addresses to permit multiple devices on one I²C-bus.

The A2 address bit is ignored and can be set to either a

one or a zero.

4.2.4 I²C-bus: Sequential Register Write Procedure

Sequential write operations, as shown in Figure 8, allow

the master to write to each register in order. The register

pointer is automatically incremented after each write. This

procedure is more efficient than the Random Register

Write if several registers must be written.

Therefore, for an I²C-bus interface the device address is:

A6

A5

A4

A3

A2

A1

A0

1

0

1

X

0

To initiate a write procedure, the R/W bit that is transmit-

ted after the seven-bit I²C device address is a logic-low.

This indicates to the addressed slave device that a reg-

ister address will follow after the slave device acknowl-

edges its device address. The register address is written

into the slave’s address pointer. Following an acknowl-

edge by the slave, the master is allowed to write data up

to the last addressed register before the register address

pointer overflows back to the beginning address. An ac-

knowledge by the device between each byte of data must

occur before the next data byte is sent.

Registers are updated every time the device sends an

acknowledge to the host. The register update does not

wait for the STOP condition to occur. Registers are

therefore updated at different times during a Sequential

Register Write.

4.2.2 I²C-bus: Random Register Write Procedure

Random write operations, as shown in Figure

6, allow the master to directly write to any

register. To initiate a write procedure, the R/W

bit that is transmitted after the seven-bit I²C

device address is a logic-low. This indicates to the ad-

dressed slave device that a register address will follow

after the slave device acknowledges its device address.

The register address is written into the slave’s address

pointer. Following an acknowledge by the slave, the

master is allowed to write eight bits of data into the ad-

dressed register. A final acknowledge is returned by the

device, and the master generates a STOP condition.

4.2.5 I²C-bus: Sequential Register Read Procedure

If either a STOP or a repeated START condition occurs

during a Register Write, the data that has been trans-

ferred is ignored.

Sequential read operations allow the master to read from

each register in order. The register pointer is automati-

cally incremented by one after each read. This proce-

dure, as shown in Figure 9, is more efficient than the

Random Register Read if several registers must be read

from.

To perform a read procedure, the R/W bit that is trans-

mitted after the seven-bit I²C address is a logic-low, as in

the Register Write procedure. This indicates to the ad-

dressed slave device that a register address will follow

after the slave device acknowledges its device address.

The register address is then written into the slave’s ad-

dress pointer.

Following an acknowledge by the slave, the master gen-

erates a repeated START condition. The repeated

START terminates the write procedure, but not until after

the slave’s address pointer is set. The slave address is

then resent, with the R/W bit set this time to a logic-high,

indicating to the slave that data will be read. The slave

will acknowledge the device address, and then transmits

all data starting with the initial addressed register. The

register address pointer will overflow if the initial register

address is larger than zero. After the last byte of data, the

master does not acknowledge the transfer but does gen-

erate a STOP condition.

4.2.3 I²C-bus: Random Register Read Procedure

Random read operations allow the master to directly read

from any register. To perform a read procedure, as

shown in Figure 7, the R/W bit that is transmitted after the

seven-bit I²C address is a logic-low, as in the Register

Write procedure. This indicates to the addressed slave

device that a register address will follow after the slave

device acknowledges its device address. The register

address is then written into the slave’s address pointer.

Following an acknowledge by the slave, the master gen-

erates a repeated START condition. The repeated

START terminates the write procedure, but not until after

the slave’s address pointer is set. The slave address is

then resent, with the R/W bit set this time to a logic-high,

indicating to the slave that data will be read. The slave

will acknowledge the device address, and then transmits

the eight-bit word. The master does not acknowledge the

transfer but does generate a STOP condition.

3.4.02

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Low-Skew Clock Fanout Buffer ICs

Figure 6: Random Register Write Procedure (I²C-bus)

S

DEVICE ADDRESS

W

A

REGISTER ADDRESS

A

DATA

A P

7-bit Receive

Register Address

Acknowledge

Data

Device Address

Acknowledge

STOP Condition

Acknowledge

START

WRITE Command

From bus host

to device

Command

From device

to bus host

Figure 7: Random Register Read Procedure (I²C-bus)

S

DEVICE ADDRESS

W

A

REGISTER ADDRESS

A

S

DEVICE ADDRESS

R

A

DATA

A P

7-bit Receive

Register Address

Acknowledge

Data

Device Address

Acknowledge

STOP Condition

NO Acknowledge

Repeat START

Acknowledge

From device

to bus host

START

WRITE Command

From bus host

to device

READ Command

Command

Figure 8: Sequential Register Write Procedure (I²C-bus)

S

DEVICE ADDRESS

W

A

REGISTER ADDRESS

A

DATA

A

DATA

A

DATA

A P

7-bit Receive

Register Address

Acknowledge

Data

Device Address

Acknowledge

START

WRITE Command

From bus host

to device

STOP Command

Command

From device

to bus host

Figure 9: Sequential Register Read Procedure (I²C-bus)

S

DEVICE ADDRESS

W

A

REGISTER ADDRESS

A

S

DEVICE ADDRESS

R

A

DATA

A

DATA

A P

7-bit Receive

Register Address

Acknowledge

Data

Device Address

Acknowledge

NO Acknowledge

Repeat START

Acknowledge

From device

to bus host

START

WRITE Command

From bus host

to device

READ Command

STOP Command

Command

3.4.02

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Low-Skew Clock Fanout Buffer ICs

registers, starting by default at Register 0. To perform a

Block Read procedure the R/W bit that is transmitted af-

ter the seven-bit SMBus address is a logic-low, as in the

Block Write procedure. The write bit resets the register

address pointer to zero. Following an acknowledge of the

SMBus address and R/W bit by the slave device, a com-

mand code is written. It is defined that all eight bits of the

command code must be zero (0).

4.2.6 SMBus: Block Write

The Block Write command permits the

SMBus

master to write several bytes of data to

sequential registers, starting by default at Register 0. The

Block Write command, as noted in Figure 10, begins with

the seven-bit SMBus device address followed by a logic-

low R/W bit to begin a Write command. Following an ac-

knowledge of the SMBus address and R/W bit by the

slave device, a command code is written. It is defined

that all eight bits of the command code must be zero (0).

Following an acknowledge by the slave, the master gen-

erates a repeated START condition. The repeated

START terminates the write procedure, but not until after

the slave’s address pointer is set. The slave SMBus ad-

dress is then resent, with the R/W bit set this time to a

logic-high, indicating to the slave that data will be read.

The slave will acknowledge the device address, and then

will expect a byte count value (which will be ignored).

Following the byte count value, the device will take com-

mand of the bus and will transmit all the data beginning

with Register 0. After the last byte of data, the master

does not acknowledge the transfer but does generate a

STOP condition.

After the command code of zero and an acknowledge,

the host then issues a byte count that describes the

number of data bytes to be written. According to SMBus

convention, the byte count should be a value between 0

and 32; however this slave device ignores the byte count

value.

Following an acknowledge of the byte count, data bytes

may be written starting with Register 0 and incrementing

sequentially. An acknowledge by the device between

each byte of data must occur before the next data byte is

sent.

If the master does not want to receive all the data, the

master can not acknowledge the last data byte and then

can issue a STOP condition of the next clock.

4.2.7 SMBus: Block Read

The Block Read command, shown in Figure 11, permits

the master to read several bytes of data from sequential

Figure 10: Block Write (SMBus)

S

DEVICE ADDRESS

W

A

BYTE COUNT = N

A

DATA BYTE 1

A

DATA BYTE N

A P

7-bit Receive

Command Code

Acknowledge

Byte Count

Data

Device Address

Acknowledge

START

WRITE Command

From bus host

to device

Acknowledge

From device

to bus host

STOP Command

Command

Figure 11: Block Read (SMBus)

S

DEVICE ADDRESS

W

A

S

DEVICE ADDRESS

R

A

BYTE COUNT = N

A

DATA BYTE 1

A

DATA BYTE N

A

P

7-bit Receive

Command Code

Acknowledge

Byte Count

Data

Device Address

Acknowledge

NO Acknowledge

Repeat START

Acknowledge

START

WRITE Command

READ Command

Acknowledge

STOP Command

Command

From bus host

From device

to device

to bus host

3.4.02

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Low-Skew Clock Fanout Buffer ICs

5.0 Electrical Specifications

Table 7: Absolute Maximum Ratings

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at

these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,

functionality, and reliability.

PARAMETER

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage, dc, Clock Buffers (V_SS= ground)

Supply Voltage, dc, Serial Communications

Input Voltage, dc

V_DD

V_{DD_I2C}

V_I

V_O

I_IK

I_OK

T_S

T_A

T_J

V_SS-0.5

-50

-65

-55

7

V

V_DD+0.5

50

Output Voltage, dc

V

Input Clamp Current, dc (V_I< 0 or V_I> V_DD

)

mA

°C

kV

Output Clamp Current, dc (V_I< 0 or V_I> V_DD

)

50

Storage Temperature Range (non-condensing)

Ambient Temperature Range, Under Bias

Junction Temperature

Lead Temperature (soldering, 10s)

Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)

150

125

260

2

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy elec-

trostatic discharge.

Table 8: Operating Conditions

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

3.3V ± 5%

MIN.

TYP.

MAX.

UNITS

Supply Voltage, Clock Buffers

Supply Voltage, Serial Communications

Ambient Operating Temperature Range

Input Frequency

V_DD

V_{DD_I2C}

T_A

f_CLK

C_L

3.135

0

3.3

3.465

70

133

30

V

°C

MHz

pF

0

Output Load Capacitance

Serial Data Transfer Rate

Standard mode

10

100

400

kb/s

3.4.02

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Low-Skew Clock Fanout Buffer ICs

Table 9: DC Electrical Specifications

Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T_A= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal

characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.

PARAMETER

Overall (FS6050)

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Supply Current, Dynamic, with Loaded

Outputs

Supply Current, Static

I_DD

f_CLK= 100MHz; V_DD= 3.47V

Outputs low; V_DD= 3.47V

180

360

3

mA

I_DDL

0.75

Serial Communication Inputs/Output (SDA, SCL)

High-Level Input Voltage

Low-Level Input Voltage

Hysteresis Voltage *

V_IH

Outputs low

2.31

V_SS-0.3

1.0

V_DD+0.3

0.9

V

V_IL

V_hys

I_IH

High-Level Input Current

-1

1

µA

Outputs low; V_IH= 0.4V, V_DD= 3.47V.

Note: SDA requires an external pull-up to

drive the data bus.

Low-Level Input Current (pull-up)

I_IL

5

11

25

15

µA

Low-Level Output Sink Current (SDA)

Output Enable Input (OE)

High-Level Input Voltage

Low-Level Input Voltage

High-Level Input Current

I_OL

V_OL= 0.4V

10

mA

V_IH

V_IL

I_IH

2.0

V_SS-0.3

-1

V_DD+0.3

0.8

1

V

µA

Low-Level Input Current (pull-up)

I_IL

V_IH= 0.4V; V_DD= 3.47V

10

22

30

Clock Input (CLK_IN)

High-Level Input Voltage

Low-Level Input Voltage

Input Leakage Current

V_IH

V_IL

I_I

2.0

V_SS-0.3

-1

V_DD+0.3

0.8

1

V

µA

Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer)

I_{OH min}

High-Level Output Source Current

I_{OH max}

V_DD= 3.135V, V_O= 2.0V

V_DD= 3.465V, V_O= 3.135V

V_DD= 3.135V, V_O= 1.0V

V_DD= 3.465V, V_O= 0.4V

V_O= 0.5V_DD; output driving high

V_O= 0.5V_DD; output driving low

-54

54

-65

-28

69

33

17.9

16.3

mA

Ω

-46

I_{OL min}

I_{OL max}

Low-Level Output Sink Current

53

24

5

z_OH

z_OL

10

-5

Output Impedance

Tristate Output Current

I_OZ

µA

mA

Short Circuit Source Current *

Short Circuit Sink Current *

I_OSH

I_OSL

V_O= 0V; shorted for 30s, max.

V_O= 3.3V; shorted for 30s, max.

-106

107

3.4.02

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Low-Skew Clock Fanout Buffer ICs

Table 10: AC Timing Specifications

Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T_A= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal

characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.

CLOCK

(MHz)

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP.

MAX.

UNITS

Overall

66.67

100

66.67

100

66.67

100

66.67

100

182

228

3.7

3.8

3.7

4.0

3.9

3.8

4.2

4.0

Clock Skew, Maximum;

Measured on the rising edge at 1.5V;

C_L= 20pF

t_skw

ps

SDRAM_0 to any SDRAM pin *

Measured on the rising edge at 1.5V;

C_L= 20pF

t_PLH(min)

t_PLH(max)

t_PHL(min)

t_PHL(max)

Measured on the rising edge at 1.5V;

C_L= 30pF

Propagation Delay, Average;

CLK_IN to any SDRAM pin *

ns

Measured on the rising edge at 1.5V;

C_L= 20pF

66.67

100

Measured on the rising edge at 1.5V;

C_L= 30pF

Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer)

t_r(min)V_O= 0.4V to 2.4V; C_L= 20pF

t_r(max)

66.67

100

66.67

100

66.67

100

66.67

100

66.67

100

66.67

100

66.67

100

66.67

100

1.0

0.9

1.2

1.0

0.7

1.1

0.8

6.5

3.8

6.5

3.8

6.5

4.6

6.3

4.5

49

Rise Time *

ns

%

V_O= 0.4V to 2.4V; C_L= 30pF

V_O= 2.4V to 0.4V; C_L= 20pF

V_O= 2.4V to 0.4V; C_L= 30pF

V_O= 2.4V; C_L= 20pF

t_f(min)

Fall Time *

t_f(max)

t_KH(min)

t_KH(max)

t_KL(min)

t_KL(max)

Clock High Time *

Clock Low Time *

Duty Cycle *

V_O= 2.4V; C_L= 30pF

V_O= 0.4V; C_L= 20pF

V_O= 0.4V; C_L= 30pF

66.67

100

66.67

100

From rising edge to rising edge at

1.5V; C_L= 20pF

45

50

46

From rising edge to rising edge at

1.5V; C_L= 30pF

t_PZL

t_PZH

t_PLZ

t_PHZ

4.7

4.6

6.3

7.9

Tristate Enable Delay *

Tristate Disable Delay *

Output tristated to output active; C_L= 20pF

Output active to output tristated; C_L= 20pF

ns

3.4.02

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FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

Table 11: Serial Interface Timing Specifications

Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range T_A= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal

characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.

PARAMETER

Clock frequency

Bus free time between STOP and START

Set up time, START (repeated)

Hold time, START

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

MAX.

UNITS

f_SCL

t_BUF

SCL

10

4.7

4.0

250

300

400

kHz

µs

t_su:STA

t_hd:STA

t_su:DAT

t_hd:DAT

µs

ns

Set up time, data input

Hold time, data input

SDA

Minimum delay to bridge undefined region of the fall-

ing edge of SCL to avoid unintended START or STOP

Output data valid from clock

t_AA

3.5

µs

Rise time, data and clock

Fall time, data and clock

High time, clock

t_r

t_f

t_H

SDA, SCL

SCL

1000

300

ns

µs

4.0

4.7

4.0

Low time, clock

t_L

SCL

Set up time, STOP

t_su:STO

Figure 12: Bus Timing Data

SCL

t_hd:STA

t_su:STA

t_su:STO

SDA

ADDRESS OR

DATA VALID

DATA CAN

CHANGE

START

STOP

Figure 13: Data Transfer Sequence

t_H

t_r

t_f

t_L

SCL

t_su:STA

t_hd:STA

t_su:STO

t_su:DAT

t_hd:DAT

SDA

IN

t_BUF

t_AA

SDA

OUT

3.4.02

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Low-Skew Clock Fanout Buffer ICs

Figure 14: SDRAM_0:17 Clock Output (3.3V Type 4 Clock Buffer)

Low Drive Current (mA)

High Drive Current (mA)

Voltage

(V)

Voltage

(V)

220

200

180

160

140

120

100

80

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

0

0.4

0.65

0.85

1

0

1

-72

-68

-67

-64

-60

-54

-39

-30

0

-116

-110

-107

-103

-98

-90

-69

-56

-15

-198

-188

-184

-177

-170

-157

-126

-107

-46

23

35

43

49

61

64

67

70

72

34

52

65

74

93

98

103

108

112

53

83

1.4

1.5

1.65

1.8

2

2.4

2.6

3.135

3.3

3.465

104

118

152

159

168

177

184

204

60

40

1.4

1.5

20

0

-20 0

-40

0.5

1

1.5

2

2.5

3

3.5

4

1.65

1.8

1.95

3.135

3.6

-60

-80

-100

-120

-140

-160

-180

-200

-220

0

-23

0

MIN.

TYP.

MAX.

30 Ω

50 Ω

90 Ω

Output Volta ge (V)

Figure 15: DC Measurement Points

Figure 17: Timing Measurement Points

3.3V

τ

KP

t_r

t_f

V_{OH 3.3}= 2.4V

V_{IH 3.3}= 2.0V

2.4V

1.5V

t_KH

V_{IL 3.3}= 0.8V

t_KL

V_{OL 3.3}= 0.4V

0.4V

(device

(system

Duty Cycle

interface)

V_DD

50%

Figure 16: Clock Skew Measurement Point

V_SS

1.5V

3.3V

50%

V_OL

t_PZL

V_OH

10%

t_skw

t_PLZ

90%

3.3V

1.5V

50%

t_PHZ

3.4.02

13

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FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

6.0 Package Information

Table 12: 48-pin SSOP (7.5mm/0.300") Package Dimensions

DIMENSIONS

48

INCHES

MILLIMETERS

MIN.

MAX.

MIN.

MAX.

A

A₁

A₂

B

C

D

E

e

0.095

0.008

0.088

0.008

0.005

0.620

0.292

0.110

0.016

0.092

0.0135

0.010

0.630

0.299

2.41

0.203

2.24

0.203

0.127

15.75

7.42

2.79

0.406

2.34

0.343

0.254

16.00

7.59

E

H

AMERICAN MICROSYSTEMS, INC.

1

ALL RADII:

0.005" TO 0.01"

7° typ.

B

e

0.025 BSC

0.64 BSC

A₂

A

H

h

L

0.400

0.010

0.024

0°

0.410

0.016

0.040

8°

10.16

0.254

0.610

0°

10.41

0.410

1.02

8°

C

D

L

θ

A₁

BASE PLANE

SEATING PLANE

Θ

Table 13: 48-pin SSOP (7.5mm/0.300") Package Characteristics

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

TYP.

UNITS

Thermal Impedance, Junction to Free-Air

Lead Inductance, Self

Lead Inductance, Mutual

Lead Capacitance, Bulk

Lead Capacitance, Mutual

Air flow = 0 m/s

Center lead

Center lead to any adjacent lead

Center lead to V_SS

Center lead to any adjacent lead

93

3.3

1.6

0.6

0.2

°C/W

nH

pF

Θ_JA

L₁₁

L₁₂

C₁₁

C₁₂

3.4.02

14

ISO9001

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

Table 14: 28-pin SOIC (7.5mm/0.300") Package Dimensions

DIMENSIONS

INCHES MILLIMETERS

28

MIN.

MAX.

MIN.

MAX.

A

A₁

A₂

B

C

D

E

e

0.093

0.004

0.08

0.013

0.009

0.697

0.291

0.104

0.012

0.100

0.013

0.009

0.713

0.299

2.35

0.10

2.05

0.33

0.23

17.70

7.40

2.65

0.30

2.55

0.51

0.32

18.10

7.60

E

H

AMERICAN MICROSYSTEMS, INC.

1

ALL RADII:

0.005" TO 0.01"

7° typ.

h x 45°

B

e

0.05 BSC

1.27 BSC

A₂

A

H

h

L

0.393

0.010

0.016

0°

0.419

0.030

0.05

8°

10.00

0.25

0.40

0°

10.65

0.75

1.27

8°

C

D

L

θ

A₁

BASE PLANE

SEATING PLANE

Θ

Table 15: 28-pin SOIC (7.5mm/0.300") Package Characteristics

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

TYP.

UNITS

Thermal Impedance, Junction to Free-Air

Lead Inductance, Self

Lead Inductance, Mutual

Lead Capacitance, Bulk

Lead Capacitance, Mutual

Air flow = 0 m/s

Center lead

Center lead to any adjacent lead

Center lead to V_SS

Center lead to any adjacent lead

80

2.5

0.85

0.42

0.08

°C/W

nH

pF

Θ_JA

L₁₁

L₁₂

C₁₁

C₁₂

3.4.02

15

ISO9001

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

Table 16: 28-pin SSOP (5.3mm/0.209") Package Dimensions

DIMENSIONS

INCHES MILLIMETERS

28

MIN.

MAX.

MIN.

MAX.

A

A₁

A₂

B

C

D

E

0.068

0.002

0.066

0.01

0.005

0.396

0.205

0.078

0.008

0.07

0.015

0.008

0.407

0.212

1.73

0.05

1.68

0.25

0.13

10.07

5.20

2.00

0.21

1.78

0.38

0.20

10.33

5.38

E

H

AMERICAN MICROSYSTEMS, INC.

1

ALL RADII:

7° typ.

0.005" TO 0.01"

B

e

0.028 BSC

0.65 BSC

C

A₂

A

H

L

0.301

0.022

0°

0.311

0.037

8°

7.65

0.55

0°

7.90

0.95

8°

D

L

θ

A₁

BASE PLANE

SEATING PLANE

Θ

Table 17: 28-pin SSOP (5.3mm/0.209") Package Characteristics

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

TYP.

UNITS

Thermal Impedance, Junction to Free-Air

Lead Inductance, Self

Lead Inductance, Mutual

Lead Capacitance, Bulk

Lead Capacitance, Mutual

Air flow = 0 m/s

Center lead

Center lead to any adjacent lead

Center lead to V_SS

Center lead to any adjacent lead

97

°C/W

nH

pF

Θ_JA

L₁₁

L₁₂

C₁₁

C₁₂

2.24

0.95

0.25

0.07

3.4.02

16

ISO9001

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

7.0 Ordering Information

DEVICE

NUMBER

ORDERING

CODE

OPERATING

PACKAGE TYPE

SHIPPING CONFIGURATION

TEMPERATURE RANGE

11257-801

11257-811

11257-802

11257-812

11257-806

11257-816

11257-803

11257-813

11257-804

11257-814

48-pin (7.5mm/0.300”) SSOP

28-pin (7.5mm/0.300”) SOIC

28-pin (7.5mm/0.209”) SOIC

28-pin (5.3mm/0.209”) SSOP

28-pin (7.5mm/0.300”) SOIC

Tape and Reel

Tube

0°C to 70°C (Commercial)

FS6050

FS6051

Tape and Reel

Tube

Tape and Reel

Tube

Tape and Reel

Tube

FS6053

FS6054

Tape and Reel

Tube

Purchase of I²C components of American Microsystems, Inc., or one of its sublicensed Associated Companies conveys

a license under Philips I²C Patent Rights to use these components in an I²C system, provided that the system conforms

to the I²C Standard Specification as defined by Philips.

Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI

makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom

of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-

serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are

intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-

ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-

mended without additional processing by AMI for such applications.

American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,

WWW Address: http://www.amis.com E-mail: tgp@amis.com

3.4.02

17

ISO9001

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

Figure 18: Board Layout

8.0 Application Information

CLK GND

VOID

8.1

Reduction of EMI

MB GND

1

2

48

47

The primary concern when designing the board layout for

this device is the reduction of electromagnetic interfer-

ence (EMI) generated by the 18 copies of the 100MHz

SDRAM clock. It is assumed the reader is familiar with

basic transmission line theory.

R_S

4

5

45

44

R_S

1000pF

R_S

1000pF

R_S

8

9

41

40

11

38

8.1.1 Layout Guidelines

R_S

13

14

36

35

R_S

To obtain the best performance, noise should be mini-

mized on the power and ground supplies to the IC. Ob-

serve good high-speed board design practices, such as:

1000pF

R_S

1000pF

R_S

17

18

32

31

§

Use multi-layer circuit boards with dedicated low im-

pedance power and ground planes for the device

(denoted as CLK VDD and CLK GND in Figure 18).

The device power and ground planes should be

completely isolated from the motherboard power and

ground planes by a void in the power planes.

1000pF

R_S

21

24

28

25

R_S

MB VDD

CLK VDD

§

Several low-pass filters using low impedance ferrite

beads (5Ω at 100MHz) are recommended to decou-

ple the device power and ground planes from the

motherboard power and ground planes (MB VDD and

MB GND). The beads should span the gap between

the power and ground planes. Seven beads for

power and seven beads for ground are suggested

(14 total) so that the clock rise times (1V/ns) can be

maintained.

Place 1000pF bypass capacitors as close as possible

to the power pins of the IC. Use RF-quality low-

inductance multi-layer ceramic chip capacitors. Six

capacitors is optimal, one on each power/ground

grouping as shown in Figure 18.

Component

Layer

MB GND

MB VDD

CLK GND

CLK VDD

MB GND

MB VDD

Signal Layer

§

8.1.2 Output Driver Termination

A signal reflection will occur at any point on a PC-board

trace where impedance mismatches exist. Reflections

cause several undesirable effects in high-speed applica-

tions, such as an increase in clock jitter and a rise in

electromagnetic emissions from the board. Using a prop-

erly designed series termination on each high-speed line

can alleviate these problems by eliminating signal reflec-

§

Load similar clock outputs equally, and keep output

loading as light as possible to help reduce clock skew

and power dissipation.

Use equal-length clock traces that are as short as tions.

possible. Rounded trace corners help reduce reflec-

tions and ringing in the clock signal.

The clock traces must never cross the void area be-

tween power/ground planes. Each trace must have a

complete plane (either VDD or GND) under the com-

plete length of the trace.

Figure 19: Series Termination

z_O

LINE

z_L

R_S

DRIVER

RECEIVE

3.4.02

18

ISO9001

FS6050/FS6051/FS6053/FS6054

Low-Skew Clock Fanout Buffer ICs

Series termination adds no dc loading to the driver, and pacitance, and the number of connected devices with

requires less power than other resistive termination their associated input currents.

methods. Further, no extra impedance exists from the

Control of the clock and data lines is done through open

signal line to a reference voltage, such as ground.

drain/collector current-sink outputs, and thus requires

As shown in Figure 19, the sum of the driver’s output im- external pull-up resistors on both lines. A guideline is

pedance (z_O) and the series termination resistance (R_S)

t_r

must equal the line impedance (z_L). That is,

R_P<

,

2×C_bus

R_S= z_L− z_O

.

where t_ris the maximum rise time (minus some margin)

and C_busis the total bus capacitance. Assuming an I²C

device on each DIMM, an I²C controller, the clock buffer,

and two other bus devices results in values in the 5kΩ to

7kΩ range. Use of a series resistor to provide protection

against high voltage spikes on the bus will alter the val-

ues for R_P.

Note that when the source impedance (z_O+R_S) is

matched to the line impedance, then by voltage division

the incident wave amplitude is one-half of the full signal

amplitude.

(z_O+ R_S)

V

V_i= V

=

(z_O+ R_S) + z_L

2

The full signal amplitude may take up to twice as long as

the propagation delay of the line to develop, reducing

noise immunity during the half-amplitude period. Note

also that the voltage at the receive end must add up to a

signal amplitude that meets the receiver switching

thresholds. The slew rate of the signal is also reduced

due to the additional RC delay of the load capacitance

and the line impedance. Also note that the output driver

impedance will vary slightly with the output logic state

(high or low).

Figure 20: Connections to the Serial Bus

R_P

SDA

SCL

R

(optiona^Sl)

Data In

Clock Out

Clock In

Data Out

8.2

Dynamic Power Dissipation

TRANSMITTER

RECEIVER

High-speed clock drivers require careful attention to

power dissipation. Transient power (P_T) consumption can

be derived from

8.3.1 For More Information

P = V_DD²×C_load× f_CLK× N_SW

More detailed information on serial bus design can be

obtained from SMBus and I²C Bus Design, available from

the Intel Corporation at http://www.intel.com.

T

where C_loadis the load capacitance, V_DDis the supply

voltage, f_CLKis the clock frequency, and N_swis the

number of switching outputs.

Information on the I²C-bus can be found in the document

The I²C-bus And How To Use It (Including Specifica-

tions), available from Philips Semiconductors at

http://www-us2.semiconductors.philips.com.

The internal heat (junction temperature, T_J) generated by

the power dissipation can be calculated from

Additional information on the System Management Bus

can be found in the System Management Bus Specifica-

tion, available from the Smart Battery System

Implementers’ Forum at http://www.sbs-forum.org.

T_J= Θ_JA× P +T_A

T

where Θ_JAis the package thermal resistance, T_Ais the

ambient temperature, and P_Tis derived above.

8.3

Serial Communications

Connection of devices to a standard-mode implementa-

tion of either the I²C-bus or the SMBus is similar to that

shown in Figure 20. Selection of the pull-up resistors (R_P)

and the optional series resistors (R_S) on the SDA and

SCL lines depends on the supply voltage, the bus ca-

3.4.02

19

ISO9001


型号：	FS6054(28SOIC)
厂家：	AMI SEMICONDUCTOR
描述：	Clock Driver, CMOS, PDSO28, 光电二极管
文件：	总19页 (文件大小：577K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FS6054(28SOIC) [AMI]

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