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FS6058-01(48-SSOP) [AMI]

Clock Driver, PDSO48,;
FS6058-01(48-SSOP)
型号： FS6058-01(48-SSOP)
厂家： AMI SEMICONDUCTOR    AMI SEMICONDUCTOR
描述：

Clock Driver, PDSO48,

光电二极管
文件： 总10页 (文件大小：117K)
中文：  中文翻译
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FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
November 2000  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
Preliminary Information  
Figure 2: Pin Configuration  
1.0 Features  
•
Distributes one differential LVPECL reference clock  
to six differential HCSL clock pairs and two single-  
ended LVTTL MREF clocks  
VSS  
VDD  
1
2
3
4
5
6
7
8
9
48 VDD  
47 VSS_H  
VDD_R  
PECL_P  
PECL_N  
VSS_R  
VDD_M  
MREF_P  
MREF_N  
46 VDD_H  
45 HOST_P1  
44 HOST_N1  
43 VSS_H  
•
•
HCSL current levels controlled by IREF current  
reference and MULT_0:1 current multiplier pins  
Host clock frequency division selected via the  
SEL_A, SEL_B, and SEL_U input signals  
42 HOST_P2  
41 HOST_N2  
40 VDD_H  
39 HOST_P3  
38 HOST_N3  
37 VSS_H  
•
•
Active-low PWR_DWN# signal disables all outputs  
VSS_M 10  
VDD 11  
Tristate output control via SEL_T facilitates board  
testing  
VSS 12  
•
Available in a 48-pin SSOP and TSSOP  
VDD_L 13  
VDD 14  
36 HOST_P4  
35 HOST_N4  
34 VDD_H  
33 HOST_P5  
32 HOST_N5  
31 VSS_H  
VSS_L 15  
SEL_T 16  
MULT_0 17  
MULT_1 18  
VDD_L 19  
VSS_L 20  
SEL_A 21  
SEL_B 22  
SEL_U 23  
PWR_DWN# 24  
Figure 1: Block Diagram  
Current  
Adjust  
MULT_0:1  
VDD_H  
HOST_P1,6  
HOST_N1,6  
VSS_H  
IREF  
30 HOST_P6  
29 HOST_N6  
28 VDD_H  
27 IREF  
÷
÷
PWR_DWN#  
SEL_T  
VDD_H  
HOST_P2:5  
HOST_N2:5  
VSS_H  
26 VSS_I  
PECL_P  
PECL_N  
25 VDD_I  
Divider  
Control  
SEL_A  
VDD_M  
MREF_P  
MREF_N  
VSS_M  
SEL_B  
÷4  
SEL_U  
FS6058  
Table 1: Divider and Power-Down Control  
CONTROL INPUTS  
CLOCK OUTPUTS (MHz)  
PWR_  
DWN#  
SEL_  
T
SEL_  
A
SEL_  
B
SEL_  
U
HOST_P1  
HOST_N1  
HOST_P2  
HOST_N2  
HOST_P3  
HOST_N3  
HOST_P4  
HOST_N4  
HOST_P5  
HOST_N5  
HOST_P6  
HOST_N6  
MREF_P  
MREF_N  
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
PECL ÷ 2  
tristate  
PECL ÷ 2  
PECL ÷ 2  
PECL ÷ 2  
PECL ÷ 4  
PECL  
PECL ÷ 2  
PECL ÷ 2  
PECL ÷ 2  
PECL ÷ 4  
PECL  
PECL ÷ 2  
PECL ÷ 2  
PECL ÷ 2  
PECL ÷ 4  
PECL  
PECL ÷ 2  
PECL ÷ 2  
PECL ÷ 2  
PECL ÷ 4  
PECL  
PECL ÷ 2  
tristate  
PECL ÷ 4  
PECL ÷ 4  
PECL ÷ 4  
PECL ÷ 4  
PECL ÷ 4  
PECL ÷ 4  
PECL ÷ 4  
PECL ÷ 2  
tristate  
PECL ÷ 4  
PECL ÷ 4  
PECL  
PECL ÷ 4  
PECL ÷ 4  
PECL  
tristate  
PECL  
PECL  
PECL  
PECL  
tristate  
PECL ÷ 2  
PECL ÷ 2  
tristate  
PECL  
PECL  
PECL  
PECL  
PECL ÷ 2  
PECL ÷ 2  
tristate  
PECL ÷ 2  
tristate  
PECL ÷ 2  
tristate  
PECL ÷ 2  
tristate  
PECL ÷ 2  
tristate  
HOST_P1 =  
2× IREF  
HOST_P2 =  
2× IREF  
HOST_P3 =  
2× IREF  
HOST_P4 =  
2× IREF  
HOST_P5 =  
2× IREF  
HOST_P6 =  
2× IREF  
MREF_P  
= high  
0
X
X
X
X
HOST_N1 =  
tristate  
HOST_N2 =  
tristate  
HOST_N3 =  
tristate  
HOST_N4 =  
tristate  
HOST_N5 =  
tristate  
HOST_N6 =  
tristate  
MREF_N  
= low  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
11.10.00  
ISO9001  
QS9000  
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
Preliminary Information  
November 2000  
Table 2: Pin Descriptions  
AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DO = Digital Output; P = Power/Ground;  
# = Active-low pin  
PIN  
TYPE  
NAME  
DESCRIPTION  
SUPPLY  
44  
45  
41  
42  
38  
39  
35  
36  
32  
33  
29  
30  
HOST_N1  
HOST_P1  
HOST_N2  
HOST_P2  
HOST_N3  
HOST_P3  
HOST_N4  
HOST_P4  
HOST_N5  
HOST_P5  
HOST_N6  
HOST_P6  
Differential  
output pair 1  
Outside  
Pair  
AO  
Differential  
output pair 2  
AO  
AO  
AO  
AO  
Differential  
output pair 3  
Current-steering differential current-mode (HCSL) outputs  
provided for clocking the CPU.  
Inside  
Pairs  
VDD_H  
The output drive current is established via a reference  
current at IREF and a multiplying factor set by MULT_0:1  
Differential  
output pair 4  
Differential  
output pair 5  
Differential  
output pair 6  
Outside  
Pair  
AO  
AI  
A fixed precision resistor from this pin to ground provides a reference current used for the  
differential current-mode HOST clock outputs  
27  
IREF  
VDD_I  
Single-ended clock (180° out of phase with MREF_P) provided as a reference clock to a  
memory clock driver  
9
8
DO  
DO  
DI  
MREF_N  
MREF_P  
VDD_M  
Single-ended clock in a pair of outputs reference clock to a memory clock driver  
MULT_0  
MULT_1  
The logic setting on these two pins selects the multiplying factor of the IREF reference current  
for the HOST pair outputs  
17, 18  
VDD_L  
VDD_R  
VDD_I  
5
4
PECL_N  
PECL_P  
LVPECL input (complementary)  
Differential Input  
AI  
DI  
LVPECL input (true)  
Asynchronous active-low LVTTL power-down signal forces MREF outputs low, tristates  
HOST_N outputs, and drives HOST_P output currents to 2xIREF  
24  
PWR_DWN#  
21  
DI  
DI  
DI  
DI  
P
SEL_A  
SEL_B  
SEL_T  
SEL_U  
VDD  
Used in conjunction with SEL_B and SEL_U to select desired output frequencies  
Used in conjunction with SEL_A and SEL_U to select desired output frequencies  
Active high input tristates all outputs  
22  
VDD_L  
16  
23  
Used in conjunction with SEL_A and SEL_B to select desired output frequencies  
3.3V core power supply  
2, 11, 14, 48  
28, 34, 40, 46  
P
VDD_H  
VDD_I  
VDD_L  
VDD_M  
VDD_R  
VSS  
3.3V power supply for the differential HOST clock outputs  
3.3V power supply for IREF current reference input  
3.3V power supply for logic input pins  
25  
P
13, 19  
P
7
P
3.3V power supply for MREF clock outputs  
3.3V power supply for PECL reference clock inputs  
Core ground  
3
P
-
1, 12  
P
31, 37, 43, 47  
P
VSS_H  
VSS_I  
VDD_L  
VSS_M  
VSS_R  
Ground for the differential HOST clock outputs  
Ground for IREF current reference input  
26  
15, 20  
10  
P
P
Ground for logic input pins  
P
Ground for the MREF clock outputs  
6
P
Ground for PECL inputs  
ISO9001  
QS9000  
2
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
November 2000  
Preliminary Information  
Table 5: HOST Buffer Clock Outputs  
2.0 HOST Buffer Current Control  
The current supplied at the HOST outputs is controlled by  
two parameters: (1) the value of the programming resistor  
from the IREF pin to ground (VSS), and (2) the multiplier  
factor determined by the logic setting of the MULT_0 and  
MULT_1 pins.  
HIGH DRIVE CURRENT (mA)  
AT PRIMARY SYSTEM CONFIGURATION  
Output  
Voltage (V)  
MIN.  
TYP.  
MAX.  
3.30  
3.14  
2.97  
2.81  
2.64  
2.48  
2.31  
2.14  
1.98  
1.81  
1.65  
1.48  
1.32  
1.15  
0.99  
0.82  
0.66  
0.49  
0.33  
0.16  
0.00  
0.00  
0.00  
0.00  
-3.03  
-4.22  
-5.76  
The HOST output current is a mirrored and scaled copy  
of the reference current flowing through the programming  
resistor on the IREF pin. The voltage that appears at the  
IREF pin is one-third of the voltage at the VDD_I pin.  
Therefore, the reference current is  
-5.66  
-7.68  
-9.86  
-7.87  
-10.30  
-11.91  
-12.56  
-12.85  
-13.07  
-13.26  
-13.42  
-13.54  
-13.64  
-13.70  
-13.73  
-13.75  
-13.76  
-13.78  
-13.79  
-13.80  
-13.81  
-13.82  
-11.85  
-12.45  
-12.84  
-13.16  
-13.45  
-13.72  
-13.96  
-14.17  
-14.36  
-14.52  
-14.64  
-14.71  
-14.74  
-14.76  
-14.78  
-14.80  
-14.82  
-14.83  
-9.67  
-11.05  
-11.98  
-12.52  
-12.77  
-12.91  
-12.99  
-13.04  
-13.07  
-13.08  
-13.09  
-13.11  
-13.12  
-13.13  
-13.13  
-13.14  
-13.15  
1
× VDD_I  
3
.
IREF  
=
RIREF  
The mirrored reference current can be increased by  
adding one or more copies of the mirror current together.  
The additional current is controlled by the logic settings  
on the MULT_0 and MULT_1 pins.  
Table 3: Current Multiplier  
MULT_0  
MULT_1  
MULTPLIER  
I
I
I
I
O = 5 × IREF  
O = 6 × IREF  
O = 4 × IREF  
O = 7 × IREF  
0
0
1
1
0
1
0
1
Output Voltage (V)  
0
1
2
3
Table 4: HOST Current Selection  
0
-2  
-4  
-6  
-8  
PROGRAM REFERENCE  
CURRENT  
TRACE  
OUTPUT  
RESISTOR  
CURRENT  
MULTIPLIER IMPEDANCE VOLTAGE  
60Ω  
50Ω  
60Ω  
50Ω  
60Ω  
50Ω  
60Ω  
50Ω  
30Ω  
25Ω  
30Ω  
25Ω  
30Ω  
25Ω  
30Ω  
25Ω  
0.71V  
0.59V  
0.85V  
0.71V  
0.56V  
0.47V  
0.99V  
0.82V  
0.75V  
0.62V  
0.90V  
0.75V  
0.60V  
0.50V  
1.05V  
0.84V  
475Ω (1%)  
IO = 5 × IREF  
IO = 6 × IREF  
IO = 4 × IREF  
IO = 7 × IREF  
IO = 5 × IREF  
IO = 6 × IREF  
IO = 4 × IREF  
IO = 7 × IREF  
2.32mA  
475Ω (1%)  
475Ω (1%)  
475Ω (1%)  
221Ω (1%)  
221Ω (1%)  
221Ω (1%)  
221Ω (1%)  
2.32mA  
2.32mA  
2.32mA  
5mA  
-10  
-12  
-14  
-16  
-18  
-20  
30Ω  
50Ω  
90Ω  
5mA  
Max VOH  
5mA  
Data in this table represents nominal characterization data only  
5mA  
NOTE: Shaded row indicates the Primary System Configuration  
ISO9001  
QS9000  
3
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
Preliminary Information  
November 2000  
3.0 Electrical Specifications  
Table 6: Absolute Maximum Ratings  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at  
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,  
functionality, and reliability.  
PARAMETER  
SYMBOL  
MIN.  
MAX.  
UNITS  
Supply Voltage (VSS = ground)  
Input Voltage, dc  
VDD  
VI  
VSS-0.5  
VSS-0.5  
VSS-0.5  
-50  
7
VDD+0.5  
VDD+0.5  
50  
V
V
Output Voltage, dc  
VO  
IIK  
V
Input Clamp Current, dc (VI < 0 or VI > VDD  
)
mA  
mA  
°C  
°C  
°C  
°C  
kV  
Output Clamp Current, dc (VI < 0 or VI > VDD  
)
IOK  
TS  
TA  
TJ  
-50  
50  
Storage Temperature Range (non-condensing)  
Ambient Temperature Range, Under Bias  
Junction Temperature  
-65  
150  
-55  
125  
125  
Lead Temperature (soldering, 10s)  
260  
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)  
2
CAUTION: ELECTROSTATIC SENSITIVE DEVICE  
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy  
electrostatic discharge.  
Table 7: Operating Conditions  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
Core (VDD)  
MIN.  
TYP.  
MAX.  
UNITS  
3.135  
3.3  
3.465  
V
Supply Voltage  
VDD  
TA  
Clock Buffers  
(VDD_H, VDD_I, VDD_M, VDD_R, VDD_L)  
3.135  
0
3.3  
3.465  
70  
V
Operating Temperature Range  
Reference Frequency Range  
Input Rise/Fall Time  
°C  
MHz  
ps  
%
200  
Input Duty Cycle  
40  
2.135  
1.490  
10  
60  
2.420  
1.825  
30  
Input High-Level Voltage  
Input Low-Level Voltage  
Load Capacitance  
V
Required LVPECL signalling parameters  
MREF_P, MREF_N  
V
CL  
RL  
pF  
HOST_P1 to HOST_P6,  
HOST_N1 to HOST_N6  
Ω
Load Resistance  
20  
105  
ISO9001  
QS9000  
4
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
November 2000  
Preliminary Information  
Table 8: DC Electrical Specifications  
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal  
characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
Overall  
fHOST = 133MHz; all supplies = 3.465V,  
RIREF= 475Ω, IOH = 6 × IREF  
Supply Current, Dynamic, with Loaded  
Outputs  
IDD  
mA  
PWR_DWN# low, all supplies = 3.465V,  
µA  
Supply Current, Static  
IDDs  
RIREF= 475Ω, IOH = 6 × IREF  
LVTTL Digital Inputs (PWR_DWN#, MULT_0, MULT_1, SEL_U, SEL_A, SEL_B, SEL_T)  
High-Level Input Voltage  
Low-Level Input Voltage  
Input Leakage Current  
VIH  
VIL  
IIL  
2.0  
VSS-0.3  
-5  
VDD+0.3  
0.8  
V
V
µA  
+5  
PECL Reference Inputs (PECL_P, PECL_N)  
High-Level Input Voltage  
VIH  
VIL  
IIL  
Low-Level Input Voltage  
Input Leakage Current  
Current Reference (IREF)  
Bias Voltage  
VOH  
IOH  
no load  
VO = 0V  
1.1  
V
Short Circuit Output Source Current  
mA  
MREF_P, MREF_N Clock Outputs (Type 5 Clock Driver)  
VDD_M, VDD_R, VDD_66 = 3.135V,  
VO = 1.0V  
IOH min  
High Level Output Source Current  
IOH max  
-33  
30  
mA  
VDD_M, VDD_R, VDD_66 = 3.465V,  
VO = 3.135V  
-33  
38  
VDD_M, VDD_R, VDD_66 = 3.135V,  
IOL min  
Low Level Output Sink Current  
IOL max  
V
O = 1.95V  
VDD_M, VDD_R, VDD_66 = 3.465V,  
O = 0.4V  
mA  
V
zOL  
Measured at 1.65V, output driving low  
Measured at 1.65V, output driving high  
12  
12  
55  
55  
10  
Ω
Output Impedance  
zOH  
µA  
mA  
mA  
Tristate Output Current  
IOZ  
-10  
Short Circuit Output Source Current  
Short Circuit Output Sink Current  
IOSH  
IOSL  
VO = 0V; shorted for 30s, max.  
VO = 3.3V; shorted for 30s, max.  
-51  
62  
HOST_P1:4, HOST_N1:4 Clock Outputs (Type X1 Clock Buffer)  
RS = 33.2Ω, RP = 49.9Ω,  
RIREF = 475Ω, IOH = 6 × IREF  
Crossover Voltage  
VX  
45  
55  
%VOH  
mA  
VO = 0.65V, RIREF = 475Ω, IOH = 6 × IREF  
VO = 0.74V, RIREF = 475Ω, IOH = 6 × IREF  
VDD = 3.30V, over settings in Table 4  
VDD_I=3.3V±5%, over settings in Table 4  
12.9  
High-Level Output Source Current  
IOH  
14.9  
+7  
-7  
∆IOH  
Output Source Current Tolerance  
%IOH  
-12  
+12  
∆VO/∆IO, where VO1 = 1.0V, VO2 = VSS  
RIREF = 475Ω, IOH = 6 × IREF  
,
Ω
Output Impedance  
zOH  
IOZ  
3000  
-10  
µA  
Tristate Output Current  
10  
ISO9001  
QS9000  
5
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
Preliminary Information  
November 2000  
Table 9: MCLK_P, MCLK_N Clock Outputs  
High Drive Current (mA)  
Low Drive Current (mA)  
Voltage  
(V)  
Voltage  
(V)  
150  
125  
100  
75  
MIN.  
TYP.  
MAX.  
MIN.  
TYP.  
MAX.  
0
0
0
0
0
-49  
-48  
-48  
-47  
-47  
-46  
-46  
-45  
-43  
-41  
-37  
-33  
-28  
-22  
-14  
-6  
-83  
-83  
-82  
-81  
-80  
-79  
-78  
-76  
-74  
-70  
-65  
-59  
-52  
-43  
-32  
-20  
-7  
-132  
-131  
-130  
-129  
-127  
-126  
-124  
-121  
-117  
-112  
-105  
-97  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
3.0  
3.2  
3.4  
11  
21  
30  
37  
43  
47  
50  
53  
54  
55  
55  
55  
56  
56  
56  
17  
32  
45  
56  
65  
73  
78  
82  
84  
85  
85  
86  
86  
86  
87  
87  
24  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
1.4  
1.6  
1.8  
2.0  
2.2  
2.4  
2.6  
2.8  
3.0  
3.2  
3.4  
45  
64  
50  
79  
25  
92  
0
103  
112  
117  
120  
121  
122  
123  
123  
124  
124  
124  
125  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
-25  
-50  
-75  
-100  
-125  
-150  
-87  
30Ω  
50Ω  
90Ω  
-74  
-60  
Output Voltage (V)  
-45  
-27  
Data in this table represents nominal characterization data only  
-7  
ISO9001  
QS9000  
6
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
November 2000  
Preliminary Information  
Table 10: AC Timing Specifications  
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and  
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
Overall  
Tristate Enable Delay *  
tDZL, tDZH  
tDLZ, tDHZ  
tSTB  
SEL_A:B=00, SEL133/100#=0  
1.0  
1.0  
10  
10  
ns  
ns  
Tristate Disable Delay *  
SEL_A:B=11, SEL133/100#=0  
via PWR_DWN#  
Clock Stabilization (on power-up) *  
3.0  
ms  
HOST_P1:6, HOST_N1:6 Clock Outputs  
Ratio of high pulse width to one clock period at VX,  
RIREF = 475Ω, IOH = 6 × IREF, RS=33.2Ω, RP=49.9Ω  
Duty Cycle *  
dt  
tsk(o)  
tj(∆P)  
tr  
45  
55  
%
ps  
ps  
ps  
%
HOST pair to HOST pair @ VX, RIREF = 475Ω,  
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω  
Clock Skew *  
100  
Rising edge to rising edge at VX,, RIREF = 475Ω,  
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω  
Jitter, Additive Period  
(peak-peak) *  
tJ(IN)+  
100  
Rising edge to rising edge at VX,, RIREF = 475Ω,  
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω  
Rise Time *  
175  
45  
450  
Rising edge to rising edge at VX,, RIREF = 475Ω,  
IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω  
Rise/Fall Time Matching*  
MREF_P, MREF_N Clock Outputs  
Duty Cycle *  
20  
55  
Ratio of high pulse width to one clock period,  
measured at 1.5V  
dt  
%
Jitter, Additive Period  
(peak-peak) *  
tJ(IN)  
100  
+
tj(∆P)  
From rising edge to rising edge at 1.5V, CL=30pF  
ps  
tr min  
tr max  
tf min  
tf max  
Measured @ 0.4V – 2.4V; CL=10pF  
Measured @ 0.4V – 2.4V; CL=30pF  
Measured @ 2.4V – 0.4V; CL=10pF  
Measured @ 2.4V – 0.4V; CL=30pF  
0.4  
0.4  
Rise Time *  
Fall Time *  
ns  
ns  
1.6  
1.6  
ISO9001  
QS9000  
7
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
Preliminary Information  
November 2000  
4.0 Package Information  
Table 11: 48-pin SSOP (0.300") Package Dimensions  
48  
DIMENSIONS  
INCHES  
MILLIMETERS  
MIN.  
MAX.  
MIN.  
MAX.  
A
A1  
b
0.095  
0.008  
0.008  
0.005  
0.620  
0.395  
0.291  
0.110  
0.016  
0.0135  
0.010  
0.630  
0.420  
0.299  
2.41  
0.20  
2.79  
0.41  
E1  
E
0.20  
0.34  
AMERICAN MICROSYSTEMS, INC.  
c
0.13  
0.25  
D
E
E1  
e
15.75  
10.03  
7.39  
16.00  
10.67  
7.59  
1
SEATING PLANE  
A
b
e
h × 45°  
0.025 BSC  
0.64 BSC  
h
0.015  
0.020  
0°  
0.025  
0.040  
8°  
0.38  
0.51  
0°  
0.64  
1.01  
8°  
c
L
L
D
θ
A1  
θ
Table 12: 48-pin SSOP (0.300") Package Characteristics  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
Air flow = 0 m/s  
TYP.  
UNITS  
ΘJA  
L11  
L12  
L13  
C11  
C12  
C13  
Thermal Impedance, Junction to Free-Air  
Lead Inductance, Self  
93  
5.5  
°C/W  
nH  
Longest lead  
Longest lead to any 1st adjacent lead  
Longest lead to any 2nd adjacent lead  
Longest lead to VSS  
Longest lead to any 1st adjacent lead  
Longest lead to any 2nd adjacent lead  
3.0  
Lead Inductance, Mutual  
Lead Capacitance, Bulk  
Lead Capacitance, Mutual  
nH  
pF  
pF  
2.1  
0.94  
0.46  
0.05  
ISO9001  
QS9000  
8
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
November 2000  
Preliminary Information  
Table 13: 48-pin TSSOP (6.1mm) Package Dimensions  
DIMENSIONS  
48  
INCHES  
MILLIMETERS  
MIN.  
MAX.  
MIN.  
MAX.  
A
A1  
b
-
0.047  
0.006  
0.011  
0.008  
0.496  
-
1.20  
0.15  
0.27  
0.20  
12.60  
0.002  
0.0067  
0.0035  
0.488  
0.05  
0.17  
0.09  
12.40  
E1  
E
c
AMERICAN MICROSYSTEMS, INC.  
D
E
0.318 BSC  
8.10 BSC  
E1  
e
0.236  
0.244  
6.00  
6.20  
1
0.019 BSC  
0.50 BSC  
SEATING PLANE  
L
0.018  
0.008  
0°  
0.030  
0.45  
0.20  
0°  
0.75  
-
b
e
S
θ2  
θ3  
c
S
-
A
θ1  
θ2  
θ3  
8°  
8°  
L
θ1  
D
A1  
12° REF  
12° REF  
12° REF  
12° REF  
Table 14: 48-pin TSSOP (6.1mm) Package Characteristics  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
Air flow = 0 m/s  
TYP.  
UNITS  
ΘJA  
L11  
L12  
L13  
C11  
C12  
C13  
Thermal Impedance, Junction to Free-Air  
Lead Inductance, Self  
89  
°C/W  
nH  
Longest lead  
3.50  
1.82  
1.17  
0.63  
0.30  
0.03  
Longest lead to any 1st adjacent lead  
Longest lead to any 2nd adjacent lead  
Longest lead to VSS  
Longest lead to any 1st adjacent lead  
Longest lead to any 2nd adjacent lead  
Lead Inductance, Mutual  
Lead Capacitance, Bulk  
Lead Capacitance, Mutual  
nH  
pF  
pF  
ISO9001  
QS9000  
9
FS6058-01  
AMERICAN MICROSYSTEMS, INC.  
LVPECL to HCSL/LVTTL Motherboard Clock Driver IC  
Preliminary Information  
November 2000  
5.0 Ordering Information  
Table 15: Device Ordering Codes  
OPERATING  
SHIPPING  
CONFIGURATION  
DEVICE NUMBER  
ORDERING CODE  
PACKAGE TYPE  
TEMPERATURE RANGE  
0°C to 70°C (Commercial)  
0°C to 70°C (Commercial)  
11915-802  
11915-202  
48-pin (0.300”) SSOP  
48-pin (6.1mm) TSSOP  
Tape and Reel  
Tape and Reel  
FS6058-01  
6.0 Revision Information  
DATE  
PAGE  
DESCRIPTION  
This document contains information on a new product. Specifications and information herein are subject to  
change without notice.  
8/4/00  
-
Copyright © 2000 American Microsystems, Inc.  
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale  
only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or  
regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or  
fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any  
time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring  
extended temperature range, unusual environmental requirements, or high reliability applications, such as military,  
medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by  
AMI for such applications.  
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,  
WWW Address: http://www.amis.com E-mail: tgp@amis.com  
ISO9001  
QS9000  
10  

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