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FS61857-01 [AMI]

Clock Driver, CMOS, PDSO48,;
FS61857-01
型号： FS61857-01
厂家： AMI SEMICONDUCTOR    AMI SEMICONDUCTOR
描述：

Clock Driver, CMOS, PDSO48,

光电二极管
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FS61857-01  
AMERICAN MICROSYSTEMS, INC.  
1:10 HSTL Zero-Delay Clock Buffer IC  
Advance Information  
November 2000  
Figure 1: Block Diagram  
1.0 Features  
•
Generates one bank of ten differential 2.5V HSTL  
clock outputs (YP0/YN0 to YP9/YN9) from one differ-  
ential HSTL reference clock input  
VDD  
YP0  
YN0  
Power  
PWRDWN#  
Down  
YP1  
YN1  
YP2  
YN2  
YP3  
YN3  
YP4  
YN4  
YP5  
YN5  
YP6  
YN6  
YP7  
YN7  
YP8  
YN8  
•
•
Meets the JEDEC Standard PLL Clock Driver for  
AVDD  
Registered DIMM Applications  
External feedback input (FBINP/FBINN) to synchro-  
nize all clock outputs to the reference input  
Operating frequency 60MHz to 170MHz  
FBINP  
FBINN  
PLL  
•
•
•
CKP  
CKN  
Tight tracking skew (spread-spectrum tolerant)  
Integrated 25Ω series damping resistors for driving  
AGND  
point-to-point loads  
•
•
•
Auto power-down mode if reference input frequency  
drops below 20MHz  
YP9  
YN9  
Active-low power-down signal (PWRDWN#) tristates  
all output drivers and disables the PLL  
Packaged in a 48-pin TSSOP  
FBOUTP  
FBOUTN  
GND  
FS61857  
2.0 Description  
Figure 2: Pin Configuration  
The FS61857 is a low skew, low jitter CMOS zero-delay  
phase-lock loop (PLL) clock buffer IC. Ten differential  
buffered clock outputs are derived from an onboard open-  
loop PLL. The PLL aligns the frequency and phase of all  
output clock pairs to the differential reference input clock  
CLKP/CLKN, including a feedback output clock pair that  
feeds back to FBINP/FBINN to close the loop. The PLL  
can be bypassed for test purposes by pulling AVDD to  
ground.  
GND  
YN0  
YP0  
VDD  
YP1  
YN1  
GND  
GND  
YN2  
1
2
3
4
5
6
7
8
9
48 GND  
47 YN5  
46 YP5  
45 VDD  
44 YP6  
43 YN6  
42 GND  
41 GND  
40 YN7  
Table 1: Function Table  
YP2 10  
VDD 11  
VDD 12  
CKP 13  
CKN 14  
VDD 15  
AVDD 16  
AGND 17  
GND 18  
YN3 19  
YP3 20  
VDD 21  
YP4 22  
YN4 23  
GND 24  
39 YP7  
38 VDD  
37 PWRDWN#  
36 FBINP  
35 FBINN  
34 VDD  
33 FBOUTN  
32 FBOUTP  
31 GND  
30 YN8  
INPUT  
OUTPUT  
PLL  
PWR  
DWN#  
YP0-  
YP9  
YN0- FBOUT FBOUT  
AVDD  
CKP CKN  
YN9  
P
N
2.5V  
2.5V  
2.5V  
2.5V  
GND  
GND  
GND  
GND  
-
L
L
H
H
L
L
H
L
H
L
H
L
H
H
L
H
L
H
L
H
L
Z
Z
L
H
Z
Z
L
Z
Z
H
L
Z
Z
H
L
Z
Z
L
H
Z
Z
L
Z
Z
H
L
Z
Z
H
L
OFF  
Zero-  
Delay  
29 YP8  
OFF  
28 VDD  
27 YP9  
L
H
H
-
26 YN9  
PLL  
Bypass  
25 GND  
H
Z
H
Z
OFF  
<20MHz  
Z
Z
ISO9001  
QS9000  
This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.  
11.14.00  
FS61857-01  
1:10 HSTL Zero-Delay Clock Buffer IC  
AMERICAN MICROSYSTEMS, INC.  
Advance Information  
November 2000  
Table 2: Pin Descriptions  
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,  
DO = Digital Output; P = Power/Ground; # = Active Low pin  
PIN  
TYPE  
NAME  
DESCRIPTION  
2.5V PLL power supply / Test mode enable.  
16  
P
AVDD  
This pin provides the power supply to the internal PLL. When pulled low, the PLL is by-  
passed and the output clocks directly follow the input clock  
17  
P
DI  
DI  
DO  
DI  
AGND  
CKP / CKN  
FBINP / FBINN  
FBOUTP / FBOUTN  
PWRDWN#  
YP0 / YN0  
PLL ground  
13 / 14  
36 / 35  
32 / 33  
37  
Reference clock input (true / complementary)  
Feedback input (true / complementary)  
Feedback output (true / complementary)  
Asynchronous power-down input shuts down PLL and tristates all outputs  
3 / 2  
5 / 6  
YP1 / YN1  
10 / 9  
20 / 19  
22 / 23  
46 / 47  
44 / 43  
39 / 40  
29 / 30  
27 / 26  
YP2 / YN2  
YP3 / YN3  
YP4 / YN4  
YP5 / YN5  
YP6 / YN6  
YP7 / YN7  
YP8 / YN8  
YP9 / YN9  
DO  
Clock outputs (true / complementary)  
1, 7, 8, 18, 24, 25,  
31, 41, 42, 48  
4, 11, 12, 15, 21,  
28, 34, 38, 45  
P
P
GND  
VDD  
Ground for all clock outputs  
2.5V power supply for all clock outputs  
3.1  
PLL Bypass  
3.0 Device Operation  
When the AVDD pin is pulled low, the reference clock  
signal bypasses the PLL and is muxed directly through to  
the outputs. The PLL is powered down, and device acts a  
fanout buffer. Note that if AVDD is re-established, the  
PLL requires a power-up and stabilization time to lock to  
the input clock.  
The FS61857 precisely aligns the frequency and phase  
of the differential HSTL output clocks to the differential  
reference input CKP/CKN by use of an on-chip phase-  
lock loop (PLL). The PLL generates 10 low-skew, low-  
jitter copies of the reference, with the outputs adjusted for  
50% duty cycle.  
The differential FBOUT clock must be hardwired to the  
FBINP/FBINN pins to complete the loop. The PLL ac- 3.2  
Power-Down  
tively adjusts the output clocks so that there is no phase  
error between the reference clock and the feedback in-  
put.  
Since the device uses a PLL to lock the output clocks to  
the input clock, there is a power-up stabilization time that  
is required for the PLL to achieve phase lock.  
The FS61857 provides an auto power-down feature that  
shuts off the PLL and tristates all outputs low if the refer-  
ence clock drops below 20MHz. The power-down circuit  
is level sensitive, and detects either a DC high or low on  
the CKP/CKN input pair. If the input clock rises above  
20MHz, the PLL powers back up to re-establish lock.  
Note that all inputs and outputs use 2.5V HSTL signal  
An asynchronous active-low PWRDWN# signal also  
levels.  
places the part in the power off state.  
ISO9001  
QS9000  
2
FS61857-01  
1:10 HSTL Zero-Delay Clock Buffer IC  
AMERICAN MICROSYSTEMS, INC.  
Advance Information  
November 2000  
4.0 Electrical Specifications  
Table 3: Absolute Maximum Ratings  
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at  
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,  
functionality, and reliability.  
PARAMETER  
SYMBOL  
MIN.  
MAX.  
UNITS  
Supply Voltage, dc, Clock Buffers (GND = ground)  
Supply Voltage, dc, Core  
Input Voltage, dc  
AVDD  
VDD  
VI  
VO  
IIK  
IOK  
TS  
TA  
GND-0.5  
GND-0.5  
GND-0.5  
GND-0.5  
-50  
4
4
V
V
V
VDD+0.5  
VDD+0.5  
50  
Output Voltage, dc  
V
Input Clamp Current, dc (VI < 0 or VI > VDD  
)
mA  
mA  
°C  
°C  
°C  
°C  
kV  
Output Clamp Current, dc (VI < 0 or VI > VDD  
)
-50  
-65  
-55  
50  
Storage Temperature Range (non-condensing)  
Ambient Temperature Range, Under Bias  
Junction Temperature  
Lead Temperature (soldering, 10s)  
Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)  
150  
125  
125  
260  
2
TJ  
CAUTION: ELECTROSTATIC SENSITIVE DEVICE  
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy  
electrostatic discharge.  
Table 4: Operating Conditions  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
AVDD  
VDD  
TA  
Core  
Outputs  
2.3  
2.3  
0
2.5  
2.5  
2.7  
2.7  
70  
Supply Voltage  
V
Ambient Operating Temperature Range  
°C  
Frequency range over which PLL  
acquires lock  
Frequency range where all timing  
parameter specification are met  
60  
90  
170  
170  
Input Frequency (CKP / CKN)  
fCLK  
MHz  
Input Duty Cycle  
Input Rise/Fall Time  
Spread-Spectrum Modulation Frequency  
Spread-Spectrum Modulation Index  
Output Load Capacitance  
CKP / CKN  
CKP / CKN (over 20% to 80%)  
40  
0.375  
30  
60  
1.5  
50  
-0.5  
15  
%
ns  
MHz  
%
tr, tf  
fm  
δm  
0
CL  
pF  
ISO9001  
QS9000  
3
FS61857-01  
1:10 HSTL Zero-Delay Clock Buffer IC  
AMERICAN MICROSYSTEMS, INC.  
Advance Information  
November 2000  
Table 5: DC Electrical Specifications  
Unless otherwise stated, all power supplies = 2.5V, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characteri-  
zation data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
Overall  
Supply Current, Dynamic,  
with Loaded Outputs  
Supply Current, Static  
IDD  
VDD = 2.7V, fCLK = 170MHz  
VDD = 2.7V, PWRDWN# low or fCLK < 20MHz  
200  
300  
100  
mA  
µA  
IDDL  
Power Down Input (PWRDWN#)  
High-Level Input Voltage  
Low-Level Input Voltage  
Input Leakage Current  
VIH  
VIL  
II  
1.7  
GND-0.3  
-10  
VDD+0.3  
0.7  
10  
V
V
µA  
VDD = 2.7V  
Differential Clock Inputs (CKP, CKN, FBINP, FBINN)  
Input Voltage Level  
Crossover Voltage  
VIN  
VIX  
GND-0.3  
VDD/2  
-0.2  
VDD+0.3  
VDD/2  
+0.2  
V
V
Magnitude of the difference between the input  
level on CKP and the input level on CKN  
Differential Voltage  
VID  
0.36  
V
DD+0.6  
µA  
Input Leakage Current  
Input Loading Capacitance *  
II  
VDD = 2.7V  
-10  
2.5  
10  
3.5  
CL(in)  
VI = 0V, as seen by an external clock driver  
pF  
Differential Clock Outputs (YP0:9, YN0:9, FBOUTP, FBOUTN)  
VDD = 2.3V, VO = 1.7V  
VDD = 2.3V, VO = 2.2V  
VDD = 2.3V, VO = 0.6V  
VDD = 2.3V, VO = 0.1V  
-12  
12  
mA  
µA  
High-Level Output Source Current  
IOH  
-100  
100  
VDD/2  
-0.2  
mA  
µA  
Low-Level Output Sink Current  
Crossover Voltage  
IOL  
VDD/2  
+0.2  
VOX  
Magnitude of the difference between the  
output levels on YP0:9, FBOUTP and the  
output levels on YN0:9, FBOUTN  
Measured at 1.25V, output driving low  
Measured at 1.25V, output driving high  
Differential Voltage  
VOD  
0.70  
-5  
VDD+0.6  
zO  
zOL  
IOZ  
Ω
Output Impedance  
µA  
mA  
mA  
Tristate Output Current  
5
Short Circuit Source Current *  
Short Circuit Sink Current *  
IOSH  
IOSL  
VO = 0V; shorted for 30s, max.  
VO = 2.5V; shorted for 30s, max.  
ISO9001  
QS9000  
4
FS61857-01  
1:10 HSTL Zero-Delay Clock Buffer IC  
AMERICAN MICROSYSTEMS, INC.  
Advance Information  
November 2000  
Table 6: AC Timing Specifications  
Unless otherwise stated, all power supplies = 2.5V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and  
are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
MIN.  
TYP.  
MAX.  
UNITS  
Overall  
Clock Skew, Output to Output *  
Dynamic Phase Offset  
tsk(o)  
tdΦ  
tΦ  
Measured VX between two output pairs CL = 15pF  
Spread modulation ON  
Spread modulation ON  
Does not include jitter  
Time required for the PLL to achieve phase lock  
ps  
ps  
Static Phase Offset  
Clock Stabilization Time *  
Phase-Lock Loop  
Loop Bandwidth *  
-120  
2.0  
120  
ps  
ms  
For calculation of Tracking Skew  
For calculation of Tracking Skew  
MHz  
°
Phase Angle *  
-0.031  
Phase Error *  
From rising edge on CLK to rising edge on FBIN  
ps  
Clock Outputs (1Y0:9, FBOUT)  
Duty Cycle *  
Jitter, Cycle-cycle *  
(peak-peak)  
dt  
45  
55  
75  
%
tj(CC)  
-75  
ps  
Jitter, Period *  
(peak-peak)  
Jitter, Half-Period *  
(peak-peak)  
tj(∆P)  
-75  
75  
ps  
ps  
tj(∆½P)  
-100  
100  
Rise Time *  
Fall Time *  
Enable Delay *  
Disable Delay *  
tr  
tf  
tDLH  
tDHL  
VO = 0.5V to 2.0V; CL = 15pF  
VO = 2.0V to 0.5V; CL = 15pF  
via PWRDWN#  
0.75  
0.75  
1.5  
1.5  
ns  
ns  
ns  
ns  
via PWRDWN#  
ISO9001  
QS9000  
5
FS61857-01  
1:10 HSTL Zero-Delay Clock Buffer IC  
AMERICAN MICROSYSTEMS, INC.  
Advance Information  
November 2000  
5.0 Package Information  
Table 7: 48-pin TSSOP (6.1mm) Package Dimensions  
DIMENSIONS  
48  
INCHES  
MILLIMETERS  
MIN.  
MAX.  
MIN.  
MAX.  
A
A1  
b
c
D
E
-
0.047  
0.006  
0.011  
0.008  
0.496  
-
1.20  
0.15  
0.27  
0.20  
12.60  
0.002  
0.0067  
0.0035  
0.488  
0.05  
0.17  
0.09  
12.40  
E1  
E
AMERICAN MICROSYSTEMS, INC.  
0.318 BSC  
8.10 BSC  
E1  
e
L
0.236  
0.019 BSC  
0.018  
0.008  
0°  
0.244  
6.00  
0.50 BSC  
0.45  
0.20  
0°  
6.20  
1
SEATING PLANE  
0.030  
-
8°  
0.75  
-
8°  
b
e
S
θ2  
θ3  
c
S
A
θ1  
θ2  
θ3  
L
θ1  
D
A1  
12° REF  
12° REF  
12° REF  
12° REF  
Table 8: 48-pin TSSOP (6.1mm) Package Characteristics  
PARAMETER  
SYMBOL  
CONDITIONS/DESCRIPTION  
TYP.  
UNITS  
ΘJA  
L11  
L12  
L13  
C11  
C12  
C13  
Thermal Impedance, Junction to Free-Air  
Lead Inductance, Self  
Air flow = 0 m/s  
Longest lead  
89  
°C/W  
nH  
3.50  
1.82  
1.17  
0.63  
0.30  
0.03  
Longest lead to any 1st adjacent lead  
Longest lead to any 2nd adjacent lead  
Longest lead to VSS  
Lead Inductance, Mutual  
Lead Capacitance, Bulk  
Lead Capacitance, Mutual  
nH  
pF  
pF  
Longest lead to any 1st adjacent lead  
Longest lead to any 2nd adjacent lead  
ISO9001  
QS9000  
6
FS61857-01  
1:10 HSTL Zero-Delay Clock Buffer IC  
AMERICAN MICROSYSTEMS, INC.  
Advance Information  
November 2000  
6.0 Ordering Information  
Table 9: Device Ordering Codes  
DEVICE  
OPERATING  
TEMPERATURE RANGE  
SHIPPING  
CONFIGURATION  
ORDERING CODE  
NUMBER  
PACKAGE TYPE  
48-pin TSSOP  
0°C to 70°C (Commercial)  
FS61857-01  
13810-801  
Tape and Reel  
(Thin Shrink Small Outline Package)  
Copyright © 2001 American Microsystems, Inc.  
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI  
makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom  
of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI re-  
serves the right to discontinue production and change specifications and prices at any time and without notice. AMI’s products are  
intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental require-  
ments, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom-  
mended without additional processing by AMI for such applications.  
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,  
WWW Address: http://www.amis.com E-mail: tgp@amis.com  
ISO9001  
QS9000  
7

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