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MTC-20277PQ-C [AMI]

ISDN Controller, 1-Func, CMOS, PQFP44, PLASTIC, QFP-44;
MTC-20277PQ-C
型号： MTC-20277PQ-C
厂家： AMI SEMICONDUCTOR    AMI SEMICONDUCTOR
描述：

ISDN Controller, 1-Func, CMOS, PQFP44, PLASTIC, QFP-44

综合业务数字网
文件： 总40页 (文件大小：276K)
中文：  中文翻译
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MTC-2 0 2 7 7 IN TT  
Single Chip ISDN NT, 4B3T  
Data Sheet and  
User Manual  
Rev. 1.2 - October 1998)  
Ke y fe a tu re s:  
Ap p lica tio n s:  
Ge ne ra l De scrip tion  
The MTC-20277 INTT integrates all of  
the communications functions required  
in a Basic Rate ISDN Network Termi-  
nator on a single monolithic integrat-  
ed circuit. The INTT is designed for  
the 4B3T line-code on the U interface  
and is pin compatible with the MTC-  
20276 INTQ, which performs identi-  
cal functions but with the 2B1Q U  
interface line code.  
▼ Fu lly in te g ra te d ISDN N T  
d e vice  
▼ Sta n d a rd ISDN N T1 a p p lica -  
tio n s (fre e -sta n d in g m o d e )  
▼ Ex p a n d e d fu n ctio n s th ro u g h  
sta n d a rd GCI p o rt:  
- ‘U’ a n d ‘S’ in te rfa ce s in  
o n e p a ck a g e  
▼ Pin co m p a tib le w ith MTC-  
2 0 2 7 6 IN TQ (2 B1 Q )  
* An a lo g lin e in te rfa ce s  
(“ N T1 +” )  
▼ Fu ll co m p lia n ce w ith th e  
a p p lica b le ETSI, ITU a n d FTZ  
re q u ire m e n ts  
* Micro -PABX  
* Da ta netw ork g a tew a ys  
▼ Minim a l ex terna l com p onents  
- u se s sta n d a rd , re a d illy  
a va ila b le p a ssive d e vice s  
▼ < 3 0 0 m W p o w e r co n su m p -  
tio n , 3 .3 V o p e ra tin g vo lta g e  
▼ Ad va n ce d 0 .5 µ CMO S  
m ix e d a n a lo g / d ig ita l  
p ro ce ss te ch n o lo g y  
ISDN NT  
module  
Power Supply  
Ana log  
Support  
Functions  
TX  
TX  
▼ 4 4 p in Pla stic Q u a d Fla t  
Pa ck p a ck a g e  
Uk0  
S0  
‘U’ interface  
‘S’ interface  
4-wire /  
2 wire  
resistor  
network  
(S-bus mode  
RX  
RX  
SPI and  
Aux. test  
access  
JTAG  
test  
access  
Digital Expansion and Test logic  
Dual GCI access  
and expansion  
port  
Power-on  
Reset  
Crystal  
Oscillator  
MTC-20277 INTT  
Ord ering Inform a tion  
Part number  
Package  
Code Temp.  
Optional Expanded functions  
(Analog lines, data  
interfaces,...)  
MTC-20277PQ-C 44 pin PQFP PQ44 0 to 70°C  
MTC-20277PC-C 44 pin PLCC PC44 0 to 70°C  
MTC-20277PQ-I 44 pin PQFP PQ44 -40 to 85°C  
MTC-20277PC-I 44 pin PLCC PC44 -40 to 85°C  
Fig .1 : MTC-2 0 2 7 7 Ap p lica tio n Blo ck Dia g ra m  
The MTC-20277 uses the  
ARM7TDMI processor core  
from ARM Ltd, UK  
MTC-2 0 2 7 7 IN TT  
NT a nd Ex te nd e d NT  
Functions (“ NTp lus” )  
The MTC-20277 requires very few  
external components, all of which are  
low-cost and readilly available types.  
In addition, the use of a 44PQFP  
package style allows further savings  
in the total cost and physical size of  
the ISDN NT module. Though  
The MTC-20277 has a number of test  
access ports to facilitate system or  
production testing. One of these ports  
is configured as a dual GCI interface,  
which operates in one of two modes.  
In Mode 0 (GMode = logic 0), the  
GCI port allows the data flow  
The application circuit section  
describes the circuit configuration of  
the MTC-20277 in its stand alone  
mode, for conventional NT1 applica-  
tions.  
Figure below shows the system con-  
cept of an MTC-20277 in an “NT1+”  
application, in combination with the  
Alcatel Microelectronics MTK-40130  
“SH-POTS” chipset for short-haul ana-  
log telephone lines, and the MTC-  
20270 CITA which performs the nec-  
essary control and interface functions.  
designed primarilly for simple ISDN  
NT modules, the INTT offers an  
between the 'U' and the 'S' ports to  
be optionally monitored.  
expansion port, using the industry-  
standard GCI format, to allow extend-  
ed functions to be added (e.g. inter-  
faces to existing analog terminal  
equipment by means of the MTK-  
40130 Short-Haul POTS chipset).  
This is the “alone” mode, which is the  
normal mode for simple NT1 applica-  
tions. No additional microprocessor  
or other control device is required in  
this mode.  
Mode 1 (GMode = logic1) allows  
separate access to the 'U' and the 'S'  
ports, for use by an external GCI  
compatible controller device. In this  
mode,the chip supports additional  
features required by extended NT  
modules (“NT1+”) such as interfaces  
to existing analog equipment, or  
advanced data communication gate-  
ways.  
Standards Compliance  
MTC-20277 complies with relevant  
ETSI specifications.  
V12:  
ETSI ETS 300 297  
ETSI ETS 300 012  
PC / POS Terminal  
Digital Telephone  
ISDN Line Connection  
U
S - bus  
MTC-20276/ 7  
INT  
S
Power  
Supply  
GCI  
mains  
Analog  
FAX  
Analog Line 1  
Analog Line 2  
MTC-  
30132  
SH-LIC  
MTC-2028x  
MTC-  
20232  
CODSP  
Controller for  
ISDN  
Terminal  
Adapters  
(under development)  
GCI  
MTC-  
30132  
SH-LIC  
Existing Analog Installation  
Answering Machine  
Analog Telephone  
MTK-40130  
SH-POTS chipset  
“NT1+” Box  
Fig .2 : Concep t of a n NT1 + Config ura tion for 2 Ana log Lines  
2
MTC-2 0 2 7 7 IN TT  
Pa ck a g e / Pin o u t  
40  
41  
42  
43  
44  
SXP  
LOUT2  
AREF  
LIN1  
28  
27  
SXN  
26  
SRP  
25  
LIN2  
SRN  
24  
TRST  
TCK  
AUX  
MTC-20277  
INTT  
23  
SPIDO  
2
3
4
22  
TMS  
SPIDI  
21  
TDI  
VDD  
20  
TDO  
XTAL1  
5
6
19  
SPICK  
SPICS  
XTAL2  
18  
VSS  
Fig .3 a : Pin o u t, 4 4 PLCC Pa ck a g e (MTC-2 0 2 7 7 -PC)  
1
SXP  
LOUT2  
33  
2
32  
SXN  
AREF  
3
31  
LIN1  
SRP  
4
30  
LIN2  
SRN  
5
29  
TRST  
AUX  
MTC-20277  
INTT  
6
28  
TCK  
TMS  
SPIDO  
7
27  
SPIDI  
8
26  
TDI  
VDD  
9
25  
TDO  
XTAL1  
10  
11  
24  
SPICK  
SPICS  
XTAL2  
23  
VSS  
Fig .3 : Pin o u t, 4 4 PQ FP Pa ck a g e (MTC-2 0 2 7 7 -PQ )  
3
MTC-2 0 2 7 7 IN TT  
Pin De scrip tio n  
Pin number one for the 44PQFP package.  
N r.  
Fu n ctio n  
N a m e  
Dir.  
De scrip tio n  
44  
1
LOUT1  
LOUT2  
O
O
U interface analog outputs. The connections LOUT1 and LOUT2 interface  
the U driver outputs, via termination resistors and the line coupling  
transformer, to the UK0 reference point.  
U
3
4
LIN1  
LIN2  
I
I
U interface analog inputs to the INTT from the analog ‘hybrid’  
Int.  
2
43  
42  
AREF  
AVDD  
AVSS  
O
P
P
Analog ground. Used as reference voltage for analog functions  
VDD for analog U interface functions  
VSS (0V ground) for U interface analog functions  
33  
32  
SXP  
SXN  
O
O
S interface analog outputs. SXP and SXN interface the S-driver outputs  
via terminating resistors and the TX line coupling transformer to the S0  
reference point (Tx).  
31  
30  
37  
S
SRP  
SRN  
SBUS  
I
I
I
S interface analog inputs. SRP and SRN interface the S inputs via a line  
coupling transformer to the S0 interface point (Rx).  
S-bus type configuration. 1 = short bus with fixed timing, 0 = adaptive  
timing for extended bus or point-to-point  
Int.  
34  
36  
35  
12  
13  
14  
15  
SATP  
AVDD  
AVSS  
G1DOUT  
G1DIN  
G1DCLK  
G1DFR  
O
P
P
O
I/ O  
O
Analog test pin. Used for test purposes only, should be left open circuit  
VDD for analog S interface functions  
VSS (0V ground) for S interface analog functions  
Primary GCI interface G1:  
GMODE = 0 : Monitoring of the internal GCI between the U and S.  
GMODE = 1 : NTplus mode; complete GCI connected to U with U as master.  
G1DOUT = data output  
GCI  
Int.  
O
G1DIN = data input (output direction in monitoring mode)  
G1DCLK = 512 KHz GCI clock  
G1DFR = 8KHz GCI frame clock which identifies the beginning of  
the frame of G1DIN and G1DOUT  
18  
19  
20  
21  
G2DOUT  
G2DIN  
G2DCLK  
G2DFR  
O
I
I
Secondary GCI interface G2:  
GMODE = 0 : No function  
GMODE = 1 : NTplus mode; complete GCI connected to S with external master.  
G2DOUT = data output  
I
G2DIN = data input  
G2DCLK = 512KHz GCI clock  
G2DFR = 8KHz GCI frame clock which identifies the beginning of  
the frame of G2DIN and G2DOUT  
Remark : if NT Plus mode not used, the inputs have to be strapped  
low.  
22  
GMODE  
I
Select NTplus mode. 0 = monitoring mode, 1 = NTplus mode.  
5
6
7
8
9
TRST  
TCK  
TMS  
TDI  
I
I
I
I
O
TAP controller reset, active low  
TAP controller clock, maximum 10 MHz  
TAP controller mode selection  
TAP controller input  
JTAG  
Int.  
TDO  
TAP controller output  
4
MTC-2 0 2 7 7 IN TT  
41  
NRESET  
I
Hardware reset, active low. Schmitt trigger input for connection to  
external RC or logic device. Reset pulse min. 10ms. (threshold 1.65V CMOS level)  
Connection to external crystal (15.36MHz ± 100ppm loading caps 2x22pF)  
Connection to external crystal. May also be used as input for external  
master clock source.  
25  
24  
XTAL1  
XTAL2  
I
I
40  
TSP  
I
Test Single Pulses. INT transmits alternate positive and negative pulses  
to act as test and search-tone on the line. Pulse repetition rate is 1KHz at the  
‘U’ interface, and about 4KHz on the ‘S’ interface.  
Test input only (strap to ground)  
39  
38  
AUX1  
AUX2  
I
I
Selection between S block mode 1 = reduced  
0 = normal  
10  
11  
27  
SPICK  
SPICS  
SPIDI  
O
O
I
SPI  
Int.  
Must be strapped to ground for normal operation of MTC-20277.  
28  
SPIDO  
O
29  
16  
26  
17  
23  
AUX  
VDD  
VDD  
VSS  
I
Must be strapped to ground for normal operation of MTC-20277.  
Positive supply for digital functions  
P
P
P
0V ground for digital functions  
VSS  
5
MTC-2 0 2 7 7 IN TT  
Ap p lica tio n Sch e m a tic  
C3  
C4  
Vdd  
Vdd  
Vdd  
C2  
R13  
S-bus type  
AREF  
LIN1  
VSS  
VDD AVSS  
AVDD SBUS  
S1  
T1  
T2  
R8  
SXP  
SXN  
LOUT1  
S0 (Tx)  
S0 (Rx)  
Rt  
Z
R9  
Passive  
Hybrid  
(Figure 4a)  
UK0 Power Feed  
(30..100V)  
MTC-20277  
INTT  
Clf  
T3  
Z
R10  
SRP  
SRN  
TSP  
LOUT2  
LIN2  
Rt  
Z
Vdd  
R11  
line test  
D1  
+/ - 40V  
-/ + 40V  
NRESET  
S2  
R12  
Vdd  
R7  
OPTO LED  
X1  
X2  
GMODE  
Power Supply  
C1  
230V AC  
Vdd  
X1  
R14  
R20  
Metalic Line  
Termination  
Circuit  
Vss  
Vdd (+3.3V)  
C7  
C6  
R15  
C5  
30...100V from  
UK0 power feed  
*
* North American Market Only  
Z1  
Fig .4 : Ap p lica tio n Sch e m a tic  
LIN1  
Com p onent  
Function  
Va lue  
Com m ent  
R1,R6  
R2,R4  
R3,R5  
R7,R12,R13  
R8,R9  
U feed  
25R  
3k3  
7k  
100k  
34R  
5k  
±1%  
±1%  
±1%  
U feed bridge  
U feed bridge  
Pull-up/ down  
S-bus transmit impedance  
S-bus receive impedance  
S-bus termination resistor  
±1%  
±1%  
R10,R11  
Rt  
100R  
X1  
crystal  
15.36 MHz  
see text  
Ch  
C1  
C2,C3,C4  
U feed bridge filter  
reset delay  
supply decoupling  
330p  
100n  
100n  
C5,C6  
C7  
R20  
Clf  
crystal load  
crystal load  
crystal load  
22p  
see text  
see text  
0 to 22p  
1m Ω  
2µ2  
Line-feed coupling  
250V  
D1  
loss-of-power reset  
1N4148  
any small signal diode  
T1  
T2,T3  
U transformer  
S transformer  
1.6:1, 6mH  
2:1  
see text  
see text  
S1  
S2  
S3  
switch  
switch  
jumper  
-
-
-
S-bus mode  
Test signal  
S-interface functions  
Z
overvoltage protection  
1N4004  
see text  
6
MTC-2 0 2 7 7 IN TT  
Tra n sfo rm e r Sp e cifica tio n s:  
S-in te rfa ce  
Pa ra m eter  
Min  
2 : 1  
20  
Ma x  
Units  
Turns Ratio  
Line : Chip  
mH  
Primary Inductance  
Leakage Inductance  
Interwinding Capacitance  
PRI DCR  
13  
µH  
50  
pF nominal  
Ω (1.1Ω ± 20%)  
Ω (2.6Ω ± 20%)  
0.9  
2.1  
1.3  
3.1  
SEC DCR  
U-in te rfa ce  
Pa ra m eter  
Min  
Ma x  
Units  
Turns Ratio  
1.6 : 1  
5.25  
Line : Chip  
Primary Inductance  
Leakage Inductance  
Interwinding Capacitance  
PRI DCR  
6.75  
60  
mH  
µH  
pF  
Ω
90  
6
7
SEC DCR  
3.5  
4.2  
Ω
Ma ste r Clock a nd XTAL Conne ctions  
At the pins XTAL1 and XTAL2 a  
crystal must be connected to form a  
parallel mode oscillator. Two capaci-  
tors of 22 pF have to be connected to  
ground.  
22pF  
15.36 MHz  
XTAL1  
XTAL2  
Cp  
Some crystals may require the parallel  
capacitor Cp to be used (10 pf Typ).  
1MΩ  
22pF  
Fig .5 : Cry sta l Co n fig u ra tio n  
Ex a m p le Cry sta l Sp e cifica tio n s  
AT cut, fundamental mode  
Series resonance frequency  
Initial tolerance  
15.360  
± 100  
± 10  
MHz  
ppm  
ppm  
Frequency drift  
Dynamic capacitance  
Load capacitance  
Parallel capacitance  
Series resistance  
15  
30  
7
40  
± 10  
fF (info)  
pF  
pF (info)  
Ω
Series resistance drift (age)  
%
Drive level  
0.25  
mW  
7
MTC-2 0 2 7 7 IN TT  
O ve rvo lta g e Pro te ctio n  
This is strongly dependant on the PCB  
layout and local specification varia-  
tions. Generally, Mietec recommends  
the use of standard small-signal diodes supply rails, and for the S interface  
(e.g. 1N4004) to clamp voltages from  
the S- and U interfaces to Vdd and  
ground. The recommended protection  
for the U interface is to diode clamp  
the chip side transformer pins to the  
disturbance voltages from causing the  
power-supply voltage to increase (full-  
wave rectifier effect through the protec-  
tion diodes), it is recommended that a  
zener-diode is used to clamp the Vdd  
voltage.  
clamp the INTT device pins (30,31,  
32,33). In order to prevent excessive  
Un u se d Pin s  
below to ensure proper operation in a  
given application. ‘0’ means connect  
to ground, ‘1’ means connect to Vdd,  
‘open’ means make no connection.  
A dash (‘-’) means that the pin is used  
in the application. All other pins have  
defined states as shown in the applica-  
tion schematic.  
The INTT has a number of device pins  
which are used only in specific appli-  
cations, or for device testing. These  
pins should be connected as shown  
Pin  
num b er  
NT m od e  
NT+ m od e  
GMODE  
22  
0
1
G2DOUT  
G2DIN  
G2DCLK  
G2DFR  
18  
19  
20  
21  
open  
-
-
-
-
1
0
0
G1DOUT  
G1DIN  
G1DCLK  
G1DFR  
12  
13  
14  
15  
open/ monitor  
open/ monitor  
open/ monitor  
open/ monitor  
-
-
-
-
TRST  
TCK  
TMS  
TDI  
5
6
7
8
9
0 (pull down)  
1 (pull up)  
1 (pull up)  
1 (pull up)  
open  
0 (pull down)  
1 (pull up)  
1 (pull up)  
1 (pull up)  
open  
TDO  
AUX  
AUX1  
29  
39  
0
0
0
0
SPICK  
SPICS  
SPIDI  
10  
11  
27  
28  
open  
open  
0
open  
open  
0
SPIDO  
open  
open  
SATP  
TSP  
34  
40  
open  
open  
0 (normal)  
0 (normal)  
1 ( test pulses)  
1 ( test pulses)  
AUX2  
S BUS  
38  
37  
0 (normal S protocol)  
1 (reduced S protocol)  
0 (normal S protocol)  
1 (reduced S protocol)  
0 (P-P S Bus)  
0 (P-P S Bus)  
1 (Short S Bus)  
1 (Short S Bus)  
8
MTC-2 0 2 7 7 IN TT  
Co m m o n Hy b rid Sch e m a tics fo r 4 B3 T (MTC-2 0 2 7 7 ) a n d 2 B1 Q (MTC-2 0 2 7 6 )  
LIN1  
12,3Ω  
LOUT1  
4n7  
T1  
100  
4k32  
6k81  
6k81  
1k  
1k  
39n  
39n  
576  
470p  
4k32  
2n7  
100  
4n7  
LOUT2  
LIN2  
12,3Ω  
MTC-2 0 2 7 6 - Recom m end ed Hyb rid com p onent Config ura tion  
LIN1  
25Ω  
LOUT1  
T1  
=
3k3  
=
=
7k  
7k  
*
*
=
=
*
470p  
3k3  
=
LOUT2  
LIN2  
=short  
25Ω  
(* for FTZ loops, 470p -> 680p and 7kΩ -> 6k8)  
Fig .5 a : MTC-2 0 2 7 7 - Recom m end ed Hyb rid Com p onent Config ura tion,  
using sa m e PCB la yout a s 2 0 2 7 6 , (ETSI loop s)  
9
MTC-2 0 2 7 7 IN TT  
(5 ohm resistance reduces  
total power consumption)  
Vdd in  
0 .. 5Ω  
10µ + 100n  
10µ + 100n  
43  
36  
16  
26  
AVDD  
AVDD VDD VDD  
AVSS  
AVSS  
VSS VSS  
42  
35  
17  
23  
Vss in  
Fig . 5 b : MTC-2 0 2 7 6 / 2 0 2 7 7 Recom m end ed Pow er Sup p ly Arra ng em ent  
10  
MTC-2 0 2 7 7 IN TT  
Ele ctrica l Ch a ra cte ristics  
Ab so lu te Ma x im u m Ra tin g s  
Operation of the device at or near  
these conditions is not guaranteed.  
Sustained exposure to these limits will  
adversely effect device reliability.  
Pa ra m eter  
Ma x  
Units  
DVDD, AVDD  
Vin, Voltage on any device pin  
3.63  
VSS-0.3  
V
V
VDD+0.3 or 3.63  
V, whichever is lower  
Storage temperature  
Temperature under bias  
-55 to +110  
-55 to +125  
°C  
°C  
O p e ra tin g Co n d itio n s  
Unless otherwise stated, all subsequent  
electrical characteristics are valid over  
the ranges specified here. (Vss = 0V).  
Pa ra m eter  
Min  
Ma x  
3,45  
10  
Units  
V
Note  
DVDD, AVDD  
3,15  
=3.3V ±5%  
SNAVDD, supply noise, analog  
SNDVDD, supply noise, digital  
SNAREF, supply noise, analog ref.  
IAREF  
mVpp  
mVpp  
mVpp  
mA  
100  
0.1  
Note 2  
- 0,25  
15,36  
- 40  
+ 0,25  
15,36  
+85  
70  
load on AREF Pin  
±50ppm, Note 1  
- I suffix  
Crystal frequency  
Mhz  
°C  
Temperature range  
0
°C  
- C suffix  
Note 1. An external clock may be  
applied to XTAL2, pin 24. Tempera-  
ture dependent drift <10ppm.  
Note 2. AREF is an output, designed  
to allow a decoupling capacitor to be  
placed on the internal analog refer-  
ence voltage. The external circuit lay-  
out must avoid the induction of noise  
on this pin.  
11  
MTC-2 0 2 7 7 IN TT  
DC Ch a ra cte ristics  
Pa ra m eter  
Cond itions  
Min  
Ma x  
Units  
Note  
Ptot  
Ppd  
Total power consumption, active  
Power consumption, power-down  
350  
20  
mW  
mW  
1,3  
VIH  
VIL  
VOH  
VOL  
Input level, logic 1  
Input level, logic 0  
Output level, logic 1  
Output level, logic 0  
0.8  
DVDD  
DVDD  
DVDD  
V
2
2
2
2
0.2  
0.4  
0.85  
VAREF  
Reference voltage output,  
load current < ±250µA.  
1.6  
1.6  
1.7  
1.7  
V
V
(1.65V±3%)  
VTNRES  
Nreset input threshold  
N o te 1 : U and S active, random sig-  
nal. U loaded 135 Ohm, S loaded 50  
Ohm.  
AVDD (U - PIN 43) = 3.3V  
AVDD (S - PIN 36) = 3.0V*  
DVDD (PIN 16 & 26) = 3.0V*  
Note 2 : All logic pins except NRESET,  
which is a Schmitt-trigger input with hys-  
teresis.  
* Using 4 Ω resistor to AVDD (PIN 43)  
Note 3 : 320 mw TYP  
AC Ch a ra cte ristics  
Pa ra m eter  
Cond itions  
Min  
Ma x  
Units  
Note  
Cin  
Cload  
VTNRES  
Input capacitance any pin  
Load capacitance on any output pin  
Reset pulse width  
1
100  
pF  
pF  
mS  
10  
Q u a lity / Re lia b ility  
Early failure rate  
Long term failure rate  
Lifetime  
≤ 0.3% at 3000 hours  
≤ 300 FIT for 45°C average ambient and 45% average humidity  
≥ 15 years  
12  
MTC-2 0 2 7 7 IN TT  
De ta ile d Fu n ctio n a l De scrip tio n  
GCI In te rfa ce , Co m m o n Fu n ctio n s  
Da ta Fo rm a t a n d Tim in g o f th e GCI In te rfa ce  
(DIN , DO UT, DCLK, DFR)  
Continuous Mod es  
Nominal bitrate of data (DIN and DOUTJ  
Nominal frequency of clock (DCLK)  
Peak-to-peak output jitter (DCLK)  
256 kbit/ s  
512 kHz  
≤ 166 ns  
Nominal frequency of frame clock (DFR)  
Mark-to-space ratio of DFR, i (input)  
Mark-to-space ratio of DFR, o (output)  
8 kHz  
1:2 . . . 2:1  
0.4:0.6 . . . 0.6:0.4  
Figure 6 shows the timing of data and  
clocks at the digital interface 256 kbit/ s  
(continuous modes).  
The start of the frame is marked by the  
rising edge of the frame clock DFR.  
Transitions of the data occur after even  
numbered rising edges of the DCLK.  
The data is valid on the odd  
numbered rising edges of the DCLK.  
Even-numbered rising edges of the  
clock are defined as the second rising  
edge following the rising edge of  
the frame clock and every second rising  
edge thereafter.The maximum allowed  
jitter is shown in figure 7.  
One frame contains four time slots. The  
data streams at DIN and DOUT consist  
of four bytes per frame. See figure 8.  
The input data DIN and the output data  
DOUT are synchronous and in phase.  
In the power-down state, the signal at  
DIN and at DOUT is high and the sig-  
nal at DFR and DCLK is low.  
Fig .6 : Tim ing of Da ta a nd Clock s a t the GCI Interfa ce  
13  
MTC-2 0 2 7 7 IN TT  
Fig .7 : Ma x im um a d m issa b le p ea k -to-p ea k inp ut jitter of clock s  
(DCLK, DFR) a t m od ule interfa ce  
Fra m e Form a t  
4 bytes are transmitted in each frame:  
1st byte B1: B-channel (64 kbit/ s data), transparent  
2nd byte B2: B-channel (64 kbit/ s data), transparent  
3rd byte B2*: Monitor channel  
DIN: 8 bit address  
DOUT: 8 bit data  
MSB first  
4th byte B1 *:  
2 bit D-channel (16 kbit/ s data)  
4 bit C/ l channel A1, A2, A3, A4  
A, E bit used to control the transfer of information  
on the Monitor channel  
Fig .8 : GCI Fra m e form a t  
14  
MTC-2 0 2 7 7 IN TT  
Ex te rna l GCI Inte rfa ce s  
Fig . 9 : Ex terna l GCI interfa ce  
G1 Ex terna l GCI Interfa ce  
Figure 9 shows a schematic representa-  
tion of the two possible modes of the  
GCI ports.  
In normal mode, corresponding to pin  
GMODE low, the two internal GCI  
interfaces are shorted. The G1 interface  
is used as a monitor.  
The UIC block is the master of the GCI  
interface and thus controls the GCI  
clock (DCLK) and the GCI frame (DFR).  
DCLK and DFR signals at the G1 inter-  
face are outputs of the INTT.  
G1 interface characteristics:  
- G1 DOUT: output, data channel,  
256 KHz  
- G1 DIN: input in NTplus mode,  
output in normal mode; data channel,  
256 KHz  
- G1 DFR: output, frame clock, 8 KHz  
- G1 DCLK:output,clock, 512 KHz  
In NTplus mode, corresponding to pin  
GMODE being high, the GCI interface  
coming from the UIC block is connected  
to the G1 External GCI.  
15  
MTC-2 0 2 7 7 IN TT  
G2 Ex terna l GCI Interfa ce  
In normal mode, corresponding to pin  
GMODE low, the two internal GCI  
interfaces are connected together. G2  
interface has no function.  
G2 interface characteristics:  
- G2 DOUT,: output, data channel,  
256 KHz  
- G2 DIN,: input, data channel,  
256 KHz  
- G2 DFR: input, frame clock, 8 KHz  
- G2 DCLK: input, clock, 512 KHz  
In NTplus mode, corresponding to pin  
GMODE high, the GCI interface of the  
SIC block is connected to the G2  
External GCI.  
The SIC block is the slave of the GCI  
interface, so the GCI clock (DCLK) and  
the GCI frame (DFR) signals at the G2  
interface are inputs of the INTT .  
16  
MTC-2 0 2 7 7 IN TT  
U Interfa ce Com m a nd List  
The evaluation of any command is done  
according to a double last look criteri-  
on: any command is recognized only  
after the same command has been  
detected in two successive frames. Until  
then the preceding command is consid-  
ered valid.  
If commands are received that are not  
included in the list, the last recognized  
command is considered valid. Com-  
mands which are logically impossible to  
receive in the current state are ignored  
(ref. ETR 80).  
The indications are transmitted continu-  
ously in each frame. Under no circum-  
stances can an indication that is not  
included in the list is transmitted.  
The maintenance and Service Chan-  
nel, and the B2* Channel are not used  
by the UIC block.  
Co m m a n d a n d In d ica te (C/ l) Ch a n n e l (A b its)  
Command (DIN) (from GCI to U) discription of events in MTC-20277  
Awake  
0000: AW  
This command has to be used when the deadivated module interface is  
to be set in the power-up state. The command may be represented by a  
steady state binary '0' condition at DIN. The module interface will be activated,  
i.e. provided with bit and frame clocks for synchronous transmission.  
Any other command may now be applied.  
The command AW, however, maintains the activated state of the module interface  
without emission of any signal at U.  
Activate  
1000: ACT  
11 00: SY  
1111: DC  
Layer 1 is activated at the U interface, starting with transmission of the wake-up  
signal INFO U1W. After execution of the wakeup procedure, the transmitter  
generates INFO U1A during synchronization process.When synchronization is  
completed successfully, the transmitter outputs INFO U1.  
Synchronized  
Deactivate  
When the synchronization process of the receiver is completed successfulIy, the  
transmitter outputs INFO U3. After reception of INFO U4, ACT is indicated, and  
the INTT will be connected through from module interface to line interface  
(transparent).  
This command enables the receiver to recognize Confirmation wake-up signals at  
the U interface, but the transmitter still is disabled. If no wake-up signal is  
recognized, the INTT is set to its power-down state. The module interface will  
be deactivated.  
17  
MTC-2 0 2 7 7 IN TT  
Indication (DOUT) (From U to GCI)  
Deactivate  
0000: DEAC  
0010: TM1  
01 00: RESYN  
1000: ACT  
1010: L2  
A request to deactivate level 1 (INFO U0) has been detected. INFO U0  
is transmitted at U.  
Test mode 1  
Forces SIC in test mode 1, sending single zeros.  
Not supported by the UIC but recognized by the SIC (NTplus mode only)  
Resynchro-  
nization  
The receiver has lost framing and is attempting to resynchronize. The INTT  
remains connected through from module interface to line interface (transparent).  
Activate  
The synchronous state of the receiver is established (without a loop 2 or a loop 4  
command). The transmitter outputs INFO U1.  
Loop 2  
The synchronous state of the receiver is established with a loop 2 command.  
The transmitter outputs INFO U3.  
Connection  
Through  
1100: CT  
INFO U4H has been detected at the U interface.  
The INTT will be connected through from module interface to line interface  
(transparent).  
Connection  
Through  
with Loop 2  
1110: CTL2  
1111: DC  
INFO U4H and a loop 2 command have been detected at the U interface.  
The INTT will be connected through from module interface to line interface  
(transparent).  
Deactivated  
Confirmation  
The transmitter is disabled, but the receiver remains enabled to detect wake-up  
signals at the U interface. The INTT is set in its power-down state, as long as wake-  
up signals are not recognized.  
When a wake-up procedure is finished, INFO U1A is transmitted.  
Pow er Dow n of the Interfa ces  
In the following description, the U inter-  
face port of the GCI interface (G1) is the  
master, and the S port of the GCI (G2)  
is the slave.  
Tra nsition from Synchronous to  
Pow er-Dow n Sta te  
The corresponding procedure is shown  
in figure 10. After a DC code has been  
detected at the module interface of the  
master in two successive frames from the  
slave, the master responds by indicating  
DC four times and then the master turns  
off the timing signals at the end of bit  
A4 of the fourth DC indication. After this  
time, the DOUT pins of master and slave  
must be kept HIGH (quiescent condi-  
tion).  
18  
MTC-2 0 2 7 7 IN TT  
Fig .1 0  
W a k e -u p Orig ina ted b y Sla ve  
Transition from power-down to  
After the timing signals have been  
detected by the slave, the slave must  
transmit AW for at least two frames  
(e.g. 8 frames). Then the slave may  
insert a valid code in the C/ I channel  
(e.g. ACT).  
Monitoring of pin DOUT for LOW by  
the master will start only after the tim-  
ing signals have been turned off.  
synchronous operation is initiated by  
the slave by transmitting LOW at  
DOUT. See the figure above.  
The master responds by turning timing  
signals on within Taw (typical 4 ms,  
max. 10 ms). To ensure continuous  
supply of timing signals by the master  
the slave must keep DOUT LOW.  
19  
MTC-2 0 2 7 7 IN TT  
It is required that the clock signals at  
DCLK and DFR will have the nominal  
frequency with the specified tolerance  
from the moment they are turned on.  
The slave may deactivate the master if  
only AW (not yet ACT) has been  
detected by the DC command or by  
transmitting continuous HIGH at  
DOUT. The master will respond by  
turning off the timing signals.  
See figure 11.  
Fig .1 1  
W a k e -u p Orig ina ted b y the  
Ma ster  
Transition of the device from power-  
down to synchronous state can  
be initiated by the master by turning  
on clock signals DCLK and DFR. Simul-  
taneously, the master must apply the  
desired command code in the C/ I  
channel.  
The slave may enter the power-up  
state immediately after clock signals  
have been applied, and the received  
command code has been evaluated.  
See figure 12.  
Fig .1 2  
20  
MTC-2 0 2 7 7 IN TT  
S-In te rfa ce Co m m a n d s a n d In d ica tio n s Su m m a ry  
Ta b le 1 5  
N T  
Do w n str  
Up str.  
Do w n str  
Up str.  
Co m m a n d  
In d ica t.  
Co m m a n d In d ica t  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
DR  
TIM  
1000  
1001  
1010  
1001  
1100  
1101  
1110  
1111  
ARd  
ARu  
RES  
(lsl)  
-
-
ssz=TM1  
-
ARL  
-
TM2  
-
-
-
RSYd  
RSYu  
AId  
AIu  
-
-
-
-
-
-
ei  
-
AIL  
-
did=DC  
DIu  
Com m a nd s (Dow nstrea m ) in NT Mod e  
Ta b le 1 6  
0000  
0001  
0010  
0011  
0100  
1000  
1010  
1100  
1110  
1111  
DR  
Deactivate  
Request  
Forces the S-interface block to deactivate the S-bus (=INFO0)  
followed by DIu and did=DC  
RES  
RESET  
Forces S-interface to soft reset, extended mode only,  
S-interface accepts it in basic mode (merged)  
ssz  
= TM1  
TEST-MODE 1  
TEST-MODE 2  
Forces S-interface to test-mode 1, sending  
single zeros  
TM2  
RSYd  
ARd  
ARL  
AId  
Forces S-interface to test-mode 2, extended mode  
only, sending continuous zeros.  
Resynchon-  
izing down  
The U-interface is not synchronous,  
S-interface sends INFO2 {or SCZ}, see remark 1 below  
Activation  
Request down  
MTC-20172 S-interface forced to INFO2 transmission,  
receiver indicates the S-bus reaction  
Activat. req  
with S-loop  
INFO2 transmission on the S-bus  
test loop2 switched (transparent loop)  
Activation  
Indication  
INFO4 transmission, normally only after  
AIu indication is received  
AIL  
Activ. Indic.  
with S-loop  
INFO4 transmission  
test loop2 switched (transparent loop)  
did=  
DC  
Deactivate  
Confirmation  
Deactivation confirmation, entering the  
power down state, INFO0 sent, critical  
timing to halt the clocks.  
Rem a rk 1 : When the U-interface is  
resynchronizing, the S-interface will  
send INFO2.  
Rem a rk 2 : During loops, the S-inter-  
face simply ignores the incoming  
INFO3 from the S-bus. The receiver syn-  
chronizes on looped INFO2/ 4.  
21  
MTC-2 0 2 7 7 IN TT  
In d ica tio n s (Up stre a m ) in N T Mo d e  
Ta b le 1 7  
0000  
TIM  
Timing  
The S-interface requires GCI clocks.  
Request  
0100  
RSYu  
Resynchron-  
izing  
The S-bus receiver tries to synchronize  
0101  
0110  
---------  
ei  
---------  
---------  
Error  
RSTB and SCZ- pin both low simultaneously  
Indication  
Activation  
Request up  
1000  
1100  
1111  
ARu  
AIu  
DIu  
INFO1 received (actually any AMI signal)  
Activation  
Indication up  
Receiver synchronized on INFO2/ 3/ 4  
(INFO3 normally, INFO2/ 4 in loop)  
Deactivation  
Indication  
Timer (32 ms) expired, or INFO0 received  
(16 ms) after DR (deactiv. request)  
Th e S-In te rfa ce Functiona l Overview  
For transmission of data over the sub-  
scriber premises, the S-interface pro-  
vides the S0-interface. This interface  
enables full duplex transmission of data  
(2B + 1 D-channel) over 4 wires at a  
nominal data rate of 192 kBits/ s. An  
Alternating Mark Invert (AMI) code is  
used for the line transmission. The trans-  
mission of data over the S0-interface  
consists of frames of 250 µs. Each  
frame is 48 bits wide, and contains 4  
data bytes (2 B1, 2 B2) and 4 D-bits.  
The frame structures are shown in  
fig.20.  
The first bit of the transmitted frame from  
TE to NT is delayed for 2 bit periods  
with respect to the frame received from  
the NT. Furthermore, an echo bit (E-bit)  
A frame start is marked using a first  
code violation (no mark inversion).  
To allow secure synchronization of the  
receiver, a second code violation is gen- for the D-channel and an activation bit  
erated before the 14th bit of the frame.  
To guarantee this second violation, an  
auxiliary framing bit pair FA and N  
(from NT to TE) or the framing bit FA  
with associated balance bit (from TE to  
NT) are introduced.  
(A-bit) are provided, where DC-balanc-  
ing is done by means of the L-bits.  
22  
MTC-2 0 2 7 7 IN TT  
Ge n e ra l De scrip tio n o f th e S-b u s In te rfa ce  
The S-interface can be used on the S-bus The S-interface contains all circuit parts  
- NT receiver bus type is selectable:  
configured as a point-to-point connec-  
tion or as a passive bus. The bus con-  
nection can handle up to 8 terminals. It  
is either a short bus with the terminals  
dispersed over a length of 200m, or  
an extended bus with a cluster of termi-  
nals within a 25 m range.  
necessary for the adaption of the S-inter- short bus with fixed timing, or adap-  
face, especially transmitter and receiver  
stages.  
tive timing for extended bus or point to  
point.  
- S-bus outputs are balanced, allow  
ing bus operation;  
- S-bus inputs are balanced;  
The S-bus tranceiver stages must be con-  
nected to the bus via external interface  
circuitry (2:1 transformer) and protec-  
tion. When the S-interface is in unpow-  
ered state (supply voltage = 0 V) the S-  
bus transmitter is high ohmic (see CCITT  
I.430).  
The chip handles full-duplex transmission - Out-of-band noise is filtered;  
of two B-channels (64 kbit/ s each) and  
one D-channel (16 kbit/ s). It handles  
also the echo E-channel, the multifram-  
ing S and Q bits, ...  
- RX has AGC and an adaptive  
threshold, and corrects long-line  
distortion by optimizing the sample  
moment.  
B2  
D
L.  
F
L.  
B1  
E
D
A
FA  
N
NT to TE  
B2  
E
D
M
B1  
E
D
S
E
D
L.  
F
L.  
2 BITS OFFSET  
D
L.  
F
L.  
B1  
L.  
D
L.  
FA  
L
B2  
TE to NT  
L.  
D
L.  
B1  
L.  
D
L.  
B2  
L.  
D
L.  
F
L.  
F : FRAMING BIT  
N : = FA  
L : DC BALANCING BIT  
D : D-CHANNEL BIT  
E : D-CHANNEL ECHO-BIT  
B1 : BIT OF CHANNEL B1  
B2 : BIT OF CHANNEL B2  
A : ACTIVATION BIT  
S : S-BIT  
FA : AUXILIARY FRAMING BIT  
M : MULTIFRAMING BIT  
Fig . 2 0 : So-Fra m e Form a t  
23  
MTC-2 0 2 7 7 IN TT  
The S -interface can be used in a point-  
to-point and in a point to multipoint con-  
figuration (including extended passive  
bus). In the first configuration, the length  
of the cable is limited to aprox. 1.2 km  
(see fig.21).  
Controlled access to the shared data  
channels is realized within the S-inter-  
face by a D-channel access procedure.  
Each terminal can be given a certain  
priority for D access. Via the echo bit,  
which is the reflection of the received D  
channel at the NT, it is possible for the  
terminal to detect the status of the D-  
channel. In order to try to gain access  
over the D-channel, a terminal has to  
see 8 to 11 consecutive ones in the  
echo-channel. The exact number  
depends on the priority given to the ter-  
minal. When several terminals try to  
gain access at the same time, collisions  
occur on the S-bus. The terminal that  
transmitted "one" but sees a “zero” in  
the echo channel detects the collision  
and loses the D-channel access.  
The terminal that transmitted the "zero"  
gains the access. When a successful D-  
channel message is transmitted, the pri-  
ority is decreased by 1 in order to guar-  
antee fairness with the other terminals.  
The status of the D-channel of the TE/ LTT  
is at the 5th bit position of the monitor  
byte. This enables the control of the D-  
channel by an external HDLC controller.  
In the bus configuration (point to multi-  
point), up to 8 terminals may be con-  
nected to the S0-interface (fig.22)  
The terminals must be connected in a  
range of 150 m. For the extended pas-  
sive bus, the terminals must be clustered  
within a 25m range with a maximum  
cable length of about 1 km.  
To avoid bus mismatching when multi-  
ple TEs are connected, the driver stages  
present a high impedance when they  
are not powered.  
<= 1.2 Km  
NT/ INT  
TE/ LTT  
GCI  
GCI  
T
T
R
S i/ f  
S i/ f  
R
Fig . 2 1 : Point to Point Config ura tion  
<150 m  
NT/ INT  
T
R
GCI  
T
R
S i/ f  
MAX 8  
S i/ f  
S i/ f  
T
R
TERMINATING RESISTO  
of 100 Ω  
TE # 8  
TE # 1  
Fig . 2 2 : Point to Multip oint Config ura tion  
24  
MTC-2 0 2 7 7 IN TT  
Te st Mo d e s Su m m a ry  
S-In te rfa ce  
Ge n e ra l O ve rvie w  
Test loops may be closed in the S-inter-  
face, where all three channels (B1, B2  
and D) are looped back as close as  
possible to the So-interface.  
The block diagram of the S-interface is  
shown in fig.23.  
The B and D data are stored in the  
buffer and multiplexed together with  
M, C/ I, MX and MR into a digital V*  
GCI frame. The pointer structure of the  
buffer guarantees a minimum round-  
trip delay. If the clock wander  
becomes too big, a warning is given  
in the C/ I channel, and the internal  
pointers are reinitialized.  
Data from the So-interface is received  
by the S-interface receiver, which has  
a balanced input, an AGC stage, a fil-  
ter and comparators with dynamically  
adapted thresholds. The timing of the  
received S0-frame is fixed (Only NT).  
Loop 2 is a transparent loop where the  
transmitted So-frame is also switched  
on the S-bus. Activation from the So-  
interface is not possible.  
Both loops are initiated over the C/ I-  
channel and under control of a layer 2  
component.  
In the fixed timing case, the timing is  
locked to the transmitted frame, and  
the tolerable phase delay on the  
received So-frame is limited. In adap-  
tive timing mode, delays up to 48 µs  
can be tolerated. The start of the  
received frame is detected in the FL-  
detection unit. An adaptive algorithm  
is used for compensation of the slope  
of the FL transition. A digital PLL recov-  
ers the received bit clock (192 kHz).  
Activation/ deactivation procedures  
are handled in the status controller.  
Two basic modes are available:  
A V* mode, compatible with the U-  
interface block, and a GCI compatible  
mode. The S-interface automatically  
selects the connect mode.  
For further testing of the subscriber line,  
two test signals can be transmitted over  
the So-interface: A 96 kHz test  
sequence sending continuous AMI  
marks, and a 2 kHz test sequence  
sending single AMI marks. Both test  
modes are under control of the C/ I  
channel, as well as TSP pin.  
The S/ Q control module handles the  
multiframing on the S and the Q chan-  
nel of the So-interface. This function is  
disabled in the INT.  
A second digital PLL generates the  
transmit bit clock (192 kHz), which is  
locked to the GCI frame. It is possible  
to compensate external circuits (e.g.  
filters) by adjusting the internal phase  
of the bit clocks by means of a register  
accessible by the monitor channel.  
In order to reduce the power consump-  
tion of the components connected to  
the subscriber line, the S-interface  
are switched to a power down mode  
during idle periods.  
These circuits work with a 7680 kHz  
±100 ppm clock. This clock is internal-  
ly delivered to the S-interface by the U-  
interface block.  
Analog  
transmitter  
S, Q  
B, D  
SX  
P
s_transmitter  
DPLL  
S/ Q control  
M control  
SX  
N
The serial B and D data from the V*  
GCI digital-interface is stored into a  
buffer with a dynamic pointer struc-  
ture, and is presented to the S_trans-  
mitter where the So-frame formatting is  
done. In the other direction, the  
S_receiver unit disassembles the  
received So-frame.  
B, D  
B, D  
FL detection  
buffer  
DIN  
DOUT  
DFR  
V*/ GCI  
MUX  
Analog  
receiver  
DCLK  
SR  
P
SR  
N
B, D  
S, Q  
status  
controller  
C/ I  
s_receiver  
activity  
detector  
7680 kHz  
oscillator  
asynchronous  
power up/ down  
CHP boundary  
XTI  
XTLO  
Fig . 2 3 : Block Dia g ra m of the S-interfa ce  
25  
MTC-2 0 2 7 7 IN TT  
GCI Clock Synchroniza tion in  
the ISDN Environm ent for the  
Up strea m S-Interfa ce (NT)  
Conclusion: the S-interface block has 3  
different clocks, which are locked in fre-  
quency, but with unknown phase rela-  
tion. Because the clocks are derived via  
DPLL blocks the phase relation is not  
constant, but has some jitter and wan-  
der.  
Activa tio n o f th e  
S-In te rfa ce in N T m o d e  
Activation through the S-bus will be seen  
by the signal detector. The S-interface  
does not need a GCI clock to activate  
the GCI interface, which it does by  
asynchronously pulling the data line  
low. The master on the bus answers  
with GCI and frame, followed by com-  
mands via the C/ I channel. The bus  
master also delivers the 7.68 MHz fre-  
quency simultaneously with GCI activa-  
tion.  
In general the downstream devices are  
slaved to the upstream devices.  
The S-interface is master of the S-bus,  
and can sample the received (upstream)  
S-bus frames with a receive clock at  
exactly the transmit frequency, but with  
an unknown phase.  
Clo ck Sp e e d  
The master clock runs at 7680 kHz +/ -  
100 PPM.  
The S-interface receives the GCI timing,  
and must derive the 192 kHz S-bus bit-  
clock from it. As the GCI timing is not  
necessarily a multiple of 192 kHz, the  
S-interface generates a 192 kHz TX and  
RX clock from a clock input at 7680  
kHz +/ - 100 ppm. The 192 kHz is not  
a pure divide by 40 of the X-tal, but is  
locked to the 8 kHz frame signal of the  
GCI-interface. This is a DPLL action  
Internally the S-bus transceiver part runs  
at 192 kHz, derived from the master  
clock, but locked to the ISDN network  
clock with a phase locked loop, adjust-  
ing one 7.68 MHz period every 250  
us. The ISDN network clock is sent  
downstream via the S-bus or the GCI  
interface.  
Activation through the GCI bus consists  
of clock and frame delivery, followed  
by commands via the C/ I channel. The  
S-interface will activate the S-bus trans-  
ceiver according to the commands,  
including the internal clock distribution.  
If the master clock must be delivered to  
S-interface. Note that the internal clock  
distribution to the S-tranceiver section is  
delayed for 2 ms (using the GCI frame-  
clock).  
The GCI part runs at the clockspeed of  
its interface, which is 512 kHz in NT  
mode.  
where the 192 kHz clock period can be  
adjusted 1/ 40 of the 192 kHz clock  
period every 250 us. Note that jitter on  
the 192 kbit S-bus signals is a combina- Pow er Sa ving / Dea ctiv-  
tion of the jitter on the 7680 kHz before  
the DPLL and the effects of the DPLL lock-  
ing to the GCI 8 kHz frame.  
a tion of the S-Interfa ce  
The S-interface is controlled via the GCI  
interface. This interface is designed to  
be shut down and consequently reacti-  
vated. Shutting the bus down is com-  
manded by the controller on the bus.  
Once the command is acknowledged,  
there exists a fixed procedure to halt the  
clock (by the controller in NT). Reacti-  
vating the bus can be done by the S-  
interface or the controller.  
The S-bus RX clock in fixed timing (short  
passive bus) is derived from the same  
clock input with the same frequency cor-  
rection as the transmit clock, but with a  
phase offset. The corrections of 1/ 40 of  
a bit period are used in open loop here.  
The S-bus RX clock in adaptive timing  
(extended bus, point to point) is also  
derived from the same master clock.  
However, the receiver must optimize the  
symbol sampling moment. This is an  
extra phase correction, which tracks  
wander and jitter of the received data.  
The receiver tracks the RX data by lock-  
ing on the F/ L transitions.  
When the GCI bus is going to be shut  
down, the S-bus transceiver is put to idle  
also. The S-bus transceiver enables an  
asynchronous signal detector, which  
can reactivate the S-interface on receipt  
of INFO via the S-bus. Then the S-inter-  
face shuts down the internal 7.68 MHz  
clock distribution. If the clock is external-  
ly provided it can be put to idle also,  
after the GCI bus has become idle.  
The S-interface can receive activation  
via the S-bus during the process of shut-  
ting down via the GCI bus.  
Note: The timing stays identical for an  
internal loop from TX to RX, because  
then the S-interface uses adaptive RX  
timing as well. Even an external S-bus  
loop can be applied, provided that the  
receiver does NOT work with fixed RX  
timing.  
26  
MTC-2 0 2 7 7 IN TT  
De ta ile d O p e ra tio n a l De scrip tio n o f th e  
S-b u s In te rfa ce  
In tro d u ctio n  
Inside the frame more balance bits are  
present serving two purposes:  
next violation will be the F flag itself, at  
a distance much larger than13 bit posi-  
tions. This distance rule allows for fast  
and reliable frame flag detection.  
In this section, external and internal  
operational details of the S-bus interface  
are given. Detailed interface timing and  
electrical specifications are given in  
related documents.  
1) In both directions they guarantee that  
the polarity of the first bit or F-bit is con-  
stant. They also increase the mark densi-  
ty on the link.  
Fra m e Synchroniza tion  
Multifra m ing Ex cep tions  
2) Moreover, in uplink direction the bits  
in the frame can be generated by differ-  
ent terminals. Therefore, the frame is  
subdivided in groups of bits, each sent  
by a single terminal and terminated also  
with a balance bit. The first binary ’0’ of  
each group of bits except for the fram-  
ing signal is coded as a negative pulse.  
The balance L-bit finishes those group  
with a positive mark if needed, to avoid  
violations of the mark inversion scheme.  
This allows the different B and D chan-  
nel bits to be sent by different transmit-  
ters on a bus, because the AMI polarity  
is always fixed. Thus no AMI violation  
can be caused by the multipoint nature  
of the bus.  
Ge n e ra l Ch a ra cte ristics  
AMI violation delay in multiframing:  
At the TE/ LT-T position the received FA  
bit is occasionally a binary 1 in case  
of multiframing. However, then the N  
bit at position 15 is a binary one,  
because it is the binary inverse of the  
FA. This guarantees a second violation  
within 14 positions after the F-bit.  
The S-interface realizes full-duplex trans-  
mission of two B-channels (64 kbit/ s  
each) and one D-channel (16 kbit/ s).  
Additionally the S-interface allows con-  
trolled access to the common D-channel  
and the activation/ deactivation of each  
connected device.  
AMI violation exception in multiframing:  
At the NT/ LT-S position the received FA  
bit is occasionally a binary 1 in case of  
multiframing. FA is followed by a bal-  
ance bit L, which is then also at binary  
1. If all B and D bits between F-L and  
FA-L are also at binary 1, then there is  
no second violation within the 14 posi-  
tions. If the remaining bits (B and D  
channels) are also at 1 in the remain-  
der of the 48 bit frame, then the second  
violation will be absent and next F-bit  
will be no violation! This can delay the  
synchronization and could trigger an  
invalid loss of synchronization.  
The delayed synchronization during  
multiframing is unavoidable. To avoid  
an invalid loss of sync at the NT/ LT-S  
when multiframing is on, all incorrect  
second violations (too late or missing) in  
uplink direction are ignored if the FA bit  
was a binary 1 in the corresponding 48  
bit frame in downlink direction. Missing  
violation at the F-bit position are  
Tra n sm issio n Ra te  
The nominal transmission rate is 192  
kbit/ s in each direction. There is no  
requirement for special bit sequences in  
the B-channels.  
AMI Vio la tio n s fo r  
Fra m e Sy n ch ro n iza tio n  
Fra m e Stru ctu re  
Data is transmitted within a frame of 48  
bits in each direction. The nominal  
frame period is 250 us which gives a  
frequency of 4 kHz. The frame structure  
is not depending on ’bus’ or ’point-to-  
point’ configuration.  
For synchronization purposes the AMI is  
violated twice per frame. A 48 bit  
frame always starts with a positive pulse  
(F-bit) followed by a negative balance  
bit L. The F-bit is a violation, because  
the last mark of the previous frame is  
positive also. The first binary ’0’ follow-  
ing a framing signal (F, L) is always  
negative, and is a second violation.  
AMI S-b us Cod ing  
For both directions a pseudo-ternary  
coding (AMI) is used. A binary ’1’ (high  
level logic) is coded as ’no signal’  
whereas a binary ’0’ sequence is repre- Fra m e Sy n ch ro n iza tio n  
sented by alternating positive and nega- Dista n ce Ru le  
tive pulses.  
The polarity inversions, coupled with a  
minimal density of marks per frame,  
reduce the low frequency components  
of the signal. The 4 kHz frame always  
starts with a positive pulse (F-bit), fol-  
lowed by a negative balance bit L.  
Balance Bits  
There are two AMI violations in the  
frame: the F-bit at the beginning is at a  
fixed position. The second violation  
must follow the F-bit within 13 bit posi-  
tions, because the frame contains an FA  
(auxiliary flag) at position 14, which is  
a binary 0, even if all other bits (2 to  
13) are binary one. After the FA the  
ignored if the preceeding 48 bit frame  
(downlink) had the FA-bit at one.  
27  
MTC-2 0 2 7 7 IN TT  
Ta b le 1 8  
Sy n ch ro n iza tio n Prin cip le s -  
Ad a p tive Bit Tim in g  
Sig na ls from netw ork to term ina l Sig na ls from term ina l to netw ork  
1) The receiver first finds the AMI viola-  
INFO0  
No signal, open circuit  
INFO0  
No signal, open circuit  
tions by oversampling.  
2) Immediate bit-synchronization is  
given by the F-L transition.  
3) The distance rule of the next violation  
within 14 positions is used to validate  
the F-bit.  
INFO2  
Frame with all bits of  
INFO1  
Continuous signal with  
the following pattern:  
positive zero,  
B, D, and E-Echo channels,  
and A bit at binary zero,  
FA, M, S, N and L bits  
follow the coding rules  
negative ZERO, six ONEs  
4) Frame synchronization is acquired  
after 3 correct frames, with a correct F-  
bit violation and a second one within  
14 bit positions.  
5) The F-L transition determines the  
adaptive bit sampling.  
INFO4  
Frame with operational  
data on B, D, and E-Echo  
channels. Bit A set to  
INFO3  
Synchronized frames with  
operational data on B, D  
channels. FA and L bits  
according to normal coding  
binary ONE. FA, M, S, N, L  
bits follow to coding  
6) At NT/ LT-S loss of sync after two  
frames not having F violation or second  
violation following the distance rule (at  
14 bits), when no multiframing is active.  
The downlink signal stays active, but  
changes automatically from INFO4 to  
INFO2. In case of multiframing we  
ignore missing second violation within  
the 14 bit distance, or the missing viola-  
tion at the next F-bit for uplink frames  
with the corresponding downlink FA bit  
at binary 1.  
TEST1  
TEST2  
Send Single Zeros (SSZ),  
AMI marks, 250 us distance  
forced via pin (NT) or C/ I  
TEST1  
TEST2  
Send Single Zeros (SSZ),  
AMI marks, 250 us distance  
forced via pin (NT) or C/ I  
Send Continuous Zeros  
(SCZ), alternating marks,  
forced via pin (NT) or C/ I  
Send Continuous Zeros  
(SCZ), alternating marks  
forced via pin (NT) or C/ I  
Tra n sm itte d Fra m e s  
- N-bit coded as N = .NOT. FA (applies  
to INFO2 and INFO4);  
- M-bit at binary zero, except when mul-  
tiframing;  
- FA-bit, additional flag (bin. zero),  
except when multiframing.  
Depending on the activation state of the-  
interface the S-interface can transmit dif-  
ferent signals called INFO 0, 1, 2, 3,  
and 4. Moreover two testsignals are  
defined:  
Sy n ch ro n iza tio n Prin cip le s -  
Fix e d Bu s Tim in g  
On a short passive bus the position of  
the bit sampling can be fixed.  
The B-channel and D-channel are trans-  
parently transmitted on the S-bus. When  
idle those channels are all binary 1.  
Without multiframing active S, FA, M  
bits are binary zeros. Multiframing is  
allowed to be active during INFO2 and  
INFO4 and influences the S, FA, M bits.  
The points 3), 4) and 6) of the previous  
paragraph are executed. No oversam-  
pling is done, no DPLL action is needed  
to track the F-L adge.  
Note that the fixed timing is changed  
automatically to adaptive timing, when  
internal S-bus loops are commanded.  
When external S-bus loops are used  
(e.g. for production test) only adaptive  
timing is suitable!  
De ta ils o n Do w n lin k Fra m e s  
The downlink frames transmitted by  
upstream devices contain an E-bit. Dur-  
ing INFO4 the E-bit is the echoed D-  
channel-bit received from the down-  
stream devices. This D-echo-channel is  
used for D-channel access procedure.  
De ta ils o n Up lin k Fra m e s  
The INFO3 frame transmitted at termi-  
nal-side consists of several groups of  
bits, each of them DC-balanced by an  
adjacent symmetry bit L.  
The uplink D-channel requires an access  
protocol. Downlink multiframing influ-  
ences the FA-bit in uplink (Q-channel):  
If the S-interface receives the FA-bit as  
binary 0 (electrical mark) it will always  
answer with binary 0.  
Pu lse Po la rity in th e S-b u s  
Fra m e  
The receiver is polarity independent.  
The transmitter in NT mode has no  
polarity requirements.  
Two L-bits are used for DC-balancing,  
after the F-bit and the last bit the frame.  
In downlink direction some special bits  
are used:  
- A-bit used for activation (A=1 for  
INFO4, A=0 for INFO2);  
If the S-interface sees the FA-bit as bina-  
ry 1 it answers with binary 1, when mul-  
tiframing is not active.  
- S-bit coded as binary zero, if no multi-  
framing active;  
28  
MTC-2 0 2 7 7 IN TT  
S-b u s Tra n sm itte r Tim -  
in g a n d Fra m in g  
ver delays. The total delay of the exter-  
nal devices was estimated at 100 ns,  
the internal delay is implementation  
related. Moreover, the sampling can be  
delayed extra by 5 periods of the 7.68  
MHz clock via the XTR4 pin, and also  
via internal register programming.  
Vio la tio n Va lid a tio n  
During the hunt for frame synchroniza-  
tion the F/ L transition forces the RX bit  
sampling clock and bit counter in an  
deterministic state, which is optimal. The  
RX part now hunts for a next violation.  
In fact the next mark must be a viola-  
tion. This violation (polarity should be  
opposite, but this is ignored) must arrive  
before the counter indicates 14  
The transmitter data are sent at 192  
kHz. The 192 kHz are derived from the  
master frequency of 7.68 MHz, by divi-  
sion by 40. The transmitter framing is at  
4 kHz. The timing is slaved to the down-  
link clocks, the 4 kHz S-bus frame is  
locked in phase to the available down-  
link framing.  
The frame synchronization knows the F  
position, and applies the rules  
explained earlier (i.e. without over- sam-  
pling). The NT in fixed bus mode can  
be forced to loop the S-bus signals inter-  
nally! Then S-interface applies adaptive  
timing, to test a maximal functionality.  
received bits. If the second violation is  
found before 14 received bits, the F/ L  
must be validated for 2 more consecu-  
Tra n sm itte r Tim in g a n d  
Fra m in g a t th e N T  
With a DPLL the 192 kHz is locked to  
the GCI interface, by synchronizing the  
S-bus frame with the GCI frame. The  
DPLL locks the falling edge of the F/ L  
frame signal on the GCI frame signal.  
Jitter is according to the CCITT I.430  
spec.  
tive frames.  
In all following frames  
the F/ L transition is oversampled to lock  
the RX bit sampling clocks with DPLL  
movements of 1 period of 7.68 MHz. If  
the F/ L validation is not correct during  
the 2 subsequent frames, the S-interface  
restarts its hunt.  
Fra m e Sy n ch ro n iza tio n  
De ta ils in Ad a p tive Tim -  
in g  
During synchronization the device over-  
samples the incoming bits with a fixed  
threshold, which is at 33 % of the nomi-  
nal pulse height, with AGC active.  
RX Bit Sy n ch ro n iza tio n N T  
Ad a p tive Bu s  
S-b u s Re cie ve r Tim in g  
a n d Sy n ch ro n iza tio n  
Bit synchronization is done only by  
detection of the F-L zero crossing. This is  
optimal for short busses and extended  
busses, where multiple signal sources  
are present, each with an independent  
bit timing. Only the F/ L is a ”stable”  
combination of all electrical drivers on  
the bus. For long point to point links the  
same technique is used, although aver-  
aging of all zero crossings would be  
better, theoretically.  
RX Fra m e Sy n c a n d Bit Sa m -  
p lin g in N T Sh o rt Pa ssive  
Bu s Mo d e  
First Vio la tio n De te ctio n  
The bit-sampling moment is fixed, and  
coupled with the TX bit clock, which is  
derived from the master clock, and  
locked to the GCI frame. The RX bit  
counters (counting the position of the  
uplink bits in the frame) are also locked  
to the downlink/ TX bit counter. Uplink  
data are 2 counts late.  
The oversampling is done at the 7.68  
Mhz master clock, or at a factor 40. A  
simple voting technique is used to detect  
a violation: the detector output incre-  
ments a counter as long as the detected  
bits are marks of the same polarity or  
zeros. When a polarity change of the  
marks is seen, the counter is cleared.  
Whenever a sequence of more than  
50 oversampled marks of the same  
polarity are seen, the receiver decides  
that a violation came in. The number 50  
must not be too large, to allow synchro-  
nization on signals with flat edges.  
Each time the bit counters indicate the  
reception of F/ L, the RX part oversam-  
ples the transition at 7.68 MHz.  
The fixed bit sampling moment is  
advanced 5 periods of the 7.68 MHz  
clock, before the edges of the S-inter-  
face transmit data stream. This is need-  
ed to allow an advance of 7% or 3  
periods of the uplink data, allowed  
according to the CCITT to be sent by TE  
at zero distance, combined with a 1  
period jump of the downlink data clock  
derived from the master clock.  
The F/ L crossing is used for several pur-  
poses:  
1) It gives an immediate estimate of the  
RX data optimal sampling moment, after  
a first violation is found, via oversam-  
pling.  
2) It indicates how to correct the RX 192  
kHz sampling clock each frame by one  
7.68 MHz period (DPLL action in adap-  
tive RX sampling).  
After finding a single violation, the over-  
sampling looks for the mark-to-zero and  
the subsequent zero-to- opposite-mark  
transition which it uses to estimate the  
actual F/ L crossing; see next para-  
graph.  
This relationship is valid on the S-bus  
itself. Inside the S-interface the actual bit  
sampling must be delayed to account  
for the nominal delay of the external  
transformer, the internal filters and dri-  
The ”F-L zero crossing” is not detected.  
The S-interface detects the transition  
mark-zero (instant t1) and the subse-  
29  
MTC-2 0 2 7 7 IN TT  
quent zero-opposite-mark (instant t2).  
During the F/ L bits the device oversam-  
ples the incoming signal with a fixed  
threshold, which is ALWAYS at 33 % of  
the nominal pulse height.  
the data, the F/ L edge is used on each  
frame to validate the sampling moment.  
The oversampling clock is used in the  
F/ L window to validate the zero cross-  
ing.  
another 650 ns to the effect of the XTR4  
pin.  
Fra m e Rela tion Betw een  
GCI a nd S-Interfa ce  
In between t1 and t2 the RX part counts  
”Y”, the number of zeros, ignoring pos-  
sible marks. The zero count Y is less  
than the t2-t1, because noise could  
force marks to be seen by the receiver  
during the interval.  
At instant t2 (zero to opposite mark tran-  
sition) the state of the counter generat-  
ing the 192 kHz clock from the 7.68  
MHz is compared with the optimal  
value, which should be loaded for an  
immediate bit synchronization as  
If the S-interface is in the Network posi-  
tion, the 192 kHz S-bus bit clock is  
derived from the master clock, which is  
locked to the 8 kHz frame of the GCI  
bus.  
explained above. If the difference (in #  
of periods of 7.68 MHz) is -1, 0, or 1,  
the counter is not changed, to provide  
hysteresis. If the difference is larger, the  
counters are adjusted with only 1 1/ 40,  
to limit the DPLL reaction.  
The leading edge of the F-bit starts the  
frame on the S-bus. The DPLL forces this  
F-bit edge in a fixed range relative to  
the frame signal of the GCI bus.  
The F-bit start is situated in a 520 ns  
zone starting with the edge beween  
bit0 and bit1 on the GCI bus. The  
uncertainty is caused by the DPLL  
actions which will correct the 192 kHz  
S-bus clock in steps of 130 ns, i.e. one  
7.68 MHz period.  
This phase relation optimizes the total  
roundtrip delay on the S-bus for each B-  
channel, if the GCI clock is 512 kHz.  
The delay of the NT with S-bus looped  
is only 125 us for both B-channels at the  
GCI side.  
The number ”Y” of intermediate zeros is  
used to estimate the slope of the arriving  
signal, to predict the edge of the F/ L  
transition. Y is limited to 15, which cor-  
responds to a first order time constant of  
2 us for the S-bus data, filtered by the S-  
interface input filter. This is 2.5 times  
slower than the worst case point to point  
signal as specified in CCITT I.430.  
In this manner the sampling moment is  
adjusted with one 7.68 MHz period,  
every 250 us. At the TE this allows a  
maximal frequency error of the X-tal of  
500 PPM.  
Note that Y could be larger than 15 if  
the zero crossing is sought on a mark  
which is followed by a zero bit, i.e.  
when the violation is not the F bit fol-  
lowed by L.  
Tim in g Re la tio n  
Be tw e e n RX a n d TX o n  
th e S-b u s in N T Mo d e  
Im m e d ia te Bit Sy n ch ro n i-  
za tio n a t In sta n t t2  
When the receiver is not synchronized  
the receiver is oversampling and hunts  
for violations.  
The delay between transmitted and  
received frames at NT is 2 bits plus the  
roundtrip delay across the S-interface,  
in normal operation. Worst case delay  
between downlink frames and uplink  
frames is 42 us (see CCITT) or 8 bits.  
Longer delays cause problems to cor-  
rectly send the E-channel bits. In loop-  
back mode, the delay is zero.  
E-Ch a n n e l Ge n e ra tio n  
At the NT site the S-interfaceA mirrors the  
uplink D-bits in the downlink E-channel.  
The purpose of the E-channel is to control  
the D-channel access from multiple TEs on  
the S-bus.  
In INFO2 the E-bits are zero, in INFO4  
the E-channel mirrors the preceding D-  
channel bit received in the S-bus receiver.  
The F/ L crossing is found at instant t2  
and the 192 kHz bit clock is preset to  
predict an optimal sampling moment.  
The data edge is estimated at instant  
( t2 - 2.00*Y ).  
The optimal sampling precedes the theo-  
retical edge by 8 periods of the 7.68  
MHz clock. The advance is needed to  
allow a jitter of +/ - 7% (15% or 6 peri-  
ods of 7.68 MHz) of the data, allowed  
according to the CCITT to be sent by  
any TE, combined with a 1 period DPLL  
correction needed at the NT to correct  
for its own X-tal.  
The receiver in NT is conceived to  
accept any delay, while in adaptive  
sampling mode. This is convenient when  
looping the S-bus signals. E-channel  
operation is only correct if the delay is 0  
to 8 bits.  
The delay trimming via XTR4 or X4 pin  
delays the sampling moment with 5  
periods of the 7.68 Mhz clock or 650  
ns in NT mode with fixed timing on  
short bus. In the adaptive timing mode  
no effect is seen.  
Mu ltifra m in g - S a n d Q  
Ch a n n e ls  
The S-interface block supports multi-  
framing according to I.430 but multi-  
framing is disabled on chip.  
Co n tin u o u s Bit Sy n ch ro n iza -  
tio n a t Ea ch F/ L Cro ssin g  
Once the receiver is synchronized on  
The delay trimming can also be con-  
trolled via the GCI M-channel adding  
30  
MTC-2 0 2 7 7 IN TT  
S-In te rfa ce Pro g ra m m in g  
M-Ch a n n e l Me ssa g e s a n d Re g iste rs  
In the INTQ, the S-interface block can  
operate in its normal mode, or can be  
selected to operate in a reduced func-  
tion mode compatible with earlier  
devices.  
Ge n e ra l Co n te n t o f  
M-Ch a n n e l Me ssa g e s  
M-Ch a n n e l O p e ra tio n s  
In the S-interface block, the M-channel  
messages are limited to double bytes.  
The first nybble of the message is a  
general address, defined in the GCI  
standards. In the S-interface this  
address nibble is limited to:  
M-Ch a n n e l Fo rm a t - Bit a n d  
By te N u m b e rin g Co n ve n tio n  
The M-channel is a byte oriented chan-  
nel. Bytes (also called octets) are trans-  
mitted in ascending numerical order.  
In tro d u ctio n  
In the S-interface block, the M-Channel  
is used for the transfer of operation and  
maintenance information:  
0001b, used to access S and Q chan- Within a byte the most significant bit is  
nel bits;  
transmitted first. The four most significant  
bits of the first message byte represent  
a general address, discussed under 7.3.  
1000b, used to read or write internal  
registers.  
1) The TRANSFER of system related reg-  
isters (S and Q channel of multitram-  
ing);  
All other values are ignored.  
By te Tra n sfe r Pro ce d u re  
2) The WRITE and READ operations of  
internal registers;  
S a n d Q Ch a n n e l Me ssa g e s  
This feature is disabled on the INTQ.  
To transfer a message composed of sub-  
sequent bytes on the GCI M-channel  
each byte is presented by the transmitter  
and acknowledged by the receiver. For  
that purpose the two M-channels (to and  
from the S-interface) have separate  
handshake bits, the MR and MX bits in  
the B1*-channel. The MX bit signals the  
presence of new information in the M-  
byte, the MR bit signals the reading of  
the information by the receiver.  
- Test and identification registers;  
- Mode registers, overriding the  
default state, changing the modes  
without having to change straps;  
- Control registers to change auxil-  
liary inputs and outputs;  
In te rn a l Re g iste r M-Ch a n n e l  
Me ssa g e s  
All internal register operations on the  
M-channel are double byte messages.  
Both READ and WRITE operations are  
possible. After every operation, the  
M-channel must go idle again.  
- Status registers, e.g. alarm and  
error monitoring;  
3) The transfer of the BUSY indication  
for the D-channel access, present in  
all modes.  
Concatenation of double byte messa-  
ges could result in errors. Messages  
In the reduced mode, the use of the  
M-channel is not necessary. Howev-  
er, it is available to access the multi-  
frame S and Q bits, and to access  
some internal registers with added  
features.  
which are aborted are ignored. The S- Id le M-Ch a n n e l  
interface block debounces the different The procedure starts from idle, where  
bytes of the message.  
MX and MR are both inactive at 1. The  
M-channel content during idle is invalid  
and should be at FFh. However, the idle  
value received by the S-interface is  
ignored.  
A WRITE operation is a one way mes-  
sage, acknowledged only via the MR  
bit. However, every register can be  
read. A READ operation results in an  
answer, delivering the CONTENT.  
The READ operation causes the two  
directions of the M-channel to be  
logically dependent! After the READ  
M-Ch a n n e l Re ce ive r a n d  
Tra n sm itte r  
In the S-interface the M-channel tran-  
Sta rt o f Me ssa g e (SO M) a n d  
First By te Tra n sfe r  
ceiver works half-duplex, with mes-  
sages lenght 2 bytes, with the M-chan- message to the S-interface block the in- From the idle state a start of message  
nel going to idle after every message,  
to allow a change of direction in the S- The M-transceiver in the S-  
interface M-transceiver.  
coming M-channel must return to IDLE.  
transmission is initiated by the sender  
with the transition of the MX-bit from  
inactive to the active state. The data to  
be transmitted are passed in the M-byte  
starting in the same frame as the MX-bit  
activation. In normal operation the first  
byte must be kept constant in the M-  
channel until the SOM is acknowledged  
by the receiver.  
interface block gives priority to the  
delivery of the CONTENT and/ or  
S/ Q messages, before it can handle  
the next incoming READ/ WRITE or  
S/ Q message.  
31  
MTC-2 0 2 7 7 IN TT  
In the next frame the MR bit must go  
back to active.  
Ack n o w le d g e o f th e SO M  
a n d First By te  
interface aborts a message only when it  
is forced in hard reset.  
On detection of the SOM the receiver  
will read the M-byte. It will acknowledge  
reception, provided that identical data  
were seen in the M-channel during two  
consecutive frames. To acknowledge  
SOM and the first byte, the MR bit goes  
from inactive to the active state, remain-  
ing there, until:  
En d o f Me ssa g e (EO M)  
Once the sender has received the  
acknowledge of the last byte, it changes  
the content to FFh, moves the MX to  
inactive and keeps it inactive for at least  
two frames.  
Ack n o w le d g e Ab o rt  
The sender acknowledges the abort  
request by entering the idle state.  
Reset of the M-Cha nnel  
Tra n sce ive r  
Ack n o w le d g e o f EO M  
1) a next byte is transferred, with MX  
indication, see next paragraph;  
2) an EOM is signalled by the transmit-  
ter;  
3) the receiver wants to abort the mes-  
sage.  
After the EOM of the sender, the receiv-  
er acknowledges the EOM by putting  
MR bit in the inactive state for at least  
two frames, keeping it there until the  
transmitter goes active again.  
At reset, the M-channel transceiver is  
forced to the idle state.  
All message bytes are put to idle, the  
MX and MR bits are forced to 1,  
aborting any ongoing message.  
Se n d e r N o t Re a d y  
Fu rth e r By te Tra n sfe rs  
If the sender is not ready (second byte  
or subsequent) the MX bit will be kept in  
the active state and the channel byte  
stays constant.  
In the case of the second byte transfer,  
the sender must detect the transition of  
the MR bit of the receiver from inactive  
to the active state (negative edge 1 to  
0), before transmitting the second byte,  
see previous paragraph. The sender  
indicates a new byte of information by  
the transition of the MX bit from active to  
inactive, for exactly one frame. The data  
is valid in the same frame. The next  
frame the MX bit goes from inactive to  
active, and the valid data are repeated.  
The data are thus repeated for minimally  
two frames. The sender repeats the data  
in all subsequent frames until the receiv-  
er returns the MR bit inactive, to  
Re ce ive r N o t Re a d y  
If the receiver is not ready for the first  
byte it keeps the MR in the inactive  
state. If the receiver is not ready for the  
second byte, it refuses to acknowledge  
the bytes by keeping MR in the active  
state.  
IDLE Fo rce d Fro m Se n d e r  
If the first byte is never acknowledged,  
i.e. MR staying at 1, the sender can  
force the M-channel and MX to IDLE.  
If the reception of a subsequent byte is  
not (or not yet) acknowledged (MR is  
staying active at 0) by the receiver, the  
sender can put the M-channel and MX  
to IDLE. The receiver should return MR to  
inactive. The last byte or even the com-  
plete message are never really acknowl-  
edged by the receiver.  
acknowledge the data (see next para-  
graph), or to abort the message.  
Fu rth e r By te Ack n o w le d g e -  
m e n t  
Each subsequent byte (signaled by MX  
going high for one frame, see previous  
paragraph) is acknowledged by the  
receiver once it has seen two consecu-  
tive identical bytes in the M-channel. It  
acknowledges it by putting the MR  
inactive (at 1) for exactly one frame.  
Ab o rt Re q u e st Fro m Re ce ive r  
The receiver can abort a message after  
the SOM acknowledge or any subse-  
quent byte acknowledge by forcing MR  
inactive for at least two frames. The S-  
32  
MTC-2 0 2 7 7 IN TT  
Write Op era tion  
For a Write operation, the double byte messages is as follows:  
Ta b le 1 9  
To S i/ f  
block  
byte 1:  
byte 2:  
1
0
0
0
X
ADR2  
ADR1  
ADRO  
CONTENT (MSB first to LSB last)  
There is no outgoing message in reac-  
tion to the WRITE.  
The second nibble is address of the  
internal register, limited from 1 to 6 in  
the S-interface block. The write  
addresses must differ from 0000, oth-  
erwise the READ operation is  
assumed.  
Rea d Op era tion a nd Content  
For a READ operation, the double byte messages is as follows:  
Ta b le 2 0  
To S i/ f  
block  
byte 1:  
byte 2:  
1
X
0
X
0
X
0
X
0
X
0
0
0
ADR2  
ADR1  
ADRO  
The second nibble is all zero for an  
internal READ operation. The fourth  
nibble is the address of the register,  
The answer is the CONTENT message, two bytes as follows:  
From S i/ f byte 1:  
block byte 2:  
1
0
0
0
BUSY  
ADR2  
ADR1  
ADRO  
CONTENT (MSB first to LSB last)  
The second nibble is the address of  
the internal register. The second  
ter. The BUSY kit, when set, indicates  
that the D Channel is in use.  
byte contains the content of the regis-  
De ta ile d Bitm a p o f th e In te rn a l Re g iste rs  
Ta b le 2 1  
Ad d ress na m e  
sent first  
Bits  
0
sent la st Access  
0h  
1h  
2h  
3h  
ID  
VN  
0
0
1
0
1
0
BUSY  
BUSY  
BUSY  
BUSY  
0
0
0
read  
read  
0
X
X
X
CONF  
OUT  
BT1/ SC  
BTO  
DEX1  
DEXO  
MFE  
TEST  
LTS/ T  
DELT  
rd/ wr  
rd/ wr  
AUX4b  
1
AUX4b  
0
AUX3b  
1
AUX3b  
0
AUX1 b AUX1 b  
1
0
4h  
5h  
6h  
7h  
IN1  
IN2  
AUX4  
(TEST)  
AUX3  
SCLK  
-
AUX1  
XTR3  
BUSY  
BUSY  
BUSY  
MOD2  
XTR2  
SLIP  
MOD1  
XTR1  
MFR  
MOD0  
XTR0  
BER  
read  
read  
XTR4  
PERF  
TEST  
S1/ Qb1 S1/ Qb2 S1/ QB3 S1/ Qb4  
read  
device test only; not used in normal operation  
rd/ wr  
33  
MTC-2 0 2 7 7 IN TT  
Id entifica tion Reg ister Rea d Only Ad d ress 0 h  
Ta b le 2 2  
ID  
0
1
1
0
BUSY  
BUSY  
0
0
0
Version Num b er Reg ister Rea d a nd W rite Ad d ress 1 h  
VN  
0
0
0
0
X
X
X
The version number of the device starts at 00h.  
Config ura tion Reg ister Rea d a nd W rite Ad d ress 2 h  
Ta b le 2 4  
CONF  
reset  
BT1/ SC  
0
BT0  
0
DEX1  
0
DEX0  
0
BUSY  
0
MFE  
0
RES  
0
DELT  
0
BT1/ SC BT0  
bus type selection  
bus type according to BUS pin; value at reset;  
bus type = Adaptive; BUS pin ignored, pin usable as l/ O;  
bus type = Fixed; BUS pin ignored.  
0
1
1
X
0
1
DEX1  
DEX0  
X
0
Common Echo Bus mode selection  
No operation.  
DE/ CEB bus not active.  
0
1
1
1
DE/ CEB bus driven and sensed.  
BUSY  
MFE  
READ only bit. Must be writen at 0, writing BUSY at 1 triggers testmodes.  
Multiframing enable if 1; Reset value is 0. Always write as 0.  
Multiframing is disabled in the MTC-20276.  
RES  
DELT  
Not used in this configuration. Always write 0. (Reserved)  
Delay triming: compensate 650 ns on the fixed bus sampling in the NT,  
transceiver roundtrip. Setting this bit increases the delay to 1300ns.  
Outp ut Reg ister Rea d a nd W rite Ad d ress 3 h  
Ta b le 2 5  
OUT  
reset  
RES4b1  
0
RES4b0  
0
RES3b1  
0
RES3b0  
0
BUSY  
0
TEST  
0
RES1 b1  
0
RES1 b0  
0
Note: The RES(i) pins are reserved and cannot be used in this configuration.  
BUSY Read only bit. Must be written 0, writing BUSY 1 triggers test modes.  
TEST Must be written 0, writing TEST 1 triggers test modes.  
34  
MTC-2 0 2 7 7 IN TT  
IN1 a nd IN2 Reg isters Rea d Only Ad d resses 4 h a nd 5 h  
Ta b le 2 6  
IN1  
AUX4  
x
1
1
AUX3  
x
AUX1  
1
BUSY  
BUSY  
MOD2  
1
MOD1  
reduced  
mode select  
MODO  
1
Reads  
IN2  
Reads  
(TEST)  
SCLK  
1
XTR4  
DELT  
XTR3  
S-bus mode  
BUSY  
BUSY  
XTR2  
TSP  
XTR1  
0
XTR0  
0
The bits represent the binary level of the  
input pin. All values are sampled asyn-  
chronously at the moment the content  
message is assembled. The BUSY bit is  
also present here.  
Perform a nce Reg ister Rea d Only Ad d ress 6 h  
Ta b le 2 7  
PERF  
RES  
RES  
RES  
RES  
BUSY  
RES  
MFR  
BER  
The RES bits are reserved and cannot  
be used in this configuration.  
BER : Bit Error Rate. This indicate that  
the SIC blocks has seen excessive bit  
errors, indicating a link transmission  
problem.  
RES  
Always reads as 0  
Indicates Multiframing synchronization if at 1.  
Set each time the BER signal goes low, reset after being read.  
MFR  
BER  
M-Cha nnel op era tion m essa g es overview  
to the SIC b lock  
from the SIC b lock  
content m essa g e  
reg ister na m e  
rea d m esssa g e  
b yte 1  
w rite m essa g e  
b yte 2  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
b yte 1  
b yte 2  
b yte 1  
80h  
81h  
82h  
83h  
84h  
85h  
86h  
b yte 2  
content  
content  
content  
content  
content  
content  
content  
identification  
version number  
configuration  
output  
80h  
80h  
80h  
80h  
80h  
80h  
80h  
-
-
-
-
82h  
83h  
content  
content  
input1  
(test only)  
(test only)  
input2  
performance  
test  
-_  
-
(test only)  
(test only)  
(test only)  
S/ Q channel  
-
-
1Fh  
S/ Q  
1Fh  
S/ Q  
35  
MTC-2 0 2 7 7 IN TT  
Pa ck a g e Sp e cifica tio n  
De vice Bra n d in g  
ALCATEL 2840  
YYWW INTQ  
MTC 20277PC-T  
TNTC-MMM ARM  
LLLLLLLLL AA  
Device Ma rk ing -PC  
Ord er num b er MTC-2 0 2 7 7 PC-I or C  
ALCATEL 2840  
YYWW INTQ  
MTC 20277 PQ-T  
TNTC-MMM ARM  
LLLLLLLLL AA  
Device Ma rk ing -PQ  
Ord er num b er MTC-2 0 2 7 7 PQ-I or C  
36  
MTC-2 0 2 7 7 IN TT  
4 4 PQ FP a n d 4 4 PLCC Me ch a n ica l Sp e cifica tio n  
.656(16.66)  
.650(16.51)  
typ.010(0.25)  
.630(16.00)  
.590(14.99)  
.695(17.65)  
.685(17.40)  
.656(16.66)  
.650(16.51)  
.695(17.65)  
.685(17.40)  
.160(4.06)  
.145(3.68)  
.180(4.57)  
.165(4.19)  
min.020(0.51)  
.021(0.53)  
.013(0.33)  
Drawing revision: 11  
Date: 07-06-95  
.050 TYP  
.630(16.00)  
.590(14.99)  
44 LEAD PLCC  
DWG.NR.87-0024  
Production package  
General dimensions  
.529(13.45)  
.510(12.95)  
.398(10.10)  
.390(9.90)  
TYP.006(0.15)  
.041(1.03)  
.026(0.65)  
.018(0.45)  
.010(0.25)  
.529(13.45)  
.510(12.95)  
.398(10.10)  
.390(9.90)  
TYP .0315(0.80)  
0°- 10°  
0°- 10°  
Pin 1  
MAX .096(2.45)  
TYP .063(1.60)  
.087(2.20)  
.075(1.90)  
MIN .002(0.05)  
Drawing revision: 11  
Date: 07-06-95  
44 LEAD PQFP / DQFP  
DWG.NR.90-0010  
General dimensions  
All dimensions are in inches and parenthetically in millimeters. Inches dimensions are approximated.  
37  
MTC-2 0 2 7 7 IN TT  
38  
MTC-2 0 2 7 7 IN TT  
39  
MTC-2 0 2 7 7 IN TT  
Alcatel Microelectronics acknowledges the trademarks of all companies referred to in this document.  
This document contains information on a new product.  
Alcatel Microelectronics reserves the right to make  
changes in specifications at any time and without notice.  
The information furnished by Alcatel Microelectronics in this  
document is believed to be accurate and reliable.  
However, no responsibility is assumed by Alcatel Micro-  
electronics for its use, nor for any infringements of patents or  
other rights of third parties resulting from its use.  
No licence is granted under any patents or patent rights  
of Alcatel Microelectronics.  
Alca te l Micro e le ctro n ics  
info@mie.alcatel.be  
http:/ / www.alcatel.com/ telecom/ micro  
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VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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