MTC-20280PQ-C [AMI]
ISDN Controller, 1-Func, PQFP100, PLASTIC, QFP-100;
| 型号： | MTC-20280PQ-C |
| 厂家： | 
AMI SEMICONDUCTOR |
| 描述： | ISDN Controller, 1-Func, PQFP100, PLASTIC, QFP-100 电信 综合业务数字网 电信集成电路 |
| 文件： | 总65页 (文件大小：2174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Data Sheet
Preliminary Rev 2.0 November 1998
Ke y Fe a tu re s
Ke y Ap p lica tio n s
Ge n e ra l De scrip tio n
▼ Integ ra ted ARM7 TDMI RISC
p rocessor core
▼ 1 6 or 8 b it m em ory b us
▼ 3 , full-d up lex HDLC form a tters
w ith FIFO
▼ 3 -w a y GCI interfa ce a nd
router
▼ Sup p orts up to 8 GCI
p erip hera ls p er p ort
▼ UART w ith full-d up lex 1 6 b yte
FIFOs
▼ ISDN NT+
▼ ISDN / IDSL routers /
m ultip lex ers
▼ ISDN PABX
▼ ISDN / IDSL Term ina l Ad a p tors
The MTC-20280 is a fully integrated
controller for ISDN/ IDSL terminal
equipment applications. It has been
specifically designed for control and
interface functions between an ISDN
access device, such as the MTC-
20276/ 77 Integrated NT, and other
terminal functions such as analog
interfaces, e.g. by means of the MTK-
40131 Short-Haul POTS chipset. It
incorporates an ARM7TDMI RISC
core, which can perform all of the
terminal control functions required in
software. It can thus form the core of
an Intelligent NT, or “NTplus” unit, as
well as being the core of router/ multiplexer
equipment for IDSL applications. the
on-chip GCI router allows any B--channel
in any timeslot of any GCI port to be
routed to any other B-channel without
the need for CPU intervention. In
addition, the 3 GCI ports support all
modes including the x8 multiplex
mode, allowing up to 16 analog
channels to be accessed per port. It
can also form the core of a small
ISDN based PABX.
▼ 8 -b it a nd 4 -b it p a ra llel I/ O
p orts
▼ 1 0 0 p in PQFP Pa ck a g e style
Ord ering Inform a tion
Part number
Package
Temp.
MTC-20280PQ-C 100 pin PQFP
MTC-20280PQ-I 100 pin PQFP
0 / +70°C
- 40 / +85°C
Fig ure 1 : Block Dia g ra m
For tape and reel, add T after package code (eg PQT)
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
TABLE O F CO N TEN TS
Key Features ........................................................................................................................................................1
Ordering Information ............................................................................................................................................1
Key Applications ..................................................................................................................................................1
General description ..............................................................................................................................................1
Table of Contents..................................................................................................................................................2
List of Figures .......................................................................................................................................................3
Electrical Characteristics........................................................................................................................................4
TTL DC Electrical characteristics (1):.....................................................................................................................4
CMOS DC Electrical characteristics (1): ...............................................................................................................4
AC Characteristics.............................................................................................................................................5
Memory Interface...........................................................................................................................................5
GCI interfaces ...............................................................................................................................................6
Absolute maximum ratings .....................................................................................................................................7
Operating ranges .................................................................................................................................................7
Operating environment..........................................................................................................................................7
Storage and Transportation conditions ....................................................................................................................7
Application information .........................................................................................................................................8
Typical application ...............................................................................................................................................8
Application schematic and external components.......................................................................................................8
The JTAG test port.................................................................................................................................................9
Detailed functional description .............................................................................................................................10
Detailed block description....................................................................................................................................12
GCI .................................................................................................................................................................13
GCI Frame formats: .........................................................................................................................................13
Parameter updating: timing and initial values......................................................................................................14
Handling D channel collisions ...........................................................................................................................15
Reset..............................................................................................................................................................15
GCI router Architecture ....................................................................................................................................16
Multiplexer .....................................................................................................................................................16
D/ CI activity detection .....................................................................................................................................21
GCI clock generation.......................................................................................................................................22
Hardware implementation of the GCI clock multiplexing.......................................................................................23
Data frame tracking .........................................................................................................................................23
HDLC formatter...................................................................................................................................................25
Description .....................................................................................................................................................25
Features: ........................................................................................................................................................25
HDLC protocol ................................................................................................................................................25
HDLC Control registers.....................................................................................................................................26
Clock generation ................................................................................................................................................32
CPU clock control protection .............................................................................................................................32
The ARM7TDMI and its interfaces .........................................................................................................................33
APB Bridge .....................................................................................................................................................34
On chip memory .............................................................................................................................................34
External Memory interface ................................................................................................................................34
Wait state(s) per memory block:........................................................................................................................37
Memory access timing. ....................................................................................................................................38
Memory space organisation .............................................................................................................................39
Interrupts ........................................................................................................................................................40
Interrupt mapping ............................................................................................................................................41
External interrupt .............................................................................................................................................41
2
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
UART interface ...................................................................................................................................................42
Features : .......................................................................................................................................................42
Baud rate generator.........................................................................................................................................42
Parallel I/ O ports ...............................................................................................................................................46
Timers ...............................................................................................................................................................48
Timers 1 and 2 ................................................................................................................................................48
Watch-dog timer .............................................................................................................................................49
Hardware identification code ..............................................................................................................................51
Programming Notes ............................................................................................................................................52
Register map summary .....................................................................................................................................52
Register physical addresses...............................................................................................................................52
D-channel collision avoidance ...........................................................................................................................59
Package and Pin-out ...........................................................................................................................................60
Pinout.............................................................................................................................................................60
Pin Description and assignment .........................................................................................................................61
Important notes on 5 V tolerant pins...................................................................................................................61
Pin description table.........................................................................................................................................62
Pin function in normal operating mode ...............................................................................................................63
Device branding..............................................................................................................................................65
Contact Addresses..............................................................................................................................................68
LIST O F FIGURES
Figure 1 : Block Diagram.......................................................................................................................................1
Figure 2 : Memory bus timing parameters................................................................................................................5
Figure 3 : GCI bus signal timing .............................................................................................................................6
Figure 4 : Typical application block diagram ...........................................................................................................8
Figure 5 : Application schematic and external components ........................................................................................8
Figure 6 : GCI Frame Formats ..............................................................................................................................13
Figure 7 : Timing of GCI control register updates....................................................................................................15
Figure 8 : GCI Router architecture.........................................................................................................................16
Figure 9 : C/ I bit interrupt architecture ..................................................................................................................21
Figure 10 : GCI clock generation .........................................................................................................................22
Figure 11 : Multiplexing of the GCI clocks (U interface example)..............................................................................23
Figure 12 : Pattern periodicity of the 4096 kHz GCI data clock ...............................................................................24
Figure 13 : HDLC Frame Format ...........................................................................................................................25
Figure 14 : The ARM7TDMI processor core and its interfaces...................................................................................33
Figure 15 : MTC-20280 - External Memory connections for ‘Case a’. .......................................................................35
Figure 16 : MTC-20280 - External Memory connections for ‘Case b’. .......................................................................36
Figure 17 : MTC-20280 - External Memory connections for ‘Case c’.........................................................................36
Figure 18 : MTC-20280 - External Memory connections for ‘Case d’. .......................................................................36
Figure 19 : Memory interface signals – Read and Write cycles ................................................................................38
Figure 20 : ARM address space organisation / Memory-map ..................................................................................39
Figure 21 : Watchdog Finite State Machine...........................................................................................................49
Figure 22 : Device pinout ....................................................................................................................................60
Figure 23 : Device branding ................................................................................................................................65
3
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Ele ctrica l Ch a ra cte ristics
The I/ O pin type as well as the rated
buffer current is given in the pin
description section; note also that
some inputs are Schmitt Trigger inputs.
TTL DC Electrica l Cha ra cteristics (1 ):
(see pin description section and special notes on 5V tolerant pins)
Sym b ol
VIH
VIL
Pa ra m eter
Cond itions
Min
2.0
Ma x
Unit
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
0.8
VOH
Ioh=rated
buffer current
Iol=rated
2.4
V
VOL
Low Level Output Voltage
buffer current
0.4
1.9
1.3
1
V
V
V
pF
pF
Vt+
Vt-
CIN
COUT
Schmitt trigger rising threshold
Schmitt trigger falling threshold
Input Capacitance, all inputs
Load Capacitance, all outputs
1.3
0.8
100
CMOS DC Electrica l Cha ra cteristics (1 ):
(see pin description section and special notes on 5V tolerant pins)
Sym b ol
VIH
VIL
Pa ra m eter
Cond itions
Min
80% of VDD
Ma x
Unit
V
V
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
20% of VDD
VOH
Ioh=rated
buffer current
Iol=rated
85% of VDD
V
VOL
Low Level Output Voltage
buffer current
0.4
2.5
1.3
1
V
V
V
pF
pF
Vt+
Vt-
CIN
COUT
Schmitt trigger rising threshold
Schmitt trigger falling threshold
Input Capacitance, all inputs
Load Capacitance, all outputs
1.8
0.8
100
(1) Rated for Vdd=2.7V to 3.6V and ambient temperature from 0 to +20 °C for C-version, -40°C to +85°C for I-version.
4
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
AC Ch a ra cte ristics
Mem ory Interfa ce
Fig ure 2 : Mem ory Bus Tim ing Pa ra m eters
Cycle
READ
Pa ra m eter
Min
8
0
Ma x
Units
ns
ns
tas
tah
tcw
32.5
(0.5 + x) * ASB period
(x = wait cycles)
ns
ns
ns
ns
ns
ns
ns
tes
the
tco
toh
tas
tah
tcw
0
0
(tcw - 17)
0
8
0
WRITE
32.5
(0.5 + x) * ASB period
(x = wait cycles)
20
ns
ns
ns
tos
toh
0
Remark: the timings are valid over all operating range conditions
5
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
GCI In te rfa ce s
Fig ure 3 : GCI Bus Sig na l Tim ing
Timing reference voltages
Sig na l
Output
Input
Hig h
2.4V
2.0V
Low
0.4V
0.8V
Pa ra m eter
Clock period
Pulse width
Frame
Frame rise/ fall
Frame width H
Frame width L
Frame hold
Sig na l
DCLK
DCLK
DFR
DFR
DFR
Mnem .
tDCL
twL, twH
tsF
Units
ns
ns
ns
ns
ns
ns
ns
Min.
239
90
Ma x .
70
tDCL-50
60
tr, tf
twFH
twFL
tfH
130
tDCL
50
DFR
DFR
Data delay, clock
Data delay, frame
Data set-up
DOUTx
DOUTx
DIN
tdDC
tdDF
tsD
ns
ns
ns
ns
100 (1)
150 (1)
twH+20
50
Data hold
DIN
thD
Note (1). Capacitive load = 150 pF.
6
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Ab so lu te Ma x im u m Ra tin g s
Stresses above those listed below can
cause permanent device failure.
Exposure to absolute maximum ratings
for extended periods can effect device
reliability. See Operating ranges section.
Sym b ol
VDD
VIN
Cond itions
power supply voltage
input voltage on any pin
Min
VSS - 0.3
VSS - 0.3
Ma x
4.0
Unit
V
V
V
VDD + 0.3 AND < 4.0
TBD
VIN5
input voltage on any 5V tolerant pin TBD
O p e ra tin g Ra n g e s
Operating ranges define the limits for
functional operation and schematic
characteristics of the device as
described above, and for the reliability
specifications as listed in the relevant
section. Functionality outside these
limits is not implied.
the ambient temperature under bias
must be less than 0.1% of the useful
life as defined in the relevant section.
device. However, if the accumulated
time when this situation occurs doesn’t
exceed 5 hours (18000 s) over the
total life of the device, the impact on
the total lifetime will remain negligible.
Therefore the 5V and 3.3V power
supplies must always be present
together, except during the short
power on/ off transient states which
rarely occur.
Furthermore, when the 5V tolerant IO
cells are used in a 5V system, the
application should be designed such
that no 5V signals are applied when
the 3.3V power supply is not present.
This otherwise limits the lifetime of the
Total cumulative dwell time outside the
normal power supply voltage range or
Sym b ol
VDD
Cond itions
power supply
full-operation power consumption
stand-by power consumption
ambient temperature I-version/ C-version
Min
3.0
Ma x
3.6
100
40
85/ 70
Unit
V
mW
mW
deg C
PTOT (1)
PPD (2)
amb
T
-40/ 0
(1) Power with all blocks of the MTC-
20280 operational and maximum
clock frequencies used at nominal
power supply voltage (3.3V) + 5%
(2) Power with all blocks of the MTC-
20280 operational, except the ARM
which is in power down mode, at nominal
power supply voltage (3.3V) + 5%
O p e ra tin g En viro n m e n t
The components are intended for
application in equipment for indoor
operation without forced cooling
airflow, only convection.
Sto ra g e a n d Tra n sp o rta tio n Co n d itio n s
The rated storage and transportation
temperature range prior to printed
board assembly is -55 to +110 °C.
In the case of IC deliveries in dry bag,
the conditions of time and humidity
during storage are specified in Alcatel
Microelectronics spec 16650. In the
case of IC deliveries not in dry bag,
the conditions for a maximum storage
period of 2 years are as follows:
Am b ient Tem p era ture (d eg C)
Rela tive Hum id ity (%)
20
30
40
50
80
70
60
50
7
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Ap p lica tion Inform a tion
Typ ica l Ap p lica tion
The MTC-20280 offers a flexible
processor architecture for use in a
wide range of telecommunications
applications where the GCI standard
interconnection bus is used.
Particularly, it offers functions and
features specifically relevant to ISDN
terminal adapter and advanced NT
applications such as “NTplus” or “NTN”.
In such applications, the block schematic
shown below is commonly used. Here,
the MTC-20280 is used to control and
monitor the MTC-20276 (or MTC-
20277) Integrated NT device (operating
in its external access mode) and the
MTK-40131 chipset for short-range
analog telephone (“POTS”) interface.
UART
Other applications such as small PABX
systems or remote access
Fig ure 4 : Typ ica l Ap p lica tion Block Dia g ra m
concentrators can also be addressed.
*
*
*
e.g.MTK-40131
*PULL-UP NEEDED
on both DO and DI
Fig ure 5 : Ap p lica tion Schem a tic a nd Ex terna l Com p onents
8
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Ap p lica tion Schem a tic
a nd Ex terna l Com p onents
The following external components
may be needed, depending upon the
application environment. GCI related
components(The pull-up on the DCI DI
pins) depend upon the requirements of
the external GCI device:
Na m e
RgciDOU
Descrip tion
Recom m end ed Va lue
Tolera nce
10%
Pull-up for GCI data-up output towards U interface
(either to 5V or 3.3V, dependent on application)
Pull-up for GCI data-down output towards S interface
(either to 5V or 3.3V, dependent on application)
Pull-up for GCI data-down output towards A interface
(either to 5V or 3.3V, dependent on application)
(2kOhm)
(2kOhm)
(2Kohm)
RgciDOS
RgciDOA
10%
10%
XTAL input related components:
Na m e
Descrip tion
Recom m end ed Va lue
Tolera nce
XTAL
External crystal to control on-chip oscillator via the
XTAL1 and XTAL2 pins.
15.36 MHz
±50 ppm
(Alternative is to control the XTAL1 pin by an external
master) clock source and connect XTAL2 to GND)
Capacitors for external crystal
CX1, CX2
30 pF
±10 pF
Power supply decoupling related
components:
Na m e
Descrip tion
Recom m end ed Va lue
Tolera nce
Cd[a..f]
Decoupling capacitors to be placed
in between each VDD-VSS pair of MTC-20280
Decoupling capacitors to be placed
100 nF
10%
Cd[g..l]
10 µF
10%
Hardware reset related components:
Na m e
Descrip tion
Va lue
Tolera nce
Rr.Cr
Power Reset circuit *
>= 1ms
10%
* Caution: As the NRST pin can be
pulled LOW by a watchdog timeout,
the application circuit should contain
a 10 Ohm resistor in series with the
pin when an external capacitor with
value larger than 100nF is used. (The
NRST pin will attempt to discharge this
capacitor very quickly, causing a high
peak current which may result in
damage to the pin driver. The resistor
limits the current to safe values).
Th e JTAG Te st Po rt
The MTC-20280 has a standard JTAG
interface to facilitate device
production testing. However, it is also
directly compatible with the In-Circuit
Emulation hardware of ARM Ltd. It can
be used to provide full de-bugging
facilities, as supported by the ARM
Software Development Toolkit from
ARM. Please contact your Alcatel
Microelectronics sales-office or
representative for more information.
9
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
De ta ile d Fu n ctio n a l De scrip tio n
O ve rvie w
CPU
(pseudo)static RAMs. The bus interface
2. S interface of MTC-20276/ 20277
INT, GCI-S
3. Interface to analog devices such as
MTK-40131 short-haul POTS
chipset, GCI-A
The integrated ARM7TDMI CPU will
generally use the 16-bit data bus
mode ‘Thumb’. The external bus
interface supports 16- or 32-bit
transfers, multiplexed to 16- or 8 bits.
Access to the on-chip SRAM can take
place as 8, 16, or 32 bit transfers (it
thus supports the full performance of
the ARM CPU). The CPU will generally
run at the clock frequency set by the
crystal oscillator (15.36 Mhz).
However, a programmable divider is
provided to allow software control of
the processor speed, and therefore the
power consumption.
logic includes a programmable WAIT
STATE generator, to allow access to
slow external memory or peripherals.
Bus timing is to allow zero wait state
execution (with fast off-chip memory)
at a CPU clock of 15 Mhz. 1 kbyte of
fast (0 wait-state with 32 bit access),
on-chip static RAM is included.
In reality, all three GCI ports are
identical - the allocation to U, S, and
A (analog) is arbitrary, for clarity only.
A programmable Chip-Select (“CS”)
decoder defines the external memory-
map - the default map ensures that the
CPU can start up from reset by
The U interface block of the INT will
always provide the GCI clocks
(master) when active. (This can be
achieved by issuing the AWAKE
command on the GCI C/ I bits to the U
interface, which activates the timing
generator of the U interface without
actually initiating transmission).
All other GCI buses will generally be
slaved to this one. In applications
where the use of the U interface is not
mandatory (e.g. in a micro-PABX
system which allows internal calling
without U activation), an internal GCI
clock source can be selected. An
integrated PLL system may be enabled
to allow the internally generated GCI
clocks to track and lock to the U GCI
clock, should this become active in the
course of operation.
enabling ROM at address 0. It
provides for seven external memory
ranges to be individually decoded.
With regard to EMC requirements, the
slope of the memory bus transitions is
controlled, in a manner consistent with
achieving the required bus transfer
speed. Each CS memory range has
programmable wait-states.
Clo ck g e n e ra tio n a n d co n tro l
A master clock oscillator, based on
an external crystal of 15.36Mhz,
is provided. This provides an output at
the crystal frequency for use by the
ISDN chip (INTT or INTQ).
A programmable divider allows lower
frequencies to be output, as required.
The CPU clock frequency is SW
selectable, allowing the power-
consumption to be reduced at times
when full processing speed is not
required.
An external interrupt request pin
allows external peripheral devices
to communicate asynchronously with
the CPU.
3 -w a y GCI in te rfa ce
(Terminology. ‘DOWNSTREAM’ refers
to the transfer of data coming from the
U interface towards the S or Analog
interfaces in an ISDN application.
Upstream is the direction from the S
or analog interfaces towards the U.)
Me m o ry b u s
The external memory bus supports
either 8-bit (for low cost) or 16 bit
(high-speed) memory systems. It allows
read/ write access to off-chip memory
and I/ O resources, and includes a
simple to use on-chip memory
decoding scheme to minimize external
logic. It is designed to interface to
standard FLASH EEPROM and
The device provides for three
GCI ports: normally allocated
as follows:
1. U interface of MTC-20276/ 20277
INT, GCI-U
10
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
All bytes of the GCI frames of all three
GCI interfaces are accessible to the
Generally, HDLC1 will be used to
manage the ISDN D-chanel. D-channel
conflicts between the S bus and the
HDLC1 controller of the device are
handled by forcing a "D-channel busy"
condition on the S-bus by means of the
appropriate command to the S interface
of the INT. This is done only after the
microprocessor has verified that the
BUSY bit in the SIC’s control registers is
clear (i.e. D-channel not in use).
Pa ra lle l I/ O p o rts
A number of 4-bit parallel I/ O ports
are provided, primarily to allow an
interface to external DTMF decoder
chips. The ports are addressable by
the CPU as a latched output, an
unlatched input, and a data-direction
register which is used to select the
direction (input at reset) of each bit.
External port pins may also request an
interrupt to the CPU (maskable) when
programmed to be an input.
processor, for both reading and writing.
A sophisticated router allows any of the
GCI fields (B channel, D channel, C/ I
bits, and Monitor channel) to be routed to
the corresponding field of any destination
channel. Bytes can also be ‘disabled’, in
which case they remain at the idle - logic
‘1’ - state. Particularly powerful is the
ability to set fixed routes of the B channels
from a source to any destination without
the need for further intervention by the
CPU, thus relieving the CPU of much real-
time processing. Up to eight GCI time-
slots is supported on each GCI port
independently, where external GCI clocks
are available. The internal GCI clock
supports one timeslot or eight timeslots.
The clock source (which determines the
number of timeslots supported by the
channel) is independently selectable for
each GCI port. Using an external clock
thus allows the GCI ports to interface to
all commonly used ISDN devices.
HDLC controllers 2 and 3 are
generally used to handle packetised
data transport over the B channels
(including balanced applications such
as LAPB). However, in specific
applications such as internal call
transfer support or PABX,
the D-channel to/ from the S-bus
requires independent management
(while still monitoring the D channel
to/ from the U interface). HDLC 2 or 3
may be used for this purpose.
In te rru p t co n tro l
The device contains several interrupt
sources. Each can be masked by
setting a bit in a control register.
Priority is resolved in software; all
‘interrupt request’ bits from the various
sources are readable in a register. This
register can be written to; writing a '1'
clears the corresponding request bit, but
writing a '0' has no effect. Individual
interrupt control registers also exist within
each of the functional blocks (HDLC
controller, UART etc.). The registers
described here provide a centralized
and thus fast means of handling
DTMF d e co d in g
With regard to EMC requirements, the
slope of the GCI data output pins is
controlled, in a manner consistent with
achieving the required bus transfer speed.
This function may be performed by low-
cost, external DTMF decoder circuits,
interfacing to the CPU via an on-chip
parallel I/ O port (programmable bit
directions). Alternatively, software
algorithms on the ARM7TDMI
priorities. The various interrupt sources
are permanently routed to the nIRQ
(normal interrupts) and to the FIRQ (fast
response) of the ARM7 CPU.
HDLC co n tro lle rs
processor may be used. The 0-wait-
state on-chip RAM facilitates this.
The three integrated HDLC controllers
can be routed two / from any B or D
channel of any port. In addition, they
each have full-duplex 64 byte FIFOs,
which allow a large timing latency and
thus ease software timing constraints. The
HDLC controller protocol may be
disabled under software control, thus
allowing the FIFOs to be used to buffer
real-time data, e.g. for the processing of
voice-band signals on B-channels (DTMF
decoding, modem emulation, pre-
recorded voice announcements etc.)
Se ria l I/ O
A UART with selectable baud-rate and
16 byte FIFOs is provided. The baud-
rate is programmable to standard
rates up to 57.7kbit/ s, 115kbps and
230 kbps, and is compatible with the
standard UART 16C550. The Rx and
Tx pins are 5V compatible. The
modem controls RTS and CTS from the
UART block are available as 5V
compatible pins.
11
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Tim e rs / w a tch d o g
allowing interrupts to be generated at
regular, programmable intervals.
Timer 2 also support timer-capture
functions (the source of which is
selectable). This allows the timing of
external events to be simplified (one
common application being hook-flash
detection on the analog ports).
2, 16 bit timer/ counters and a
(1-second) Watchdog timer are
included. The timers support auto-pre-
load timer interrupt generation, thus
12
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
De ta ile d Blo ck De scrip tio n
GCI fra m e fo rm a ts:
The contents of one GCI frame is
different whether it concerns an ISDN
interface (U or S) or an analogue
interface (SHPOTS). ISDN connections
use two D-channel bits, which are
used as normal signalling/ control
bits for SHPOTS.
The MTC-20280 however will always
handle the U, S, and A interfaces in
the same way: They are functionally
identical and can be interchanged,
the names U, S, and A being used for
convenience only. Therefore, the two
D and four C/ I bits are always
considered separately as for an ISDN
connection.
The software is responsible for correct
interpretation of the two formats, i.e.
consider the two D bits as two
additional CI bits.
Fig ure 6 : GCI Fra m e Form a ts
The meaning of the six C/ I bits for
Alcatel Microelectronics’ SHPOTS is
described in the MTK-40131 data-
sheet. The interpretation of these for
the ISDN components MTC-2071
(single 4B3TU interface), MTC-20172
(S-interface), MTC-20276 and MTC-
20277 (Integrated NT devices for
2B1Q and 4B3T respectively) is
described in detail in the data-sheets
for these products.
Serial communication is done MSB
first; therefore the MSB of the data in
parallel registers of the MTC-20280
that are related to GCI, will be
sent/ received as the first bit.
B1 cha nnel
B2 cha nnel
Monitor cha nnel
C/ I cha nnel
GCI
(1 byte)
(1 byte)
(1 byte)
(1 byte)
VERSION
Signalling and
control bits
Monitor
handshake bits
ISDN
ANALOG
B1 (8)
B1 (8)
B2 (8)
B2 (8)
M (8)
M (8)
D (2) C/ I (4)
C/ I (6)
A/ E (2)
A/ E (2)
13
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
In order to cope with the difference in
convention between GCI and HDLC
(LSB first) formats, the HDLC modules
offer the possibility to do bit-reversal
on the parallel data when the data are
not to be HDLC formatted. This is
selected by means of a user-
on this default rule. The Source, CPU
and Swap registers of the GCI router
(i.e. all registers named “_SRC”,
“_CPU” and “_SWP) can be written at
any time, but will only be updated
/ used based on the rate at which the
RAM open/ closed space will be
switched (see architecture of GCI
router). The rate is equivalent to the
GCI frame rate, but the moment of
switching coincides with the last byte
of the last burst in the GCI frame (see
next Figure). The value that is read is
the value that is used in the current
GCI frame I; therefore, the read value
can be different from the last written
value (if no update was done since it
was last written).
Notice that after power reset, no write
operations will be issued before the
first GCI frame FSC is generated. This
in order to allow correct initialisation
of the MTC-20280.
Notice also that, after power reset, the
default GCI clocks selected for U/ S/ A
is the ‘power down’ mode. This means
the FSC/ DCL remains inactive low
(‘0’), but also the output GCI data
stream remains inactive high (‘1’:
idle). Thus, none of the uninitialised
register values will be put onto the
output stream, except under software
control. The software has to do the
appropriate initialisation before
programmable control bit.
The MTC-20280 supports multiplexed
GCI channels: E.g. an 8-channel
multiplexed mode, in which case the
frame contents as described above, is
sent eight times faster over the bit-
serial I/ O. According to the GCI
specification, the first transmitted
channel is called Channel0, the last
one Channel7; these channels are
referenced to as “Burst0” up to
selecting it as source register.
“Burst7” in the following sections. GCI
frames of up to 3088 kbps (eight
bursts x 32bit + 130 spare bits, all at
8kHz) are accepted if generated by
an external GCI master. An external
GCI master may also apply less than
eight bursts, e.g. a 768kbps GCI
frame of three bursts of 32 bits.
The HDxTX registers are read only
and show the value which is being
transferred in the current GCI frame
(see next Figure). The RX registers (i.e.
all registers named “_RX”) are read
only and show the value which was
received during the previous GCI
frame (see next Figure).
When the GCI clocks are switched
from one to another source (e.g.
between Umaster and crystal based
clocks on the A interface), the data
could be unpredictable during the
switch. This is because a re-
synchronisation must take place unless
specific measures are taken. The MTC-
20280 GCI clock circuitry contains a
digital phase-locked loop (DPLL) which
allows timing differences to be
For the RX register corresponding to
the last byte of the last burst in the
GCI frame, an exception must be
made, as shown in the figure. The
value should not be read during the
time window starting the moment the
RAM space is swapped until the start
of a new GCI frame. (It is therefore
recommended to read these registers
soon after the frame-interrupt request).
Pa ra m eter up d a ting :
tim ing a nd initia l va lues
The following sections describe the
functional building blocks and their
parameters, which are stored in
CPU-addressable registers in the
memory space.
tracked. See the section on GCI clock
generation for details.
The default rule is that all parameters
can be read or written at any time,
and the new value that is written is
immediately used. This is also valid for
the GCI related parameters
GCI_CPU_RX, GCI_SRC_BUR,
GCI_ITx and GCI_MSCx (x=U,S,A).
However, for the following GCI
related registers an exception is made
14
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Fig ure 7 : Tim ing of GCI Control Reg ister Up d a tes
Ha n d lin g D ch a n n e l co llisio n s
The GCI router and MTC-20280
architecture / parameters allow the
control of whether the D-channel from
S to U upstream is busy or not; it
allows use of the output of an HDLC
block as D-channel U-up when S is
inactive. Details on this are described
in the ‘Programming’ section.
NRST: resets the integrated ARM
processor (i.e. disables the ARM clock)
and the functional MTC-20280 blocks,
without affecting the JTAG related
memories. (I.e. the test configuration
register, down-loaded via the bit-serial
JTAG interface is not reset. If set in a
specific test mode, this mode will
remain selected while resetting the
ARM and functional blocks).
N TRST: resets the JTAG interface
logic, including the test configuration
register. This puts the MTC-20280 in
non-test, functional mode. Note that
the NTRST input cell has an integrated
pull-down, such that the JTAG logic is
reset by default, without requiring a
connection to this pin on the PCB.
Re se t
The MTC-20280 has two reset pins:
NRST (Functional reset) and NTRST
(JTAG reset). Both active low reset
inputs are independent and do
not interact.
Note also that the NRST pin is made
bidirectional, such that it can indicate
when the watchdog resets the
MTC-20280.
15
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
GCI Ro u te r Arch ite ctu re
Fig ure 8 : GCI Router Architecture
The core of GCI Router is made of a dual
port RAM. One port is dedicated to the
GCI interfaces, the other one to the
processor access.
Multip lex er
further on).
The CPU can program an automatic
routing of any channel from any burst
through the GCI buses, from the CPU
addressable registers or from one of
the 3 HDLC formatters.
In addition, “swapping” can also be
programmed between the channels
B1 and B2 via the so-called SWP
registers. (This allows re-allocation
of the B1 and B2 channels, should
the external device not support
this function).
The RAM is split into two spaces:
Open: space where the data can be
modified, used to store the
The source of each channel output is
controlled by the value stored in the
source control registers, as shown in
the next register table. The registers
can be written by the ARM: if a new
value is written to the register, it will
only be used from the next GCI frame
onwards. However, due to the RAM
architecture, a valve which must stay
constant indefinately must be written
in two concecutive frames. Before
reading such a SRC register, the burst
number must first be specified by
writing into register GCI_SRC_BUR.
This is because up to eight sources
can be stored in a SRC register, one
for each possible burst (see examples
incoming GCI frames.
Closed: space where the data are held for
one GCI frame, used to store the
GCI frames to be sent.
This architecture allows the reception and
transmission of up to eight bursts per GCI
interfaces (max 8x3x4 bytes).
Should any GCI interface work faster than
2048 kbps (e.g. 3088 kbps, the highest
GCI rate accepted by MTC-20280), the
extra bits received by the MTC-20280 will
not be stored in the RAM. The
corresponding output stream generated by
the MTC-20280 will contain idle spare bits
(i.e. value = ‘1’ according to GCI).
16
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
7F
Fu n ctio n
b y te
200
GCI_SRC_BUR
U_B1_SRC
Burst selection for reading Source control registers: [2:0] = target burst (0 to 7)
Source control of B1 U-up channels routing : [2:0] = target burst (0 to 7)
[4:3] = source line 0 = U-down channel
1 = S-up channel
80
2 = A-up channel
3 = Extension
[7:5] = if source line = U or S or A : source burst (0 to 7)
if source line = Extension: : one of following possible sources:
0 = IDLE
1 = CPU register
2 = HDLC1
3 = HDLC2
4 = HDLC3
U_B2_SRC
U_D_SRC
U_CI_SRC (*)
81
82
83
204
208
20C
Source control of B2 U-up channels routing description: idem
Source control of D U-up channels routing description: idem
Source control of C/ I U-up channels routing description:
idem, except for HDLC source (*)
U_M_SRC (*)
U_AE_SRC(*)
84
85
210
214
Source control of M U-up channels routing description:
idem, except for HDLC source (*)
Source control of A/ E U-up channels routing description:
idem, except for HDLC source (*)
S_B1_SRC
S_B2_SRC
S_D_SRC
86
87
88
89
218
21C
220
224
Source control of B1 S-down channels routing description: idem
Source control of B2 S-down channels routing description: idem
Source control of D S-down channels routing description: idem
Source control of C/ I S-down channels routing description:
idem, except for HDLC source (*)
S_CI_SRC (*)
S_M_SRC (*)
S_AE_SRC(*)
8A
8B
228
22C
Source control of M S-down channels routing description:
idem, except for HDLC source (*)
Source control of A/ E S-down channels routing description:
idem, except for HDLC source (*)
A_B1_SRC
A_B2_SRC
A_D_SRC
8C
8D
8E
8F
230
234
238
23C
Source control of B1 A-down channels routing description: idem
Source control of B2 A-down channels routing description: idem
Source control of D A-down channels routing description: idem
Source control of C/ I A-down channels routing description:
idem, except for HDLC source (*)
A_CI_SRC (*)
A_M_SRC (*)
A_AE_SRC(*)
U_B1_SWP
B0
B1
B2
2C0
2C4
2C8
Source control of M A-down channels routing description:
idem, except for HDLC source (*)
Source control of A/ E A-down channels routing description:
idem, except for HDLC source (*)
bit[ i ] = 0: no swap; B1-burst i U-up channel will be routed with the
B1 channel of the selected source (U,S,A only)
= 1: swap;
B1-burst i U-up channel will be routed with the
B2 channel of the selected source (U,S,A only)
U_B2_SWP
B3
2CC
bit[ i ] = 0: no swap; B2-burst i U-up channel will be routed with the
B2 channel of the selected source (U,S,A only)
= 1: swap;
B2-burst i U-up channel will be routed with the
B1 channel of the selected source (U,S,A only)
17
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
B4
Fu n ctio n
b y te
2D0
S_B1_SWP
bit[ i ] = 0: no swap; B1-burst i S-down channel will be routed with the
B1 channel of the selected source (U,S,A only)
= 1: swap;
B1-burst i S-down channel will be routed with the
B2 channel of the selected source (U,S,A only)
S_B2_SWP
A_B1_SWP
A_B2_SWP
B5
B6
B7
2D4
2D8
2DC
bit[ i ] = 0: no swap; B2-burst i S-down channel will be routed with the
B2 channel of the selected source (U,S,A only)
= 1: swap;
B2-burst i S-down channel will be routed with the
B1 channel of the selected source (U,S,A only)
bit[ i ] = 0: no swap; B1-burst i A-down channel will be routed with the
B1 channel of the selected source (U,S,A only)
= 1: swap;
B1-burst i A-down channel will be routed with the
B2 channel of the selected source (U,S,A only)
bit[ i ] = 0: no swap; B2-burst i A-down channel will be routed with the
B2 channel of the selected source (U,S,A only)
= 1: swap;
B2-burst i A-down channel will be routed with the
B1 channel of the selected source (U,S,A only)
N o te s:
channels. For the data routed from
one GCI interface to another one, a
delay of one GCI frame is inserted.
All register contents are undefined
If one wants to connect the destination
• "U / burst3 / B1" with the source
"S / burst7 / B2", then make
• U_B1_SRC[7..0] = “111 01
011” (source burst=7 ; source=S ;
target burst=3), and
after reset, which means that the user
software must initialise all the register
values before using them. Note
however that the default source of all
GCI channels is the IDLE source, such
that all output streams will be
If the target burst number is set higher
than the number of bursts which may
be transmitted on a GCI output
stream, it will be neglected.
• U_B1_SWP[7..0] = “xxxx 1xxx”
(bit3 set to ‘1’ in order to swap the
source of U/ B1: B2)
continuously ‘1’ (idle).
Conversely, for a source burst number
higher than the number of bursts in the
GCI input stream, the content of the
byte will be unspecified. In case of a
non-multiplexed GCI stream, the
source and target burst numbers must
be set to ‘0’.
All registers can be read and written:
Write operation: the new value will be
effective from the next GCI frame on.
Read operation: value used for the
current GCI frame is read The HDLC
source selections are not applicable
for the CI, M and AE channels (see
registers marked (*)); the bits are
unspecified if the HDLC would still be
selected as source. Therefore, it is
advised not to do so.
Note that the SWAP register values
are only used if the corresponding
source is U, S, or A (upstream or
downstream) and is not an HDLC
controller or IDLE, for example.
Ex a m p le s:
If one wants to connect the destination
"U / burst3 / B1" with the source
"S / burst7 / B1", then make
• U_B1_SRC[7..0] = “111 01
011” (source burst=7 ; source=S ;
target burst=3), and
• U_B1_SWP[7..0] = “xxxx 0xxx”
(bit3 set to ‘0’ in order not to swap
the source of U/ B1: B1)
For an ‘Analog’ GCI frame, the D and
CI channels form one entity but the
MTC-20280 handles them separately;
therefore, the user software should use
the same selection for both D and CI
18
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Reading the SRC value shows the
connection that is selected for the
current GCI Frame. Because eight
values can be specified at the same
time for each SRC register (e.g.
U_B1_SRC, one value per target
burst), reading U_B1_SRC necessitates
first writing to register GCI_SRC_BUR
to choose one target burst:
• Write U_B1_SRC[7..0] = “111
00 010” (source burst=7 ;
source=U ; target burst=2)
• Write U_B1_SRC[7..0] = “101
10 001” (source burst=5 ;
source=A ; target burst=1)
• Write GCI_SRC_BUR[2..0] =
“011” (specify target burst=2 for
reading)
• Write GCI_SRC_BUR[2..0] =
“011” (specify target burst=3 for
reading)
• Read U_B1_SRC[7..0] = “110
01 011” (source burst=6 ;
source=S ; target burst=3)
CPU registers (ARM “→” GCI)
• Read U_B1_SRC[7..0] = “111
00 010” (source burst=7 ;
source=U ; target burst=2)
Through the CPU registers,
the ARM can send data directly
to any GCI channel.
• Write U_B1_SRC[7..0] = “110
01 011” (source burst=6 ;
source=S ; target burst=3)
Reg ister ta b le:
N a m e
Ad d re ss
w o rd
60
Fu n ctio n
b y te
180
Ui_B1_CPU
CPU source value register for U-up / B1, burst i
i is defined by the register GCI_CPU_RX
Ui_B2_CPU
Ui_M_CPU
Ui_E_CPU
61
62
63
184
188
18C
CPU source value register for U-up / B2, burst i
CPU source value register for U-up / M, burst i
CPU source value register for [7:6] = U-up / D, burst i
[5:2] = U-up / CI, burst i
[1:0] = U-up / AE, burst i
Si_B1_CPU
Si_B2_CPU
Si_M_CPU
Si_E_CPU
64
65
66
67
190
194
198
19C
CPU source value register for S-down / B1, burst i
CPU source value register for S-down / B2, burst i
CPU source value register for S-down / M, burst i
CPU source value register for [7:6] = S-down / D, burst i
[5:2] = S-down / CI, burst i
[1:0] = S-down / AE, burst i
Ai_B1_CPU
Ai_B2_CPU
Ai_M_CPU
Ai_E_CPU
68
69
6A
6B
1A0
1A4
1A8
1AC
CPU source value register for A-down / B1, burst i
CPU source value register for A-down / B2, burst i
CPU source value register for A-down / M, burst i
CPU source value register for [7:6] = A-down / D, burst i
[5:2] = A-down / CI, burst i
[1:0] = A-down / AE, burst i
GCI_CPU_RX
78
1EO
Specifies the target burst for line U,S or A used when accessing the CPU and
RX registers:
[1:0] = target line;
0 = U
1 = S
2 = A
[4:2] = CPU target burst (0 to 7)
[7:5] = RX target burst (0 to 7)
Notes:
All registers are undefined after reset
(idem as for GCI multiplexing registers)
The register GCI_CPU_RX can define
and store three commands in parallel:
one for each interface (U, S, and A). The
last stored command for each interface
will be used to select the corresponding
CPU and TX register of that source.
Example:
• GCI_CPU_RX = “ 000 010 01 “ ; S:
CPU-burst=2 , RX-burst=0
• GCI_CPU_RX = “ 011 110 00 “ ; U:
CPU-burst=6 , RX-burst=3
Initialisation: select for S and U:
19
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
use CPU and RX registers:
NOTE: When a constant value needs to be
used from a CPU register, the value should
be written into the CPU register twice in
two consecutive GCI frames. (This is an
artifact of the architecture with two parallel
RAM spaces – the constant value must be
written into both RAM spaces. Failure to do
so results in the output value alternating
between the LAST output value and the
new (‘constant’) value).
• Si_B2_CPU = Ui_B1_RX; means
CPU/ S_B2/ burst=2 gets data from
RX/ U_B1/ burst=3
re-select for S:
• GCI_CPU_RX = “ 000 101 01 “ ; S:
CPU-burst=5 , RX-burst=0
use CPU and RX registers:
• Si_B2_CPU = Ui_B1_RX; means
CPU/ S_B2/ burst=5 gets data from
RX/ U_B1/ burst=3
RX registers (GCI “→” ARM)
All CPU registers can be read and written:
write operation: new value will be effective
from the next GCI frame.
The CPU can read the GCI content on
each interface (U, S, and A) at any time,
with a delay of one frame:
read operation: value used for the current
GCI frame is read
Reg ister ta b le:
N a m e
Ad d re ss
w o rd
6C
6D
6E
Fu n ctio n
b y te
1B0
1B4
1B8
1BC
Ui_B1_RX
Ui_B2_RX
Ui_M_RX
Ui_E_RX
First byte of the U downstream GCI frame, burst i
Second byte of the U downstream GCI frame, burst i
Third byte of the U downstream GCI frame, burst i
Fourth byte of the U downstream GCI frame, burst i
i is defined by the register GCI_CPU_RX
6F
Si_B1_RX
Si_B2_RX
Si_M_RX
Si_E_RX
70
71
72
73
1C0
1C4
1C8
1CC
First byte of the S upstream GCI frame, burst i
Second byte of the S upstream GCI frame, burst i
Third byte of the S upstream GCI frame, burst i
Fourth byte of the S upstream GCI frame, burst i
i is defined by the register GCI_CPU_RX
Ai_B1_RX
Ai_B2_RX
Ai_M_RX
Ai_E_RX
74
75
76
77
1D0
1D4
1D8
1DC
First byte of the A upstream GCI frame, burst i
Second byte of the A upstream GCI frame, burst i
Third byte of the A upstream GCI frame, burst i
Fourth byte of the A upstream GCI frame, burst i
i is defined by the register GCI_CPU_RX
GCI_CPU_RX
78
1E0
Specify the burst targeted by the ARM when writing to the CPU and RX registers:
[1:0] = target line;
0 = U
1 = S
2 = A
[4:2] = CPU target burst (0 to 7)
Notes:
All RX registers can only be read: The value received during the previous GCI frame is read.
20
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
D/ CI Activity De te ctio n
Mask
Activity
U1-DCI
U-D/ CI, frame i
U-D/ CI, frame i-1
itCI
Fig ure 9 : C/ I Bit Interrup t Architecture
The value of each bit of the six D/ CI-
bits of one GCI burst is compared to
its value during the previously
received GCI frame.
There is one mask register per D/ CI-
activity-detection register. After reset,
the mask registers are set to 0xFF, all
activity detection being masked.
The interrupt requests stay active until
they are explicitly cleared by writing
to the GCI_ITx registers.
The interrupt source itCI is internally
routed to the interrupt handler (i.e. the
raw, unmasked interrupt bit). It is also
routed to the capture signal of Timer1,
which allows the time between events
to be measured (e.g. for detecting
dial-pulses on a POTS interface).
If at least one of the six bits of burst k
changed, the corresponding burst-bit
k=0..7 is set in the CI-activity-detection
register, unless it is masked (by setting
the corresponding ‘mask bit’ to 1).
If less than 8 bursts are present on a
certain GCI interface, the activity bits
corresponding to the non-existing
bursts will remain inactive ‘0’; so no
masking is required to prevent an
incorrect activity detection.
There are three D/ CI-activity-detection
registers: one for each interface (U, S,
and A), each eight bits wide (for the
eight possible bursts per interface).
Note that no debouncing is done on
the activity detection. If necessary, this
must be done in software.
From the moment that one of the 3x8
CI-activity bits is active, an interrupt
request is generated.
Reg ister ta b le:
N a m e
Ad d re ss
w o rd
79
Fu n ctio n
b y te
1E4
GCI_ITU
READ access:
bit[i]=1 : CI activity detected on U-downstream, burst I
WRITE access:
bit[i]=1 : reset the interrupt detection on U-downstream, burst I
READ access:
bit[i]=1 : CI activity detected on S-upstream, burst I
WRITE access:
bit[i]=1 : reset the interrupt detection on S-upstream, burst i
READ access:
GCI_ITS
GCI_ITA
7A
7B
1E8
1EC
bit[i]=1 : CI activity detected on A-upstream, burst i
WRITE access:
bit[i]=1 : reset the interrupt detection on A-upstream, burst i
bit[i]=1 : mask CI activity detection on U, burst i
bit[i]=1 : mask CI activity detection on S, burst i
bit[i]=1 : mask CI activity detection on A, burst i
GCI_MSKU
GCI_MSKS
GCI_MSKA
7C
7D
7E
1F0
1F4
1F8
21
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
GCI Clo ck Ge n e ra tio n
Fig ure 1 0 : GCI Clock Genera tion
Each GCI interface can work at a
different speed (=clock domain fsc/ dcl),
but in all cases each (U,S,A) is
synchronised via its FSC signal on one
and only one GCI Master FSC (fscMstr).
The selection of fscMstr as well as the
clock domain to be used for U,S,A is
under software control.
The Master FSC (fscMstr) can be
non-a ctive: this is the default after
reset, and means dcl/ fsc of that
interface remains inactive low and the
GCI data output stream remains
inactive high (idle code). Selection of
the non-active source for the interface,
will overrule any other source selected
for the data stream (e.g. U_B1_SRC =
HDLC1
selected from four different sources, and
the corresponding DCL clock will also
be used as an input to the MTC-20280:
• Crystal clocks = dcl512 / fsc512
• U GCI interface = DCLU / FSCU
• S GCI interface = DCLS / FSCS
• A GCI interface = DCLA / FSCA
As each interface can be selected to be
a GCI master, and at most one
will be overruled)
The default source after reset is the
internal crystal, because this source will
always be present.
interface can work as master and the
others as slave, all FSC/ DCL pins are
bidirectional. After reset, all three pairs
of pins are in input mode such that no
conflict occurs on any of the interfaces
with a possible external master device.
m a ster (dclMstr / fscMstr): the dcl/ fsc
clocks of that interface will follow the
dclMstr / fscMstr of the interface
For each clock domain fsc/ dcl of
U,S,A , one can choose between four
possible sources:
which is selected as master interface.
22
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
512k (dcl512 / fsc512): the dcl/ fsc clocks
are derived from the crystal (15.36 MHz),
but synchronized (1)
The source specified for that GCI interface
which is selected as Master, becomes
compatible with any other GCI compatible
device.
irrelevant: whatever source is specified, it will
not be used such that no conflicts can arise.
with the master frame clock (fscMstr). Dcl =
512 kHz, 1 burst per frame.
Bit-rates of up to 3088 kbps may be applied
as master; this corresponds to a maximum of
8 burst of 32 bits, followed by 130 spare
bits (see GCI specification). Note that should
spare bits occur in the input data stream,
these will not be stored for possible
With a crystal based master
4096k (dcl4096 / fsc4096): the dcl/ fsc
clocks are derived from the crystal (15.36
MHz), but synchronized with the master
frame clock (fscMstr). Dcl = 4096 kHz, 8
burst per frame.
(the MTC-20280 being GCI master), the
MTC-20280 can only generate either non-
multiplexed (one burst), or 8-burst
multiplexed GCI frame formats. However,
when an external master is specified, the
MTC-20280 will follow the format of the
external master: e.g. a 5-burst mode, or an
8-burst mode with extra spare bits. So the
MTC-20280, when in slave mode, is fully
processing, nor be routed through to another
GCI output data stream (e.g. from DIU to
DOS). Incoming spare bits are neglected,
and outgoing spare bits are always set idle
‘1’.
Note: When Xtal is selected as master, fsc is
synchronised with a free running, internally
generated crystal-based 8kHz FSC signal.
Ha rd w a re Im p le m e n ta tio n o f th e GCI Clo ck Mu ltip le x in g
The control of the multiplexers comes
directly (asynchronously) from the
CPU register CLK_GCI; the
application software must take care
when it modifies the multiplexing.
Typically, the control will be set once
at power-up initialisation because it’s
mainly dependent of the devices
connected to the GCI lines. The dcl
and dfr signals have the same source.
Fig ure 1 1 : Multip lex ing of the GCI Clock s (U Interfa ce Ex a m p le)
Da ta fra m e tra ck in g
The DPLL adds/ substacts a maximum of 32 pluses
of the 15.36 MHz clock per frame
the generated dfr’s will be free running.
Application example: For the S interface, use the
internal clocks (dfr512/ dcl512) and the frame
clock coming from the U as dfr master. As soon as
no activity occurs on the U frame, the S frame is
free running (based on the crystal frequency).
Immediately the U activated, the DPLL begins to
recover an eventual frame phase delay
between U and S.
The generated dfr signals (dfr512 and dfr4096)
are slaved to the dfr signal that has been chosen
as master. An on-chip digital PLL (DPLL) can make
a correction of maximum +/ - 1.7% per frame; so
a maximum of 30 frames (=50%/ 1.7%) can be
needed when changing the dfr master.
(= 32/ 1920=1.7% : 15.36 MHz = ± 65 ns). The
DPLL works with a hysteresis of 65 ns; a phase shift
of +/ -65 ns or more will caused a correction. A
flag bit reports the status of the DPLL (frames
synchro. / not synchro. See the CLK_3 register
description). If no frame clock is present on the
selected dfr master, no tracking will be applied, so
The frequencies of the data clocks (dlc512 and
dcl4096) are adapted in the same way.
23
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Reg ister ta b le:
Na m e
Ad d ress
Function
CLK_GCI
90
240
bit[5:0]: GCI DCL clock selection per interface U,S,A:
bit[1:0] = for the U GCI router
bit[3:2] = for the S GCI router
bit[5:4] = for the A GCI router
0 = non-active (default at reset)
1 = master : dclMstr / fscMstr
2 = 512k: dcl512 / fsc512
3 = 4096k: dcl4096 / fsc4096
bit[7:6] : GCI Master FSC selection (fscMstr)
0 = Crystal oscillator (default at reset)
1 = U
2 = S
3 = A
CHIP_GCI_L
CHIP_GCI_M
02
03
8
C
Bits per GCI Frame on GCI master interface (Read only):
result of auto-detection of the mode of the GCI master interface
this 16-bit word stored in upper (_M) and lower byte (_L) value corresponds to
the number of bits detected in one GCI frame:
e.g. 8-burst 2048 kbps : CHIP_GCI_[M/ L] = 256 = ox 01 00 = [1 / 0]
3-burst mode : CHIP_GCI_[M/ L] = 96 = ox 00 60 = [0 / 96]
8-burst 3088 kbps : CHIP_GCI_[M/ L] = 386 = ox 01 82 = [0/ 130]
bit [0] : DPLL status (read only)
CLK_3
93
24c
0 = internal gci clocks not synchronized with
the extern reference; dpll is tracking
1 = internal gci clocks synchronized
bit [1] : UART clock disable
bit [3:2]: APB clock division factor
0 = 15.36 Mhz/ 4 (max.speed)
1 = 15.36 Mhz/ 8
2 = 15.36 Mhz/ 16
3 = 15.36 Mhz/ 32
Note:
The 4096 kHz clock generated from
the crystal does not have a perfect
50% duty cycle clock. (The ratio
15360 to 4096 is not an integer
value).
Fig ure 1 2 : Pa ttern Period icity of the 4 0 9 6 k Hz GCI Da ta Clock
24
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
HDLC Fo rm a tte r
De scrip tio n
Fe a tu re s:
• 64 byte FIFOs in both directions
• Transparent mode, where the FIFOs
can be used to buffer data transfers
without HDLC formatting.
Three identical HDLC formatters are
provided. They can be routed to any
B1, B2, or D channels for any burst of
any U, S, or A interface. Each HDLC
formatter works as a single-channel
HDLC controller with separate send
and receive FIFO pools. It is designed
to work in OS1 Layer2 (Data Link
layer) applications, such as a LAP-D or
LAP-B processor.
• Flag generation and detection
• Abort generation and checking
• CRC generation and checking
• Zero insertion and deletion
• Receive address comparison
• 1 broadcast TEI register
• 2 programmable address matching
registers
• Data bit-reversal possible
(lsb ´ msb) in order to cope with the
different formatting between HDLC
(LSB first) and non-HDLC, GCI
formatted data (MSB first).
• Interruption generation
• 2 programmable “wildcard”
registers
• Transmit address of packets can be
set from register or data stream
HDLC p ro to co l
Flag
Flag
01111110
Address
Control
Information
in LAPD
FCS
01111110
Nmax=260
0-N Octets
(optional)
2/ 4 Octets
1-2 Octets
1-2 Octets
Passed between Receive/ Transmit FIFOs
Fig ure 1 3 : HDLC Fra m e Form a t
HDLC (High Level Data Link Control)
is a bit-oriented, synchronous serial
protocol used in data communications
systems. Both LAPD (Link Access
Protocol on D-channel) and LAPB
(Link Access Protocol Balanced)
are based on HDLC, differing only
in frame content.
Figure 13 shows the HDLC
frame format.
Ad d re ssin g
The frame address is contained in the
first field following the start flag. This
can be either one or two octets long,
and is used to distinguish the various
network devices from one another.
Together with optional address-
matching circuit, the HDLC block can
search the complete address field of
incoming frames, selecting only those
frames addressed to it. The address
field is transferred to and from the
HDLC block.
Fra m in g
A flag is the unique bit-pattern
‘01111110’ (7E hex), and marks
both the start and the end of the
frame. Flags are generated internally,
and the HDLC block automatically
appends start and end flags on
frame transmission. Flags are
searched for on a bit by bit basis,
and can be recognised at any point
in the received bit stream.
The HDLC block transmits and
receives data in frames. The start and
end of frames are marked by a unique
bit pattern called a flag. The data
between the start and end flags
consists of an address field, control
field, information field and a Frame
Check Sequence (FCS) field.
Flags are not transferred to or from
the HDLC block.
25
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Control
CRC generation and checking is
performed automatically by the HDLC
block. On transmit, the CRC generator
is initialised with FFFF hex. The CRC is
computed serially on the address,
control, and information fields, and is
then complemented before being
transmitted MSB first.
Fra m e a b ort
A control field follows the address field.
This can be either one or two octets long,
and is used to transfer commands and
responses between Layer 2 entities and
the network. The HDLC block does not
operate on this field, transferring it
transparently.
Transmission of data frames can be
prematurely cancelled by use of an
abort character. The transmitter aborts
a frame by sending the abort
character ‘11111110’ (FE hex). The
receiver interprets this character as an
abort, and begins the search for a
new frame.
In the receive direction the CRC
checker is initialised with FFFF hex on
receipt of a valid start flag. A CRC is
performed on all bits between the start
and end flags, including the
Inform a tion
Ho w to g e n e ra te
a Tx Fra m e Ab o rt:
This can be done in one of the
following 3 ways:
- disable the TX before the ‘end-of-
frame’ (indicated by writing the ‘last-
byte-indication’ to the TX-fifo)
- clear the TX-fifo before the ‘end-of-
frame’
The information field contains the data
to be transmitted, and may be null.
This field is not necessarily an integer
number of octets long. If the last few
bits of the information field do not
completely fill the last octet, then that
octet is padded with zeros before
being transferred to the Receive FIFO
as a complete byte. The device will
only transmit frames with an integer
number of octets (before zero
insertion).
transmitted CRC field, and the result is
compared to 1D0F hex (or
C704DD7B hex for CRC-32). The
frame is transferred to the receiver
FIFO, regardless of whether the CRC
checker detected an error or not. The
CRC field can also be transferred to
the receiver FIFO if required.
- let the TX-fifo run empty before the
‘end-of-frame’
Zero insertion/ d eletion
HDLC control registers
Zero insertion and deletion is
performed by the HDLC block to
prevent the start and end flags from
being imitated by the data. The
transmitter section inserts a zero after
any succession of five 1’s within a
frame (i.e. between start and end
flags). The receiver section
This section details the programmable
registers accessible to the CPU. These
registers either control the operation
Error check ing
The Frame Check Sequence (FCS)
field is contained in the last two octets
before the end flag in a frame. The
field is computed using a Cyclic
Redundancy Check (CRC) polynomial.
This is used to perform error detection
on the address, control, and
information fields. The standard CRC-
CCITT polynomial is used in both the
receive and transmit directions:
of the HDLC formatter, or report its
status. HDx parameters in the next
table refer to three parameters, x
automatically deletes all 0’s inserted
by the transmitter.
referring to any of the three HDLC
formatters.
Inter-fra m e tim e fill
An inter-frame time fill condition
occurs when the HDLC block has no
frames to transmit. The device can be
configured to either transmit an idle
stream or flag characters during this
period. The idle stream consists of
binary 1’s in the LAPD protocol: the
number of 1’s can be less than a full
octet. The LAPB protocol, on the other
hand, specifies flag characters to be
inserted between frames.
X16 + X12 + X5 + 1
The HDLC block also provides support
for a non-standard 32 bit CRC (CRC-
32), which may be used instead of the
standard CCITT-CRC. The polynomial
for this is:
X32 + X26 + X23 + X22 + X16 +
X12 + X11 + X10 + X8+ X7 + X5 +
X4 + X2 + X + 1
26
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
Fu n ctio n
b y te
HDx-SRC
Source data for the receive path:
[1:0]: line selection
x=1
x=2
x=3
40
41
42
100
104
108
0 = U
1 = S
2 = A
3 = / (unspecified; not to be used)
[4:2]: burst selection (0 to 7)
[6:5]: channel selection
0 = B1
1 = B2
2 = D
3 = / (unspecified; not to be used)
HD_BREV
43
10C
Bit-reverse data byte (lsb ´ msb) read/ written from/ to the HDLC FIFOs
bit[0] = 1 : bit-reverse data for HDCL1 formatter
bit[1] = 1 : bit-reverse data for HDLC2 formatter
bit[2] = 1 : bit-reverse data for HDLC3 formatter
bit[4] = 1 : bit reversed per block of 2 for D channel transmission through
HDLC1 in transparent mode
bit[5] = 1 : bit reversed per block of 2 for D channel transmission through
HDLC2 in transparent mode
bit[6] = 1 : bit reversed per block of 2 for D channel transmission through
HDLC3 in transparent mode
HDx-TX
x=1
x=2
HDLC packet ready to be transmitted in the current frame
(read only register; the register is updated by and when the HDLC TX-fifo
is active, transmitting data)
44
45
46
110
114
118
x=3
HDx-MODE
HDLC Mode Register (MODE)
This register controls the formatter configuration
= [0, HEN, TXE, RXE, CR32, ITF, FLS, TIC]
HEN : HDLC Protocol Enable
1 : HDLC protocol enabled (data sent LSB first)
0 : HDLC protocol disabled (data sent LSB first)
TXE : Transmitter Enable
x=1
x=2
x=3
10
20
30
40
80
C0
1 : Transmitter activated
0 : Transmitter deactivated
RXE : Receiver Enable
1 : Receiver activated
0 : Receiver deactivated
CR32 : 32 bit CRC Enable
1 : Enable 32 bit CRC (non-standard)
0 : Disable 32 bit CRC
ITF : Inter-frame Time Fill
1 : Continuous 1’s between frames
0 : Flag characters between frames
FLS : Flag sharing
1 : Transmit one flag between frames
0 : Transmit two flags between frames
27
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
Fu n ctio n
b y te
TIC : Transmit Incorrect CRC
1 : Transmit an incorrect CRC field value
0 : Transmit correct CRC field value
HDx-EMODE
HDLC Extended Mode Register (EMODE)
This register controls the configuration of the extended HDLC modes.
= [LPB, CPT, TAIE, RAF1, RAF0, MFLE, MFL1, MFL0]
LPB : Loop-back (at parallel ARM-IO side, NOT at bit-serial GCI side)
1 : Transmit – receive looped back
x=1
x=2
x=3
11
21
31
44
84
C4
0 : Transmit – receive not looped back
CPT : CRC Pass Through
1 : Pass CRC bytes into the data stream
0 : Do not pass CRC bytes into data stream
TAIE : Transmit Address Insertion Enable
1 : Transmit address octets sourced from TA1/ 2
0 : Transmit address octets sourced from data
RAF[1:0] : Receive Address Filter
00 : No filter on receive addresses
01 : Frame accepted if first address octet corresponds to
either RA1/ RAW1 or RA2/ RAW2
10 : Frame accepted if second address octet corresponds to
either RA1/ RAW1 or RA2/ RAW2
11 : Frame accepted if
first address octet corresponds to RA1/ RAW1 and
second address octet corresponds to RA2/ RAW2
MFLE : Minimum Frame Length Check Enable
1 : Minimum frame length check enabled
0 : Minimum frame length check disabled
MFL[1:0] : Minimum Frame Length Check
00 : Only receive frames of 3 bytes or more
01 : Only receive frames of 4 bytes or more
10 : Only receive frames of 5 bytes or more
11 : Only receive frames of 6 bytes or more
HDLC Command Register (CMD)
HDx-CMD
Commands for the formatter are written to this register. Writing a ‘1’ to any
of the bit locations will cause the appropriate action to take place.
= [0, 0, 0, 0, TFT, TFC, RFC, RFB]
x=1
x=2
x=3
12
22
32
48
88
C8
TFT : Transmit Frame Terminator
1 : The next byte to be written to the Transmit FIFO is the last of the frame
TFC : Transmit FIFO Clear
1 : Transmit FIFO is cleared
RFC : Receive FIFO Clear
1 : Receive FIFO is cleared
RFB : Receive Frame Abort
1 : Abort the receive frame
0 : Transmit two flags between frames
28
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
Fu n ctio n
b y te
HDx-SSTAT
HDLC Serial Status Register (SSTAT)
This register contains the current status of the Formatter receive and transmit serial functions.
= [0, 0, 0, 0, SPG, RID, RFL, TIF]
SPG : Serial Port Grant : this bit will have no influence if being reset, because
the it is always granted by hardware construction:
1 : Serial port granted
x=1
x=2
x=3
13
23
33
4C
8C
CC
0 : Serial port has not been granted
RID : Receive Line Idle
1 : Receiving idle characters
0 : Frames or starting flags are being received
RFL : Receiving Flag Characters
1 : Receiving flag characters
0 : Idle/ frame data being received
TIF : Transmit in Frame
1 : Transmitting frame data characters
0 : Transmitting idle/ flag characters
HDx-FSTAT
HDLC Fifo Status Register (FSTAT)
This register contains the current status of the formatter.
= [0, RSB, TLL, TFE, TOU, RLH, RFE, ROU]reset value = 32 hex
RSB : Receive Status Byte
1 : Next byte on receive FIFO is a status byte
0 : Next byte on receive FIFO is a data byte
TLL : Transmit FIFO Level is Low
x=1
x=2
x=3
14
24
34
50
90
D0
1 : Transmit FIFO level is less than its threshold level
0 : Transmit FIFO level is greater than or equal to its threshold level
TFE : Transmit FIFO is Full/ Empty
1 : Transmit FIFO full if TLL=0, empty if TLL=1
0 : Transmit FIFO is neither full nor empty
TOU : Transmit FIFO has Overrun/ Underrun
1 : Transmit FIFO overrun if TLL=0, underrun if TLL=1
0 : Transmit FIFO has neither overrun nor underrun
RLH : Receive FIFO Level is High
1 : Receive FIFO level is greater than or equal to its threshold level
0 : Receive FIFO level is less than its threshold level
RFE : Receive FIFO is Full/ Empty
1 : Receive FIFO full if RLH=1, empty if RLH=0
0 : The receive FIFO is neither full nor empty
ROU : Receive FIFO has Overrun/ Underrun
1 : Receive FIFO overrun if RLH=1, underrun if RLH=0
0 : Receive FIFO has neither overrun nor underrun
threshold level = half of the FIFO depth
HDx-ISTAT
HDLC Interrupt Status Register (ISTAT)
= [TXOK, TXERR, RXOK, RXERR, TXFL, TXFU, RXFH, RXFO]
(see HDLC Interrupt Mask Register (HDx_IMASK))
Holds the current interrupt status;
x=1
x=2
x=3
15
25
35
54
94
D4
Reading this register returns the same value that was read during the last read of HDx_ISERV.
29
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
Fu n ctio n
b y te
HDx-ISRV
HDLC Interrupt Service Register (ISRV)
= [TXOK, TXERR, RXOK, RXERR, TXFL, TXFU, RXFH, RXFO]
(see HDLC Interrupt Mask Register (IMASK))
Reading this register :
returns a value indicating all pending interrupts, and clears the interrupts (ISRV reset to 00hex);
The returned value is stored in HDx-ISTAT for further reading.
HDLC Interrupt Mask Register (IMASK)
= [TXOK, TXERR, RXOK, RXERR, TXFL, TXFU, RXFH, RXFO]
TXOK : Transmit Frame OK
x=1
x=2
x=3
16
26
36
58
98
D8
HDx-IMASK
x=1
x=2
x=3
17
27
37
5C
9C
DC
1 : Frame transmitted OK
0 : No interrupt
TXERR : Transmit Frame Aborted
1 : Transmit frame aborted
0 : No interrupt
RXOK : Receive Frame OK
1 : Frame received OK
0 : No interrupt
RXERR : Receive Frame Error
1 : Frame aborted/ received with CRC error
0 : No interrupt
TXFL : Transmit FIFO low
1 : Transmit FIFO level has fallen below threshold
0 : No interrupt
TXFU : Transmit FIFO Underrun
1 : Transmit FIFO has underrun
0 : No interrupt
RXFH : Receive FIFO High
1 : Receive FIFO level has risen above threshold
0 : No interrupt
RXFO : Receive FIFO Overrun
1 : Receive FIFO has underrun
0 : No interrupt
HDx-FIFO
TX / RX Data
Reading this register pops data off the Receive FIFO, from the current read
address, and writing this register pushes data onto the Transmit FIFO.
Note that writing a ‘1’ to the TFT bit in the HDx_CMD register before writing
the last byte to this register will terminate the last byte in the HDLC frame.
Note that when changing to transparent mode either from reset, or during
normal operation, the first received byte in the RX FIFO should be ignored.
= [D7, D6, D5, D4, D3, D2, D1, D0]
x=1
x=2
x=3
18
28
38
60
A0
E0
HDx-RFBC
Receive Frame Byte Count (RFBC)
The contents of this register are valid after an RXOK/ RXERR interrupt. The value
in this register corresponds to the number of receive frame bytes placed into the
Receive FIFO. This value includes CRC bytes if CPT=1, but does not include the
Receive Status Byte placed into the Receive FIFO immediately following the frame data.
= [C7, C6, C5, C4, C3, C2, C1, C0] (modulo 256)
x=1
x=2
x=3
19
29
39
64
A4
64
30
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
Fu n ctio n
b y te
HDx-TA1
Transmit Address 1 (TA1)
This register contains the first address octet for outgoing HDLC frames.
This register value will only be used as the first address octet if the TAIE bit in
the HDx_EMODE register is set to ‘1’.
x=1
x=2
x=3
1A
2A
3A
68
A8
68
= [T17, T16, T15, T14, T13, T12, T11, T10]
HDx-TA2
Transmit Address 2 (TA2)
This register contains the second address octet for outgoing HDLC frames.
This register value will only be used as the second address octet if the TAIE bit
in the HDx_EMODE register is set to ‘1’.
x=1
x=2
x=3
1B
2B
3B
6C
AC
EC
= [T27, T26, T25, T24, T23, T22, T21, T20]
HDx-RAW1
Receive Address Wildcard 1 (RAW1)
This register contains a ‘wildcard’ pattern for use by the receive address register RA1.
Any bits set to ‘1’ in this register will not be used in the comparison with an
address octet.
= [RW17, RW16, RW15, RW14, RW13, RW12, RW11, RW10]
Receive Address Wildcard 2 (RAW2)
x=1
x=2
x=3
HDx-RAW2
1C
2C
3C
70
B0
F0
This register contains a ‘wildcard’ pattern for use by the receive address register RA2.
Any bits set to ‘1’ in this register will not be used in the comparison with an
address octet.
= [RW27, RW26, RW25, RW24, RW23, RW22, RW21, RW20]
Receive Address 1 (RA1)
x=1
x=2
x=3
1D
2D
3D
74
B4
F4
HDx-RA1
This register contains a value to be used in the address matching circuitry for
received HDLC frames. The RAF bits in the HDx_EMODE register control the
operation of the address matching circuitry.
= [RA17, RA16, RA15, RA14, RA13, RA12, RA11, RA10]
Receive Address 2 (RA2)
x=1
x=2
x=3
1E
2E
3E
78
B8
F8
HDx-RA2
This register contains a value to be used in the address matching circuitry for
received HDLC frames. The RAF bits in the HDx_EMODE register control the
operation of the address matching circuitry.
x=1
x=2
x=3
1F
2F
3F
7C
BC
FC
= [RA27, RA26, RA25, RA24, RA23, RA22, RA21, RA20]
Notes:
Receive Status Byte = [0 , 0 , 0 , RAB ,
CRC/ ERR , PAD2 , PAD1 , PAD0]
On the reception of a frame, a receive
status byte is appended to the frame
data in the FIFO. This status byte
indicates how successfully the frame
was received. The status byte can be
identified in the receive data stream
either by examining the RSB status bit
of the HDx_FSTAT register, or by
examining the RFBC register value
after an RXOK/ RXERR interrupt has
occurred.
RAB : Receive Abort
1 : Receive frame aborted
0 : Receive frame not aborted
CRC/ ERR : Receive CRC Error
1 : Receive CRC Error
0 : No receive CRC Error
PAD[2:0] : 3 bit number
indicating the number of
padding bits added to the final
receive character in the case of
non octet aligned data.
31
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Clock g enera tion
input clock; in this case, the user
should set this parameter to divide
the clock by two.
activity detection circuit, triggering the
ARM interrupt (FIQ or IRQ). Therefore,
before going into power-down, the
software must take care that the
appropriate interrupt input source is
enabled (not masked); otherwise only
a power reset will allow to start-up the
ARM again. The bits CLK_2[7..4] will
be reset automatically by the
A master clock oscillator, based on an
external crystal of 15.36 MHz is
provided. This can provide an output
at the crystal frequency for use by the
ISDN chip (INTT or INTQ). It therefore
offers better than 100-ppm accuracy ;
the external crystal is specified to
50-ppm accuracy.
The processor clock (ARM clock) is
also a programmable clock derived
from the 15.36 MHz input clock. It is
user-programmable via the control
register CLK_2 from 15.36 MHz in
even integer division steps. (15.36
MHz, 15.36/ 2 MHz, 15.36/ 4 MHz,
15.36/ 6 MHz, …).
hardware activity detection.
Note: the oscillator pins may also
be controlled from an external master
clock. In that case, the external master
clock is connected to the pin XTAL1,
whereas pin XTAL2 is connected
to GND.
Notice that during ARM power-down,
all other hardware units (HDLC,
UART,..) and the GCI interfaces will
keep running.
In addition, the ARM clock can
completely be disabled, bringing the
ARM in complete power-down mode.
CPU clock control p rotection
In order to avoid a disabling of the
clocks by accident, and thus causing
a lock-up, a four-bit word must be
written in specific register fields
(CLK_1[7..4] and CLK_2[7..4]).
After reset, the clock CKOUT and the
ARM clock are set to the maximum
frequency and are not disabled:
One clock output (CKOUT) with a
programmable division ratio from the
15.36 MHz input clock, is provided
for use by any external peripheral
function. It is user-programmable via
the control register CLK_1 from 15.36
MHz in even integer division steps.
(15.36 MHz, 15.36/ 2 MHz,
15.36/ 4 MHz, 15.36/ 6 MHz, …).
The clock output can also be disabled;
when the clock is disabled, it remains
constant high.
Typically, CKOUT can be used to
drive the 15.36MHz input clock of the
INTT/ INTQ and therefore this will be
the default start-up value. An MTC-
20172 device in a TE application,
for example, requires a 7.68MHz
CKOUT
= 15.36 MHz (CLK_1=0)
ARM clock = 15.36 MHz (CLK_2=0)
CKOUT must be enabled by software
by writing any value different from
“1001” to CLK_1[7..4]; at the same
time the value written in CLK_1[3..0]
defines the frequency used at restart.
Furthermore, the clock generator will
generate an input clock for the
integrated UART block. This clock will
be derived from the 15.36 MHz input
clock and will have a fixed frequency
of 3.6864 MHz. The UART can
generate different baud rates based
on that input clock.
For the ARM clock, this is slightly
different. It is disabled under software
control by writing the appropriate
value to register CLK_2; this also
defines the start-up frequency.
However, enabling is done by an
Reg ister ta b le :
N a m e
Ad d re ss
Fu n ctio n
w o rd b y te
CLK_1 [3..0]
CLK_1 [7..4]
91
244
Integer representing the CKOUT output clock frequency
CKOUT = 15.36 MHz / (2 * CLK_1)
Remarks:
CLK_1[3..0] = 0 is translated into a division by one
the max division factor is CLK_1[3..1]=15
CKOUT can be disabled by setting bits CLK_1[7..4] == “1001”
32
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
Fu n ctio n
w o rd b y te
CLK_2 [3..0]
CLK_2 [7..4]
92
248
Integer representing the ARM clock frequency
ARM clock = 15.36 MHz / (2 * CK2)
Remarks:
CLK_2[3..0] = 0 is translated into a division by one
the max division factor is CLK_2[3..0]=15
CLK2 can be disabled by setting bits CLK_2[7..4] == “1001”
TBD
CLK_3
93
24C
bit [0] : DPLL status (read only)
0 = internal gci clocks not synchronized with
the extern reference; dpll is tracking
1 = internal gci clocks synchronized
bit [1] : UART clock disable
bit [3:2]: APB clock division factor
0 = 15.36 Mhz/ 4 (max.speed)
1 = 15.36 Mhz/ 8
2 = 15.36 Mhz/ 16
3 = 15.36 Mhz/ 32
The ARM7 TDMI a nd its interfa ces
ASB: Advanced System BusAsbClock:
i.e. ARM clock CLK2 , (user
programmable frequency)
APB: Advanced Peripheral Bus
ApbClock : fixed to Xtal/ 4
Ram
256x32
Ram itf
Dedicated
Logic
ASB
APB
APB
bridge
ARM
The ARM processor is configured to
operate in ‘Little-Endian’ mode when
treating the bytes in memory. The
ARM core hardware decides whether
an 8-bit (byte b_0), 16-bit (bytes =
b_1, b_0 with b_0=LSB byte) or 32-bit
word (bytes b_3, b_2, b_1, b_0 with
b_0=LSB byte) is to be accessed.
Dedicated Logic registers are 8-bit
wide, so the ARM will only request for
a 8-bit access and the APBBridge will
only support Single Byte access. The
physical address of each hardware
register lies on a word boundary (NB.
ARM Ltd. has chosen to call a 32-bit
entity a ‘word’. This convention is
retained in this document).
wait
Memory
interface
Wait Controller
External memories
Fig ure 1 4 : The ARM7 TDMI Processor Core a nd its Interfa ces
The External Memory interface can be
set to operate in one of four possible
33
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
modes. Depending on the mode, 16-
bit and 32-bit accesses will be
require at most 2 cycles, due to the 2
cycle read-modify-write sequence that
is automatically generated by the
internal memory interface. In order to
reduce the processor wait cycles, the
FSM will only introduce a wait cycle if
the previous internal memory access
operation is not fully completed (this is
identical to the APB bridge case). This
can only occur when a 8- or 16-bit
write access is scheduled just after
another 8- or 16-bit write access to
the same on chip memory. (Mostly,
the ARM will not execute two write
operations successively, but will fetch
a new instruction in the mean time).
• MC7..0 : 8 Memory control output
signals, of which the function
depends on the selected
MemoryAccess mode (e.g. MC7
might be the lsb of the address bits)
automatically transformed into one or
two consecutive Two Byte accesses, or
two or four consecutive Single Byte
accesses respectively. The internal
memory allows direct access to 1-, 2-
or 4-byte words.
• MM1, MM0: two MemoryAccess
configuration bits
Depending on the Memory Access
mode, up to six blocks of 0.5Mbytes
can be accessed = three Mbytes in
total; the selection of the appropriate
block is done with the control signals
MC7..0, performing the function of
‘chip select’ signals (see also table
further on).
APB b rid g e
The APB clock is fixed to 15.36 MHz
/ 4 = 3.84 MHz for power
optimization. However, depending on
the ASB clock (= processor clock), the
APB clock will be modulated in order
to minimize the cycles needed for the
read and write operations, thus
maximizing processor throughput.
Processor wait cycles will only be
introduced by the hardware controller
according to the following rules:
The MemoryAccess input pins must be
strapped to VDD/ VSS in order to select
one of four possible access modes. The
different modes allow interfaces to
simple and common byte-oriented
external memories, or more advanced
two-byte-oriented memories. Note
however that the selected
MemoryAccess mode is valid for each
block and all external memories : each
block in the MTC-20280 address space
is handled in the same way.
Ex terna l m em ory interfa ce
The external memory interface consist of:
•
A[18:1] and MC7 : 19 bits address bus
READ operations: no wait cycle
• DQ[15:0]: 16 bits data bus
allowing SingleByte or TwoByte
transfers; the MSB of the data bus
DQ[15] may have a special
function depending on the selected
MemoryAccess configuration
WRITE operations: two ASB cycles are
needed; wait cycles will be introduced
depending on an internal finite state-
machine. If the previous WRITE
operation is completed, no wait cycle
is needed. One wait cycle will be
introduced to wait until the end of the
previous operation if needed. (This
situation seldom occurs in practice,
due to the processor executing an
intermediate READ cycle to fetch the
next instruction in most cases).
• NWR,NOE: two control signals with
fixed function
Basically, the following four modes
are supported by the MTC-20280:
Ca se
MM1
MM0
Descrip tion
a:
0
0
WordAccess Disabled
(only single-byte access possible)
WordAccess Enabled with
ChipSelect/ Low/ Up control outputs
WordAccess Enabled with
ChipSelect/ Nbyte/ Addr0 control outputs
WordAccess Enabled with
b:
c:
d:
1
1
0
1
0
1
On chip m em ory
A RAM of 1kbyte with zero wait-state
access is foreseen on chip. Read
access is performed in one single
cycle, for 8-bit, 16-bit as 32-bit word
accesses. Writing 32 bit wide words
is always done in one cycle. Write
accesses of 8-bit and 16-bit words
ChipSelectUp/ ChipSelectLow control outputs
34
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
When the WordAccess Mode is
disabled, the MTC-20280 Memory
interface will always convert the 8-,
16- or 32-bit access of the ARM into
one, two or four consecutive
The following memory types and
configurations are supported:
case c: (see Figure 17) external
memory with integrated
single/ double byte access
mode (controlled by
case a: (see Figure 15)
normal byte-oriented external
memory (controlled by
CS,OE,WE,BYTE,A0) (e.g.
AMD or INTEL memories)
addressed in SingleByte or
TwoByte access (WordAccess
Enabled).
SingleByte external accesses.
CS,OE,WE) one memory
allocated to store both LSB
and MSBytes addressed in
SingleByte access mode only
(WordAccess Disabled).
When the WordAccess Mode is
enabled, the MTC-20280 memory
interface will decide which type of
access is performed. TwoByte (using the
full 16bit data bus DQ[15:0]) or
SingleByte mode (using only eight bits
of the 16bit data bus). One SingleByte
access for an 8-bit ARM access, and
one or two TwoByte accesses for 16-
and 32-bit ARM access. The alignment
of the bytes onto the data bus depends
on the selected mode, as shown below
in the table.
case d: (see Figure 18) normal byte-
oriented external memory
(controlled by CS,OE,WE)
with two memories allocated
(one for LSByte, one for
case b: (see Figure 16)
normal byte-oriented external
memory (controlled by
CS,OE,WE) two memories
allocated (one for LSByte, one
for MSByte) addressed in
SingleByte or TwoByte access
(WordAccess Enabled)
requires glue logic for chip-
select signal generation in
between the MTC-20280 and
the memory.
MSByte) addressed in
SingleByte or TwoByte access
(WordAccess Enabled) no
glue logic for chip-select
signal generation in between
the MTC-20280 and the
memory needed.
The three types of WordAccess Mode
Enabled allow control of different
types of external memory by the MTC-
20280, each of them connected and
controlled in a different way.
Therefore, the meaning of the control
signals MC7..0 that are sent to the
external memory will depend on the
selected type.
Figure 1 5 : MTC-2 0 2 8 0 - Ex terna l Mem ory Connections for ‘Ca se a ’.
35
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Figure 1 6 : MTC-2 0 2 8 0 - Ex terna l Mem ory Connections for ‘Ca se b’.
Figure 1 7 : MTC-2 0 2 8 0 - Ex terna l Mem ory Connections for ‘Ca se c’.
Add17..0
Data7..0
CS
OE
DQ15..8
WE
MC1,3,7,5 (nCsUp)
EXT MEM (MSB)
A18..1
DQ7..0
NOE
NWR
Add17..0
Data7..0
CS
MC0, 2,6,4 (nCsLow)
ITCB
PIN (function)
OE
WE
EXT MEM (LSB)
Figure 1 8 : MTC-2 0 2 8 0 - Ex terna l Mem ory Connections for ‘Ca se d’.
36
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
The output pins have the following logical meaning dependent on the mode:
SingleByte Tw oByte
MM NW R NOE MC0 MC1 MC2 MC3 MC4 MC5 MC6 MC7
A
DQ
DQ
DQ
DQ
1: 0
18:1 15:8 7:0
15:8 7:0
a
0 0 nwr
1 1 nwr
1 0 nwr
noe ncs0 ncs1 ncs2 ncs3 ncs4 ncs5
x
a0
addr pio
18:1
b_i
--
--
b
noe ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 nup
nlow addr b_1
18:1 b_3
b_0
b_2
b_i
b_1
b_3
b_1
b_3
b_1
b_3
b_0
b_2
b_0
b_2
b_0
b_2
c
noe ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 nbyte a0* addr
18:1
noe ncl0 ncu0 ncl1 ncu1 ncl3 ncu3 ncl2 ncu2 addr b_1
18:1 b_3
z
d 0
1
nwr
b_0
b_2
Meaning of the codes:
ncs<i>: active low chip select for block
<i> in the memory map (both
LSByte and MSByte)
ncl<i> : active low chip select for block
<i> in the memory map (only
LSByte)
ncu<i> : active low chip select for block
<i> in the memory map (only
MSByte)
nlow : active low indication that lower
byte is transferred
nup : active low indication that
upper byte is transferred
nwr : active low indication for write
enable
noe : active low indication for read
enable
nbyte : active low indication for
SingleByte transfer selection,
TwoByte (nbyte=1)
Note that in case d, each chip select
output must be split into two signals:
one for the lower byte and one for the
upper byte. Re-use of pins MC6 and
MC7 allows the user to split the select
signals for the lower four blocks of the
memory map; blocks 5 and 6 of the
external memory map will not be
addressable. Instead, one obtains the
advantage that no glue logic is
SingleByte selected by the memory
interface controller:
alignment of any byte_i to be
transferred to/ from external memory
at a given time
TwoByte selected by the memory
interface controller:
alignment of any byte_i to be
transferred to/ from external memory
at a given time
needed to control the chip select pins
of the external memories.
-- :
x :
non-occurring situation
means the output is not used in
this mode; it will not be
W a it sta te(s) p er m em ory b lock :
For each of the six external blocks,
wait cycles can be specified in order
to optimize the external components
configuration. The registers
CHIP_WTC1, 2 and 3 allow up to 15
wait cycles to be inserted per block;
the default value after reset is 15 wait
cycles for each block.
floating but set to VDD
means the bidirectional IO is
not used in this mode; it will be
set to tri-state (input)
z :
pio : pins used as parallel IO: ports
DQ15..12=PE3..0 and
or SingleByte (nbyte=0)
DQ11..8=PF3..0
a0 : LSB of address
The following logical relationship must
hold between the signals:
a0* : the LSB of the address will not be
used and be put in tri-state, if and
only if a TwoByte access is
selected; this is done to be
compatible with AMD memories,
for which DQ15 and a0 must
be connected to the same pin
(ref [13])
nlow = (nbyte + a0)*not(nbyte);
nup
= (nbyte +
not(a0))*not(nbyte);
ncl<i> = (ncs<i> + nlow);
ncu<i> = (ncs<i> + nup);
37
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Mem ory a ccess tim ing .
The drawing below shows the timing
relationship of the memory interface
for a 2-byte access, making use of the
Nbyte control signal:
• Timing compatible with standard
SRAM and Flash, NCS controlled.
• When no wait state is specified, the
NCS strobe correspond to the low
level of the internal ARM clock; the
width of the low and the high level
of NCS is symetric and correspond
to the selected ARM clock speed.
• When wait states are specified, an
equivalent number of ARM cycles is
added to the external access timing;
so ONLY the low level of NCS is
extended (as required for slower
SRAMs). It’s always possible to keep
the levels symetric if neede by
instead of placing wait states,
decreasing the ARM clock
NBYTE/NUP/NLOW
frequency.
NBYTE/NUP/NLOW
Figure 1 9 : Mem ory Interfa ce Signa ls – Rea d a nd Write Cycles
38
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Mem ory sp a ce org a nisa tion
The most significant bits of the 32-bit
internal ARM address word, are
decoded to split the memory space
into 8 blocks assigned as follows:
fast memory’ and the ‘APB memory’ a
full length page of 0x1000 0000 bytes
is allocated, although the current MTC-
20280 design uses only 0x400 and
0x100 bytes respectively for these
memory banks. This is done to ensure
backward compatibility in future
versions of the MTC-2028x controller
family.
LSB of the address being zero (from
0xE000 0000 up to 0xE0000 03FC).
At reset the ARM will start-up at the
fixed boot address 0x0000 0000,
accessing the external block 0.
0: external block 0
1: external block 1
2: external block 2
3: external block 3
4: external block 4
5: external block 5
6: internal fast memory
7: APB bus
In order to allow re-definition of the
code in external block 0 (e.g. for
reprogramming of the interrupt
vectors), the addresses of block 0 can
be swapped with block 3 under
software control. This is done as soon
as the bit CHIP_CFG[7]=1 is set. At
reset, the blocks are not swapped.
Data in the ‘internal RAM’ can be
either a byte, half-word or word; their
addresses are LSB aligned, making
use of the 10 LSB of the ARM address
bus (from 0xC000 0000 up to
When the ARM accesses one of the
external blocks <i>, the MTC-20280
will bring the corresponding chip select
control signal nCS<i> active low. Note
that there are no gaps between
0xC000 03FF). All data of the ‘APB
memory’ are bytes; their addresses
are ‘word-aligned’ (LSB+2bits) such
that the data byte is always LSB
aligned onto the data bus. The ARM
address bits [9..2] are used to
addresses of successive external
memory blocks. For both the ‘internal
address the full memory map, the 2
Figure 2 0 : ARM Address Spa ce Orga nisa tion / Mem ory-m a p
39
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Reg ister ta b le:
N a m e
Ad d re ss
Fu n ctio n
w o rd b y te
CHIP_CFG[7]
01
04
05
06
4
Swap addresses for external memory block 0 and 3 (1 bit):
0=unswapped (default at reset, address 00 in block 0),
1=swapped (address 00 in block 3)
Wait cycles for external memory blocks (default 15: slow at reset)
bit[3:0]: for memory block 0
bit[7:4]: for memory block 1
Wait cycles for external memory blocks (default 15: slow at reset)
bit[3:0]: for memory block 2
CHIP_WTC1
CHIP_WTC2
CHIP_WTC3
10
14
18
bit[7:4]: for memory block 3
Wait cycles for external memory blocks (default 15: slow at reset)
bit[3:0]: for memory block 4
bit[7:4]: for memory block 5
Interrup ts
Each source can be masked by
(STR) interrupt status can be checked.
The chip contains several interrupt sources.
These sources are split into two types of
interrupts: a fast (NFIQ) and normal (NIRQ)
interrupt. Priority within one class is
resolved in software. Interrupts are
controlled by writing to / reading from a
set of control/ status registers: IRQ1_* for
NFIQ, and IRQ2_* for NIRQ.
clearing a bit in a control register
(ENCLR), or unmasked by setting a bit
(ENSET). At reset, all sources are
masked by default. All ‘interrupt
request’ bits from the various sources
are readable in a register, and each
of them can be cleared. Both the
masked (ST) and the unmasked ‘raw’
As soon as a non-masked interrupt
occurs, the NFIQ/ NIRQ pin of the
ARM goes active low. The interrupt
can be cleared by writing to the
acknowledge control register (ACK). If
all interrupts in irqStatus are cleared,
the NFIQ/ NIRQ pin goes inactive
high again.
Reg ister ta b le:
N a m e
Ad d re ss
w o rd
Fu n ctio n
b y te
IRQ1_ST
94 (R only) 250
95 (R only) 254
96 (R only) 258
97 (W only) 25C
98 (W only) 260
99 (W only) 264
9A (R only) 268
9B (R only) 26C
9C (R only) 270
Interrupt status for sources after masking with IRQ1_EN
( IRQ1_ST(i)=1 if interrupt(i) is active after masking )
Interrupt status for sources without masking
IRQ1_STR
IRQ1_EN
( IRQ1_STR(i)=1 if interrupt(i) is active )
Interrupt mask register used to generate IRQ1_ST
( IRQ1_EN(i)=1 if interrupt(i) must not be masked )
Control register to unmask an interrupt
( IRQ1_ENSET(i)=1 results in IRQ1_EN(i)=1, i.e. unmask interrupt(i) )
Control register to mask an interrupt
( IRQ1_ENCLR(i)=1 results in IRQ1_EN(i)=0, i.e. mask interrupt(i) )
Control register to clear an interrupt
( IRQ1_ACK(i)=1 resets the interrupt(i) detection in irq(Raw)Status(i) )
Interrupt status for sources after masking with IRQ2_EN
( IRQ2_ST(i)=1 if interrupt(i) is active after masking )
Interrupt status for sources without masking
IRQ1_ENSET
IRQ1_ENCLR
IRQ1_ACK
IRQ2_ST
IRQ2_STR
IRQ2_EN
( IRQ2_STR(i)=1 if interrupt(i) is active )
Interrupt mask register used to generate IRQ2_ST
( IRQ2_EN(i)=1 if interrupt(i) must not be masked )
40
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
Fu n ctio n
b y te
IRQ2_ENSET
IRQ2_ENCLR
IRQ2_ACK
9D (W only) 274
9E (W only) 278
9F (W only) 27C
Control register to unmask an interrupt
( IRQ2_ENSET(i)=1 results in IRQ2_EN(i)=1, i.e. unmask interrupt(i) )
Control register to mask an interrupt
( IRQ2_ENCLR(i)=1 results in IRQ2_EN(i)=0, i.e. mask interrupt(i) )
Control register to clear an interrupt
( IRQ2_ACK(i)=1 resets the interrupt(i) detection in irq(Raw)Status(i) )
Interrup t m a p p ing
NFIQ Interrupt sources ( bit k=0..7 of registers IRQ1_*[ k ] with
k=0=LSB )
NIRQ Interrupt sources ( bit k=0..7 of registers IRQ2_*[ k ] with
k=0=LSB )
0 : GCI
interrupt generated each time a new GCI frame starts 0 : UART
interrupt generated by UART (see module
description to know various sources of interrupts).
The UART interrupt register can be read to
determine which interrupt has occurred.
Parallel IO B interrupt is generated as soon as one
of the input bits is toggled
1 : HDLC1 formatter interrupt generated by HDLC1 formatter
(see module description for the various sources of
interrupts). The HDLC interrupt registers can be
read to determine which interrupt has occurred.
2 : HDLC2 formatter idem as for HDLC1
3 : HDLC3 formatter idem as for HDLC1
4 : Timer1 Timer 1 reaches the limit
1 : PB
2 : External
Rising / falling edge or IRQ high/ low level
detection on the MTC-20280 pin IT
5 : PA
Parallel IO A interrupt is generated as soon as one of 3 : C/ I
the input bits is toggled (b)
Activity detected on one activity of the C/ I
channels not detection masked. The GCI
interrupt register can be read to determine
which channel is concerned.
6 : PF
Parallel IO F [ only applicable if MM[1,0]=
00 ] interrupt is generated as soon as one of the
input bits is toggled
4 : Timer2 Timer 2 reaches the limit
7 : NA
5 : PC
6 : PD
7 : PE
Parallel IO C. Interrupt is generated as soon as
one of the input bits is toggled
Parallel IO D. Interrupt is generated as soon as
one of the input bits is toggled
Parallel IO E [ only applicable if MM[1,0]=
00 ]. Interrupt is generated as soon as one of the
input bits is toggled
Ex terna l interrup t
The external interrupt can be made edge or
level sensitive by writing the appropriate
value to the following control register :
Reg ister ta b le
N a m e
Ad d re ss
w o rd
01
Fu n ctio n
Type of external interrupt to detect (2bit):
b y te
4
CHIP_CFG
41
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
UART Interfa ce
The chip contains a UART (Universal
Asynchronous Receiver/ Transmitter)
compatible with the popular “16550”
family, which is fully programmable by
the ARM CPU.
Fea tures
Word lengths from 5 to 8 bits
Parity bit : even, odd or forced to a
defined state
Modem control signals RTS and CTS
available
Two, 16 bytes FIFOs, one for transmit
and one for receive
One or two stop bits
Programmable Baud rate generator
(19.2 kbps, 57.6 kbps, 115.2 kbps,
230.4 kbps, …)
Interrupt generated from any one of 10
sources of the UART module itself
Ba u d ra te g e n e ra to r
Ba ud Ra te (b p s)
2400
4800
9600
19200
Division Fa ctor (DL)
The baud rate is specified by the
divisor register DL (DLM = MSB; DLL =
LSB, see Register table below) in the
following way:
96
48
24
12
6
38400
baud rate = ( 230400 / DL ) bps
57600
4
115200
2
Reg ister ta b le
N a m e
Ad d re ss
w o rd
50 (R only)
[ if DLAB=0 ]
Fu n ctio n
b y te
140
UART_RBR
Receiver Buffer Register,
This register is updated from the receiver shift register at the end of a
receive sequence.
UART_THR
UART_IER
50 (W only) 140
[ if DLAB=0 ]
Transmitter Holding Register,
Data is held in this register until transferred to the transmitter shift register
Interrupt Enable Register
51
144
[ if DLAB=0 ]
= [x, x, x, x, EDSSI, ELSI, ETBEI, ERBFI]
EDSSI : Enable Modem Status Interrupt
When set (‘1’), an UART interrupt is generated if D0, D1, D2, or D3 of the
Modem Status Register become set.
ELSI : Enable Rx Status Interrupt
When set (‘1’), an interrupt is generated if D1, D2, D3 or D4 of the Line
Status Register become set.
ETBEI : Enable Tx Holding Register Empty Interrupt
When set (‘1’), an interrupt is generated if THRE=1 or the Transmitting
Holding Register is empty.
ERBFI Enable Receiver Buffer Register
When set (‘1’), an interrupt is generated if the Receive Buffer contains data.
42
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
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Fu n ctio n
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UART_IIR
52 (R only) 148
Interrupt Identification Register
= [FIFOE, FIFOE, 0, 0, ID2, ID1, ID0, NINT]
FIFOE
Returns 1 if FIFOs enable, otherwise 0
ID[2:0] : Interrupt ID
0 : Modem status. Interrupt cleared when reading the modem status register
1 : Transmitter holding register empty. Interrupt cleared when reading this
register or when writing to the transmitter holding register
2 : Receive Data available or Rx FIFO trigger. Interrupt cleared when reading
receive buffer register
3 : Receiver line status. Interrupt cleared when reading the line status register
4 : /
5 : /
6 : Character timeout indication. Interrupt cleared when reading receive buffer register
7 : /
NINT
Interrupt pending, active low
Notes:
Receive timeout interrupt occurs if all the following apply:
- there is at least one character in the FIFO
- the most recent character was received longer than 4 character periods ago (inclusive
of all start, parity, and stop bits)
- the most recent CPU read of the FIFO was longer than 4 character periods ago
The timeout timer is restarted on receipt of a new byte from the input shift register, or on
a CPU read from the Rx FIFO.
TX FIFO interrupt occurs when Tx FIFO is empty. This interrupt will be delayed
one character period minus the last stop bit period whenever; THRE=1 and there have
not been at least 2 bytes in the Tx FIFO at the same time since the last time THRE=1. If
the Tx interrupt is enabled, setting bit 0 of the FCR will generate an immediate interrupt.
If the FIFOs are enabled and at least one of the active bits in IER is disabled, then the
UART will operate in the FIFO polled mode. Since the Tx and Rx paths are controlled
separately, either one or both can be in the polled mode. The application software
should check Tx and Rx status using the LSR.
UART_FCR
52 (W only) 148
FIFO Control Register
= [RFTL1, RFTL0, x,x, DMA1, CLRT, CLRR, FIFOE]
RFTL[1:0] : RX FIFO trigger level
Defines RX FIFO trigger level in number of bytes
00 : 01 bytes
01 : 04 bytes
10 : 08 bytes
11 : 14 bytes
DMA1
Set DMA mode 1. In MTC-20280 configuration, no DMA support is provided.
CLRT : Clear TX FIFO
CLRR : Clear RX FIFO
43
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
Fu n ctio n
b y te
FIFOE
Enable FIFOs; when the FIFOs are enabled or disabled, both Rx and Tx FIFOs are
reset. This bit must be a 1 for any of the other bits in the register to have any effect.
Line Control Register
UART_LCR
53
14C
= [DLAB, SB, SP, EPS, PEN, STB, WLS1, WLS0]
DLAB : Divisor Latch Access Bit
When clear ‘0’, Receive and Transmitter Registers are read/ written address 50
and IER register at address 51. When set ‘1’, Divisor Latch LS is read/ written at
address 50 and Divisor Latch MS read/ written at address 51.
SB : Set Break
When set ‘1’, TXD signal is forced into the ‘0’ state
SP : Stick Parity
When set ‘1’, parity bit is forced into a defined state, dependent upon state
of EPS, PEN :
If EPS=’1’ & PEN=’1’ parity bit is set and checked = ‘0’
If EPS=’0’ & PEN=’1’ parity bit is set and checked = ‘1’
EPS : Even Parity Select
When set ‘1’ and PEN = ‘1’ an even number of ones is sent and checked.
When clear ‘0’ and PEN = ‘1’ an odd number of ones is sent and checked.
PEN : Parity Enable
When set to ‘1’, parity is transmitted and checked. Parity bit is added after the data field
and before the STOP bits. When clear ‘0’ parity is neither transmitted nor checked.
STB : Number of STOP bits
When set ‘1’ two STOP bits are added after each character is sent, except if
character length is 5, then 1_ STOP bits are added. When clear ‘0’ one STOP
bit is always added. Only the transmit STOP bits are programmable, the
receiver stage only expects one STOP bit irrespective of the state of STB.
WLS[1:0] : Word Length Select
Transmitted and received character size defined as follow:
00 = 5 bit
01 = 6 bit
10 = 7 bit
11 = 8 bit
UART_MCR
54
150
Modem Control Register
= [X, X, X, LOOP, OUT2, OUT1, RTS, DTR]
LOOP : Loop back mode
When set ‘1’ the following conditions are implemented: TXD is forced to ‘1’
RXD is disconnected from the Rx input shift register
the Rx input shift register is connected to the Tx output shift register
the modem status signals are disconnected
the modem control signals are connected to modem status inputs
OUT[2:1]
Not used
RTS
Control the state of the corresponding output, even in loop mode.
DTR
Control the state of the corresponding output, even in loop mode.
44
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
55
Fu n ctio n
b y te
154
UART_LSR
Line Status Register
= [FIFOERR, TEMT, THRE, BI, FE, PE, OE, DR]
FIFOERR : RX Data Error in FIFO
This bit is set to 1 when there is at least one PE, FE, or BI in the RX FIFO. It is cleared
by a read from the LSR register, if there are no subsequent errors in the FIFO.
TEMT : Transmitter Empty
If the FIFOs are disabled, this bit is set to ‘1’ whenever the transmitter holding
register and the transmitter shift register are empty. If the FIFOs are enabled,
this bit is set whenever the TX FIFO and the transmitter shift register are empty.
In both cases, this bit is cleared when a byte is written to the TX data channel.
THRE : Transmitter Holding Register Empty
If the FIFOs are disabled, this bit is set to ‘1’ whenever the transmitter holding
register is empty and ready to accept new data, this bit is cleared when the
data is transferred to the transmitter shift register. If the FIFOs are enabled, this
bit is set to ‘1’ whenever the TX FIFO is empty. It is cleared when at least one
byte is written to the TX FIFO.
BI : Break Interrupt
If the FIFOs are disabled, this bit is set whenever the RXD is held in the 0 state
for more than a transmission time (START bit + DATA bits + PARITY + STOP
bits). BI is reset by the CPU reading this register. If the FIFOs are enabled, this
error is associated with the corresponding character in the FIFO. The error is
flagged when this byte is at the top of the FIFO. When break occurs, only one
zero character is loaded into the FIFO. The next character transfer is enabled
when RXD goes into the marking state and receives the next valid start bit.
FE : Framing Error
If the FIFOs are disabled, this bit is set if the received data did not have a valid STOP
bit, FE is reset by the CPU reading this register. If the FIFOs are enabled, the state of
this bit is revealed when the byte it refers to is at the top of the FIFO.
PE : Parity Error
If the FIFOs are disabled, this bit is set if the received data does not have a valid
parity bit, PE is reset by the CPU reading this register. If the FIFOs are enabled, the
state of this bit is revealed when the byte it refers to is at the top of the FIFO
OE : Overrun Error
If the FIFOs are disabled, this bit is set if the receive buffer was not read by the
CPU before new data from the receiver shift register overwrote previous
contents. OE is cleared when the CPU reads this register. If the FIFOs are
enabled, an overrun error occurs when the RX FIFO is full and the RX shift
register becomes full. OE is set as soon as this happens. The character in the
shift register is then overwritten, but is not transferred to the FIFO.
DR : Data Ready
This bit is set whenever the receive buffer is full, or by a byte being transferred
into the FIFO. DR is cleared by the CPU reading the receive buffer or by
reading all of the FIFO bytes. This bit is also cleared whenever the FIFO enable
bit is changed.
45
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
Ad d re ss
w o rd
56
Fu n ctio n
b y te
158
UART_MSR
Modem Status Register
= [DCD, RI, DSR, CTS, DDCD, TERI, DDSR, DCTS]
DCD : Data Carry Detect
When Loop = ‘0’ this is the input signal DCD
When Loop = ‘1’ this is equal to OUT2 (not used)
RI
When Loop = ‘0’ this is the input signal RI
When Loop = ‘1’ this is equal to OUT1 (not used)
DSR : Data Set Ready
When Loop = ‘0’ this is the input signal DSR
When Loop = ‘1’ this is equal to DTR
CTS : Clear To Send
When Loop = ‘0’ this is the input signal CTS
When Loop = ‘1’ this is equal to RTS
DDCD : Delta Data Carry Detect
This bit is set (‘1’) if the state of DSR has changed since this register was last read.
TERI : Trailing Edge Ring Indicator
This bit is set if the RI input changes from ‘1’ to ‘0’ since this register was last read.
DDSR : Delta Data Set Ready
This bit is set (‘1’) if the state of DSR has changed since this register was last read.
DCTS : Delta Clear to Send
This bit is set (‘1’) if the state of CTS has changed since this register was last read.
Scratch Register
UART_SCR
57
15C
General-purpose read/ write register, undefined after reset.
Divisor Latch , MSB and LSB for baud-rate control
(see table)
UART_DLM
UART_DLL
51
50
144
140
(if DLAB=1)
After reset DLM,DLL are undefined.
Pa ra llel I/ O p orts
Four times 4-bit bidirectional I/ O ports
are provided (PA[3..0], PB[3..0],
PC[3..0], PD[3..0]) to allow
additional, user-defined functions. The
application software can define the
access direction of any of the four pins
and have a total visibility of the pin
activity (read and write access). One
interrupt signal is generated per
parallel I/ O source.
In case the WordAccess of the
become irrelevant and no interrupt
signal will be generated.
external memory interface is disabled
(case a), the MSB of the data bus is
used for 2 more 4-bit parallel I/ O
ports (PE[3..0], PF[3..0]) ; these ports
have the same functionality as the
other parallel I/ O ports. Whenever
the WordAccess mode of the memory
interface is enabled, the registers
controlling the ports PE and PF
The port PB has an extra function: by
setting the bit CHIP_CFG[0]=1, this
port can also be used for UART
extended modem control signals.
Pin
Direction
Input
Input
Input
Output
UART-pin and function (all active high and non inverted)
DCD: Data carrier detect input of UART
RI: Ring indicator input of UART
DSR: Data set ready input of UART
DTR: Data Terminal Ready output of UART
PB0
PB1
PB2
PB3
46
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
In this case, the value of PB_DIR is by-
passed. As soon as CHIP_CFG[0]
CHIP_CFG[0]=0, which corresponds to
the non-UART mode.
setting any of the four configuration
bits CHIP_CFG[6..3]=1, the
becomes zero again, the actual value of
PB_DIR will be used as before. At reset,
Similarly, the port PA has an extra
function related to the Timers: by
corresponding PA bit is connected to
either a Timer input or output.
Pin
Dire ctio n
Output
Input
Output
Input
Tim e r fu n ctio n
PA0
PA1
PA2
PA3
Connected to T2O if CHIP_CFG[3]=1
Connected to T2I if CHIP_CFG[4]=1
Connected to T1O if CHIP_CFG[5]=1
Connected to T1I if CHIP_CFG[6]=1
The value of PA_DIR[k] is by-passed at
that moment CHIP_CFG[k+3]=1. As
soon as CHIP_CFG[k+3] becomes zero
again, the actual value of PA_DIR[k] will
be used as before. At reset,
CHIP_CFG[k+3]=0, which corresponds
to the normal non-timer mode.
Reg ister ta b le
N a m e
Ad d re ss
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Fu n ctio n
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PAB_OUT
PAB_IN
PAB_DIR
A0 [3..0] 280 Data register used to drive PB[3..0] set in output direction
A1 [3..0] 284 Data register to store value of PB[3..0]
A2 [3..0] 288 Selection of the direction of each bit.
Biti = 0 : Pbi set to input node
1 : Pbi set to output node
reset value = 0 hex : all bits set in INPUT mode
CHIP_CFG[0]
01
4
bit[0] : Control bit to connect PB with UART (=1) or not (=0)
N a m e
Ad d re ss
Fu n ctio n
PAB_OUT
PAB_IN
PAB_DIR
A0 [7..4] 280 Data register used to drive PA[3..0] set in output direction
A1 [7..4] 284 Data register to store value of PA[3..0]
A2 [7..4] 288 Selection of the direction of each bit.
Biti = 0 : Pai set to input node
1 : PAi set to output node
reset value = 0 hex : all bits set in INPUT mode
CHIP_CFG[6..3
01
4
bit[k+3] : Control bit to connect PA[k] with a Timer (=1) or not (=0)
N a m e
Ad d re ss
Fu n ctio n
PCD_OUT
PCD_IN
PCD_DIR
A3 [7..4] 282 Data register used to drive PC[3..0] set in output direction
A4 [7..4] 290 Data register to store value of PC[3..0]
A5 [7..4] 294 Selection of the direction of each bit.
Biti = 0 :PCi set to input node
1 :PCi set to output node
reset value = 0 hex : all bits set in INPUT mode
A3 [3..0] 282 Data register used to drive PD[3..0] set in output direction
A4 [3..0] 290 Data register to store value of PD[3..0]
A5 [3..0] 294 Selection of the direction of each bit.
Biti = 0 : PDi set to input node
PCD_OUT
PCD_IN
PCD_DIR
1 : PDi set to output node
reset value = 0 hex : all bits set in INPUT mode
47
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
N a m e
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Fu n ctio n
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PEF_OUT
PEF_IN
PEF_DIR
A6 [7..4] 298 Data register used to drive PE[3..0] set in output direction
A7 [7..4] 29C Data register to store value of PE[3..0]
A8 [7..4] 2A0 Selection of the direction of each bit.
Biti = 0 :PEi set to input node
1 :PEi set to output node
reset value = 0 hex : all bits set in INPUT mode
A6 [3..0] 298 Data register used to drive PF[3..0] set in output direction
A7 [3..0] 29C Data register to store value of PF[3..0]
A8 [3..0] 2A0 Selection of the direction of each bit.
Biti = 0 : PFi set to input node
PEF_OUT
PEF_IN
PEF_DIR
1 : PFi set to output node
reset value = 0 hex : all bits set in INPUT mode
Tim e rs
In slow internal mode, the period
between timeout / toggling events can
be up to 68 ms (216 x (960 kHz)-1,
or about 1 µs per count step) .
capEn (capEn=1). The following
sources can be used to generate the
capSig signal:
Tim ers 1 a nd 2
Down-counting timers with interrupt
generation, event-count and –capture
functions
• the CI activity detection signal
(detection of change in CI bit values
• the Parallel I/ O A detection signal
(detection of change on bits, set in
input mode)
• the External interrupt input signal
(either rising/ falling edge or
high/ low level detection)
The timers can be set to count rising
edges of an input signal (T1I, T2I)
which is applied on the parallel I/ O
port A. The “external count mode” is
selected as soon as the CHIP_CFG bit
corresponding to T1I or T2I is set. The
input signal is sampled at 3840 kHz
for the detection of a rising edge. Two
variants exist:
Two timers are provided (Timer1 and
Timer2). Both are 16-bit load-able
down-counters which count down as
long as the counter is enabled
(count=1). They restart automatically
by presetting to the initial_value when
timer_value == 00 is reached. They
generate an interrupt request on
timeout (whenever timer_value == 00).
They also generate a ‘toggling’ output
signal (T1O, T2O), that changes state
at each timeout occurrence. The output
signal can be used in the external
application via the Parallel I/ O port
A. Timers can be read on the fly (no
need to put count=0 to read). By
default, the counters operate on
• the Parallel IO B detection signal
(detection of change on bits, set in
input mode)
slo w e x te rn a l m o d e (fa st=0 ):
the counter is decreased every fourth
time a rising edge is detected
fa st e x te rn a l m o d e (fa st=1 ):
the counter is decreased every single
time a rising edge is detected
These four signals correspond to the
unmasked, ‘raw’ interrupt status bits.
Capturing is done only once, for the
first event occurring since the capEn
bit was set by software. Once
In this mode the counters may be reset
or stopped “on-the-fly”.
captured, the bit is automatically reset
by the hardware. This prevents the
timer from capturing twice before
reading / re-enabling the capturing
registers. Moreover, the bit also has
an acknowledge function: reading the
bit value permits a check on whether a
capture event occurred or not.
“internal count mode”, where counting
is based on one of two possible fixed
counting frequencies :
Furthermore, Timer1 has an extra
capture register which can be used to
store the actual value of the timer
register when the capture control
signal (capSig, generated by a
hardware event) becomes true.
Capturing is enabled by the control bit
slow internal mode (fast=0): 960 kHz
(=15.36 MHz / 16), default after reset
fast internal mode (fast=1):
3840 kHz (=15.36 MHz / 4)
48
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
After reset, the counters are initialised
as follows:
any value to the WD_MAGIC register.
Caution: As the NRST pin can be
pulled LOW by a watchdog timeout,
the application circuit should contain
a resistor in series with the pin when
an external capacitor is used to form a
power-on reset circuit. (The NRST pin
will attempt to discharge this capacitor
very quickly causing a high peak
current, which may result in damage
to the pin driver. The resistor limits the
current to safe values).
Once enabled, the watchdog can be
‘kicked’ by writing the specific ‘kick-
value’ to WD_MAGIC. ‘Kicking’ the
watchdog performs a re-initialisation
at one of four possible values: This
prevents the timer from reaching the
zero value, which will generate a
reset for the ARM. The initial value is
selected by the two control bits in the
WD_SC register.
• Timer CMD register (TI_CMD) =
0x00 (no-count, not-init, capturing
disabled, slow (internal) mode)
• Internal mode selected because at
reset CHIP_CFG[6,4]=0
• Timer registers (TI_1L, TI_1M, TI_2L,
TI_2M) = 0xFF
• Timer1 capture registers (TI_C1L,
TI_C1M) = 0xFF
W a tch-d og tim er
The output of the watchdog timer
controls the active-low NRESET pin of
the ARM processor and resets all
functional MTC-20280 blocks. It pulses
active low, as soon as the timer
reaches the zero value. It has the
same function as applying an external
hardware reset on the pin NRST and
is externally available for system reset.
A watchdog timer is provided,
working on the ApbClock (with
frequency = Xtal/ 4 or 3.84 Mhz =
0.26 ns). It is a countdown timer,
which is by default disabled after
(power-up) reset of the MTC-20280.
It can be disabled, enabled and
‘kicked’ under software control by
writing a specific “magic” word value
to the WD_MAGIC register. This
changes the state of the watchdog
finite state-machine (FSM), of which
the state can be monitored by reading
the state bit values in the WD_SC
status/ control register.
Disabling is achieved by writing a
sequence of three words to the
WD_MAGIC register (“magic1-word”,
“magic2-word”, and “magic3-word”).
This is to avoid accidental disabling of
the timer. If the sequence is
interrupted by writing any other value
to the WD_MAGIC register, it must be
restarted in order to disable the
watchdog successfully. However, the
sequence may be interleaved without
harm by write commands to other
registers, or by read commands to any
register including WD_MAGIC itself.
Figure 2 1 : Wa tchdog Finite Sta te Ma chine
Enabling is done by a single write of
49
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Reg ister ta b le
N a m e
Ad d re ss
w o rd
C0
Fu n ctio n
b y te
300
304
TI_1L
TI_1M
Timer 1 counter 16 bits (TI_1: LSB & MSB)
Read: counter value
C1
Write: initial value
TI_2L
TI_2M
C2
C3
308
Timer 2 counter 16 bits (TI_2: LSB & MSB)
30C Read: counter value
Write: initial value
TI_CMD
C4
310
Timers command register:
Timer 1:
bit[0]: count (=1:counting; =0:not counting)
bit[1]: init (set to 1 to re-initialise; self-clearing bit)
bit[2]: fast (=1: fast clock = Xtal/ 4; =0: slow clock = Xtal/ 16)
bit[3]: capEn (=1:capture enabled; =0:disabled)
(cleared by HW when captured)
Timer 2:
bit[4]: count (=1:counting; =0:not counting)
bit[5]: init (set to 1 to re-initialise; self-clearing bit)
bit[6]: fast (=1: fast clock = Xtal/ 4; =0: slow clock = Xtal/ 16)
bit[7]: / (not used)
TI_C1L
TI_C1M
TI_CSEL
C5
C6
C7
314
318
Timer 1 capture registers: 16 bits (LSB & MSB)
Read only
31C capture source selection register :
00 : CI change (default)
01 : external interrupt IT
10 : PB input port change
11 : PA input port change
WD_SC [3.. 0]
C8
320
Watch-dog Status and Control register (4 bit)
bit[1.. 0] : Init_value selection (Write and Read possible)
00 : 0.48 sec
01 : 0.61 sec
10 : 0.89 sec
11 : 1.02 sec (default)
bit[3.. 2] : State of watch-dog FSM (Read only)
00 : init & count
01 : unlock1
10 : unlock2
11 : disable (default)
WD_MAGIC
C9
324
Watch-dog Magic word register (8bit);
gives a command to the watch-dog by writing a specific value:
value=DC : Kick command;
value=A5 : Magic1-word command;
value=5A : Magic2-word command;
value=AF : Magic3-word command;
50
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Ha rd w a re id entifica tion cod e
The MTC-20280 contains a read-only
register with a hardware identification
code. Writing to this register will
cause no harm.
for MTC-20280 variants:
MTC-2 0 2 8 0 version
HW id entifica tion cod e
MTC-20280.NAA
0x 001 00 000 = 0x20
The ID code corresponds to the next
eight bits:
FFF RR SSS with
FFF = product family code
( 001 for MTC-20280)
RR = revision code
(rev.N=00, rev.O=01,
rev.P=10, rev.Q=11)
SSS = mask set version
( 000: first, 001: second, …)
The following ID codes are foreseen
Reg ister ta b le
N a m e
Ad d re ss
w o rd
00
Fu n ctio n
b y te
0
CHIP_ID
Returns the chip identification code 0x<MN>
(Hardware version dependent)
51
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Pro g ra m m in g N o te s
For information about programming of
the ARM7TDMI processor core, please
refer to the ARM7 programming
manual.
APB address:
bit[3.. 0]: registers selection
bit[7.. 4]: page selection
0: chip configuration (00-06)
Reg ister m a p sum m a ry
Below is a summary of the complete
memory map of the registers discussed
in the previous sections.
All parameters that are related to the
same hardware unit are grouped
together in registers that are in the
same ‘page’. For details, please see
the Detailed Functional Description
above.
1: HDLC1
2: HDLC2
3: HDLC3
4: HDLC extra (40-46)
5: UART (50-57)
6,7,8: GCI router
9: clock gen, interrupt
A: parallel IO’s
B: GCI router (ext’) (B0-B7)
C: Timers and Watchdog
(C0-C9)
Addresses not listed in the table
should not be used, as they are
allocated for possible future upgrades
of the memory map for new products.
Registers indicated by a “• ” in the first
column have a different physical
address than the functional equivalent
(where appropriate) in the MTC-
20270 device.
Reg ister p hysica l a d d resses
The APB address space is limited to 8
bits wide, corresponding to the ARM
address bits 9 to 2 (32-bit word
aligned addresses), located in the 7th
block of the ARM address space. The
data are of type “byte” and are LSB
aligned onto the (32-bit) data bus. All
other bits (bits 8 to 31) are of
undefined state during a read. A write
to these bits has no effect. The
physical address of an APB register is
thus given by ((APB Address)*4 +
0xE0000000). Standard header-files
for ‘C’ or assembler programs that
define the register mnemonics and
physical addresses are available from
Alcatel Microelectronics.
52
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Na m e
Ad d r.
w ord b yte
Access W id th
(b its)
Reset
(hex )
Function
MTC-2 0 2 8 0 Config ura tion
•
CHIP_ID
00
0
4
R
8
8
<MN>
06
Returns the chip identification code = 0x<MN>
(HW version dependent)
•
CHIP_CFG
01
RW
bit[0]=1 : Configures PB[3.. 0] in PB2Uart mode
bit[2,1] = external interrupt (IT) type
00: falling edge 01: rising edge
10: low-level 11:high-level (default)
bit[3]=1 : use PA0 as Timer output T2O
bit[4]=1 : use PA1 as Timer input T2I
bit[5]=1 : use PA2 as Timer output T1O
bit[6]=1 : use PA3 as Timer input T1I
bit[7]=1 : swap addresses for external
memory block 0 and 3
•
CHIP_GCI_L
02
8
R
8
00
Data rate detected on the master GCI interface
(data bits per frame).
Lsb bits of data rate
•
•
CHIP_GCI_M
CHIP_WTC1
03
04
C
10
R
RW
8
8
00
FF
Msb bits of data rate
Wait cycles for external memory blocks
bit[3:0]: mem block 0
bit[7:4]: mem block 1
•
•
CHIP_WTC2
CHIP_WTC3
05
06
14
18
RW
RW
8
8
FF
FF
bit[3:0]: mem block 2
bit[7:4]: mem block 3
bit[3:0]: mem block 4
bit[7:4]: mem block 5
HDLC Form a tters
HD1_MODE
HD1_EMODE
HD1_CMD
HD1_SSTAT
HD1_FSTAT
HD1_ISTAT
HD1_ISRV
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
80
84
88
RW
RW
W
R
R
R
R
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
W
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
00
00
00
00
32
00
00
00
00
00
00
00
00
00
00
00
00
00
00
HDLC mode register
HDLC Extended mode register
HDLC Command register
HDLC Serial Status register
Fifo Status register
Interrupt Status Register
Interrupt Service Request Register
Interrupt Mask Register
Rx/ Tx Fifo data register
Receive Frame Byte Count
Transmit Address 1
HD1_IMASK
HD1_FIFO
HD1_RFBC
HD1_TA1
HD1_TA2
Transmit Address 2
HD1_RAW1
HD1_RAW2
HD1_RA1
Receive Address Wildcard 1
Receive Address Wildcard 2
Receive Address Register 1
Receive Address Register 2
HDLC mode register
HD1_RA2
HD2_MODE
HD2_EMODE
HD2_CMD
HDLC Extended mode register
HDLC Command register
53
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
(b its)
(hex )
Na m e
Ad d r.
Access Width
Reset
Function
w ord b yte
HD2_SSTAT
HD2_FSTAT
HD2_ISTAT
HD2_ISRV
HD2_IMASK
HD2_FIFO
HD2_RFBC
HD2_TA1
HD2_TA2
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
8C
90
94
98
9C
A0
A4
A8
AC
B0
B4
B8
BC
C0
C4
C8
CC
D0
D4
D8
DC
E0
R
R
R
R
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
W
R
R
R
R
RW
RW
R
RW
RW
RW
RW
RW
RW
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
00
32
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
32
00
00
00
00
00
00
00
00
00
00
00
X
HDLC Serial Status register
Fifo Status register
Interrupt Status Register
Interrupt Service Request Register
Interrupt Mask Register
Rx/ Tx Fifo data register
Receive Frame Byte Count
Transmit Address 1
Transmit Address 2
HD2_RAW1
HD2_RAW2
HD2_RA1
Receive Address Wildcard 1
Receive Address Wildcard 2
Receive Address Register 1
Receive Address Register 2
HDLC mode register
HDLC Extended mode register
HDLC Command register
HDLC Serial Status register
Fifo Status register
Interrupt Status Register
Interrupt Service Request Register
Interrupt Mask Register
Rx/ Tx Fifo data register
Receive Frame Byte Count
Transmit Address 1
HD2_RA2
HD3_MODE
HD3_EMODE
HD3_CMD
HD3_SSTAT
HD3_FSTAT
HD3_ISTAT
HD3_ISRV
HD3_IMASK
HD3_FIFO
HD3_RFBC
HD3_TA1
HD3_TA2
HD3_RAW1
HD3_RAW2
HD3_RA1
E4
E8
EC
F0
F4
Transmit Address 2
Receive Address Wildcard 1
Receive Address Wildcard 2
Receive Address Register 1
Receive Address Register 2
Source data:
F8
FC
HD3_RA2
HD1_SRC
•
•
•
•
100 RW
104 RW
108 RW
10C RW
[1:0]: line selection (0.. 2: U-S-A)
[4:2]: burst selection (0 ... 7)
[6:5]: channel selection (0.. 2: B1-B2-D)
Source data:
[1:0]: line selection (0.. 2: U-S-A)
HD2_SRC
HD3_SRC
HD_BREV
41
42
43
8
8
3
X
X
0
[4:2]: burst selection (0…7)
[6:5]: channel selection (0.. 2: B1-B2-D)
Source data:
[1:0]: line selection (0.. 2: U-S-A)
[4:2]: burst selection (0…7)
[6:5]: channel selection (0.. 2: B1-B2-D)
bit-reverse data bit (lsb fl‡ msb) read/ written from/ to the
HDLC Fifo
bit[0]=1 bit-reverse data from/ to HDLC 1
bit[1]=1 bit-reverse data from/ to HDLC 2
bit[2]=1 bit-reverse data from/ to HDLC 3
bit[4]=1 bit reversed per block of 2 for D channel
transmission through HDLC1 in transparent mode
bit[5]=1 bit reversed per block of 2 for D channel
transmission through HDLC2 in transparent mode
bit[6]=1 bit reversed per block of 2 for D channel
transmission through HDLC3 in transparent mode
54
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
(b its)
(hex )
Na m e
Ad d r.
w ord
44
45
46
Access Width
Reset
Function
b yte
110
114
118
•
•
•
HD1_TX
HD2_TX
HD3_TX
R
R
R
8
8
8
X
X
X
HDLC packet ready to be transmitted in the current frame
HDLC packet ready to be transmitted in the current frame
HDLC packet ready to be transmitted in the current frame
UART
UART_RBR
50(*)
50(*)
51(*)
52
52
53
140
140
144
148
148
14C
150
154
158
15C
140
144
R
W
RW
R
W
RW
RW
R
RW
RW
RW
RW
8
8
8
8
8
8
8
8
8
8
8
8
00
00
00
00
00
00
00
60
00
00
00
00
Receiver Buffer Register
Transmitter Holding Register
Interrupt Enable Register
Interrupt Ident Register
Fifo Control Register
Line Control Register (with UART_LCR[7]=DLAB bit)
Modem Control Register
Line Status Register
Modem Status Register
Scratch Register
Divisor Latch Register (LSB)
Divisor Latch Register (MSB)
(*) Register addresses 50 & 51 corresponds to
- DLL & DLM ONLY if UART_LCR[7]=DLAB=1
- RBR/ THR & IER if UART_LCR[7]=DLAB=0
UART_THR
UART_IER
UART_IIR
UART_FCR
UART_LCR
UART_MCR 54
UART_LSR 55
UART_MSR 56
UART_SCR
UART_DLL
UART_DLM
57
50(*)
51(*)
GCI router
•
•
•
•
Ui_B1_CPU 60
Ui_B2_CPU 61
180
184
188
18C
RW
RW
RW
RW
8
8
8
8
X
X
X
X
CPU value for the B1 upstream Ui channel
CPU value for the B2 upstream Ui channel
CPU value for the M upstream Ui channel
CPU value for the C/ I byte upstream Ui channel
bit[7:6] = D bits
Ui_M_CPU
Ui_E_CPU
62
63
bit[5:2] = CI bits
bit[1:0] = AE bits
•
•
•
•
Si_B1_CPU
Si_B2_CPU
Si_M_CPU
Si_E_CPU
64
65
66
67
190
194
198
19C
RW
RW
RW
RW
8
8
8
8
X
X
X
X
CPU value for the B1 downstream Si channel
CPU value for the B2 downstream Si channel
CPU value for the M downstream Si channel
CPU value for the C/ I byte downstream Si channel
bit[7:6] = D bits
bit[5:2] = CI bits
bit[1:0] = AE bits
•
•
•
•
Ai_B1_CPU 68
Ai_B2_CPU 69
1A0
1A4
1A8
1AC
RW
RW
RW
RW
8
8
8
8
X
X
X
X
CPU value for the B1 downstream Ai channel
CPU value for the B2 downstream Ai channel
CPU value for the M downstream Ai channel
CPU value for the C/ I byte downstream Ai channel
bit[7:6] = D bits
Ai_M_CPU
Ai_E_CPU
6A
6B
bit[5:2] = CI bits
bit[1:0] = AE bits
•
•
•
•
•
Ui_B1_RX
Ui_B2_RX
Ui_M_RX
Ui_E_RX
6C
6D
6E
6F
70
1B0
1B4
1B8
1BC
1C0
R
R
R
R
R
8
8
8
8
8
X
X
X
X
X
B1 channel read from the Ui downstream GCI frame
B2 channel read from the Ui downstream GCI frame
M channel read from the Ui downstream GCI frame
[D,CI,AE] channel read from the Ui down GCI frame
B1 channel read from the Si upstream GCI frame
Si_B1_RX
55
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
(b its)
(hex )
Na m e
Ad d r.
Access Width
Reset
Function
w ord b yte
•
•
•
•
•
•
•
•
Si_B2_RX
Si_M_RX
Si_E_RX
Ai_B1_RX
Ai_B2_RX
Ai_M_RX
Ai_E_RX
71
72
73
74
75
76
77
78
1C4
1C8
1CC
1D0
1D4
1D8
1DC
1E0
R
R
R
R
R
R
R
W
8
8
8
8
8
8
8
8
X
X
X
X
X
X
X
0
B2 channel read from the Si upstream GCI frame
M channel read from the Si upstream GCI frame
[D,CI,AE] channel read from the S up GCI frame
B1 channel read from the Ai upstream GCI frame
B2 channel read from the Ai upstream GCI frame
M channel read from the Ai upstream GCI frame
[D,CI,AE] channel read from the Ai upstream GCI frame
Specify the burst targeted by the ARM
GCI_CPU_RX
CPU registers access
Rx registers access
bit[1:0] = target line U-S-A
bit[4:2] = CPU target burst
bit[7:5] = Rx target burst
•
GCI_ITU
79
1E4
1E8
RW
RW
8
00
bit[i]: CI activity detected on U, burst I
Read bit[I]=1: activity detection;
Write bit[I]=1: interrupt cleared
bit[i]: CI activity detected on S, burst i
•
•
•
•
•
•
•
GCI_ITS
GCI_ITA
7A
7B
7C
7D
7E
7F
80
8
8
8
8
8
3
8
00
00
FF
FF
FF
0
1EC RW
bit[i]: CI activity detected on A, burst i
GCI_MSKU
GCI_MSKS
GCI_MSKA
GCI_SRC_BUR
U_B1_SRC
1F0
1F4
1F8
1FC RW
200 RW
RW
RW
RW
bit[i]=1: mask CI activity detected on U, burst i
bit[i]=1: mask CI activity detected on S, burst i
bit[i]=1: mask CI activity detected on A, burst i
Target burst selection for reading _SRC registers
Source control register for target U_B1 upstream:
[7:5] source burst
X
[4:3] source line
[2:0] target burst
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
U_B2_SRC
U_D_SRC
U_CI_SRC
U_M_SRC
U_AE_SRC
S_B1_SRC
S_B2_SRC
S_D_SRC
S_CI_SRC
S_M_SRC
S_AE_SRC
A_B1_SRC
A_B2_SRC
A_D_SRC
A_CI_SRC
A_M_SRC
A_AE_SRC
U_B1_SWP
U_B2_SWP
S_B1_SWP
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
B0
B1
B2
B3
B4
204 RW
208 RW
20C RW
210 RW
214 RW
218 RW
21C RW
220 RW
224 RW
228 RW
22C RW
230 RW
234 RW
238 RW
23C RW
2C0 RW
2C4 RW
2C8 RW
2CC RW
2D0 RW
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Source control register for target U_B2 upstream
Source control register for target U_D upstream
Source control register for target U_CI upstream
Source control register for target U_M upstream
Source control register for target U_AE upstream
Source control register for target S_B1 downstream
Source control register for target S_B2 downstream
Source control register for target S_D downstream
Source control register for target S_CI downstream
Source control register for target S_M downstream
Source control register for target S_AE downstream
Source control register for target A_B1 downstream
Source control register for target A_B2 downstream
Source control register for target A_D downstream
Source control register for target A_CI downstream
Source control register for target A_M downstream
Source control register for target A_AE downstream
bit[i] = swap / no swap for B1 channel on U burst i
bit[i] = swap / no swap for B2 channel on U burst I
bit[i] = swap / no swap for B1 channel on S burst I
56
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
(b its)
(hex )
Na m e
Ad d r.
Access Width
Reset
Function
w ord b yte
•
•
•
S_B2_SWP
A_B1_SWP
A_B2_SWP
B5
B6
B7
2D4 RW
2D8 RW
2DC RW
8
8
8
X
X
X
bit[i] = swap / no swap for B2 channel on S burst I
bit[i] = swap / no swap for B1 channel on A burst I
bit[i] = swap / no swap for B2 channel on A burst i
Clock Genera tion
•
CLK_GCI
90
240 RW
8
00
bit[5:0]: GCI DCL selection per interface. U,S,A:
bit[1:0] = for the U GCI router
bit[3:2] = for the S GCI router
bit[5:4] = for the A GCI router
0 = non-active (default at reset)
1 = master : dclMstr / fscMstr
2 = 512k: dcl512 / fsc512
3 = 4096k: dcl4096 / fsc4096
bit[7:6] : GCI Master FSC selection (fscMstr)
0 = Xtal (default at reset)
1 = U
2 = S
3 = A
•
•
•
CLK_1
CLK_2
CLK_3
91
92
93
244 RW
248 RW
24C RW
8
8
8
00
00
00
Parameters for CKOUT:
bits [7.. 4]: Disabled if equal to “1001”
bits [3.. 0]: Freq. Division par. CLK_1 for CKOUT
Parameters for ARM Clock:
bits [7.. 4]: Disabled if equal to “1001”
bits [3.. 0]: Freq. Division par. CLK_2 for ARMclock
bit [0] : DPLL status (read only)
0 = internal gci clocks not synchronized with
the extern reference; dpll is tracking
1 = internal gci clocks synchronized
bit [1] : UART clock disable
bit [3:2]: APB clock division factor
0 = 15.36 Mhz/ 4 (max.speed)
1 = 15.36 Mhz/ 8
2 = 15.36 Mhz/ 16
3 = 15.36 Mhz/ 32
Interrup t
•
•
•
•
•
•
•
•
•
•
•
•
IRQ1_ST
IRQ1_STR
IRQ1_EN
IRQ1_ENSET
IRQ1_ENCLR
IRQ1_ACK
IRQ2_ST
IRQ2_STR
IRQ2_EN
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
250
254
258
25C
260
264
268
26C
270
274
278
27C
R
R
R
W
W
W
R
R
R
8
8
8
8
8
8
8
8
8
8
8
8
00
00
00
00
00
00
00
00
00
00
00
00
Interrupt status after mask
Interrupt status without mask
Interrupt mask to be used
Set maskbit control input register
Clear maskbit control input register
Clear interrupt status register
Interrupt status after mask
Interrupt status without mask
Interrupt mask to be used
IRQ2_ENSET
IRQ2_ENCLR
IRQ2_ACK
W
W
W
Set maskbit control input register
Clear maskbit control input register
Clear interrupt status register
57
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
(b its)
(hex )
Na m e
Ad d r.
Access Width Reset
Function
w ord b yte
Pa ra llel IO
•
•
•
PAB_OUT
A0
A1
A2
280 RW
284
288 RW
8
8
8
00
00
00
bit[7..4]: PA output data register
bit[3:0]: PB output data register
bit[7..4]: PA input data register
bit[3:0]: PB input data register
bit[7..4]: PA direction control register (0=input)
bit[3:0]: PB direction control register (0=input)
PAB_IN
R
PAB_DIR
•
•
•
•
•
PCD_IN
PCD_DIR
PEF_OUT
PEF_IN
A4
A5
A6
A7
A8
290
R
8
8
8
8
8
00
00
00
00
00
bit[7..4]: PC input data register
bit[3:0]: PD input data register
bit[7..4]: PC direction control register (0=input)
bit[3:0]: PD direction control register (0=input)
bit[7..4]: PE output data register
bit[3:0]: PF output data register
bit[7..4]: PE input data register
bit[3:0]: PF input data register
bit[7..4]: PE direction control register (0=input)
bit[3:0]: PF direction control register (0=input)
294
298
29C
2A0
RW
RW
R
PEF_DIR
RW
GCI Router ex t’
see before
•
B0-BF
see GCI Router pages
Tim ers a nd W a tch-d og
•
•
•
•
•
TI_1L
C0
C1
C2
C3
C4
900
304
308
30C
310
RW
RW
RW
RW
RW
8
8
8
8
8
FF
FF
FF
FF
00
Timer 1 lsb
R: counter value
W: initial value
Timer 1 msb
R: counter value
W: initial value
Timer 2 lsb
R: counter value
W: initial value
Timer 2 msb
R: counter value
W: initial value
Timer command register:
Timer 1
TI_1M
TI_2L
TI_2M
TI_CMD
bit[0]: count (=1:counting; =0:not counting)
bit[1]: init (set to 1 to re-initialise; self-clearing bit)
bit[2]: fast (=1: fast clock = Xtal/ 4;
=0: slow clock = Xtal/ 16)
bit[3]: capEn (=1:capture enabled; =0:disabled)
(cleared by HW when captured)
Timer 2:
bit[4]: count (=1:counting; =0:not counting)
bit[5]: init (set to 1 to re-initialise; self-clearing bit)
bit[6]: fast (=1: fast clock = Xtal/ 4;
=0: slow clock = Xtal/ 16)
bit[7]: / (not used)
58
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
•
•
•
TI_C1L
TI_C1M
TI_CSEL
C5
C6
C7
314
318
31C
R
R
RW
8
8
2
FF
FF
0
Timer 1 capture register : lsb
Timer 1 capture register : msb
capture source selection register :
00 : CI change (default)
01 : external interrupt IT
10 : PB input port change
11 : PA input port change
(hex )
(b its)
Na m e
Ad d ress
Access
Width
Reset
Function
w ord
b yte
•
WD_SC
C8
320
4
RW
F
Watch-dog status and control register
bit[1..0] : Init_value selection
00 : 0.48 sec
01 : 0.61 sec
10 : 0.89 sec
11 : 1.02 sec (default)
R
bit[3..2] : State of watch-dog FSM (Read only)
00 : init & count
01 : unlock1
10 : unlock2
11 : disable (default)
•
WD_MAGIC
C9
324
RW
8
00
Watch-dog magic word register:
value written : command issued
value=DC : Kick command;
value=A5 : Magic1-word command;
value=5A : Magic2-word command;
value=AF : Magic3-word command;
D-cha nnel collision a void a nce
The pseudo-C code below is intended to
show a user of the MTC-20270 or
20280 families of ISDN controllers
(“ITC”) how to implement the D-channel
collision avoidance protocol.
3. Switch the upstream D channel to
come from the transmitted data
stream of one of the MTC-20280's
HDLC controllers (e.g. HDLC1).
4. Send the data packet
The ITC register map is externally
declared as a struct pointer, which is
initialised to the physical hardware
address. A simple interrupt routine
driven by the GCI frame clock
5. Wait for the packet to end by
increments an int-sized counter called
monitoring the TIF bit, and then allow
time for the flag character to leave
6. Switch the upstream U D channel
back to the S bus
7. Unblock the S bus D channel by
letting the E bit follow the S bus D bit.
framecount.
It is based on the use of the MTC-2027x
series of ISDN Integrated NT devices,
whose S interface support the use of the
DE collision protocol. The same applies
to the MTC-20172 ‘S’ interface circuit.
NOTE: When a constant value needs to
be used from a CPU register, the value
should be written into the CPU register
twice in two consecutive GCI frames.
(This is an artifact of the architecture
with two parallel RAM spaces – the
constant value must be written into both
RAM spaces. Failure to do so results in
the output value alternating between the
LAST output value and the new
The basic algorithm is:
1. Check that the S bus is not using the D
channel by monitoring the BUSY bit in
the S interface device.
2. Block the use of the S bus D channel by
forcing an active condition on the E bit.
The low-level routines d=read_M(p,a)
and write_M(p,a,d) read and write
data d to/ from GCI port p (p=U,S or
A) at register address a, using
the M-channel protocol.
(‘constant’) value).
59
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
/* D-channel conflict handling in C */
extern struct *ITC;
extern int framecount;
/* Defines ITC registers */
/* counter incremented each GCI frame */
send_D-chan(char *p)
{
int fc;
while((read_M(S,0) & BUSY))
write_M(S,2,0x30);
{;}
/* Wait until BUSY bit in INT S is clear */
/* Set DE bus active (DE pin is bonded LOW on MTC-2027x ISDN NT chips) */
ITC->U_DX_SRC = 3; /* Set Upstream U D-channel to HDLC1 Tx */
/* SEND DATA PACKET TO HDLC1 HERE */
while((ITC->HD1-SSTAT & TIF)) {;}
/* Wait until TIF bit goes inactive */
/* Present framecounter value*/
fc=framecount;
while ((framecount-fc) < 4) {;}
/* Let 4 complete GCI frames pass to allow flag to leave */
ITC->U_DX_SRC = 2;
write_M(S,2,0x20);
/* Disable DE bus to allow S bus D channel to operate */}
/* Connect upstream U D channel to S */
Pa ck a g e a n d Pin o u t
The device is mounted in a 100-pin
PQFP package. The following
figures show the pin-out names and
package orientations in top view.
MTC-20280
Figure 2 2 : Device Pinout
60
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Pin description a nd a ssignm ent
The next table lists the device pins and
their. The type of pin is encoded with
a letter code, such as “DId” for a
digital input with internal pull down.
Im p o rta n t n o te s o n 5 V to le ra n t
p in s
Note 1:
The exact meaning is that these cells
tolerate 5V INPUT signals, but they do
not generate 5V OUTPUT signals. The
I/ O cell can be either :
The first letter differentiates between:
D: Digital
A: Analog
P : Power
tri-stateable (cells of type “*5z”): this
is required for driving bus structures in
open drain configuration (e.g. GCI
data out). In all cases it requires an
external pull-up resistor to either 3.3V
or 5V depending on which high
output level is requested by the
application system
The second letter differentiates
between:
I : Input
O
: Output
B : Bidirectional
The next letter differentiates between:
d : pin with internal pull-down
u : pin with internal pull-up
non-tristateable (cells of type “*5”):
when no bus must be driven and fast
transitions are needed (e.g. GCI
clocks and UART outputs). No external
pull-up is required, but then a 3.3V
high output level will be driven
The next letter indicates whether the pin is:
s : pin with Schmitt trigger input
The next letter indicates whether the pin is:
5 : 5 Volt tolerant input/ output
Note 2:
When using a 5V interface, the system
should be designed such that no 5V
inputs are applied when the 3.3V
power supply is not present, as this
limits the lifetime of the device.
The next letter indicates whether the pin is:
z : pin with tri-state output
If pins are unused in the application,
the tables show whether they must be
connected fixed to power (VDD) or
ground (GND), or must remain
unconnected (DNC).
61
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Pin d escrip tion ta b le
Pin Id entifica tion
43
44
45
46
52
51
50
49
48
47
21
54
53
40
41
55
56
59
60
98
97
96
95
94
90
91
79
93
80
85
86
87
88
81
82
83
84
61
62
63
64
17
18
19
20
A15
A16
A17
A18
MC0
MC1
MC2
MC3
MC4
MC5
MC6
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
7
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
Nr.
78
77
76
75
72
71
70
69
68
67
66
65
99
100
1
Name Type
23
39
57
73
89
8
24
42
58
74
92
DIU
DIs5
DO5z
DBs5
DBs5
DIs5
DO5z
DBs5
DBs5
DIs5
DO5z
DBs5
DBs5
DBs
DOU
DCLU
FSCU
DIS
DOS
DCLS
FSCS
DIA
DOA
DCLA
FSCA
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
Cmos
4mA
TTL
6mA
NWR DO
NOE
MM1
MM0
RXD
TXD
CTS
RTS
NTRST DId
DO
DI
DI
DIs5
DO5
DIs5
DO5
Cmos
4mA
TTL
Cmos
4mA
DBs
DBs
DBs
DBs
6mA
2
3
4
5
6
9
DBs
DBs
DBs
DBs
Cmos
4mA
TMS
TCK
TDI
DIu
DIu
DIu
DO
10
11
12
13
14
15
16
22
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DBs
TDO
DQ10 DBs
DQ11 DBs
DQ12 DBs
DQ13 DBs
DQ14 DBs
DQ15 DBs
XTAL1 DIs
XTAL2 DIs
CKOUT DO
NRST DB5s
Cmos
4mA
TTL
6mA
TTL
IT
DI5s
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3
PD0
PD1
PD2
PD3
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
DBs5
MC7
A1
DOz
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
6mA
Cmos
4mA
A2
A3
TTL
6mA
A4
A5
A6
A7
TTL
6mA
A8
A9
A10
A11
A12
A13
A14
TTL
6mA
62
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Pin function in norm a l op era ting
m od e
• the parallel I/ O port PB[3..0] can
be used to access input/ output
control signals of the UART module
for implementing a modem
communication protocol; this
happens as soon as the Pb2Uart
mode is selected.
The following table gives a summary
of all MTC-20280 pins and their
functions in normal (i.e. non-test)
mode. Test modes are used by Alcatel
for production testing only.
Note that the allocation of GCI ports
to U,S, or A (*) is for convenience
only: all three ports are functionally
identical and can be interchanged.
• the parallel I/ O port PA[3..0] can
be used to access one input and/ or
one output control signal for each
Timer module. The input allows
counting based on externally
Note also that depending on the
configuration in which the MTC-
20280 is used:
applied rising-edge events; the
output shows a toggling signal,
based on the timer interrupt events,
which can be used as a clock. The
connection to either the general
purpose Parallel IO function or a
Timer function, is programmed on a
bit-basis by setting the
• the MSB byte of the data bus can be
re-used as parallel IO; this is the
case when the Word Access Mode
is disabled.
corresponding CHIP_CFG[i] bit .
Pin Nr.
76
75
Pin na m e
DCLU
FSCU
DIU
Descrip tion
GCI-U*
INT.
GCI Data clock associated with the U-GCI interface
GCI Frame clock associated with the U-GCI interface
GCI Data from the U-GCI interface
78
77
70
69
72
DOU
DCLS
FSCS
DIS
GCI Data to the U-GCI interface
GCI-S*
INT.
GCI Data clock associated with the S-GCI interface
GCI Frame clock associated with the S-GCI interface
GCI Data from the S-GCI interface
71
DOS
GCI Data to the S-GCI interface
66
65
68
DCLA
FSCA
DIA
GCI-A*
INT.
GCI Data clock associated with the A-GCI interface
GCI Frame clock associated with the A-GCI interface
GCI Data from the A-GCI interface
67
DOA
GCI Data to the A-GCI interface
63
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Pin Nr.
99,100,
1…16
Pin na m e
DQ15..0
Descrip tion
RAM
INT.
Bidirectional data bus; DQ0:Isb, DQ15:msb ;Msb byte used as
parallel ports PE,PF if singleByte access mode is chosen
Address bus: A18:msb, A1:lsb (note: lsb=MC7 depending on
interface mode)
Memory control outputs (meaning dependent on interface mode):
e.g., chip select signals (active low), lsb/ msb byte selection, and
address lsb, depending on MM1..0
25…46
A18..1
MC7..0
21,22,
47…52
40,41
54
53
55
56
59
60
98
97
MM1..0
NWR
NOE
RXD
TXD
CTS
MemoryAccess mode selection
Write enable signal, active low
Output enable signal, active low
Serial data input
UART
JTAG
Serial data output
Modem control signal : Clear to Send input
Modem control signal : Request to Send output
JTAG reset signal, active low
JTAG mode select signal
JTAG clock (max 10 MHz)
RTS
JTNRS
JTMS
JTCK
JTDI
96
95
JTAG data input
94
90
JTDO
XTAL1
JTAG data output
Clocks
Pins to connect an external parallel mode Xtal for the on-chip
oscillator. Nominal frequency : 15.36 MHz ±50ppm
Remark : XTAL1 may be used as an input for an external master
clock source; in that case XTAL2 must be connected to GND
Programmable output clock (typically 15.36 MHz for U-interface)
Hardware reset, active low. Schmitt-trigger input with threshold at
1.65 V (CMOS LEVEL). Connect an external (RC) circuit with timing > 1 ms
External interrupt source (rising/ falling edge or level triggered)
Bitwise controlled Input or Output, or potential connection to Timer
modules T1 or T2 (PA3=T1I, PA2=T1O, PA1=T2I, PA0=T2O)
depending on CHIP_CFG[6..3]
91
XTAL2
79
93
CKOUT
NRST
80
85…88
IT
PA3..0
Parallel IO
61…64
81…84
PC3..0
PD3..0
PB3..0
Bitwise controlled Input or Output
Bitwise controlled Input or Output, or potential extra connection to
the UART for modem communication with PB3 == DTR output,
PB2..0 == DSR/ RI/ DCD inputs depending on CHIP_CFG[0]
3.3 V power supply
7,23,39,57,
73,89
8,24,42,58
74,92
VDD
VSS
Power
Ground
0 V ground
64
MTC-2 0 2 8 0
ISDN/ IDSL Terminal Controller
Device b ra nd ing
Alcatel Microelectronics acknowledges the trademarks of all companies referred to in this document.
This document contains information on a new product.
Alcatel Microelectronics reserves the right to make
changes in specifications at any time and without notice.
The information furnished by Alcatel Microelectronics in this
document is believed to be accurate and reliable.
However, no responsibility is assumed by Alcatel
Microelectronics for its use, nor for any infringements of
patents or other rights of third parties resulting from its use.
No licence is granted under any patents or patent rights
of Alcatel Microelectronics.
Alca te l Micro e le ctro n ics
info@mie.alcatel.be
http:/ / www.alcatel.com/ telecom/ micro
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65
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