AS3665_04 [AMSCO]
9 Channel Advanced Command Driven RGB/White LED Driver; 9通道高级命令驱动RGB /白光LED驱动器
| 型号： | AS3665_04 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | 9 Channel Advanced Command Driven RGB/White LED Driver |
| 文件： | 总78页 (文件大小：3331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
austriamicrosystems AG
is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
Datasheet,Confidential
AS3665
9 Channel Advanced Command Driven RGB/White LED Driver
1 General Description
2 Key Features
ꢀ
High efficiency capacitive 150mA charge pump with
1:1, 1:1.5 and 1:2 modes with automatic mode
switching; 1:2 mode can be disabled
The AS3665 is a capacitive low noise charge pump with
9 current sources. The charge pump automatically
switches between 1:1 and 1:1.5 modes. The connected
current sources have a very low voltage compliance to
improve efficiency of the whole system. Three current
sources have the possibility to operate either from VBAT
or VCP (especially useful for red LEDs).
ꢀ
9 Channel High Side 20mA Current sources
- Less than 50mV at 10mA dropout voltage
- LED7,8,9 either powered by VBAT or VCP
Advanced Command based Pattern Generatr
- 96 x 16 bits program memory
- Dedicated lighting commands like ogarithmic fade
- Programming control and condional umps
Audio Controlled Lighting with ternl digital filters
3 Sequencers
ꢀ
The internal control is done by command based pattern
generators implemented by three sequencers. These
commands are optimized for lighting applications (e.g.
ramp up brightness logarithmically). It includes high
level commands like conditionals jumps and variables.
Any of the three sequencers can be dynamically
ꢀ
ꢀ
- Dynamically mapped to 9 PWM generators
Intenal/External Synronzation
mapped to any of the 9 PWM generators for the LEDs.
The AS3665 supports an audio input and sophisticated
light patterns can be controlled by internal digital filters.
9 PWM generators (12 bit resolution)
- Automatic RGB Color Correction by TAMB
I2C interface wh dedicated EN pin
The AS3665 is controlled by I2C mode. Synchronization
over several AS3665 is possible by the TRIG pin.
ꢀ
ꢀ
Available in WL-CSP-25 (2.610x2.675mm) 0.5mm
pitch
The AS3665 is available in a space-saving WL-CSP-25
(2.610x2.675mm) 0.5mm pitch and operates ovr the -
30ºC to +85ºC temperature range.
3 Applications
GB/White Fun or Event LED for mobile phones or por-
tabe devices; Lighting Management Unit
Figure 1. Typical Operating Circuit
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Revision 1.0.2
1 - 77
AS3665
Datasheet, Confidential - Pinout
4 Pinout
Pin Assignment
Figure 2. Pin Assignments WL-CSP-25 (2.610x2.675mm) 0.5mm pitch (Top View)
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AS3665
AS3665
Pin Description
Table 1. Pin Description for AS3665
Pin Number
Pin Name
C2-
Description
ChaPump flying caitor - make a short connection to capacitor CFLY2
Charge Pump flying cor 1 - make a short connection to capacitor CFLY1
Ground supply iput pn
A1
A2
A3
A4
A5
B1
B2
C1-
GND
LED9
LED8
VBAT
C2+
LED9 ouut - current source from VCP or VBAT
LED8 output current source from VCP or VBAT
Positive pply input pin
harge Pump flying capacitor 2 - make a short connection to capacitor CFLY2
Digital input - I2C address select; the value of the resistor RADDR defines the actual
I2C address used
B3
ADDR
Internal supply - connect a 1µF ceramic capacitor between C2V5 and GND
LED7 output - current source from VCP or VBAT
B4
B5
C1
C
C3
C4
C5
D1
D2
2V5
LED7
VCP
Charge Pump output - make a short connection to capacitor CVCPOUT
Charge Pump flying capacitor 1 - make a short connection to capacitor CFLY1
LED3 output - current source from VCP
C1+
LED3
TRIG
GPO
LED2
LED1
Digital open drain input/output - used to synchronize across several AS3665
Digital open drain input/output - General purpose output and ADC input
LED2 output - current source from VCP
LED1 output - current source from VCP
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Pinout Pin Description
Table 1. Pin Description for AS3665 (Continued)
Pin Number
Pin Name
Description
Digital input - active high enable for AS3665
D3
EN
Digital clock input - connect a 32.768kHz signal; if this signal is not available,
connect this pin to GND
D4
CLK32K
Depending on the AS3665 configuration INT/AUDIO_IN is a
1. Open drain digital output - interrupt output pin
D5
INT/AUDIO_IN
2. Analog input - audio or ADC signal input
LED5 output - current source from VCP
LED4 output - current source from VCP
LED6 output - current source from VCP
E1
E2
E3
E4
LED5
LED4
LED6
SCL
Digital input - clock input for I2C communication
Digital open drain input/output - data input/output for I2C commuicatin
E5
SDA
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AS3665
Datasheet, Confidential - Absolute Maximum Ratings Pin Description
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Table 3, “Electrical
Characteristics,” on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Min
-0.3
-0.3
Max
Units
Comments
VBAT, VCP, C1+, C1-,
C2+, C2- to GND
+7.0
V
V
Note: Diode between VCP and VBAT
VCP to VBAT
VCP +
0.3
LED1, LED2...LED9 to GND
-0.3
V
7.0
VBAT +
0.3
SDA, SCL, EN, CLK32K, TRIG,
INT/AUDIO_IN, GPO, ADDR, C2V5 to GND
-0.3
V
7.0
+10
+IIN
Input Pin Current without causing latchup
Continuous Power Dissipation (TA = +70ºC)
Continuous power dissipation
-100
m
Norm: EIA/JESD78
1
.78
14.2
mW
PT
2
Continuous power dissipation derating factor
mW/ºC
PDERATE
Electrostatic Discharge
ESD HBM
±1000
±500
±0
V
V
Norm: JEDEC JESD22-A114F
Norm: JEDEC JESD 22-C101C
ESD CDM
ESD MM
Norm: JEDEC JESD 22-A115-A level A
Temperature Ranges and Storage nditions
Internally limited (overtemperature
protection)
Junction Temperature
+150
ºC
Storage Temperature Range
Humidity
-5
5
+125
85
ºC
%
Non condensing
Body Temperature during Solderng
+260
ºC
according to IPC/JEDEC J-STD-020C
1. Depending on actual PCB layot and PCB used
2. PDERATE derating factor chages the total continuous power dissipation (PT) if the ambient temperature is not
70ºC. Therefore for e.g. TMB=5ºC calculate PT at 85ºC = PT - PDERATE * (85ºC - 70ºC)
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AS3665
Datasheet, Confidential - Electrical Characteristics Pin Description
6 Electrical Characteristics
VVBAT = +2.7V to +5.5V, TAMB = -30ºC to +85ºC, unless otherwise specified. Typical values are at VVBAT = +3.6V, TAMB
= +25ºC, unless otherwise specified.
Table 3. Electrical Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
General Operating Conditions
VVBAT
Supply Voltage
Supply Voltage
2.7
2.5
3.6
5.5
2.7
V
V
AS3665 functionally working, but not all
parameters fulfilled
VVBATREDU
CED_FUNC
ISHUTDOWN
ISTANBY
Shutdown Current
0.4
1.6
1.3
6.0
µA
µA
I2C interface active
Standby mode Current
I2C interface active
IACTIVE
Active mode Current
Charge Pump Current
300
µA
Internal oscillator running, program executed
Charge pump operating in 1:1.5 mode,
no load current
ICP1:1.5
TAMB
7
25
mA
ºC
Operating
Temperature
-30
85
Charge Pump
Charge Pump output
Voltage (pin VOUT)
VVOUT
Internay Limited
5.5
V
Charge Pump output
current
IVOUT
η
0.0
150
mA
%
Efficiency
75
All inernal timings are derivd from this
oscilator if no clock is applid on pin CLK32K
fCLK
Operating Frequency
-10%
2.0 +10% MHz
1:1 Mode
VBAT>=3.3V, IL0mA
1:1.5 Mode
0.65
3.3
Ω
Ω
Charge pump
effective resistance
RCP
Current Sources
LED1...LED9 output
ILED1..9
0.0
-7
25.5
+7
mA
%
current range
LED1...LED9 current
source accuracy
ILED1..9Δ
ILED = 17.5mA
ILED = 17.5mA
LED1...LED9 curret
source matching
ILED1..9
MATCH
2.5
0
%
LED1...LED9 leakge
current
ILED1..9
current source off
-5
+5
µA
LEAKAGE
LED1...LED9 current
surcvoltage
ompliance
Minimum voltage between pin VOUT and
LED1...LED9 or VBAT and LED7...LED9
VILED_COMP
100
mV
ADC
ADCRE
ADC resolution
10
Bits
ADC Integral non-
linearity
ADCIN
ADCDNL
ADCLSB
-2
-2
±0.2
+2
+2
LSB
ADC differential non-
linearity
±0.25
6.1
LSB
mV
LSB of ADC
conversion
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Electrical Characteristics Pin Description
Table 3. Electrical Characteristics (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
ADC temperature
measurement offset
value
ADCTOFFSE
T
393
ºC
Code temperature
coefficient
ºC/
Code
ADCTC
1.322
Temperature sensor
accuracy
TTOL
-10
+10
ºC
Audio Input
pin INT/AUDIO_IN if used as analog input;
at maximum input gain (+30dB)
RAUDIO_IN Audio Input resistance
20
kΩ
Digital Interface
High Level Input
VIH
1.26
0.0
VVBAT
0.54
0.2
V
V
Voltage
Pins SDA, SCL, EN, CLK32K, TRIG,
INT/AUDIO_IN, GPO1
Low Level Input
VIL
Voltage
Pins SDA, TRIG, INT/UDIOIN, GPO
IOL=3mA
Low Level Output
VOL
V
Voltage
Pins SDA, SCL, , CLK32K, TRIG, INT/
AUDGPO
ILEAK
Leakage Current
0.01
1.0
µA
I2C mode timings - see Figure 3 on page 7
fSCLK
SCL Clock Frequency
0
400
kHz
µs
Bus Free Time
Between a STOP and
START Condition
tBUF
1.3
Hold Time (Repeated)
START Condition2
tHD:STA
0.6
µs
LOW Period of SCL
Clock
tLOW
tHIGH
1.3
0.6
µs
µs
HIGH Period of SCL
Clock
Setup Time for a
Repeated START
Condition
tSU:STA
0.6
µs
Data Hold Time3
Data Setup Tim4
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
CB
0
0.9
µs
ns
100
20 +
0.1CB
Rise Timof Both
SDA and SCSignals
300
300
ns
ns
µs
pF
pF
20 +
0.1CB
Fall me of Both SDA
and CL Signals
Setup Time for STOP
Condition
0.6
Capacitive Load for
Each Bus Line
CB — total capacitance of one bus line in pF
400
10
I/O Capacitance
(SDA, SCL)
CI/O
If SCL and SDA are low for longer than this
time, the AS3665 is switched into shutdown
I2C timeout
tTIMEOUT
100
ms
mode5
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AS3665
Datasheet, Confidential - Electrical Characteristics Timing Diagrams
1. The logic input levels VIH and VIL allow for 1.8V supplied driving circuit
2. After this period the first clock pulse is generated.
3. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
4. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then
be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max +
tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
5. This feature can be disabled by setting auto_shutdown (see page 13)=0
Timing Diagrams
Figure 3. I2C mode Timing Diagram
SDA
t
BUF
t
LOW
t
D:STA
t
R
F
SCL
t
HD:STA
t
SU:STO
t
SU:STA
t
t
t
SU:DAT
HD:DAT
HIGH
REPEATED
START
STOP START
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AS3665
Datasheet, Confidential - Typical Operating Characteristics
7 Typical Operating Characteristics
VVBAT = 3.6V, TA = +25ºC (unless otherwise specified).
Figure 4. Efficiency vs. Battery voltage, ILEDS=50mA
Figure 5. IVBAT vs. Battery voltage, ILEDS=50mA
95
90
85
80
75
70
65
60
55
50
45
40
35
3
full bias = LEDX_max=25.5mA
1/4 bias = LEDX_max=6.3mA
full bias = LEDX_max=25.5mA
1/4 bias = LEDX_max=6.3mA
90
85
80
75
70
65
60
55
White LED,2.85V,full Bias
White ED,2.V,full Bias
White LE2.85V, 1/4 bias
RGB ATBG66,full bias
GB LABG66, 1/4bias
50
White LED,2.85V, 1/4 bias
RGB LATBG66,full bias
45
RGB LATBG66, 1/4bias
40
2.6
3
3.4
3.8
4.2
.6
3
3.4
3.8
4.2
Input Voltage (V)
Input Voltage (V)
Figure 6. ILEDS vs. Battery voltage
ure 7. ILED1 Linearitof current source vs. Code
52
25
20
15
10
51
50
49
48
White LED,2.85V,full Bs
White LED85V, 1/4 bias
RGB LATBG6ull bias
RGB LTG66, bias
5
TAM B=25deg
TAM B=85deg
TAM B=-25deg
0
2.6
3
3.4
3.8
4.2
0
50
100
150
200
250
Input Voltage (V)
Digital Code
Figure 8. ILED1 Monotony of curent source vs. Code
Figure 9. Logarithmic PWM ramp
0.5
25
0.4
0.3
0.2
0.1
0
20
15
10
5
.1
-0.2
-0.3
TAM B=25deg
TAM B=85deg
ILED
IBAT
-0.4
TAM B=-25deg
-0.5
0
0
50
100
150
200
250
0
50
100
150
200
250
Digital Code
Digital Code
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AS3665
Datasheet, Confidential - Typical Operating Characteristics
Figure 10. Logarithmic PWM ramp
Figure 11. ILED vs. Voltage on current source
100
25
LEDX_max=25.5mA
20
15
10
5
10
1
0.1
ILED=20mA
ILED=15mA
ILED=10mA
ILED=5mA
ILED
IBAT
0.01
0
0
50
100
150
200
250
0
0.2
0.4
0.6
8
1
Digital Code
Voltage on current sourc(V)
Figure 12. ILED vs. Voltage on current source
Figur13. ILD vs. Voltage on current source
30
20
LEDX_max=25.5mA
25
19
18
LEDX_max=19.1mA
20
15
10
5
LEDX_max=12.7mA
LEDX_max=6.3A
17
LEDX_max=19.1mA
LEDX_Current=19.1mA
16
ILED=6.3mA
TAM B=25deg
TAM B=85deg
TAM B=-20deg
ILED=12.7mA
ILED=19.1A
ILED=25.5A
0
15
0
0.2
0.4
0.6
0
1
0
0.2
0.4
0.6
0.8
1
Voltage on current source (V)
Voltage on current source (V)
Figure 14. CP in 1:1.5 mode, 150A load, ac-coupled
500ns/Div
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AS3665
Datasheet, Confidential - Detailed Description Timing Diagrams
8 Detailed Description
The AS3665 is a fixed frequency charge pump. Its output (VOUT) is connected to nine current sources (LED1..LED9).
A sophisticated command based pattern generator with three sequencers controls the nine PWM generators (12 bit
resolution), which are connected to the current sources.
Commands are downloaded to the AS3665 internal memory space and can be executed autonomously in the three
sequencers. The commands are optimized for lighting applications (e.g. a single command executes logarithmic up
dimming). It supports command flow control (like unconditional and conditional jumps). Variables which are accessible
through the I2C interface allow control of the program execution by the I2C interface and communication between the
three sequencers.
The three sequencers can be dynamically assigned to any of the nine outputs (under program control).
The AS3665 supports an audio input pin INT/AUDIO_IN which allows the control of patterns depending on an audio
input signal. This audio input can be feed through internal digital filters for better visual appearance.
If the audio feature is not used, the pin INT/AUDIO_IN can be used as interrupt output1 to send interupts.
The AS3665 is controlled by an I2C interface and additional dedicated control lines. An EN input oerateas a global
enable/disable pin and with the pin TRIG several AS3665 can be synchronized in a system. A searatCLK32K input
can be used to set an exact clock input frequency (all internal timins can be derived either frCL32K or an internal
oscillator). The I2C address is selectable by the pin ADDR - see 2C Addss selection on page 4A GPO pin can be
used for external control or as an additional ADC input.
The AS3665 supports LED testing (verification of the perfoe of the conneced LEDs in an assembled system).
Following blocks are included inside the AS3665:
- Low Noise charge pump operating in 1:1, 1:1.5 and 1:2
- Automatic mode switching of the charge pump u& down)
- 1MHz oscillator
- Internal LDO for powering the internal rcuitr
- Audio processing of an analog inpusigna
- Overtemperature Protection
- Temperature Measurements of tS3665
- 10 Bit ADC
- 9x12 bit, 1x8 bit PWM Generators
- 6 accurate current sources connected to VC
- 3 accurate current source configurabto be connected to VBAT or VCP (to improve efficiency e.g. of red LEDs)
- Internal memory for the program executn
- 3 sequencers (3 parallel processig its)
- a fully programmable multiplexer cocting the three sequencers to the 10 PWM generators
- Automatic shutdown to safe owe(if SCL and SDA=0 for 100ms)
1. INT/AUDIO_IN is an open drain output. Several interrupt can be easily combined externally.
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Detailed Description Internal Circuit
Internal Circuit
Figure 15. AS3665 internal circuit
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Detailed Description Device Operating Mode
Device Operating Mode
The operating mode is selected according to the following flowchart:
Figure 16. AS3665 operating mode selection
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After power on reset, the AS366waits until EN=1 and SCL=1 or SDA=12and then initializes its internal registers and
program memory. Once sanby mode is reached, the program and setup can be download to the AS3665 and by set-
ting chip_en=1 the progracan be executed.
2. SCL and SDA is monitored to detect if the I2C bus is powered. Therefore if EN is not used, it can be tied to
VBAT and the mode selection between shutdown and the other modes is performed by SCL and SDA.
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AS3665
Datasheet, Confidential - Detailed Description Device Operating Mode
If EN is pulled low or if the power from the I2C bus pullup resistors is removed3 for more than tTIMEOUT, the AS3665
enters shutdown4.
Table 4. Exec_Enable Register
Addr: 00h
Bit Name
Exec_Enable Register
Description
Bit
Default Access
Enables the active mode (see Figure 16)
AS3665 standby mode select.
Set cp_auto_on=0 before setting chip_en=0.
0
1
Output drivers disabled, I2C communication possible
chip_en
ram_init
6
0h
0h
R/W
R/W
AS3665 active mode select.
Set cp_auto_on=1 after setting chip_en=
All functions active, internal oscillator runnin.
Initialization of the internal memory (seFigure 16)
Memory initialization is fiishe
0
1
Writing: Reset internal prgram memory and all
register from 60h...FFh to their default state
eadingmemory initialization onoing; when finished
an interrupt an triggered
7
(init_ready_int (see page 37) is set)
The bit auto_shutdown controls the automatic entering of shtdown mode if the 2C bs is disabled:
Table 5. Supervision Register
Addr: 08h
Bit Name
Supvision Register
Description
Bit
DeauAccess
Eables the shutdown mode (see Figure 16)
AS3665 cannot enter shutdown
1
auto_shutdown
7
1h
R/W
do not set pin EN=0 if cp_auto_on=1 or cp_on=1
AS3665 can use shutdown
EN=0 can be used to enter shutdown mode
A complete reset cycle can be triggered by sting bit force_reset:
Table 6. Reset_Control Register
Addr: 3Ch
Reset_Control Register
Description
Bit
Bit Name
Default Access
Start reset cycle (see Figure 16)
Normal operation
0
1
forc_reset
0
0
R/W
Reset all registers from 00h...1Fh and 5Fh to their
default value
3. Therefore SCL and SDA both are low.
4. Unless auto_shutdown (see page 13)=0
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Detailed Description Clock Generation
Clock Generation
The AS3665 has an internal oscillator running at fCLK and an external clock input CLK32K:
Figure 17. Clock Generation
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The charge pump and the PWM generator use the fCLK cloignal from the intel oscillator. Depending on the sig-
nal sel_ext_clock, the internal timers and ramp generators ue either the pin CL32K s input or fCLK divided by 2 and
31:
Table 7. GPO_Control Register
Addr: 04h
Bit Name
O_Control Register
Description
Enbles the external clock on CLK32K (see Figure 17)
Bit
Deault Access
Use internal fCLK clock divided by 31*2
sel_ext_clock
6
0h
R/W
Use external clock on CLK32K (also
osc_always_on=0)1
1
1. Using an external clock has two advantage
a) Reduced quiescent current: the inerclock is switched off whenever possible and the timers run from
CLK32K.
b) All timings (e.g. ramp-up, wa) are as accurate as the external clock (usually derived from a crystal).
The external clock on CLK32K is monitored and if the internal clock is enabled and no valid clock are detected the reg-
ister bit no_extclock_detted (see page 37) is set and an interrupt can be triggered.
The internal osciatr ienabled and disabled automatically if register bit osc_always_on is reset:
Table 8. Supervision Register
ddr08h
Bit Name
Supervision Register
Description
Bit
Default Access
Enables the internal oscillator (see Figure 17)
Enable internal oscillator only if required
0
1
osc_always_on
5
0h
R/W
The internal oscillator is always running (except in
shutdown mode)
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Detailed Description Current Sources
Current Sources
The internal circuit of the current sources is shown in Figure 18 (one current source shown; internally there are 9 iden-
tical blocks):
Figure 18. Current Sources
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AS3665
The processing path consists of the follog step (using current source 1 as example):
1. The input of the complete urrent source block is the register pwm_LED1 (see page 22). This register can be
controlled by I2C directly or by any of the three sequencers (see section Sequencers on page 48).
2. The signal is conertefrom logarithmic domain to linear domain (depending on signal loglin1 (see page 25))
or multiplied by 16 to obtain 12 bits.
3. It passes adjstable fader (it can be multiplied by any of the fader registers fader1, fader2 or fader3). If
fader_src1 (ee page 25)=0, the fader is not used (signal is unchanged).
4. Color correction is performed (temp_int_ext (see page 24) selects either internal temperature measurement or
use the register led_temp (see page 24)). The gain of the color correction can be adjusted by color_slope1
e page 25). If color_slope1=0, color correction is disabled.
5. The resulting 12 bit signal goes to the PMW generator and then to the current source itself.
6The current source is enabled by LED1_on5 and its current is adjusted by LED_current1 and LED1_max.
5. LED1_on...LED9_on have only effect if all sequencer are switched off (p1_en (see page 46)=00 and
p2_en=00 and p3_en=00). This allow direct control of the LEDs if no program is executed.
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Detailed Description Current Sources
7. LED7, LED8 and LED9 have the option to be powered by VBAT directly (configured by
LED7_on_cp...LED9_on_cp)
Interface to sequencers
pwm_LED1 (see page 22), pwm_LED2...pwm_LED9 is the input PWM value of the current sources (8 bit value). This
value can be either controlled by the I2C interface or by any of the sequencers (see section Sequencers on page 48).
Logarithmic/Linear Ramping
All current sources support logarithmic or linear ramping (selected by register bits loglin1 (see page 25),
loglin2...loglin9). As light is perceived logarithmically, it is recommended to keep the current sources in logarithmic
mode (default setting).
RGB Color Correction
The RGB Color correction changes the output PWM value depending on the temperature (either the junction tepera-
ture if temp_int_ext (see page 24)=0, or a I2C value stored in led_temp (see page 24) if temp_int_ext=1). This compen-
sates different temperature drifts of LEDs and keep the white point over temperature. The slope of thitemperature
compensation is adjustable with the register color_slope1 (see page 25), color_slope2...color_slope(seto 0 if the
color correction is not used).
Faders
There are three global faders: fader1 (see page 23), fader2 and fder3. Each current sure an be configured to be
multiplied by any of the three faders (controlled by fader_(see page 25), fader_src2...fader_src9). Therefore a
fader can operate on any number of current sources in par(e.g. to generate ooth fade-out effects on several
LEDs). The faders can operate linear or logarithmic (defined by fader_loglin1 (see pae 23), fader_loglin2 and
fader_loglin3).
Analog Current Setting
All current sources can be completely enabld/disble by the regir LED1_on, LED2_on...LED9_on. The actual
analog current is set by LED_current1 (ee page 17), LED_curret2...LED_current9. The maximum current
6
driving capability of the current soures s set by registers LE1_max (see page 20), LED2_max...LED9_max .
Current Source Registers
Analog Current setting registers
Table 9. LED_Control1 Register
Addr: 02h
Bit Name
LED_Control1 Register
Description
Bit
Dult Access
0
1
0
1
0
1
0
1
0
1
LED1 is off
LED1 is enabled
LED2 is off
LED1_on
LED2_on
LED3_on
LED4_on
LED5_on
0
0b
0b
0b
0b
0b
R/W
R/W
R/W
R/W
R/W
1
2
3
4
LED2 is enabled
LED3 is off
LED3 is enabled
LED4 is off
LED4 is enabled
LED5 is off
LED5 is enabled
6. Always use the minimum setting for LED1_max, LED2_max...LED9_max suitable for the application to
reduce quiescent current of the internal current source
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Table 9. LED_Control1 Register
Addr: 02h
LED_Control1 Register
Description
Bit
Bit Name
Default Access
0
1
0
1
0
1
LED6 is off
LED6 is enabled
LED7 is off
LED6_on
5
0b
0b
0b
R/W
R/W
R/W
LED7_on
LED8_on
6
7
LED7 is enabled
LED8 is off
LED8 is enabled
Table 10. LED_Control2 Register
Addr: 03h
LED_Control2 Register
Bit
Bit Name
Default Access
0b R/W
Description
LED9 is off
0
1
LED9_on
0
LED9 is enaed
Table 11. LED_Current1 Register
Addr: 10h
LED_Current1 egister
Bit
Bit Name
Default Access
Description
Sets the curnt for current source on LED1
LED1_max
0
01
10
11
LED_current1
7:0
00
R/W
0
Current source off
0.1mA
25.5mA
74.9µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
255
Table 12. LED_Current2 Register
Addr: 11h
LED_Current2 Register
Description
Bit
Bit Name
Deult Access
Sets the current for current source on LED2
LED2_max
00
01
10
11
D_crrent2
7:0
00h
R/W
0
1
Current source off
0.1mA
25.5mA
74.9µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
...
255
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Table 13. LED_Current3 Register
Addr: 12h
LED_Current3 Register
Description
Bit
Bit Name
Default Access
Sets the current for current source on LED3
LED3_max
00
01
10
11
LED_current3
7:0
00h
R/W
0
1
Current source off
0.1mA
25.5mA
74.9µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
...
255
Table 14. LED_Current4 Register
Addr: 13h
LED_Current4 Register
Description
Bit
Bit Name
Default Access
Sets e current for current surce on LED4
LE4_mx
00
01
10
11
LED_current4
7:0
00h
R/W
1
Curent source off
0.1mA
.5m
749µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
...
255
Table 15. LED_Current5 Register
Addr: 14h
LED_Current5 Register
Description
Bit
Bit Name
Default Access
Sets the current for current source on LED5
LED5_max
00
01
10
11
LED_current5
7:0
R/W
0
1
Current source off
0.1mA
25.5mA
74.9µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
...
255
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Table 16. LED_Current6 Register
Addr: 15h
LED_Current6 Register
Description
Bit
Bit Name
Default Access
Sets the current for current source on LED6
LED6_max
00
01
10
11
LED_current6
7:0
00h
R/W
0
1
Current source off
0.1mA
25.5mA
74.9µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
...
255
Table 17. LED_Current7 Register
Addr: 16h
LED_Current7 Register
Description
Bit
Bit Name
Default Access
Sets e current for current surce on LED7
LE7_mx
00
01
10
11
LED_current7
7:0
00h
R/W
1
Curent source off
0.1mA
.5m
749µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
...
255
Table 18. LED_Current8 Register
Addr: 17h
LED_Current8 Register
Description
Bit
Bit Name
Default Access
Sets the current for current source on LED8
LED8_max
00
01
10
11
LED_current8
7:0
R/W
0
1
Current source off
0.1mA
25.5mA
74.9µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
...
255
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Table 19. LED_Current9 Register
Addr: 18h
LED_Current9 Register
Description
Bit
Bit Name
Default Access
Sets the current for current source on LED9
LED9_max
00
01
10
11
LED_current9
7:0
00h
R/W
0
1
Current source off
0.1mA
25.5mA
74.9µA
19.1mA
49.8µA
12.7mA
24.7µA
6.3mA
...
255
Table 20. LED_MaxCurr1 Register
Addr: 19h
LED_MaxCurr1 Register
Description
Bit
Bit Name
Default Access
Setthe mximum current for currnt source on LED1
ee LED_current1 on page 17)
0
ILED1 = 0...25.5mA
D1 = 0...19.1mA
LED1 = 0...12.7mA
ILED1 = 0...6.3mA
LED1_max
1:0
00b
00b
00b
R/W
R/W
R/W
R/W
10
11
Sets he mimm current for current source on LED2
(see LED_current2 on page 17)
00
ILED2 = 0...25.5mA
ILED2 = 0...19.1mA
ILED2 = 0...12.7mA
ILED2 = 0...6.3mA
LED2_max
LED3_max
LE4_max
3:2
5:4
7:6
01
11
Sets the maximum current for current source on LED3
(see LED_current3 on page 18)
00
ILED3 = 0...25.5mA
ILED3 = 0...19.1mA
ILED3 = 0...12.7mA
ILED3 = 0...6.3mA
01
10
11
Sets the maximum current for current source on LED4
(see LED_current4 on page 18)
00
ILED4 = 0...25.5mA
ILED4 = 0...19.1mA
ILED4 = 0...12.7mA
ILED4 = 0...6.3mA
01
10
11
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Table 21. LED_MaxCurr2 Register
Addr: 1Ah
LED_MaxCurr2 Register
Description
Bit
Bit Name
Default Access
Sets the maximum current for current source on LED5
(see LED_current5 on page 18)
00
ILED5 = 0...25.5mA
ILED5 = 0...19.1mA
ILED5 = 0...12.7mA
ILED5 = 0...6.3mA
LED5_max
1:0
00b
00b
00b
00b
R/W
R/W
R/W
R/W
01
10
11
Sets the maximum current for current source on LED6
(see LED_current6 on page 19)
00
ILED6 = 0...25.5mA
ILED6 = 0...19.1mA
ILED6 = 0...12.7mA
ILED6 = 0..3mA
LED6_max
LED7_max
LED8_max
3:2
5:4
7:6
01
10
11
Setthe maimum current for current source on LED7
(see LED_curreton page 19)
ED7 = 0...25.5mA
ILED= 0...19.1mA
ILED7 = 0...12.7mA
ILED7 = 0...6.3mA
0
10
11
Sets tmaximum current for current source on LED8
(see LED_current8 on page 19)
00
ILED8 = 0...25.5mA
ILED8 = 0...19.1mA
ILED8 = 0...12.7mA
ILED8 = 0...6.3mA
0
11
Table 22. LED_MaxCurr3 Register
Addr: 1Bh
LED_MaxCurr3 Register
Description
Bit
Bit Name
Default Access
Sets the maximum current for current source on LED9
(see LED_current9 on page 20)
00
ILED9 = 0...25.5mA
ILED9 = 0...19.1mA
ILED9 = 0...12.7mA
ILED9 = 0...6.3mA
LE9_mx
1:0
00b
R/W
01
10
11
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PWM Data Input Registers
Table 23. PWM_LED1, PWM_LED2...PWM_LED9, PWM_GPO Registers
Addr: 80h-89h
Bit
PWM_LED1, PWM_LED2...PWM_LED9, PWM_GPO Register
Addr
Name
Default Access
Description
PWM value for Current source on LED1
LED1 Off
0
...
pwm_LED1
pwm_LED2
pwm_LED3
pwm_LED4
pwm_LED5
pwm_LED6
pwmLED7
pwm_LED8
pwm_LED9
80h
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0
7:0
00h
00h
00h
00h
0h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
255
LED1 Full Scale
PWM value for Current source on LED2
LED2 Off
0
...
81h
82h
83h
84h
85h
86h
87h
88h
255
LED2 Full Scal
PWM value for Current source on LED3
LED3
0
...
5
LED3 Full Scale
PWM value for Current source on LED4
LED4 Off
0
...
255
LED4 Full Scale
PWM value for Current source on LED5
LED5 Off
0
5
LED5 Full Scale
PWM value for Current source on LED6
LED6 Off
0
...
255
LED6 Full Scale
PWM value for Current source on LED7
LED7 Off
0
...
255
LED7 Full Scale
PWM value for Current source on LED8
LED8 Off
0
...
255
LED8 Full Scale
PWM value for Current source on LED9
LED9 Off
0
...
255
LED9 Full Scale
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Table 23. PWM_LED1, PWM_LED2...PWM_LED9, PWM_GPO Registers (Continued)
Addr: 80h-89h
Bit
PWM_LED1, PWM_LED2...PWM_LED9, PWM_GPO Register
Addr
Name
Default Access
Description
PWM value for GPO PWM generator (8 bits)
PWM GPO Off
0
...
pwm_GPO
89h
7:0
00h
R/W
255
PWM GPO Full Scale
RGB Color correction, Fader and Logarithmic/Linear Registers
Table 24. LED_Control2 Register
Addr: 03h
Bit Name
LED_Control2 Register
Bit
Default Access
Description
Temperature compensation operang mode
Normal ode
0
1
temp_comp_mode1
3
0
R/W
Posite Values of correction: Normal operation
Negtive values of crrecton: correction value
divided b2
Fader 1 linr / logarithmic control
Linear Operation
fader_loglin1
fader_loglin2
fader_loglin3
4
5
6
0
0
0
R/W
R/W
R/W
0
1
Logarithmic Operation
der 2 linear / logarithmic control
Linear Operation
0
1
Logarithmic Operation
Fader 3 linear / logarithmic control
Linear Operation
1
Logarithmic Operation
1. Its safe to keep temp_comp_mode at defalt ‘0’
Table 25. Fader1, Fader2 and Fader3 Rters
Addr: 9B-9Dh
Fader1, Fader2 and Fader3 Register
Description
Addr
Bit
Nam
Default Access
Global Fader1 value
0
...
Off
fader1
9Bh
7:0
00h
00h
R/W
R/W
255
Full Scale
Global Fader2 value
Off
0
...
fader2
Ch
7:0
255
Full Scale
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Table 25. Fader1, Fader2 and Fader3 Registers (Continued)
Addr: 9B-9Dh
Bit
Fader1, Fader2 and Fader3 Register
Addr
Name
Default Access
Description
Global Fader3 value
Off
0
...
fader3
9Dh
7:0
00h
R/W
255
Full Scale
Table 26. Temp_Sense_ Control Register
Addr: 0Eh
Temp_Sense_ Control Register
Description
Bit
Bit Name
Default Access
The RGB color correction uses interal/external
source for temperature compension
(see RGB Color Correction on age 6)
temp_int_ext
0
0b
R/W
I2C register led_emp iused
0
1
inrnal junction temperature measured1
Internal temperature sensor enable
Internaemperature sensor off
temp_sens_on
1
2
0b
0b
R/W
R
1
Inernl temperature sensor on
Internal tempeature sensor busy status signal
Innatemperature sensor off or not busy
Internal temperature sensor busy
temp_meas_busy
0
1
1. Set temp_sens_on=1
Table 27. LED_Temp Register
Addr: 1Fh
LED_Temp Register
Description
Bit
Bit Name
Default Access
Value used for RGB color correction if temp_int_ext=1
(see RGB Color Correction on page 16)
185
-30ºC
25ºC
led_temp
7:0
00h
R/W
142
96
+85ºC
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Table 28. Driver_Setup1 Register
Addr: A0h
Driver_Setup1 Register
Description
Bit
Bit Name
Default Access
LED1 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope1
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED1 Logarithmic/Linear Ramping (sepage 16)
linear ramping/dimmin
logarithmic rampg/dimming
LED1 Faders (see page 16)
fader disaled
loglin1
5
1b
R/W
R/W
0
1
0
10
11
fader_src1
7:6
00b
use der1 (see page 23)
use fader2
use fader3
Table 29. Driver_Setup2 Register
Addr: A1h
Driver_Setup2 Register
Bit
Bit Name
fault Access
Description
LED2 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope2
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED2 Logarithmic/Linear Ramping (see page 16)
linear ramping/dimming
logarithmic ramping/dimming
LED2 Faders (see page 16)
fader disabled
logn2
5
1b
R/W
R/W
0
1
00
01
10
11
fader_src2
:6
00b
use fader1 (see page 23)
use fader2
use fader3
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Table 30. Driver_Setup3 Register
Addr: A2h
Driver_Setup3 Register
Description
Bit
Bit Name
Default Access
LED3 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope3
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED3 Logarithmic/Linear Ramping (sepage 16)
linear ramping/dimmin
logarithmic rampg/dimming
LED3 Faders (see page 16)
fader disaled
loglin3
5
1b
R/W
R/W
0
1
0
10
11
fader_src3
7:6
00b
use der1 (see page 23)
use fader2
use fader3
Table 31. Driver_Setup4 Register
Addr: A3h
Driver_Setup4 Register
Bit
Bit Name
fault Access
Description
LED4 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope4
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED4 Logarithmic/Linear Ramping (see page 16)
linear ramping/dimming
logarithmic ramping/dimming
LED4 Faders (see page 16)
fader disabled
logn4
5
1b
R/W
R/W
0
1
00
01
10
11
fader_src4
:6
00b
use fader1 (see page 23)
use fader2
use fader3
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Table 32. Driver_Setup5 Register
Addr: A4h
Driver_Setup5 Register
Description
Bit
Bit Name
Default Access
LED5 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope5
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED5 Logarithmic/Linear Ramping (sepage 16)
linear ramping/dimmin
logarithmic rampg/dimming
LED5 Faders (see page 16)
fader disaled
loglin5
5
1b
R/W
R/W
0
1
0
10
11
fader_src5
7:6
00b
use der1 (see page 23)
use fader2
use fader3
Table 33. Driver_Setup6 Register
Addr: A5h
Driver_Setup6 Register
Bit
Bit Name
fault Access
Description
LED6 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope6
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED6 Logarithmic/Linear Ramping (see page 16)
linear ramping/dimming
logarithmic ramping/dimming
LED6 Faders (see page 16)
fader disabled
logn6
5
1b
R/W
R/W
0
1
00
01
10
11
fader_src6
:6
00b
use fader1 (see page 23)
use fader2
use fader3
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Table 34. Driver_Setup7 Register
Addr: A6h
Driver_Setup7 Register
Description
Bit
Bit Name
Default Access
LED7 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope7
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED7 Logarithmic/Linear Ramping (sepage 16)
linear ramping/dimmin
logarithmic rampg/dimming
LED7 Faders (see page 16)
fader disaled
loglin7
5
1b
R/W
R/W
0
1
0
10
11
fader_src7
7:6
00b
use der1 (see page 23)
use fader2
use fader3
Table 35. Driver_Setup8 Register
Addr: A7h
Driver_Setup8 Register
Bit
Bit Name
fault Access
Description
LED8 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope8
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED8 Logarithmic/Linear Ramping (see page 16)
linear ramping/dimming
logarithmic ramping/dimming
LED8 Faders (see page 16)
fader disabled
logn8
5
1b
R/W
R/W
0
1
00
01
10
11
fader_src8
:6
00b
use fader1 (see page 23)
use fader2
use fader3
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Table 36. Driver_Setup9 Register
Addr: A8h
Driver_Setup9 Register
Description
Bit
Bit Name
Default Access
LED9 RGB Color Correction (see page 16) slope
00h
01h
...
RGB Color Correction disabled
+0.15%/ºC
...
+2.263%/ºC
color_slope9
4:0
00h
R/W
0Fh
11h
...
-2.263%/ºC
...
1Fh
-0.15%/ºC
LED9 Logarithmic/Linear Ramping (sepage 16)
linear ramping/dimmin
logarithmic rampg/dimming
LED9 Faders (see page 16)
fader disaled
loglin9
5
1b
R/W
R/W
0
1
0
10
11
fader_src9
7:6
00b
use der1 (see page 23)
use fader2
use fader3
Charge Pump
The charge pump used the two flying capcitorCFLY1 and CFYto oprate in 1:1, 1:1.5 and 1:2 mode boosting the
input supply VBAT to VOUT (shown in igur19). An implemnted soft start mechanism reduces the inrush current.
Battery current is smoothed when switg the charge pump on and also at each switching condition. This precaution
reduces electromagnetic radiation signicantly.
Figure 19. Charge Pump
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AS3665
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Detailed Description Charge Pump
The operating modes are controlled according to the following tables:
Table 37. CP_Control Register
Addr: 05h
Bit Name
CP_Control Register
Bit
Default Access
Description
Operating mode of charge pump (in manual mode sets the
operating mode, in automatic mode reports the mode)
00
01
10
11
1:1 mode
1:1.5 mode
cp_mode
1:0
00b
00b
R/W
R/W
1:2 mode
reserved - don’t use
Mode switching control
00
01
10
1:1, 1:1.5 automatically up and dwn switching
1:1, 1:1.5 automatically up witcing
1:1, 1:1.5, 1:2 automaically up switching
cp_mode_switching
3:2
11 Manuamode switching; mode efined by cp_mode
Autmatically switch on thchae pump if required
Charge pump should be enabled by cp_on
cp_auto_on
cp_on
4
5
1b
0b
R/W
R/W
CP is automaticallenabled if a current source is
enabled1
1
Automatiswitch on the charge pump if required
he charge pump stays in 1:1 mode
(unless cp_auto_on is set)
0
1
Enable manual or automatic mode switching
Control the hysteresis for down switching
from 1:1.5 to 1:1 mode
00
01
10
11
default hysteresis
cp_down_hyst
7:6
00b
/W
default-75mV hysteresis
default-150mV hysteresis
default-225mV hysteresis
1. Exception: LED7...LED9 if conected to VBAT. Defined by register LED7_on_cp, LED8_on_cp and
LED9_on_cp.
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AS3665
Datasheet, Confidential - Detailed Description Charge Pump
The charge pump starts operation always in 1:1 mode and returns back to 1:1 mode if all current sources are switched
off7. If the voltage across a enabled current source is no longer sufficient to operate the current source, the charge
pump automatically select the next operating mode (which modes are allowed is controlled by cp_mode_switching.
cp_auto_on or cp_on should be set for enabling this logic). In 1:1.5 mode and if cp_mode_switching=00, the charge
pump also can automatically switch back into 1:1 mode if the voltage across all current sources is sufficiently high to
use the more efficient 1:1 mode (a fine adjustment of this hysteresis is possible with cp_down_hyst).
Table 38. CP_Mode_Switch Register
Addr: 06h
Bit Name
CP_Mode_Switch Register
Bit
Default Access
Description
Configure if LED7 is powered by charge pump
LED7 is powered by VBAT (e.g. red LED
LED7 is powered from VOUT
LED7_on_cp
LED8_on_cp
LED9_on_cp
cp_max_5V4
0
1b
1b
1b
0b
R/W
R/W
R/W
R/W
0
1
Configure if LED8 is powered by chage pump
LED8 is powered by VBAT (e.. red LED)
LED8 is powerefrom VOUT
1
2
3
0
1
Confgue if LED9 is powered bcharge pump
LED9 is powered by VBT (e.g. red LED)
LEDpowered from VOUT
0
Ajusts the maximuoutt voltage of the charge pump
0
1
chargpump VOUT regulates to 4.5V
charpump VOUT regulates to maximum 5.4V
llows pulse skip mode of charge pump
Pulse skip of charge pump is disabled
0
cp_skip_on
4
5
1b
1b
R/W
RW
Enable pulse skip of charge pump in low load
conditions (reduce quiescent current in 1:1.5 mode)
Iall current sources are off, reset the charge pump back to
1:1 mode
cp_auto_reset
0
1
charge pump keeps last mode
Reset charge pump to 1:1 if all current sources are off
Application Hint
Its usually safe to keep the default valus of the charge pump registers. Only if a red LED is used (on LED7...LED9),
reset the register bits LED7_oncp=0, LED8_on_cp=0 and/or LED9_on_cp=0 to improve efficiency.
7. Exception: The manual mode switching mode (cp_mode_switching=11) can override this behavior.
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Detailed Description General Purpose Output
General Purpose Output
The general purpose output ball can be used as an open drain PWM output pad, an ADC input or as a general purpose
open drain output.
Table 39. LED_Control2 Register
Addr: 03h
Bit Name
LED_Control2 Register
Description
Bit
Default Access
Enable PWM generator driving GPO
GPO PWM generator is off
GPO_on
7
0b
R/W
0
1
GPO PWM generator is enabled
The output pad GPO is controlled by register GPO_Control:
Table 40. GPO_Control Register
Addr: 04h
GPO_Control Register
Bit
Bit Name
Default Access
Description
Dfine operating mode of GPO ball
open draiWoutput
00
1
11
gpo_mode
1:0
00b
0b
R/W
/W
open draoutput of signal gpo_signal
don’t use
Ss of GPO ball if gpo_mode=01
active low
gpo_signal
2
0
1
tristate or if used for ADC
Analog to Digital Converte
The AS3665 has a built-in 10-bit successive approximatinalog-to-digital converter (ADC). It is internally supplied
by C2V5, which is also the full-scale input range (0defines the ADC zero-code). For input signal exceeding C2V5 (typ.
2.5V) a resistor divider is used to scale the input of e ADC converter.
Table 41 shows the resolution and input rangs.
Table 41. ADC Input Ranges
Channel
Pin oSignal
Input Range
VLSB
Note
pin INT/AUDIO_IN if
used witaudio buffer
see section Audio
Input on page 34
0h
0.0V - 2.5V
NA
unction temperature
ADCTEMPCODE
1h
-30ºC - 125ºC
0.0V - VBAT
0.0V - VOUT
ADCTC
ADCLSB
ADCLSB
see EQ 1
INT/AUDIO_IN,
GPO, VBAT
internal voltage
divider
3h-5h
6h-Fh
VOUT, LED1,
LED2...LED9
internal voltage
divider
Thjunction temperature can be calculated according to following formula (ADCTEMPCODE is the result of the ADC
convsion from channel 1h):
TJUNCTION [ºC] = ADCTOFFSET - ADCTC * ADCTEMPCODE
(EQ 1)
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AS3665
Datasheet, Confidential - Detailed Description Analog to Digital Converter
The ADC is controlled by:
Table 42. ADC_Control Register
Addr: 09h
Bit Name
ADC_Control Register
Bit
Default Access
Description
Select ADC channel to be converted
Audio Buffer (uses pin INT/AUDIO_IN and audio input
amplifier - see section Audio Input on page 34)
0h
1h
1
ADCTEMPCODE
2h
3h
don’t use
INT/AUDIO_IN
GPO2
4h
5h
6h
7h
8h
Bh
Ch
Dh
Eh
Fh
VBAT
VOUT
adc_select
3:0
0h
R/W
LED
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
Enable ADC continuous conversion
no continuous conversion
1
adc_continuous
5
1b
/W
ADC is continuously converting. If a conversion is
finished an interrupt can be sent (register bit adc_eoc
on page 37)
select ADC conversion time
16µs ADC conversion time
32µs ADC conversion time
adc_slow
6
7
0b
R/W
W
0
1
writing ‘1’ starts a single ADC conversion. If a conversion is
finished an interrupt can be sent (register bit adc_eoc)
adc_single_conersin
1. Set temp_sen_on (se page 24)=1 before the measurement
2. set gpo_signal=1 nd gpo_mode=01 to switch pad GPO into tristate
The ADC sult is stored in registers adc<9:3> and adc<2:0>; a running conversion is identified by result_not_ready:
Tble 43ADC_MSB_Result Register
Addr: 0Ah
Bit Name
adc<9:3>
ADC_MSB_Result Register
Description
Bit
Default Access
NA
6:0
R
ADC Result bits 9:3 (MSBs)
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AS3665
Datasheet, Confidential - Detailed Description Audio Input
Table 43. ADC_MSB_Result Register (Continued)
Addr: 0Ah
ADC_MSB_Result Register
Description
Bit
Bit Name
Default Access
Indicates end of ADC conversion cycle
Result is ready
result_not_ready
7
NA
R
0
1
Conversion is running
Table 44. ADC_LSB_Result Register
Addr: 0Bh
ADC_LSB_Result Register
Description
Bit
Bit Name
Default Access
NA
adc<2:0>
2:0
R
ADC Result bits 2:0 (LSBs)
Audio Input
Figure 20. Audio Input internal Circuit
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AS3665
The audio input can be used to connect an analog audio signal to the AS3665 and do lighting effects dependent on this
input signal on pad INT/AUDIO_IN8.
The audio processing path is shown in ig20: The audio signal is amplified by the input amplifier with an adjustable
gain setting to allow different audio input ls. With the ADC the signal is converted into a digital 10 bits signal. After
the AGC, the data is filtered and ten can be used with the sequencer command Get ADC (see page 67). The
sequencers can then run differnt fter and processing algorithms to obtain the lighting effects.
Table 45. Audio_Control Rester
Addr: 1Ch
Bit Nme
Audio_Control Register
Description
Bit
Default Access
Enable AGC and Peak Detect for audio processing
Get ADC gets ADC value directly
0
1
audio_on
0
0b
R/W
Get ADC uses AGC and audio filter -recommended
setting if a audio signal is connected to the AS3665
8. Set int_mode=01 (analog input for ball INT/AUDIO_IN) and set adc_select=0 (to select audio buffer)
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AS3665
Datasheet, Confidential - Detailed Description Audio Input
Table 45. Audio_Control Register (Continued)
Addr: 1Ch
Audio_Control Register
Description
Bit
Bit Name
Default Access
Modifies the behavior for over/underflow with the
sequencer adder and subtract commands
0
1
A over/underflow rolls over
audio_cmdset
1
0b
0b
R/W
R/W
The adder/subtract command saturate
at zero and full scale1
Enable audio input buffer
Off
0
1
audio_buf_on
2
any selection of adc_select possible
On
adc_select=0 (audio buffer) mandatory
Audio input buffer gain setng
000
001
010
1
101
110
111
-12dB
-6dB
0dB
audio_buf_gain
5:3
7:6
000b
R/W
R/W
+6dB
+12dB
+18dB
+24dB
+30dB
reserved
0b
reserved - always set to 00b
1. For audio processing always set au_cmdset=1
AGC (Automatic Gain Control)
The AGC is used to ‘compress’ the input signal anto ttenuate very low input amplitude signals (this is performed to
ensure no light output for low signals especally for noisy input signals).
The AGC monitors the input signal amplitde ad filters this amplitude with a filter with a short attack time, but a long
decay time (decay time depends on the reer agc_ctrl). This amplitude measurement (represented by an integer
value from 0 to 15; the decay time of this asurement is controlled by agc_time) is then used to amplify or attenuate
the input signal with one of the folowinamplification ratios (output to input ratio) – the curve A, B, or C is selected
depending on the register agc_trl:
Table 46. AGC gain curvs
Input Amplitude
AGC gain
curve B
0.0
curve A
0.0
curve C
0.0
0
1
2
3
4
5
6
7.5
5.0
3.5
7.0
4.0
3.0
4.5
3.5
2.5
3.5
3.0
2.0
3.0
2.5
1.5
2.5
2.5
1.5
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AS3665
Datasheet, Confidential - Detailed Description Interrupt Generator
Table 46. AGC gain curves
Input Amplitude
curve A
AGC gain
curve B
2.0
curve C
1.5
2.0
2.0
1.5
1.5
1.5
1.0
1.0
1.0
1.0
7
8
2.0
1.5
9
2.0
1.5
10
11
12
13
14
15
1.5
1.0
1.5
1.0
1.5
1.0
1.0
1.0
1.0
1.0
1.0
.0
Table 47. Audio_AGC Register
Addr: 1Dh
Au_AGC Register
Bit
Bit Name
Default Access
Descrption
Control AGC transfer function
AC off (bypass)
0
001
attenuate w aplitude signals otherwise linear
respnse (to remove e.g. noise)
010
011
10
111
AGC urvA; slow decay of amplitude detection
AGC curve A; fast decay of amplitude detection
AGC curve B; slow decay of amplitude detection
AGC curve B; fast decay of amplitude detection
AGC curve C; slow decay of amplitude detection
AGC curve C; fast decay of amplitude detection
agc_ctrl
2:0
000b
R/W
AGC amplitude detection decay time; minimum duration
from min. gain to max. gain
00
460ms
920ms
agc_time
4:3
b
R/W
01
10
11
1840ms
3670ms
Interrupt Generator
The interrupt generaor can send interrupt signals to e.g. the application processor to identify e.g. the end of pattern or
a special evet. Wen a not masked interrupt (register Interrupt_Mask) is triggered the INT/AUDIO_IN9 pin is pulled
low until interrupt is reset by the I2C interface.
Ierrupt re eadout by the Interrupt_Status register; pending interrupts are reset by writing back ‘1’ to the register bit
in Inerrupt_Status which should be reset:
Following procedure to readout the interrupt is recommended:
9. The output should be enabled by setting register int_mode=00 (open drain interrupt output)
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AS3665
Datasheet, Confidential - Detailed Description Interrupt Generator
1. Readout Register Interrupt_Status
2. Write back the readout value in (1) to Interrupt_Status - this automatically resets all readout interrupts (and no
interrupts can be lost)
Table 48. Interrupt_Status Register
Addr: 0Ch
Bit Name
Interrupt_Status Register
Description
Bit
Default Access
Sequencer 1 has triggered an interrupt
see End/Interrupt command on page 54
int1
int2
int3
0
0
0
0
R/W
R/W
R/W
0
1
No interrupt
Interrupt pending
Sequencer 2 has triggered an interrupt
see End/Interrupt command on page 54
1
2
0
1
No interrupt
Interrupt pending
Sequencer 3 has triggeed an nterrupt
see End/Interrupt commanon page 54
0
No nterrupt
Interrupt pending
onitor external clock etection on pin CLK32K - see
Clock eneration on page 14
no_extclock_detected
3
0
R/W
0
External cck is ok or internal clock is selected
Exteclock is selected and no external clock is
detected
1
seDevice Operating Mode on page 12
Initialization of the internal data of AS3665 is ongoing
Initialization of the AS3665 is finished
init_ready_int
adc_eoc
4
5
6
0
0
0
R/W
R/W
R/W
0
ADC end of conversion -
see Analog to Digital Converter on page 32
0
1
ADC not started or conversion ongoing
ADC has finished a conversion
see Temperature Supervision on page 39
Temperature ok
ov_temp
0
1
Overtemperature detected
Interrupts can be enabled disabled individually by the Interrupt_Mask register (if an interrupt is masked, it will not pull-
down the pin INTAUDI_IN):
Table 49. Interrupt_ask Register
ddr0Dh
Bit Name
Interrupt_Mask Register
Description
Bit
Default Access
0
1
0
1
No Mask
int1_masked
int2_masked
1
1
R/W
R/W
int1 is masked
No Mask
1
int2 is masked
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AS3665
Datasheet, Confidential - Detailed Description Interrupt Generator
Table 49. Interrupt_Mask Register (Continued)
Addr: 0Dh
Interrupt_Mask Register
Description
Bit
Bit Name
Default Access
0
1
0
1
0
1
0
1
0
1
No Mask
int3_masked
2
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
int3 is masked
No Mask
no_extclock_detected_m
asked
3
4
5
6
no_extclock_detected is masked
No Mask
init_ready_int is masked
No Mask
init_ready_int_masked
adc_eoc_masked
ov_temp_masked
adc_eoc is masked
No Mask
ov_temp is masked
The interrupt output pad INT/AUDIO_IN is controlled by register GPO_ontrol:
Table 50. GPO_Control Register
Addr: 04h
Bit Name
GPO_Control Register
Bit
Default Access
Decription
Define opeting mode of INT/AUDIO_IN ball
en drain output of interrupt status
push/pull output of signal int_signal
00
01
10
int_mode
4:3
00b
R/W
analog input -
use for Audio Input (see page 34) or
Analog to Digital Converter (see page 32)
11
Status of INT/AUDIO_IN ball if int_mode=01
active low
int_signal
5
7
0b
R/W
R/W
0
1
active high (VBAT)
Interrupt output selection flag
Interrupt status is available on ball INT/AUDIO_IN
(if int_mode=00)
0
1
int_on_trig
Interrupt status is available on ball TRIG1
1. Set int_on_trig=1 if the ball INT/AUDIO_IN is used for audio and/or ADC and an interrupt output is required;
the ball TRIG is then usd as the interrupt open drain output
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AS3665
Datasheet, Confidential - Detailed Description Trigger pin TRIG
Trigger pin TRIG
Trigger commands can be sent by the internal sequencers to any other sequencer and or to/from the pin TRIG using
the sequencer command Trigger (see page 55). The pin TRIG is active low, requires and external pullup resistor and
the input should be enabled by setting trig_input_on=1.
Table 51. Exec_Mode Register
Addr: 01h
Bit Name
Exec_Mode Register
Description
Bit
Default Access
Enable external trigger input on pin TRIG
External trigger disabled
trig_input_on
7
0b
R/W
0
1
External trigger enabled
Sent external trigger commands are three 32.768kHz clock cycles (see Clock Generation on page 14) long and
received external triggers shall be longer than two clock cycles. During sending of an external trigger, he TRIG input is
blocked.
Note: If two AS3665 devices send an external trigger at the exactly same time, the trigger command might get lost.
Therefore it is recommended that only one AS3665 in a system should send trigger command and all other
devices only receive trigger commands.
It is recommend to configure trig_input_on before ogram execution as changing trig_input_on during pro-
gram execution can set a trigger pulse to the progr
LED Test
To test the LED in the production line, force a test curet through the to tesd LED. Measure the voltage on the
LED (by setting adc_select (see page 33) to thLED channel LED1...L9). If the voltage on the LED is within the
specified parameters for the LED, the LED iworkng properly.
Temperature Supervision
The temperature supervision protect tAS3665 against rtemperature - in case of overtemperature the AS3665 is
reset (and therefore the charge pump is set back to 1:1 and all current sources are switched off). It is recom-
mended to leave the temperature supervision always enabled (register bit ov_temp_on, default on):
Table 52. Supervision Register
Addr: 08h
Bit Name
Supervision Register
Description
Bit
Delt Access
Overtemperature protection
Overtemperature protection disabled
Overtemperature protection enabled
Overtemperature protection triggered
No overtemperature detected
ov_temp_on1
0
1h
0h
R/W
R/W
0
1
otem_status
1
0
1
Overtemperature detected
1. Alwayave ov_temp_on set.
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AS3665
2
Datasheet, Confidential - Detailed Description I C mode Serial Data Bus
I2C mode Serial Data Bus
The AS3665 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the
bus access, and generates the START and STOP conditions must control the bus. The AS3665 operates as a slave on
the I2C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode (400kHz
maximum clock rate) are defined. The AS3665 works in both modes. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
I2C Address selection
The slave address can be selected depending on the external resistor RADDR connected to the pin ADDR. The acu
address for reading and writing is selected according to Table 53.
Table 53. I2C Address Selection
I2C Address1 for
RADDR
Writing
80h
Readin
81
> 320kΩ (leave RADDR open)
320kΩ
160kΩ
82h
83h
h
85h
80kΩ
8
87h
40kΩ
88
89h
20kΩ
8Ah
8Ch
8Eh
8Bh
8Dh
8Fh
10kΩ
0kΩ (short to GND)
1. This I2C address has 8 bits and inclues the R/W flag (LSBIf a 7 bits address is required, use the 7 MSBs.
The following bus protocol has been defined (Figure 21)
ꢀ
ꢀ
Data transfer may be initiated only when the bs is not busy.
During data transfer, the data line must remain sable whenever the clock line is HIGH. Changes in the data line
while the clock line is HIGH are interpretd as control signals.
Accordingly, the following bus conditions hve been defined:
Bus Not Busy
Both data and clock lines remain IGH
Start Data Transfer
A change in the state of thdata line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
Stop Data Transer
A change in te state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
Data V
Te state f the data line represents valid data when, after a START condition, the data line is stable for the duration of
the IGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal.
There s one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes
transferred between START and STOP conditions are not limited, and are determined by the master device. The
information is transferred byte-wise and each receiver acknowledges with a ninth bit.
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AS3665
2
Datasheet, Confidential - Detailed Description I C mode Serial Data Bus
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The
master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the
SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold
times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge
bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to
enable the master to generate the STOP condition.
Figure 21. Data Transfer on I2C Serial Bus
SDA
MSB
SLAVE
ADDRESS
R/W
DIRECTION
BIT
ACKNOWLDGENT
SIGNAL ROM
RECEIVE
ACKNOWLEDGMENT
SIAL FROM
RR
SCL
1
2
1
6
7
8
2
9
-8
ACK
STOP CONDITION
OR REPEATED
START CONDITION
START
CONDITION
REPEATED IF
MOE BYTES ARE
TRANSFERRED
Depending upon the state of the R/W two types of daanser are possible:
1. Data transfer from a master transmitter to a receiver. The first byte transmitted by the master is the
slave address. Next follows a number of dta bytes. The slave returns an acknowledge bit after each received
byte. Data is transferred with the most signficat bit (MSB) first.
2. Data transfer from a slave transmtter to a master receiver. The master transmits the first byte (the slave
address). The slave then returns an aknowledge bit, followed by the slave transmitting a number of data
bytes. The master returns an aknledge bit after all received bytes other than the last byte. At the end of the
last received byte, a “not acknowge” is returned. The master device generates all of the serial clock pulses
and the START and STOconditions. A transfer is ended with a STOP condition or with a repeated START
condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not
released. Data is transfeed with the most significant bit (MSB) first.
The AS3665 can operate n the following two modes:
1. Slave RecevMode (Write Mode): Serial data and clock are received through SDA and SCL. After each
byte is recved an acknowledge bit is transmitted. START and STOP conditions are recognized as the begin-
ning and end f a serial transfer. Address recognition is performed by hardware after reception of the slave
addres and direction bit (see Figure 22). The slave address byte is the first byte received after the master
gerates the START condition. The slave address byte contains the 7-bit AS3665 address, which is
00XX10, followed by the direction bit (R/W), which, for a write, is 0.11 After receiving and decoding the
slave address byte the device outputs an acknowledge on the SDA line. After the AS3665 acknowledges the
slave address + write bit, the master transmits a register address to the AS3665. This sets the register pointer
on the AS3665. The master may then transmit zero or more bytes of data (if more than one data byte is written
10.’XXX’ depends on the external resistor RADDR used; see I2C Address selection on page 40
11.The address for writing to the AS3665 is 8Xh = 1000XXX0b - see Table 53
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AS3665
2
Datasheet, Confidential - Detailed Description I C mode Serial Data Bus
see also Blockwrite/read boundaries on page 43), with the AS3665 acknowledging each byte received. The
address pointer will increment after each data byte is transferred. The master generates a STOP condition to
terminate the data write.
2. Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode.
However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmit-
ted on SDA by the AS3665 while the serial clock is input on SCL. START and STOP conditions are recognized
as the beginning and end of a serial transfer (Figure 23 and Figure 24). The slave address byte is the first byte
received after the master generates a START condition. The slave address byte contains the 7-bit AS3665
address, which is 1000XXX, followed by the direction bit (R/W), which, for a read, is 1.12 After receiving and
decoding the slave address byte the device outputs an acknowledge on the SDA line. The AS3665 then
begins to transmit data starting with the register address pointed to by the register pointer (if more than one
data byte is read see also Blockwrite/read boundaries on page 43). If the register pointer is not written to
before the initiation of a read mode the first address that is read is the last one stored in the register pointer
The AS3665 must receive a “not acknowledge” to end a read.
Figure 22. Data Write - Slave Receiver Mode
ta(+X)>
XXXXXXXX
<Word Address (n)>
XXXXXXXX
Datn+1)>
XXXXXXXX
<Slave Address>
1000XXX
<Data(n)>
S
0
A
A
XXXXXXX
A
P
S - Start
A - Acknowledge (ACK)
P - Stop
Data Transferre
(X + 1 Bytes + Anowlege)
Figure 23. Data Read (from Current Pointer Location) - Transmitter Mode
<Data(n+X)>
XXXXXXXX
<Slave Address>
1000XXX
<Data(n)
<Data(n+1)>
XXXXXXXX
<Data(n+2)>
XXXXXXXX
S
1
A
XXXXXXX
A
A
A
NA
P
S - Start
A - Acknowledge (AK)
P - Stop
Data Transferred
(X + 1 Bytes + Acknowledge)
Note: Last data byte is followed by a NACK
NA - Not Acknedge ACK)
12.The address for read mode from the AS3665 is 8Xh+1 = 1000XXX1b - see Table 53
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Datasheet, Confidential - Detailed Description I C mode Serial Data Bus
Figure 24. Data Read (Write Pointer, Then Read) - Slave Receive and Transmit
<Word Address (n)>
XXXXXXXX
<Slave Address>
1
A
S
1000XXX
0
A
A
Sr
1000XXX
<Data(n+1)>
XXXXXXXX
<Data(n+2)>
XXXXXXXX
<Data(n+X)>
XXXXXXXX
<Data(n)>
XXXXXXXX
A
A
A
NA
P
S - Start
Sr - Repeated Start
A - Acknowledge (ACK)
P - Stop
Data Transferred
(X + 1 Bytes + Acknowledge)
Note: Last data byte is followed by a NACK
NA -Not Acknowledge (NACK)
Blockwrite/read boundaries
If more than a single data-byte is written to or read from the AS365 the ddress boundaes dscribed in Table 54shall
not be crossed13
:
Table 54. Blockwrite/read boundaries
Area
Area 1
Start
00h
10h
19h
End
0Fh
18h
3Eh
Area 2
Area 3
Area 4 - Program Page Select
Area 5 - Program Access
Area 7
5Fh
D0h
7Fh
CEh
DFh
Area 8 - SRAM
FEh - special I2C command
Area 9 - Program Direct Access
Program Downloading
There are two possibilities to download programs - Program Direct Access and Program Download using Page
Select14
:
Program Direct Access
Wring to I2C register Progrm_Direct_Access allows direct access to the complete internal program memory using a
single blockwrite mmad. Program downloading starts from address <n> and each program word is transferred with
two I2C bytes (MSB fist) as shown in Figure 25.
13.A single blockread or write shall not operate e.g. from 5Fh to 62h.
14.Choose the type of program download which fits best to the I2C controller
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Datasheet, Confidential - Detailed Description I C mode Serial Data Bus
Figure 25. Program Write - Slave Receiver Mode
<FEh>
<Slave Address>
1000XXX
Program_Direct_Access <Addr.-start: n>
A
S
0
A
11111110
A
XXXXXXXX
<Program(n)-LSB> <Program(n+1)-MSB>
<Program(n+X)-LSB>
A
XXXXXXXX
<Program(n)-MSB>
XXXXXXXX
P
A
XXXXXXXX
A
XXXXXXXX
A
S - Start
Data Transferred
A - Acknowledge (ACK)
P - Stop
(X + 1 program words + Acknowledge)
Note: Each program word has 2x8 Bits
Program Download using Page Select
First the register page_select is set to the program page, which shoud be accessed. Then throgrm page (part of or
full page) can be downloaded to the registers Cmd_0_MSB, Cm_0_LS, Cmd_1_MSB, Cmd__LSB...Cmd_F_MSB,
Cmd_F_LSB (I2C registers area 60h to 7Fh)15
Table 55. Page_Select Register
Addr: 5Fh
.
Page_Select Regser
Description
Bit
Bit Name
Default Access
Sts program page for download
page 0 - Addr 00h-0Fh
page 1 - Addr 10h-1Fh
page 2 - Addr 20h-2Fh
page 3 - Addr 30h-3Fh
page 4 - Addr 40h-4Fh
page 5 - Addr 50h-5Fh
don’t use
000
001
010
100
101
110
111
page_select
2:0
000b
R/W
don’t use
15.Setting page_select and writing of the program content shall use separate I2C commands (see Blockwrite/
read boundaries on page 43)
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AS3665
Datasheet, Confidential - Programming Concept
9 Programming
Concept
The internal structure for the sequencers, memory, PWM generator and I2C map is shown in Figure 26:
Figure 26. Internal Sequencers Structure
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The AS3665 includes three program corolled sequencers oprating on the internal memory. Each of these sequenc-
ers can be dynamically mapped to anthe PWM gen. Each of the PWM controllers has following structure:
Figure 27. PWM Controllers
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AS3665
Datasheet, Confidential - Programming Program Execution and Debugging
It uses the command delivered by the sequencers, executes them, converts the data from linear to logarithmic repre-
sentation add color correction and a master value. This signal is then feed into the actual PWM generator which con-
trols the LED current source.
Program Execution and Debugging
Following steps are required for the setup of the AS3665 and execution of a program
1. The AS3665 operating mode should be standby or active - see Device Operating Mode on page 12
2. Set the LED currents - see Current Sources on page 15
3. The charge pump usually can be left at their default setting - see CP setting Application Hint on page 31
4. Download of program: see Program Downloading on page 43.
5. Write the program start addresses to registers start_addr1, start_addr2 and start_addr316
6. Initialize the program counters PC1...PC3 by setting p1_en=01, p2_en=01 and p3_en=01. The prograex
cution is automatically enabled (p1_en...p3_en is set to 10 by the AS3665).
7. Set AS3665 operating mode to active by setting chip_en=1 - see Device Operating Mode on page 12
8. Execute the program by setting p1_mode=10, p2_mode=10 and p3_mode=10
Sequencers can be stopped by setting p1_mode...p3_moe=00 (hold). Single step uggng is achieved by
setting p1_mode...p3_mode=01.17 The program countecan be ontroller either by direcwriting to registers
PC1...PC3 or reset with p1_en...p3_en as shown above
9. Use AS3665 standby mode (set chip_en=0) to stop l programs and disabe all current sources
Table 56. Exec_Enable Register
Addr: 00h
Bit Name
ExecablRegister
Description
Bit
Default ccess
xecution enable for sequencer 1
Sequencer 1 is disabled1
00
Reload program counter and enable:
set PC1 to start_addr1, initialize sequencer 1 internal
loop counters then set p1_en=10 (run)
p1_en
1:0
00b
R/W
Execute sequencer commands as defined by
10
p1_mode
11
don’t use
Execution enable for sequencer 2
Sequencer 2 is disabled1
00
Reload program counter and enable:
01 set PC2 to start_addr2, initialize sequencer 2 internal
loop counters then set p2_en=10 (run)
p2_n
3:2
00b
R/W
Execute sequencer commands as defined by
10
p2_mode
11
don’t use
16.Assuming all three sequencers are actually used for the program.
17.The demoboard software simplifies the debugging using a graphical user interface.
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Datasheet, Confidential - Programming Program Execution and Debugging
Table 56. Exec_Enable Register (Continued) (Continued)
Addr: 00h
Bit Name
Exec_Enable Register
Bit
Default Access
Description
Execution enable for sequencer 3
Sequencer 3 is disabled1
00
Reload program counter and enable:
01 set PC3 to start_addr3, initialize sequencer 3 internal
loop counters then set p3_en=10 (run)
p3_en
5:4
00b
R/W
Execute sequencer commands as defined by
10
p3_mode
11
don’t use
1. If all sequencers are switched off (p1_en=00, p2_en=00 and p3_en=00), LED1_on...LED9_on control the oper-
ation of the LEDs - see Current Sources on page 15
The Exec_Mode register defines the sequencer executing mode (e.g. single step or run):
Table 57. Exec_Mode Register
Addr: 01h
Bit Name
xec_Mode Registe
escription
Bit
Default Access
Execution moe for equencer 1 if p1_en=10
Hold - nish current instruction and stop.
00
01
10
11
Step - cute one instruction at PC1 and increment
PC1 then reset p1_mode (hold)
p1_mode
p2_mode
p3_mode
1:0
00b
00b
00b
R/W
R/W
R/W
Run - start execution from PC1
Step in place - execute one instruction at PC1 but
don’t increment PC1 then reset p1_mode (hold)
Execution mode for sequencer 2 if p2_en=10
Hold - finish current instruction and stop.
00
01
10
11
Step - execute one instruction at PC2 and increment
PC2 then reset p2_mode (hold)
3:2
Run - start execution from PC2
Step in place - execute one instruction at PC2 but
don’t increment PC2 then reset p2_mode (hold)
Execution mode for sequencer 3 if p3_en=10
Hold - finish current instruction and stop.
00
01
10
11
Step - execute one instruction at PC3 and increment
PC3 then reset p3_mode (hold)
5:4
Run - start execution from PC3
Step in place - execute one instruction at PC3 but
don’t increment PC3 then reset p3_mode (hold)
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AS3665
Datasheet, Confidential - Programming Sequencers
The program memory areas are setup using start_addr1...start_addr3:
Table 58. Start_Addr1 Register
Addr: B0h
Bit Name
start_addr1
Start_Addr1 Register
Bit
Default Access
00h R/W
Description
7:0
Sequencer 1 start of program
Table 59. Start_Addr2 Register
Addr: B1h
Start_Addr2 Register
Bit
Bit Name
Default Access
00h R/W
Description
start_addr2
7:0
Sequencer 2 start of program
Table 60. Start_Addr3 Register
Addr: B2h
Start_Addr3 Register
Bit
Bit Name
Default Access
00h R/W
Description
start_addr3
7:0
Sequencer 3 start orogrm
The actual program execution of the sequencers is defined by the progam counters PC.PC3:
Table 61. Seq1_PC Register
Addr: B4h
Bit Name
PC1
Seq1_PC egisr
Description
Bit
Default Access
00h R/W
7:0
equencer 1 program counter
Table 62. Seq2_PC Register
Addr: B5h
Seq2_PC Register
Description
Bit
Bit Name
efault Access
00h R/W
PC2
7:0
Sequencer 2 program counter
Table 63. Seq3_PC Register
Addr: B6h
Seq3_PC Register
Description
Bit
Bit Name
Det Access
00h R/W
PC3
7:0
Sequencer 3 program counter
Sequencers
All three sequences are atonomous program execution unit executing the commands described in Sequencer Com-
mands Table (see pag66). Programs are downloaded, started and stopped as described in Program Downloading
(see page 43). The outpuof these sequencers is used for the PWM generator defined by so called MUX tables:
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AS3665
Datasheet, Confidential - Programming Sequencers
MUX tables - assignments of sequencers to channels
The MUX tables are setup during a program execution dynamically with the following sequencer commands:
- MUX set start address (see page 55) and MUX set end address (see page 56) define a memory region where the
MUX tables is operating (MUX next address or MUX previous address). MUX set start address automatically
loads the MUX for this sequencer with the content of the memory of ‘start address’.
- MUX next address (see page 56) and MUX previous address (see page 57) increase (or decrease) the MUX
pointer by one and load the MUX of this sequencer with the memory content the pointer is addressing. The MUX
pointer is kept within range defined by MUX set start address and MUX set end address.
- MUX set ptr (see page 58) sets the MUX pointer to a address defined by a displacement and MUX set start
address
- MUX select LED (see page 56) selects a single PWM output (single LED) where this sequencer is connected to.
This is useful for simple sequencer - PWM connections without requiring to setup a dedicated MUX table.
- MUX clear (see page 56) clears the MUX of this sequencer (no PWM channels are selected anymore).
The sequencer can operate in two operating modes:
1. PWM mode - this is the standard operating mode; the sequencer directly controls any of thPWM generators.
This is the default operating mode.
2. Ratiometric mode - the sequencer controls one or more of the faders (fader1 (see pge 23, fader2 and/or
fader3). The fader can control general LED brightness (cnfiguble to control any numer of LEDs) - see Cur-
rent Sources (see page 15).18
The ratiometric mode is entered with the command MUX RM (see page 66) or MUX fade (see page 66). The
AS3665 returns to PWM mode with the command MUX resRM.9
The sequencer are connected to the PWM generators and faers according to Fiure 28 (the 16 bits are the content of
the memory register, the MUX pointer is pointing to. A ‘1’ connects the sequecer to this output, a ‘0’ disconnects this
output):
Figure 28. MUX table connections
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Variables
The AS3665 includes fovariables ra, rb, rc and rd. These variables can read and written by the I2C interface and in
parallel read and wrtteby the sequencers20. Using the variables, programs can be controlled by a single I2C com-
mands. Sequencercan use these variables for internal calculations, for communication between the sequencers and
to communicae to the I2C controller.
18.The MUX tables share the same start address set by MUX set start address but have separate current
addresses and end addresses set by MUX set end address
19.Use only the highest (in order 1,2,3) sequencers for ratiometric mode (e.g. SEQ1 PWM, SEQ2 ratiometric
but not SEQ3 for PWM mode at the same time)
20.Variable rd is read/writable by I2C but only readable by the sequencers.
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AS3665
Datasheet, Confidential - Programming Sequencers
There are two local variables (local to each sequencer): ra and rb - each sequencer sees its own variable:
Table 64. Variable_A1 Register
Addr: B8h
Bit Name
var_a1
Variable_A1 Register
Description
Sequencer 1 local variable ra
Bit
Default Access
00h R/W
7:0
Table 65. Variable_A2 Register
Addr: B9h
Variable_A2 Register
Bit
Bit Name
Default Access
00h R/W
Description
var_a2
7:0
Sequencer 2 local variable ra
Table 66. Variable_A3 Register
Addr: BAh
Variable_A3 Register
Bit
Bit Name
Default Access
00h R/W
Description
var_a3
7:0
Sequencer 3 local iable ra
Table 67. Variable_B1 Register
Addr: BCh
Variable_B1 egister
Bit
Bit Name
Default Access
00h R/W
Decription
var_b1
7:0
Seencer 1 local variable rb
Table 68. Variable_B2 Register
Addr: BDh
Vaiable_B2 Register
Bit
Bit Name
Defalt Access
00h R/W
Description
var_b2
7:0
Sequencer 2 local variable rb
Table 69. Variable_B3 Register
Addr: BEh
Variable_B3 Register
Bit
Bit Name
Defaut Access
0R/W
Description
var_b3
7:0
Sequencer 3 local variable rb
There are two global variables: rc and r- these are shared between all sequencers:
Table 70. Variable_C Register
Addr: BBh
Bit ame
Variable_C Register
Description
Bit
Default Access
00h R/W
global variable rc -
variable available for all sequencers
ar_c
7:0
Table 7ariable_D Register
Addr: 0Fh
Variable_D Register
Description
Bit
Bit Name
Default Access
00h R/W
global variable rd -
variable available for all sequencers
var_d
7:0
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AS3665
Datasheet, Confidential - Programming Audio Processing
Audio Processing
Use austriamicrosystems sample codes for audio processing.
Sequencer Commands
Ramping of PWM(s) is achieved by the Ramp/Wait command shown in Table 72. The selected channels are chosen
by MUX tables - assignments of sequencers to channels on page 49. This command also can be used to wait for a
defined time in the program execution (if number of increments = 0).
Table 72. Ramp/Wait Command
Ramp/Wait Command
Ramps the PWM of the selected PWM generator up or down;
if the number of increments is zero, it simply waits
Name
Bits
D15
D14
Bitname
Parameter Description
Compiler syntax: RMP, prescale, step time, sign, number of increments;
0
0
1
each step has 16 clock cycles (typ. 0.49ms 32768Hz)
each stehas 512 clock cycles (typ. 5.6mat 32768Hz)
prescale
the clock generation s descbed in section Clock Generation on page 14
duration between single increments/decrements
Ramp/Wait
D13:D9
D8
step time
sign
1-31
e.g. ime=8, presca0, sign=0, the duration between
very increment is typcally 0.49ms*8 = 3.92ms
0
1
0
ramp up, always incemnt by 1; 255 is maximum value
ramp down, alws derement by 1; 0 is minimum value
Wait foduron defined by prescale and step time
number of
increments
D7:D0
number of ctual cycles in a single ramp command
(e.g. 255 defines a full scale ramp)
1-255
With the Set PWM command PWM(s) WM channels nected to a sequencer as shown in section MUX tables
- assignments of sequencers to channels on page 49) caimmediately forced to a value:
Table 73. Set PWM Command
Set PWM Command
Force PWM
Name
Bits
Bitname
Parameter Description
Compiler syntax: SPW, pwm value;
0100000b
(40h)
D15:D8
D7:0
Set PWM
actual PWM value used:
0...off
pwm value
0-255
255...full scale
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Ramping of PWM(s) dependent on variables is achieved by the Ramp with variable command shown in Table 74. This
command also can be used to wait for a defined time in the program execution (if number of increments = 0).
Table 74. Ramp with variable Command
Ramp with variable Command
Ramps the PWM of the selected PWM generator up or down;
if the number of increments is zero, it simply waits
Name
Bits
Bitname
Parameter Description
Compiler syntax: RWV, prescale, sign, variable for step, variable for number of increments;
10000100_
D15:D6
00b
0
1
each step has 16 clock cycles (typ. 0.49ms at 32768Hz)
each step has 512 clock cycles (typ. 15.6ms at 32768H)
D5
D4
prescale
the clock generation is described in section Clock Genetion on page 14
0
1
ramp up, always increment by 1; 255 is mximum value
ramp down, always decrement by 1; 0 is minimum value
The content of he varble defines the duratiobetween single
sign
increments/decreents; eg. if variable rx=8, prescale=0, sign=0, the
duration between verincrement is typclly .49ms*8 = 3.92ms
Ramp with
variable
0
1
2
3
vrable ra
variarb
variable rc
variable rd
variable for
step
D3:D2
If e content of the variable rx is
0 then wait for drtion defined by prescale and D3:D2
1-255 then it defins the number of actual cycles in a single ramp
comand (e.g. 255 defines a full scale ramp)
variable
number of
increments
0
1
2
3
variable ra
variable rb
variable rc
variable rd
D1:D0
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With the Set PWM to variable command PWM(s) (PWM channels are connected to a sequencer as shown in section
MUX tables - assignments of sequencers to channels on page 49) can be immediately forced to a value of a variable:
Table 75. Set PWM to variable Command
Set PWM to variable Command
Force PWM
Name
Bits
Bitname
Parameter Description
Compiler syntax: SPV, variable;
10000100_
011000b
D15:D2
The content of the variable is used to set the PWM value:
0...off
255...full scale
Set PWM to
variable
0
1
2
3
variable ra
variable rb
variable rc
variable rd
D1:D0
variable
With the GoTo Start command the program counter of the quencer is reset to its start value:
Table 76. GoTo Start Command
GoTo Start Command
Name
Bits
Bitname
PaeteDescription
Compiler ntaGS;
Set sequencprogram counter to start address
iseqencer 1 then PC1 = start_addr1
if equencer 2 then PC2 = start_addr2
if sequencer 3 then PC3 = start_addr3
00000000_
0000000
(0000h
GoTo Start
D15:D0
With the Branch command loops can be implemeed. Loops can be nested without limits:
Table 77. Branch Command
Branch Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: BRN, loop count, step number;
D15:D13
D12:D7
010b
0
infinite loops
1 to 63 loops
loop count
Branch
1-63
jump to ‘step number’ for ‘loop count’ times;
sets the PC of this sequencer = ‘step number’; in the compiler
‘step number’ can be defined by a label
D6:D0
step number 0-127
Wh the ranch with variable command loops can be implemented. The number of loops are defined by a variable.
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Loops can be nested without limits:
Table 78. Branch with variable Command
Branch with variable Command
Parameter Description
Compiler syntax: BRV, step number, variable;
Name
Bits
Bitname
D15:D9
D8:D2
1000011b
jump to ‘step number’ for ‘variable’ times;
sets the PC of this sequencer = ‘step number’; in the compiler
‘step number’ can be defined by a label
step number 0-127
Branch with
variable
The content of the variable defines the number of loops performed
(0=infinite)
0
variable ra
variable rb
variable rc
variable rd
D1:D0
variable
1
2
3
With the End/Interrupt command command program execution is toppd and optionally ainerrupt is sent:
Table 79. End/Interrupt command Command
End/Interrupt comand Command
Name
Bits
D15:D13
D12
Bitname
101b
int
Paramer Description
Compiler syntax: Eint, reset;
0
1
no interrupt is sent
send an nterrupt (see Interrupt Generator on page 36) and
disable this sequencer
r sequencer 1, int3=1 and p1_en (see page 46) = 00
End/Interrupt
command
0
1
program counter is incremented by 1
D11
reset
program counter is reset to start address
e.g. for sequencer 1, PC1 = start_addr1
000_
00000000b
stop program execution by resetting px_mode
e.g. for sequencer 1, p1_mode (see page 47) = 00
D10:D0
With the Trigger command intenal between sequencers) and external (between several AS3665) synchronization is
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possible (see Trigger pin TRIG on page 39):
Table 80. Trigger Command
Trigger Command
Parameter Description
Name
Bits
Bitname
Compiler syntax: TRG, wait trigger channels, send trigger channels;
D15:D13
111b
Wait for trigger from...
0
1
no trigger
D12
Ext Trig
wait for external trigger from pin TRIG1
D11:D10
D9
XXb
CH3
0
1
0
1
0
1
no trigger
wait for trigger from sequence3
no trigger
D8
D7
CH2
CH1
wfor trigger from sequecer 2
no triggr
Trigger
wait for trigger from sequencer 1
nd trigger to...
0
1
no trigger
D6
D5:D4
D3
Ext Trig
XXb
nd trigger to pin TRIG
0
1
0
1
0
1
no trigger
send trigger to sequencer 3
no trigger
CH3
D2
CH2
send trigger to sequencer 2
no trigger
D1
D0
CH1
Xb
send trigger to sequencer 1
1. Set trig_input_on (see page 39=1 to enable the input.
With the MUX set start addres and MUX set end address commands the memory area for the multiplexer between
the sequencers and the otput PWM generators are initialized. (see MUX tables - assignments of sequencers to chan-
nels on page 49)
Table 81. MUX set sart address Command
MUX set start address Command
Na
Bits
Bitname
Parameter Description
Compiler syntax: MSS, RAM address;
10011100
0b
D15:D7
MUX set start
address
Sets the multiplexer start address to ‘RAM address’. After the
D6:D0 RAM address 0-127 next command is executed the multiplexer for this sequencer is
initialized by the content of this ‘RAM address’.
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A similar command is used to set the multiplexer memory area end address:
Table 82. MUX set end address Command
MUX set end address Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: MSE, RAM address;
MUX set end
address
10011100
1b
D15:D7
D6:D0 RAM address 0-127
Sets the multiplexer end address to ‘RAM address’.
With the MUX select LED command the sequencer can be simply connected to a single output (if more than one ou
put should be controlled by one sequencer see MUX tables - assignments of sequencers to channels (see pag49)):
Table 83. MUX select LED Command
MUX select LED Command
Name
Bits
Bitname
Parameter Description
Compiler syntx: MS, LED select;
10011101
0b
D15:D7
D6:D0
MUX select
LED
Connes sequencer to a gle output defined by ‘LED select’;
e.g. 3 selectoutput LED3
LED select
1-9
With the MUX clear command the multiplexer tabs arinitialized (see ge 4):
Table 84. MUX clear Command
MUX clear Comand
Name
Bits
Bitnm
Parameter Description
iler syntax: MCL;
10011101
00000000b
(9D00h)
MUX clear
Clear the MUX table
(this sequencer is not connected to any output)
D15:D0
With the MUX next address command the UX pointer can be moved down in the MUX table (see page 49):
Table 85. MUX next address Command
MUX next address Command
Name
Bits
Bitame
Parameter Description
Compiler syntax: MNA;
increase the MUX pointer by one; if the address would be above the
address defined by MUX set end address, reset the MUX pointer to the
address defined by MUX set start address; load the MUX with the content
of this memory address
MUX next
address
10011101
10000000b
(9D80h)
D1:D0
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With the MUX previous address command the MUX pointer can be moved up in the MUX table (see page 49):
Table 86. MUX previous address Command
MUX previous address Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: MPA;
decrease the MUX pointer by one; if the address would be below the
address defined by MUX set start address, reset the MUX pointer to the
address defined by MUX set end address; load the MUX with the conten
of this memory address
MUX previous
address
10011101
11000000b
(9D8Ch)
D15:D0
With the MUX set RM and MUX reset RM command the sequencer can be configured for ratiometric mode or PWM
mode:
Table 87. MUX set RM Command
MUX set RM Command
Name
Bits
Bitname
Parameter Description
Compilesynt: SRM;
10011101
00100000b
(9D20h)
MUX set RM
Set Sequencer ratioetric mode - see MUX tales - assignments of
sequencers to channels on page 49
D15:D0
Table 88. MUX reset RM Command
MUrst RM Command
Pamter Description
Compiler synax: RRM;
Name
Bits
Bitname
1001110
0100000
(9D40
MUX reset RM
Reset Sequenceratiometric mode (= PWM mode) - see MUX tables -
aments of sequencers to channels on page 49
D15:D0
MUX fade is used to set the sequencer in ratiomeic mde and configure the faders which are connected to this
sequencer with one single command - no dditional MUX tables are required:
Table 89. MUX fade Command
MUX fade Command
Name
Bits
Bitame
Parameter Description
Compiler syntax: MXF,<faders>;
Set Sequencer ratiometric mode - see MUX tables - assignments of
sequencers to channels on page 49 and configure the faders, which are
connected to this sequencer.
10011101
00100b
D15:D3
D2
1
0
1
0
1
0
sequencer controls fader 3
sequencer does not control fader 3
sequencer controls fader 2
fader3
fader2
fader1
MUX fade
D1
sequencer does not control fader 2
sequencer controls fader 1
D0
sequencer does not control fader 1
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MUX set ptr set the MUX pointer to an address <vector number>+MUX set start address:
Table 90. MUX set ptr Command
MUX set ptr Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: MXP,<vector number>;
10011101
011b
D15:D5
MUX set ptr
The MUX pointer is set to <vector number> + address defined by MUX set
start address
D4:D0 vector number
With the je (jump ==), jge (jump >=), jl (jump <) and jne (jump <>) commands the program flow21 can be controed
depending on values in variables:
Table 91. je (jump ==) Command
je (jump ==) Command
Name
Bits
Bitname
Compiler syntax: JE, instrucons skiped, variable 1, variable 2;
1000100b
Parameter Description
D15:D9
D8:D4
defines the number f instructions skipped, if
variable1 variable2
instructions
skipped
0-31
PC = PC + ‘istructions skipped’
0
1
3
0
1
2
3
vriable1 = ra
variable1 = rb
variable1 = rc
variable1 = rd
variable2 = ra
variable2 = rb
variable2 = rc
variable2 = rd
je (jump ==)
D3:D2
D1:D0
variable 1
variable 2
21.Only positive jumps (jump down) can be implemented. If jumps in both directions are required, use these
commands in combination with Branch (see page 53)
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Table 92. jge (jump >=) Command
jge (jump >=) Command
Parameter Description
Compiler syntax: JGE, instructions skipped, variable 1, variable 2;
1000101b
Name
Bits
Bitname
D15:D9
D8:D4
defines the number of instructions skipped, if
variable1 >= variable2
instructions
skipped
0-31
PC = PC + ‘instructions skipped’
0
1
2
3
0
1
2
3
variable1 = ra
variable1 = rb
variable1 = rc
variable1 = rd
variable2 = ra
variable2 = rb
variable2 = rc
variable2 = rd
jge (jump >=)
D3:D2
D1:D0
variable 1
variable 2
Table 93. jl (jump <) Command
jl (jump <) ommand
Parameer Description
Compiler syntax: JL, instructions sed, variable 1, variable 2
1000110b
Name
Bits
Bitname
D15:D9
D8:D4
defies the number of instructions skipped, if
variable1 < variable2
instructios
skiped
0-31
PC = PC + ‘instructions skipped’
0
1
2
0
1
2
3
variable1 = ra
variable1 = rb
variable1 = rc
variable1 = rd
variable2 = ra
variable2 = rb
variable2 = rc
variable2 = rd
jl (jump <)
D3:D2
D1:D0
variable 1
varible
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Table 94. jne (jump <>) Command
jne (jump <>) Command
Parameter Description
Compiler syntax: JNE, instructions skipped, variable 1, variable 2
1000111b
Name
Bits
Bitname
D15:D9
D8:D4
defines the number of instructions skipped, if
variable1 <> variable2 (not equal)
PC = PC + ‘instructions skipped’
instructions
skipped
0-31
0
1
2
3
0
1
2
3
variable1 = ra
variable1 = rb
variable1 = rc
variable1 = rd
variable2 = ra
variable2 = rb
variable2 = rc
variable2 = rd
jne (jump <>)
D3:D2
D1:D0
variable 1
variable 2
Variable can be initialized to a constant value by the commd load):
Table 95. ld (load) Command
l(load) Command
Name
Bits
Bitname
Pmeter Description
Compiler syntax: LD trget variable, value;
1001b
(9)
D15:D12
0
1
2
3
set ra = value
set rb = value
set rc = value
don’t use
ld (load)
D11:D10 target variable
D9:D8
D7:D0
00b
value
0-255
value
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A constant value can be added to a variable with the command add number:
Table 96. add number Command
add number Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: ADN, target variable, value;
1001b
(9h)
D15:D12
0
1
2
3
set ra = ra + value
set rb = rb + value
set rc = rc + value
don’t use
add number
D11:D10 target variable
D9:D8
D7:D0
01b
value
0-255
value
Variable are added together with the command add variable:
Table 97. add variable Command
add variabmand
ParameteDesption
Compiler syntax: ADV, target variable, ariable 1, variable 2;
1001b
Name
Bits
Bitname
D15:D12
(9h)
1
2
3
et ra = variable1 + variable2
set rb = variable1 + variable2
set rc = variable1 + variable2
don’t use
D11:D10 target vari
D9:D4
D3:D2
110000b
add variable
0
1
2
3
0
1
2
3
variable1 = ra
variable1 = rb
variable1 = rc
variable1 = rd
variable2 = ra
variable2 = rb
variable2 = rc
variable2 = rd
variable 1
D1:D0
variable 2
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A constant value can be subtracted from a variable with the command sub number:
Table 98. sub number Command
sub number Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: SBN, target variable, value;
1001b
(9h)
D15:D12
0
1
2
3
set ra = ra - value
set rb = rb - value
set rc = rc - value
don’t use
sub number
D11:D10 target variable
D9:D8
D7:D0
10b
value
0-255
value
Variable are subtracted with the command sub variable:
Table 99. sub variable Command
sub variabmand
ParameteDesption
Compiler syntax: SBV, target variable, ariable 1, variable 2;
1001b
Name
Bits
Bitname
D15:D12
(9h)
1
2
3
set ra = variable1 - variable2
set rb = variable1 - variable2
set rc = variable1 - variable2
don’t use
D11:D10 target vari
D9:D4
D3:D2
110001b
sub variable
0
1
2
3
0
1
2
3
variable1 = ra
variable1 = rb
variable1 = rc
variable1 = rd
variable2 = ra
variable2 = rb
variable2 = rc
variable2 = rd
variable 1
D1:D0
variable 2
Audio Cmmands
austriamosstems provides audio programs to control light depending on an audio input as a starting point for an
actal implementation. Due to the complexity of these programs it is recommend to use the demos and modify the
demo odes accordingly.
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With the command Get ADC, data can be fetched from the audio filter (See Audio Input on page 34):
Table 100. Get ADC Command
Get ADC Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: GET, target variable;
10001010_
0010b
(8A2h)
D15:D4
0h
5h
Ah
Fh
set ra = value from ADC or filter
set rb = value from ADC or filter
set rc = value from ADC or filter
set rd = value from ADC or filte
Get ADC
D3:D0 target variable
other
values
don’t use
Memory Operation Command - load/store SRAM
Table 101. Load SRAM Command
Load SRAmmand
Name
Bits
D15:D9
D8
Bitname
Parameter Description
Compiler syntax: LDS, R/W, sourcetarget variable;
1000_111b
(87h)
oad from or storto SAM (Register SRAM0, SRAM1...SRAM15)
R/W
0
1
Read from SRAM: SRAM -> target variable
Write to SRAM: source variable -> SRAM
Define SRAM address register to load from or store to
sram_0
0
1
SRAM
Address
sram_1
D7:D4
Load SRAM
...
F
...
sram_15
Set source variable for read or target variable for write
0h
5h
Ah
Fh
ra
rb
rc
rd
source/target
variable
D3:0
other
values
don’t use
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Logical Operation Commands
or command provides a binary or between variables:
Table 102. or Command
or Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: OR, input variable, output variable;
D15:D9
1000101b
0
1
2
3
ra
rb
rc
rd
D8:D7 input variable
or
D6:D4
D3:D0
001b
0h
5h
Ah
Fh
set ra = ra or <input variable>
set rb = rb or <input vable>
serc = rc or <input variable>
set rd = rd or <input variable>
output
variable
other
values
donuse
and command provides a binary and between variables
Table 103. and Command
and Comman
Name
Bits
Bitnm
Parameter Description
Compiler syntaD, input variable, output variable;
D15:D9
1000110b
0
1
2
3
ra
rb
rc
rd
D8:D7 input variable
and
D6:D4
3:D0
00b
0h
5h
Ah
Fh
set ra = ra and <input variable>
set rb = rb and <input variable>
set rc = rc and <input variable>
set rd = rd and <input variable>
output
variable
other
values
don’t use
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Shift Commands
shift left Variable shift a variable left by 1 (multiply by 2) - if the result exceeds 255, 255 is used as result:
Table 104. shift left Command
shift left Command
Name
Bits
Bitname
Parameter Description
Compiler syntax: SL, input variable, output variable;
D15:D9
1000101b
0
1
2
3
ra
rb
rc
rd
D8:D7 input variable
shift left
D6:D4
D3:D0
000b
0h
5h
Ah
Fh
set ra = <input variable> * 2
set rb = <input variab> * 2
src = <input variable> * 2
set rd = <input variable> * 2
output
variable
other
values
donuse
shift right Variable shifts a variable right by 1 (divide by , rounded to 0)
Table 105. shift right Command
shift right Comand
Name
Bits
Bitnm
Parameter Description
Compiler synt, input variable, output variable;
D15:D9
1000110b
0
1
2
3
ra
rb
rc
rd
D8:D7 input variable
shift right
D6:D4
3:D0
00b
0h
5h
Ah
Fh
set ra = <input variable> / 2
set rb = <input variable> / 2
set rc = <input variable> / 2
set rd = <input variable> / 2
output
variable
other
values
don’t use
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10 Sequencer Commands Table
Table 106. Sequencer Commands Table
Command
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
pres
cale
Ramp/Wait
Set PWM
0
0
1
step time
sign
0
number of increments
pwm value
51
51
52
1
0
0
0
0
0
0
0
0
1
0
0
Ramp with
variable
pres
cale
variable
for step increment
variable
0
0
0
sign
Set PWM to
variable
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
variable
53
GoTo Start
Branch
0
1
0
0
0
1
0
0
53
53
loop count
step number
step number
Branch with
variable
1
1
0
1
0
0
0
0
1
0
1
0
vaiable
54
54
End/Interrupt
command
rese
t
int
0
0
0
0
0
0
0
0
0
Wait for trigger from...
Send Trgger o...
Trigger
1
1
1
X
55
Ext
Ext
X
1
1
X
1
1
CH3 CH1
X
X
CH3 CH2 CH1
Trig
Trig
MUX set start
address
1
1
0
0
0
0
1
1
0
0
0
0
0
1
RAM address
RAM address
LED select
55
56
MUX set end
address
MUX select
LED
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
0
1
56
56
56
MUX clear
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MUX next
address
MUX previous
address
1
0
0
1
1
1
1
1
0
0
0
0
0
0
57
MUX set RM
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
57
57
MUX reset RM
fade fade fade
r3 r2 r1
MUX fade
1
0
0
1
1
1
0
1
1
0
0
0
1
1
1
0
0
57
58
MUX set ptr
je (jump ==)
jge (jump >=)
jl (jump <)
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
vector number
instructions skipped
instructions skipped
instructions skipped
instructions skipped
variable 1 variable 2 58
variable 1 variable 2 59
variable 1 variable 2 59
variable 1 variable 2 60
jne (jump <>)
target
ld (load)
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
1
0
value
value
60
61
variable
target
variable
add number
add variable
sub number
target
variable
0
0
0
0
variable 1 variable 2 61
target
variable
value
62
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AS3665
Datasheet, Confidential - Sequencer Commands Table Sequencer Commands
Table 106. Sequencer Commands Table
Command
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
target
sub variable
1
0
0
1
1
1
0
0
0
0
0
1
1
0
variable 1 variable 2 62
variable
Get ADC
1
1
0
0
0
0
0
0
1
1
0
1
1
1
0
target variable
63
Load SRAM
R/W
SRAM Address
source/target variable 63
input
or
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
target variable
target variable
target variable
target vriable
64
64
65
65
variable
input
variable
and
input
variable
shift left
shift right
input
variable
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Revision 1.0.2
67 - 77
AS3665
Datasheet, Confidential - Registermap Sequencer Commands
11 Registermap
Table 107. Register Map
Register
Definition
Content
Name
b7
b6
b5
b4
b3
b2
b1
b0
Exec_Enable
00h 00h ram_init chip_en
trig_input
p3_en
p3_mode
p2_en
p2_mode
p1_en
p1_mode
Exec_Mode
01h 00h
0
_on
LED_Control1
02h 00h LED8_on LED7_on LED6_on LED5_on LED4_on LED3_on LED2_on LED1_
temp_co
mp_mod
e
fader_log fader_log fader_log
LED_Control2
03h 00h GPO_on
LED9_on
lin3
lin2
lin1
int_on_tri sel_ext_ int_signa
gpo_sign
al
GPO_Control
CP_Control
04h 00h
05h 10h
06h 37h
08h 81h
int_mode
gpo_mode
cp_mode
g
clock
l
cp_a_
on
cp_down_hyst
cp_on
cp_mode_switching
cp_to_ cp_skip_ cp_max_ LED9_on LED8_on LED7_on
re
CP_Mode_Switch
Supervision
on
5V4
_cp
_cp
_cp
auto_shu
tdown
osc_awa
ys_on
ov_temp ov_temp
_status _on
adc_sing
09h 00h le_conve adc_slow
rsion
adc_cont
inuous
ADC_Control
adc_select
result_n
0Ah 00h
ADC_MSB_Result
ADC_LSB_Result
adc<9:3>
t_ready
0Bh 00h
adc<2:0>
int2
no_extcl
ock_dete
cted
init_read
y_int
Interrupt_Status
Interrupt_Mask
0Ch 40h
ov_temp adc_eoc
int3
int1
no_extcl
init_read
y_int_ma
sked
o_temp adc_eoc
_msked _masked
ock_dete int3_mas int2_mas int1_mas
0Dh FFh
0Eh 00h
cted_ma
sked
ked
ked
ked
Temp_Sense_
Control
temp_me temp_se temp_int
as_busy ns_on _ext
Variable_D
LED_Current1
LED_Current
LED_Current3
LED_Currnt4
LEDrrent5
LED_Current6
LE_Current7
LED_Current8
LED_Current9
LED_MaxCurr1
0Fh 00h
1000h
1h 00h
12h 00h
13h 00h
14h 00h
15h 00h
16h 00h
17h 00h
18h 00h
19h 00h
var_d
LED_current1
LED_current2
LED_current3
LED_current4
LED_current5
LED_current6
LED_current7
LED_current8
LED_current9
LED4_max
LED3_max
LED2_max
LED1_max
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Registermap Sequencer Commands
Table 107. Register Map (Continued)
Register
Definition
Content
Name
b7
b6
b5
b4
b3
b2
b1
LED5_max
LED9_max
b0
LED_MaxCurr2
LED_MaxCurr3
1Ah 00h
1Bh 00h
LED8_max
LED7_max
LED6_max
audio_bu audio_c
Audio_Control
1Ch 00h
0
0
audio_buf_gain
audio_on
f_on
mdset
Audio_AGC
LED_Temp
1Dh 00h
1Fh 00h
agc_time
led_temp
agc_ctrl
force_res
et
Reset_Control
3Ch 00h
Chip_ID1
3Dh C9h
3Eh 5xh
5Fh 00h
60h 00h
61h 00h
62h 00h
63h 00h
64h 00h
65h 00h
66h 00h
67h 00h
68h 00h
69h 00h
6Ah 00h
6Bh 00h
6Ch 00h
6Dh 00h
6Eh 00h
6Fh 00
0h 0h
71h 00h
72h 00h
73h 00h
74h 00h
75h 00h
76h 00h
77h 00h
78h 00h
1
0
1
1
0
0
0
1
1
0
0
1
Chip_ID2
visin
ge_select
Page_Select
Cmd_0_MSB
Cmd_0_LSB
Cmd_1_MSB
Cmd_1_LSB
Cmd_2_MSB
Cmd_2_LSB
Cmd_3_MSB
Cmd_3_LSB
Cmd_4_MSB
Cmd_4_LSB
Cmd_5_MSB
Cmd_5_LSB
Cmd_6_MSB
Cmd_6_LSB
Cmd_7_MSB
Cmd_7_LSB
Cmd_8_MSB
Cmd_8_LSB
Cmd_9_MSB
CmdLSB
Cmd_MSB
Cmd_A_LSB
Cmd_B_MSB
Cmd_B_LSB
Cmd_C_MSB
cmd_0_msb
cmd_0_lsb
cmd_1_ms
cmd_1_sb
c_2_msb
cmd_2_lsb
cmd_3_msb
cmd_3_lsb
cmd_4_msb
cmd_4_lsb
cmd_5_msb
cmd_5_lsb
cmd_6_msb
cmd_6_lsb
cmd_7_msb
cmd_7_lsb
cmd_8_msb
cmd_8_lsb
cmd_9_msb
cmd_9_lsb
cmd_A_msb
cmd_A_lsb
cmd_B_msb
cmd_B_lsb
cmd_C_msb
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Registermap Sequencer Commands
Table 107. Register Map (Continued)
Register
Definition
Content
Name
b7
b6
b5
b4
b3
b2
b1
b0
Cmd_C_LSB
Cmd_D_MSB
Cmd_D_LSB
Cmd_E_MSB
Cmd_E_LSB
Cmd_F_MSB
Cmd_F_LSB
PWM_LED1
PWM_LED2
PWM_LED3
PWM_LED4
PWM_LED5
PWM_LED6
PWM_LED7
PWM_LED8
PWM_LED9
PWM_GPO
Fader1
79h 00h
7Ah 00h
7Bh 00h
7Ch 00h
7Dh 00h
7Eh 00h
7Fh 00h
80h 00h
81h 00h
82h 00h
83h 00h
84h 00h
85h 00h
86h 00h
87h 00h
88h 00h
8Fh 00h
9Bh 00h
9Ch 00h
9Dh 00h
A0h 20h
A1h 20h
A2h 20h
A3h 20h
A4h 20h
A5h 20h
A6h 20h
A7h 20h
A8h 20h
B0h 00h
B1h 00h
B2h 00h
B4h 00h
B5h 00h
B6h 00h
B8h 00h
cmd_C_lsb
cmd_D_msb
cmd_D_lsb
cmd_E_msb
cmd_E_lsb
cmd_F_msb
cmd_F_lsb
pwm_LED1
pwm_LED2
pw_LED3
pwm_LED4
pwm_LED5
pwm_LED
pwm_LD7
p_LED8
pwm_LED9
pwm_GPO
fader1
Fader2
fader2
Fader3
fader3
Driver_Setup1
Driver_Setup2
Driver_Setup3
Driver_Setup4
Driver_Setup5
Driver_Setup6
Driver_Setup7
Driver_Setup8
Driver_Sep9
Start_Addr1
StarAdr2
tart_Addr3
Seq1_PC
fade_src1
loglin1
loglin2
loglin3
loglin4
loglin5
loglin6
loglin7
loglin8
loglin9
color_slope1
color_slope2
color_slope3
color_slope4
color_slope5
color_slope6
color_slope7
color_slope8
color_slope9
fader_sr2
fadec3
fader_src4
fader_src5
fader_src6
fader_src7
fader_src8
fader_src9
start_addr1
start_addr2
start_addr3
PC1
Seq2_PC
PC2
Seq3_PC
PC3
Variable_A1
var_a1
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AS3665
Datasheet, Confidential - Registermap Sequencer Commands
Table 107. Register Map (Continued)
Register
Definition
Content
Name
Variable_A2
Variable_A3
Variable_C
Variable_B1
Variable_B2
Variable_B3
SRAM0
b7
b6
b5
b4
b3
b2
b1
b0
B9h 00h
BAh 00h
BBh 00h
Bch 00h
Bdh 00h
BEh 00h
D0h 00h
D1h 00h
D2h 00h
D3h 00h
D4h 00h
D5h 00h
D6h 00h
D7h 00h
D8h 00h
D9h 00h
Dah 00h
Dbh 00h
Dch 00h
Ddh 00h
Deh 00h
Dfh 00h
var_a2
var_a3
var_c
var_b1
var_b2
var_b3
sram_0
SRAM1
sram_1
SRAM2
sram_2
SRAM3
am_3
SRAM4
sram_4
SRAM5
sram_5
SRAM6
sram_6
SRAM7
sram7
SRAM8
m_8
SRAM9
sram_9
SRAM10
SRAM11
SRAM12
SRAM13
SRAM14
SRAM15
sram_10
sram_11
sram_12
sram_13
sram_14
sram_15
96x16_bits_instruction_code
Program_Direct_A
ccess
FEh 00h
see Program Direct Access on page 43
Register is R/W
Register is read-only
Table 108. Inormation Registers (only for demoboard software)
Rster
Defiition
Content
Name
b7
b6
b5
b4
b3
b2
b1
b0
LED9_hi LED9_lo
CP_Mode_Switch
06h 00h
07h 00h
see Table 107 on page 68
gh_volt
w_volt
LED_Low_Voltage
_Status
LED8_lo LED7_lo LED6_lo LED5_lo LED4_lo LED3_lo LED2_lo LED1_lo
w_volt
w_volt
w_volt
w_volt
w_volt
w_volt
w_volt
w_volt
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Registermap Sequencer Commands
Table 108. Information Registers (only for demoboard software) (Continued)
Register
Definition
Content
Name
b7
b6
b5
b4
b3
b2
b1
b0
Temp_Sense_
Control
cp_skip_
status
0Eh 00h
1Dh 00h
1Eh 00h
audio_di audio_m
s_start an_start
Audio_AGC
LED_High_Voltage
_Status
LED8_lhi LED7_hi LED6_hi LED5_hi LED4_hi LED3_hi LED2_hi LED1_h
gh_volt gh_volt gh_volt gh_volt gh_volt gh_volt gh_volt gh_vol
Mux1_LSB
Mux2_LSB
Mux3_LSB
Mux1_MSB
Mux2_MSB
Mux3_MSB
20h 00h s1_led8 s1_led7 s1_led6 s1_led5 s1_led4 s1_led3 s1_led2 s1led1
21h 00h s2_led8 s2_led7 s2_led6 s2_led5 s2_led4 s2_led3 s2_led2 s2_led1
22h 00h s3_led8 s3_led7 s3_led6 s3_led5 s3_led4 s3_led3 3_le2 s3_led1
24h 00h s1_gpo
25h 00h s2_gpo
26h 00h s3_gpo
s1_led9
s2_led9
s3_led9
ext_rigg ch3_trigg ch2_trigg
eer er
Trigger_Wait1
Trigger_Wait2
28h 00h
29h 00h
ext_igg ch3_trigg
ch1_trigg
er
er
er
ext_trigg
er
ch2_trigg ch1_trigg
er er
Trigger_Wait3
Audio_Result
2Ah 00h
2Fh 00h
udio_result
loop_cou
nter_sele
ct
Page_Select
5Fh 00h
see Table 107 on page 68
Table1_StartAddr
Table2_StartAddr
Table3_StartAddr
Table1_EndAddr
Table2_EndAddr
Table3_EndAddr
Table1_Pointer
Table2_Pointer
Table3_Pointe
C4h 00h
C5h 00h
C6h 00h
C8h 00h
C9h 00h
Cah 00h
Cch 00h
Cd00h
Ch 00h
table_start1
table_start2
table_start3
table_end1
table_end2
table_end3
table_ptr1
table_ptr2
table_ptr3
Register is R/W
Register is read-only
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Revision 1.0.2
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AS3665
Datasheet, Confidential - Application Information External Components
12 Application Information
External Components
Low ESR input capacitors reduce input switching noise and reduce the peak current drawn from the battery. Low ESR
output capacitors should be used to minimize VOUT ripple.
Ceramic capacitors are required and should be located as close to the device as is practical. X5R dielectric material is
recommended due to their ability to maintain capacitance over wide voltage and temperature range.
Input, Output and C2V5 Capacitor
Table 109. Recommended Input, Output and C2V5 Capacitor
Rated
Name
Part Number
GRM188R60J105K
223824613663
C
TC Code
Size
0603
0603
Manufacturer
Voltage
Murata
wwwmurata.com
1.0µF +/-15%
1.0µF +/-10%
X5R
6V3
CBAT,
CVCPOUT,
C2V5
Phycmp
www.pycomp.com
X5R
10V
If a different input capacitor is chosen, ensure similar ESR value and at last 0.6µF capacitance t the maximum input
supply voltage. Larger capacitor values (C) for CBAT may be usewithot limitations.
Flying capacitors
Table 110. Recommended Input, Output and C2V5 Capacito
Rated
Name
Part Number
C
TC Code
X5R
Size
0402
0603
Manufacturer
ge
Murata
www.murata.com
GRM155R60J474K
C0603C474K4RAC
470F +/-15%
470nF +/-10%
6V3
CFLY1,
CFLY2
Kemet
www.kemet.com
7R
16V
If a different input capacitor is chosen, ensure similar ESlue and at least 0.3µF capacitance at the maximum out-
put voltage. Larger capacitor values (C) may be ued wthout limitations.
PCB Layout Guideline
The high speed operation requires proper yout for optimum performance. Route the power traces first and try to min-
imize the area and wire length of the two h frequency/high current loops:
1. CBAT to CFLY1 and/or CFL2
2. CFLY1 and/or CFLY2 to VCPOT
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AS3665
Datasheet, Confidential - Application Information LED Test
The ground plane of the system should be connected to the layout of the AS3665 only at a single point. This avoid
noise to travel from the internal switching node to the application - see Figure 29:
Figure 29. Layout recommendation
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LED Test
See LED Test on page 39.
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AS3665
Datasheet, Confidential - Package Drawings and Markings LED Test
13 Package Drawings and Markings
Figure 30. WL-CSP-25 (2.610x2.675mm) 0.5mm pitch Marking
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AS3665
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Figure 31. WL-CSP-25 (2.610x2.675mm) 0.5mm pitch Package Dimensions
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AS3665
Datasheet, Confidential - Ordering Information LED Test
14 Ordering Information
The devices are available as the standard products shown in Table 111.
Table 111. Ordering Information
Model
Description
Delivery Form
Package
WL-CSP-25
(2.610x2.675mm) 0.5mm
pitch
9 Channel Advanced Command Driven RGB/White
LED Driver
AS3665-ZWLT
Tape & Reel
Note: AS3665-ZWLT
AS3665-
Z
Temperature Range:
Z........... -30ºC - 85ºC
WL Package Type:
WL ....... Wafer Level Chip Scale Package WL-CSP-25 (2.610x2.675mm) 0.mm itch
Delivery Form:
T........... Tape & Reel (no dry pack required)
T
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AS3665
Datasheet, Confidential - Ordering Information LED Test
Copyrights
Copyright © 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans-
lated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding
the information set forth herein or regarding the freedom of the described devices from patent infringement. austria-
microsystems AG reserves the right to change specifications and prices at any time and without notice. Therefre,
prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current inrma-
tion. This product is intended for use in normal commercial applications. Applications requiring extened temperature
range, unusual environmental requirements, or high reliability applications, such as military, medicalife-upport or life-
sustaining equipment are specifically not recommended without additional processing by austriamicroystems AG for
each application. For shipments of less than 100 parts the manufacturing flow might show detionfrom the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems AG is belived o be correct and acuate. However,
austriamicrosystems AG shall not be liable to recipient or ird party for any damages, including but not limited to
personal injury, property damage, loss of profits, loss of useterruption of busineor indirect, special, incidental or
consequential damages, of any kind, in connection with or aring out of the furnihing, performance or use of the tech-
nical data herein. No obligation or liability to recipient or any third party shall rise or flow out of
austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters
austriamicrosstems AG
A-8141 SchlosPremstaetten, Austria
Te: +43 ) 336 500 0
Fa+43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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