AS3676 [AMSCO]
Flexible Lighting Management; 灵活的照明管理
| 型号： | AS3676 |
| 厂家： | 
AMS(艾迈斯) |
| 描述： | Flexible Lighting Management |
| 文件： | 总92页 (文件大小：4733K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
austriamicrosystems AG
is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
Datasheet
AS3676
Flexible Lighting Management (CP, DCDC, 13 Current Sinks,
ADC, LED Test, LDO, DLS and Ambient Light sensing)
1 General Description
The AS3676 is a highly-integrated CMOS Power and
Lighting Management Unit for mobile telephones, and
other 1-cell Li+ or 3-cell NiMH powered devices.
- Light Sensor input with internal hardware process-
ing to control backlight according to ambient light
using 3 groups - any current source can select one
of the groups or no light sensor control
The AS3676 incorporates one Step Up DC/DC Con-
verter for white backlight LEDs, one high-power Charge
Pump, one Analog-to-Digital Converter, 13 current sinks,
LED in-circuit function test, a two wire serial interface,
and control logic all onto a single device. It supports
ambient light sensor processing and a Dynamic Lumi-
nance Scaling (DLS) input. Output voltages and output
currents are fully programmable.
Internal PWM Generation
- 8 Bit resolution
- Autonomous Logarithmic up/down dimming
Led Pattern Generator
- Autonomous driving for Fun RGB LEDs
- Support indicator LEDs
10-bit Successive Approximation AC
The AS3676 is part of the austriamicrosystems AS3675,
AS3687/87XM and AS3689 lighting management unit
family. It is software compatible to AS3687/87XM and
AS3689 and pin and software compatible to AS3675.
27µs Conversion Time
- Seleable Inputs: VANA/GPGPIO1/DLS,
GPI2/LIGHT, all curent ources, VBAT, CPOUT,
DCDC_FB
- Internal Tempeasurement
- Light Sensor inpuwith Java support (JSR-256):
read ADproessed value
2 Key Features
High-Efficiency Step Up DC/DC Converter
Support for automatic LED testing (open and
shorLEDs can be identified)
- Up to 26V/50mA for White LEDs
- Programmable Output Voltage with Extenal Resis-
tors and Serial Interface
obe Timeout protection
- Up o 1600ms
- hree different timing modes
Two General Purpose Inputs/Output
- Over voltage Protection
High-Efficiency High-Power Charump
- GPIO1/DLS, GPIO2/LIGHT
- Digital Input, Digital Output using VANA/GPI sup-
ply and Tristate
- 1:1, 1:1.5, and 1:2 Mode
- Automatic Up Switching (can be disabled an1:2
mode can be blocked)
- Output Current up to 400mA/500mA plsed
- Efficiency up to 95%
- GPIOs Programmable Pull-Up/Down
Programmable LDO
- 1.8 to 3.35V, 150mA
- Programmable via Serial Interface
Standby LDO always on
- Very Low effective Resistance (2.5 . in 1:1.5)
- Only 4 External Capacitors Require
2 x 1µF Flying Capacitors, 2 x 2.2F Input/Output
Capacitors
- Supports LCD White Bckligt LEDs, or RGB
LEDs
- Regulated 2.5V max. output 10mA
- 3µA Quiescent Current
Audio can be used to drive RGB LED(s)
- Color and Brightness depends on audio amplitude
Wide Battery Supply Range: 3.0 to 5.5V
Two Wire Serial Interface Control
Over current and Thermal Protection
WL-CSP30 3x2.5mm, 0.5mm pitch Package
13 Current Snks
- All 13 current inks fully Programmable (8-bit)
from: 0.15mA to 38.5mA (up to 75.6mA for
CURR3...CRR33)
- Thurrent sinks are High Voltage capable
(CR, CURR2, CURR6)
Programmable Hardware Control (Strobe, and Pre-
ew or PWM)
- Selectively Enable/Disable Current Sinks
- Dynamic Luminance Scaling (DLS) support to
improve backlight operating time (can adjust any
current source)
3 Applications
Power- and lighting-management for mobile telephones
and other 1-cell Li+ or 3-cell NiMH powered devices.
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AS3676
Datasheet - Applications
Figure 1. AS3676 Block Diagram
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AS3676
Datasheet - Applications
Contents
1 General Description ............................................................................................................................1
2 Key Features .......................................................................................................................................1
3 Applications ........................................................................................................................................1
4 Pinout ...................................................................................................................................................4
4.1 Pin Definitions ..............................................................................................................................................5
5 Absolute Maximum Ratings ...............................................................................................................6
6 Electrical Characteristics ...................................................................................................................6
7 Typical Operating Characteristics ...................................................................................................
8 Detailed Description .......................................................................................................................
8.1 Analog LDO ................................................................................................................................................9
8.2 Step Up DC/DC Converter .......................................................................................................................11
8.3 Charge Pump .........................................................................................................................................16
8.4 Current Sinks .........................................................................................................................................25
8.5 General Purpose Input / Output ............................................................................................................56
8.6 LED Test ...............................................................................................................................................62
8.7 Analog-to-Digital Converter ..................................................................................................................64
8.8 Audio controlled LEDs .......................................................................................................................67
8.9 Power-On Reset ....................................................................................................................................74
8.10 Temperature Supervision ........................................................................................................................75
8.11 Serial Interface ....................................................................................................................................76
8.12 Operating Modes ..............................................................................................................................79
9 Register Map .................................................................................................................................81
10 External Components ...............................................................................................................85
11 Package Drawings and Markgs .........................................................................................86
11.1 Tape & Reel Information .........................................................................................................................87
12 Ordering Information ...................................................................................................................88
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AS3676
Datasheet - Pinout
4 Pinout
Table 1. Pin Description for AS3676
Pin
Number
Pin Name
Type
Description
A1
GPIO1/DLS
VANA/GPI
AIO
AIO
Digital Luminance Scaling PWM input and General Purpose Input Output 1
LDO Output/General Purpose Input
A2
Charge Pump flying capacitor; connect a ceramic capacitor of 500nF to this
pin.
A3
A4
A5
C2_N
C1_P
AIO
AIO
AO
Charge Pump flying capacitor; connect a ceramic capacitor of 500nF to thi
pin.
Output voltage of the Charge Pump; connect a ceramic capacitor of µF
(±20%).
CPOUT
A6
B1
B2
DATA
DIO
AIO
Serial interface data input/output.
Ambient Light Sensor input and General Purpose Inpt Ouput 2
Ground Pad for Charge Pump
GPIO2/LIGHT
VSS_CP
GND
Charge Pump flying caacitr; onnect a ceramic capaitor of 500nF to this
pin.
B3
B4
C1_N
C2_P
AIO
AIO
Charge Pump flycapacitor; connect a ceramic capacitor of 500nF to this
pin.
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
DCDC_GATE
CLK
AO
DI
DCDC gatdriver.
Clock input foserial interface.
CURR41
RGB3
AI
Anacurrent sink input
AI
Aalog current sink input
VSS
GND
S
Ground pad
VBAT
Supply pad. Connect to battery.
CURR30
DCDC_SNS
CURR43
RGB1
AI
Analrent sink input, intended for activity icon LED
Sense nput of shunt resistor for Step Up DC/DC Converter.
Analog current sink input
AI
AI
AI
Analog current sink input
CURR33
CURR31
CURR2
DCDC_FB
CURR42
RGB2
AI
Analog current sink input, intended for activity icon LED
Analog current sink input, intended for activity icon LED
Analog current sink input (intended for Keyboard backlight)
DCDC feedback. Connect to resistor string.
Analog current sink input
I
I_HV
AI
AI
AI
Analog current sink input
CURR32
CURR6
CURR1
AI
Analog current sink input, intended for activity icon LED
Analog current sink input (intended for Keyboard backlight)
Analog current sink input (intended for Keyboard backlight)
AI_HV
AI_HV
Output voltage of the Low-Power LDO; always connect a ceramic capacitor of
1µF (±20%) or 2.2µF (+100%/-50%).
E6
V2_5
AO3
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AS3676
Datasheet - Pinout
4.1
Pin Definitions
Table 2. Pin Type Definitions
Type
DI
Description
Digital Input
Digital Output
DO
Digital Input/Output
Analog Pad
DIO
AIO
AI
Analog Input
High-Voltage (26V) Pin
Analog Output (3.3V)
Supply Pad
AI_HV
AO3
S
Ground Pad
GND
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AS3676
Datasheet - Absolute Maximum Ratings
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 3 may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in Table 4, “Operating
Conditions,” on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Comments
Applicable for high-voltage
current sink pins CURR1,
CURR2, CURR6
VIN_HV
26V Pins
-0.3
26
V
Applicable for 5V pins
VBAT, CURR30-3,
CURR41-43, RGB1-3, C1_N,
C2_N, C1_P, C2_P, CPOUT,
DCDC_FB, CDC_GATE,
CK, DATA;
VIN_MV
VIN_LV
5V Pins
-0.3
7.0
V
Applicable or 3.3V pins
V2DCC_SNS, GPIO1/
DLS, PIO2/LIGHT, VANA/
GPI
3.3V Pins
-0.3
5.0
V
Input Pin Current
Storage Temperature Range
Humidity
-25
5
5
+25
125
85
mA
%
At 25ºC, Norm: JEDEC 17
Tstrg
IIN
Non-condensing
Norm: MIL 883 E Method
3015
VESD
Pt
Electrostatic Discharge
Total Power Dissiption
Peak Body Tmperature
Moisture Sensitivity Level
-2000
20
0.75
260
V
TA = 70 ºC, Tjunc_max =
125ºC
W
ºC
T = 20 to 40s, in accordance
with IPC/JEDEC J-STD 020.
TBODY
MSL
Represents a max. floor life
time of unlimited
MSL 1
6 Electrical Characteristics
Table 4. Operating Conditions
Symbol
Parameter
Condition
Min
Typ
Max
Unit
General Operating Conditions
Applicable for high-voltage current sink pins
CURR1, CURR2 and CURR6.
VHV
VBAT
VPERI
V2_5
High Voltae
0.0
3.0
1.5
2.4
-30
26.0
5.5
5.5
2.6
85
V
V
Batty Votage
Pin VBAT
3.6
Pephery Supply
oltage
For serial interface pins.
Internally generated
V
Volage on Pin V2_5
2.5
25
V
Operating
Temperature Range
TAM
ºC
Normal Operating current (see Operating
Modes on page 80)
IACIVE
Battery current
110
8
µA
µA
µA
Current consumption in standby mode. Only
2.5V regulator on, interface active
ISTANDBY Standby Mode Current
13
3
Shutdown Mode
ISHUTDOWN
interface inactive (CLKand DATA set to 0V)
0.1
Current
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AS3676
Datasheet - Typical Operating Characteristics
7 Typical Operating Characteristics
Figure 2. DCDC Step Up Converter: Efficiency of +15V,
Figure 3. Charge Pump: Efficiency vs. VBAT
Step Up to 15V vs. Load Current at VBAT=3.8V
100
90
80
70
60
50
40
30
20
10
0
90
VOUT=14.2V
VOUT=14.2V
fclk=550kHz
ILOAD=150mA
85
80
75
70
65
VOUT=22V
VOUT=17.2V
ILOAD=305mA
ILOAD=80mA
I
=40mA
LOAD
8
3
3.2
3.4
6
8
4
4.2
0
0.01
0.02
0.03
0.04
0.05
0.06
VBAT [V
Load Current [A]
Figure 4. Charge Pump: Battery Current vs. VBAT
Figure Current Sink CURR1 vsV(CURRx)
40.0
600
500
400
ICURR1=38.25mA
35.0
30.0
25.0
ILOA D=3mA
ICURR1=19.2mAm
300
20
5.0
10.0
200
ILO150mA
ILOA D=80mA
ILOA D=40mA
100
0
5.0
0.0
ICURR1=2.4mA
2.8
3
3.2
3.4
3.6
3.8
4
4.2
0.0
0.5
1.0
1.5
2.0
VBat[V]
VCURR1 [V]
Figure 6.
Figure 7. Current Sink CURR3x vs. VBAT
40.0
CURR30
I
=38.25mA
35.0
30.0
25.0
20.0
15.0
10.0
5.0
CURR30
I
=19.2mAm
CURR30
I
=2.4mA
0.0
0.0
0.5
1. 0
1. 5
2. 0
CURR30
V
[V]
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AS3676
Datasheet - Typical Operating Characteristics
Figure 8. Charge Pump Input and Output Ripple
1:1.5 Mode, 100mA load
Figure 9. Charge Pump Input and Output Ripple
1:2 Mode, 100mA load
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VBAT = 3.6V, TA = +25ºC (unless otherwise specified).
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AS3676
Datasheet - Detailed Description
8 Detailed Description
8.1
Analog LDO
The LDO is a general purpose LDO and the output pin connected to VANA/GPI. The design is optimized to deliver the
best compromise between quiescent current and regulator performance for battery powered devices.
Stability is guaranteed with ceramic output capacitors of 1µF ±20% (X5R) or 2.2µF +100/-50%(Z5U). The low ESR of
these capacitors ensures low output impedance at high frequencies. The low impedance of the power transistor
enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease in performance.
The LDO is off by default after start-up.
Figure 10. Analog LDO Block Diagram
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AS3676
Table 5. Electrical Characteristics
Symbol
VBAT
Parameter
Condition
Min
Typ
Max
Unit
Supply Voltage
Range
3.0
5.5
V
RON
On Resistance
@150mA, full og temperature range
1.0
150
50
@150mA
@50mA
mV
mV
VDROPOUT
ION
Dropout Voltage
Without load
With 150mA load
Without load
50
Supply Current
µA
150
IOFF
tstart
Shutdown Current
Start-up Time
100
200
nA
µs
Output Votage
Tolance
Vout_tol
-3
+3
%
V
VBAT = 3.0V and IOUT=150mA
1.8
1.8
2.85
3.35
VOUT
utput Voltage
Full Programmable Range;
VBAT > VOUT+ 150mV and IOUT<=150mA
V
Pin VANA/GPI. LDO acts as current source if
the output current exceeds ILIMIT.
1
4502
LDO Current Limit
300
mA
ILIM
1. Nt production tested – guaranteed by design and laboratory verification
2. During startup of the LDO the current limit is half the value of ILIMIT
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AS3676
Datasheet - Detailed Description
8.1.1 LDO Registers
Table 6. Reg. control Register
Reg. control
Addr: 00
This register enables/disables the LDOs, Charge Pumps, Charge Pump LEDs,
current sinks, the Step Up DC/DC Converter, and low-power mode.
Bit
Bit Name
Default Access
Description
0
1
Analog LDO is switched off
Analog LDO is switched on
ldo_on
0
0
R/W
Table 7. LDO Voltage Register
LDO Voltage
This register sets the output voltage (VANA/GPI) for the LDO.
Addr: 07h
Bit
Bit Name
Default Access
Description
Controls LDO voltage sectio.
0000b
...
1.8
SB=50mV
3.35V
ldo_voltage
4:0
00000b
R/W
111b
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AS3676
Datasheet - Detailed Description
8.2
Step Up DC/DC Converter
The Step Up DC/DC Converter is a high-efficiency current mode PWM regulator, providing output voltage up to e.g.
25V/50mA1. A constant switching-frequency results in a low noise on the supply and output voltages.
Figure 11. Step Up DCDC Converter Block Diagram Option: Current Feedback with Over voltage protection
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AS3676
Table 8. Step Up DC/DC Converter Paraters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IVDD
Quiescent Curre
Pulse skipping mode.
140
µA
Feedback oltage for
Exteral Rsistor
Dider
For constant voltage control.
VFB1
VFB2
1.20
0.4
1.25 1.30
V
step_up_res = 1
Feedbck Voltage for
Current Sink
on CURR1, CURR2 or CURR6 in regulation.
0.5
0.6
V
step_up_res = 0
Regulation
1. The AS3676 internal driver structure allows output voltage higher than 25V. The Over voltage Protection in
Current Feedback Mode (see page 13) or Voltage Feedback (see page 14) should be set to fit to the exter-
nal components used (maximum voltage rating of Q1, C9 and D1).
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AS3676
Datasheet - Detailed Description
Table 8. Step Up DC/DC Converter Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Additional Tuning
Current at Pin
Adjustable by software using Register DCDC
control1
0
31
µA
DCDC_FB and over
voltage protection
1µA step size (0-31µA)
VPROTECT = 1.25V +
IDCDC_FB * R2
IDCDC_FB
Accuracy of Feedback
Current at full scale
-6
92
50
60
6
%
e.g., 1.32A for 0.1 sense resistor R1.
132
66
170
86
Current Limit Voltage
at R1
For fixed startup time of
500us
Vrsense_max
mV
If step_up_lowcur= 1
ON-resistance of external switching transistor.
At 26V output voltage
86
114
1
RSW
ILOAD
fIN
Switch Resistance
Load Current
mA
0
50
.1
Switching Frequency
Internally trimmed
0.9
1
MHz
Ceramic, ±20%. Use nominal 4.7µF capacitors
to obtain at least 0.7µF uder all conditions
(voltage dependencof cpcitors)
COUT
Output Capacitor
Inductor
0.7
7
4.7
µF
µH
Use inductors with small Crasit(<100pF) to
get hefficiency.
L
10
13
tMIN_ON
Minimum on Time
Maximum Duty Cycle
Voltage ripple >20kHz
Voltage ripple <20kHz
Efficiency
90
90
140
190
ns
%
MDC
160
40
mV
mV
%
Vripple
Cout=4.7µF,Iou=0..45mA, VBA.0...4.2V
Iut=20mA,Vout=17V,VAT=3.8V
Efficiency
85
To ensure soft startup of the dcdc cnver, the over current liits are reduced for a fixed time after enabling the dcdc
converter. The total startup time for atput voltage of 6V is less than 2ms. If C7 and C8 are mounted and the
bit step_up_prot is set, the total startup time can exceed
Note: If the DCDC converter is only used in current feedback mode (CURR1, CURR2 or CURR6 - and not used for a
constant voltage source), the capacitors C7 and C8 can be removed.
8.2.1 Feedback Selection
Register DCDC control1 and DCDC contrselects the type of feedback for the Step Up DC/DC Converter.
The feedback for the DC/DC convrter can be selected either by current sinks (CURR1, CURR2, CURR6) or by a volt-
age feedback at pin DCDC_FB. If te register bit step_up_fb_auto is set, the feedback path is automatically selected
between CURR1, CURR2 and CRR6 (the lowest voltage of these current sinks is used).
Setting step_up_fb enabs feedback on the pins CURR1, CURR2 or CURR6. The Step Up DC/DC Converter is regu-
lated such that the required current at the feedback path can be supported. (Bit step_up_res should be set to 0 in this
configuration)
Note: Alwaychoose the path with the highest voltage drop as feedback to guarantee adequate supply for the other
(unreglated) paths or enable the register bit step_up_fb_auto.
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AS3676
Datasheet - Detailed Description
8.2.2 Over voltage Protection in Current Feedback Mode
The over voltage protection in current feedback mode (step_up_fb = 01, 10 or 11 or step_up_fb_auto = 1) works as fol-
lows: Only resistor R2 and C7/C82 is soldered and R3 is omitted. An internal current source (sink) is used to generate
a voltage drop across the resistor R2. If then the voltage on DCDC_FB is above 1.25V and step_up_prot=1, the DCDC
is momentarily disabled to avoid too high voltages on the output of the DCDC converter. When the voltage on
DCDC_FB drops below 1.25V, the DCDC automatically resumes operation.
The protection voltage can be calculated according to the following formula:
VPROTECT = 1.25V + IDCDC_FB * R2
(EQ 1)
Note: The voltage on the pin DCDC_FB is limited by an internal protection diode to VBAT + one diode forward volt-
age (typ. 0.6V).
If the over voltage protection is not used in current feedback mode, connect DCDC_FB to ground.
Figure 12. Step Up DC/DC Converter Detail Diagram; Option: Regulated Output Current, Feedback is
automatically selected between CURR1, CURR2, CURR6 (step_up_fb_auto=1); over voltae protection
is enabled (step_up_prot=1); 1MHz clock frequency (step_up_frequ=0)
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AS3676
2. If the DCDC converter is only used in current feedback mode (CURR1, CURR2 or CURR6 - and not used
for a constant voltage source), the capacitors C7 and C8 can be removed.
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AS3676
Datasheet - Detailed Description
8.2.3 Voltage Feedback
Setting bit step_up_fb (see page 15) = 00 enables voltage feedback at pin DCDC_FB. Capacitors C7 and C8 have to
be soldered in this operating mode.
The output voltage is regulated to a constant value, given by (Bit step_up_res should be set to 1 in this configuration)
UStep up_out = (R2+R3)/R3 *1.25 + IDCDC_FB * R2
If R3 is not used, the output voltage is by (Bit step_up_res should be set to 0 in this configuration)
UStep up_out = 1.25 + IDCDC_FB * R2
(EQ 2)
(EQ 3)
Where:
UStep up_out = Step Up DC/DC Converter output voltage
R2 = Feedback resistor R2
R3 = Feedback resistor R3
IDCDC_FB = Tuning current at ball DCDC_FB; 0 to 31µA
Table 9. Voltage Feedback Example Values
UStep up_out
UStep upout
IDCDC_FB
µA
0
R2 = 1M, R3 not used
R2 = 0k, R3 = 50k
-
13.75
14.25
14.75
15.25
15.75
16.25
16.75
17.25
17.75
18.25
18.75
19.25
19.75
20.25
20.75
21.25
…
1
2
3
-
4
-
5
6.25
7.25
8.25
5
11.25
12.25
13.25
14.25
15.25
16.25
…
6
7
8
9
10
11
12
13
14
15
…
30
3
31.25
32.25
28.75
29.25
Note: The voage on CURR1, CURR2 and CURR6 must not exceed 26V (see page 25)
8.4 CB Layout Hints
To esure good EMC performance of the DCDC converter, keep its external power components C6, R1, L1, Q1, D1
and C9 close together. Connect the ground of C6, R1 and C9 locally together and connect this with a short path to
AS3676 VSS. This ensures that local high-frequency currents will not flow to the battery.
8.2.5 Unused DCDC converter
If the DCDC converter is not used, connect DCDC_SNS to GND. DCDC_FB3 and DCDC_GATE can be left open.
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AS3676
Datasheet - Detailed Description
8.2.6 Step up Registers
Table 10. Reg. control Register
Reg. control
Addr: 00
This register enables/disables the Charge Pump and the Step Up DC/DC
Converter.
Bit
Bit Name
Default Access
Description
Enable the step up converter
Disable the Step Up DC/DC Converter
Enable the Step Up DC/DC Converter
step_up_on
0b
1b
3
0
R/W
Table 11. DCDC control1 Register
DCDC control1
Addr: 21h
This register controls the Step Up DC/DC Conerter
Bit
Bit Name
Default Access
Description
Dfines e clock frequency of thStep Up DC/DC
Converter.
step_up_frequ
R/W
R/W
0
0
0
1
1MHz
500kHz
Controls the feedbck source if step_up_fb_auto = 0
DCDCFB enabled (external resistor divider).
00
Set step_up_fb=00 (DCDC_FB)
step_up_fb
2:1
00
01
10
1
CURR1 feedback enabled (feedback via LEDs)
CURR2 feedback enabled (feedback via LEDs)
CURR6 feedback enabled (feedback via LEDs)
Defines the tuning current at pin DCDC_FB.
00000
00001
00010
....
0 µA
1 µA
2 µA
step_up_vtuning
7:3
0000
R/W
10000
.....
15 µA
31 µA
11111
3. DCDC_FB can be used as a general purpose ADC input (see Analog-to-Digital Converter on page 65)
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AS3676
Datasheet - Detailed Description
Table 12. DCDC control2 Register
DCDC control2
Addr: 22h
This register controls the Step Up DC/DC Converter and low-voltage current
sinks CURR3x.
Bit
Bit Name
Default Access
Description
Gain selection for Step Up DC/DC Converter
Select 0 if Step Up DC/DC Converter is used
with current feedback (CURR1, CURR2,
CURR6) or if DCDC_FB is used with current
feedback only – R2, C7, C8 connected, R3 not
used
0
1
step_up_res
0
0
0
R/W
R/W
Select 1 if DCDC_FB is used with extenal
resistor divider using 2 resistors: R2 and R3
Step Up DC/DC Converter output voltage at low loads,
when pulse skipping is active
skip_fast
1
0
1
Accurate output voltage, ore ripple
Elevated output ltageless ripple
SteUp DC/DC Converter protection
No over voltage protection
0
1
step_up_prot
2
3
1
0
R/W
R/W
Over voltge protection on pin DCDC_FB
enabled voltaglmitation =1.25V on DCDC_FB
Step Up D/DC Converter coil current limit
Normal current limit
step_up_lowcur
0
1
Current limit reduced by approx. 33%
step_up_fb selects the feedback of the DCDC
converter
0
If step_up_fb is not DCDC_FB (00), then
feedback is automatically chosen within the
current sinks CURR1, CURR2 and CURR6.
Only those are used for this selection, which are
enabled (currX_mode must not be 00) and not
connected to the charge pump (currX_on_cp
must be 0).
step_up_fb_auto
7
0
R/W
1
8.3
Charge Pump
The Charge Pump uses two exteal flyng capacitors C3, C4 to generate output voltages higher than the battery volt-
age. There are three different peraing modes of the charge pump itself:
1:1 Bypass Mode
- Battery input and ouput are connected by a low-impedance switch
- battery current = utput current.
1:1.5 Mode
- The outut voltage is up to 1.5 times the battery voltage (without load), but is limited to VCPOUTmax all the time
- battery crret = 1.5 times output current.
1:2 e
- The output voltage is up to 2 times the battery voltage (without load), but is limited to VCPOUTmax all the time
- battery current = 2 times output current
As the battery voltage decreases, the Charge Pump must be switched from 1:1 mode to 1:1.5 mode and eventually in
1:2 mode in order to provide enough supply for the current sinks. Depending on the actual current the mode with best
overall efficiency can be automatically or manually selected:
Examples:
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AS3676
Datasheet - Detailed Description
Battery voltage = 3.7V, LED dropout voltage = 3.5V. The 1:1 mode will be selected and there is 200mV drop on the
current sink and on the Charge Pump switch. Efficiency 95%.
Battery voltage = 3.5V, LED dropout voltage = 3.5V. The 1:1.5 mode will be selected and there is 1.5V drop on the
current sink and 250mV on the Charge Pump. Efficiency 66%.
The efficiency is dependent on the LED forward voltage given by:
Eff=(V_LED*Iout)/(Uin*Iin)
(EQ 4)
The charge pump mode switching can be done manually or automatically with the following possible software settings:
Automatic up all modes allowed (1:1, 1:1.5, 1:2)
- Start with 1:1 mode
- Switch up automatically 1:1 to 1:1.5 to 1:2
Automatic up, but only 1:1 and 1:1.5 allowed
- Start with 1:1 mode
- Switch up automatically only from 1:1 to 1:1.5 mode; 1:2 mode is not used
Manual
- Set modes 1:1, 1:1.5, 1:2 by software
Figure 13. Charge Pump Pin Connections
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The Charge Pump requires the external ponents listed in the following table:
Table 13. Charge Pump External Comonents
Symbol
Parameter
Condition
Min
Typ
Max
Unit
External Decoupling
Capaitor
Ceramic low-ESR capacitor between pins
VBAT and VSS.
C2
1.0
µF
Ceramic low-ESR capacitor between pins
C1_P and C1_N, between pins C2_P and
C2_N and between VBAT and VSS
Eternal Flying
Caacitor (2x)
C3, C4
C5
1.0
2.2
µF
µF
Ceramic low-ESR capacitor between pins
CPOUT and VSS, pins CPOUT and VSS. Use
nominal 2.2µF capacitors (size 0603)
External Storage
Capacitor
Note: The connections of the external capacitors C2, C3, C4 and C5 should be kept as short as possible.
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AS3676
Datasheet - Detailed Description
The maximum voltage on the flying capacitors C3 and C4 is VBAT.
Table 14. Charge Pump Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Output Current
Continuous
Depending on PCB layout
0.0
400
mA
ICPOUT
max. 200ms
VCPOUT=
VBAT * CPMODE – ILOAD * RCP
Output Current
Pulsed
0.0
60
500
mA
VCPOUTmax
Output Voltage
Efficiency
Internally limited, Including output ripple
5.6
90
V
Including current sink loss;
ICPOUT < 100mA.
%
ICP1_1.5
ICP1_2
Power Consumption
without Load
1:1.5 Mode
3.4
3.8
mA
1:2 Mode
fclk = 1 MHz
Rcp1_1
Rcp1_1.5
Rcp1_2
1:1 Mode; VBAT 3.5V
1:1.5 Mode; VBAT 3.3V
1:1.2 Mode; VBAT 3.1V
0.57
2.65
3.2
Effective Charge
Pump Output
Resistance (Open
Loop, fclk = 1MHz)
Accuracy of Clock
Frequency
fclk Accuracy
currhv_switch
10
10
%
V
CURR1, 2, 6
minimum voltage
0.45
CURR30-33, RGB1-
3, CURR41-3,
If the voltage drops below this thresold, te
charge pumwill use the next avaible
mode
0.2
0.4
V
V
minimum voltage
CURR30-33
0-75.6mA range
for strobe if
curr3x_strobe_high=
1
currlv_switch
1:1 -> 1:1.5 or 11.5 -1:2
cp_debounce=0
240
µsec
µsec
CP automatic up-
switching debounce
time
tdeb
After switching CP (cp_on set to 1), if
cp_start_debounce=1
2000
8.3.1 Charge Pump Mode Switchin
If automatic mode switching is enabled cmoe_switching (see page 20) = 00 or cp_mode_switching = 01) the
charge pump monitors the current sinks, h are connected via a led to the output CPOUT. To identify these current
sources (sinks), the registers CP mode Switch1 and CP mode Switch2 (register bits curr30_on_cp (see page 21) …
curr33_on_cp, rgb1_on_cp … rgb_oncp, curr1_on_cp, curr2_on_cp, curr41_on_cp … curr43_on_cp and
curr6_on_cp) should be setup bfore starting the charge pump (cp_on (see page 20) = 1). If any of the voltage on
these current sources drops elow the threshold (currlv_switch, currhv_switch), the next higher mode is selected after
the debounce time.
To avoid switchinito :2 mode (battery current = 2 times output current), set cp_mode_switching = 01.
If the currX_on_cp=0 and the according current sink is connected to the charge pump, the current sink will be func-
tional, but thee is no up switching of the charge pump, if the voltage compliance is too low for the current sink to sup-
ply the specifiecurrent.
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AS3676
Datasheet - Detailed Description
Figure 14. Automatic Mode Switching
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AS3676
8.3.2 Soft Start
An implemented soft start mechanism reduces the inrush current. Battery current is smoothed when switching the
charge pump on and also at each switching condition. This precaution reduces electromagnetic radiation significantly.
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Datasheet - Detailed Description
8.3.3 Unused Charge Pump
If the charge pump is not used, capacitors C3, C4 and C5 can be removed. The pins C1_P, C1_N, C2_P, C2_N and
CPOUT should be left open and keep register cp_on and cp_auto_on at 0 (default value).
8.3.4 Charge Pump Registers
Table 15. Reg. control Register
Reg. control
Addr: 00h
This register controls the Charge Pump.
Bit
Bit Name
Default Access
Description
Set Charge Pump into 1:1 mode (off state) unls
cp_auto_on is set
0
1
cp_on
2
0
R/W
Enable manual or automatic mode switchig
Table 16. CP control Register
CP control
Addr: 23h
This register enables/diables the Charge Pump anthe Sep Up DC/DC
Converter.
Bit
Bit Name
Default Access
Description
Clock quency selection.
1 MHz
cp_clk
0
0
R/W
1
500 kHz
Charge Pumode (in manual mode sets this mode, in
aumatic mode reports the actual mode used)1
00
01
11
1:1 mode
cp_mode
2:1
00b
R/W
1:1.5 mode
1:2 mode
NA
Set the mode switching algorithm
Automatic Mode switching; 1:1, 1:1.5 and 1:2
allowed
00
01
10
Automatic Mode switching; only 1:1 and 1:1.5
allowed
cp_mode_switching
4:3
b
R/W
Manual Mode switching; register cp_mode defines
the actual charge pump mode used
11
0
Reserved
Mode switching debounce timer is always 240µs
Upon startup (cp_on set to 1) the mode switching
debounce time is first started with 2ms then
reduced to 240µs
cp_stat_debounce
cp_auto_on
5
0
0
R/W
R/W
1
0
Charge Pump is switched on/off with cp_on
Charge Pump is automatically switched on if a
current sink, which is connected to the charge
pump (defined by registers CP Mode Switch 1 & 2)
is switched on
1
1. Direct switching from 1:1.5 mode into 1:2 in manual mode and vice versa is not allowed. Always switch over 1:1
mode.
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Datasheet - Detailed Description
Table 17. CP mode Switch1 Register
CP mode Switch1
Setup which current sinks are connected (via leds) to the charge pump; if set to
‘1’ the correspond current source (sink) is used for automatic mode selection of
the charge pump
Addr: 24h
Bit
Bit Name
Default Access
Description
current Sink CURR30 is not connected to charge
pump
0
1
0
1
0
1
0
1
0
1
0
curr30_on_cp
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
current sink CURR30 is connected to charge pump
current Sink CURR31 is not connected to charge
pump
curr31_on_cp
curr32_on_cp
curr33_on_cp
rgb1_on_cp
rgb2_on_cp
rgb3_on_cp
1
2
3
4
5
6
current sink CURR31 is connected to charge pump
current Sink CURR32 is not connected to charge
pump
current sink CURR32 is connecteto carge pump
current Sink CURR33 is t conected to charge
pump
curret sink CURR33 s conected to charge pump
current Sink RGB1 is not connected to charge
pump
current sink GB1 is connected to charge pump
current Snk RGB2 is not connected to charge
pump
urrent sink RGB2 is connected to charge pump
current Sink RGB3 is not connected to charge
pump
current sink RGB3 is connected to charge pump
Table 18. CP mode Switch2 Register
CP mode Switch2
Setup hich current sinks are connected (via LEDs) to the charge pump; if set
t‘the correspond current source (sink) is used for automatic mode selection
of the charge pump
Addr: 25h
Bit
Bit Name
Default Access
Description
current Sink CURR1is not connected to charge
pump
0
1
0
1
0
1
0
1
curr1_on_p
0
0
0
0
0
R/W
R/W
R/W
R/W
current sink CURR1 is connected to charge pump
current Sink CURR2 is not connected to charge
pump
cur2_on_cp
curr41_on_cp
curr42_on_cp
1
2
3
current sink CURR2 is connected to charge pump
current Sink CURR41 is not connected to charge
pump
current sink CURR41 is connected to charge pump
current Sink CURR42 is not connected to charge
pump
current sink CURR42 is connected to charge pump
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Datasheet - Detailed Description
Table 18. CP mode Switch2 Register (Continued)
CP mode Switch2
Setup which current sinks are connected (via LEDs) to the charge pump; if set
to ‘1’ the correspond current source (sink) is used for automatic mode selection
of the charge pump
Addr: 25h
Bit
Bit Name
Default Access
Description
current Sink CURR43 is not connected to charge
pump
0
1
0
1
curr43_on_cp
curr6_on_cp
4
0
0
R/W
R/W
current sink CURR43 is connected to charge pump
current Sink CURR6 is not connected to charge
pump
7
current sink CURR6 is connected to charge ump
Table 19. Curr low voltage status1 Register
Curr low voltage status1
Indicates the low voltage status of the current sinks. the urrX_low_v bit is
set, the voltage on the urrensink is too low, to drive the selected output
current
Addr: 2Ah
Bit
Bit Name
Default Access
Description
0
1
0
1
0
0
1
0
1
0
1
0
1
voltage of cunt Sink CURR30 >currlv_switch
voltage ocrent Sink CURR30 <currlv_switch
voltage of current Sink CURR31 >currlv_switch
voge f current Sink CURR31 <currlv_switch
oltage of current Sink CURR32 >currlv_switch
voltage of current Sink CURR32 <currlv_switch
voltage of current Sink CURR33 >currlv_switch
voltage of current Sink CURR33 <currlv_switch
voltage of current Sink RGB1 >currlv_switch
voltage of current Sink RGB1 <currlv_switch
voltage of current Sink RGB2 >currlv_switch
voltage of current Sink RGB2 <currlv_switch
voltage of current Sink RGB3 >currlv_switch
voltage of current Sink RGB31 <currlv_switch
voltage of current Sink CURR6 >currlv_switch
voltage of current Sink CURR6 <currlv_switch
curr30_low_v
curr31_low_v
curr32_low_v
curr33_low_v
rgb1_low_v
rgb2_low_v
rgb3_low_v
curr6_lw_v
0
NA
NA
A
NA
NA
N
NA
NA
R
R
R
R
R
R
R
1
2
3
4
5
6
7
Table 20. Curlow voage status2 Register
Curr low voltage status2
Indicates the low voltage status of the current sinks. If the currX_low_v bit is
set, the voltage on the current sink is too low, to drive the selected output
current
Addr: 2Bh
Bit
Bit Name
curr1_low_v
Default Access
Description
0
1
voltage of current Sink CURR1 >currhv_switch
voltage of current Sink CURR1 <currhv_switch
0
NA
R
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Datasheet - Detailed Description
Table 20. Curr low voltage status2 Register (Continued)
Curr low voltage status2
Indicates the low voltage status of the current sinks. If the currX_low_v bit is
set, the voltage on the current sink is too low, to drive the selected output
current
Addr: 2Bh
Bit
Bit Name
Default Access
Description
0
1
0
1
0
1
0
1
voltage of current Sink CURR2 >currhv_switch
voltage of current Sink CURR2 <currhv_switch
voltage of current Sink CURR41 >currlv_switch
voltage of current Sink CURR41 <currlv_swith
voltage of current Sink CURR42 >currlv_sitch
voltage of current Sink CURR42 <currlv_swch
voltage of current Sink CURR43 >urrlv_switch
voltage of current Sink CURR43 currlv_switch
curr2_low_v
curr41_low_v
curr42_low_v
curr43_low_v
1
NA
NA
NA
NA
R
R
R
R
2
3
4
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AS3676
Datasheet - Detailed Description
8.4
Current Sinks
The AS3676 contains general purpose current sinks intended to control RGB LEDs, white LEDs (e.g. backlights) and
can also be used for buzzers or vibrators. All current sinks have an integrated over voltage protection.
CURR1, CURR2 and CURR6 are also used as feedback for the Step Up DC/DC Converter (regulated to 0.5V in this
configuration) see Feedback Selection on page 12.
Current sinks CURR1, CURR2 and CURR6 are high-voltage compliant (26V) current sinks, used e.g., for series of
white LEDs
Current sinks CURR3x (CURR30, CURR31, CURR32 and CURR33) are parallel 5V current sinks, used for back-
lighting, indicator LEDs or RGB LEDs.
Current sinks RGB1, RGB2, and RGB3 are general purpose current sinks e.g. for a fun LED.
Current sinks CURR4x (CURR41, CURR42, and CURR43) are general purpose current sinks.
Table 21. Current Sink Function Overview
Max.
Current Sink Voltage
(V)
Max.
Current
(mA)
Resolution
Software
Current
Control
Can be assignto
Auio Controlled
LEChannel
Hardware On/Off
Control
(Bits)
(mA)
CURR1
ch1
ch2
ch3
LED Pattern;
Internal PWM;
external PWM at
GPIO1/DLS
CURR2
CURR6
26.0
38.25
8
8
0.15
Searate
Flash LED Strobe
(CRR1 or
CUR30) &
review
CURR30
CURR31
CURR32
38.25
ombined in
Strobe/
Preview
or
Completely individual
assignment of the
audio channels
(75.6mA
for strobe
if
curr3x_str
obe_high=
1)
(CRR2);
0.15
Iernal PWM; ch1,ch2 and ch3 to the
outputs
Separate
LED Pattern;
xternal PWM at
GPIO1/DLS
CURR33
RGB1
VBAT
(5.5V)
ch1
ch2
ch3
ch1
ch2
ch3
LED Pattern;
Internal PWM;
external PWM at
GPIO1/DLS
RGB2
38.25
38.25
8
8
0.15
0.15
Searate
Separate
RGB3
CURR41
CURR42
CURR43
LED Pattern;
Internal PWM;
external PWM at
GPIO1/DLS
8.4.1 Unused Current Sinks
Unused current sinks can be left oen r used as a ADC input (see Analog-to-Digital Converter on page 65).
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AS3676
Datasheet - Detailed Description
8.4.2 High Voltage Current Sinks CURR1, CURR2, CURR6
The high voltage current sinks have a resolution of 8 bits.
Table 22. HV Current Sinks Characteristics
Symbol
IBIT7
IBIT6
IBIT5
IBIT4
IBIT3
IBIT2
IBIT1
IBIT0
Parameter
Condition
Min
Typ
19.2
9.6
Max
Unit
Current sink if Bit7 = 1
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
4.8
2.4
For V(CURRx) > 0.45V
mA
1.2
0.6
0.3
0.15
I
BIT7 and IBIT6
-5
5
%
%
m1
matching Accuracy
CURR1,CURR2,CURR6
all other bits
-10
+10
absolute Accuracy
Voltage compliance
-15
+15
26
%
V
VCURR1,2,6x
0.45
1. Variation between currents within this group
2. Variation between the programmed current and the actual current
High Voltage Current Sinks CURR1, CURR2, CURR6 Registers
Table 23. Curr1 current Register
Curr1 current
Addr: 09h
This recontrols the High voltage current sink current.
Bit
Bit Name
Default Access
Description
Defines current into current sink curr1
00h
01h
....
0 mA
0.15 mA
....
curr1_current
7:0
R/W
FFh
38.25 mA
Table 24. Curr2 current Regiter
Curr2 current
Adr: 0A
This register controls the High voltage current sink current.
Bit
Bit Name
Default Access
Description
Defines current into current sink curr2
00h
01h
....
0 mA
0.15 mA
....
curr2_current
0
0
R/W
FFh
38.25 mA
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AS3676
Datasheet - Detailed Description
Table 25. curr6 current Register
curr6 current
Addr: 2Fh
This register controls the High voltage current sink current.
Bit
Bit Name
Default Access
Description
Defines current into current sink CURR6
00h
01h
....
0 mA
0.15 mA
....
curr6_current
7:0
0
R/W
FFh
38.25 mA
Table 26. curr12 control Register
curr12 control
Addr: 01h
This register select the mode of the current sinks controls Hih voage current
sink current.
Bit
Bit Name
Default Access
Descriptio
Selethe mode of the current sink curr1
00b
1b
10b
11b
off
curr1_mode
on
PWM controlled
1:0
0
0
R/W
R/W
LED pattern controlled
Selthmode of the current sink curr2
off
00b
1b
10b
11b
curr2_mode
on
3:2
PWM controlled
LED pattern controlled
Table 27. curr rgb control Register
curr rgb control
Addr: 02h
This register select the mode of the current sinks CURR6.
Bit
Bit Name
Default Access
Description
Select the mode of the current sink CURR6
00b
01b
10b
11b
off
on
curr6_mde
7:6
0
R/W
PWM controlled
LED pattern controlled
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AS3676
Datasheet - Detailed Description
8.4.3 Current Sinks CURR30, CURR31, CURR32, CURR33
These current sinks have a resolution of 8 bits and can sink up to 38.25mA. The current values can be controlled indi-
vidually with curr30_current – curr33_current or common with curr3x_strobe or curr3x_preview.
Table 28. Current Sinks CURR30,31,32,33 Parameters
Symbol
IBIT7
IBIT6
IBIT5
IBIT4
IBIT3
IBIT2
IBIT1
IBIT0
Parameter
Condition
Min
Typ
19.2
9.6
Max
Unit
Current sink if Bit7 = 1
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
4.8
2.4
For V(CURR3x) > 0.2V
mA
1.2
0.6
0.3
0.1
I
BIT7 and IBIT6
ll other bits
-5
+5
%
%
m1
matching Accuracy
absolute Accuracy
Voltage compliance
CURR30-33
-10
+10
1
+15
%
V
0.2
0.4
CPO
UT
VCURR3X
curr3x_strobe_hig=1 and strobe funtion
1. Variation between currents within this group
2. Variation between the programmed current ad the actual current
Current Sinks CURR3x Registers
Table 29. Curr3 control2 Register
Curr3 control2
This egister selects the modes of the current sinks30..33 current.
Addr: 12h
Bit
Bit Name
Deult Access
Description
Select the switch off mode after strobe pulse
normal preview/strobe mode
0
1
preview_off_after strobe
0
R/W
switch off preview after strobe duration has
expired. To reinitiate the torch mode the
preview_ctrl has to be set off and on again
Preview is triggered by
off
00b
01b
software trigger (setting this bit automatically
triggers preview)
prview_ctrl
2:1
00b
0b
R/W
R/W
10b
11b
CURR2 active high; set gpi_curr2_en=1
CURR2 active low; set gpi_curr2_en=1
Double current on CURR30...CURR33
during strobe function
curr3x_strobe_high
5
0
1
normal strobe current (0-37.8mA)
double strobe current (0-75.6mA)
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AS3676
Datasheet - Detailed Description
Table 29. Curr3 control2 Register (Continued)
Curr3 control2
Addr: 12h
This register selects the modes of the current sinks30..33 current.
Bit
Bit Name
Default Access
Description
Select strobe input pin and current sink outputs (only if
strobe_ctrl=10 or 11)
CURR1 is strobe input; CURR30...CURR33
strobe_pin
7
0
R/W
0
flash output; set gpi_curr1_en=1
CURR30 is strobe input; CURR1, CURR2,
CURR6 flash output; set gpi_curr30_en=1
1
Table 30. Curr3 strobe control Register
Curr3 strobe control
Addr: 11h
This register selects the modes of the current sinks3..33 urrent.
Bit
Bit Name
Default Access
Description
Strobe is triggereby
off
00b
software trigger (setting this bit automatically
triggers strobe)
strobe_ctrl
1:0
00b
R/W
CUR1 (or CURR30 see strobe_pin)
active high
10b
11b
CURR1 (or CURR30 see strobe_pin)
active low
Selects strobe mode
Mode1 (Tstrobe=Ts; strobe trigger signal
b
10µs)
strobe_mode
3:2
00b
R/W
1b
10b
11b
Mode 2 (Tstrobe=max Ts)
Mode 3 (Tstrobe = strobe signal)
not used
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AS3676
Datasheet - Detailed Description
Table 30. Curr3 strobe control Register (Continued)
Curr3 strobe control
This register selects the modes of the current sinks30..33 current.
Addr: 11h
Bit
Bit Name
Default Access
Description
Selects strobe time (Ts)
100 msec
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000
100b
1010b
11b
100b
1101b
1110b
1111b
200 msec
300 msec
400 msec
500 msec
600 msec
700 mse
strobe_timing
7:4
0000b
R/W
800 msec
900 sec
1000 msec
1100 msec
1200 msec
1300 msec
1400 msec
1500 msec
1600 msec
Table 31. Curr3x strobe Register
Curr3x strobe
This egister selects the strobe current of the current sinks30..33
Addr: 0Eh
Bit
Bit Name
Default Access
Description
Defines Strobe current of Current sinks curr30-33
00h
01h
....
0 mA
curr3x_strobe
5:0
00
R/W
0.6 mA (1.2mA if curr3x_strobe_high=1)
....
3Fh
37.8 mA (75.6mA if curr3x_strobe_high=1)
Table 32. Curr3previw Register
Curr3x preview
Addr: 0Fh
This register selects the preview current of the current sinks30..33
Bit
Bit Name
Default Access
Description
Defines Preview current of Current sinks curr30-33
00h
01h
....
0 mA
0.6 mA
....
curr3x_preview
5:0
00
R/W
3Fh
37.8 mA
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AS3676
Datasheet - Detailed Description
Table 33. Curr3x other Register
Curr3x other
Addr: 10h
This register selects the current of the current sinks30..33
Bit
Bit Name
Default Access
Description
Selects CURR30...33 current, if CURR30...33 is not
programmed for strobe/preview
(curr30_mode...curr33_mode=11b)
00h
01h
....
0 mA
0.6 mA
....
curr3x_other
5:0
00
R/W
3Fh
37.8 mA
Table 34. Curr30 current Register
Curr30 current
This register selects the current of the crrent ink30
Addr: 40h
Bit
Bit Name
Default Access
Description
Seleccurr30 current, if cur30 inot used for strobe/
preview (curr30_mode=11b)
0h
01h
....
0 mA
0.15 mA
....
curr30_current
7:0
00
R/W
FFh
38.25 mA
Table 35. Curr31 current Register
Curr31 current
This er selects the current of the current sink31
Addr: 41h
Bit
Bit Name
Default Acess
Description
Selects curr31 current, if curr31 is not used for strobe/
preview (curr31_mode=11b)
00h
01h
....
0 mA
0.15 mA
....
curr31_current
7:0
R/W
FFh
38.25 mA
Table 36. Curr32 currnt Rgister
Curr32 current
This register selects the current of the current sink32
Addr: 4h
Bit
Bit Name
Default Access
Description
Selects CURR32 current, if CURR32 is not used for strobe/
preview (curr32_mode=11b)
00h
01h
....
0 mA
0.15 mA
....
curr32_current
7:0
00
R/W
FFh
38.25 mA
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AS3676
Datasheet - Detailed Description
Table 37. Curr33 current Register
Curr33 current
Addr: 43h
This register selects the current of the current sink33
Bit
Bit Name
Default Access
Description
Selects curr33 current, if curr33 is not used for strobe/
preview (curr33_mode=11b)
00h
01h
....
0 mA
0.15 mA
....
curr33_current
7:0
00
R/W
FFh
38.25 mA
Table 38. curr3 control1 Register
curr3 control1
This register select the mode of the current sinks30 33
Addr: 03h
Bit
Bit Name
Default Access
Descriptio
Selecthe mode of thcurrent sink curr30
off
00b
1b
10b
strobe/preview
curr30_mode
1:0
0
0
0
R/W
R/W
R/W
curr30_currnt or curr3x_other PWM controlled
curr30current or curr3x_other - don’t use
curr3x_other if softdim_pattern=1, use
curr30_current instead
11b
Selct the mode of the current sink curr31
b
1b
10b
off
strobe/preview
curr31_mode
3:2
curr31_current or curr3x_other PWM controlled
curr31_current - don’t use curr3x_other if
softdim_pattern=1, use curr31_current instead
11b
Select the mode of the current sink CURR32
00b
01b
10b
off
strobe/preview
curr32_mode
5:4
curr32_current or curr3x_other PWM controlled
curr32_current or curr3x_other - don’t use
curr3x_other if softdim_pattern=1, use
curr32_current instead
11b
Select the mode of the current sink curr33
00b
01b
10b
off
strobe/preview
curr33_mode
7:6
0
R/W
curr33_current or curr3x_other PWM controlled
curr33_current or curr3x_other- don’t use
curr3x_other if softdim_pattern=1, use
curr33_current instead
11b
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AS3676
Datasheet - Detailed Description
Table 39. Pattern control Register
Pattern control
Addr: 18h
This register controls the LED pattern
Description
Bit
Bit Name
Default Access
Additional CURR33 LED pattern control bit
CURR30 controlled according curr30_mode
curr30_pattern
4
0b
0b
0b
0b
R/W
R/W
R/W
R/W
0b
register
1b
CURR30 controlled by LED pattern generator
Additional CURR33 LED pattern control bit
CURR31 controlled according curr31_mode
register
curr31_pattern
curr32_pattern
curr33_pattern
5
6
7
0b
1b
CURR31 controlled by LED pattern genetor
Additional CURR33 LED patterconrol bit
CURR32 controlled accoding curr33_mode
reister
0b
1b
CRR32 controlled by LD pattern generator
ddiional CURR33 LED patern control bit
CURR33 ntrolled according curr33_pattern
register
b
1b
CURR33 cntrolled by LED pattern generator
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Datasheet - Detailed Description
8.4.4 Current Sinks RGB1, RGB2, RGB3
These current sinks have a resolution of 8 bits and can sink up to 38.25mA.
Table 40. Current Sinks RGB1, RGB2, RGB3 Parameters
Symbol
IBIT7
IBIT6
IBIT5
IBIT4
IBIT3
IBIT2
IBIT1
IBIT0
Parameter
Condition
Min
Typ
19.2
9.6
Max
Unit
Current sink if Bit7 = 1
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
4.8
2.4
For V(RGBx) > 0.2V
mA
1.2
0.6
0.3
0.15
I
BIT7 and IBIT6
all other bits
-5
5
%
%
m1
matching Accuracy
RGB1, RGB2, RGB3
-10
+10
absolute Accuracy
Voltage compliance
-15
0.2
+15
%
V
CPO
UT
VRGBX
1. Variation between currents within this group
2. Variation between the programmed current and the actual current
RGB Current Sinks Registers
Table 41. curr rgb control Register
curr rgb control
This register the mode of the current sinks RGB1, RGB2, RGB3
Addr: 02h
Bit
Bit Name
Default Acess
Description
Select the mode of the current sink RGB1
00b
01b
10b
11b
off
rgb1_mode
1:0
0
0
R/W
R/W
R/W
on
PWM controlled
LED pattern controlled
Select the mode of the current sink RGB2
00b
01b
10b
11b
off
rb2_mode
rgb3_mode
3:2
5:4
on
PWM controlled
LED pattern controlled
Select the mode of the current sink RGB3
off
00b
01b
10b
11b
on
PWM controlled
LED pattern controlled
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AS3676
Datasheet - Detailed Description
Table 42. Rgb1 current Register
Rgb1 current
Addr: 0Bh
This register controls the RGB current sink current.
Bit
Bit Name
Default Access
Description
Defines current into Current sink RGB1
00h
01h
....
0 mA
0.15 mA
....
rgb1_current
7:0
0
R/W
FFh
38.25 mA
Table 43. Rgb2 current Register
Rgb2 current
Addr: 0Ch
This register controls the RGB current sink curent.
Bit
Bit Name
Default Access
Description
Dfes current into Currensink RGB2
00h
....
0 A
0.15 mA
....
rgb2_current
7:0
0
R/W
FFh
38.25 mA
Table 44. Rgb3 current Register
Rgb3 current
Addr: 0Dh
This regier controls the RGB current sink current.
Bit
Bit Name
efault Access
Description
Defines current into Current sink RGB3
00h
01h
....
0 mA
0.15 mA
....
rgb3_current
7:0
0
R/W
FFh
38.25 mA
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AS3676
Datasheet - Detailed Description
8.4.5 General Purpose Current Sinks CURR4x
These low voltage current sinks have a resolution of 8 bits and can sink up to 38.25mA.
Table 45. CURR4x Sinks Characteristics
Symbol
IBIT7
IBIT6
IBIT5
IBIT4
IBIT3
IBIT2
IBIT1
IBIT0
Parameter
Condition
Min
Typ
19.2
9.6
Max
Unit
Current sink if Bit7 = 1
Current sink if Bit6 = 1
Current sink if Bit5 = 1
Current sink if Bit4 = 1
Current sink if Bit3 = 1
Current sink if Bit2 = 1
Current sink if Bit1 = 1
Current sink if Bit0 = 1
4.8
2.4
For V(CURRx) > 0.2V
mA
1.2
0.6
0.3
0.15
I
BIT7 and IBIT6
-5
5
%
%
m1
matching Accuracy
absolute Accuracy
CURR4x
all other bits
-10
+10
-15
0.2
+15
%
V
CPO
UT
VCURR41,42,43x Voltage compliance
1. Variation between currents within this group
2. Variation between the programmed current and the actual current
General Purpose Current Sinks CURR4Reisters
Table 46. curr4 control Register
curr4 control
Addr: 04h
This register s the mode of the current sinks CURR41, CURR42,
CURR43
Bit
Bit Name
Default Aces
Description
Select the mode of the current sink CURR41
00b
01b
10b
11b
off
curr41_mode
1:0
0
0
R/W
R/W
R/W
on
PWM controlled
LED pattern controlled
Select the mode of the current sink CURR42
00b
01b
10b
11b
off
curr2_mode
curr43_mode
3:2
5:4
on
PWM controlled
LED pattern controlled
Select the mode of the current sink CURR43
00b
01b
10b
11b
off
on
PWM controlled
LED pattern controlled
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AS3676
Datasheet - Detailed Description
Table 47. Curr41 current Register
Curr41 current
Addr: 13h
This register controls the curr41 current sink current.
Bit
Bit Name
Default Access
Description
Defines current into Current sink CURR41
00h
01h
....
0 mA
0.15 mA
....
curr41_current
7:0
0
R/W
FFh
38.25 mA
Table 48. Curr42 current Register
Curr42 current
Addr: 14h
This register controls the curr42 current sink cuent.
Bit
Bit Name
Default Access
Description
Defns current into Current nk CURR42
00h
....
0 A
0.15 mA
....
curr42_current
7:0
0
R/W
FFh
38.25 mA
Table 49. Curr43 current Register
Curr43 current
Addr: 15h
This regiser cotrols the curr43 current sink current.
Bit
Bit Name
efault Access
Description
Defines current into Current sink CURR43
00h
01h
....
0 mA
0.15 mA
....
curr43_current
7:0
0
R/W
FFh
38.25 mA
8.4.6 LED Pattern Geneato
The LED pattern generator icapble of producing a pattern with 32 bits length and 1 second duration (31.25ms for
each bit). The pattern itsecan be started every second, every 2nd, 3rd up to 7th second4.
With this pattern l urrnt sinks can be controlled. The pattern itself switches the configured current sources between
0 and their programed current.
If everything se is switched off, the current consumption in this mode is IACTIVE. (excluding current through switched
on current source) and the charge pump, if required. The charge pump can be automatically switched on/off depending
on he pern (set register cp_auto_on on page 20=1) to reduce the overall current consumption.
LEpattern start/stop depends on writing the pattern registers in correct order - it is recommended to use austriami-
crosytems Android driver to ensure this.
4. All times can be extended by a factor of 8 by setting pattern_slow=1 (this result in a delay of up to 56s)
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AS3676
Datasheet - Detailed Description
Figure 15. LED Pattern Generator AS3676 for pattern_color = 0
%ꢇꢝꢊꢁꢇꢚꢃ"ꢂꢃ"ꢊꢈꢃꢊꢁꢃꢈꢘꢇꢃꢉꢇꢈꢅ#ꢃꢆꢇ$ꢊꢉꢈꢇꢆꢃ#ꢀꢈꢈꢇꢆꢁ&ꢚꢀꢈꢀ
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ꢃ
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ꢎꢍ ꢌ ꢍ ꢎ ꢏ ꢐ ꢑꢒ ꢓ ꢔ
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(ꢍꢐ ꢙꢉꢃꢊꢝꢃ#ꢀꢈꢈꢇꢆꢁ&ꢉꢛꢜ)*ꢌ+
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To select the different current sinks to be controlled by the LED pattern generator, see the ‘xxxx’_mode registers
(where ‘xxxx’ stands for the to be controlled current sink, e.g. curr1_mode for CURR1 current sink). See also the
description of the different current sinks.
To allow the generator of a color patterns set the bit pattern_color to ‘1’. Then the pattern can be connected to CURRx
as follows:
Figure 16. LED Pattern Generator AS3676 for pattern_color = 1
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ꢆ ꢅ %
ꢉꢔ ꢆ ꢅ %
ꢎꢎꢎ
ꢉ & ꢔ
ꢊ ꢋ ꢍ
ꢉꢍ ꢉ & ꢔ
ꢊꢀ ꢊ ꢋ ꢍ
ꢎꢎꢎ
ꢎꢎꢎ
ꢐ
ꢆꢀꢀꢒ
ꢓꢔꢀꢀꢑꢒꢕꢖꢗꢙꢐꢐꢚꢛꢜꢝꢒ !"#ꢆ$
0ꢐꢕꢐꢒꢕꢐꢖꢑ(ꢚ ꢙ*ꢕ!ꢗꢕꢀꢒꢌꢆꢒꢌꢉꢒꢌꢎꢎꢎꢌꢔꢒꢌꢆꢋꢒꢌꢉꢅꢒꢌꢊꢉꢒꢌꢅꢀꢒꢌꢅꢔꢒꢌ&ꢋꢒ
/ꢙꢜꢕ)ꢚꢘꢛ!-ꢛꢙꢑꢑꢚ(
Only those current sinks will be controd, where the ‘xode register is configured for LED pattern.
If the register bit pattern_slow is set, all pattern times are increased by a factor of eight. (bit duration: 250ms if
pattern_color=0 / 800ms if pattern_color=1, delays between pattern up to 56s).
Soft Dimming for Pattern
The internal pattern generator can be comined with the internal pwm dimming modulator to obtain as shown in the fol-
lowing figure:
Figure 17. Soft dimming Architecre fr the AS3676 (softdim_pattern=1 and pattern_color = 1)
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ꢇꢏꢂ
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ꢗꢇꢅꢂꢄꢇꢕꢚꢌꢗꢏꢄꢄꢃꢅꢂꢌꢚꢇꢏꢄꢗꢃꢚꢌ'ꢇꢅ ꢇ(()ꢌ(ꢇꢄ
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ꢌꢗꢏꢄꢄ+,ꢊꢇꢐꢃꢌ-ꢌ./ꢈꢌꢎꢁꢂꢂꢃꢄꢅ
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AS3676
Datasheet - Detailed Description
With the AS3676 smooth fade-in and fade-out effects can be automatically generated.
As there is only one dimming ramp generator and one pwm modulator following constraints have to be considered
when setting up the pattern (applies only if pattern_color=1):
Figure 18. Soft dimming example Waveform for CURR30-32
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ꢎꢍꢋꢔꢎꢕꢕꢎꢉꢖꢋꢗꢌ
However using the identical dimming waveform for two chs is possible as shown in the following figure:
Figure 19. Soft dimming example Waveform for CURR30-3
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LED Pattern Registers
Table 50. Pattern data0...Pattern data3 Registers
Pattern data0, Pattern data1, Pattern data2, Pattern data3
Addr: 19h,1Ah,1Bh,1Ch
This registers contains the pattern data for the current sinks.
Bit
Bit Name
Default Access
Description
pattern_data[7:1
7:0
0
0
R/W
R/W
Pattern data0
7:0
Pattern data1
pattern_dta[158]
patterndata[23:16]
patten_data[31:24]
7:0
7:0
0
0
R/W
R/W
Pattern data2
Pattern data3
1. Update any f the pattern register only if none of the current sources is connected to the pattern generator
('xxxxode must not be 11b). The pattern generator is automatically started at the same time when any of the
currensources is connected to the pattern generator
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AS3676
Datasheet - Detailed Description
Table 51. Pattern control Register
Pattern control
Addr: 18h
This register controls the LED pattern
Description
Bit
Bit Name
Default Access
Defines the pattern type for the current sinks
0b
1b
single 32 bit pattern (also set currX_mode = 11)
pattern_color
0
0
R/W
R/W
R/W
RGB pattern with each 10 bits (set all
currX_mode = 11)
Delay between pattern, details (see Table 54); together wit
pattern_delay2 sets the delay time between pattern
pattern_delay
2:1
3
00b
0b
Enable the ‘soft’ dimming feature for the pattern genrato
Pattern generator directly control curret
softdim_pattern1
0
sources
1
‘Soft Dimming’ is performed (see page 37)
1. If softdim_pattern=1, don’t set curr30_mode, curr31_mode, cu32_mode or curr33_mode t11b.
Table 52. gpio current Register
Addr: 2Ch
Bit Name
gpio curt
Description
Bit
Default Access
Delay between pattrn (see Table 54 on page 39); together
with patternay sets the delay time between patterns
pattern_delay2
4
0
R/W
Pattern timing control
0b
1
normal mode
pattern_slow
6
R/W
slow mode (all pattern times are increased by a
factor of eight)
Table 53. Pattern End Register
Addr: 54h
Pattern End
Description
Bit
Bit Name
Defaut Access
pattern_end is toggled from 0 to 1 (or from 1 to 0) at each
end of the pattern just before restarting of the internal
pattern generator at the first bit of the pattern data
(can be used to synchronize the baseband software to the
pattern_end
0
0
R
pattern generator)1
1. pattern_end toggles whnever the AS3676 is in active mode (see Section 8.12 Operating Modes on page 80)
even if no pattrn dahas been setup.
Table 54. LEPattern timing
pattern_delay2 pattern_delay[1..0]
bit duration [ms]
pattern
duration [s]
(total cycle
time:
pattern +
delay)
delay[s]
between
patterns
pttern_slow
delay between patterns
pattern_color=0 pattern_color=1
01
1
0
0
0
0
00
01
31
31
100
100
1
2
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AS3676
Datasheet - Detailed Description
Table 54. LED Pattern timing
pattern_delay2 pattern_delay[1..0]
bit duration [ms]
pattern
duration [s]
(total cycle
time:
pattern +
delay)
delay[s]
between
patterns
pattern_slow
delay between patterns
pattern_color=0 pattern_color=1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
10
11
00
01
10
11
00
01
10
11
00
01
10
11
31
31
100
100
100
100
100
100
800
800
800
800
800
00
800
800
2
3
3
4
31
4
5
31
5
6
31
6
7
31
7
8
250
250
250
50
25
250
250
250
0
8
8
16
24
32
40
48
56
64
1
24
32
40
48
56
1. Even by setting 000 for pattern delay, theris small delay befre thnepatterns starts.
8.4.7 PWM Generator
The PWM generator can be used for aurrent sink. The settig applies for all current sinks, which are controlled by
the pwm generator (e.g. CURR1 is pwcontrolled if cuode = 10). The pwm modulated signal can switch on/off
the current sinks and therefore depending on its duty cyange the brightness of an attached LED.
Internal PWM Generator
The internal PWM generator uses the 2MHinternal clock as input frequency and its dimming range is 6 bits digital
(2MHz / 2^6 = 31.3kHz pwm frequency) and 2 its analog. Depending on the actual code in the register pwm_code the
following algorithm is used:
If pwm_code bit 7 = 1
Then the upper 6 bits (Bits 7:2) of wmcode are used for the 6 bits PWM generation, which controls the selected cur-
rents sinks directly
If pwm_code bit 7 =0 and bit 6 = 1
Then bits 6:1 of pwm_ode re used for the 6 bits PWM generation. This signal controls the selected current sinks, but
the analog current f thee sinks is divided by 2
If pwm_code bit 7 and bit 6 = 0
Then bits 5:0 opwm_code are used for the 6 bits PWM generation. This signal controls the selected current sinks, but
the anaurrent of these sinks is divided by 4
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AS3676
Datasheet - Detailed Description
Figure 20. PWM Control
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ꢄꢗꢘꢘꢇꢙꢓꢚꢉ ꢘꢇꢉꢆꢒ#ꢒꢆꢇꢆꢉꢑ$ꢉꢌ
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Automatic Up/Down Dimming
If the register pwm_dim_mode is set to 01 (up dimming) or 10 (down dimming) the value within the reister pwm_code
is increased (up dimming) or decreased (down dimming) every time and amount (either 1/4th or 1/8th) dined by the
register pwm_dim_speed. The maximum value of 255 (completely on) and the minimum value of 0 (o) is never
exceeded. It is used to smoothly and automatically dim the brightnes of the LEDs connecteo aof the current
sinks. The PWM code is readable all the time (also during up andowdimming).
The waveform for up dimming looks as follows (cycles omitted fosimplcity):
Figure 21. PWM Dimming Waveform for up dimming (pwm_ode = 01); cur_mode = PWM controlled (not
all steps shown)
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The internal pwm modulator circuit controls the currnt sinks as shown in the following figure:
Figure 22. PWM Control Circuit (currX_mode 10b (PWM controlled)); X = any current sink
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ꢐꢁꢚꢛ
AS3676
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ꢝꢆꢔꢒ
#ꢍꢎ
!&ꢙꢒꢓꢔꢌꢃ!ꢔꢌꢔꢂꢃꢍꢙ(ꢙꢉ)ꢙꢂꢈꢙ)ꢉ
The adder logic (available for all current sinks) is intended to allow dimming not only from 0% to 100% (or 100% to 0%)
of currX_current, but also e.g. from 10% to 110% (or 110% to 10%) of currX_current. The starting current for up dim-
ming is defined by 0 + currX_adder and the end current is defined by currX_current + currX_adder.
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Datasheet - Detailed Description
An overflow of the internal bus (8 Bits wide to the IDAC) has to be avoided by the register settings (currX_current +
currX_adder must not exceed 255).
If the register subX_en is set, the result from the pwm modulator is inverted logically. That means for up dimming the
starting current is defined by currX_adder - 1 and the end current is defined by currX_adder - currX_current - 1. An
overflow of the internal bus (8 Bits wide to the IDAC) has to be avoided by the register settings (currX_adder -
currX_current - 1 must not be below zero).
Its purpose is to dim one channel e.g. CURR30 from e.g. 110% to 10% of curr30_current and at the same time dim
another channel e.g. CURR31 from 20% to 120% of curr31_current.
Note: The adder logic operates independent of the currX_mode setting, but its main purpose is to work together wit
the pwm modulator (improved up/down dimming)
If the adder logic is not used anymore, set the bit currX_adder to 0. (Setting adder_currentX to 0 is not sufi-
cient)
At the end of up/down dimming, the pwm_code register keeps its final value (for up-dimming 255 and for own-
dimming 0). This can be used to identify the exact time, when up/down dimming is finished.
Table 55. PWM Dimming Table
Decrease by 1/4th
every step
Decrease by 1/8th
every step
Seconds
Seconds
ecods
Seconds
50mec/
Step
25mse/
Step
5msec/
Step
2.5msec/
Step
Step
%Dimming
PWM
%Dimming
PWM
1
100,0
75,3
56,5
42,4
31,8
23,9
18,0
13,7
10,6
8,2
255
192
144
108
81
61
46
35
27
21
16
12
9
100,0
87,8
76,9
67,
5,2
52,2
45,9
40,4
35,7
31,4
27
4,3
21,6
19,2
16,9
14,9
13,3
11,8
10,6
9,4
2
224
196
172
151
133
7
91
0,00s
0,05s
0,10s
0s
0,20s
0,25s
0,30s
0,35s
0,40s
0,45s
0,50s
0,55s
0,60s
0,65s
0,70s
0,75s
0,80s
0,85s
0,90s
0,95s
1,00s
1,05s
1,10s
1,15s
,00s
0,03s
0,05s
0,08s
0,10s
0,13s
0,15s
0,18s
0,20s
0,23s
0,25s
0,28s
0,30s
0,33s
0,35s
0,38s
0,40s
0,43s
0,45s
0,48s
0,50s
0,53s
0,55s
0,58s
0,000s
0,005s
0,010s
0,015s
0,020s
0,025s
0,030s
0,035s
0,040s
0,045s
0,050s
0,055s
0,060s
0,065s
0,070s
0,075s
0,080s
0,085s
0,090s
0,095s
0,100s
0,105s
0,110s
0,115s
0,000s
0,003s
0,005s
0,008s
0,010s
0,013s
0,015s
0,018s
0,020s
0,023s
0,025s
0,028s
0,030s
0,033s
0,035s
0,038s
0,040s
0,043s
0,045s
0,048s
0,050s
0,053s
0,055s
0,058s
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
22
23
24
80
6,3
70
4,7
62
3,5
55
2,7
7
49
2,4
6
43
2,0
5
38
1
4
34
12
3
30
0,8
2
27
0,4
1
24
0,0
0
8,2
21
7,5
19
6,7
17
5,9
15
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Datasheet - Detailed Description
Table 55. PWM Dimming Table
Decrease by 1/4th
every step
Decrease by 1/8th
every step
Seconds
Seconds
Seconds
Seconds
50msec/
Step
25msec/
Step
5msec/
Step
2.5msec/
Step
Step
%Dimming
PWM
%Dimming
PWM
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
5,5
5,1
4,7
4,3
3,9
3,5
3,1
2,7
2,4
2,0
1,6
1,2
0,8
0,4
0,0
14
13
12
11
10
9
1,20s
1,25s
1,30s
1,35s
1,40s
1,45s
1,50s
1,55s
1,60s
1,65s
1,0s
1,75s
1,80s
1,85s
1,9
0,60s
0,63s
0,65s
0,68s
0,70s
0,73s
0,75s
0,78s
0,80s
0,83s
0,85s
0,88s
,90s
0,93s
0,95s
0,120s
0,125s
0,130s
0,135s
0,140s
0,145s
0,150s
0,55s
0160s
0,16s
0,170s
0,175s
0,180s
0,185s
0,190s
0,060s
0,063s
0,065s
0,068s
0,07s
0,073s
0,075s
0,078s
0,080s
0,083s
0,085s
0,088s
0,090s
0,093s
0,095s
8
7
6
5
4
2
1
0
PWM Generator Registers
Table 56. Pwm control Register
Pwm control
Addr: 16h
is register controls PWM generator
Description
Bit
Bit Name
Default Aces
Selects the dimming mode
no dimming; actual content of register
pwm_code is used for pwm generator
00b
01b
logarithmic up dimming (codes are increased).
Start value is actual pwm_code
pwm_dim_moe
2:1
00b
R/W
logarithmic down dimming (codes are
decreased). Start value is actual pwm_code;
switch off the dimmed current source after
dimming is finished to avoid unnecessary
quiescent current
10b
11b
NA
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Table 56. Pwm control Register (Continued)
Pwm control
Addr: 16h
This register controls PWM generator
Description
Bit
Bit Name
Default Access
Defines dimming speed by increase/decrease pwm_code
by 1/4th every 50 msec (total dim time 1.0s)
000b
by 1/8th every 50 msec (total dim time 1.9s)
001b
by 1/4th every 25 msec (total dim time 0.5s)
010b
by 1/8th every 25 msec (total dim time 095s)
011b
pwm_dim_speed
5:3
000b
R/W
by 1/4th every 5 msec (total dim time 100ms)
100b
by 1/8th every 5 msec (total im tie 190ms)
101b
by 1/4th every 2.5 ms(totdim time 50ms)
110b
b1/8th every 2.5 msec (total dim time 95ms)
111
Table 57. pwm code Register
pwm code
This register conols the Pwm code.
Description
Addr: 17h
Bit
Bit Name
Default Access
Selects the PWM code
00h
...
0% duty cycle
....
pwm_code
7:0
00b
R/W
Fh
100% duty cycle
Table 58. Adder Current 1 Register
Adder Current 1
Addr: 30h
Ts register defines the current which can be added to CURR1, CURR30,
CURR41, RGB1
Bit
Bit Name
Default Access
Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h
....
0 (represents 0mA)
....
adder_curent1
7:0
00b
R/W
FFh
255 (represents 38.25mA)
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Table 59. Adder Current 2 Register
Adder Current 2
Addr: 31h
This register defines the current which can be added to CURR2, CURR31,
CURR42, RGB2
Bit
Bit Name
Default Access
Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h
....
0 (represents 0mA)
....
adder_current2
7:0
00b
R/W
FFh
255 (represents 38.25mA)
Table 60. Adder Current 3 Register
Adder Current 3
Addr: 32h
This register defines the current which can be added to CUR6, CURR32,
CURR43, RGB3
Bit
Bit Name
Default Access
Description
Selecthe aded current vaue – do not exceed together
with crrX_current the internal 8 Bit range (see text)
h
....
0 (represents 0mA)
....
adder_current3
7:0
00b
R/W
FFh
255 (represents 38.25mA)
Table 61. Adder Current 4 Register
Adder Current 4
This register defies the current which can be added to CURR33
Addr: 52h
Bit
Bit Name
efault Acces
Description
Selects the added current value – do not exceed together
with currX_current the internal 8 Bit range (see text)
00h
....
0 (represents 0mA)
....
adder_current4
7:0
00
R/W
FFh
255 (represents 38.25mA)
Table 62. Adder Enable 1 Register
Adder Enable 1
Enables the adder circuit for the selected current sources
Addr: 33h
Bit
Bit Nme
Default Access
Description
Enables adder circuit for current source RGB1
Normal Operation of the current source
0
1
rgb1_adder
0
0
0
R/W
R/W
adder_current1 gets added to the current
source current
Enables adder circuit for current source RGB2
Normal Operation of the current source
0
1
rgb2_adder
1
adder_current2 gets added to the current
source current
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Datasheet - Detailed Description
Table 62. Adder Enable 1 Register (Continued)
Adder Enable 1
Addr: 33h
Enables the adder circuit for the selected current sources
Bit
Bit Name
Default Access
Description
Enables adder circuit for current source RGB3
Normal Operation of the current source
0
1
rgb3_adder
2
0
0
0
0
R/W
R/W
R/W
R/W
adder_current3 gets added to the current
source current
Enables adder circuit for current source CURR41
0
Normal Operation of the current source
curr41_adder
curr42_adder
curr43_adder
3
4
5
adder_current1 gets added to the currnt
source current
1
Enables adder circuit for current surce CURR42
0
Normal Operation of the cuent source
adder_current2 getdded to the current
source curent
1
Enbles adder circuit for urret source CURR43
Normaperation of the current source
addercurre3 gets added to the current
source current
Table 63. Adder Enable 2 Register
Adder Enable 2
Addr: 34h
Enables the addecircuit for the selected current sources
Bit
Bit Name
fault Access
Description
Enables adder circuit for current source CURR1
Normal Operation of the current source
0
1
curr1_adder
0
0
0
0
0
0
/W
R/W
R/W
R/W
R/W
adder_current1 gets added to the current
source current
Enables adder circuit for current source CURR2
Normal Operation of the current source
0
1
curr2_adder
crr6adder
curr30_adder
curr31_adder
1
2
3
4
adder_current2 gets added to the current
source current
Enables adder circuit for current source CURR6
Normal Operation of the current source
0
1
adder_current3 gets added to the current
source current
Enables adder circuit for current source CURR30
0
Normal Operation of the current source
adder_current1 gets added to the current
source current
1
Enables adder circuit for current source CURR31
0
Normal Operation of the current source
adder_current2 gets added to the current
source current
1
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Datasheet - Detailed Description
Table 63. Adder Enable 2 Register (Continued)
Adder Enable 2
Addr: 34h
Enables the adder circuit for the selected current sources
Bit
Bit Name
Default Access
Description
Enables adder circuit for current source CURR32
0
Normal Operation of the current source
curr32_adder
5
0
0
R/W
R/W
adder_current3 gets added to the current
source current
1
Enables adder circuit for current source CURR33
0
Normal Operation of the current source
curr33_adder
6
adder_current4 gets added to the currnt
source current
1
Table 64. Subtract Enable Register
Subtract Enable
Addr: 35h
Enable the inveion fothe signal from the pwm generator
Bit
Bit Name
Default Access
Description
Inverts the sigl from the pwm generator
Drect peration (no inversion)
0
1
sub_en1
0
0
0
R/W
R/W
The snal from the pwm generator for which
he ader is enabled (curr1_adder = 1,
curr30_adder = 1, rgb1_adder = 1,
curr41_adder = 1) is inverted
Invets the signal from the pwm generator
Direct Operation (no inversion)
1
sub_en2
1
The signal from the pwm generator for which
the adder is enabled (curr2_adder = 1,
curr31_adder = 1, rgb2_adder = 1,
curr42_adder = 1) is inverted
Inverts the signal from the pwm generator
Direct Operation (no inversion)
0
1
sub_en3
suben4
2
3
0
R/W
R/W
The signal from the pwm generator for which
the adder is enabled (curr6_adder = 1,
curr32_adder = 1, rgb3_adder = 1,
curr43_adder = 1) is inverted
Inverts the signal from the pwm generator
Direct Operation (no inversion)
0
1
The signal from the pwm generator for which
the adder is enabled (curr33_adder = 1)
is inverted
8.4.8 LS - Ambient Light Sensing
The ADC converts every 1ms the ambient light sensor signal from pin GPIO2/LIGHT5. This signal is pre-processed
with a ffset defined by amb_offset and a gain defined by amb_gain (1/4, 1/2, 1, 2). Then it is low-pass filtered with a
programmable cut-off frequency going from 0.25Hz to 32Hz. Increasing signals and decreasing signal can have indi-
vidual cut-off frequencies adjustable from 0.25Hz to 32Hz (amb_filter_up and amb_filter_down). When setting
amb_on=1, this filter is pre-loaded with the initial value from the ADC to startup the filter at a defined condition.
5. adc_select=0 (select GPIO2/LIGHT input)
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This filtered signal can be readout from the register amb_result<7:0>.
Each of the available three channels (N=1, 2 or 3) has six 8-bit registers:
- groupN_y0: define current multiplier for values below groupN_X1
- groupN_y3: define current multiplier for high values (actual starting point defined by groupN_x1,groupN_k1 and
groupN_x2,groupN_k2)
- groupN_x1, groupN_k1: If ADC reading is > groupN_x1 then groupN_k1 divided by 32 defines the slope of the
first ramp
- groupN_x2, groupN_k2: If ADC reading is > groupN_x2 then groupN_k2 divided by 32 defines the slope of the
second ramp
Each current sources has a 2 bit register (currX_amb_group) to select None, Group1, Group2 or Group3 of ambient
light sensing.
The calculations are done every 1ms resulting in a flicker-free 1000Hz update rate of the current sources.
Note: A current source should not use adder or subtractor current at the same time together with ALS (e.g.
curr1_adder=1 and curr1_amb_group=01, 10 or 11). For details see austriamicrosystems application note
AN3676_ALS_with_adder_current.
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AS3676
Datasheet - Detailed Description
Figure 23. Ambient Light Sensor internal circuit
AS3676
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Ambient Light Sensor Registrs
Table 65. ALS control Reister
ALS control
Addr90h
control ambient light sensing
Bit
Bit Name
Default Access
Description
Enables the ambient light sensing feature
ambient light sensor disabled
amb_on
0
0
R/W
0
1
ambient light sensor enabled
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Table 65. ALS control Register (Continued)
ALS control
Addr: 90h
control ambient light sensing
Description
Bit
Bit Name
Default Access
Control Ambient Light Sensor preprocessing gain
00
gain = 1/4
gain = 1/2
gain = 1
amb_gain
2:1
0
R/W
01
10
11
gain = 2
Table 66. ALS filter Register
ALS filter
Addr: 91h
control for ambient light sensor filtering
Description
Bit
Bit Name
Default Access
Corols tfilter cut off (-3dB) freuency (increasing)
000
1
010
011
100
101
110
11
0.2Hz
0.5Hz
1Hz
amb_filter_up
2:0
000
R/W
2Hz
4Hz
8Hz
16Hz
32Hz
ontrols the filter cut off (-3dB) frequency (decreasing)
000
001
010
011
100
101
110
111
0.25Hz
0.5Hz
1Hz
amb_filter_down
6:4
0
R/W
2Hz
4Hz
8Hz
16Hz
32Hz
Table 67. ALS offsRegister
Addr92h
ALS offset
Description
Bit
Bit Name
Default Access
00h R/W
amb_offset
7:0
Controls the offset of the ambient light sensor
Table 68. ALS result Register
Addr: 93h
ALS result
Description
Bit
Bit Name
Default Access
00h R/W
amb_result
7:0
Filtered result of the ambient light sensor value
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Datasheet - Detailed Description
Table 69. ALS curr12 group Register
ALS curr12 group
Addr: 94h
controls the group mapping for CURR1 and CURR2
Bit
Bit Name
Default Access
Description
CURR1 is mapped to ambient light sensor group
00
None - no ambient light sensor control
curr1_amb_group
1:0
00
00
R/W
R/W
01
10
11
Group 1
Group 2
Group 3
CURR2 is mapped to ambient light sensor grou
00
None - no ambient light sensor contr
curr2_amb_group
3:2
01
10
11
Group 1
Group 2
Grp 3
Table 70. ALS rgb group Register
ALS rgb group
controls the grup mapping for RGB1, GB2, RGB3 and CURR6
Addr: 95h
Bit
Bit Name
Default Access
Description
RGB1 apped to ambient light sensor group
00
None - no ambient light sensor control
rgb1_amb_group
1:0
0
00
00
00
R/W
R/W
R/W
R/W
01
1
11
Group 1
Group 2
Group 3
RGB2 is mapped to ambient light sensor group
00
None - no ambient light sensor control
rgb2_amb_group
rgb3_ambgroup
curr6_amb_group
3:2
5:4
:6
01
10
11
Group 1
Group 2
Group 3
RGB3 is mapped to ambient light sensor group
00
None - no ambient light sensor control
01
10
11
Group 1
Group 2
Group 3
CURR6 is mapped to ambient light sensor group
00
None - no ambient light sensor control
01
10
11
Group 1
Group 2
Group 3
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Table 71. ALS curr3x group Register
ALS curr3x group
Addr: 96h
controls the group mapping for CURR30, CURR31, CURR32 and CURR33
Bit
Bit Name
Default Access
Description
CURR30 is mapped to ambient light sensor group
00
None - no ambient light sensor control
curr30_amb_group
1:0
00
00
00
00
R/W
R/W
R/W
R/W
01
10
11
Group 1
Group 2
Group 3
CURR31 is mapped to ambient light sensor grop
00
None - no ambient light sensor contr
curr31_amb_group
curr32_amb_group
curr33_amb_group
3:2
5:4
7:6
01
10
11
Group 1
Group 2
Grp 3
CRR32 mapped to ambient light sensor group
00
None - no ambient ight sensor control
1
10
11
Group 1
Group 2
Group 3
CURR3mapped to ambient light sensor group
00
None - no ambient light sensor control
1
10
11
Group 1
Group 2
Group 3
Table 72. ALS curr4x group Register
ALS curr4x group
controls the group mapping for CURR41, CURR42 and CURR43
Addr: 97h
Bit
Bit Name
Deault Access
Description
CURR41 is mapped to ambient light sensor group
00
None - no ambient light sensor control
curr41_am_group
1:0
00
00
R/W
R/W
01
10
11
Group 1
Group 2
Group 3
CURR42 is mapped to ambient light sensor group
00
None - no ambient light sensor control
curr42_amb_group
:2
01
10
11
Group 1
Group 2
Group 3
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Datasheet - Detailed Description
Table 72. ALS curr4x group Register (Continued)
ALS curr4x group
controls the group mapping for CURR41, CURR42 and CURR43
Addr: 97h
Bit
Bit Name
Default Access
Description
CURR43 is mapped to ambient light sensor group
00
None - no ambient light sensor control
curr43_amb_group
5:4
00
R/W
01
10
11
Group 1
Group 2
Group 3
Group1
Table 73. ALS group 1 Y0 Register
Addr: 98h
ALS group 1 Y0
Bit
Bit Name
Default Access
00h R/W
Description
group1_y0
7:0
Goup 1 y0 value - divideby 256
Table 74. ALS group 1 Y3 Register
Addr: 99h
ALS group 1 Y3
Bit
Bit Name
Default Access
00h RW
escription
group1_y3
7:0
Gup 1 y3 value - divided by 256
Table 75. ALS group 1 X1 Register
Addr: 9Ah
ALS group 1 X1
Description
Bit
Bit Name
ault Access
00h R/W
group1_x1
7:0
Group 1 x1 value
Table 76. ALS group 1 K1 Register
Addr: 9Bh
ALS group 1 K1
Description
Bit
Bit Name
Deult Access
R/W
group1_k1
7:0
Group 1 k1 value - divided by 32 defines first slope
Table 77. ALS group 1 X2 Rester
Addr: 9Ch
ALS group 1 X2
Description
Bit
Bit Name
Default Access
00h R/W
roup_x2
7:0
Group 1 x2 value
Table 78. ALgrop 1 K2 Register
Addr: 9Dh
ALS group 1 K2
Description
Bit
Bit Name
Default Access
00h
group1_k2
7:
R/W Group 1 k2 value- value divided by 32 defines second slope
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Datasheet - Detailed Description
Group2
Table 79. ALS group 2 Y0 Register
Addr: 9Eh
ALS group 2 Y0
Description
Bit
Bit Name
Default Access
00h R/W
group2_y0
7:0
Group 2 y0 value - divided by 256
Table 80. ALS group 2 Y3 Register
Addr: 9Fh
ALS group 2 Y3
Bit
Bit Name
Default Access
00h R/W
Description
group2_y3
7:0
Group 2 y3 value - divided by 256
Table 81. ALS group 2 X1 Register
Addr: A0h
ALS group 2 X1
Description
Bit
Bit Name
Default Access
00h R/W
group2_x1
7:0
Group 2 x1 vale
Table 82. ALS group 2 K1 Register
Addr: A1h
ALS group K1
Bit
Bit Name
Default Access
00h R/W
Desription
group2_k1
7:0
Group 2 k1 vale - divided by 32 defines first slope
Table 83. ALS group 2 X2 Register
Addr: A2h
LS group 2 X2
Description
Bit
Bit Name
efault Access
00h R/W
group2_x2
7:0
Group 2 x2 value
Table 84. ALS group 2 K2 Register
Addr: A3h
ALS group 2 K2
Description
Bit
Bit Name
DefaulAccess
group2_k2
7:0
0
R/W Group 2 k2 value- value divided by 32 defines second slope
Group3
Table 85. ALS group 3 Y0 Rgistr
Addr: A4h
ALS group 3 Y0
Bit
Bit Nme
Default Access
00h R/W
Description
group3_y0
7:0
Group 3 y0 value - divided by 256
Table 86LS group 3 Y3 Register
Addr: A5h
ALS group 3 Y3
B
Bit Name
Default Access
00h R/W
Description
group3_y3
7:0
Group 3 y3 value - divided by 256
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Datasheet - Detailed Description
Table 87. ALS group 3 X1 Register
Addr: A6h
ALS group 3 X1
Description
Group 3 x1 value
Bit
Bit Name
Default Access
00h R/W
group3_x1
7:0
Table 88. ALS group 3 K1 Register
Addr: A7h
ALS group 3 K1
Bit
Bit Name
Default Access
00h R/W
Description
group3_k1
7:0
Group 3 k1 value - divided by 32 defines first slope
Table 89. ALS group 3 X2 Register
Addr: A8h
ALS group 3 X2
Description
Bit
Bit Name
Default Access
00h R/W
group3_x2
7:0
Group 3 x2 value
Table 90. ALS group 3 K2 Register
Addr: A9h
AS group 3 K2
Description
Bit
Bit Name
Default Access
00h
group3_k2
7:0
R/W Gup 3 k2 value- value diided by 32 defines second slope
8.4.9 DLS - Dynamic Luminance Scaling Input
The pin GPIO1/DLS can be used for dynamic backlight scaling input. Damic backlight scaling is used to reduce the
power of the backlight especially when showng drk picture contes on he display. The control unit to operate DLS
is the display processor sending a PWM gnato the AS3676 and in arallel changing the display content to compen-
sate for a reduced brightness backlight.
Table 91. DLS Input Parameters
Symbol
Parameter
dition
Min
Typ
Max
Unit
pin GPIO1/DLS if used for DLS (any bit set
in registeDLS mode control1 or DLS mode
control2)
DLS input frequency
range
fDLS
25
1000
kHz
Note: If the input signal from the PWM (. for DLS) is '0', the voltage on the current sink is captured with a S/H.
Do not enable DLS operation usihe DCDC step up converter if the input GPIO1/DLS is continuously at 0.
When this feature is enabled, the urret sink current is disabled when the pin GPIO1/DLS is at 0. If GPIO1/DLS=1,
the current sink operates at its ogrammed current as shown in Figure 24:
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AS3676
Datasheet - Detailed Description
Figure 24. DLS (Dynamic Luminance Scaling) internal circuit shown for a single current sink
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Table 92. DLS mode control1 Register
DLS mode control1
Addr: 56h
Setup which ct snks are conned to the DLS; if set to '1' the
correspond cent source (sink) is combined with the DLS input
Bit
Bit Name
Default Access
escription
0
1
0
0
1
0
1
0
1
0
1
0
1
CR30 current sink is not combined with DLS
URR30 current sink is combined with DLS
URR31 current sink is not combined with DLS
CURR31 current sink is combined with DLS
CURR32 current sink is not combined with DLS
CURR32 current sink is combined with DLS
CURR33 current sink is not combined with DLS
CURR33 current sink is combined with DLS
RGB1 current sink is not combined with DLS
RGB1 current sink is combined with DLS
RGB2 current sink is not combined with DLS
RGB2 current sink is combined with DLS
RGB3 current sink is not combined with DLS
RGB3 current sink is combined with DLS
curr30_on_dls
curr31_on_dls
curr32_on_dls
curr33_on_dls
rgb1_on_dls
rgb2_on_dls
rgb_on_dls
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
2
3
4
5
6
Table 93. DLmode control2 Register
DLS mode control2
Addr: 57h
Setup which current sinks are connected to the DLS; if set to '1' the
correspond current source (sink) is combined with the DLS input
Bit
Bit Name
Default Access
Description
0
1
CURR1 current sink is not combined with DLS
CURR1 current sink is combined with DLS
curr1_on_dls
0
0
R/W
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Datasheet - Detailed Description
Table 93. DLS mode control2 Register (Continued)
DLS mode control2
Addr: 57h
Setup which current sinks are connected to the DLS; if set to '1' the
correspond current source (sink) is combined with the DLS input
Bit
Bit Name
Default Access
Description
0
1
0
1
0
1
0
1
0
1
CURR2 current sink is not combined with DLS
CURR2 current sink is combined with DLS
CURR41 current sink is not combined with DLS
CURR41 current sink is combined with DLS
CURR42 current sink is not combined with DL
CURR42 current sink is combined with LS
CURR43 current sink is not cobined with DLS
CURR43 current sink is cobinewith DLS
CURR6 current sink inot ombined with DLS
URR6 current sink is ombined with DLS
curr2_on_dls
1
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
curr41_on_dls
curr42_on_dls
curr43_on_dls
curr6_on_dls
2
3
4
7
8.5
General Purpose Input / Output
The GPIOs are a highly-configurable general purpose inputput pins which can e used for the following functional-
ity:
Digital Schmitt Trigger Input
Digital Output with 4mA Driving Capability at 28V Supply (VANA)
Tristate Output
Analog Input to the ADC
Default Mode for GPIO1/DLS, GPIO2/IGHT and VANA/GPI iInput (Pull-Down)
Table 94. GPIO Pin Function Summa
GPIO Pin
Configuration
Additional Function
Digital Input, Totem-Pole Output (Push/Pull),
Open Drain (PMOS or NOS), High-Z, Pull-
Down oPull-Up Resistor
ADC Input, PWM Input, DLS input (see page
55)
GPIO1/DLS
Digital Input, Totem-Pole Output (Push/Pull),
Open Drain (PMor NMOS), High-Z, Pull-
Down Pull-Up Resistor
ADC Input, ALS - light sensor input (see page
47)
GPIO2/LIGHT
VANA/GPI
Digital Input1
ADC Input, LDO output
1. As VANA/GPI is used as a ower supply for GPIO1/DLS, GPIO2/LIGHT, it is not recommended to use it as a
digital input.
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AS3676
Datasheet - Detailed Description
Figure 25. GPIOs and VANA/GPI Blockdiagram
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8.5.1 Unused GPIO Pins
If the pins GPIO1/DLS or GPIO2/LIGHT are not used, they can be left open (an internal pulldown, which is enabled by
default, will pull them to GND).
8.5.2 GPIO Characteristics
Table 95. GPIO DC Characteristics
Symbol
Rpull
Parameter
Condition
Min
30
Typ
Max
75
Unit
k
V
Pull up/Puldow
Resistanc
enabled by gpio1_pulls and
gpio2_pulls
VGPIO
Supy Volage
=VANA/GPI
1.8
3.35
55% of
VANA/
GPI
High Level Input
Voltage
VIH
VI
V
V
V
pins GPIO1/DLS and GPIO2/
LIGHT
28% of
VANA/
GPI
Low Level Input
Voltage
5% of
VANA/
GPI
VHYS
Hysteresis
ILEAK
VOH
Input Leakage Current To V2_5 or VANA/GPI and VSS
-5
5
µA
V
High Level Output
at Iout
0.8·VANA
/GPI
Voltage
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Datasheet - Detailed Description
Table 95. GPIO DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Unit
0.2·
VANA/
GPI
Low Level Output
Voltage
VOL
at Iout
V
VANA/GPI = 2.8V,
gpio1_low_curr or
gpio2_low_curr= 1
4
IOUT
Driving Capability
Capacitive Load
mA
pF
VANA/GPI = 2.8V,
gpio1_low_curr or
gpio2_low_curr = 0
16
CLOAD
50
8.5.3 GPIO Registers
Table 96. GPIO output 1 Register
GPIO output 1
Addr: 05h
This register controls GPIO outps.
Bit
Bit Name
Default Access
Description
Enables the CURR1 input
input disabled
gpi_curr1_en
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
input enabled
Enbles the CURR2 input
input disabled
gpi_curr2_en
gpi_curr6_en
gpi_en
1
2
3
4
5
6
7
0
1
input enabled
Enables the CURR6 input
input disabled
0
1
input enabled
Enables the VANA/GPI input
input disabled
0
1
input enabled
Enables the CURR30 input
input disabled
gpi_curr30_en
gpi_crr31en
gpi_curr32_en
gpi_curr33_en
0
1
input enabled
Enables the CURR31 input
input disabled
0
1
input enabled
Enables the CURR32 input
input disabled
0
1
input enabled
Enables the CURR33 input
input disabled
0
1
input enabled
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Datasheet - Detailed Description
Table 97. GPIO signal 1 Register
GPIO signal 1
Addr: 06h
This register controls GPIO outputs.
Bit
0
Bit Name
gpi_curr1_in
gpi_curr2_in
gpi_curr6_in
gpi_in
Default Access
Description
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
R
R
R
R
R
R
R
R
Reads a logic signal from pin CURR1; if gpi_curr1_en=1
Reads a logic signal from pin CURR2; if gpi_curr2_en=1
Reads a logic signal from pin CURR6; if gpi_curr6_en=1
Reads a logic signal from pin CURR6; if gpi_en=1
Reads a logic signal from pin CURR30; if gpi_curr30_e=
Reads a logic signal from pin CURR31; if gpi_curr31en=
Reads a logic signal from pin CURR32; if gpi_curr32_n=1
Reads a logic signal from pin CURR33; if gp_curr33_en=1
1
2
3
gpi_curr30_in
gpi_curr31_in
gpi_curr32_in
gpi_curr33_in
4
5
6
7
Table 98. GPIO output 2 Register
GIO output 2
This rgistr controls GPIO upus.
Description
Addr: 50h
Bit
Bit Name
Default Access
Wtes a logic signal to pin PIO1/DLS; this is independent
of any other bit settg e.g., gpio1_mode Table 100.
gpio1_out
0
0
0
R/W
R/W
Writes a logic signal o pin GPIO1/DLS; this is independent
of any obit setting e.g., gpio2_mode Table 100
gpio2_out
1
2
Enables the RGB1 input
gpi_rgb1_en
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
0
1
input disabled
input enabled
Enables the RGB2 input
input disabled
gpi_rgb2_en
gpi_rgb3_en
3
4
5
6
0
1
input enabled
Enables the RGB3 input
input disabled
0
1
input enabled
Enables the CURR41 input
input disabled
gpi_curr1_n
gpi_curr42_en
gpi_curr43_en
0
1
input enabled
Enables the CURR42 input
input disabled
0
1
input enabled
Enables the CURR43 input
input disabled
0
1
input enabled
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Datasheet - Detailed Description
Table 99. GPIO signal 2 Register
GPIO signal 2
This register controls GPIO outputs.
Description
Addr: 51h
Bit
Bit Name
Default Access
Reads a logic signal from pin GPIO1/DLS; this is
independent of any other setting e.g.,Table 100 except
gpio1_pulls=11
gpio1_in
0
N/A
N/A
R
R
Reads a logic signal from pin GPIO2/LIGHT; this is
independent of any other setting e.g.,Table 100 except
gpio2_pulls=11
gpio2_ in
1
gpi_rgb1_in
gpi_rgb2_in
gpi_rgb3_in
gpi_curr41_in
gpi_curr42_in
gpi_curr43_in
2
3
4
5
6
7
N/A
N/A
N/A
N/A
N/A
N/A
R
R
R
R
R
R
Reads a logic signal from pin RGB1; if gpi_rgb1_en=1
Reads a logic signal from pin RGB2; if gpi_rgb2_e=1
Reads a logic signal from pin RGB3; if gpi_rgb3_en=1
Reads a logic signal from pin CURR41; f gpicurr41_en=1
Reads a logic signal from pin CURR42if g_curr42_en=1
Reads a logisignal from pin CURR3; if gpi_curr43_en=1
Table 100. GPIO control Register
GPIO cool
Addr: 1Eh
This regier controls GPIO nd GPIO1 pin functions.
Bit
Bit Name
Default Access
Description
Des the direction for pin GPIO1/DLS
Input only
00
01
Output (push and pull)
gpio1_mode
1:0
00
01
00
R/W
R/W
R/W
Output (open drain, only push; only NMOS is
active)
10
11
Output (open drain, only pull; only PMOS is
active)
Adds the following pullup/pulldown to pin GPIO1/DLS; this
is independent of setting of bits gpio1_mode
00
01
10
None
Pulldown
Pullup
gpio1_pulls
3:2
ADC input (gpio1_mode = XX); recommended
for analog signals
11
Defines the direction for pin GPIO2/LIGHT
Input only
00
01
Output (push and pull)
gpio2_mode
5:4
Output (open drain, only push; only NMOS is
active)
10
11
Output (open drain, only pull; only PMOS is
active)
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Datasheet - Detailed Description
Table 100. GPIO control Register (Continued)
GPIO control
Addr: 1Eh
This register controls GPIO and GPIO1 pin functions.
Bit
Bit Name
Default Access
Description
Adds the following pullup/pulldown to pin GPIO2/LIGHT;
this is independent of setting of bits gpio2_mode
00
01
10
None
Pulldown
Pullup
gpio2_pulls
7:6
01
R/W
ADC input (gpio2_mode = XX); recommende
for analog signals
11
Table 101. GPIO driving cap Register
GPIO driving cap
Addr: 20h
This register enables low current mode or GIOs.
Bit
Bit Name
Default Access
Description
Denethe driving capaility f pin GPIO1/DLS
gpio1_low_curr
0
0
0
R/W
R/W
1
Iout
Iout /4
Defines the dring capability of pin GPIO2/LIGHT
gpio2_low_curr
1
0
1
Iout
Iout /4
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AS3676
Datasheet - Detailed Description
8.6
LED Test
Figure 26. LED Function Testing
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AS3676
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The AS3676 supports the verification of the funtionality of all the conned LEDs (open and shorted LEDs can be
detected). This feature is especially useful in prodction test to vethe correct assembly of the LEDs, all its connec-
tors and cables. It can also be used in thfield o verify if any of the LDs is damaged. A damaged LED can then be
disabled (to avoid unnecessary currens).
The current sources, charge pump, dcconverter and thnteral ADC are used to verify the forward voltage of the
LEDs. If this forward voltage is within the specified limitLEDs, the external circuitry is assumed to operate.
8.6.1 Function Testing for single LEDs conncted to the Charge Pump
For any current source connected to the carge pump (CURR30-33) where only one LED is connected between the
charge pump and the current sink (see Figur1) use:
Table 102. Function Testing for LEDs oncted to the Charge Pump
Step
Action
Example Code
Switch on the chrge ump and set it into manual
1:2 mode (to avod automatic mode switching
duing measurements)
Reg 23h 14h (cp_mode = 1:2, manual)
Reg 00h 04h (cp_on = 1)
1
e.g. for register CURR31set to 9mA use
Reg 10h 0Fh (curr3x_other = 9mA)
2
3
Swih on he current sink for the LED to be tested
Mesure with the ADC the voltage on CPOUT
Reg 03h 0ch (curr31_mode = curr31_other)
Reg 26h 95h (adc_select=CPOUT,start ADC)
Fetch the ADC result from Reg 27h and 28h
Measure with the ADC the voltage on the switched
on current sink
Reg 26h 8bh (adc_select=CURR31,start ADC)
4
Fetch the ADC result from Reg 27h and 28h
Switch off the current sink for the LED to be tested
Reg 03h 00h (curr31_mode = off)
Compare the difference between the ADC
measurements (which is the actual voltage across
the tested LED) against the specification limits of
the tested LED
6
Calculation performed in baseband uProcessor
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Datasheet - Detailed Description
Table 102. Function Testing for LEDs connected to the Charge Pump
Step
Action
Example Code
Do the same procedure for the next LED starting
from point 2
7
Jump to 2. If not all the LEDs have been tested
Switch off the charge pump
set charge pump automatic mode
Reg 00h 00h (cp_on = 0)
Reg 23h 00h
8
8.6.2 Function Testing for LEDs connected to the Step Up DCDC Converter
For LEDs connected to the DCDC converter (usually current sinks CURR1,CURR2 and CURR6) use the following pr-
cedure:
Table 103. Function Testing for LEDs connected to the DCDC converter
Step
Action
Example Code
e.g. Test LEDs on CURR1:
Reg 01h 01h (curr1_moe=on)
Reg 09h 3ch (curr1_curnt = 9mA)
Switch on the current sink for the LED string to be
tested (CURR1,2 or 6)
1
Select the feedback path for the LED string to be
tested (e.g. step_up_fb = 01 for LED string on
CURR1)
2
3
Reg 21h 02h (st_up_b=curr1)
Set the current for step_up_vtuning exactly above
the maximum forward voltage of the tested
string + 0.6V (for the current sink) + 0.25V; ad
margin (accuracy of step_up_vtuning); this sethe
maximum output voltage limit for the DCDC
converter
e.g. 4 LEDs with UfMAX = 41V gives 17.25V +6% =
18.29V; if R=1M and R3 = open, then select
step_up_vtuni= 18 (Reg 21h 92h; results in
19.25V over voltagprotection voltage – Table 9 on
page 14)
4
5
6
Set step_up_prot = 1
Reg 22h 04h
Reg 00h 08h
Switch on the DCDC onvrter
Wait 80ms (DCDC_Fsetting time)
Reg 26h 96h (adc_select=DCDC_FB, start ADC;
7
8
9
Measure the voltage DCDC_FB (ADC)
Fetch the ADC result from Reg 27h and 28h)
If the voltage on DCDC_FB is above 1.0
tested LED string is broken – then skip the following
steps
(Code >199h)
Switch off the over voltae protection
(step_up_prot=0
Reg 22h 00h
Reduce step_up_vtuning sby step until the
measured voltage on DCDFB (ADC) is above
1.0V.
e.g.: Reg 21h 62h (step_up_vtuning=12): ADC
10
result=1,602V
After changing step_u_vuning always wait 80ms,
befoe AD-conversion
11
12
Masurvoltage on DCDC_FB
Switch off the DCDC converter
e.g. DCDC_FB=1.602V
Reg 00h 00h
The vltage on the LED string can be calculated
now as follows (R4 = open):
VLEDTRING = V(DCDC_FB) + I(step_up_vtuning) *
R2 – 0.5V (current sinks feedback voltage: VFB2).
V(DCDC_FB) = ADC Measurement from point 11
I(step_up_vtuning) = last setting used for point 10
13
1
e.g.: VLED = (1.602V + 12V – 0.5V) / 4 = 3.276V
Compare the calculated value against the
specification limits of the tested LEDs
Note: With the above described procedures electrically open and shorted LEDs can be automatically detected
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AS3676
Datasheet - Detailed Description
8.7
Analog-to-Digital Converter
The AS3676 has a built-in 10-bit successive approximation analog-to-digital converter (ADC). It is internally supplied
by V2_5, which is also the full-scale input range (0V defines the ADC zero-code). For input signals exceeding V2_5
(typ. 2.5V) a resistor divider with a gain of 0.4 (Ratioprescaler) is used to scale the input of the ADC converter. Conse-
quently the resolution is:
Table 104. ADC Input Ranges, Compliances and Resolution
Channels (Pins)
Input Range
VLSB
Note
DCDC_FB, GPIO1/DLS, GPIO2/
LIGHT, VANA/GPI, audio controlled
LED buffer output
0V-2.5V
2.44mV
VLSB=2.5/1024
ADCTEMP_CODE
-30°C to 125°C
0V-5.5V
1 / ADCTC
6.1mV
junction temperature
CURR3x, CURR4x, RGBx
VBAT, CPOUT
VLSB=(2.5/1024)/0.4; inteal
resistor divider used
CURR1, CURR2, CURR6
0V-1.0V
2.44mV
VLSB=2.51024
Table 105. ADC Parameters
Symbol
Parameter
Conditon
Min
Typ
Max
Unit
Resolution
10
Bit
see
Table
104
VIN
Input Voltage Range
VSU= V2_5
VSS
V
Differential Non-
Linearity
DNL
± 0.25
LSB
INL
Vos
Rin
Cin
Integral Non-Linearity
Input Offset Voltage
Input Impedance
± 0.5
LSB
LSB
M
pF
± 0.25
100
Input Capacitance
9
VSUPPLY
Power Supply Range
± 2%, nally trimmed.
Durig conversion only.
2.5
V
(V2_5)
Idd
Idd
Power Supply Current
Power Down Current
300
100
µ A
nA
Temperature Sensor
Accuracy
TTOL
ADCTOFFSET
ADCTC
@ 25 C
-10
+10
C
C
ADC temperatre
measurement oset
value
375
Code temprature
cofficient
1.293
9
C/
Code
Temperature change per ADC LSB
For all low voltage current sinks, CPOUT
and VBAT
RatioPRESCALE
R
atio f Prescaler
0.4
Transient Prameters (2.5V, 25 ºC)
Tc
fc
ts
Conversion Time
Clock Frequency
27
1.0
16
µs
MHz
µs
All signals are internally generated and
triggered by start_conversion
Settling Time of S&H
The junction temperature (TJUNCTION) can be calculated with the following formula (ADCTEMP_CODE is the adc conver-
sion result for channel 17h selected by register adc_select = 010111b):
TJUNCTION [C] = ADCTOFFSET - ADCTC · ADCTEMP_CODE
(EQ 5)
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Datasheet - Detailed Description
ADC Registers
Table 106. ADC_MSB result Register
ADC_MSB result
Addr: 27h
Together with Register 27h, this register contains the results (MSB) of an ADC
cycle.
Bit
Bit Name
Default Access
Description
ADC results register.
D9:D3
6:0
N/A
N/A
R
R
Indicates end of ADC conversion cycle
Result is ready
result_not_ready
7
0
1
Conversion is running
Table 107. ADC_LSB result Register
ADC_LSB result
Addr: 28h
Together with Register 28h, this register contains the resus (LB) of an ADC
cycle
Bit
Bit Name
Default Access
N/A
Description
D2:D0
2:0
R
ADC result regiter
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Datasheet - Detailed Description
Table 108. ADC_control Register
ADC_control
Addr: 26h
This register input source selection and initialization of ADC
Bit
Bit Name
Default Access
Description
Selects input source as ADC input
000000 (00h)
GPIO2/LIGHT
000001 (01h)
000010 (02h)
000011 (03h)
000100 (04h)
000101 (05h)
000110 (06h)
000111 (07h)
001000 (08h)
00100(09h)
1010(0Ah)
011 (0Bh)
00100 (0Ch)
001101 (0Dh)
001110 (0Eh
001111 (0F)
01000 (0h)
0001 (11h)
010 (12h)
010011 (13h)
010100 (14h)
010101 (15h)
010110 (16h)
010111 (17h)
VANA/GPI
GPIO1/DLS
audio controlled LED buffer output
reserved
RGB1
RGB
RGB3
CRR1
CURR2
CURR30
CURR31
adc_select1
5:0
03h
R/W
CURR32
CURR33
CURR41
CURR42
CURR43
reserved
reserved
CURR6
VBAT
CPOUT
DCDC_FB
ADCTEMP_CODE (junction temperature)
011xxx,
1xxxxx
reserved
NA
6
7
st_coversion
N/A
W
Writing a 1 into this bit starts one ADC conversion cycle.
1. See Table able 04 for ADC ranges and resolution.
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AS3676
Datasheet - Detailed Description
Figure 27. ADC Circuit
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AS3676
8.8
Audio controlled LEDs
Up to four RGB LEDs and/or up to 13 LEDs (number of LEDis fully configurab) can be controlled by an audio
source (connected to the pin CURR33, DCDC_FB or GPIO2/LIGHT). The cor of te RGB LED(s) or the brightness of
the single color LED(s) is depending on the input mplitde. For the RGLEDit starts from black transitions to blue,
green, cyan, yellow, red and for high amplitudewhite is used (internal okup table if audio_color=000b).
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AS3676
Datasheet - Detailed Description
Figure 28. Audio controlled LED internal circuit
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AS3676
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The audio controlled LED block is enabled if ny of the registers curr30_aud_src[1:0]...curr33_aud_src[1:0],
curr126_aud_on, rgbx_aud_on or curr4_d_on not equal zero.
The audio input amplifier (enabled by auuf_on=1) is used to allow the attenuation (or amplification of the input sig-
nal) and has the following parameers:
Table 109. Audio input Paramters
Symbol
VIN
Paamter
Condition
Min
Typ
Max
Unit
V
Input Volage Range
m. Input Impedance
0
2.5
Rin_min
at max. input gain (30dB)
20
k
The signal is onveted with the ADC (If the audio controlled LED is active, the internal ADC is continuously running. In
this case ADC cannot be used for any other purpose). The digital processing converts this signal into 3 channels
(c1, chch):
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Datasheet - Detailed Description
Figure 29. Audio controlled LED digital processing internal circuit
AS3676
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These three output channels (ch1, ch2, ch3) can be routed to any of the current sources according to Figure 28
The input amplitude is mapped into different colors (Look Up Table in Figure 29) for RGB LED(s) or bightness for sin-
gle color LED(s). The mapping is controlled by the register audio_color. If audio_color = 000, then te maping is done
as follows:
Very low amplitudes are mapped to black, for higher amplitudes, te color smoothly transitionrom lue, green, cyan,
yellow, red and eventually to white (for high input amplitudes).
8.8.1 AGC
The AGC is used to ‘compress’ the input signal and to attee very low input alitude signals (this is performed to
ensure no light output for low signals especially for noisy inpt signals).
The AGC monitors the input signal amplitude and filters this amplitude with filter with a short attack time, but a long
decay time (decay time depends on the register acct). This amplitudmeasrement (represented by an integer
value from 0 to 15) is then used to amplify or atnuate the input signath ne of the following amplification ratios
(output to input ratio) – the curve A, B, or C iseleted depending the register agc_ctrl:
Figure 30. AGC curve A (x-axis: input amptude, y-axis: outpt amlitude; actual value: gain between output to
input)
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Datasheet - Detailed Description
Figure 31. AGC curve B (x-axis: input amplitude, y-axis: output amplitude; actual value: gain between output to
input)
Figure 32. AGC curve C (x-axis: input amplitude, y-axis: output mpliue; actual value: gain beween output to
input)
8.8.2 Audio Controlled LED Regrs
Table 110. Audio Control Register
Audio Control
Addr: 46h
Audio Sync Mode control
Bit
Bit ame
Default Access
Description
Audio input buffer enable
off; for audio direct input to ADC use
adc_select = 00h (AUDIO_IN)
aud_buf_on
0
0b
R/W
R/W
0
1
on; set adc_select = 03h (buffer output)
audio controlled LED color selection (amplitude mode)
audio_color
4:2
000b
000
color scheme defined by lookup table
single color scheme (b2=R, b1=G, b0=B)
001-111
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Datasheet - Detailed Description
Table 110. Audio Control Register (Continued)
Audio Control
Addr: 46h
Audio Sync Mode control
Bit
Bit Name
Default Access
Description
Audio controlled LED persistence time (ramping down)
00
01
10
11
none
audio_speed_down
7:6
00b
R/W
200ms
400ms
800ms
Table 111. Audio input Register
Audio input
Addr: 47h
Audio Sync input control
Bit
Bit Name
Default Access
Description
Audio input buffer gain ontrol
000
1dB
-6dB
0
011
100
101
110
111
0dB
audio_gain
2:0
000b
R/W
+6dB
+12dB
+18dB
+24dB
+30dB
dio input buffer AGC function controls AGC switching
threshold
000
AGC off
Attenuate low amplitude signals otherwise linear
response (to remove e.g. noise)
001
010
011
100
101
110
111
AGC curve A; slow decay of amplitude detection
AGC curve A; fast decay of amplitude detection
AGC curve B; slow decay of amplitude detection
AGC curve B; fast decay of amplitude detection
AGC curve C; slow decay of amplitude detection
AGC curve C; fast decay of amplitude detection
agc_ctrl
5:3
b
R/W
Startup Control of audio input buffer (used to charge
optional external dc blocking capacitor)
audio_man_start1
audio_dis_start2
6
7
0b
0b
R/W
R/W
0
1
automatic precharging 300us (if audio_dis_start = 0)
continuously precharging (if aud_buf_on = 1)
Disable Startup Control of audio input buffer (used to
charge optional external dc blocking capacitor)
0
1
precharging enabled
precharging disabled
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Datasheet - Detailed Description
1. Its safe to keep default value
2. Its safe to keep default value
Table 112. Audio output Register
Audio output
Addr: 48h
Audio Sync input control
Bit
Bit Name
Default Access
Description
LED(s) output amplitude control (in percent of selected
output current)
000
001
010
011
100
10
110
6.25%
12.5%
25%
aud_amplitude
2:0
000b
R/W
50%
75%
87.5%
93.5%
100%
Adio controlled LED enabfor CURR1, CURR2, CURR6
curr126_aud_on
rgbx_aud_on
4
5
6
0b
0b
0b
R/W
R/W
R/W
0
1
off
on, audio controlled LED is enabled
Auio controlled LED enable for RGB1-RGB3
off
0
1
on, audio controlled LED is enabled
Audio controlled LED enable for CURR41-CURR43
curr4x_aud_on
0
1
off
on, audio controlled LED is enabled
Table 113. CURR3x audio source Registe
CURR3x audio source
Controls CURR30,31,32,33 audio outputs and enables audio controlled LED
Addr: 53h
Bit
Bit Name
Default Access
Description
Audio controlled LED source for CURR30
All other modes
00
01
ch1 connected to CURR30, audio controlled
LED on
curr0_aud_src[1:0]
1:0
00b
R/W
ch2 connected to CURR30, audio controlled
LED on
10
11
ch3 connected to CURR30, audio controlled
LED on
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Table 113. CURR3x audio source Register (Continued)
CURR3x audio source
Controls CURR30,31,32,33 audio outputs and enables audio controlled LED
Addr: 53h
Bit
Bit Name
Default Access
Description
Audio controlled LED source for CURR31
All other modes
00
01
ch1 connected to CURR31, audio controlled
LED on
curr31_aud_src[1:0]
3:2
00b
00b
0b
R/W
R/W
R/W
ch2 connected to CURR31, audio controlled
LED on
10
11
ch3 connected to CURR32, audio contrlled
LED on
Audio controlled LED source for CRR32
All other mods
00
01
ch1 connected to CURR32audio controlled
LED on
curr32_aud_src[1:0]
5:4
h2 connected tCURR32, audio controlled
LED on
10
11
ch3 conned to CURR32, audio controlled
LED on
Audio corolleLED source for CURR33
All other modes
00
01
c1 connected to CURR33, audio controlled
LED on
curr33_aud_src[1:0]
7:6
ch2 connected to CURR33, audio controlled
LED on
0
11
ch3 connected to CURR33, audio controlled
LED on
Table 114. Audio Control 2 Register
Audio Control 2
Addr: 55h
Audio Mode Control Register
Description
Bit
Bit Name
Default Access
0
NA
not used
Audio controlled LED filtering time (ramping up)
000
none
001
010
011
100
101
110
111
50ms
100ms
150ms
200ms
250ms
400ms
800ms
audio_speed_up
3:1
000b
R/W
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Datasheet - Detailed Description
Table 114. Audio Control 2 Register (Continued)
Audio Control 2
Audio Mode Control Register
Description
Addr: 55h
Bit
Bit Name
Default Access
Audio Buffer input source
00
01
10
11
CURR33
DCDC_FB
audio_source
5:4
00b
R/W
GPIO1/DLS
GPIO2/LIGHT
8.9
Power-On Reset
The internal reset is controlled by two sources:
VBAT Supply
Serial interface state (CLK, DATA)
The internal reset is forced if VBAT is low or if both interface pin(CLK, ATA) are low for more than tPOR_DEB (typ.
100ms)6. Then device enters shutdown mode. For details ee section Operating Modes on pge 80.
The reset levels control the state of all registers. As long as T and CLK/DATA e below their reset thresholds, the
register contents are set to default. Access by serial interfacis possible once the reethresholds are exceeded.
Figure 33. Zero Power Device Wakeup block diaram
AS3676
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Tble 115. Power On Reset Parameters
Smbol
Parameter
Condition
Min
Typ
Max
Unit
Overall Power-On
Reset
Monitor voltage on V2_5; power-on reset for
all internal functions.
2.41
VPOR_VBAT
1.8
2.15
V
6. Only if shutdwn_enab=1
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Datasheet - Detailed Description
Table 115. Power On Reset Parameters
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Reset Level for pins
CLK, DATA
VPOR_PERI
Monitor voltage on pins CLK, DATA
0.29
1.0
1.38
V
Reset debounce time
for pins CLK, DATA
tPOR_DEB
tstart
80
4
100
6
120
8
ms
ms
Interface Startup Time
1. Guaranteed by design - min./max. limits not production tested
8.9.1 Reset control register
Table 116. Reset and Overtemp control Register
Reset and Overtemp control
Addr: 29h
This register reads and resets the overtemperare flg.
Default Access Description
Bit
Bit Name
Eable Shutdown mode and seial interface reset.
Seial Interface reet disabled. Device does not
0
enter Shutown mode
shutdwn_enab
4
0
R/W
Serial Intace reset enabled, device enters
1
shutdown wen SCL and SDA remain low for
tPOR_DEB
8.10 Temperature Supervision
An integrated temperature sensor provides oer-tmperature protion or the AS3676. This sensor generates a flag
if the device temperature reaches the ovetemerature threshold of 10º. The threshold has a hysteresis to prevent
oscillation effects.
If the device temperature exceeds the threshold all current ources, the charge pump and the dcdc converter is
disabled and the ov_temp flag is set. Ater decreasing tperature by THYST operation is resumed.
The ov_temp flag can only be reset by first writing a 1 and then a 0 to the register bit rst_ov_temp.
Bit ov_temp_on = 1 activates temperature supervison (able 118). It is recommend to leave this bit set (default state).
Table 117. Overtemperature Detection
Symbol
T140
Parameter
Condition
Min
Typ
140
5
Max
Unit
ºC
ov_temp Rising
Threshold
THYST
ov_temp Hyeresis
ºC
Table 118. Reset and Ortemp control Register
Reset and Overtemp control
This register reads and resets the overtemperature flag.
Default Access Description
Addr29h
Bit
Bit Name
Activates/deactivates device temperature supervision.
Default: Off - all other bits are only valid if this bit is set to 1
Temperature supervision is disabled. No reset
ov_temp_on
0
1
W
0
1
will be generated if the device temperature
exceeds 140ºC
Temperature supervision is enabled
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Table 118. Reset and Overtemp control Register (Continued)
Reset and Overtemp control
This register reads and resets the overtemperature flag.
Addr: 29h
Bit
Bit Name
Default Access
Description
Indicates that the overtemperature threshold
has been reached; this flag is not cleared by an
overtemperature reset. It has to be cleared
using rst_ov_temp
ov_temp
1
N/A
0
R
1
The ov_temp flag is cleared by first setting this bit to 1, and
then setting this bit to 0.
rst_ov_temp
2
R/W
8.11 Serial Interface
The AS3676 is controlled using serial interface pins CLK and DATA:
Figure 34. Serial interface block diagram
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The clock line CLK is never held low by thAS3676 (as the AS366 does not use clock stretching of the bus).
Table 119. Serial Interface VoltageanTimings
Symbol
Parameter
dition
Min
Typ
Max
Unit
High Level Input
Voltage
VIHI/F
1.38
VBAT
V
Low Level Input
Voltage
VILI/F
0.0
0.52
V
Pins DATA and CLK
VHYSTI/F
tRISE
Hysteresis
Rise Time
0.1
V
0
0
1000
300
ns
ns
ns
ns
tFALL
Fall Time
tCLK_FILTER
tDATA_FILTER
Spike Filtr on LK
Spike Fier on DATA
100
300
The AS3676 is comatible to the NXP two wire specification http://www.nxp.com/acrobat_download/literature/9398/
39340011.pdfVersion 2.1, January 2000 for standard and fast mode (no high speed mode).
8.11.1 rial Interface Features
Fast ode Capability (Maximum Clock Frequency is 400 kHz)
-bit Addressing Mode
Write Formats
- Single-Byte Write
- Page-Write
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Read Formats
- Current-Address Read
- Random-Read
- Sequential-Read
DATA Input Delay and CLK spike filtering by integrated RC components
8.11.2 Device Address Selection
The serial interface address of the AS3676 has the following address:
80h – Write Commands
81h – Read Commands
Figure 35. Complete Serial Data Transfer
DATA
CLK
8
1-7
8
9
1-7
1-7
8
9
P
S
Stop
Condition
Start
Condition
Address R/W
ACK
Data
ACK
Data
ACK
Serial Data Transfer Formats
Definitions used in the serial data transfer omat dagrams are listein the following table:
Table 120. Serial Data Transfer Byte Defintions
Symbol
finition
Start Condition after Sto
Repeated Sta
R/W (AS3676 Slave)
Note
S
Sr
R
R
R
R
R
W
R
R
R
R
R
1 bit
1 bit
10000000b (80h).
10000001b (81h)
8 bits
DW
DR
Device Addess for Write
Device Addresfor Read
Word dress
WA
A
Acknowledge
1 bit
N
Not Acknowledge
1 bit
reg_data
data (n)
P
Register Data/Write
Register Data/read
Stop Condition
8 bits
1 bit
8 bits
WA+
Increment Word Address Internally
During Acknowledge
Figure 3Serial Interface Byte Write
S
DW
A
WA
A
reg_data
A P
Write Register
WA++
AS3675
AS3675
(= Slave) receives data
(= Slave) transmits data
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Figure 37. Serial Interface Page Write
n
S
DW
A
WA
A
reg_data 1
A
reg_data 2
A
…
reg_data
A P
Write Register
WA++
Write Register
WA++
Write Register
WA++
AS3675
AS3675
(= Slave) receives data
(= Slave) transmits data
Byte Write and Page Write formats are used to write data to the slave.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state
(the bus is free). The device-write address is followed by the word address. After the word address any number of data
bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data byteo
subsequent address locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either ith a
repeated START condition followed by the device-read address, or simply with a new transmission START followed by
the device-read address, when the bus is in IDLE state. The device-read address is always followed by he 1st register
byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be reafrothe slave.
The word address is incremented internally.
The following diagrams show the serial read formats supported by the S3676.
Figure 38. Serial Interface Random Read
S
DW
A
WA
A
S
DR
A
da
N P
Rd Reger
WA
AS3675
AS3675
(= slave) res ta
(= slave) transmits ata
Random Read and Sequential Read are ombed formats. The repeted START condition is used to change the
direction after the data transfer from the mater.
The word address transfer is initiated a START conditon isued by the master while the bus is idle. The START
condition is followed by the device-writaddress and thaddress.
In order to change the data direction a repeated START condition is issued on the 1st CLKpulse after the ACKNOWL-
EDGE bit of the word address transfer. After the reeptin of the device-read address, the slave becomes the transmit-
ter. In this state the slave transmits registedata located by the previous received word address vector. The master
responds to the data byte with a NOT ACKNWLEDGE, and issues a STOP condition on the bus.
Figure 39. Serial Interface Sequential Re
n
S
DW
A
WA
A
Sr
DR
A
data 1
A
data 2
...
A
data
N P
Read Register
WA++
AS3675
AS3675
(= sla) receives data
(slave) ansmits data
Sequential Read is the extended form of Random Read, as multiple register-data bytes are subsequently transferred.
In contrast to te Random Read, in a sequential read the transferred register-data bytes are responded by an acknowl-
edge frohe master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the
wrd-addess counter). To terminate the transmission the master has to send a NOT ACKNOWLEDGE following the
last ata byte and subsequently generate the STOP condition.
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Datasheet - Detailed Description
Figure 40. Serial Interface Current Address Read
n
S
DR
A
data 1
A
data 2
…
A
data
N P
Read Register
WA++
Read Register
WA++
Read Register
WA++
AS3675
(= slave) receives data
AS3675
(= slave) transmits data
To keep the access time as small as possible, this format allows a read access without the word address transfer in
advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read
address.
Analogous to Random Read, a single byte transfer is terminated with a NOT ACKNOWLEDGE after the 1st register
byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytemu
be responded to with an ACKNOWLEDGE from the master.
For termination of the transmission the master sends a NOT ACKNOWLEDGE following the last data byte and a sub-
sequent STOP condition.
8.12 Operating Modes
If the voltages on CLK and DATA is less than VPOR_PERI for > tPR_DEsee Table 115 on page 75), the AS3676 is in
shutdown mode and its current consumption is minimized (IBAT = SHUTDWN) and all internal registers are reset to their
default values.
If the voltage at CLK or DATA rises above VPOR_PERI, the A76 serial interfacenabled and the AS3676 and the
standby mode is selected. The AS3676 is switched automatally from standby mod(IBAT = ISTANBY) into normal
mode (IBAT = IACTIVE) and back, if one of the following blocks are activated:
Charge pump
Step up regulator
Any current sink
ADC conversion started
PWM active
Pattern mode active.
If any of these blocks are already switched on the internllator is running and a write instruction to the registers is
directly evaluated within 1 internal CLK cycle (typ. µs)
If all these blocks are disabled, a write instruction tenble these blocks is delayed by 64 CLK cycles (oscillator will
startup, within max 200µs).
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Datasheet - Detailed Description
The mode switching is shown in Figure 41:
Figure 41. Startup and Operating Mode Selection
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www.austriamicrosystems.com/AS3676
1v1-4
81 - 91
AS3676
Datasheet - Register Map
9 Register Map
Table 121. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
step_up
_on
cp_on
ldo_on
Reg. control
00h
00
curr2_mode
curr1_mode
rgb1_mode
curr12 control
curr rgb control
curr3 control1
curr4 control
01h 00h
02h 00h
03h 00h
04h 00h
curr6_mode
rgb3_mode
rgb2_mode
curr31_mode
curr42_mode
curr33_mode
curr32_mode
curr43_mode
curr30_mode
curr41_mode
gpi_curr
32_en
gpi_curr
30_en
gpi_curr
6_en
gpi_curr
1_en
gpi_curr
g_curr
gpi_curr
gpi_en
gpi_in
GPIO output 1
GPIO signal 1
05h 00h
06h 00h
31_en
2_n
33_en
gpi_curr
32_in
gpi_curr
30_in
gpi_curr
6_n
gpi_curr
1_in
gpi_curr
31_in
gpicurr
2_in
gpi_curr
33_in
ldo_voltag
LDO Voltage
Curr1 current
Curr2 current
Rgb1 current
Rgb2 current
Rgb3 current
Curr3x strobe
Curr3x preview
Curr3x other
07h 00h
09h 00h
0Ah 00h
0Bh 00h
0Ch 00h
0Dh 00h
0Eh 00h
0Fh 00h
10h 00h
curr1_current
curr2_curre
rgb1_currnt
rgb2_crrent
r_current
curr3x_strobe
curr3x_preview
curr3x_other
Curr3 strobe
control
strobe_t
strobe_mode
strobe_ctrl
11h 00h
12h 00h
curr3x_s
trobe_hi
gh
preview_
off_after
strobe
strobe_p
in
preview_ctrl
Curr3 control2
curr41_current
Curr41 current
Curr42 current
Curr43 current
Pwm control
pwm code
13h 00h
14h 00h
15h 00h
16h 00h
17h 00h
curr42_current
curr43_current
pwm_dim_speed
pwm_code
curr33_p curr32_p curr31_p curr30_p softdim_
pwm_dim_mode
pattern_delay
pattern_
color
Pattern control
18h 00h
attern attern attern attern pattern
pattern_data[7:0]
pattern_data[15:8]
pattern_data[23:16]
pattern_data[31:24]
Pattern daa0
Patteata1
Patterdata2
Ptern data3
GPIO control
19h 00h
1Ah 00h
1Bh 00h
1Ch 00h
1Eh 44h
gpio1_pulls
gpio1_mode
gpio2_pulls
gpio2_mode
gpio1_lo
w_curr
gpio2_lo
w_curr
GPIO driving cap 20h 00h
www.austriamicrosystems.com/AS3676
1v1-4
82 - 91
AS3676
Datasheet - Register Map
Table 121. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
step_up
_frequ
step_up_vtuning
step_up_fb
DCDC control1
DCDC control2
21h 00h
step_up
_fb_auto
step_up step_up
step_up
_res
skip_fast
22h 04h
23h 00h
_lowcur
_prot
cp_start
cp_auto
_on
cp_mode_switchin
g
_deboun
ce
cp_mode
cp_clk
CP control
rgb3_on rgb2_on rgb1_on curr33_o curr32_o curr31_o curr30
_cp _cp _cp n_cp n_cp n_cp _cp
CP mode Switch1 24h 00h
CP mode Switch2 25h 00h
curr6_on
_cp
curr43_o curr42_o curr41_o curr2_on cur_on
n_cp
n_cp
n_cp
cp
_cp
start_co
nversion
adc_select
D9:D3
ADC_control
26h 03h
result_n
ot_ready
ADC_MSB result 27h
NA
NA
D2:D0
ADC_LSB result 28h
Reset and
shutdwn
_enab
rst_ov_t
emp
ov_temp
_on
ov_temp
29h 01h
2Ah NA
2Bh NA
Overtemp control
curr6_lo rgb3_low rgb2_low rgb1_low curr3_l curr32_l curr31_l curr30_l
w_v
Curr low voltage
status1
_v
_v
_v
ow_v
ow_v
ow_v
ow_v
currl curr42_l curr41_l curr2_lo curr1_lo
Curr low voltage
status2
ow
ow_v
ow_v
w_v
w_v
pttern_
slow
paen_
delay2
gpio current
curr6 current
2Ch 00h
2Fh 00h
curr6_current
adder_current1
(can be enabled for CURR30, CURR1, RGB1, CURR41)
Adder Current 1 30h 00h
Adder Current 2 31h 00h
Adder Current 3 32h 00h
adder_current2
(can be enabled for CURR31, CURR2, RGB2, CURR42)
adder_current3
(can be enabled for CURR32, CURR6, RGB3, CURR43)
curr43_a curr42_a curr41_a rgb3_ad rgb2_ad rgb1_ad
dder dder dder der der der
Adder Enable 1
Adder Enable 2
33h 00h
34h 00h
curr33_a curr32_a curr31_a curr30_a curr6_ad curr2_ad curr1_ad
dder
dder
dder
dder
der
der
der
sub_en4 sub_en3 sub_en2 sub_en1
Subtract Enable 35h 00h
ASIC ID1
3EAEh
Fh 5Xh
40h 00h
41h 00h
42h 00h
43h 00h
1
0
0
1
1
0
0
1
1
1
1
0
ASIC ID2
revision
curr30_current
curr31_current
curr32_current
curr33_current
Curr30 currnt
Curr3curent
urr32 current
Curr33 current
aud_buf
_on
audio_speed_down
audio_color
Audio Control
Audio input
46h 00h
47h 00h
audio_di audio_m
s_start an_start
agc_ctrl
audio_gain
www.austriamicrosystems.com/AS3676
1v1-4
83 - 91
AS3676
Datasheet - Register Map
Table 121. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
curr4x_a rgbx_au curr126_
aud_amplitude
Audio output
GPIO output 2
GPIO signal 2
48h 00h
ud_on d_on aud_on
gpi_curr gpi_curr gpi_curr gpi_rgb3 gpi_rgb2 gpi_rgb1 gpio2_o gpio1_o
43_en 42_en 41_en _en _en _en ut ut
50h 00h
51h 00h
gpi_curr gpi_curr gpi_curr gpi_rgb3 gpi_rgb2 gpi_rgb1
gpio2_ in gpio1_in
43_in
42_in
41_in
_in
adder_current4
(can be enabled for CURR33)
_in
_in
Adder Current 4 52h 00h
curr33_aud_src[1:0 curr32_aud_src[1:0 curr31_aud_src[1:0 curr30_aud_sc[1:0
CURR3x audio
53h 00h
source
]
]
]
]
pattern_
end
Pattern End
54h 00h
55h 00h
56h 00h
Audio Control 2
audio_source
audio_seed_p
curr30_o
n_dls
DLS mode
control1
rgb3_on rgb2_orgb1n curr33_o curr32_curr31_o
_dls _dls _dln_dls n_dls n_dls
curr1_on
_dls
DLS mode
control2
curr6_on
_dls
curr43_o curr42_o curr41_o curr2_on
n_dls n_s n_dls _dls
57h 00h
amb_gain
amb_on
ALS control
ALS filter
90h 00h
91h 00h
92h 00h
93h 00h
amb_filter_down
amb_filter_up
b_offset
amb_result
curr2_amb_group curr1_amb_group
rgb3_amb_group rgb2_amb_group rgb1_amb_group
ALS offset
ALS result
ALS curr12 group 94h 00h
ALS rgb group 95h 00h
cuamb_group
curr33_amb_group _amb_group curr31_amb_group curr30_amb_group
ALS curr3x group 96h 00h
ALS curr4x group 97h 00h
curr43_amb_group curr42_amb_group curr41_amb_group
group1_y0
group1_y3
group1_x1
group1_k1
group1_x2
group1_k2
group2_y0
group2_y3
group2_x1
group2_k1
group2_x2
group2_k2
group3_y0
group3_y3
group3_x1
ALS group 1 Y0
ALS group 1 Y3
98h 00h
99h 00h
ALS group 1 X1 9Ah 00h
ALS group 1 K1 9Bh 00h
ALS group 1 X2 9Ch 00
ALS group 1 K2 9Dh 0h
ALS group 2 Y0 9Eh 00h
ALS group 2 Y3 9Fh 00h
ALS group X1 A0h 00h
ALS grp 2 K1 A1h 00h
LS grup 2 X2 A2h 00h
ALgroup 2 K2 A3h 00h
ALS group 3 Y0 A4h 00h
ALS group 3 Y3 A5h 00h
ALS group 3 X1 A6h 00h
www.austriamicrosystems.com/AS3676
1v1-4
84 - 91
AS3676
Datasheet - Register Map
Table 121. Registermap
Register
Content
b4 b3
Definition
Name
b7
b6
b5
b2
b1
b0
group3_k1
group3_x2
group3_k2
ALS group 3 K1 A7h 00h
ALS group 3 X2 A8h 00h
ALS group 3 K2 A9h 00h
Note: If writing to register, write 0 to unused bits
Write to read only bits will be ignored
yellow color = read only
www.austriamicrosystems.com/AS3676
1v1-4
85 - 91
AS3676
Datasheet - External Components
10 External Components
Table 122. External Components List
Value
Package
(min.)1
tol.
(min.)
Rating
(max)
Part Number
Min
Max
Notes
Typ
Ceramic, X5R (V2_5 output)
(e.g. Taiyo Yuden
C1
1µF
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
6.3V
6.3V
6.3V
6.3V
.3V
6.3V
25V
0402
0402
002
0402
0403
0402
0402
0402
JMK105BJ105KV-F)
Ceramic, X5R (VBAT) (e.g.
Taiyo Yuden JMK105BJ105KV-
F)
C2
1µF
1µF
Ceramic, X5R (Charge Pump)
(e.g. Taiyo Yuden
C3
C4
JMK105BJ105KV-F)
Ceramic, X5R (Charge Pup)
(e.g. Taiyo Yuden
1µF
JMK105BJ105KV-F)
Ceramic, X5R (Chge Pump
Output) (e.g. Taiyo Yuden
JMK107BJ225MA)
C5
2.2µF
1µF
Ceramic, X5R (Step Up DCDC
inpt) (e.g. Taiyo Yuden
JM105BJ105KV-F)
C6
Cerami, X5R (Step Up DCDC
eedback, 150pF for over
voltage protection)
only
C7 - optional
C8 - optional
1.5nF
15nF
required
involtage
feedback
mode of
DCDC
Ceamic, X5R (Step Up DCDC
Feedback, 1.5nF for over
voltage protection)
6.3
Ceramic, X5R, X7R (Step Up
DCDC output)
e.g. Murata
GRM188R61E106MA732
10µF
0603
C9
±20
25V
e.g. Taiyo Yuden
TMK316BJ475KD
3.2x1.6x
0.85mm
4.7µF
Ceramic, X5R (VANA/GPI
output) (e.g. Taiyo Yuden
JMK107BJ225MA-T)
C10
2.2µF
±20%
6.3V
0402
R1
R2
100
1
±5%
±1%
Shunt Resistor
0603
0201
Step Up DC/DC Converter
Voltage Feedback
Step Up DC/DC Converter
Voltage Feedback - not
required for over voltage
protection
R3
100k
±1%
±1%
0201
0201
DATA, CLK Pullup resistor –
usually already inside master
R4, R5
1-10k
Recommended Type: Coilcraft
LPS3010-1234 or
Murata LQH3NPN100NJ0,
LQH3NPN150NJ0 or
Panasonic ELLSFG100MA
or TDK VLF3012Aor Taiyo
Yuden NRH3012T100MN
10µH
L1
±20%
3x3x1mm
(15µH3)
www.austriamicrosystems.com/AS3676
1v1-4
86 - 91
AS3676
Datasheet - External Components
Table 122. External Components List
Package
(min.)1
tol.
(min.)
Value
Typ
Rating
(max)
Part Number
Min
Max
Notes
Integrated NMOS and Schottky MicroFET
Fairchild FDFMA3N109
diode
2x2mm
Q1 (+ D1)
D2:D20
Integrated NMOS and Schottky
diode; recommended for
Fairchild FDFME3N311ZT or
OnSemi NTLUF4189NZ
MicroFET
1.6x1.6mm
configurations up to 12 LEDs
LED
As required by application
1. in 1/100 inch (unless otherwise specified)
2. Specified >1µF at 20V; use up to 20V DCDC output voltage
3. Results in improved efficiency compared to 10µH
4. For highest efficiency
As system efficiency is depending on LED configurations, external components and operating conditns, see austria-
microsystems application note ‘Mobile Backlight Selection Guide 1vx.pdf’ for optimizing efficency nd components
size (coil L1, transistor Q1, diode D1).
www.austriamicrosystems.com/AS3676
1v1-4
87 - 91
AS3676
Datasheet - Package Drawings and Markings
11 Package Drawings and Markings
Figure 42. WL-CSP30 3x2.5mm 6x5 Balls Package Drawing
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AS3676
<Code>
Encode datecode 4 characters
Figure 43. WL-CSP30 3x2.5mm 6x5 Balls Detail Dimensions
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www.austriamicrosystems.com/AS3676
1v1-4
88 - 91
AS3676
Datasheet - Package Drawings and Markings
11.1 Tape & Reel Information
Figure 44. Tape & Reel Dimensions
www.austriamicrosystems.com/AS3676
1v1-4
89 - 91
AS3676
Datasheet - Ordering Information
12 Ordering Information
The devices are available as the standard products shown in Table 123.
Table 123. Ordering Information
Model
Description
Delivery Form
Package
AS3676
30pin WL-CSP
(3x2.5mm)
RoHS compliant / Pb-Free
Wafer Level Chip Scale Package,
size 3x2.5mm, 6x5 balls, 0.5mm pitch,
Pb-Free
AS3676-ZWLT
Tape & Reel
Note: All products are RoHS compliant and austriamicrosystems green.
Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect
Technical support is found at http://www.austriamicrosystems.com/Technical-Support
For further information and requests, please contact us mailto:sales@austriamicrosystems.com
or find your local distributor at http://www.austriamicrosystems.com/distributor
Note: AS3676-ZWLT
AS3676-
Z
Temperature Range: -30ºC - 85ºC
WL Package: Wafer Level Chip Scale PackagL-CSP) 3x2.5mm
T
Delivery Form: Tape & Reel
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AS3676
Datasheet - Ordering Information
Copyrights
Copyright © 1997-2012, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe.
Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, trans-
lated, stored, or used without the prior written consent of the copyright owner.
All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing
in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regadin
the information set forth herein or regarding the freedom of the described devices from patent infringement. autria
crosystems AG reserves the right to change specifications and prices at any time and without notice. Therefre, prior
to designing this product into a system, it is necessary to check with austriamicrosystems AG for curent information.
This product is intended for use in normal commercial applications. Applications requiring extendetemperature
range, unusual environmental requirements, or high reliability applications, such as military, medical le-support or life-
sustaining equipment are specifically not recommended without adional processing by auramrosystems AG for
each application. For shipments of less than 100 parts the manufcturiflow might show deviaons from the standard
production flow, such as test flow or test location.
The information furnished here by austriamicrosystems Abelieved to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or ahird party for any dmages, including but not limited to
personal injury, property damage, loss of profits, loss of use, nterruption of busess indirect, special, incidental or
consequential damages, of any kind, in connection with or arising out of the rnishng, performance or use of the tech-
nical data herein. No obligation or liability to recipor any third party l arie or flow out of
austriamicrosystems AG rendering of technicl r other services.
Contact Information
Headquarters
austriamicrosysteAG
Tobelbaderstrsse 30
Schloss Premtaeten
A-8141 ria
Te+43 (0) 3136 500 0
Fax: 43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit:
http://www.austriamicrosystems.com/contact
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